2 * Copyright © 2008-2015 Intel Corporation
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25 #include <linux/prefetch.h>
26 #include <linux/dma-fence-array.h>
30 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
35 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
37 return to_request(fence)->timeline->common->name;
40 static bool i915_fence_signaled(struct dma_fence *fence)
42 return i915_gem_request_completed(to_request(fence));
45 static bool i915_fence_enable_signaling(struct dma_fence *fence)
47 if (i915_fence_signaled(fence))
50 intel_engine_enable_signaling(to_request(fence));
54 static signed long i915_fence_wait(struct dma_fence *fence,
58 return i915_wait_request(to_request(fence), interruptible, timeout);
61 static void i915_fence_release(struct dma_fence *fence)
63 struct drm_i915_gem_request *req = to_request(fence);
65 kmem_cache_free(req->i915->requests, req);
68 const struct dma_fence_ops i915_fence_ops = {
69 .get_driver_name = i915_fence_get_driver_name,
70 .get_timeline_name = i915_fence_get_timeline_name,
71 .enable_signaling = i915_fence_enable_signaling,
72 .signaled = i915_fence_signaled,
73 .wait = i915_fence_wait,
74 .release = i915_fence_release,
77 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
78 struct drm_file *file)
80 struct drm_i915_private *dev_private;
81 struct drm_i915_file_private *file_priv;
83 WARN_ON(!req || !file || req->file_priv);
91 dev_private = req->i915;
92 file_priv = file->driver_priv;
94 spin_lock(&file_priv->mm.lock);
95 req->file_priv = file_priv;
96 list_add_tail(&req->client_list, &file_priv->mm.request_list);
97 spin_unlock(&file_priv->mm.lock);
103 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
105 struct drm_i915_file_private *file_priv = request->file_priv;
110 spin_lock(&file_priv->mm.lock);
111 list_del(&request->client_list);
112 request->file_priv = NULL;
113 spin_unlock(&file_priv->mm.lock);
116 void i915_gem_retire_noop(struct i915_gem_active *active,
117 struct drm_i915_gem_request *request)
119 /* Space left intentionally blank */
122 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
124 struct i915_gem_active *active, *next;
126 lockdep_assert_held(&request->i915->drm.struct_mutex);
127 GEM_BUG_ON(!i915_gem_request_completed(request));
129 trace_i915_gem_request_retire(request);
131 spin_lock_irq(&request->engine->timeline->lock);
132 list_del_init(&request->link);
133 spin_unlock_irq(&request->engine->timeline->lock);
135 /* We know the GPU must have read the request to have
136 * sent us the seqno + interrupt, so use the position
137 * of tail of the request to update the last known position
140 * Note this requires that we are always called in request
143 list_del(&request->ring_link);
144 request->ring->last_retired_head = request->postfix;
145 request->i915->gt.active_requests--;
147 /* Walk through the active list, calling retire on each. This allows
148 * objects to track their GPU activity and mark themselves as idle
149 * when their *last* active request is completed (updating state
150 * tracking lists for eviction, active references for GEM, etc).
152 * As the ->retire() may free the node, we decouple it first and
153 * pass along the auxiliary information (to avoid dereferencing
154 * the node after the callback).
156 list_for_each_entry_safe(active, next, &request->active_list, link) {
157 /* In microbenchmarks or focusing upon time inside the kernel,
158 * we may spend an inordinate amount of time simply handling
159 * the retirement of requests and processing their callbacks.
160 * Of which, this loop itself is particularly hot due to the
161 * cache misses when jumping around the list of i915_gem_active.
162 * So we try to keep this loop as streamlined as possible and
163 * also prefetch the next i915_gem_active to try and hide
164 * the likely cache miss.
168 INIT_LIST_HEAD(&active->link);
169 RCU_INIT_POINTER(active->request, NULL);
171 active->retire(active, request);
174 i915_gem_request_remove_from_client(request);
176 if (request->previous_context) {
177 if (i915.enable_execlists)
178 intel_lr_context_unpin(request->previous_context,
182 i915_gem_context_put(request->ctx);
184 dma_fence_signal(&request->fence);
185 i915_gem_request_put(request);
188 void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
190 struct intel_engine_cs *engine = req->engine;
191 struct drm_i915_gem_request *tmp;
193 lockdep_assert_held(&req->i915->drm.struct_mutex);
194 if (list_empty(&req->link))
198 tmp = list_first_entry(&engine->timeline->requests,
201 i915_gem_request_retire(tmp);
202 } while (tmp != req);
205 static int i915_gem_check_wedge(struct drm_i915_private *dev_priv)
207 struct i915_gpu_error *error = &dev_priv->gpu_error;
209 if (i915_terminally_wedged(error))
212 if (i915_reset_in_progress(error)) {
213 /* Non-interruptible callers can't handle -EAGAIN, hence return
214 * -EIO unconditionally for these.
216 if (!dev_priv->mm.interruptible)
225 static int i915_gem_init_global_seqno(struct drm_i915_private *i915, u32 seqno)
227 struct i915_gem_timeline *timeline = &i915->gt.global_timeline;
228 struct intel_engine_cs *engine;
229 enum intel_engine_id id;
232 /* Carefully retire all requests without writing to the rings */
233 ret = i915_gem_wait_for_idle(i915,
234 I915_WAIT_INTERRUPTIBLE |
239 i915_gem_retire_requests(i915);
240 GEM_BUG_ON(i915->gt.active_requests > 1);
242 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
243 if (!i915_seqno_passed(seqno, atomic_read(&timeline->next_seqno))) {
244 while (intel_breadcrumbs_busy(i915))
245 cond_resched(); /* spin until threads are complete */
247 atomic_set(&timeline->next_seqno, seqno);
249 /* Finally reset hw state */
250 for_each_engine(engine, i915, id)
251 intel_engine_init_global_seqno(engine, seqno);
253 list_for_each_entry(timeline, &i915->gt.timelines, link) {
254 for_each_engine(engine, i915, id) {
255 struct intel_timeline *tl = &timeline->engine[id];
257 memset(tl->sync_seqno, 0, sizeof(tl->sync_seqno));
264 int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
266 struct drm_i915_private *dev_priv = to_i915(dev);
268 lockdep_assert_held(&dev_priv->drm.struct_mutex);
273 /* HWS page needs to be set less than what we
274 * will inject to ring
276 return i915_gem_init_global_seqno(dev_priv, seqno - 1);
279 static int reserve_global_seqno(struct drm_i915_private *i915)
281 u32 active_requests = ++i915->gt.active_requests;
282 u32 next_seqno = atomic_read(&i915->gt.global_timeline.next_seqno);
285 /* Reservation is fine until we need to wrap around */
286 if (likely(next_seqno + active_requests > next_seqno))
289 ret = i915_gem_init_global_seqno(i915, 0);
291 i915->gt.active_requests--;
298 static u32 __timeline_get_seqno(struct i915_gem_timeline *tl)
300 /* next_seqno only incremented under a mutex */
301 return ++tl->next_seqno.counter;
304 static u32 timeline_get_seqno(struct i915_gem_timeline *tl)
306 return atomic_inc_return(&tl->next_seqno);
309 void __i915_gem_request_submit(struct drm_i915_gem_request *request)
311 struct intel_engine_cs *engine = request->engine;
312 struct intel_timeline *timeline;
315 /* Transfer from per-context onto the global per-engine timeline */
316 timeline = engine->timeline;
317 GEM_BUG_ON(timeline == request->timeline);
318 assert_spin_locked(&timeline->lock);
320 seqno = timeline_get_seqno(timeline->common);
322 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
324 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno, seqno));
325 request->previous_seqno = timeline->last_submitted_seqno;
326 timeline->last_submitted_seqno = seqno;
328 /* We may be recursing from the signal callback of another i915 fence */
329 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
330 request->global_seqno = seqno;
331 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
332 intel_engine_enable_signaling(request);
333 spin_unlock(&request->lock);
335 GEM_BUG_ON(!request->global_seqno);
336 engine->emit_breadcrumb(request,
337 request->ring->vaddr + request->postfix);
339 spin_lock(&request->timeline->lock);
340 list_move_tail(&request->link, &timeline->requests);
341 spin_unlock(&request->timeline->lock);
343 i915_sw_fence_commit(&request->execute);
346 void i915_gem_request_submit(struct drm_i915_gem_request *request)
348 struct intel_engine_cs *engine = request->engine;
351 /* Will be called from irq-context when using foreign fences. */
352 spin_lock_irqsave(&engine->timeline->lock, flags);
354 __i915_gem_request_submit(request);
356 spin_unlock_irqrestore(&engine->timeline->lock, flags);
359 static int __i915_sw_fence_call
360 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
362 if (state == FENCE_COMPLETE) {
363 struct drm_i915_gem_request *request =
364 container_of(fence, typeof(*request), submit);
366 request->engine->submit_request(request);
372 static int __i915_sw_fence_call
373 execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
379 * i915_gem_request_alloc - allocate a request structure
381 * @engine: engine that we wish to issue the request on.
382 * @ctx: context that the request will be associated with.
383 * This can be NULL if the request is not directly related to
384 * any specific user context, in which case this function will
385 * choose an appropriate context to use.
387 * Returns a pointer to the allocated request if successful,
388 * or an error code if not.
390 struct drm_i915_gem_request *
391 i915_gem_request_alloc(struct intel_engine_cs *engine,
392 struct i915_gem_context *ctx)
394 struct drm_i915_private *dev_priv = engine->i915;
395 struct drm_i915_gem_request *req;
398 lockdep_assert_held(&dev_priv->drm.struct_mutex);
400 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
401 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
404 ret = i915_gem_check_wedge(dev_priv);
408 ret = reserve_global_seqno(dev_priv);
412 /* Move the oldest request to the slab-cache (if not in use!) */
413 req = list_first_entry_or_null(&engine->timeline->requests,
415 if (req && __i915_gem_request_completed(req))
416 i915_gem_request_retire(req);
418 /* Beware: Dragons be flying overhead.
420 * We use RCU to look up requests in flight. The lookups may
421 * race with the request being allocated from the slab freelist.
422 * That is the request we are writing to here, may be in the process
423 * of being read by __i915_gem_active_get_rcu(). As such,
424 * we have to be very careful when overwriting the contents. During
425 * the RCU lookup, we change chase the request->engine pointer,
426 * read the request->global_seqno and increment the reference count.
428 * The reference count is incremented atomically. If it is zero,
429 * the lookup knows the request is unallocated and complete. Otherwise,
430 * it is either still in use, or has been reallocated and reset
431 * with dma_fence_init(). This increment is safe for release as we
432 * check that the request we have a reference to and matches the active
435 * Before we increment the refcount, we chase the request->engine
436 * pointer. We must not call kmem_cache_zalloc() or else we set
437 * that pointer to NULL and cause a crash during the lookup. If
438 * we see the request is completed (based on the value of the
439 * old engine and seqno), the lookup is complete and reports NULL.
440 * If we decide the request is not completed (new engine or seqno),
441 * then we grab a reference and double check that it is still the
442 * active request - which it won't be and restart the lookup.
444 * Do not use kmem_cache_zalloc() here!
446 req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
452 req->timeline = i915_gem_context_lookup_timeline(ctx, engine);
453 GEM_BUG_ON(req->timeline == engine->timeline);
455 spin_lock_init(&req->lock);
456 dma_fence_init(&req->fence,
459 req->timeline->fence_context,
460 __timeline_get_seqno(req->timeline->common));
462 i915_sw_fence_init(&req->submit, submit_notify);
463 i915_sw_fence_init(&req->execute, execute_notify);
464 /* Ensure that the execute fence completes after the submit fence -
465 * as we complete the execute fence from within the submit fence
466 * callback, its completion would otherwise be visible first.
468 i915_sw_fence_await_sw_fence(&req->execute, &req->submit, &req->execq);
470 INIT_LIST_HEAD(&req->active_list);
471 req->i915 = dev_priv;
472 req->engine = engine;
473 req->ctx = i915_gem_context_get(ctx);
475 /* No zalloc, must clear what we need by hand */
476 req->global_seqno = 0;
477 req->previous_context = NULL;
478 req->file_priv = NULL;
482 * Reserve space in the ring buffer for all the commands required to
483 * eventually emit this request. This is to guarantee that the
484 * i915_add_request() call can't fail. Note that the reserve may need
485 * to be redone if the request is not actually submitted straight
486 * away, e.g. because a GPU scheduler has deferred it.
488 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
489 GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
491 if (i915.enable_execlists)
492 ret = intel_logical_ring_alloc_request_extras(req);
494 ret = intel_ring_alloc_request_extras(req);
498 /* Record the position of the start of the request so that
499 * should we detect the updated seqno part-way through the
500 * GPU processing the request, we never over-estimate the
501 * position of the head.
503 req->head = req->ring->tail;
508 i915_gem_context_put(ctx);
509 kmem_cache_free(dev_priv->requests, req);
511 dev_priv->gt.active_requests--;
516 i915_gem_request_await_request(struct drm_i915_gem_request *to,
517 struct drm_i915_gem_request *from)
521 GEM_BUG_ON(to == from);
523 if (to->timeline == from->timeline)
526 if (to->engine == from->engine) {
527 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
530 return ret < 0 ? ret : 0;
533 if (!from->global_seqno) {
534 ret = i915_sw_fence_await_dma_fence(&to->submit,
537 return ret < 0 ? ret : 0;
540 if (from->global_seqno <= to->timeline->sync_seqno[from->engine->id])
543 trace_i915_gem_ring_sync_to(to, from);
544 if (!i915.semaphores) {
545 if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
546 ret = i915_sw_fence_await_dma_fence(&to->submit,
553 ret = to->engine->semaphore.sync_to(to, from);
558 to->timeline->sync_seqno[from->engine->id] = from->global_seqno;
563 i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req,
564 struct dma_fence *fence)
566 struct dma_fence_array *array;
570 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
573 if (dma_fence_is_i915(fence))
574 return i915_gem_request_await_request(req, to_request(fence));
576 if (!dma_fence_is_array(fence)) {
577 ret = i915_sw_fence_await_dma_fence(&req->submit,
578 fence, I915_FENCE_TIMEOUT,
580 return ret < 0 ? ret : 0;
583 /* Note that if the fence-array was created in signal-on-any mode,
584 * we should *not* decompose it into its individual fences. However,
585 * we don't currently store which mode the fence-array is operating
586 * in. Fortunately, the only user of signal-on-any is private to
587 * amdgpu and we should not see any incoming fence-array from
588 * sync-file being in signal-on-any mode.
591 array = to_dma_fence_array(fence);
592 for (i = 0; i < array->num_fences; i++) {
593 struct dma_fence *child = array->fences[i];
595 if (dma_fence_is_i915(child))
596 ret = i915_gem_request_await_request(req,
599 ret = i915_sw_fence_await_dma_fence(&req->submit,
600 child, I915_FENCE_TIMEOUT,
610 * i915_gem_request_await_object - set this request to (async) wait upon a bo
612 * @to: request we are wishing to use
613 * @obj: object which may be in use on another ring.
615 * This code is meant to abstract object synchronization with the GPU.
616 * Conceptually we serialise writes between engines inside the GPU.
617 * We only allow one engine to write into a buffer at any time, but
618 * multiple readers. To ensure each has a coherent view of memory, we must:
620 * - If there is an outstanding write request to the object, the new
621 * request must wait for it to complete (either CPU or in hw, requests
622 * on the same ring will be naturally ordered).
624 * - If we are a write request (pending_write_domain is set), the new
625 * request must wait for outstanding read requests to complete.
627 * Returns 0 if successful, else propagates up the lower layer error.
630 i915_gem_request_await_object(struct drm_i915_gem_request *to,
631 struct drm_i915_gem_object *obj,
634 struct dma_fence *excl;
638 struct dma_fence **shared;
639 unsigned int count, i;
641 ret = reservation_object_get_fences_rcu(obj->resv,
642 &excl, &count, &shared);
646 for (i = 0; i < count; i++) {
647 ret = i915_gem_request_await_dma_fence(to, shared[i]);
651 dma_fence_put(shared[i]);
654 for (; i < count; i++)
655 dma_fence_put(shared[i]);
658 excl = reservation_object_get_excl_rcu(obj->resv);
663 ret = i915_gem_request_await_dma_fence(to, excl);
671 static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
673 struct drm_i915_private *dev_priv = engine->i915;
675 if (dev_priv->gt.awake)
678 intel_runtime_pm_get_noresume(dev_priv);
679 dev_priv->gt.awake = true;
681 intel_enable_gt_powersave(dev_priv);
682 i915_update_gfx_val(dev_priv);
683 if (INTEL_GEN(dev_priv) >= 6)
684 gen6_rps_busy(dev_priv);
686 queue_delayed_work(dev_priv->wq,
687 &dev_priv->gt.retire_work,
688 round_jiffies_up_relative(HZ));
692 * NB: This function is not allowed to fail. Doing so would mean the the
693 * request is not being tracked for completion but the work itself is
694 * going to happen on the hardware. This would be a Bad Thing(tm).
696 void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
698 struct intel_engine_cs *engine = request->engine;
699 struct intel_ring *ring = request->ring;
700 struct intel_timeline *timeline = request->timeline;
701 struct drm_i915_gem_request *prev;
704 lockdep_assert_held(&request->i915->drm.struct_mutex);
705 trace_i915_gem_request_add(request);
708 * To ensure that this call will not fail, space for its emissions
709 * should already have been reserved in the ring buffer. Let the ring
710 * know that it is time to use that space up.
712 request->reserved_space = 0;
715 * Emit any outstanding flushes - execbuf can fail to emit the flush
716 * after having emitted the batchbuffer command. Hence we need to fix
717 * things up similar to emitting the lazy request. The difference here
718 * is that the flush _must_ happen before the next request, no matter
722 err = engine->emit_flush(request, EMIT_FLUSH);
724 /* Not allowed to fail! */
725 WARN(err, "engine->emit_flush() failed: %d!\n", err);
728 /* Record the position of the start of the breadcrumb so that
729 * should we detect the updated seqno part-way through the
730 * GPU processing the request, we never over-estimate the
731 * position of the ring's HEAD.
733 err = intel_ring_begin(request, engine->emit_breadcrumb_sz);
735 request->postfix = ring->tail;
736 ring->tail += engine->emit_breadcrumb_sz * sizeof(u32);
738 /* Seal the request and mark it as pending execution. Note that
739 * we may inspect this state, without holding any locks, during
740 * hangcheck. Hence we apply the barrier to ensure that we do not
741 * see a more recent value in the hws than we are tracking.
744 prev = i915_gem_active_raw(&timeline->last_request,
745 &request->i915->drm.struct_mutex);
747 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
750 spin_lock_irq(&timeline->lock);
751 list_add_tail(&request->link, &timeline->requests);
752 spin_unlock_irq(&timeline->lock);
754 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno,
755 request->fence.seqno));
757 timeline->last_submitted_seqno = request->fence.seqno;
758 i915_gem_active_set(&timeline->last_request, request);
760 list_add_tail(&request->ring_link, &ring->request_list);
761 request->emitted_jiffies = jiffies;
763 i915_gem_mark_busy(engine);
766 i915_sw_fence_commit(&request->submit);
767 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
770 static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
774 spin_lock_irqsave(&q->lock, flags);
775 if (list_empty(&wait->task_list))
776 __add_wait_queue(q, wait);
777 spin_unlock_irqrestore(&q->lock, flags);
780 static unsigned long local_clock_us(unsigned int *cpu)
784 /* Cheaply and approximately convert from nanoseconds to microseconds.
785 * The result and subsequent calculations are also defined in the same
786 * approximate microseconds units. The principal source of timing
787 * error here is from the simple truncation.
789 * Note that local_clock() is only defined wrt to the current CPU;
790 * the comparisons are no longer valid if we switch CPUs. Instead of
791 * blocking preemption for the entire busywait, we can detect the CPU
792 * switch and use that as indicator of system load and a reason to
793 * stop busywaiting, see busywait_stop().
796 t = local_clock() >> 10;
802 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
804 unsigned int this_cpu;
806 if (time_after(local_clock_us(&this_cpu), timeout))
809 return this_cpu != cpu;
812 bool __i915_spin_request(const struct drm_i915_gem_request *req,
813 int state, unsigned long timeout_us)
817 /* When waiting for high frequency requests, e.g. during synchronous
818 * rendering split between the CPU and GPU, the finite amount of time
819 * required to set up the irq and wait upon it limits the response
820 * rate. By busywaiting on the request completion for a short while we
821 * can service the high frequency waits as quick as possible. However,
822 * if it is a slow request, we want to sleep as quickly as possible.
823 * The tradeoff between waiting and sleeping is roughly the time it
824 * takes to sleep on a request, on the order of a microsecond.
827 timeout_us += local_clock_us(&cpu);
829 if (__i915_gem_request_completed(req))
832 if (signal_pending_state(state, current))
835 if (busywait_stop(timeout_us, cpu))
838 cpu_relax_lowlatency();
839 } while (!need_resched());
845 __i915_request_wait_for_execute(struct drm_i915_gem_request *request,
849 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
850 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
851 wait_queue_head_t *q = &request->i915->gpu_error.wait_queue;
855 if (flags & I915_WAIT_LOCKED)
856 add_wait_queue(q, &reset);
859 prepare_to_wait(&request->execute.wait, &wait, state);
861 if (i915_sw_fence_done(&request->execute))
864 if (flags & I915_WAIT_LOCKED &&
865 i915_reset_in_progress(&request->i915->gpu_error)) {
866 __set_current_state(TASK_RUNNING);
867 i915_reset(request->i915);
868 reset_wait_queue(q, &reset);
872 if (signal_pending_state(state, current)) {
873 timeout = -ERESTARTSYS;
877 timeout = io_schedule_timeout(timeout);
879 finish_wait(&request->execute.wait, &wait);
881 if (flags & I915_WAIT_LOCKED)
882 remove_wait_queue(q, &reset);
888 * i915_wait_request - wait until execution of request has finished
889 * @req: the request to wait upon
890 * @flags: how to wait
891 * @timeout: how long to wait in jiffies
893 * i915_wait_request() waits for the request to be completed, for a
894 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
897 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
898 * in via the flags, and vice versa if the struct_mutex is not held, the caller
899 * must not specify that the wait is locked.
901 * Returns the remaining time (in jiffies) if the request completed, which may
902 * be zero or -ETIME if the request is unfinished after the timeout expires.
903 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
904 * pending before the request completes.
906 long i915_wait_request(struct drm_i915_gem_request *req,
910 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
911 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
913 struct intel_wait wait;
916 #if IS_ENABLED(CONFIG_LOCKDEP)
917 GEM_BUG_ON(debug_locks &&
918 !!lockdep_is_held(&req->i915->drm.struct_mutex) !=
919 !!(flags & I915_WAIT_LOCKED));
921 GEM_BUG_ON(timeout < 0);
923 if (i915_gem_request_completed(req))
929 trace_i915_gem_request_wait_begin(req);
931 if (!i915_sw_fence_done(&req->execute)) {
932 timeout = __i915_request_wait_for_execute(req, flags, timeout);
936 GEM_BUG_ON(!i915_sw_fence_done(&req->execute));
938 GEM_BUG_ON(!i915_sw_fence_done(&req->submit));
939 GEM_BUG_ON(!req->global_seqno);
941 /* Optimistic short spin before touching IRQs */
942 if (i915_spin_request(req, state, 5))
945 set_current_state(state);
946 if (flags & I915_WAIT_LOCKED)
947 add_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
949 intel_wait_init(&wait, req->global_seqno);
950 if (intel_engine_add_wait(req->engine, &wait))
951 /* In order to check that we haven't missed the interrupt
952 * as we enabled it, we need to kick ourselves to do a
953 * coherent check on the seqno before we sleep.
958 if (signal_pending_state(state, current)) {
959 timeout = -ERESTARTSYS;
968 timeout = io_schedule_timeout(timeout);
970 if (intel_wait_complete(&wait))
973 set_current_state(state);
976 /* Carefully check if the request is complete, giving time
977 * for the seqno to be visible following the interrupt.
978 * We also have to check in case we are kicked by the GPU
979 * reset in order to drop the struct_mutex.
981 if (__i915_request_irq_complete(req))
984 /* If the GPU is hung, and we hold the lock, reset the GPU
985 * and then check for completion. On a full reset, the engine's
986 * HW seqno will be advanced passed us and we are complete.
987 * If we do a partial reset, we have to wait for the GPU to
988 * resume and update the breadcrumb.
990 * If we don't hold the mutex, we can just wait for the worker
991 * to come along and update the breadcrumb (either directly
992 * itself, or indirectly by recovering the GPU).
994 if (flags & I915_WAIT_LOCKED &&
995 i915_reset_in_progress(&req->i915->gpu_error)) {
996 __set_current_state(TASK_RUNNING);
997 i915_reset(req->i915);
998 reset_wait_queue(&req->i915->gpu_error.wait_queue,
1003 /* Only spin if we know the GPU is processing this request */
1004 if (i915_spin_request(req, state, 2))
1008 intel_engine_remove_wait(req->engine, &wait);
1009 if (flags & I915_WAIT_LOCKED)
1010 remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1011 __set_current_state(TASK_RUNNING);
1014 trace_i915_gem_request_wait_end(req);
1019 static void engine_retire_requests(struct intel_engine_cs *engine)
1021 struct drm_i915_gem_request *request, *next;
1023 list_for_each_entry_safe(request, next,
1024 &engine->timeline->requests, link) {
1025 if (!__i915_gem_request_completed(request))
1028 i915_gem_request_retire(request);
1032 void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
1034 struct intel_engine_cs *engine;
1035 enum intel_engine_id id;
1037 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1039 if (!dev_priv->gt.active_requests)
1042 GEM_BUG_ON(!dev_priv->gt.awake);
1044 for_each_engine(engine, dev_priv, id)
1045 engine_retire_requests(engine);
1047 if (!dev_priv->gt.active_requests)
1048 mod_delayed_work(dev_priv->wq,
1049 &dev_priv->gt.idle_work,
1050 msecs_to_jiffies(100));