drivers/gpu/drm/i915/i915_irq.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #ifndef __I915_IRQ_H__
   7 #define __I915_IRQ_H__
   8
   9 #include <linux/ktime.h>
  10 #include <linux/types.h>
  11
  12 #include "display/intel_display.h"
  13 #include "i915_reg.h"
  14
  15 struct drm_crtc;
  16 struct drm_device;
  17 struct drm_display_mode;
  18 struct drm_i915_private;
  19 struct intel_crtc;
  20 struct intel_crtc;
  21 struct intel_gt;
  22 struct intel_guc;
  23 struct intel_uncore;
  24
  25 void intel_irq_init(struct drm_i915_private *dev_priv);
  26 void intel_irq_fini(struct drm_i915_private *dev_priv);
  27 int intel_irq_install(struct drm_i915_private *dev_priv);
  28 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
  29
  30 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
  31                               enum pipe pipe);
  32 void
  33 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  34                      u32 status_mask);
  35
  36 void
  37 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  38                       u32 status_mask);
  39
  40 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
  41 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
  42
  43 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
  44                                    u32 mask,
  45                                    u32 bits);
  46 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
  47                             u32 interrupt_mask,
  48                             u32 enabled_irq_mask);
  49 static inline void
  50 ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
  51 {
  52         ilk_update_display_irq(dev_priv, bits, bits);
  53 }
  54 static inline void
  55 ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
  56 {
  57         ilk_update_display_irq(dev_priv, bits, 0);
  58 }
  59 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
  60                          enum pipe pipe,
  61                          u32 interrupt_mask,
  62                          u32 enabled_irq_mask);
  63 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
  64                                        enum pipe pipe, u32 bits)
  65 {
  66         bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
  67 }
  68 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
  69                                         enum pipe pipe, u32 bits)
  70 {
  71         bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
  72 }
  73 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
  74                                   u32 interrupt_mask,
  75                                   u32 enabled_irq_mask);
  76 static inline void
  77 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
  78 {
  79         ibx_display_interrupt_update(dev_priv, bits, bits);
  80 }
  81 static inline void
  82 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
  83 {
  84         ibx_display_interrupt_update(dev_priv, bits, 0);
  85 }
  86
  87 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
  88 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
  89 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
  90 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
  91 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
  92 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
  93 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
  94 u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
  95
  96 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
  97 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
  98 bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
  99 void intel_synchronize_irq(struct drm_i915_private *i915);
 100
 101 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 102 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 103                                      u8 pipe_mask);
 104 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
 105                                      u8 pipe_mask);
 106 void gen9_reset_guc_interrupts(struct intel_guc *guc);
 107 void gen9_enable_guc_interrupts(struct intel_guc *guc);
 108 void gen9_disable_guc_interrupts(struct intel_guc *guc);
 109 void gen11_reset_guc_interrupts(struct intel_guc *guc);
 110 void gen11_enable_guc_interrupts(struct intel_guc *guc);
 111 void gen11_disable_guc_interrupts(struct intel_guc *guc);
 112
 113 bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 114                               bool in_vblank_irq, int *vpos, int *hpos,
 115                               ktime_t *stime, ktime_t *etime,
 116                               const struct drm_display_mode *mode);
 117
 118 u32 i915_get_vblank_counter(struct drm_crtc *crtc);
 119 u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
 120
 121 int i8xx_enable_vblank(struct drm_crtc *crtc);
 122 int i915gm_enable_vblank(struct drm_crtc *crtc);
 123 int i965_enable_vblank(struct drm_crtc *crtc);
 124 int ilk_enable_vblank(struct drm_crtc *crtc);
 125 int bdw_enable_vblank(struct drm_crtc *crtc);
 126 void i8xx_disable_vblank(struct drm_crtc *crtc);
 127 void i915gm_disable_vblank(struct drm_crtc *crtc);
 128 void i965_disable_vblank(struct drm_crtc *crtc);
 129 void ilk_disable_vblank(struct drm_crtc *crtc);
 130 void bdw_disable_vblank(struct drm_crtc *crtc);
 131
 132 void gen2_irq_reset(struct intel_uncore *uncore);
 133 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
 134                     i915_reg_t iir, i915_reg_t ier);
 135
 136 void gen2_irq_init(struct intel_uncore *uncore,
 137                    u32 imr_val, u32 ier_val);
 138 void gen3_irq_init(struct intel_uncore *uncore,
 139                    i915_reg_t imr, u32 imr_val,
 140                    i915_reg_t ier, u32 ier_val,
 141                    i915_reg_t iir);
 142
 143 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \
 144 ({ \
 145         unsigned int which_ = which; \
 146         gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
 147                        GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
 148 })
 149
 150 #define GEN3_IRQ_RESET(uncore, type) \
 151         gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
 152
 153 #define GEN2_IRQ_RESET(uncore) \
 154         gen2_irq_reset(uncore)
 155
 156 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
 157 ({ \
 158         unsigned int which_ = which; \
 159         gen3_irq_init((uncore), \
 160                       GEN8_##type##_IMR(which_), imr_val, \
 161                       GEN8_##type##_IER(which_), ier_val, \
 162                       GEN8_##type##_IIR(which_)); \
 163 })
 164
 165 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
 166         gen3_irq_init((uncore), \
 167                       type##IMR, imr_val, \
 168                       type##IER, ier_val, \
 169                       type##IIR)
 170
 171 #define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
 172         gen2_irq_init((uncore), imr_val, ier_val)
 173
 174 #endif /* __I915_IRQ_H__ */