drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include <drm/drm_drv.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_globals.h"
  33 #include "i915_selftest.h"
  34
  35 #define PLATFORM(x) .platform = (x)
  36 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
  37
  38 #define I845_PIPE_OFFSETS \
  39         .pipe_offsets = { \
  40                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  41         }, \
  42         .trans_offsets = { \
  43                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  44         }
  45
  46 #define I9XX_PIPE_OFFSETS \
  47         .pipe_offsets = { \
  48                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  49                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  50         }, \
  51         .trans_offsets = { \
  52                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  53                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  54         }
  55
  56 #define IVB_PIPE_OFFSETS \
  57         .pipe_offsets = { \
  58                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  59                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  60                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  61         }, \
  62         .trans_offsets = { \
  63                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  64                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  65                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  66         }
  67
  68 #define HSW_PIPE_OFFSETS \
  69         .pipe_offsets = { \
  70                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  71                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  72                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  73                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  74         }, \
  75         .trans_offsets = { \
  76                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  77                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  78                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  79                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  80         }
  81
  82 #define CHV_PIPE_OFFSETS \
  83         .pipe_offsets = { \
  84                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  85                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  86                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  87         }, \
  88         .trans_offsets = { \
  89                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  90                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  91                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  92         }
  93
  94 #define I845_CURSOR_OFFSETS \
  95         .cursor_offsets = { \
  96                 [PIPE_A] = CURSOR_A_OFFSET, \
  97         }
  98
  99 #define I9XX_CURSOR_OFFSETS \
 100         .cursor_offsets = { \
 101                 [PIPE_A] = CURSOR_A_OFFSET, \
 102                 [PIPE_B] = CURSOR_B_OFFSET, \
 103         }
 104
 105 #define CHV_CURSOR_OFFSETS \
 106         .cursor_offsets = { \
 107                 [PIPE_A] = CURSOR_A_OFFSET, \
 108                 [PIPE_B] = CURSOR_B_OFFSET, \
 109                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 110         }
 111
 112 #define IVB_CURSOR_OFFSETS \
 113         .cursor_offsets = { \
 114                 [PIPE_A] = CURSOR_A_OFFSET, \
 115                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 116                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 117         }
 118
 119 #define I965_COLORS \
 120         .color = { .gamma_lut_size = 129, \
 121                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 122         }
 123 #define ILK_COLORS \
 124         .color = { .gamma_lut_size = 1024 }
 125 #define IVB_COLORS \
 126         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
 127 #define CHV_COLORS \
 128         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
 129                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 130                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 131         }
 132 #define GLK_COLORS \
 133         .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 134                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 135                                         DRM_COLOR_LUT_EQUAL_CHANNELS, \
 136         }
 137
 138 /* Keep in gen based order, and chronological order within a gen */
 139
 140 #define GEN_DEFAULT_PAGE_SIZES \
 141         .page_sizes = I915_GTT_PAGE_SIZE_4K
 142
 143 #define I830_FEATURES \
 144         GEN(2), \
 145         .is_mobile = 1, \
 146         .num_pipes = 2, \
 147         .display.has_overlay = 1, \
 148         .display.cursor_needs_physical = 1, \
 149         .display.overlay_needs_physical = 1, \
 150         .display.has_gmch = 1, \
 151         .gpu_reset_clobbers_display = true, \
 152         .hws_needs_physical = 1, \
 153         .unfenced_needs_alignment = 1, \
 154         .engine_mask = BIT(RCS0), \
 155         .has_snoop = true, \
 156         .has_coherent_ggtt = false, \
 157         I9XX_PIPE_OFFSETS, \
 158         I9XX_CURSOR_OFFSETS, \
 159         GEN_DEFAULT_PAGE_SIZES
 160
 161 #define I845_FEATURES \
 162         GEN(2), \
 163         .num_pipes = 1, \
 164         .display.has_overlay = 1, \
 165         .display.overlay_needs_physical = 1, \
 166         .display.has_gmch = 1, \
 167         .gpu_reset_clobbers_display = true, \
 168         .hws_needs_physical = 1, \
 169         .unfenced_needs_alignment = 1, \
 170         .engine_mask = BIT(RCS0), \
 171         .has_snoop = true, \
 172         .has_coherent_ggtt = false, \
 173         I845_PIPE_OFFSETS, \
 174         I845_CURSOR_OFFSETS, \
 175         GEN_DEFAULT_PAGE_SIZES
 176
 177 static const struct intel_device_info intel_i830_info = {
 178         I830_FEATURES,
 179         PLATFORM(INTEL_I830),
 180 };
 181
 182 static const struct intel_device_info intel_i845g_info = {
 183         I845_FEATURES,
 184         PLATFORM(INTEL_I845G),
 185 };
 186
 187 static const struct intel_device_info intel_i85x_info = {
 188         I830_FEATURES,
 189         PLATFORM(INTEL_I85X),
 190         .display.has_fbc = 1,
 191 };
 192
 193 static const struct intel_device_info intel_i865g_info = {
 194         I845_FEATURES,
 195         PLATFORM(INTEL_I865G),
 196 };
 197
 198 #define GEN3_FEATURES \
 199         GEN(3), \
 200         .num_pipes = 2, \
 201         .display.has_gmch = 1, \
 202         .gpu_reset_clobbers_display = true, \
 203         .engine_mask = BIT(RCS0), \
 204         .has_snoop = true, \
 205         .has_coherent_ggtt = true, \
 206         I9XX_PIPE_OFFSETS, \
 207         I9XX_CURSOR_OFFSETS, \
 208         GEN_DEFAULT_PAGE_SIZES
 209
 210 static const struct intel_device_info intel_i915g_info = {
 211         GEN3_FEATURES,
 212         PLATFORM(INTEL_I915G),
 213         .has_coherent_ggtt = false,
 214         .display.cursor_needs_physical = 1,
 215         .display.has_overlay = 1,
 216         .display.overlay_needs_physical = 1,
 217         .hws_needs_physical = 1,
 218         .unfenced_needs_alignment = 1,
 219 };
 220
 221 static const struct intel_device_info intel_i915gm_info = {
 222         GEN3_FEATURES,
 223         PLATFORM(INTEL_I915GM),
 224         .is_mobile = 1,
 225         .display.cursor_needs_physical = 1,
 226         .display.has_overlay = 1,
 227         .display.overlay_needs_physical = 1,
 228         .display.supports_tv = 1,
 229         .display.has_fbc = 1,
 230         .hws_needs_physical = 1,
 231         .unfenced_needs_alignment = 1,
 232 };
 233
 234 static const struct intel_device_info intel_i945g_info = {
 235         GEN3_FEATURES,
 236         PLATFORM(INTEL_I945G),
 237         .display.has_hotplug = 1,
 238         .display.cursor_needs_physical = 1,
 239         .display.has_overlay = 1,
 240         .display.overlay_needs_physical = 1,
 241         .hws_needs_physical = 1,
 242         .unfenced_needs_alignment = 1,
 243 };
 244
 245 static const struct intel_device_info intel_i945gm_info = {
 246         GEN3_FEATURES,
 247         PLATFORM(INTEL_I945GM),
 248         .is_mobile = 1,
 249         .display.has_hotplug = 1,
 250         .display.cursor_needs_physical = 1,
 251         .display.has_overlay = 1,
 252         .display.overlay_needs_physical = 1,
 253         .display.supports_tv = 1,
 254         .display.has_fbc = 1,
 255         .hws_needs_physical = 1,
 256         .unfenced_needs_alignment = 1,
 257 };
 258
 259 static const struct intel_device_info intel_g33_info = {
 260         GEN3_FEATURES,
 261         PLATFORM(INTEL_G33),
 262         .display.has_hotplug = 1,
 263         .display.has_overlay = 1,
 264 };
 265
 266 static const struct intel_device_info intel_pineview_g_info = {
 267         GEN3_FEATURES,
 268         PLATFORM(INTEL_PINEVIEW),
 269         .display.has_hotplug = 1,
 270         .display.has_overlay = 1,
 271 };
 272
 273 static const struct intel_device_info intel_pineview_m_info = {
 274         GEN3_FEATURES,
 275         PLATFORM(INTEL_PINEVIEW),
 276         .is_mobile = 1,
 277         .display.has_hotplug = 1,
 278         .display.has_overlay = 1,
 279 };
 280
 281 #define GEN4_FEATURES \
 282         GEN(4), \
 283         .num_pipes = 2, \
 284         .display.has_hotplug = 1, \
 285         .display.has_gmch = 1, \
 286         .gpu_reset_clobbers_display = true, \
 287         .engine_mask = BIT(RCS0), \
 288         .has_snoop = true, \
 289         .has_coherent_ggtt = true, \
 290         I9XX_PIPE_OFFSETS, \
 291         I9XX_CURSOR_OFFSETS, \
 292         I965_COLORS, \
 293         GEN_DEFAULT_PAGE_SIZES
 294
 295 static const struct intel_device_info intel_i965g_info = {
 296         GEN4_FEATURES,
 297         PLATFORM(INTEL_I965G),
 298         .display.has_overlay = 1,
 299         .hws_needs_physical = 1,
 300         .has_snoop = false,
 301 };
 302
 303 static const struct intel_device_info intel_i965gm_info = {
 304         GEN4_FEATURES,
 305         PLATFORM(INTEL_I965GM),
 306         .is_mobile = 1,
 307         .display.has_fbc = 1,
 308         .display.has_overlay = 1,
 309         .display.supports_tv = 1,
 310         .hws_needs_physical = 1,
 311         .has_snoop = false,
 312 };
 313
 314 static const struct intel_device_info intel_g45_info = {
 315         GEN4_FEATURES,
 316         PLATFORM(INTEL_G45),
 317         .engine_mask = BIT(RCS0) | BIT(VCS0),
 318         .gpu_reset_clobbers_display = false,
 319 };
 320
 321 static const struct intel_device_info intel_gm45_info = {
 322         GEN4_FEATURES,
 323         PLATFORM(INTEL_GM45),
 324         .is_mobile = 1,
 325         .display.has_fbc = 1,
 326         .display.supports_tv = 1,
 327         .engine_mask = BIT(RCS0) | BIT(VCS0),
 328         .gpu_reset_clobbers_display = false,
 329 };
 330
 331 #define GEN5_FEATURES \
 332         GEN(5), \
 333         .num_pipes = 2, \
 334         .display.has_hotplug = 1, \
 335         .engine_mask = BIT(RCS0) | BIT(VCS0), \
 336         .has_snoop = true, \
 337         .has_coherent_ggtt = true, \
 338         /* ilk does support rc6, but we do not implement [power] contexts */ \
 339         .has_rc6 = 0, \
 340         I9XX_PIPE_OFFSETS, \
 341         I9XX_CURSOR_OFFSETS, \
 342         ILK_COLORS, \
 343         GEN_DEFAULT_PAGE_SIZES
 344
 345 static const struct intel_device_info intel_ironlake_d_info = {
 346         GEN5_FEATURES,
 347         PLATFORM(INTEL_IRONLAKE),
 348 };
 349
 350 static const struct intel_device_info intel_ironlake_m_info = {
 351         GEN5_FEATURES,
 352         PLATFORM(INTEL_IRONLAKE),
 353         .is_mobile = 1,
 354         .display.has_fbc = 1,
 355 };
 356
 357 #define GEN6_FEATURES \
 358         GEN(6), \
 359         .num_pipes = 2, \
 360         .display.has_hotplug = 1, \
 361         .display.has_fbc = 1, \
 362         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 363         .has_coherent_ggtt = true, \
 364         .has_llc = 1, \
 365         .has_rc6 = 1, \
 366         .has_rc6p = 1, \
 367         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 368         .ppgtt_size = 31, \
 369         I9XX_PIPE_OFFSETS, \
 370         I9XX_CURSOR_OFFSETS, \
 371         ILK_COLORS, \
 372         GEN_DEFAULT_PAGE_SIZES
 373
 374 #define SNB_D_PLATFORM \
 375         GEN6_FEATURES, \
 376         PLATFORM(INTEL_SANDYBRIDGE)
 377
 378 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
 379         SNB_D_PLATFORM,
 380         .gt = 1,
 381 };
 382
 383 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 384         SNB_D_PLATFORM,
 385         .gt = 2,
 386 };
 387
 388 #define SNB_M_PLATFORM \
 389         GEN6_FEATURES, \
 390         PLATFORM(INTEL_SANDYBRIDGE), \
 391         .is_mobile = 1
 392
 393
 394 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
 395         SNB_M_PLATFORM,
 396         .gt = 1,
 397 };
 398
 399 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 400         SNB_M_PLATFORM,
 401         .gt = 2,
 402 };
 403
 404 #define GEN7_FEATURES  \
 405         GEN(7), \
 406         .num_pipes = 3, \
 407         .display.has_hotplug = 1, \
 408         .display.has_fbc = 1, \
 409         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 410         .has_coherent_ggtt = true, \
 411         .has_llc = 1, \
 412         .has_rc6 = 1, \
 413         .has_rc6p = 1, \
 414         .ppgtt_type = INTEL_PPGTT_FULL, \
 415         .ppgtt_size = 31, \
 416         IVB_PIPE_OFFSETS, \
 417         IVB_CURSOR_OFFSETS, \
 418         IVB_COLORS, \
 419         GEN_DEFAULT_PAGE_SIZES
 420
 421 #define IVB_D_PLATFORM \
 422         GEN7_FEATURES, \
 423         PLATFORM(INTEL_IVYBRIDGE), \
 424         .has_l3_dpf = 1
 425
 426 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
 427         IVB_D_PLATFORM,
 428         .gt = 1,
 429 };
 430
 431 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 432         IVB_D_PLATFORM,
 433         .gt = 2,
 434 };
 435
 436 #define IVB_M_PLATFORM \
 437         GEN7_FEATURES, \
 438         PLATFORM(INTEL_IVYBRIDGE), \
 439         .is_mobile = 1, \
 440         .has_l3_dpf = 1
 441
 442 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
 443         IVB_M_PLATFORM,
 444         .gt = 1,
 445 };
 446
 447 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
 448         IVB_M_PLATFORM,
 449         .gt = 2,
 450 };
 451
 452 static const struct intel_device_info intel_ivybridge_q_info = {
 453         GEN7_FEATURES,
 454         PLATFORM(INTEL_IVYBRIDGE),
 455         .gt = 2,
 456         .num_pipes = 0, /* legal, last one wins */
 457         .has_l3_dpf = 1,
 458 };
 459
 460 static const struct intel_device_info intel_valleyview_info = {
 461         PLATFORM(INTEL_VALLEYVIEW),
 462         GEN(7),
 463         .is_lp = 1,
 464         .num_pipes = 2,
 465         .has_runtime_pm = 1,
 466         .has_rc6 = 1,
 467         .display.has_gmch = 1,
 468         .display.has_hotplug = 1,
 469         .ppgtt_type = INTEL_PPGTT_FULL,
 470         .ppgtt_size = 31,
 471         .has_snoop = true,
 472         .has_coherent_ggtt = false,
 473         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 474         .display_mmio_offset = VLV_DISPLAY_BASE,
 475         I9XX_PIPE_OFFSETS,
 476         I9XX_CURSOR_OFFSETS,
 477         I965_COLORS,
 478         GEN_DEFAULT_PAGE_SIZES,
 479 };
 480
 481 #define G75_FEATURES  \
 482         GEN7_FEATURES, \
 483         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 484         .display.has_ddi = 1, \
 485         .has_fpga_dbg = 1, \
 486         .display.has_psr = 1, \
 487         .display.has_dp_mst = 1, \
 488         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 489         HSW_PIPE_OFFSETS, \
 490         .has_runtime_pm = 1
 491
 492 #define HSW_PLATFORM \
 493         G75_FEATURES, \
 494         PLATFORM(INTEL_HASWELL), \
 495         .has_l3_dpf = 1
 496
 497 static const struct intel_device_info intel_haswell_gt1_info = {
 498         HSW_PLATFORM,
 499         .gt = 1,
 500 };
 501
 502 static const struct intel_device_info intel_haswell_gt2_info = {
 503         HSW_PLATFORM,
 504         .gt = 2,
 505 };
 506
 507 static const struct intel_device_info intel_haswell_gt3_info = {
 508         HSW_PLATFORM,
 509         .gt = 3,
 510 };
 511
 512 #define GEN8_FEATURES \
 513         G75_FEATURES, \
 514         GEN(8), \
 515         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 516                       I915_GTT_PAGE_SIZE_2M, \
 517         .has_logical_ring_contexts = 1, \
 518         .ppgtt_type = INTEL_PPGTT_FULL, \
 519         .ppgtt_size = 48, \
 520         .has_64bit_reloc = 1, \
 521         .has_reset_engine = 1
 522
 523 #define BDW_PLATFORM \
 524         GEN8_FEATURES, \
 525         PLATFORM(INTEL_BROADWELL)
 526
 527 static const struct intel_device_info intel_broadwell_gt1_info = {
 528         BDW_PLATFORM,
 529         .gt = 1,
 530 };
 531
 532 static const struct intel_device_info intel_broadwell_gt2_info = {
 533         BDW_PLATFORM,
 534         .gt = 2,
 535 };
 536
 537 static const struct intel_device_info intel_broadwell_rsvd_info = {
 538         BDW_PLATFORM,
 539         .gt = 3,
 540         /* According to the device ID those devices are GT3, they were
 541          * previously treated as not GT3, keep it like that.
 542          */
 543 };
 544
 545 static const struct intel_device_info intel_broadwell_gt3_info = {
 546         BDW_PLATFORM,
 547         .gt = 3,
 548         .engine_mask =
 549                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 550 };
 551
 552 static const struct intel_device_info intel_cherryview_info = {
 553         PLATFORM(INTEL_CHERRYVIEW),
 554         GEN(8),
 555         .num_pipes = 3,
 556         .display.has_hotplug = 1,
 557         .is_lp = 1,
 558         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 559         .has_64bit_reloc = 1,
 560         .has_runtime_pm = 1,
 561         .has_rc6 = 1,
 562         .has_logical_ring_contexts = 1,
 563         .display.has_gmch = 1,
 564         .ppgtt_type = INTEL_PPGTT_FULL,
 565         .ppgtt_size = 32,
 566         .has_reset_engine = 1,
 567         .has_snoop = true,
 568         .has_coherent_ggtt = false,
 569         .display_mmio_offset = VLV_DISPLAY_BASE,
 570         CHV_PIPE_OFFSETS,
 571         CHV_CURSOR_OFFSETS,
 572         CHV_COLORS,
 573         GEN_DEFAULT_PAGE_SIZES,
 574 };
 575
 576 #define GEN9_DEFAULT_PAGE_SIZES \
 577         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 578                       I915_GTT_PAGE_SIZE_64K | \
 579                       I915_GTT_PAGE_SIZE_2M
 580
 581 #define GEN9_FEATURES \
 582         GEN8_FEATURES, \
 583         GEN(9), \
 584         GEN9_DEFAULT_PAGE_SIZES, \
 585         .has_logical_ring_preemption = 1, \
 586         .display.has_csr = 1, \
 587         .has_guc = 1, \
 588         .display.has_ipc = 1, \
 589         .ddb_size = 896
 590
 591 #define SKL_PLATFORM \
 592         GEN9_FEATURES, \
 593         /* Display WA #0477 WaDisableIPC: skl */ \
 594         .display.has_ipc = 0, \
 595         PLATFORM(INTEL_SKYLAKE)
 596
 597 static const struct intel_device_info intel_skylake_gt1_info = {
 598         SKL_PLATFORM,
 599         .gt = 1,
 600 };
 601
 602 static const struct intel_device_info intel_skylake_gt2_info = {
 603         SKL_PLATFORM,
 604         .gt = 2,
 605 };
 606
 607 #define SKL_GT3_PLUS_PLATFORM \
 608         SKL_PLATFORM, \
 609         .engine_mask = \
 610                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 611
 612
 613 static const struct intel_device_info intel_skylake_gt3_info = {
 614         SKL_GT3_PLUS_PLATFORM,
 615         .gt = 3,
 616 };
 617
 618 static const struct intel_device_info intel_skylake_gt4_info = {
 619         SKL_GT3_PLUS_PLATFORM,
 620         .gt = 4,
 621 };
 622
 623 #define GEN9_LP_FEATURES \
 624         GEN(9), \
 625         .is_lp = 1, \
 626         .display.has_hotplug = 1, \
 627         .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 628         .num_pipes = 3, \
 629         .has_64bit_reloc = 1, \
 630         .display.has_ddi = 1, \
 631         .has_fpga_dbg = 1, \
 632         .display.has_fbc = 1, \
 633         .display.has_psr = 1, \
 634         .has_runtime_pm = 1, \
 635         .display.has_csr = 1, \
 636         .has_rc6 = 1, \
 637         .display.has_dp_mst = 1, \
 638         .has_logical_ring_contexts = 1, \
 639         .has_logical_ring_preemption = 1, \
 640         .has_guc = 1, \
 641         .ppgtt_type = INTEL_PPGTT_FULL, \
 642         .ppgtt_size = 48, \
 643         .has_reset_engine = 1, \
 644         .has_snoop = true, \
 645         .has_coherent_ggtt = false, \
 646         .display.has_ipc = 1, \
 647         HSW_PIPE_OFFSETS, \
 648         IVB_CURSOR_OFFSETS, \
 649         IVB_COLORS, \
 650         GEN9_DEFAULT_PAGE_SIZES
 651
 652 static const struct intel_device_info intel_broxton_info = {
 653         GEN9_LP_FEATURES,
 654         PLATFORM(INTEL_BROXTON),
 655         .ddb_size = 512,
 656 };
 657
 658 static const struct intel_device_info intel_geminilake_info = {
 659         GEN9_LP_FEATURES,
 660         PLATFORM(INTEL_GEMINILAKE),
 661         .ddb_size = 1024,
 662         GLK_COLORS,
 663 };
 664
 665 #define KBL_PLATFORM \
 666         GEN9_FEATURES, \
 667         PLATFORM(INTEL_KABYLAKE)
 668
 669 static const struct intel_device_info intel_kabylake_gt1_info = {
 670         KBL_PLATFORM,
 671         .gt = 1,
 672 };
 673
 674 static const struct intel_device_info intel_kabylake_gt2_info = {
 675         KBL_PLATFORM,
 676         .gt = 2,
 677 };
 678
 679 static const struct intel_device_info intel_kabylake_gt3_info = {
 680         KBL_PLATFORM,
 681         .gt = 3,
 682         .engine_mask =
 683                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 684 };
 685
 686 #define CFL_PLATFORM \
 687         GEN9_FEATURES, \
 688         PLATFORM(INTEL_COFFEELAKE)
 689
 690 static const struct intel_device_info intel_coffeelake_gt1_info = {
 691         CFL_PLATFORM,
 692         .gt = 1,
 693 };
 694
 695 static const struct intel_device_info intel_coffeelake_gt2_info = {
 696         CFL_PLATFORM,
 697         .gt = 2,
 698 };
 699
 700 static const struct intel_device_info intel_coffeelake_gt3_info = {
 701         CFL_PLATFORM,
 702         .gt = 3,
 703         .engine_mask =
 704                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 705 };
 706
 707 #define GEN10_FEATURES \
 708         GEN9_FEATURES, \
 709         GEN(10), \
 710         .ddb_size = 1024, \
 711         .has_coherent_ggtt = false, \
 712         GLK_COLORS
 713
 714 static const struct intel_device_info intel_cannonlake_info = {
 715         GEN10_FEATURES,
 716         PLATFORM(INTEL_CANNONLAKE),
 717         .gt = 2,
 718 };
 719
 720 #define GEN11_FEATURES \
 721         GEN10_FEATURES, \
 722         .pipe_offsets = { \
 723                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 724                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 725                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 726                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 727                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 728                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 729         }, \
 730         .trans_offsets = { \
 731                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 732                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 733                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 734                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 735                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 736                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 737         }, \
 738         GEN(11), \
 739         .ddb_size = 2048, \
 740         .has_logical_ring_elsq = 1, \
 741         .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
 742
 743 static const struct intel_device_info intel_icelake_11_info = {
 744         GEN11_FEATURES,
 745         PLATFORM(INTEL_ICELAKE),
 746         .engine_mask =
 747                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 748 };
 749
 750 static const struct intel_device_info intel_elkhartlake_info = {
 751         GEN11_FEATURES,
 752         PLATFORM(INTEL_ELKHARTLAKE),
 753         .is_alpha_support = 1,
 754         .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
 755         .ppgtt_size = 36,
 756 };
 757
 758 #undef GEN
 759 #undef PLATFORM
 760
 761 /*
 762  * Make sure any device matches here are from most specific to most
 763  * general.  For example, since the Quanta match is based on the subsystem
 764  * and subvendor IDs, we need it to come before the more general IVB
 765  * PCI ID matches, otherwise we'll use the wrong info struct above.
 766  */
 767 static const struct pci_device_id pciidlist[] = {
 768         INTEL_I830_IDS(&intel_i830_info),
 769         INTEL_I845G_IDS(&intel_i845g_info),
 770         INTEL_I85X_IDS(&intel_i85x_info),
 771         INTEL_I865G_IDS(&intel_i865g_info),
 772         INTEL_I915G_IDS(&intel_i915g_info),
 773         INTEL_I915GM_IDS(&intel_i915gm_info),
 774         INTEL_I945G_IDS(&intel_i945g_info),
 775         INTEL_I945GM_IDS(&intel_i945gm_info),
 776         INTEL_I965G_IDS(&intel_i965g_info),
 777         INTEL_G33_IDS(&intel_g33_info),
 778         INTEL_I965GM_IDS(&intel_i965gm_info),
 779         INTEL_GM45_IDS(&intel_gm45_info),
 780         INTEL_G45_IDS(&intel_g45_info),
 781         INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
 782         INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
 783         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 784         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 785         INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 786         INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 787         INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 788         INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 789         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 790         INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 791         INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 792         INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 793         INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
 794         INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 795         INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 796         INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
 797         INTEL_VLV_IDS(&intel_valleyview_info),
 798         INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 799         INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 800         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 801         INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
 802         INTEL_CHV_IDS(&intel_cherryview_info),
 803         INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 804         INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 805         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 806         INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
 807         INTEL_BXT_IDS(&intel_broxton_info),
 808         INTEL_GLK_IDS(&intel_geminilake_info),
 809         INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 810         INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 811         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 812         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 813         INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 814         INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 815         INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 816         INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
 817         INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
 818         INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 819         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 820         INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 821         INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 822         INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
 823         INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 824         INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
 825         INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
 826         INTEL_CNL_IDS(&intel_cannonlake_info),
 827         INTEL_ICL_11_IDS(&intel_icelake_11_info),
 828         INTEL_EHL_IDS(&intel_elkhartlake_info),
 829         {0, 0, 0}
 830 };
 831 MODULE_DEVICE_TABLE(pci, pciidlist);
 832
 833 static void i915_pci_remove(struct pci_dev *pdev)
 834 {
 835         struct drm_device *dev;
 836
 837         dev = pci_get_drvdata(pdev);
 838         if (!dev) /* driver load aborted, nothing to cleanup */
 839                 return;
 840
 841         i915_driver_unload(dev);
 842         drm_dev_put(dev);
 843
 844         pci_set_drvdata(pdev, NULL);
 845 }
 846
 847 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 848 {
 849         struct intel_device_info *intel_info =
 850                 (struct intel_device_info *) ent->driver_data;
 851         int err;
 852
 853         if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
 854                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 855                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 856                          "to enable support in this kernel version, or check for kernel updates.\n");
 857                 return -ENODEV;
 858         }
 859
 860         /* Only bind to function 0 of the device. Early generations
 861          * used function 1 as a placeholder for multi-head. This causes
 862          * us confusion instead, especially on the systems where both
 863          * functions have the same PCI-ID!
 864          */
 865         if (PCI_FUNC(pdev->devfn))
 866                 return -ENODEV;
 867
 868         /*
 869          * apple-gmux is needed on dual GPU MacBook Pro
 870          * to probe the panel if we're the inactive GPU.
 871          */
 872         if (vga_switcheroo_client_probe_defer(pdev))
 873                 return -EPROBE_DEFER;
 874
 875         err = i915_driver_load(pdev, ent);
 876         if (err)
 877                 return err;
 878
 879         if (i915_inject_load_failure()) {
 880                 i915_pci_remove(pdev);
 881                 return -ENODEV;
 882         }
 883
 884         err = i915_live_selftests(pdev);
 885         if (err) {
 886                 i915_pci_remove(pdev);
 887                 return err > 0 ? -ENOTTY : err;
 888         }
 889
 890         return 0;
 891 }
 892
 893 static struct pci_driver i915_pci_driver = {
 894         .name = DRIVER_NAME,
 895         .id_table = pciidlist,
 896         .probe = i915_pci_probe,
 897         .remove = i915_pci_remove,
 898         .driver.pm = &i915_pm_ops,
 899 };
 900
 901 static int __init i915_init(void)
 902 {
 903         bool use_kms = true;
 904         int err;
 905
 906         err = i915_globals_init();
 907         if (err)
 908                 return err;
 909
 910         err = i915_mock_selftests();
 911         if (err)
 912                 return err > 0 ? 0 : err;
 913
 914         /*
 915          * Enable KMS by default, unless explicitly overriden by
 916          * either the i915.modeset prarameter or by the
 917          * vga_text_mode_force boot option.
 918          */
 919
 920         if (i915_modparams.modeset == 0)
 921                 use_kms = false;
 922
 923         if (vgacon_text_force() && i915_modparams.modeset == -1)
 924                 use_kms = false;
 925
 926         if (!use_kms) {
 927                 /* Silently fail loading to not upset userspace. */
 928                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 929                 return 0;
 930         }
 931
 932         return pci_register_driver(&i915_pci_driver);
 933 }
 934
 935 static void __exit i915_exit(void)
 936 {
 937         if (!i915_pci_driver.driver.owner)
 938                 return;
 939
 940         pci_unregister_driver(&i915_pci_driver);
 941         i915_globals_exit();
 942 }
 943
 944 module_init(i915_init);
 945 module_exit(i915_exit);
 946
 947 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 948 MODULE_AUTHOR("Intel Corporation");
 949
 950 MODULE_DESCRIPTION(DRIVER_DESC);
 951 MODULE_LICENSE("GPL and additional rights");