2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
29 #include <drm/drm_drv.h>
32 #include "i915_globals.h"
33 #include "i915_selftest.h"
34 #include "intel_fbdev.h"
36 #define PLATFORM(x) .platform = (x)
37 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
39 #define I845_PIPE_OFFSETS \
41 [TRANSCODER_A] = PIPE_A_OFFSET, \
44 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
47 #define I9XX_PIPE_OFFSETS \
49 [TRANSCODER_A] = PIPE_A_OFFSET, \
50 [TRANSCODER_B] = PIPE_B_OFFSET, \
53 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
54 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
57 #define IVB_PIPE_OFFSETS \
59 [TRANSCODER_A] = PIPE_A_OFFSET, \
60 [TRANSCODER_B] = PIPE_B_OFFSET, \
61 [TRANSCODER_C] = PIPE_C_OFFSET, \
64 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
65 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
66 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
69 #define HSW_PIPE_OFFSETS \
71 [TRANSCODER_A] = PIPE_A_OFFSET, \
72 [TRANSCODER_B] = PIPE_B_OFFSET, \
73 [TRANSCODER_C] = PIPE_C_OFFSET, \
74 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
77 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
78 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
79 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
80 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
83 #define CHV_PIPE_OFFSETS \
85 [TRANSCODER_A] = PIPE_A_OFFSET, \
86 [TRANSCODER_B] = PIPE_B_OFFSET, \
87 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
90 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
91 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
92 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
95 #define I845_CURSOR_OFFSETS \
97 [PIPE_A] = CURSOR_A_OFFSET, \
100 #define I9XX_CURSOR_OFFSETS \
101 .cursor_offsets = { \
102 [PIPE_A] = CURSOR_A_OFFSET, \
103 [PIPE_B] = CURSOR_B_OFFSET, \
106 #define CHV_CURSOR_OFFSETS \
107 .cursor_offsets = { \
108 [PIPE_A] = CURSOR_A_OFFSET, \
109 [PIPE_B] = CURSOR_B_OFFSET, \
110 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
113 #define IVB_CURSOR_OFFSETS \
114 .cursor_offsets = { \
115 [PIPE_A] = CURSOR_A_OFFSET, \
116 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
117 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
120 #define I9XX_COLORS \
121 .color = { .gamma_lut_size = 256 }
122 #define I965_COLORS \
123 .color = { .gamma_lut_size = 129, \
124 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
127 .color = { .gamma_lut_size = 1024 }
129 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
131 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
132 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
133 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
136 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
137 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
138 DRM_COLOR_LUT_EQUAL_CHANNELS, \
141 /* Keep in gen based order, and chronological order within a gen */
143 #define GEN_DEFAULT_PAGE_SIZES \
144 .page_sizes = I915_GTT_PAGE_SIZE_4K
146 #define I830_FEATURES \
150 .display.has_overlay = 1, \
151 .display.cursor_needs_physical = 1, \
152 .display.overlay_needs_physical = 1, \
153 .display.has_gmch = 1, \
154 .gpu_reset_clobbers_display = true, \
155 .hws_needs_physical = 1, \
156 .unfenced_needs_alignment = 1, \
157 .engine_mask = BIT(RCS0), \
159 .has_coherent_ggtt = false, \
161 I9XX_CURSOR_OFFSETS, \
163 GEN_DEFAULT_PAGE_SIZES
165 #define I845_FEATURES \
168 .display.has_overlay = 1, \
169 .display.overlay_needs_physical = 1, \
170 .display.has_gmch = 1, \
171 .gpu_reset_clobbers_display = true, \
172 .hws_needs_physical = 1, \
173 .unfenced_needs_alignment = 1, \
174 .engine_mask = BIT(RCS0), \
176 .has_coherent_ggtt = false, \
178 I845_CURSOR_OFFSETS, \
180 GEN_DEFAULT_PAGE_SIZES
182 static const struct intel_device_info intel_i830_info = {
184 PLATFORM(INTEL_I830),
187 static const struct intel_device_info intel_i845g_info = {
189 PLATFORM(INTEL_I845G),
192 static const struct intel_device_info intel_i85x_info = {
194 PLATFORM(INTEL_I85X),
195 .display.has_fbc = 1,
198 static const struct intel_device_info intel_i865g_info = {
200 PLATFORM(INTEL_I865G),
203 #define GEN3_FEATURES \
206 .display.has_gmch = 1, \
207 .gpu_reset_clobbers_display = true, \
208 .engine_mask = BIT(RCS0), \
210 .has_coherent_ggtt = true, \
212 I9XX_CURSOR_OFFSETS, \
214 GEN_DEFAULT_PAGE_SIZES
216 static const struct intel_device_info intel_i915g_info = {
218 PLATFORM(INTEL_I915G),
219 .has_coherent_ggtt = false,
220 .display.cursor_needs_physical = 1,
221 .display.has_overlay = 1,
222 .display.overlay_needs_physical = 1,
223 .hws_needs_physical = 1,
224 .unfenced_needs_alignment = 1,
227 static const struct intel_device_info intel_i915gm_info = {
229 PLATFORM(INTEL_I915GM),
231 .display.cursor_needs_physical = 1,
232 .display.has_overlay = 1,
233 .display.overlay_needs_physical = 1,
234 .display.supports_tv = 1,
235 .display.has_fbc = 1,
236 .hws_needs_physical = 1,
237 .unfenced_needs_alignment = 1,
240 static const struct intel_device_info intel_i945g_info = {
242 PLATFORM(INTEL_I945G),
243 .display.has_hotplug = 1,
244 .display.cursor_needs_physical = 1,
245 .display.has_overlay = 1,
246 .display.overlay_needs_physical = 1,
247 .hws_needs_physical = 1,
248 .unfenced_needs_alignment = 1,
251 static const struct intel_device_info intel_i945gm_info = {
253 PLATFORM(INTEL_I945GM),
255 .display.has_hotplug = 1,
256 .display.cursor_needs_physical = 1,
257 .display.has_overlay = 1,
258 .display.overlay_needs_physical = 1,
259 .display.supports_tv = 1,
260 .display.has_fbc = 1,
261 .hws_needs_physical = 1,
262 .unfenced_needs_alignment = 1,
265 static const struct intel_device_info intel_g33_info = {
268 .display.has_hotplug = 1,
269 .display.has_overlay = 1,
272 static const struct intel_device_info intel_pineview_g_info = {
274 PLATFORM(INTEL_PINEVIEW),
275 .display.has_hotplug = 1,
276 .display.has_overlay = 1,
279 static const struct intel_device_info intel_pineview_m_info = {
281 PLATFORM(INTEL_PINEVIEW),
283 .display.has_hotplug = 1,
284 .display.has_overlay = 1,
287 #define GEN4_FEATURES \
290 .display.has_hotplug = 1, \
291 .display.has_gmch = 1, \
292 .gpu_reset_clobbers_display = true, \
293 .engine_mask = BIT(RCS0), \
295 .has_coherent_ggtt = true, \
297 I9XX_CURSOR_OFFSETS, \
299 GEN_DEFAULT_PAGE_SIZES
301 static const struct intel_device_info intel_i965g_info = {
303 PLATFORM(INTEL_I965G),
304 .display.has_overlay = 1,
305 .hws_needs_physical = 1,
309 static const struct intel_device_info intel_i965gm_info = {
311 PLATFORM(INTEL_I965GM),
313 .display.has_fbc = 1,
314 .display.has_overlay = 1,
315 .display.supports_tv = 1,
316 .hws_needs_physical = 1,
320 static const struct intel_device_info intel_g45_info = {
323 .engine_mask = BIT(RCS0) | BIT(VCS0),
324 .gpu_reset_clobbers_display = false,
327 static const struct intel_device_info intel_gm45_info = {
329 PLATFORM(INTEL_GM45),
331 .display.has_fbc = 1,
332 .display.supports_tv = 1,
333 .engine_mask = BIT(RCS0) | BIT(VCS0),
334 .gpu_reset_clobbers_display = false,
337 #define GEN5_FEATURES \
340 .display.has_hotplug = 1, \
341 .engine_mask = BIT(RCS0) | BIT(VCS0), \
343 .has_coherent_ggtt = true, \
344 /* ilk does support rc6, but we do not implement [power] contexts */ \
347 I9XX_CURSOR_OFFSETS, \
349 GEN_DEFAULT_PAGE_SIZES
351 static const struct intel_device_info intel_ironlake_d_info = {
353 PLATFORM(INTEL_IRONLAKE),
356 static const struct intel_device_info intel_ironlake_m_info = {
358 PLATFORM(INTEL_IRONLAKE),
360 .display.has_fbc = 1,
363 #define GEN6_FEATURES \
366 .display.has_hotplug = 1, \
367 .display.has_fbc = 1, \
368 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
369 .has_coherent_ggtt = true, \
373 .ppgtt_type = INTEL_PPGTT_ALIASING, \
376 I9XX_CURSOR_OFFSETS, \
378 GEN_DEFAULT_PAGE_SIZES
380 #define SNB_D_PLATFORM \
382 PLATFORM(INTEL_SANDYBRIDGE)
384 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
389 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
394 #define SNB_M_PLATFORM \
396 PLATFORM(INTEL_SANDYBRIDGE), \
400 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
405 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
410 #define GEN7_FEATURES \
413 .display.has_hotplug = 1, \
414 .display.has_fbc = 1, \
415 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
416 .has_coherent_ggtt = true, \
420 .ppgtt_type = INTEL_PPGTT_FULL, \
423 IVB_CURSOR_OFFSETS, \
425 GEN_DEFAULT_PAGE_SIZES
427 #define IVB_D_PLATFORM \
429 PLATFORM(INTEL_IVYBRIDGE), \
432 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
437 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
442 #define IVB_M_PLATFORM \
444 PLATFORM(INTEL_IVYBRIDGE), \
448 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
453 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
458 static const struct intel_device_info intel_ivybridge_q_info = {
460 PLATFORM(INTEL_IVYBRIDGE),
462 .num_pipes = 0, /* legal, last one wins */
466 static const struct intel_device_info intel_valleyview_info = {
467 PLATFORM(INTEL_VALLEYVIEW),
473 .display.has_gmch = 1,
474 .display.has_hotplug = 1,
475 .ppgtt_type = INTEL_PPGTT_FULL,
478 .has_coherent_ggtt = false,
479 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
480 .display_mmio_offset = VLV_DISPLAY_BASE,
484 GEN_DEFAULT_PAGE_SIZES,
487 #define G75_FEATURES \
489 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
490 .display.has_ddi = 1, \
492 .display.has_psr = 1, \
493 .display.has_dp_mst = 1, \
494 .has_rc6p = 0 /* RC6p removed-by HSW */, \
498 #define HSW_PLATFORM \
500 PLATFORM(INTEL_HASWELL), \
503 static const struct intel_device_info intel_haswell_gt1_info = {
508 static const struct intel_device_info intel_haswell_gt2_info = {
513 static const struct intel_device_info intel_haswell_gt3_info = {
518 #define GEN8_FEATURES \
521 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
522 I915_GTT_PAGE_SIZE_2M, \
523 .has_logical_ring_contexts = 1, \
524 .ppgtt_type = INTEL_PPGTT_FULL, \
526 .has_64bit_reloc = 1, \
527 .has_reset_engine = 1
529 #define BDW_PLATFORM \
531 PLATFORM(INTEL_BROADWELL)
533 static const struct intel_device_info intel_broadwell_gt1_info = {
538 static const struct intel_device_info intel_broadwell_gt2_info = {
543 static const struct intel_device_info intel_broadwell_rsvd_info = {
546 /* According to the device ID those devices are GT3, they were
547 * previously treated as not GT3, keep it like that.
551 static const struct intel_device_info intel_broadwell_gt3_info = {
555 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
558 static const struct intel_device_info intel_cherryview_info = {
559 PLATFORM(INTEL_CHERRYVIEW),
562 .display.has_hotplug = 1,
564 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
565 .has_64bit_reloc = 1,
568 .has_logical_ring_contexts = 1,
569 .display.has_gmch = 1,
570 .ppgtt_type = INTEL_PPGTT_FULL,
572 .has_reset_engine = 1,
574 .has_coherent_ggtt = false,
575 .display_mmio_offset = VLV_DISPLAY_BASE,
579 GEN_DEFAULT_PAGE_SIZES,
582 #define GEN9_DEFAULT_PAGE_SIZES \
583 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
584 I915_GTT_PAGE_SIZE_64K | \
585 I915_GTT_PAGE_SIZE_2M
587 #define GEN9_FEATURES \
590 GEN9_DEFAULT_PAGE_SIZES, \
591 .has_logical_ring_preemption = 1, \
592 .display.has_csr = 1, \
594 .display.has_ipc = 1, \
597 #define SKL_PLATFORM \
599 /* Display WA #0477 WaDisableIPC: skl */ \
600 .display.has_ipc = 0, \
601 PLATFORM(INTEL_SKYLAKE)
603 static const struct intel_device_info intel_skylake_gt1_info = {
608 static const struct intel_device_info intel_skylake_gt2_info = {
613 #define SKL_GT3_PLUS_PLATFORM \
616 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
619 static const struct intel_device_info intel_skylake_gt3_info = {
620 SKL_GT3_PLUS_PLATFORM,
624 static const struct intel_device_info intel_skylake_gt4_info = {
625 SKL_GT3_PLUS_PLATFORM,
629 #define GEN9_LP_FEATURES \
632 .display.has_hotplug = 1, \
633 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
635 .has_64bit_reloc = 1, \
636 .display.has_ddi = 1, \
638 .display.has_fbc = 1, \
639 .display.has_psr = 1, \
640 .has_runtime_pm = 1, \
641 .display.has_csr = 1, \
643 .display.has_dp_mst = 1, \
644 .has_logical_ring_contexts = 1, \
645 .has_logical_ring_preemption = 1, \
647 .ppgtt_type = INTEL_PPGTT_FULL, \
649 .has_reset_engine = 1, \
651 .has_coherent_ggtt = false, \
652 .display.has_ipc = 1, \
654 IVB_CURSOR_OFFSETS, \
656 GEN9_DEFAULT_PAGE_SIZES
658 static const struct intel_device_info intel_broxton_info = {
660 PLATFORM(INTEL_BROXTON),
664 static const struct intel_device_info intel_geminilake_info = {
666 PLATFORM(INTEL_GEMINILAKE),
671 #define KBL_PLATFORM \
673 PLATFORM(INTEL_KABYLAKE)
675 static const struct intel_device_info intel_kabylake_gt1_info = {
680 static const struct intel_device_info intel_kabylake_gt2_info = {
685 static const struct intel_device_info intel_kabylake_gt3_info = {
689 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
692 #define CFL_PLATFORM \
694 PLATFORM(INTEL_COFFEELAKE)
696 static const struct intel_device_info intel_coffeelake_gt1_info = {
701 static const struct intel_device_info intel_coffeelake_gt2_info = {
706 static const struct intel_device_info intel_coffeelake_gt3_info = {
710 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
713 #define GEN10_FEATURES \
717 .has_coherent_ggtt = false, \
720 static const struct intel_device_info intel_cannonlake_info = {
722 PLATFORM(INTEL_CANNONLAKE),
726 #define GEN11_FEATURES \
729 [TRANSCODER_A] = PIPE_A_OFFSET, \
730 [TRANSCODER_B] = PIPE_B_OFFSET, \
731 [TRANSCODER_C] = PIPE_C_OFFSET, \
732 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
733 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
734 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
737 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
738 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
739 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
740 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
741 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
742 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
746 .has_logical_ring_elsq = 1, \
747 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
749 static const struct intel_device_info intel_icelake_11_info = {
751 PLATFORM(INTEL_ICELAKE),
753 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
756 static const struct intel_device_info intel_elkhartlake_info = {
758 PLATFORM(INTEL_ELKHARTLAKE),
759 .is_alpha_support = 1,
760 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
768 * Make sure any device matches here are from most specific to most
769 * general. For example, since the Quanta match is based on the subsystem
770 * and subvendor IDs, we need it to come before the more general IVB
771 * PCI ID matches, otherwise we'll use the wrong info struct above.
773 static const struct pci_device_id pciidlist[] = {
774 INTEL_I830_IDS(&intel_i830_info),
775 INTEL_I845G_IDS(&intel_i845g_info),
776 INTEL_I85X_IDS(&intel_i85x_info),
777 INTEL_I865G_IDS(&intel_i865g_info),
778 INTEL_I915G_IDS(&intel_i915g_info),
779 INTEL_I915GM_IDS(&intel_i915gm_info),
780 INTEL_I945G_IDS(&intel_i945g_info),
781 INTEL_I945GM_IDS(&intel_i945gm_info),
782 INTEL_I965G_IDS(&intel_i965g_info),
783 INTEL_G33_IDS(&intel_g33_info),
784 INTEL_I965GM_IDS(&intel_i965gm_info),
785 INTEL_GM45_IDS(&intel_gm45_info),
786 INTEL_G45_IDS(&intel_g45_info),
787 INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
788 INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
789 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
790 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
791 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
792 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
793 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
794 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
795 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
796 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
797 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
798 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
799 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
800 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
801 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
802 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
803 INTEL_VLV_IDS(&intel_valleyview_info),
804 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
805 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
806 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
807 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
808 INTEL_CHV_IDS(&intel_cherryview_info),
809 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
810 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
811 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
812 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
813 INTEL_BXT_IDS(&intel_broxton_info),
814 INTEL_GLK_IDS(&intel_geminilake_info),
815 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
816 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
817 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
818 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
819 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
820 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
821 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
822 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
823 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
824 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
825 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
826 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
827 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
828 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
829 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
830 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
831 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
832 INTEL_CNL_IDS(&intel_cannonlake_info),
833 INTEL_ICL_11_IDS(&intel_icelake_11_info),
834 INTEL_EHL_IDS(&intel_elkhartlake_info),
837 MODULE_DEVICE_TABLE(pci, pciidlist);
839 static void i915_pci_remove(struct pci_dev *pdev)
841 struct drm_device *dev;
843 dev = pci_get_drvdata(pdev);
844 if (!dev) /* driver load aborted, nothing to cleanup */
847 i915_driver_unload(dev);
850 pci_set_drvdata(pdev, NULL);
853 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
855 struct intel_device_info *intel_info =
856 (struct intel_device_info *) ent->driver_data;
859 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
860 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
861 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
862 "to enable support in this kernel version, or check for kernel updates.\n");
866 /* Only bind to function 0 of the device. Early generations
867 * used function 1 as a placeholder for multi-head. This causes
868 * us confusion instead, especially on the systems where both
869 * functions have the same PCI-ID!
871 if (PCI_FUNC(pdev->devfn))
875 * apple-gmux is needed on dual GPU MacBook Pro
876 * to probe the panel if we're the inactive GPU.
878 if (vga_switcheroo_client_probe_defer(pdev))
879 return -EPROBE_DEFER;
881 err = i915_driver_load(pdev, ent);
885 if (i915_inject_load_failure()) {
886 i915_pci_remove(pdev);
890 err = i915_live_selftests(pdev);
892 i915_pci_remove(pdev);
893 return err > 0 ? -ENOTTY : err;
899 static struct pci_driver i915_pci_driver = {
901 .id_table = pciidlist,
902 .probe = i915_pci_probe,
903 .remove = i915_pci_remove,
904 .driver.pm = &i915_pm_ops,
907 static int __init i915_init(void)
912 err = i915_globals_init();
916 err = i915_mock_selftests();
918 return err > 0 ? 0 : err;
921 * Enable KMS by default, unless explicitly overriden by
922 * either the i915.modeset prarameter or by the
923 * vga_text_mode_force boot option.
926 if (i915_modparams.modeset == 0)
929 if (vgacon_text_force() && i915_modparams.modeset == -1)
933 /* Silently fail loading to not upset userspace. */
934 DRM_DEBUG_DRIVER("KMS disabled.\n");
938 return pci_register_driver(&i915_pci_driver);
941 static void __exit i915_exit(void)
943 if (!i915_pci_driver.driver.owner)
946 pci_unregister_driver(&i915_pci_driver);
950 module_init(i915_init);
951 module_exit(i915_exit);
953 MODULE_AUTHOR("Tungsten Graphics, Inc.");
954 MODULE_AUTHOR("Intel Corporation");
956 MODULE_DESCRIPTION(DRIVER_DESC);
957 MODULE_LICENSE("GPL and additional rights");