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24 * Robert Bragg <robert@sixbynine.org>
29 * DOC: i915 Perf Overview
31 * Gen graphics supports a large number of performance counters that can help
32 * driver and application developers understand and optimize their use of the
35 * This i915 perf interface enables userspace to configure and open a file
36 * descriptor representing a stream of GPU metrics which can then be read() as
37 * a stream of sample records.
39 * The interface is particularly suited to exposing buffered metrics that are
40 * captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.
42 * Streams representing a single context are accessible to applications with a
43 * corresponding drm file descriptor, such that OpenGL can use the interface
44 * without special privileges. Access to system-wide metrics requires root
45 * privileges by default, unless changed via the dev.i915.perf_event_paranoid
51 * DOC: i915 Perf History and Comparison with Core Perf
53 * The interface was initially inspired by the core Perf infrastructure but
54 * some notable differences are:
56 * i915 perf file descriptors represent a "stream" instead of an "event"; where
57 * a perf event primarily corresponds to a single 64bit value, while a stream
58 * might sample sets of tightly-coupled counters, depending on the
59 * configuration. For example the Gen OA unit isn't designed to support
60 * orthogonal configurations of individual counters; it's configured for a set
61 * of related counters. Samples for an i915 perf stream capturing OA metrics
62 * will include a set of counter values packed in a compact HW specific format.
63 * The OA unit supports a number of different packing formats which can be
64 * selected by the user opening the stream. Perf has support for grouping
65 * events, but each event in the group is configured, validated and
66 * authenticated individually with separate system calls.
68 * i915 perf stream configurations are provided as an array of u64 (key,value)
69 * pairs, instead of a fixed struct with multiple miscellaneous config members,
70 * interleaved with event-type specific members.
72 * i915 perf doesn't support exposing metrics via an mmap'd circular buffer.
73 * The supported metrics are being written to memory by the GPU unsynchronized
74 * with the CPU, using HW specific packing formats for counter sets. Sometimes
75 * the constraints on HW configuration require reports to be filtered before it
76 * would be acceptable to expose them to unprivileged applications - to hide
77 * the metrics of other processes/contexts. For these use cases a read() based
78 * interface is a good fit, and provides an opportunity to filter data as it
79 * gets copied from the GPU mapped buffers to userspace buffers.
82 * Issues hit with first prototype based on Core Perf
83 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85 * The first prototype of this driver was based on the core perf
86 * infrastructure, and while we did make that mostly work, with some changes to
87 * perf, we found we were breaking or working around too many assumptions baked
88 * into perf's currently cpu centric design.
90 * In the end we didn't see a clear benefit to making perf's implementation and
91 * interface more complex by changing design assumptions while we knew we still
92 * wouldn't be able to use any existing perf based userspace tools.
94 * Also considering the Gen specific nature of the Observability hardware and
95 * how userspace will sometimes need to combine i915 perf OA metrics with
96 * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're
97 * expecting the interface to be used by a platform specific userspace such as
98 * OpenGL or tools. This is to say; we aren't inherently missing out on having
99 * a standard vendor/architecture agnostic interface by not using perf.
102 * For posterity, in case we might re-visit trying to adapt core perf to be
103 * better suited to exposing i915 metrics these were the main pain points we
106 * - The perf based OA PMU driver broke some significant design assumptions:
108 * Existing perf pmus are used for profiling work on a cpu and we were
109 * introducing the idea of _IS_DEVICE pmus with different security
110 * implications, the need to fake cpu-related data (such as user/kernel
111 * registers) to fit with perf's current design, and adding _DEVICE records
112 * as a way to forward device-specific status records.
114 * The OA unit writes reports of counters into a circular buffer, without
115 * involvement from the CPU, making our PMU driver the first of a kind.
117 * Given the way we were periodically forward data from the GPU-mapped, OA
118 * buffer to perf's buffer, those bursts of sample writes looked to perf like
119 * we were sampling too fast and so we had to subvert its throttling checks.
121 * Perf supports groups of counters and allows those to be read via
122 * transactions internally but transactions currently seem designed to be
123 * explicitly initiated from the cpu (say in response to a userspace read())
124 * and while we could pull a report out of the OA buffer we can't
125 * trigger a report from the cpu on demand.
127 * Related to being report based; the OA counters are configured in HW as a
128 * set while perf generally expects counter configurations to be orthogonal.
129 * Although counters can be associated with a group leader as they are
130 * opened, there's no clear precedent for being able to provide group-wide
131 * configuration attributes (for example we want to let userspace choose the
132 * OA unit report format used to capture all counters in a set, or specify a
133 * GPU context to filter metrics on). We avoided using perf's grouping
134 * feature and forwarded OA reports to userspace via perf's 'raw' sample
135 * field. This suited our userspace well considering how coupled the counters
136 * are when dealing with normalizing. It would be inconvenient to split
137 * counters up into separate events, only to require userspace to recombine
138 * them. For Mesa it's also convenient to be forwarded raw, periodic reports
139 * for combining with the side-band raw reports it captures using
140 * MI_REPORT_PERF_COUNT commands.
142 * - As a side note on perf's grouping feature; there was also some concern
143 * that using PERF_FORMAT_GROUP as a way to pack together counter values
144 * would quite drastically inflate our sample sizes, which would likely
145 * lower the effective sampling resolutions we could use when the available
146 * memory bandwidth is limited.
148 * With the OA unit's report formats, counters are packed together as 32
149 * or 40bit values, with the largest report size being 256 bytes.
151 * PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a
152 * documented ordering to the values, implying PERF_FORMAT_ID must also be
153 * used to add a 64bit ID before each value; giving 16 bytes per counter.
155 * Related to counter orthogonality; we can't time share the OA unit, while
156 * event scheduling is a central design idea within perf for allowing
157 * userspace to open + enable more events than can be configured in HW at any
158 * one time. The OA unit is not designed to allow re-configuration while in
159 * use. We can't reconfigure the OA unit without losing internal OA unit
160 * state which we can't access explicitly to save and restore. Reconfiguring
161 * the OA unit is also relatively slow, involving ~100 register writes. From
162 * userspace Mesa also depends on a stable OA configuration when emitting
163 * MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be
164 * disabled while there are outstanding MI_RPC commands lest we hang the
167 * The contents of sample records aren't extensible by device drivers (i.e.
168 * the sample_type bits). As an example; Sourab Gupta had been looking to
169 * attach GPU timestamps to our OA samples. We were shoehorning OA reports
170 * into sample records by using the 'raw' field, but it's tricky to pack more
171 * than one thing into this field because events/core.c currently only lets a
172 * pmu give a single raw data pointer plus len which will be copied into the
173 * ring buffer. To include more than the OA report we'd have to copy the
174 * report into an intermediate larger buffer. I'd been considering allowing a
175 * vector of data+len values to be specified for copying the raw data, but
176 * it felt like a kludge to being using the raw field for this purpose.
178 * - It felt like our perf based PMU was making some technical compromises
179 * just for the sake of using perf:
181 * perf_event_open() requires events to either relate to a pid or a specific
182 * cpu core, while our device pmu related to neither. Events opened with a
183 * pid will be automatically enabled/disabled according to the scheduling of
184 * that process - so not appropriate for us. When an event is related to a
185 * cpu id, perf ensures pmu methods will be invoked via an inter process
186 * interrupt on that core. To avoid invasive changes our userspace opened OA
187 * perf events for a specific cpu. This was workable but it meant the
188 * majority of the OA driver ran in atomic context, including all OA report
189 * forwarding, which wasn't really necessary in our case and seems to make
190 * our locking requirements somewhat complex as we handled the interaction
191 * with the rest of the i915 driver.
194 #include <linux/anon_inodes.h>
195 #include <linux/sizes.h>
196 #include <linux/uuid.h>
198 #include "i915_drv.h"
199 #include "i915_oa_hsw.h"
200 #include "i915_oa_bdw.h"
201 #include "i915_oa_chv.h"
202 #include "i915_oa_sklgt2.h"
203 #include "i915_oa_sklgt3.h"
204 #include "i915_oa_sklgt4.h"
205 #include "i915_oa_bxt.h"
206 #include "i915_oa_kblgt2.h"
207 #include "i915_oa_kblgt3.h"
208 #include "i915_oa_glk.h"
209 #include "i915_oa_cflgt2.h"
210 #include "i915_oa_cflgt3.h"
211 #include "i915_oa_cnl.h"
212 #include "i915_oa_icl.h"
213 #include "intel_lrc_reg.h"
215 /* HW requires this to be a power of two, between 128k and 16M, though driver
216 * is currently generally designed assuming the largest 16M size is used such
217 * that the overflow cases are unlikely in normal operation.
219 #define OA_BUFFER_SIZE SZ_16M
221 #define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
224 * DOC: OA Tail Pointer Race
226 * There's a HW race condition between OA unit tail pointer register updates and
227 * writes to memory whereby the tail pointer can sometimes get ahead of what's
228 * been written out to the OA buffer so far (in terms of what's visible to the
231 * Although this can be observed explicitly while copying reports to userspace
232 * by checking for a zeroed report-id field in tail reports, we want to account
233 * for this earlier, as part of the oa_buffer_check to avoid lots of redundant
236 * In effect we define a tail pointer for reading that lags the real tail
237 * pointer by at least %OA_TAIL_MARGIN_NSEC nanoseconds, which gives enough
238 * time for the corresponding reports to become visible to the CPU.
240 * To manage this we actually track two tail pointers:
241 * 1) An 'aging' tail with an associated timestamp that is tracked until we
242 * can trust the corresponding data is visible to the CPU; at which point
243 * it is considered 'aged'.
244 * 2) An 'aged' tail that can be used for read()ing.
246 * The two separate pointers let us decouple read()s from tail pointer aging.
248 * The tail pointers are checked and updated at a limited rate within a hrtimer
249 * callback (the same callback that is used for delivering EPOLLIN events)
251 * Initially the tails are marked invalid with %INVALID_TAIL_PTR which
252 * indicates that an updated tail pointer is needed.
254 * Most of the implementation details for this workaround are in
255 * oa_buffer_check_unlocked() and _append_oa_reports()
257 * Note for posterity: previously the driver used to define an effective tail
258 * pointer that lagged the real pointer by a 'tail margin' measured in bytes
259 * derived from %OA_TAIL_MARGIN_NSEC and the configured sampling frequency.
260 * This was flawed considering that the OA unit may also automatically generate
261 * non-periodic reports (such as on context switch) or the OA unit may be
262 * enabled without any periodic sampling.
264 #define OA_TAIL_MARGIN_NSEC 100000ULL
265 #define INVALID_TAIL_PTR 0xffffffff
267 /* frequency for checking whether the OA unit has written new reports to the
268 * circular OA buffer...
270 #define POLL_FREQUENCY 200
271 #define POLL_PERIOD (NSEC_PER_SEC / POLL_FREQUENCY)
273 /* for sysctl proc_dointvec_minmax of dev.i915.perf_stream_paranoid */
276 static u32 i915_perf_stream_paranoid = true;
278 /* The maximum exponent the hardware accepts is 63 (essentially it selects one
279 * of the 64bit timestamp bits to trigger reports from) but there's currently
280 * no known use case for sampling as infrequently as once per 47 thousand years.
282 * Since the timestamps included in OA reports are only 32bits it seems
283 * reasonable to limit the OA exponent where it's still possible to account for
284 * overflow in OA report timestamps.
286 #define OA_EXPONENT_MAX 31
288 #define INVALID_CTX_ID 0xffffffff
290 /* On Gen8+ automatically triggered OA reports include a 'reason' field... */
291 #define OAREPORT_REASON_MASK 0x3f
292 #define OAREPORT_REASON_SHIFT 19
293 #define OAREPORT_REASON_TIMER (1<<0)
294 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
295 #define OAREPORT_REASON_CLK_RATIO (1<<5)
298 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
300 * The highest sampling frequency we can theoretically program the OA unit
301 * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell.
303 * Initialized just before we register the sysctl parameter.
305 static int oa_sample_rate_hard_limit;
307 /* Theoretically we can program the OA unit to sample every 160ns but don't
308 * allow that by default unless root...
310 * The default threshold of 100000Hz is based on perf's similar
311 * kernel.perf_event_max_sample_rate sysctl parameter.
313 static u32 i915_oa_max_sample_rate = 100000;
315 /* XXX: beware if future OA HW adds new report formats that the current
316 * code assumes all reports have a power-of-two size and ~(size - 1) can
317 * be used as a mask to align the OA tail pointer.
319 static const struct i915_oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = {
320 [I915_OA_FORMAT_A13] = { 0, 64 },
321 [I915_OA_FORMAT_A29] = { 1, 128 },
322 [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
323 /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
324 [I915_OA_FORMAT_B4_C8] = { 4, 64 },
325 [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 },
326 [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 },
327 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
330 static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
331 [I915_OA_FORMAT_A12] = { 0, 64 },
332 [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
333 [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
334 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
337 #define SAMPLE_OA_REPORT (1<<0)
340 * struct perf_open_properties - for validated properties given to open a stream
341 * @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
342 * @single_context: Whether a single or all gpu contexts should be monitored
343 * @ctx_handle: A gem ctx handle for use with @single_context
344 * @metrics_set: An ID for an OA unit metric set advertised via sysfs
345 * @oa_format: An OA unit HW report format
346 * @oa_periodic: Whether to enable periodic OA unit sampling
347 * @oa_period_exponent: The OA unit sampling period is derived from this
349 * As read_properties_unlocked() enumerates and validates the properties given
350 * to open a stream of metrics the configuration is built up in the structure
351 * which starts out zero initialized.
353 struct perf_open_properties {
356 u64 single_context:1;
359 /* OA sampling state */
363 int oa_period_exponent;
366 static void free_oa_config(struct drm_i915_private *dev_priv,
367 struct i915_oa_config *oa_config)
369 if (!PTR_ERR(oa_config->flex_regs))
370 kfree(oa_config->flex_regs);
371 if (!PTR_ERR(oa_config->b_counter_regs))
372 kfree(oa_config->b_counter_regs);
373 if (!PTR_ERR(oa_config->mux_regs))
374 kfree(oa_config->mux_regs);
378 static void put_oa_config(struct drm_i915_private *dev_priv,
379 struct i915_oa_config *oa_config)
381 if (!atomic_dec_and_test(&oa_config->ref_count))
384 free_oa_config(dev_priv, oa_config);
387 static int get_oa_config(struct drm_i915_private *dev_priv,
389 struct i915_oa_config **out_config)
393 if (metrics_set == 1) {
394 *out_config = &dev_priv->perf.oa.test_config;
395 atomic_inc(&dev_priv->perf.oa.test_config.ref_count);
399 ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock);
403 *out_config = idr_find(&dev_priv->perf.metrics_idr, metrics_set);
407 atomic_inc(&(*out_config)->ref_count);
409 mutex_unlock(&dev_priv->perf.metrics_lock);
414 static u32 gen8_oa_hw_tail_read(struct drm_i915_private *dev_priv)
416 return I915_READ(GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
419 static u32 gen7_oa_hw_tail_read(struct drm_i915_private *dev_priv)
421 u32 oastatus1 = I915_READ(GEN7_OASTATUS1);
423 return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
427 * oa_buffer_check_unlocked - check for data and update tail ptr state
428 * @dev_priv: i915 device instance
430 * This is either called via fops (for blocking reads in user ctx) or the poll
431 * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check
432 * if there is data available for userspace to read.
434 * This function is central to providing a workaround for the OA unit tail
435 * pointer having a race with respect to what data is visible to the CPU.
436 * It is responsible for reading tail pointers from the hardware and giving
437 * the pointers time to 'age' before they are made available for reading.
438 * (See description of OA_TAIL_MARGIN_NSEC above for further details.)
440 * Besides returning true when there is data available to read() this function
441 * also has the side effect of updating the oa_buffer.tails[], .aging_timestamp
442 * and .aged_tail_idx state used for reading.
444 * Note: It's safe to read OA config state here unlocked, assuming that this is
445 * only called while the stream is enabled, while the global OA configuration
448 * Returns: %true if the OA buffer contains data, else %false
450 static bool oa_buffer_check_unlocked(struct drm_i915_private *dev_priv)
452 int report_size = dev_priv->perf.oa.oa_buffer.format_size;
454 unsigned int aged_idx;
455 u32 head, hw_tail, aged_tail, aging_tail;
458 /* We have to consider the (unlikely) possibility that read() errors
459 * could result in an OA buffer reset which might reset the head,
460 * tails[] and aged_tail state.
462 spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
464 /* NB: The head we observe here might effectively be a little out of
465 * date (between head and tails[aged_idx].offset if there is currently
466 * a read() in progress.
468 head = dev_priv->perf.oa.oa_buffer.head;
470 aged_idx = dev_priv->perf.oa.oa_buffer.aged_tail_idx;
471 aged_tail = dev_priv->perf.oa.oa_buffer.tails[aged_idx].offset;
472 aging_tail = dev_priv->perf.oa.oa_buffer.tails[!aged_idx].offset;
474 hw_tail = dev_priv->perf.oa.ops.oa_hw_tail_read(dev_priv);
476 /* The tail pointer increases in 64 byte increments,
477 * not in report_size steps...
479 hw_tail &= ~(report_size - 1);
481 now = ktime_get_mono_fast_ns();
483 /* Update the aged tail
485 * Flip the tail pointer available for read()s once the aging tail is
486 * old enough to trust that the corresponding data will be visible to
489 * Do this before updating the aging pointer in case we may be able to
490 * immediately start aging a new pointer too (if new data has become
491 * available) without needing to wait for a later hrtimer callback.
493 if (aging_tail != INVALID_TAIL_PTR &&
494 ((now - dev_priv->perf.oa.oa_buffer.aging_timestamp) >
495 OA_TAIL_MARGIN_NSEC)) {
498 dev_priv->perf.oa.oa_buffer.aged_tail_idx = aged_idx;
500 aged_tail = aging_tail;
502 /* Mark that we need a new pointer to start aging... */
503 dev_priv->perf.oa.oa_buffer.tails[!aged_idx].offset = INVALID_TAIL_PTR;
504 aging_tail = INVALID_TAIL_PTR;
507 /* Update the aging tail
509 * We throttle aging tail updates until we have a new tail that
510 * represents >= one report more data than is already available for
511 * reading. This ensures there will be enough data for a successful
512 * read once this new pointer has aged and ensures we will give the new
513 * pointer time to age.
515 if (aging_tail == INVALID_TAIL_PTR &&
516 (aged_tail == INVALID_TAIL_PTR ||
517 OA_TAKEN(hw_tail, aged_tail) >= report_size)) {
518 struct i915_vma *vma = dev_priv->perf.oa.oa_buffer.vma;
519 u32 gtt_offset = i915_ggtt_offset(vma);
521 /* Be paranoid and do a bounds check on the pointer read back
522 * from hardware, just in case some spurious hardware condition
523 * could put the tail out of bounds...
525 if (hw_tail >= gtt_offset &&
526 hw_tail < (gtt_offset + OA_BUFFER_SIZE)) {
527 dev_priv->perf.oa.oa_buffer.tails[!aged_idx].offset =
528 aging_tail = hw_tail;
529 dev_priv->perf.oa.oa_buffer.aging_timestamp = now;
531 DRM_ERROR("Ignoring spurious out of range OA buffer tail pointer = %u\n",
536 spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
538 return aged_tail == INVALID_TAIL_PTR ?
539 false : OA_TAKEN(aged_tail, head) >= report_size;
543 * append_oa_status - Appends a status record to a userspace read() buffer.
544 * @stream: An i915-perf stream opened for OA metrics
545 * @buf: destination buffer given by userspace
546 * @count: the number of bytes userspace wants to read
547 * @offset: (inout): the current position for writing into @buf
548 * @type: The kind of status to report to userspace
550 * Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`)
551 * into the userspace read() buffer.
553 * The @buf @offset will only be updated on success.
555 * Returns: 0 on success, negative error code on failure.
557 static int append_oa_status(struct i915_perf_stream *stream,
561 enum drm_i915_perf_record_type type)
563 struct drm_i915_perf_record_header header = { type, 0, sizeof(header) };
565 if ((count - *offset) < header.size)
568 if (copy_to_user(buf + *offset, &header, sizeof(header)))
571 (*offset) += header.size;
577 * append_oa_sample - Copies single OA report into userspace read() buffer.
578 * @stream: An i915-perf stream opened for OA metrics
579 * @buf: destination buffer given by userspace
580 * @count: the number of bytes userspace wants to read
581 * @offset: (inout): the current position for writing into @buf
582 * @report: A single OA report to (optionally) include as part of the sample
584 * The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*`
585 * properties when opening a stream, tracked as `stream->sample_flags`. This
586 * function copies the requested components of a single sample to the given
589 * The @buf @offset will only be updated on success.
591 * Returns: 0 on success, negative error code on failure.
593 static int append_oa_sample(struct i915_perf_stream *stream,
599 struct drm_i915_private *dev_priv = stream->dev_priv;
600 int report_size = dev_priv->perf.oa.oa_buffer.format_size;
601 struct drm_i915_perf_record_header header;
602 u32 sample_flags = stream->sample_flags;
604 header.type = DRM_I915_PERF_RECORD_SAMPLE;
606 header.size = stream->sample_size;
608 if ((count - *offset) < header.size)
612 if (copy_to_user(buf, &header, sizeof(header)))
614 buf += sizeof(header);
616 if (sample_flags & SAMPLE_OA_REPORT) {
617 if (copy_to_user(buf, report, report_size))
621 (*offset) += header.size;
627 * Copies all buffered OA reports into userspace read() buffer.
628 * @stream: An i915-perf stream opened for OA metrics
629 * @buf: destination buffer given by userspace
630 * @count: the number of bytes userspace wants to read
631 * @offset: (inout): the current position for writing into @buf
633 * Notably any error condition resulting in a short read (-%ENOSPC or
634 * -%EFAULT) will be returned even though one or more records may
635 * have been successfully copied. In this case it's up to the caller
636 * to decide if the error should be squashed before returning to
639 * Note: reports are consumed from the head, and appended to the
640 * tail, so the tail chases the head?... If you think that's mad
641 * and back-to-front you're not alone, but this follows the
642 * Gen PRM naming convention.
644 * Returns: 0 on success, negative error code on failure.
646 static int gen8_append_oa_reports(struct i915_perf_stream *stream,
651 struct drm_i915_private *dev_priv = stream->dev_priv;
652 int report_size = dev_priv->perf.oa.oa_buffer.format_size;
653 u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.vaddr;
654 u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
655 u32 mask = (OA_BUFFER_SIZE - 1);
656 size_t start_offset = *offset;
658 unsigned int aged_tail_idx;
663 if (WARN_ON(!stream->enabled))
666 spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
668 head = dev_priv->perf.oa.oa_buffer.head;
669 aged_tail_idx = dev_priv->perf.oa.oa_buffer.aged_tail_idx;
670 tail = dev_priv->perf.oa.oa_buffer.tails[aged_tail_idx].offset;
672 spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
675 * An invalid tail pointer here means we're still waiting for the poll
676 * hrtimer callback to give us a pointer
678 if (tail == INVALID_TAIL_PTR)
682 * NB: oa_buffer.head/tail include the gtt_offset which we don't want
683 * while indexing relative to oa_buf_base.
689 * An out of bounds or misaligned head or tail pointer implies a driver
690 * bug since we validate + align the tail pointers we read from the
691 * hardware and we are in full control of the head pointer which should
692 * only be incremented by multiples of the report size (notably also
693 * all a power of two).
695 if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
696 tail > OA_BUFFER_SIZE || tail % report_size,
697 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
703 (taken = OA_TAKEN(tail, head));
704 head = (head + report_size) & mask) {
705 u8 *report = oa_buf_base + head;
706 u32 *report32 = (void *)report;
711 * All the report sizes factor neatly into the buffer
712 * size so we never expect to see a report split
713 * between the beginning and end of the buffer.
715 * Given the initial alignment check a misalignment
716 * here would imply a driver bug that would result
719 if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
720 DRM_ERROR("Spurious OA head ptr: non-integral report offset\n");
725 * The reason field includes flags identifying what
726 * triggered this specific report (mostly timer
727 * triggered or e.g. due to a context switch).
729 * This field is never expected to be zero so we can
730 * check that the report isn't invalid before copying
733 reason = ((report32[0] >> OAREPORT_REASON_SHIFT) &
734 OAREPORT_REASON_MASK);
736 if (__ratelimit(&dev_priv->perf.oa.spurious_report_rs))
737 DRM_NOTE("Skipping spurious, invalid OA report\n");
741 ctx_id = report32[2] & dev_priv->perf.oa.specific_ctx_id_mask;
744 * Squash whatever is in the CTX_ID field if it's marked as
745 * invalid to be sure we avoid false-positive, single-context
748 * Note: that we don't clear the valid_ctx_bit so userspace can
749 * understand that the ID has been squashed by the kernel.
751 if (!(report32[0] & dev_priv->perf.oa.gen8_valid_ctx_bit))
752 ctx_id = report32[2] = INVALID_CTX_ID;
755 * NB: For Gen 8 the OA unit no longer supports clock gating
756 * off for a specific context and the kernel can't securely
757 * stop the counters from updating as system-wide / global
760 * Automatic reports now include a context ID so reports can be
761 * filtered on the cpu but it's not worth trying to
762 * automatically subtract/hide counter progress for other
763 * contexts while filtering since we can't stop userspace
764 * issuing MI_REPORT_PERF_COUNT commands which would still
765 * provide a side-band view of the real values.
767 * To allow userspace (such as Mesa/GL_INTEL_performance_query)
768 * to normalize counters for a single filtered context then it
769 * needs be forwarded bookend context-switch reports so that it
770 * can track switches in between MI_REPORT_PERF_COUNT commands
771 * and can itself subtract/ignore the progress of counters
772 * associated with other contexts. Note that the hardware
773 * automatically triggers reports when switching to a new
774 * context which are tagged with the ID of the newly active
775 * context. To avoid the complexity (and likely fragility) of
776 * reading ahead while parsing reports to try and minimize
777 * forwarding redundant context switch reports (i.e. between
778 * other, unrelated contexts) we simply elect to forward them
781 * We don't rely solely on the reason field to identify context
782 * switches since it's not-uncommon for periodic samples to
783 * identify a switch before any 'context switch' report.
785 if (!dev_priv->perf.oa.exclusive_stream->ctx ||
786 dev_priv->perf.oa.specific_ctx_id == ctx_id ||
787 (dev_priv->perf.oa.oa_buffer.last_ctx_id ==
788 dev_priv->perf.oa.specific_ctx_id) ||
789 reason & OAREPORT_REASON_CTX_SWITCH) {
792 * While filtering for a single context we avoid
793 * leaking the IDs of other contexts.
795 if (dev_priv->perf.oa.exclusive_stream->ctx &&
796 dev_priv->perf.oa.specific_ctx_id != ctx_id) {
797 report32[2] = INVALID_CTX_ID;
800 ret = append_oa_sample(stream, buf, count, offset,
805 dev_priv->perf.oa.oa_buffer.last_ctx_id = ctx_id;
809 * The above reason field sanity check is based on
810 * the assumption that the OA buffer is initially
811 * zeroed and we reset the field after copying so the
812 * check is still meaningful once old reports start
818 if (start_offset != *offset) {
819 spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
822 * We removed the gtt_offset for the copy loop above, indexing
823 * relative to oa_buf_base so put back here...
827 I915_WRITE(GEN8_OAHEADPTR, head & GEN8_OAHEADPTR_MASK);
828 dev_priv->perf.oa.oa_buffer.head = head;
830 spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
837 * gen8_oa_read - copy status records then buffered OA reports
838 * @stream: An i915-perf stream opened for OA metrics
839 * @buf: destination buffer given by userspace
840 * @count: the number of bytes userspace wants to read
841 * @offset: (inout): the current position for writing into @buf
843 * Checks OA unit status registers and if necessary appends corresponding
844 * status records for userspace (such as for a buffer full condition) and then
845 * initiate appending any buffered OA reports.
847 * Updates @offset according to the number of bytes successfully copied into
848 * the userspace buffer.
850 * NB: some data may be successfully copied to the userspace buffer
851 * even if an error is returned, and this is reflected in the
854 * Returns: zero on success or a negative error code
856 static int gen8_oa_read(struct i915_perf_stream *stream,
861 struct drm_i915_private *dev_priv = stream->dev_priv;
865 if (WARN_ON(!dev_priv->perf.oa.oa_buffer.vaddr))
868 oastatus = I915_READ(GEN8_OASTATUS);
871 * We treat OABUFFER_OVERFLOW as a significant error:
873 * Although theoretically we could handle this more gracefully
874 * sometimes, some Gens don't correctly suppress certain
875 * automatically triggered reports in this condition and so we
876 * have to assume that old reports are now being trampled
879 * Considering how we don't currently give userspace control
880 * over the OA buffer size and always configure a large 16MB
881 * buffer, then a buffer overflow does anyway likely indicate
882 * that something has gone quite badly wrong.
884 if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
885 ret = append_oa_status(stream, buf, count, offset,
886 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
890 DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
891 dev_priv->perf.oa.period_exponent);
893 dev_priv->perf.oa.ops.oa_disable(stream);
894 dev_priv->perf.oa.ops.oa_enable(stream);
897 * Note: .oa_enable() is expected to re-init the oabuffer and
898 * reset GEN8_OASTATUS for us
900 oastatus = I915_READ(GEN8_OASTATUS);
903 if (oastatus & GEN8_OASTATUS_REPORT_LOST) {
904 ret = append_oa_status(stream, buf, count, offset,
905 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
908 I915_WRITE(GEN8_OASTATUS,
909 oastatus & ~GEN8_OASTATUS_REPORT_LOST);
912 return gen8_append_oa_reports(stream, buf, count, offset);
916 * Copies all buffered OA reports into userspace read() buffer.
917 * @stream: An i915-perf stream opened for OA metrics
918 * @buf: destination buffer given by userspace
919 * @count: the number of bytes userspace wants to read
920 * @offset: (inout): the current position for writing into @buf
922 * Notably any error condition resulting in a short read (-%ENOSPC or
923 * -%EFAULT) will be returned even though one or more records may
924 * have been successfully copied. In this case it's up to the caller
925 * to decide if the error should be squashed before returning to
928 * Note: reports are consumed from the head, and appended to the
929 * tail, so the tail chases the head?... If you think that's mad
930 * and back-to-front you're not alone, but this follows the
931 * Gen PRM naming convention.
933 * Returns: 0 on success, negative error code on failure.
935 static int gen7_append_oa_reports(struct i915_perf_stream *stream,
940 struct drm_i915_private *dev_priv = stream->dev_priv;
941 int report_size = dev_priv->perf.oa.oa_buffer.format_size;
942 u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.vaddr;
943 u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
944 u32 mask = (OA_BUFFER_SIZE - 1);
945 size_t start_offset = *offset;
947 unsigned int aged_tail_idx;
952 if (WARN_ON(!stream->enabled))
955 spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
957 head = dev_priv->perf.oa.oa_buffer.head;
958 aged_tail_idx = dev_priv->perf.oa.oa_buffer.aged_tail_idx;
959 tail = dev_priv->perf.oa.oa_buffer.tails[aged_tail_idx].offset;
961 spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
963 /* An invalid tail pointer here means we're still waiting for the poll
964 * hrtimer callback to give us a pointer
966 if (tail == INVALID_TAIL_PTR)
969 /* NB: oa_buffer.head/tail include the gtt_offset which we don't want
970 * while indexing relative to oa_buf_base.
975 /* An out of bounds or misaligned head or tail pointer implies a driver
976 * bug since we validate + align the tail pointers we read from the
977 * hardware and we are in full control of the head pointer which should
978 * only be incremented by multiples of the report size (notably also
979 * all a power of two).
981 if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
982 tail > OA_BUFFER_SIZE || tail % report_size,
983 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
989 (taken = OA_TAKEN(tail, head));
990 head = (head + report_size) & mask) {
991 u8 *report = oa_buf_base + head;
992 u32 *report32 = (void *)report;
994 /* All the report sizes factor neatly into the buffer
995 * size so we never expect to see a report split
996 * between the beginning and end of the buffer.
998 * Given the initial alignment check a misalignment
999 * here would imply a driver bug that would result
1002 if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
1003 DRM_ERROR("Spurious OA head ptr: non-integral report offset\n");
1007 /* The report-ID field for periodic samples includes
1008 * some undocumented flags related to what triggered
1009 * the report and is never expected to be zero so we
1010 * can check that the report isn't invalid before
1011 * copying it to userspace...
1013 if (report32[0] == 0) {
1014 if (__ratelimit(&dev_priv->perf.oa.spurious_report_rs))
1015 DRM_NOTE("Skipping spurious, invalid OA report\n");
1019 ret = append_oa_sample(stream, buf, count, offset, report);
1023 /* The above report-id field sanity check is based on
1024 * the assumption that the OA buffer is initially
1025 * zeroed and we reset the field after copying so the
1026 * check is still meaningful once old reports start
1027 * being overwritten.
1032 if (start_offset != *offset) {
1033 spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
1035 /* We removed the gtt_offset for the copy loop above, indexing
1036 * relative to oa_buf_base so put back here...
1040 I915_WRITE(GEN7_OASTATUS2,
1041 ((head & GEN7_OASTATUS2_HEAD_MASK) |
1042 GEN7_OASTATUS2_MEM_SELECT_GGTT));
1043 dev_priv->perf.oa.oa_buffer.head = head;
1045 spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
1052 * gen7_oa_read - copy status records then buffered OA reports
1053 * @stream: An i915-perf stream opened for OA metrics
1054 * @buf: destination buffer given by userspace
1055 * @count: the number of bytes userspace wants to read
1056 * @offset: (inout): the current position for writing into @buf
1058 * Checks Gen 7 specific OA unit status registers and if necessary appends
1059 * corresponding status records for userspace (such as for a buffer full
1060 * condition) and then initiate appending any buffered OA reports.
1062 * Updates @offset according to the number of bytes successfully copied into
1063 * the userspace buffer.
1065 * Returns: zero on success or a negative error code
1067 static int gen7_oa_read(struct i915_perf_stream *stream,
1072 struct drm_i915_private *dev_priv = stream->dev_priv;
1076 if (WARN_ON(!dev_priv->perf.oa.oa_buffer.vaddr))
1079 oastatus1 = I915_READ(GEN7_OASTATUS1);
1081 /* XXX: On Haswell we don't have a safe way to clear oastatus1
1082 * bits while the OA unit is enabled (while the tail pointer
1083 * may be updated asynchronously) so we ignore status bits
1084 * that have already been reported to userspace.
1086 oastatus1 &= ~dev_priv->perf.oa.gen7_latched_oastatus1;
1088 /* We treat OABUFFER_OVERFLOW as a significant error:
1090 * - The status can be interpreted to mean that the buffer is
1091 * currently full (with a higher precedence than OA_TAKEN()
1092 * which will start to report a near-empty buffer after an
1093 * overflow) but it's awkward that we can't clear the status
1094 * on Haswell, so without a reset we won't be able to catch
1097 * - Since it also implies the HW has started overwriting old
1098 * reports it may also affect our sanity checks for invalid
1099 * reports when copying to userspace that assume new reports
1100 * are being written to cleared memory.
1102 * - In the future we may want to introduce a flight recorder
1103 * mode where the driver will automatically maintain a safe
1104 * guard band between head/tail, avoiding this overflow
1105 * condition, but we avoid the added driver complexity for
1108 if (unlikely(oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW)) {
1109 ret = append_oa_status(stream, buf, count, offset,
1110 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
1114 DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
1115 dev_priv->perf.oa.period_exponent);
1117 dev_priv->perf.oa.ops.oa_disable(stream);
1118 dev_priv->perf.oa.ops.oa_enable(stream);
1120 oastatus1 = I915_READ(GEN7_OASTATUS1);
1123 if (unlikely(oastatus1 & GEN7_OASTATUS1_REPORT_LOST)) {
1124 ret = append_oa_status(stream, buf, count, offset,
1125 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
1128 dev_priv->perf.oa.gen7_latched_oastatus1 |=
1129 GEN7_OASTATUS1_REPORT_LOST;
1132 return gen7_append_oa_reports(stream, buf, count, offset);
1136 * i915_oa_wait_unlocked - handles blocking IO until OA data available
1137 * @stream: An i915-perf stream opened for OA metrics
1139 * Called when userspace tries to read() from a blocking stream FD opened
1140 * for OA metrics. It waits until the hrtimer callback finds a non-empty
1141 * OA buffer and wakes us.
1143 * Note: it's acceptable to have this return with some false positives
1144 * since any subsequent read handling will return -EAGAIN if there isn't
1145 * really data ready for userspace yet.
1147 * Returns: zero on success or a negative error code
1149 static int i915_oa_wait_unlocked(struct i915_perf_stream *stream)
1151 struct drm_i915_private *dev_priv = stream->dev_priv;
1153 /* We would wait indefinitely if periodic sampling is not enabled */
1154 if (!dev_priv->perf.oa.periodic)
1157 return wait_event_interruptible(dev_priv->perf.oa.poll_wq,
1158 oa_buffer_check_unlocked(dev_priv));
1162 * i915_oa_poll_wait - call poll_wait() for an OA stream poll()
1163 * @stream: An i915-perf stream opened for OA metrics
1164 * @file: An i915 perf stream file
1165 * @wait: poll() state table
1167 * For handling userspace polling on an i915 perf stream opened for OA metrics,
1168 * this starts a poll_wait with the wait queue that our hrtimer callback wakes
1169 * when it sees data ready to read in the circular OA buffer.
1171 static void i915_oa_poll_wait(struct i915_perf_stream *stream,
1175 struct drm_i915_private *dev_priv = stream->dev_priv;
1177 poll_wait(file, &dev_priv->perf.oa.poll_wq, wait);
1181 * i915_oa_read - just calls through to &i915_oa_ops->read
1182 * @stream: An i915-perf stream opened for OA metrics
1183 * @buf: destination buffer given by userspace
1184 * @count: the number of bytes userspace wants to read
1185 * @offset: (inout): the current position for writing into @buf
1187 * Updates @offset according to the number of bytes successfully copied into
1188 * the userspace buffer.
1190 * Returns: zero on success or a negative error code
1192 static int i915_oa_read(struct i915_perf_stream *stream,
1197 struct drm_i915_private *dev_priv = stream->dev_priv;
1199 return dev_priv->perf.oa.ops.read(stream, buf, count, offset);
1202 static struct intel_context *oa_pin_context(struct drm_i915_private *i915,
1203 struct i915_gem_context *ctx)
1205 struct intel_engine_cs *engine = i915->engine[RCS0];
1206 struct intel_context *ce;
1209 ret = i915_mutex_lock_interruptible(&i915->drm);
1211 return ERR_PTR(ret);
1214 * As the ID is the gtt offset of the context's vma we
1215 * pin the vma to ensure the ID remains fixed.
1217 * NB: implied RCS engine...
1219 ce = intel_context_pin(ctx, engine);
1220 mutex_unlock(&i915->drm.struct_mutex);
1224 i915->perf.oa.pinned_ctx = ce;
1230 * oa_get_render_ctx_id - determine and hold ctx hw id
1231 * @stream: An i915-perf stream opened for OA metrics
1233 * Determine the render context hw id, and ensure it remains fixed for the
1234 * lifetime of the stream. This ensures that we don't have to worry about
1235 * updating the context ID in OACONTROL on the fly.
1237 * Returns: zero on success or a negative error code
1239 static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
1241 struct drm_i915_private *i915 = stream->dev_priv;
1242 struct intel_context *ce;
1244 ce = oa_pin_context(i915, stream->ctx);
1248 switch (INTEL_GEN(i915)) {
1251 * On Haswell we don't do any post processing of the reports
1252 * and don't need to use the mask.
1254 i915->perf.oa.specific_ctx_id = i915_ggtt_offset(ce->state);
1255 i915->perf.oa.specific_ctx_id_mask = 0;
1262 if (USES_GUC_SUBMISSION(i915)) {
1264 * When using GuC, the context descriptor we write in
1265 * i915 is read by GuC and rewritten before it's
1266 * actually written into the hardware. The LRCA is
1267 * what is put into the context id field of the
1268 * context descriptor by GuC. Because it's aligned to
1269 * a page, the lower 12bits are always at 0 and
1270 * dropped by GuC. They won't be part of the context
1271 * ID in the OA reports, so squash those lower bits.
1273 i915->perf.oa.specific_ctx_id =
1274 lower_32_bits(ce->lrc_desc) >> 12;
1277 * GuC uses the top bit to signal proxy submission, so
1280 i915->perf.oa.specific_ctx_id_mask =
1281 (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
1283 i915->perf.oa.specific_ctx_id_mask =
1284 (1U << GEN8_CTX_ID_WIDTH) - 1;
1285 i915->perf.oa.specific_ctx_id =
1286 upper_32_bits(ce->lrc_desc);
1287 i915->perf.oa.specific_ctx_id &=
1288 i915->perf.oa.specific_ctx_id_mask;
1293 i915->perf.oa.specific_ctx_id_mask =
1294 ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
1295 ((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
1296 ((1 << GEN11_ENGINE_CLASS_WIDTH) - 1) << (GEN11_ENGINE_CLASS_SHIFT - 32);
1297 i915->perf.oa.specific_ctx_id = upper_32_bits(ce->lrc_desc);
1298 i915->perf.oa.specific_ctx_id &=
1299 i915->perf.oa.specific_ctx_id_mask;
1304 MISSING_CASE(INTEL_GEN(i915));
1307 DRM_DEBUG_DRIVER("filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
1308 i915->perf.oa.specific_ctx_id,
1309 i915->perf.oa.specific_ctx_id_mask);
1315 * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold
1316 * @stream: An i915-perf stream opened for OA metrics
1318 * In case anything needed doing to ensure the context HW ID would remain valid
1319 * for the lifetime of the stream, then that can be undone here.
1321 static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
1323 struct drm_i915_private *dev_priv = stream->dev_priv;
1324 struct intel_context *ce;
1326 dev_priv->perf.oa.specific_ctx_id = INVALID_CTX_ID;
1327 dev_priv->perf.oa.specific_ctx_id_mask = 0;
1329 ce = fetch_and_zero(&dev_priv->perf.oa.pinned_ctx);
1331 mutex_lock(&dev_priv->drm.struct_mutex);
1332 intel_context_unpin(ce);
1333 mutex_unlock(&dev_priv->drm.struct_mutex);
1338 free_oa_buffer(struct drm_i915_private *i915)
1340 mutex_lock(&i915->drm.struct_mutex);
1342 i915_vma_unpin_and_release(&i915->perf.oa.oa_buffer.vma,
1343 I915_VMA_RELEASE_MAP);
1345 mutex_unlock(&i915->drm.struct_mutex);
1347 i915->perf.oa.oa_buffer.vaddr = NULL;
1350 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
1352 struct drm_i915_private *dev_priv = stream->dev_priv;
1354 BUG_ON(stream != dev_priv->perf.oa.exclusive_stream);
1357 * Unset exclusive_stream first, it will be checked while disabling
1358 * the metric set on gen8+.
1360 mutex_lock(&dev_priv->drm.struct_mutex);
1361 dev_priv->perf.oa.exclusive_stream = NULL;
1362 dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
1363 mutex_unlock(&dev_priv->drm.struct_mutex);
1365 free_oa_buffer(dev_priv);
1367 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1368 intel_runtime_pm_put(dev_priv, stream->wakeref);
1371 oa_put_render_ctx_id(stream);
1373 put_oa_config(dev_priv, stream->oa_config);
1375 if (dev_priv->perf.oa.spurious_report_rs.missed) {
1376 DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n",
1377 dev_priv->perf.oa.spurious_report_rs.missed);
1381 static void gen7_init_oa_buffer(struct drm_i915_private *dev_priv)
1383 u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
1384 unsigned long flags;
1386 spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
1388 /* Pre-DevBDW: OABUFFER must be set with counters off,
1389 * before OASTATUS1, but after OASTATUS2
1391 I915_WRITE(GEN7_OASTATUS2,
1392 gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT); /* head */
1393 dev_priv->perf.oa.oa_buffer.head = gtt_offset;
1395 I915_WRITE(GEN7_OABUFFER, gtt_offset);
1397 I915_WRITE(GEN7_OASTATUS1, gtt_offset | OABUFFER_SIZE_16M); /* tail */
1399 /* Mark that we need updated tail pointers to read from... */
1400 dev_priv->perf.oa.oa_buffer.tails[0].offset = INVALID_TAIL_PTR;
1401 dev_priv->perf.oa.oa_buffer.tails[1].offset = INVALID_TAIL_PTR;
1403 spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
1405 /* On Haswell we have to track which OASTATUS1 flags we've
1406 * already seen since they can't be cleared while periodic
1407 * sampling is enabled.
1409 dev_priv->perf.oa.gen7_latched_oastatus1 = 0;
1411 /* NB: although the OA buffer will initially be allocated
1412 * zeroed via shmfs (and so this memset is redundant when
1413 * first allocating), we may re-init the OA buffer, either
1414 * when re-enabling a stream or in error/reset paths.
1416 * The reason we clear the buffer for each re-init is for the
1417 * sanity check in gen7_append_oa_reports() that looks at the
1418 * report-id field to make sure it's non-zero which relies on
1419 * the assumption that new reports are being written to zeroed
1422 memset(dev_priv->perf.oa.oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1424 /* Maybe make ->pollin per-stream state if we support multiple
1425 * concurrent streams in the future.
1427 dev_priv->perf.oa.pollin = false;
1430 static void gen8_init_oa_buffer(struct drm_i915_private *dev_priv)
1432 u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
1433 unsigned long flags;
1435 spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
1437 I915_WRITE(GEN8_OASTATUS, 0);
1438 I915_WRITE(GEN8_OAHEADPTR, gtt_offset);
1439 dev_priv->perf.oa.oa_buffer.head = gtt_offset;
1441 I915_WRITE(GEN8_OABUFFER_UDW, 0);
1446 * "This MMIO must be set before the OATAILPTR
1447 * register and after the OAHEADPTR register. This is
1448 * to enable proper functionality of the overflow
1451 I915_WRITE(GEN8_OABUFFER, gtt_offset |
1452 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1453 I915_WRITE(GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
1455 /* Mark that we need updated tail pointers to read from... */
1456 dev_priv->perf.oa.oa_buffer.tails[0].offset = INVALID_TAIL_PTR;
1457 dev_priv->perf.oa.oa_buffer.tails[1].offset = INVALID_TAIL_PTR;
1460 * Reset state used to recognise context switches, affecting which
1461 * reports we will forward to userspace while filtering for a single
1464 dev_priv->perf.oa.oa_buffer.last_ctx_id = INVALID_CTX_ID;
1466 spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
1469 * NB: although the OA buffer will initially be allocated
1470 * zeroed via shmfs (and so this memset is redundant when
1471 * first allocating), we may re-init the OA buffer, either
1472 * when re-enabling a stream or in error/reset paths.
1474 * The reason we clear the buffer for each re-init is for the
1475 * sanity check in gen8_append_oa_reports() that looks at the
1476 * reason field to make sure it's non-zero which relies on
1477 * the assumption that new reports are being written to zeroed
1480 memset(dev_priv->perf.oa.oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1483 * Maybe make ->pollin per-stream state if we support multiple
1484 * concurrent streams in the future.
1486 dev_priv->perf.oa.pollin = false;
1489 static int alloc_oa_buffer(struct drm_i915_private *dev_priv)
1491 struct drm_i915_gem_object *bo;
1492 struct i915_vma *vma;
1495 if (WARN_ON(dev_priv->perf.oa.oa_buffer.vma))
1498 ret = i915_mutex_lock_interruptible(&dev_priv->drm);
1502 BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
1503 BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
1505 bo = i915_gem_object_create(dev_priv, OA_BUFFER_SIZE);
1507 DRM_ERROR("Failed to allocate OA buffer\n");
1512 i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
1514 /* PreHSW required 512K alignment, HSW requires 16M */
1515 vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0);
1520 dev_priv->perf.oa.oa_buffer.vma = vma;
1522 dev_priv->perf.oa.oa_buffer.vaddr =
1523 i915_gem_object_pin_map(bo, I915_MAP_WB);
1524 if (IS_ERR(dev_priv->perf.oa.oa_buffer.vaddr)) {
1525 ret = PTR_ERR(dev_priv->perf.oa.oa_buffer.vaddr);
1529 DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr = %p\n",
1530 i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma),
1531 dev_priv->perf.oa.oa_buffer.vaddr);
1536 __i915_vma_unpin(vma);
1539 i915_gem_object_put(bo);
1541 dev_priv->perf.oa.oa_buffer.vaddr = NULL;
1542 dev_priv->perf.oa.oa_buffer.vma = NULL;
1545 mutex_unlock(&dev_priv->drm.struct_mutex);
1549 static void config_oa_regs(struct drm_i915_private *dev_priv,
1550 const struct i915_oa_reg *regs,
1555 for (i = 0; i < n_regs; i++) {
1556 const struct i915_oa_reg *reg = regs + i;
1558 I915_WRITE(reg->addr, reg->value);
1562 static int hsw_enable_metric_set(struct i915_perf_stream *stream)
1564 struct drm_i915_private *dev_priv = stream->dev_priv;
1565 const struct i915_oa_config *oa_config = stream->oa_config;
1569 * OA unit is using “crclk” for its functionality. When trunk
1570 * level clock gating takes place, OA clock would be gated,
1571 * unable to count the events from non-render clock domain.
1572 * Render clock gating must be disabled when OA is enabled to
1573 * count the events from non-render domain. Unit level clock
1574 * gating for RCS should also be disabled.
1576 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1577 ~GEN7_DOP_CLOCK_GATE_ENABLE));
1578 I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) |
1579 GEN6_CSUNIT_CLOCK_GATE_DISABLE));
1581 config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
1583 /* It apparently takes a fairly long time for a new MUX
1584 * configuration to be be applied after these register writes.
1585 * This delay duration was derived empirically based on the
1586 * render_basic config but hopefully it covers the maximum
1587 * configuration latency.
1589 * As a fallback, the checks in _append_oa_reports() to skip
1590 * invalid OA reports do also seem to work to discard reports
1591 * generated before this config has completed - albeit not
1594 * Unfortunately this is essentially a magic number, since we
1595 * don't currently know of a reliable mechanism for predicting
1596 * how long the MUX config will take to apply and besides
1597 * seeing invalid reports we don't know of a reliable way to
1598 * explicitly check that the MUX config has landed.
1600 * It's even possible we've miss characterized the underlying
1601 * problem - it just seems like the simplest explanation why
1602 * a delay at this location would mitigate any invalid reports.
1604 usleep_range(15000, 20000);
1606 config_oa_regs(dev_priv, oa_config->b_counter_regs,
1607 oa_config->b_counter_regs_len);
1612 static void hsw_disable_metric_set(struct drm_i915_private *dev_priv)
1614 I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) &
1615 ~GEN6_CSUNIT_CLOCK_GATE_DISABLE));
1616 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) |
1617 GEN7_DOP_CLOCK_GATE_ENABLE));
1619 I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) &
1624 * NB: It must always remain pointer safe to run this even if the OA unit
1625 * has been disabled.
1627 * It's fine to put out-of-date values into these per-context registers
1628 * in the case that the OA unit has been disabled.
1631 gen8_update_reg_state_unlocked(struct intel_context *ce,
1633 const struct i915_oa_config *oa_config)
1635 struct drm_i915_private *i915 = ce->gem_context->i915;
1636 u32 ctx_oactxctrl = i915->perf.oa.ctx_oactxctrl_offset;
1637 u32 ctx_flexeu0 = i915->perf.oa.ctx_flexeu0_offset;
1638 /* The MMIO offsets for Flex EU registers aren't contiguous */
1639 i915_reg_t flex_regs[] = {
1650 CTX_REG(reg_state, ctx_oactxctrl, GEN8_OACTXCONTROL,
1651 (i915->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
1652 (i915->perf.oa.periodic ? GEN8_OA_TIMER_ENABLE : 0) |
1653 GEN8_OA_COUNTER_RESUME);
1655 for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
1656 u32 state_offset = ctx_flexeu0 + i * 2;
1657 u32 mmio = i915_mmio_reg_offset(flex_regs[i]);
1660 * This arbitrary default will select the 'EU FPU0 Pipeline
1661 * Active' event. In the future it's anticipated that there
1662 * will be an explicit 'No Event' we can select, but not yet...
1669 for (j = 0; j < oa_config->flex_regs_len; j++) {
1670 if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {
1671 value = oa_config->flex_regs[j].value;
1677 CTX_REG(reg_state, state_offset, flex_regs[i], value);
1681 CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
1682 gen8_make_rpcs(i915, &ce->sseu));
1686 * Manages updating the per-context aspects of the OA stream
1687 * configuration across all contexts.
1689 * The awkward consideration here is that OACTXCONTROL controls the
1690 * exponent for periodic sampling which is primarily used for system
1691 * wide profiling where we'd like a consistent sampling period even in
1692 * the face of context switches.
1694 * Our approach of updating the register state context (as opposed to
1695 * say using a workaround batch buffer) ensures that the hardware
1696 * won't automatically reload an out-of-date timer exponent even
1697 * transiently before a WA BB could be parsed.
1699 * This function needs to:
1700 * - Ensure the currently running context's per-context OA state is
1702 * - Ensure that all existing contexts will have the correct per-context
1703 * OA state if they are scheduled for use.
1704 * - Ensure any new contexts will be initialized with the correct
1705 * per-context OA state.
1707 * Note: it's only the RCS/Render context that has any OA state.
1709 static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
1710 const struct i915_oa_config *oa_config)
1712 struct intel_engine_cs *engine = dev_priv->engine[RCS0];
1713 unsigned int map_type = i915_coherent_map_type(dev_priv);
1714 struct i915_gem_context *ctx;
1715 struct i915_request *rq;
1718 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1721 * The OA register config is setup through the context image. This image
1722 * might be written to by the GPU on context switch (in particular on
1723 * lite-restore). This means we can't safely update a context's image,
1724 * if this context is scheduled/submitted to run on the GPU.
1726 * We could emit the OA register config through the batch buffer but
1727 * this might leave small interval of time where the OA unit is
1728 * configured at an invalid sampling period.
1730 * So far the best way to work around this issue seems to be draining
1731 * the GPU from any submitted work.
1733 ret = i915_gem_wait_for_idle(dev_priv,
1735 MAX_SCHEDULE_TIMEOUT);
1739 /* Update all contexts now that we've stalled the submission. */
1740 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1741 struct intel_context *ce = intel_context_lookup(ctx, engine);
1744 /* OA settings will be set upon first use */
1745 if (!ce || !ce->state)
1748 regs = i915_gem_object_pin_map(ce->state->obj, map_type);
1750 return PTR_ERR(regs);
1752 ce->state->obj->mm.dirty = true;
1753 regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs);
1755 gen8_update_reg_state_unlocked(ce, regs, oa_config);
1757 i915_gem_object_unpin_map(ce->state->obj);
1761 * Apply the configuration by doing one context restore of the edited
1764 rq = i915_request_alloc(engine, dev_priv->kernel_context);
1768 i915_request_add(rq);
1773 static int gen8_enable_metric_set(struct i915_perf_stream *stream)
1775 struct drm_i915_private *dev_priv = stream->dev_priv;
1776 const struct i915_oa_config *oa_config = stream->oa_config;
1780 * We disable slice/unslice clock ratio change reports on SKL since
1781 * they are too noisy. The HW generates a lot of redundant reports
1782 * where the ratio hasn't really changed causing a lot of redundant
1783 * work to processes and increasing the chances we'll hit buffer
1786 * Although we don't currently use the 'disable overrun' OABUFFER
1787 * feature it's worth noting that clock ratio reports have to be
1788 * disabled before considering to use that feature since the HW doesn't
1789 * correctly block these reports.
1791 * Currently none of the high-level metrics we have depend on knowing
1792 * this ratio to normalize.
1794 * Note: This register is not power context saved and restored, but
1795 * that's OK considering that we disable RC6 while the OA unit is
1798 * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
1799 * be read back from automatically triggered reports, as part of the
1802 if (IS_GEN_RANGE(dev_priv, 9, 11)) {
1803 I915_WRITE(GEN8_OA_DEBUG,
1804 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
1805 GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
1809 * Update all contexts prior writing the mux configurations as we need
1810 * to make sure all slices/subslices are ON before writing to NOA
1813 ret = gen8_configure_all_contexts(dev_priv, oa_config);
1817 config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
1819 config_oa_regs(dev_priv, oa_config->b_counter_regs,
1820 oa_config->b_counter_regs_len);
1825 static void gen8_disable_metric_set(struct drm_i915_private *dev_priv)
1827 /* Reset all contexts' slices/subslices configurations. */
1828 gen8_configure_all_contexts(dev_priv, NULL);
1830 I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) &
1834 static void gen10_disable_metric_set(struct drm_i915_private *dev_priv)
1836 /* Reset all contexts' slices/subslices configurations. */
1837 gen8_configure_all_contexts(dev_priv, NULL);
1839 /* Make sure we disable noa to save power. */
1840 I915_WRITE(RPM_CONFIG1,
1841 I915_READ(RPM_CONFIG1) & ~GEN10_GT_NOA_ENABLE);
1844 static void gen7_oa_enable(struct i915_perf_stream *stream)
1846 struct drm_i915_private *dev_priv = stream->dev_priv;
1847 struct i915_gem_context *ctx = stream->ctx;
1848 u32 ctx_id = dev_priv->perf.oa.specific_ctx_id;
1849 bool periodic = dev_priv->perf.oa.periodic;
1850 u32 period_exponent = dev_priv->perf.oa.period_exponent;
1851 u32 report_format = dev_priv->perf.oa.oa_buffer.format;
1854 * Reset buf pointers so we don't forward reports from before now.
1856 * Think carefully if considering trying to avoid this, since it
1857 * also ensures status flags and the buffer itself are cleared
1858 * in error paths, and we have checks for invalid reports based
1859 * on the assumption that certain fields are written to zeroed
1860 * memory which this helps maintains.
1862 gen7_init_oa_buffer(dev_priv);
1864 I915_WRITE(GEN7_OACONTROL,
1865 (ctx_id & GEN7_OACONTROL_CTX_MASK) |
1867 GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
1868 (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
1869 (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
1870 (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
1871 GEN7_OACONTROL_ENABLE);
1874 static void gen8_oa_enable(struct i915_perf_stream *stream)
1876 struct drm_i915_private *dev_priv = stream->dev_priv;
1877 u32 report_format = dev_priv->perf.oa.oa_buffer.format;
1880 * Reset buf pointers so we don't forward reports from before now.
1882 * Think carefully if considering trying to avoid this, since it
1883 * also ensures status flags and the buffer itself are cleared
1884 * in error paths, and we have checks for invalid reports based
1885 * on the assumption that certain fields are written to zeroed
1886 * memory which this helps maintains.
1888 gen8_init_oa_buffer(dev_priv);
1891 * Note: we don't rely on the hardware to perform single context
1892 * filtering and instead filter on the cpu based on the context-id
1895 I915_WRITE(GEN8_OACONTROL, (report_format <<
1896 GEN8_OA_REPORT_FORMAT_SHIFT) |
1897 GEN8_OA_COUNTER_ENABLE);
1901 * i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
1902 * @stream: An i915 perf stream opened for OA metrics
1904 * [Re]enables hardware periodic sampling according to the period configured
1905 * when opening the stream. This also starts a hrtimer that will periodically
1906 * check for data in the circular OA buffer for notifying userspace (e.g.
1907 * during a read() or poll()).
1909 static void i915_oa_stream_enable(struct i915_perf_stream *stream)
1911 struct drm_i915_private *dev_priv = stream->dev_priv;
1913 dev_priv->perf.oa.ops.oa_enable(stream);
1915 if (dev_priv->perf.oa.periodic)
1916 hrtimer_start(&dev_priv->perf.oa.poll_check_timer,
1917 ns_to_ktime(POLL_PERIOD),
1918 HRTIMER_MODE_REL_PINNED);
1921 static void gen7_oa_disable(struct i915_perf_stream *stream)
1923 struct intel_uncore *uncore = &stream->dev_priv->uncore;
1925 intel_uncore_write(uncore, GEN7_OACONTROL, 0);
1926 if (intel_wait_for_register(uncore,
1927 GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
1929 DRM_ERROR("wait for OA to be disabled timed out\n");
1932 static void gen8_oa_disable(struct i915_perf_stream *stream)
1934 struct intel_uncore *uncore = &stream->dev_priv->uncore;
1936 intel_uncore_write(uncore, GEN8_OACONTROL, 0);
1937 if (intel_wait_for_register(uncore,
1938 GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
1940 DRM_ERROR("wait for OA to be disabled timed out\n");
1944 * i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
1945 * @stream: An i915 perf stream opened for OA metrics
1947 * Stops the OA unit from periodically writing counter reports into the
1948 * circular OA buffer. This also stops the hrtimer that periodically checks for
1949 * data in the circular OA buffer, for notifying userspace.
1951 static void i915_oa_stream_disable(struct i915_perf_stream *stream)
1953 struct drm_i915_private *dev_priv = stream->dev_priv;
1955 dev_priv->perf.oa.ops.oa_disable(stream);
1957 if (dev_priv->perf.oa.periodic)
1958 hrtimer_cancel(&dev_priv->perf.oa.poll_check_timer);
1961 static const struct i915_perf_stream_ops i915_oa_stream_ops = {
1962 .destroy = i915_oa_stream_destroy,
1963 .enable = i915_oa_stream_enable,
1964 .disable = i915_oa_stream_disable,
1965 .wait_unlocked = i915_oa_wait_unlocked,
1966 .poll_wait = i915_oa_poll_wait,
1967 .read = i915_oa_read,
1971 * i915_oa_stream_init - validate combined props for OA stream and init
1972 * @stream: An i915 perf stream
1973 * @param: The open parameters passed to `DRM_I915_PERF_OPEN`
1974 * @props: The property state that configures stream (individually validated)
1976 * While read_properties_unlocked() validates properties in isolation it
1977 * doesn't ensure that the combination necessarily makes sense.
1979 * At this point it has been determined that userspace wants a stream of
1980 * OA metrics, but still we need to further validate the combined
1981 * properties are OK.
1983 * If the configuration makes sense then we can allocate memory for
1984 * a circular OA buffer and apply the requested metric set configuration.
1986 * Returns: zero on success or a negative error code.
1988 static int i915_oa_stream_init(struct i915_perf_stream *stream,
1989 struct drm_i915_perf_open_param *param,
1990 struct perf_open_properties *props)
1992 struct drm_i915_private *dev_priv = stream->dev_priv;
1996 /* If the sysfs metrics/ directory wasn't registered for some
1997 * reason then don't let userspace try their luck with config
2000 if (!dev_priv->perf.metrics_kobj) {
2001 DRM_DEBUG("OA metrics weren't advertised via sysfs\n");
2005 if (!(props->sample_flags & SAMPLE_OA_REPORT)) {
2006 DRM_DEBUG("Only OA report sampling supported\n");
2010 if (!dev_priv->perf.oa.ops.enable_metric_set) {
2011 DRM_DEBUG("OA unit not supported\n");
2015 /* To avoid the complexity of having to accurately filter
2016 * counter reports and marshal to the appropriate client
2017 * we currently only allow exclusive access
2019 if (dev_priv->perf.oa.exclusive_stream) {
2020 DRM_DEBUG("OA unit already in use\n");
2024 if (!props->oa_format) {
2025 DRM_DEBUG("OA report format not specified\n");
2029 /* We set up some ratelimit state to potentially throttle any _NOTES
2030 * about spurious, invalid OA reports which we don't forward to
2033 * The initialization is associated with opening the stream (not driver
2034 * init) considering we print a _NOTE about any throttling when closing
2035 * the stream instead of waiting until driver _fini which no one would
2038 * Using the same limiting factors as printk_ratelimit()
2040 ratelimit_state_init(&dev_priv->perf.oa.spurious_report_rs,
2042 /* Since we use a DRM_NOTE for spurious reports it would be
2043 * inconsistent to let __ratelimit() automatically print a warning for
2046 ratelimit_set_flags(&dev_priv->perf.oa.spurious_report_rs,
2047 RATELIMIT_MSG_ON_RELEASE);
2049 stream->sample_size = sizeof(struct drm_i915_perf_record_header);
2051 format_size = dev_priv->perf.oa.oa_formats[props->oa_format].size;
2053 stream->sample_flags |= SAMPLE_OA_REPORT;
2054 stream->sample_size += format_size;
2056 dev_priv->perf.oa.oa_buffer.format_size = format_size;
2057 if (WARN_ON(dev_priv->perf.oa.oa_buffer.format_size == 0))
2060 dev_priv->perf.oa.oa_buffer.format =
2061 dev_priv->perf.oa.oa_formats[props->oa_format].format;
2063 dev_priv->perf.oa.periodic = props->oa_periodic;
2064 if (dev_priv->perf.oa.periodic)
2065 dev_priv->perf.oa.period_exponent = props->oa_period_exponent;
2068 ret = oa_get_render_ctx_id(stream);
2070 DRM_DEBUG("Invalid context id to filter with\n");
2075 ret = get_oa_config(dev_priv, props->metrics_set, &stream->oa_config);
2077 DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set);
2081 /* PRM - observability performance counters:
2083 * OACONTROL, performance counter enable, note:
2085 * "When this bit is set, in order to have coherent counts,
2086 * RC6 power state and trunk clock gating must be disabled.
2087 * This can be achieved by programming MMIO registers as
2088 * 0xA094=0 and 0xA090[31]=1"
2090 * In our case we are expecting that taking pm + FORCEWAKE
2091 * references will effectively disable RC6.
2093 stream->wakeref = intel_runtime_pm_get(dev_priv);
2094 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
2096 ret = alloc_oa_buffer(dev_priv);
2098 goto err_oa_buf_alloc;
2100 ret = i915_mutex_lock_interruptible(&dev_priv->drm);
2104 stream->ops = &i915_oa_stream_ops;
2105 dev_priv->perf.oa.exclusive_stream = stream;
2107 ret = dev_priv->perf.oa.ops.enable_metric_set(stream);
2109 DRM_DEBUG("Unable to enable metric set\n");
2113 mutex_unlock(&dev_priv->drm.struct_mutex);
2118 dev_priv->perf.oa.exclusive_stream = NULL;
2119 dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
2120 mutex_unlock(&dev_priv->drm.struct_mutex);
2123 free_oa_buffer(dev_priv);
2126 put_oa_config(dev_priv, stream->oa_config);
2128 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
2129 intel_runtime_pm_put(dev_priv, stream->wakeref);
2133 oa_put_render_ctx_id(stream);
2138 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
2139 struct intel_context *ce,
2142 struct i915_perf_stream *stream;
2144 if (engine->class != RENDER_CLASS)
2147 stream = engine->i915->perf.oa.exclusive_stream;
2149 gen8_update_reg_state_unlocked(ce, regs, stream->oa_config);
2153 * i915_perf_read_locked - &i915_perf_stream_ops->read with error normalisation
2154 * @stream: An i915 perf stream
2155 * @file: An i915 perf stream file
2156 * @buf: destination buffer given by userspace
2157 * @count: the number of bytes userspace wants to read
2158 * @ppos: (inout) file seek position (unused)
2160 * Besides wrapping &i915_perf_stream_ops->read this provides a common place to
2161 * ensure that if we've successfully copied any data then reporting that takes
2162 * precedence over any internal error status, so the data isn't lost.
2164 * For example ret will be -ENOSPC whenever there is more buffered data than
2165 * can be copied to userspace, but that's only interesting if we weren't able
2166 * to copy some data because it implies the userspace buffer is too small to
2167 * receive a single record (and we never split records).
2169 * Another case with ret == -EFAULT is more of a grey area since it would seem
2170 * like bad form for userspace to ask us to overrun its buffer, but the user
2173 * http://yarchive.net/comp/linux/partial_reads_writes.html
2175 * Returns: The number of bytes copied or a negative error code on failure.
2177 static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream,
2183 /* Note we keep the offset (aka bytes read) separate from any
2184 * error status so that the final check for whether we return
2185 * the bytes read with a higher precedence than any error (see
2186 * comment below) doesn't need to be handled/duplicated in
2187 * stream->ops->read() implementations.
2190 int ret = stream->ops->read(stream, buf, count, &offset);
2192 return offset ?: (ret ?: -EAGAIN);
2196 * i915_perf_read - handles read() FOP for i915 perf stream FDs
2197 * @file: An i915 perf stream file
2198 * @buf: destination buffer given by userspace
2199 * @count: the number of bytes userspace wants to read
2200 * @ppos: (inout) file seek position (unused)
2202 * The entry point for handling a read() on a stream file descriptor from
2203 * userspace. Most of the work is left to the i915_perf_read_locked() and
2204 * &i915_perf_stream_ops->read but to save having stream implementations (of
2205 * which we might have multiple later) we handle blocking read here.
2207 * We can also consistently treat trying to read from a disabled stream
2208 * as an IO error so implementations can assume the stream is enabled
2211 * Returns: The number of bytes copied or a negative error code on failure.
2213 static ssize_t i915_perf_read(struct file *file,
2218 struct i915_perf_stream *stream = file->private_data;
2219 struct drm_i915_private *dev_priv = stream->dev_priv;
2222 /* To ensure it's handled consistently we simply treat all reads of a
2223 * disabled stream as an error. In particular it might otherwise lead
2224 * to a deadlock for blocking file descriptors...
2226 if (!stream->enabled)
2229 if (!(file->f_flags & O_NONBLOCK)) {
2230 /* There's the small chance of false positives from
2231 * stream->ops->wait_unlocked.
2233 * E.g. with single context filtering since we only wait until
2234 * oabuffer has >= 1 report we don't immediately know whether
2235 * any reports really belong to the current context
2238 ret = stream->ops->wait_unlocked(stream);
2242 mutex_lock(&dev_priv->perf.lock);
2243 ret = i915_perf_read_locked(stream, file,
2245 mutex_unlock(&dev_priv->perf.lock);
2246 } while (ret == -EAGAIN);
2248 mutex_lock(&dev_priv->perf.lock);
2249 ret = i915_perf_read_locked(stream, file, buf, count, ppos);
2250 mutex_unlock(&dev_priv->perf.lock);
2253 /* We allow the poll checking to sometimes report false positive EPOLLIN
2254 * events where we might actually report EAGAIN on read() if there's
2255 * not really any data available. In this situation though we don't
2256 * want to enter a busy loop between poll() reporting a EPOLLIN event
2257 * and read() returning -EAGAIN. Clearing the oa.pollin state here
2258 * effectively ensures we back off until the next hrtimer callback
2259 * before reporting another EPOLLIN event.
2261 if (ret >= 0 || ret == -EAGAIN) {
2262 /* Maybe make ->pollin per-stream state if we support multiple
2263 * concurrent streams in the future.
2265 dev_priv->perf.oa.pollin = false;
2271 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer)
2273 struct drm_i915_private *dev_priv =
2274 container_of(hrtimer, typeof(*dev_priv),
2275 perf.oa.poll_check_timer);
2277 if (oa_buffer_check_unlocked(dev_priv)) {
2278 dev_priv->perf.oa.pollin = true;
2279 wake_up(&dev_priv->perf.oa.poll_wq);
2282 hrtimer_forward_now(hrtimer, ns_to_ktime(POLL_PERIOD));
2284 return HRTIMER_RESTART;
2288 * i915_perf_poll_locked - poll_wait() with a suitable wait queue for stream
2289 * @dev_priv: i915 device instance
2290 * @stream: An i915 perf stream
2291 * @file: An i915 perf stream file
2292 * @wait: poll() state table
2294 * For handling userspace polling on an i915 perf stream, this calls through to
2295 * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
2296 * will be woken for new stream data.
2298 * Note: The &drm_i915_private->perf.lock mutex has been taken to serialize
2299 * with any non-file-operation driver hooks.
2301 * Returns: any poll events that are ready without sleeping
2303 static __poll_t i915_perf_poll_locked(struct drm_i915_private *dev_priv,
2304 struct i915_perf_stream *stream,
2308 __poll_t events = 0;
2310 stream->ops->poll_wait(stream, file, wait);
2312 /* Note: we don't explicitly check whether there's something to read
2313 * here since this path may be very hot depending on what else
2314 * userspace is polling, or on the timeout in use. We rely solely on
2315 * the hrtimer/oa_poll_check_timer_cb to notify us when there are
2318 if (dev_priv->perf.oa.pollin)
2325 * i915_perf_poll - call poll_wait() with a suitable wait queue for stream
2326 * @file: An i915 perf stream file
2327 * @wait: poll() state table
2329 * For handling userspace polling on an i915 perf stream, this ensures
2330 * poll_wait() gets called with a wait queue that will be woken for new stream
2333 * Note: Implementation deferred to i915_perf_poll_locked()
2335 * Returns: any poll events that are ready without sleeping
2337 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
2339 struct i915_perf_stream *stream = file->private_data;
2340 struct drm_i915_private *dev_priv = stream->dev_priv;
2343 mutex_lock(&dev_priv->perf.lock);
2344 ret = i915_perf_poll_locked(dev_priv, stream, file, wait);
2345 mutex_unlock(&dev_priv->perf.lock);
2351 * i915_perf_enable_locked - handle `I915_PERF_IOCTL_ENABLE` ioctl
2352 * @stream: A disabled i915 perf stream
2354 * [Re]enables the associated capture of data for this stream.
2356 * If a stream was previously enabled then there's currently no intention
2357 * to provide userspace any guarantee about the preservation of previously
2360 static void i915_perf_enable_locked(struct i915_perf_stream *stream)
2362 if (stream->enabled)
2365 /* Allow stream->ops->enable() to refer to this */
2366 stream->enabled = true;
2368 if (stream->ops->enable)
2369 stream->ops->enable(stream);
2373 * i915_perf_disable_locked - handle `I915_PERF_IOCTL_DISABLE` ioctl
2374 * @stream: An enabled i915 perf stream
2376 * Disables the associated capture of data for this stream.
2378 * The intention is that disabling an re-enabling a stream will ideally be
2379 * cheaper than destroying and re-opening a stream with the same configuration,
2380 * though there are no formal guarantees about what state or buffered data
2381 * must be retained between disabling and re-enabling a stream.
2383 * Note: while a stream is disabled it's considered an error for userspace
2384 * to attempt to read from the stream (-EIO).
2386 static void i915_perf_disable_locked(struct i915_perf_stream *stream)
2388 if (!stream->enabled)
2391 /* Allow stream->ops->disable() to refer to this */
2392 stream->enabled = false;
2394 if (stream->ops->disable)
2395 stream->ops->disable(stream);
2399 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
2400 * @stream: An i915 perf stream
2401 * @cmd: the ioctl request
2402 * @arg: the ioctl data
2404 * Note: The &drm_i915_private->perf.lock mutex has been taken to serialize
2405 * with any non-file-operation driver hooks.
2407 * Returns: zero on success or a negative error code. Returns -EINVAL for
2408 * an unknown ioctl request.
2410 static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
2415 case I915_PERF_IOCTL_ENABLE:
2416 i915_perf_enable_locked(stream);
2418 case I915_PERF_IOCTL_DISABLE:
2419 i915_perf_disable_locked(stream);
2427 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
2428 * @file: An i915 perf stream file
2429 * @cmd: the ioctl request
2430 * @arg: the ioctl data
2432 * Implementation deferred to i915_perf_ioctl_locked().
2434 * Returns: zero on success or a negative error code. Returns -EINVAL for
2435 * an unknown ioctl request.
2437 static long i915_perf_ioctl(struct file *file,
2441 struct i915_perf_stream *stream = file->private_data;
2442 struct drm_i915_private *dev_priv = stream->dev_priv;
2445 mutex_lock(&dev_priv->perf.lock);
2446 ret = i915_perf_ioctl_locked(stream, cmd, arg);
2447 mutex_unlock(&dev_priv->perf.lock);
2453 * i915_perf_destroy_locked - destroy an i915 perf stream
2454 * @stream: An i915 perf stream
2456 * Frees all resources associated with the given i915 perf @stream, disabling
2457 * any associated data capture in the process.
2459 * Note: The &drm_i915_private->perf.lock mutex has been taken to serialize
2460 * with any non-file-operation driver hooks.
2462 static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
2464 if (stream->enabled)
2465 i915_perf_disable_locked(stream);
2467 if (stream->ops->destroy)
2468 stream->ops->destroy(stream);
2470 list_del(&stream->link);
2473 i915_gem_context_put(stream->ctx);
2479 * i915_perf_release - handles userspace close() of a stream file
2480 * @inode: anonymous inode associated with file
2481 * @file: An i915 perf stream file
2483 * Cleans up any resources associated with an open i915 perf stream file.
2485 * NB: close() can't really fail from the userspace point of view.
2487 * Returns: zero on success or a negative error code.
2489 static int i915_perf_release(struct inode *inode, struct file *file)
2491 struct i915_perf_stream *stream = file->private_data;
2492 struct drm_i915_private *dev_priv = stream->dev_priv;
2494 mutex_lock(&dev_priv->perf.lock);
2495 i915_perf_destroy_locked(stream);
2496 mutex_unlock(&dev_priv->perf.lock);
2502 static const struct file_operations fops = {
2503 .owner = THIS_MODULE,
2504 .llseek = no_llseek,
2505 .release = i915_perf_release,
2506 .poll = i915_perf_poll,
2507 .read = i915_perf_read,
2508 .unlocked_ioctl = i915_perf_ioctl,
2509 /* Our ioctl have no arguments, so it's safe to use the same function
2510 * to handle 32bits compatibility.
2512 .compat_ioctl = i915_perf_ioctl,
2517 * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD
2518 * @dev_priv: i915 device instance
2519 * @param: The open parameters passed to 'DRM_I915_PERF_OPEN`
2520 * @props: individually validated u64 property value pairs
2523 * See i915_perf_ioctl_open() for interface details.
2525 * Implements further stream config validation and stream initialization on
2526 * behalf of i915_perf_open_ioctl() with the &drm_i915_private->perf.lock mutex
2527 * taken to serialize with any non-file-operation driver hooks.
2529 * Note: at this point the @props have only been validated in isolation and
2530 * it's still necessary to validate that the combination of properties makes
2533 * In the case where userspace is interested in OA unit metrics then further
2534 * config validation and stream initialization details will be handled by
2535 * i915_oa_stream_init(). The code here should only validate config state that
2536 * will be relevant to all stream types / backends.
2538 * Returns: zero on success or a negative error code.
2541 i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
2542 struct drm_i915_perf_open_param *param,
2543 struct perf_open_properties *props,
2544 struct drm_file *file)
2546 struct i915_gem_context *specific_ctx = NULL;
2547 struct i915_perf_stream *stream = NULL;
2548 unsigned long f_flags = 0;
2549 bool privileged_op = true;
2553 if (props->single_context) {
2554 u32 ctx_handle = props->ctx_handle;
2555 struct drm_i915_file_private *file_priv = file->driver_priv;
2557 specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle);
2558 if (!specific_ctx) {
2559 DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n",
2567 * On Haswell the OA unit supports clock gating off for a specific
2568 * context and in this mode there's no visibility of metrics for the
2569 * rest of the system, which we consider acceptable for a
2570 * non-privileged client.
2572 * For Gen8+ the OA unit no longer supports clock gating off for a
2573 * specific context and the kernel can't securely stop the counters
2574 * from updating as system-wide / global values. Even though we can
2575 * filter reports based on the included context ID we can't block
2576 * clients from seeing the raw / global counter values via
2577 * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
2578 * enable the OA unit by default.
2580 if (IS_HASWELL(dev_priv) && specific_ctx)
2581 privileged_op = false;
2583 /* Similar to perf's kernel.perf_paranoid_cpu sysctl option
2584 * we check a dev.i915.perf_stream_paranoid sysctl option
2585 * to determine if it's ok to access system wide OA counters
2586 * without CAP_SYS_ADMIN privileges.
2588 if (privileged_op &&
2589 i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
2590 DRM_DEBUG("Insufficient privileges to open system-wide i915 perf stream\n");
2595 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
2601 stream->dev_priv = dev_priv;
2602 stream->ctx = specific_ctx;
2604 ret = i915_oa_stream_init(stream, param, props);
2608 /* we avoid simply assigning stream->sample_flags = props->sample_flags
2609 * to have _stream_init check the combination of sample flags more
2610 * thoroughly, but still this is the expected result at this point.
2612 if (WARN_ON(stream->sample_flags != props->sample_flags)) {
2617 list_add(&stream->link, &dev_priv->perf.streams);
2619 if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
2620 f_flags |= O_CLOEXEC;
2621 if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
2622 f_flags |= O_NONBLOCK;
2624 stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
2625 if (stream_fd < 0) {
2630 if (!(param->flags & I915_PERF_FLAG_DISABLED))
2631 i915_perf_enable_locked(stream);
2636 list_del(&stream->link);
2638 if (stream->ops->destroy)
2639 stream->ops->destroy(stream);
2644 i915_gem_context_put(specific_ctx);
2649 static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
2651 return div64_u64(1000000000ULL * (2ULL << exponent),
2652 1000ULL * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
2656 * read_properties_unlocked - validate + copy userspace stream open properties
2657 * @dev_priv: i915 device instance
2658 * @uprops: The array of u64 key value pairs given by userspace
2659 * @n_props: The number of key value pairs expected in @uprops
2660 * @props: The stream configuration built up while validating properties
2662 * Note this function only validates properties in isolation it doesn't
2663 * validate that the combination of properties makes sense or that all
2664 * properties necessary for a particular kind of stream have been set.
2666 * Note that there currently aren't any ordering requirements for properties so
2667 * we shouldn't validate or assume anything about ordering here. This doesn't
2668 * rule out defining new properties with ordering requirements in the future.
2670 static int read_properties_unlocked(struct drm_i915_private *dev_priv,
2673 struct perf_open_properties *props)
2675 u64 __user *uprop = uprops;
2678 memset(props, 0, sizeof(struct perf_open_properties));
2681 DRM_DEBUG("No i915 perf properties given\n");
2685 /* Considering that ID = 0 is reserved and assuming that we don't
2686 * (currently) expect any configurations to ever specify duplicate
2687 * values for a particular property ID then the last _PROP_MAX value is
2688 * one greater than the maximum number of properties we expect to get
2691 if (n_props >= DRM_I915_PERF_PROP_MAX) {
2692 DRM_DEBUG("More i915 perf properties specified than exist\n");
2696 for (i = 0; i < n_props; i++) {
2697 u64 oa_period, oa_freq_hz;
2701 ret = get_user(id, uprop);
2705 ret = get_user(value, uprop + 1);
2709 if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) {
2710 DRM_DEBUG("Unknown i915 perf property ID\n");
2714 switch ((enum drm_i915_perf_property_id)id) {
2715 case DRM_I915_PERF_PROP_CTX_HANDLE:
2716 props->single_context = 1;
2717 props->ctx_handle = value;
2719 case DRM_I915_PERF_PROP_SAMPLE_OA:
2721 props->sample_flags |= SAMPLE_OA_REPORT;
2723 case DRM_I915_PERF_PROP_OA_METRICS_SET:
2725 DRM_DEBUG("Unknown OA metric set ID\n");
2728 props->metrics_set = value;
2730 case DRM_I915_PERF_PROP_OA_FORMAT:
2731 if (value == 0 || value >= I915_OA_FORMAT_MAX) {
2732 DRM_DEBUG("Out-of-range OA report format %llu\n",
2736 if (!dev_priv->perf.oa.oa_formats[value].size) {
2737 DRM_DEBUG("Unsupported OA report format %llu\n",
2741 props->oa_format = value;
2743 case DRM_I915_PERF_PROP_OA_EXPONENT:
2744 if (value > OA_EXPONENT_MAX) {
2745 DRM_DEBUG("OA timer exponent too high (> %u)\n",
2750 /* Theoretically we can program the OA unit to sample
2751 * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns
2752 * for BXT. We don't allow such high sampling
2753 * frequencies by default unless root.
2756 BUILD_BUG_ON(sizeof(oa_period) != 8);
2757 oa_period = oa_exponent_to_ns(dev_priv, value);
2759 /* This check is primarily to ensure that oa_period <=
2760 * UINT32_MAX (before passing to do_div which only
2761 * accepts a u32 denominator), but we can also skip
2762 * checking anything < 1Hz which implicitly can't be
2763 * limited via an integer oa_max_sample_rate.
2765 if (oa_period <= NSEC_PER_SEC) {
2766 u64 tmp = NSEC_PER_SEC;
2767 do_div(tmp, oa_period);
2772 if (oa_freq_hz > i915_oa_max_sample_rate &&
2773 !capable(CAP_SYS_ADMIN)) {
2774 DRM_DEBUG("OA exponent would exceed the max sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without root privileges\n",
2775 i915_oa_max_sample_rate);
2779 props->oa_periodic = true;
2780 props->oa_period_exponent = value;
2782 case DRM_I915_PERF_PROP_MAX:
2794 * i915_perf_open_ioctl - DRM ioctl() for userspace to open a stream FD
2796 * @data: ioctl data copied from userspace (unvalidated)
2799 * Validates the stream open parameters given by userspace including flags
2800 * and an array of u64 key, value pair properties.
2802 * Very little is assumed up front about the nature of the stream being
2803 * opened (for instance we don't assume it's for periodic OA unit metrics). An
2804 * i915-perf stream is expected to be a suitable interface for other forms of
2805 * buffered data written by the GPU besides periodic OA metrics.
2807 * Note we copy the properties from userspace outside of the i915 perf
2808 * mutex to avoid an awkward lockdep with mmap_sem.
2810 * Most of the implementation details are handled by
2811 * i915_perf_open_ioctl_locked() after taking the &drm_i915_private->perf.lock
2812 * mutex for serializing with any non-file-operation driver hooks.
2814 * Return: A newly opened i915 Perf stream file descriptor or negative
2815 * error code on failure.
2817 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
2818 struct drm_file *file)
2820 struct drm_i915_private *dev_priv = dev->dev_private;
2821 struct drm_i915_perf_open_param *param = data;
2822 struct perf_open_properties props;
2823 u32 known_open_flags;
2826 if (!dev_priv->perf.initialized) {
2827 DRM_DEBUG("i915 perf interface not available for this system\n");
2831 known_open_flags = I915_PERF_FLAG_FD_CLOEXEC |
2832 I915_PERF_FLAG_FD_NONBLOCK |
2833 I915_PERF_FLAG_DISABLED;
2834 if (param->flags & ~known_open_flags) {
2835 DRM_DEBUG("Unknown drm_i915_perf_open_param flag\n");
2839 ret = read_properties_unlocked(dev_priv,
2840 u64_to_user_ptr(param->properties_ptr),
2841 param->num_properties,
2846 mutex_lock(&dev_priv->perf.lock);
2847 ret = i915_perf_open_ioctl_locked(dev_priv, param, &props, file);
2848 mutex_unlock(&dev_priv->perf.lock);
2854 * i915_perf_register - exposes i915-perf to userspace
2855 * @dev_priv: i915 device instance
2857 * In particular OA metric sets are advertised under a sysfs metrics/
2858 * directory allowing userspace to enumerate valid IDs that can be
2859 * used to open an i915-perf stream.
2861 void i915_perf_register(struct drm_i915_private *dev_priv)
2865 if (!dev_priv->perf.initialized)
2868 /* To be sure we're synchronized with an attempted
2869 * i915_perf_open_ioctl(); considering that we register after
2870 * being exposed to userspace.
2872 mutex_lock(&dev_priv->perf.lock);
2874 dev_priv->perf.metrics_kobj =
2875 kobject_create_and_add("metrics",
2876 &dev_priv->drm.primary->kdev->kobj);
2877 if (!dev_priv->perf.metrics_kobj)
2880 sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
2882 if (INTEL_GEN(dev_priv) >= 11) {
2883 i915_perf_load_test_config_icl(dev_priv);
2884 } else if (IS_CANNONLAKE(dev_priv)) {
2885 i915_perf_load_test_config_cnl(dev_priv);
2886 } else if (IS_COFFEELAKE(dev_priv)) {
2887 if (IS_CFL_GT2(dev_priv))
2888 i915_perf_load_test_config_cflgt2(dev_priv);
2889 if (IS_CFL_GT3(dev_priv))
2890 i915_perf_load_test_config_cflgt3(dev_priv);
2891 } else if (IS_GEMINILAKE(dev_priv)) {
2892 i915_perf_load_test_config_glk(dev_priv);
2893 } else if (IS_KABYLAKE(dev_priv)) {
2894 if (IS_KBL_GT2(dev_priv))
2895 i915_perf_load_test_config_kblgt2(dev_priv);
2896 else if (IS_KBL_GT3(dev_priv))
2897 i915_perf_load_test_config_kblgt3(dev_priv);
2898 } else if (IS_BROXTON(dev_priv)) {
2899 i915_perf_load_test_config_bxt(dev_priv);
2900 } else if (IS_SKYLAKE(dev_priv)) {
2901 if (IS_SKL_GT2(dev_priv))
2902 i915_perf_load_test_config_sklgt2(dev_priv);
2903 else if (IS_SKL_GT3(dev_priv))
2904 i915_perf_load_test_config_sklgt3(dev_priv);
2905 else if (IS_SKL_GT4(dev_priv))
2906 i915_perf_load_test_config_sklgt4(dev_priv);
2907 } else if (IS_CHERRYVIEW(dev_priv)) {
2908 i915_perf_load_test_config_chv(dev_priv);
2909 } else if (IS_BROADWELL(dev_priv)) {
2910 i915_perf_load_test_config_bdw(dev_priv);
2911 } else if (IS_HASWELL(dev_priv)) {
2912 i915_perf_load_test_config_hsw(dev_priv);
2915 if (dev_priv->perf.oa.test_config.id == 0)
2918 ret = sysfs_create_group(dev_priv->perf.metrics_kobj,
2919 &dev_priv->perf.oa.test_config.sysfs_metric);
2923 atomic_set(&dev_priv->perf.oa.test_config.ref_count, 1);
2928 kobject_put(dev_priv->perf.metrics_kobj);
2929 dev_priv->perf.metrics_kobj = NULL;
2932 mutex_unlock(&dev_priv->perf.lock);
2936 * i915_perf_unregister - hide i915-perf from userspace
2937 * @dev_priv: i915 device instance
2939 * i915-perf state cleanup is split up into an 'unregister' and
2940 * 'deinit' phase where the interface is first hidden from
2941 * userspace by i915_perf_unregister() before cleaning up
2942 * remaining state in i915_perf_fini().
2944 void i915_perf_unregister(struct drm_i915_private *dev_priv)
2946 if (!dev_priv->perf.metrics_kobj)
2949 sysfs_remove_group(dev_priv->perf.metrics_kobj,
2950 &dev_priv->perf.oa.test_config.sysfs_metric);
2952 kobject_put(dev_priv->perf.metrics_kobj);
2953 dev_priv->perf.metrics_kobj = NULL;
2956 static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv, u32 addr)
2958 static const i915_reg_t flex_eu_regs[] = {
2969 for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
2970 if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)
2976 static bool gen7_is_valid_b_counter_addr(struct drm_i915_private *dev_priv, u32 addr)
2978 return (addr >= i915_mmio_reg_offset(OASTARTTRIG1) &&
2979 addr <= i915_mmio_reg_offset(OASTARTTRIG8)) ||
2980 (addr >= i915_mmio_reg_offset(OAREPORTTRIG1) &&
2981 addr <= i915_mmio_reg_offset(OAREPORTTRIG8)) ||
2982 (addr >= i915_mmio_reg_offset(OACEC0_0) &&
2983 addr <= i915_mmio_reg_offset(OACEC7_1));
2986 static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
2988 return addr == i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) ||
2989 (addr >= i915_mmio_reg_offset(MICRO_BP0_0) &&
2990 addr <= i915_mmio_reg_offset(NOA_WRITE)) ||
2991 (addr >= i915_mmio_reg_offset(OA_PERFCNT1_LO) &&
2992 addr <= i915_mmio_reg_offset(OA_PERFCNT2_HI)) ||
2993 (addr >= i915_mmio_reg_offset(OA_PERFMATRIX_LO) &&
2994 addr <= i915_mmio_reg_offset(OA_PERFMATRIX_HI));
2997 static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
2999 return gen7_is_valid_mux_addr(dev_priv, addr) ||
3000 addr == i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) ||
3001 (addr >= i915_mmio_reg_offset(RPM_CONFIG0) &&
3002 addr <= i915_mmio_reg_offset(NOA_CONFIG(8)));
3005 static bool gen10_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
3007 return gen8_is_valid_mux_addr(dev_priv, addr) ||
3008 (addr >= i915_mmio_reg_offset(OA_PERFCNT3_LO) &&
3009 addr <= i915_mmio_reg_offset(OA_PERFCNT4_HI));
3012 static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
3014 return gen7_is_valid_mux_addr(dev_priv, addr) ||
3015 (addr >= 0x25100 && addr <= 0x2FF90) ||
3016 (addr >= i915_mmio_reg_offset(HSW_MBVID2_NOA0) &&
3017 addr <= i915_mmio_reg_offset(HSW_MBVID2_NOA9)) ||
3018 addr == i915_mmio_reg_offset(HSW_MBVID2_MISR0);
3021 static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
3023 return gen7_is_valid_mux_addr(dev_priv, addr) ||
3024 (addr >= 0x182300 && addr <= 0x1823A4);
3027 static u32 mask_reg_value(u32 reg, u32 val)
3029 /* HALF_SLICE_CHICKEN2 is programmed with a the
3030 * WaDisableSTUnitPowerOptimization workaround. Make sure the value
3031 * programmed by userspace doesn't change this.
3033 if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg)
3034 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
3036 /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
3037 * indicated by its name and a bunch of selection fields used by OA
3040 if (i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) == reg)
3041 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
3046 static struct i915_oa_reg *alloc_oa_regs(struct drm_i915_private *dev_priv,
3047 bool (*is_valid)(struct drm_i915_private *dev_priv, u32 addr),
3051 struct i915_oa_reg *oa_regs;
3058 if (!access_ok(regs, n_regs * sizeof(u32) * 2))
3059 return ERR_PTR(-EFAULT);
3061 /* No is_valid function means we're not allowing any register to be programmed. */
3062 GEM_BUG_ON(!is_valid);
3064 return ERR_PTR(-EINVAL);
3066 oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL);
3068 return ERR_PTR(-ENOMEM);
3070 for (i = 0; i < n_regs; i++) {
3073 err = get_user(addr, regs);
3077 if (!is_valid(dev_priv, addr)) {
3078 DRM_DEBUG("Invalid oa_reg address: %X\n", addr);
3083 err = get_user(value, regs + 1);
3087 oa_regs[i].addr = _MMIO(addr);
3088 oa_regs[i].value = mask_reg_value(addr, value);
3097 return ERR_PTR(err);
3100 static ssize_t show_dynamic_id(struct device *dev,
3101 struct device_attribute *attr,
3104 struct i915_oa_config *oa_config =
3105 container_of(attr, typeof(*oa_config), sysfs_metric_id);
3107 return sprintf(buf, "%d\n", oa_config->id);
3110 static int create_dynamic_oa_sysfs_entry(struct drm_i915_private *dev_priv,
3111 struct i915_oa_config *oa_config)
3113 sysfs_attr_init(&oa_config->sysfs_metric_id.attr);
3114 oa_config->sysfs_metric_id.attr.name = "id";
3115 oa_config->sysfs_metric_id.attr.mode = S_IRUGO;
3116 oa_config->sysfs_metric_id.show = show_dynamic_id;
3117 oa_config->sysfs_metric_id.store = NULL;
3119 oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr;
3120 oa_config->attrs[1] = NULL;
3122 oa_config->sysfs_metric.name = oa_config->uuid;
3123 oa_config->sysfs_metric.attrs = oa_config->attrs;
3125 return sysfs_create_group(dev_priv->perf.metrics_kobj,
3126 &oa_config->sysfs_metric);
3130 * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config
3132 * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from
3133 * userspace (unvalidated)
3136 * Validates the submitted OA register to be saved into a new OA config that
3137 * can then be used for programming the OA unit and its NOA network.
3139 * Returns: A new allocated config number to be used with the perf open ioctl
3140 * or a negative error code on failure.
3142 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3143 struct drm_file *file)
3145 struct drm_i915_private *dev_priv = dev->dev_private;
3146 struct drm_i915_perf_oa_config *args = data;
3147 struct i915_oa_config *oa_config, *tmp;
3150 if (!dev_priv->perf.initialized) {
3151 DRM_DEBUG("i915 perf interface not available for this system\n");
3155 if (!dev_priv->perf.metrics_kobj) {
3156 DRM_DEBUG("OA metrics weren't advertised via sysfs\n");
3160 if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
3161 DRM_DEBUG("Insufficient privileges to add i915 OA config\n");
3165 if ((!args->mux_regs_ptr || !args->n_mux_regs) &&
3166 (!args->boolean_regs_ptr || !args->n_boolean_regs) &&
3167 (!args->flex_regs_ptr || !args->n_flex_regs)) {
3168 DRM_DEBUG("No OA registers given\n");
3172 oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
3174 DRM_DEBUG("Failed to allocate memory for the OA config\n");
3178 atomic_set(&oa_config->ref_count, 1);
3180 if (!uuid_is_valid(args->uuid)) {
3181 DRM_DEBUG("Invalid uuid format for OA config\n");
3186 /* Last character in oa_config->uuid will be 0 because oa_config is
3189 memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid));
3191 oa_config->mux_regs_len = args->n_mux_regs;
3192 oa_config->mux_regs =
3193 alloc_oa_regs(dev_priv,
3194 dev_priv->perf.oa.ops.is_valid_mux_reg,
3195 u64_to_user_ptr(args->mux_regs_ptr),
3198 if (IS_ERR(oa_config->mux_regs)) {
3199 DRM_DEBUG("Failed to create OA config for mux_regs\n");
3200 err = PTR_ERR(oa_config->mux_regs);
3204 oa_config->b_counter_regs_len = args->n_boolean_regs;
3205 oa_config->b_counter_regs =
3206 alloc_oa_regs(dev_priv,
3207 dev_priv->perf.oa.ops.is_valid_b_counter_reg,
3208 u64_to_user_ptr(args->boolean_regs_ptr),
3209 args->n_boolean_regs);
3211 if (IS_ERR(oa_config->b_counter_regs)) {
3212 DRM_DEBUG("Failed to create OA config for b_counter_regs\n");
3213 err = PTR_ERR(oa_config->b_counter_regs);
3217 if (INTEL_GEN(dev_priv) < 8) {
3218 if (args->n_flex_regs != 0) {
3223 oa_config->flex_regs_len = args->n_flex_regs;
3224 oa_config->flex_regs =
3225 alloc_oa_regs(dev_priv,
3226 dev_priv->perf.oa.ops.is_valid_flex_reg,
3227 u64_to_user_ptr(args->flex_regs_ptr),
3230 if (IS_ERR(oa_config->flex_regs)) {
3231 DRM_DEBUG("Failed to create OA config for flex_regs\n");
3232 err = PTR_ERR(oa_config->flex_regs);
3237 err = mutex_lock_interruptible(&dev_priv->perf.metrics_lock);
3241 /* We shouldn't have too many configs, so this iteration shouldn't be
3244 idr_for_each_entry(&dev_priv->perf.metrics_idr, tmp, id) {
3245 if (!strcmp(tmp->uuid, oa_config->uuid)) {
3246 DRM_DEBUG("OA config already exists with this uuid\n");
3252 err = create_dynamic_oa_sysfs_entry(dev_priv, oa_config);
3254 DRM_DEBUG("Failed to create sysfs entry for OA config\n");
3258 /* Config id 0 is invalid, id 1 for kernel stored test config. */
3259 oa_config->id = idr_alloc(&dev_priv->perf.metrics_idr,
3262 if (oa_config->id < 0) {
3263 DRM_DEBUG("Failed to create sysfs entry for OA config\n");
3264 err = oa_config->id;
3268 mutex_unlock(&dev_priv->perf.metrics_lock);
3270 DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id);
3272 return oa_config->id;
3275 mutex_unlock(&dev_priv->perf.metrics_lock);
3277 put_oa_config(dev_priv, oa_config);
3278 DRM_DEBUG("Failed to add new OA config\n");
3283 * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config
3285 * @data: ioctl data (pointer to u64 integer) copied from userspace
3288 * Configs can be removed while being used, the will stop appearing in sysfs
3289 * and their content will be freed when the stream using the config is closed.
3291 * Returns: 0 on success or a negative error code on failure.
3293 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3294 struct drm_file *file)
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3298 struct i915_oa_config *oa_config;
3301 if (!dev_priv->perf.initialized) {
3302 DRM_DEBUG("i915 perf interface not available for this system\n");
3306 if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
3307 DRM_DEBUG("Insufficient privileges to remove i915 OA config\n");
3311 ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock);
3315 oa_config = idr_find(&dev_priv->perf.metrics_idr, *arg);
3317 DRM_DEBUG("Failed to remove unknown OA config\n");
3322 GEM_BUG_ON(*arg != oa_config->id);
3324 sysfs_remove_group(dev_priv->perf.metrics_kobj,
3325 &oa_config->sysfs_metric);
3327 idr_remove(&dev_priv->perf.metrics_idr, *arg);
3329 DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
3331 put_oa_config(dev_priv, oa_config);
3334 mutex_unlock(&dev_priv->perf.metrics_lock);
3339 static struct ctl_table oa_table[] = {
3341 .procname = "perf_stream_paranoid",
3342 .data = &i915_perf_stream_paranoid,
3343 .maxlen = sizeof(i915_perf_stream_paranoid),
3345 .proc_handler = proc_dointvec_minmax,
3350 .procname = "oa_max_sample_rate",
3351 .data = &i915_oa_max_sample_rate,
3352 .maxlen = sizeof(i915_oa_max_sample_rate),
3354 .proc_handler = proc_dointvec_minmax,
3356 .extra2 = &oa_sample_rate_hard_limit,
3361 static struct ctl_table i915_root[] = {
3371 static struct ctl_table dev_root[] = {
3382 * i915_perf_init - initialize i915-perf state on module load
3383 * @dev_priv: i915 device instance
3385 * Initializes i915-perf state without exposing anything to userspace.
3387 * Note: i915-perf initialization is split into an 'init' and 'register'
3388 * phase with the i915_perf_register() exposing state to userspace.
3390 void i915_perf_init(struct drm_i915_private *dev_priv)
3392 if (IS_HASWELL(dev_priv)) {
3393 dev_priv->perf.oa.ops.is_valid_b_counter_reg =
3394 gen7_is_valid_b_counter_addr;
3395 dev_priv->perf.oa.ops.is_valid_mux_reg =
3396 hsw_is_valid_mux_addr;
3397 dev_priv->perf.oa.ops.is_valid_flex_reg = NULL;
3398 dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set;
3399 dev_priv->perf.oa.ops.disable_metric_set = hsw_disable_metric_set;
3400 dev_priv->perf.oa.ops.oa_enable = gen7_oa_enable;
3401 dev_priv->perf.oa.ops.oa_disable = gen7_oa_disable;
3402 dev_priv->perf.oa.ops.read = gen7_oa_read;
3403 dev_priv->perf.oa.ops.oa_hw_tail_read =
3404 gen7_oa_hw_tail_read;
3406 dev_priv->perf.oa.oa_formats = hsw_oa_formats;
3407 } else if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
3408 /* Note: that although we could theoretically also support the
3409 * legacy ringbuffer mode on BDW (and earlier iterations of
3410 * this driver, before upstreaming did this) it didn't seem
3411 * worth the complexity to maintain now that BDW+ enable
3412 * execlist mode by default.
3414 dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats;
3416 dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable;
3417 dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable;
3418 dev_priv->perf.oa.ops.read = gen8_oa_read;
3419 dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
3421 if (IS_GEN_RANGE(dev_priv, 8, 9)) {
3422 dev_priv->perf.oa.ops.is_valid_b_counter_reg =
3423 gen7_is_valid_b_counter_addr;
3424 dev_priv->perf.oa.ops.is_valid_mux_reg =
3425 gen8_is_valid_mux_addr;
3426 dev_priv->perf.oa.ops.is_valid_flex_reg =
3427 gen8_is_valid_flex_addr;
3429 if (IS_CHERRYVIEW(dev_priv)) {
3430 dev_priv->perf.oa.ops.is_valid_mux_reg =
3431 chv_is_valid_mux_addr;
3434 dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
3435 dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set;
3437 if (IS_GEN(dev_priv, 8)) {
3438 dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120;
3439 dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce;
3441 dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25);
3443 dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
3444 dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
3446 dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
3448 } else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
3449 dev_priv->perf.oa.ops.is_valid_b_counter_reg =
3450 gen7_is_valid_b_counter_addr;
3451 dev_priv->perf.oa.ops.is_valid_mux_reg =
3452 gen10_is_valid_mux_addr;
3453 dev_priv->perf.oa.ops.is_valid_flex_reg =
3454 gen8_is_valid_flex_addr;
3456 dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
3457 dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set;
3459 dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
3460 dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
3462 dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
3466 if (dev_priv->perf.oa.ops.enable_metric_set) {
3467 hrtimer_init(&dev_priv->perf.oa.poll_check_timer,
3468 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3469 dev_priv->perf.oa.poll_check_timer.function = oa_poll_check_timer_cb;
3470 init_waitqueue_head(&dev_priv->perf.oa.poll_wq);
3472 INIT_LIST_HEAD(&dev_priv->perf.streams);
3473 mutex_init(&dev_priv->perf.lock);
3474 spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
3476 oa_sample_rate_hard_limit = 1000 *
3477 (RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
3478 dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
3480 mutex_init(&dev_priv->perf.metrics_lock);
3481 idr_init(&dev_priv->perf.metrics_idr);
3483 dev_priv->perf.initialized = true;
3487 static int destroy_config(int id, void *p, void *data)
3489 struct drm_i915_private *dev_priv = data;
3490 struct i915_oa_config *oa_config = p;
3492 put_oa_config(dev_priv, oa_config);
3498 * i915_perf_fini - Counter part to i915_perf_init()
3499 * @dev_priv: i915 device instance
3501 void i915_perf_fini(struct drm_i915_private *dev_priv)
3503 if (!dev_priv->perf.initialized)
3506 idr_for_each(&dev_priv->perf.metrics_idr, destroy_config, dev_priv);
3507 idr_destroy(&dev_priv->perf.metrics_idr);
3509 unregister_sysctl_table(dev_priv->perf.sysctl_header);
3511 memset(&dev_priv->perf.oa.ops, 0, sizeof(dev_priv->perf.oa.ops));
3513 dev_priv->perf.initialized = false;