1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * DOC: The i915 register macro definition style guide
31 * Follow the style described here for new macros, and while changing existing
32 * macros. Do **not** mass change existing definitions just to update the style.
37 * Keep helper macros near the top. For example, _PIPE() and friends.
39 * Prefix macros that generally should not be used outside of this file with
40 * underscore '_'. For example, _PIPE() and friends, single instances of
41 * registers that are defined solely for the use by function-like macros.
43 * Avoid using the underscore prefixed macros outside of this file. There are
44 * exceptions, but keep them to a minimum.
46 * There are two basic types of register definitions: Single registers and
47 * register groups. Register groups are registers which have two or more
48 * instances, for example one per pipe, port, transcoder, etc. Register groups
49 * should be defined using function-like macros.
51 * For single registers, define the register offset first, followed by register
54 * For register groups, define the register instance offsets first, prefixed
55 * with underscore, followed by a function-like macro choosing the right
56 * instance based on the parameter, followed by register contents.
58 * Define the register contents (i.e. bit and bit field macros) from most
59 * significant to least significant bit. Indent the register content macros
60 * using two extra spaces between ``#define`` and the macro name.
62 * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
63 * contents so that they are already shifted in place, and can be directly
64 * OR'd. For convenience, function-like macros may be used to define bit fields,
65 * but do note that the macros may be needed to read as well as write the
68 * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
69 * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
72 * Group the register and its contents together without blank lines, separate
73 * from other registers and their contents with one blank line.
75 * Indent macro values from macro names using TABs. Align values vertically. Use
76 * braces in macro values as needed to avoid unintended precedence after macro
77 * substitution. Use spaces in macro values according to kernel coding
78 * style. Use lower case in hexadecimal values.
83 * Try to name registers according to the specs. If the register name changes in
84 * the specs from platform to another, stick to the original name.
86 * Try to re-use existing register macro definitions. Only add new macros for
87 * new register offsets, or when the register contents have changed enough to
88 * warrant a full redefinition.
90 * When a register macro changes for a new platform, prefix the new macro using
91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
92 * prefix signifies the start platform/generation using the register.
94 * When a bit (field) macro changes or gets added for a new platform, while
95 * retaining the existing register macro, add a platform acronym or generation
96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
101 * (Note that the values in the example are indented using spaces instead of
102 * TABs to avoid misalignment in generated documentation. Use TABs in the
105 * #define _FOO_A 0xf000
106 * #define _FOO_B 0xf001
107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
108 * #define FOO_ENABLE (1 << 31)
109 * #define FOO_MODE_MASK (0xf << 16)
110 * #define FOO_MODE_SHIFT 16
111 * #define FOO_MODE_BAR (0 << 16)
112 * #define FOO_MODE_BAZ (1 << 16)
113 * #define FOO_MODE_QUX_SNB (2 << 16)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
123 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
125 #define INVALID_MMIO_REG _MMIO(0)
127 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
132 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
134 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
137 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
139 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
142 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
144 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
146 #define _PLANE(plane, a, b) _PIPE(plane, a, b)
147 #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
148 #define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
149 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
150 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
151 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
152 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
153 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
154 #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
155 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
156 #define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
157 #define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \
158 _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
159 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
160 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
162 #define _MASKED_FIELD(mask, value) ({ \
163 if (__builtin_constant_p(mask)) \
164 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
165 if (__builtin_constant_p(value)) \
166 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
167 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
168 BUILD_BUG_ON_MSG((value) & ~(mask), \
169 "Incorrect value for mask"); \
170 (mask) << 16 | (value); })
171 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
172 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
187 #define RENDER_CLASS 0
188 #define VIDEO_DECODE_CLASS 1
189 #define VIDEO_ENHANCEMENT_CLASS 2
190 #define COPY_ENGINE_CLASS 3
191 #define OTHER_CLASS 4
192 #define MAX_ENGINE_CLASS 4
194 #define MAX_ENGINE_INSTANCE 3
196 /* PCI config space */
198 #define MCHBAR_I915 0x44
199 #define MCHBAR_I965 0x48
200 #define MCHBAR_SIZE (4 * 4096)
203 #define DEVEN_MCHBAR_EN (1 << 28)
205 /* BSM in include/drm/i915_drm.h */
207 #define HPLLCC 0xc0 /* 85x only */
208 #define GC_CLOCK_CONTROL_MASK (0x7 << 0)
209 #define GC_CLOCK_133_200 (0 << 0)
210 #define GC_CLOCK_100_200 (1 << 0)
211 #define GC_CLOCK_100_133 (2 << 0)
212 #define GC_CLOCK_133_266 (3 << 0)
213 #define GC_CLOCK_133_200_2 (4 << 0)
214 #define GC_CLOCK_133_266_2 (5 << 0)
215 #define GC_CLOCK_166_266 (6 << 0)
216 #define GC_CLOCK_166_250 (7 << 0)
218 #define I915_GDRST 0xc0 /* PCI config register */
219 #define GRDOM_FULL (0 << 2)
220 #define GRDOM_RENDER (1 << 2)
221 #define GRDOM_MEDIA (3 << 2)
222 #define GRDOM_MASK (3 << 2)
223 #define GRDOM_RESET_STATUS (1 << 1)
224 #define GRDOM_RESET_ENABLE (1 << 0)
226 /* BSpec only has register offset, PCI device and bit found empirically */
227 #define I830_CLOCK_GATE 0xc8 /* device 0 */
228 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
230 #define GCDGMBUS 0xcc
233 #define GCFGC 0xf0 /* 915+ only */
234 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
235 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
236 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
237 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
238 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
239 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
240 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
241 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
242 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
243 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
244 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
245 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
246 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
247 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
248 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
249 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
250 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
251 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
252 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
253 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
254 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
255 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
256 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
257 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
258 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
259 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
260 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
261 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
262 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
268 #define SWSCI_SCISEL (1 << 15)
269 #define SWSCI_GSSCIE (1 << 0)
271 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
274 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
275 #define ILK_GRDOM_FULL (0<<1)
276 #define ILK_GRDOM_RENDER (1<<1)
277 #define ILK_GRDOM_MEDIA (3<<1)
278 #define ILK_GRDOM_MASK (3<<1)
279 #define ILK_GRDOM_RESET_ENABLE (1<<0)
281 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
282 #define GEN6_MBC_SNPCR_SHIFT 21
283 #define GEN6_MBC_SNPCR_MASK (3<<21)
284 #define GEN6_MBC_SNPCR_MAX (0<<21)
285 #define GEN6_MBC_SNPCR_MED (1<<21)
286 #define GEN6_MBC_SNPCR_LOW (2<<21)
287 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
289 #define VLV_G3DCTL _MMIO(0x9024)
290 #define VLV_GSCKGCTL _MMIO(0x9028)
292 #define GEN6_MBCTL _MMIO(0x0907c)
293 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
294 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
295 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
296 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
297 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
299 #define GEN6_GDRST _MMIO(0x941c)
300 #define GEN6_GRDOM_FULL (1 << 0)
301 #define GEN6_GRDOM_RENDER (1 << 1)
302 #define GEN6_GRDOM_MEDIA (1 << 2)
303 #define GEN6_GRDOM_BLT (1 << 3)
304 #define GEN6_GRDOM_VECS (1 << 4)
305 #define GEN9_GRDOM_GUC (1 << 5)
306 #define GEN8_GRDOM_MEDIA2 (1 << 7)
308 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228)
309 #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518)
310 #define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base+0x220)
311 #define PP_DIR_DCLV_2G 0xffffffff
313 #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4)
314 #define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8)
316 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
317 #define GEN8_RPCS_ENABLE (1 << 31)
318 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
319 #define GEN8_RPCS_S_CNT_SHIFT 15
320 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
321 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
322 #define GEN8_RPCS_SS_CNT_SHIFT 8
323 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
324 #define GEN8_RPCS_EU_MAX_SHIFT 4
325 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
326 #define GEN8_RPCS_EU_MIN_SHIFT 0
327 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
329 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
331 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
332 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
333 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
334 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
336 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
337 #define HSW_RCS_CONTEXT_ENABLE (1 << 7)
338 #define HSW_RCS_INHIBIT (1 << 8)
340 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
341 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
342 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
343 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
344 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
345 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
346 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
347 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
348 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
349 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
351 #define GAM_ECOCHK _MMIO(0x4090)
352 #define BDW_DISABLE_HDC_INVALIDATION (1<<25)
353 #define ECOCHK_SNB_BIT (1<<10)
354 #define ECOCHK_DIS_TLB (1<<8)
355 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
356 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
357 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
358 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
359 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
360 #define ECOCHK_PPGTT_UC_HSW (0x1<<3)
361 #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
362 #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
364 #define GAC_ECO_BITS _MMIO(0x14090)
365 #define ECOBITS_SNB_BIT (1<<13)
366 #define ECOBITS_PPGTT_CACHE64B (3<<8)
367 #define ECOBITS_PPGTT_CACHE4B (0<<8)
369 #define GAB_CTL _MMIO(0x24000)
370 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
372 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
373 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
374 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
375 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
376 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
377 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
378 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
379 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
380 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
381 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
382 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
383 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
384 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
385 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
386 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
387 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
388 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
392 #define VGA_ST01_MDA 0x3ba
393 #define VGA_ST01_CGA 0x3da
395 #define _VGA_MSR_WRITE _MMIO(0x3c2)
396 #define VGA_MSR_WRITE 0x3c2
397 #define VGA_MSR_READ 0x3cc
398 #define VGA_MSR_MEM_EN (1<<1)
399 #define VGA_MSR_CGA_MODE (1<<0)
401 #define VGA_SR_INDEX 0x3c4
403 #define VGA_SR_DATA 0x3c5
405 #define VGA_AR_INDEX 0x3c0
406 #define VGA_AR_VID_EN (1<<5)
407 #define VGA_AR_DATA_WRITE 0x3c0
408 #define VGA_AR_DATA_READ 0x3c1
410 #define VGA_GR_INDEX 0x3ce
411 #define VGA_GR_DATA 0x3cf
413 #define VGA_GR_MEM_READ_MODE_SHIFT 3
414 #define VGA_GR_MEM_READ_MODE_PLANE 1
416 #define VGA_GR_MEM_MODE_MASK 0xc
417 #define VGA_GR_MEM_MODE_SHIFT 2
418 #define VGA_GR_MEM_A0000_AFFFF 0
419 #define VGA_GR_MEM_A0000_BFFFF 1
420 #define VGA_GR_MEM_B0000_B7FFF 2
421 #define VGA_GR_MEM_B0000_BFFFF 3
423 #define VGA_DACMASK 0x3c6
424 #define VGA_DACRX 0x3c7
425 #define VGA_DACWX 0x3c8
426 #define VGA_DACDATA 0x3c9
428 #define VGA_CR_INDEX_MDA 0x3b4
429 #define VGA_CR_DATA_MDA 0x3b5
430 #define VGA_CR_INDEX_CGA 0x3d4
431 #define VGA_CR_DATA_CGA 0x3d5
434 * Instruction field definitions used by the command parser
436 #define INSTR_CLIENT_SHIFT 29
437 #define INSTR_MI_CLIENT 0x0
438 #define INSTR_BC_CLIENT 0x2
439 #define INSTR_RC_CLIENT 0x3
440 #define INSTR_SUBCLIENT_SHIFT 27
441 #define INSTR_SUBCLIENT_MASK 0x18000000
442 #define INSTR_MEDIA_SUBCLIENT 0x2
443 #define INSTR_26_TO_24_MASK 0x7000000
444 #define INSTR_26_TO_24_SHIFT 24
447 * Memory interface instructions used by the kernel
449 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
450 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
451 #define MI_GLOBAL_GTT (1<<22)
453 #define MI_NOOP MI_INSTR(0, 0)
454 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
455 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
456 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
457 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
458 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
459 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
460 #define MI_FLUSH MI_INSTR(0x04, 0)
461 #define MI_READ_FLUSH (1 << 0)
462 #define MI_EXE_FLUSH (1 << 1)
463 #define MI_NO_WRITE_FLUSH (1 << 2)
464 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
465 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
466 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
467 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
468 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
469 #define MI_ARB_ENABLE (1<<0)
470 #define MI_ARB_DISABLE (0<<0)
471 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
472 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
473 #define MI_SUSPEND_FLUSH_EN (1<<0)
474 #define MI_SET_APPID MI_INSTR(0x0e, 0)
475 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
476 #define MI_OVERLAY_CONTINUE (0x0<<21)
477 #define MI_OVERLAY_ON (0x1<<21)
478 #define MI_OVERLAY_OFF (0x2<<21)
479 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
480 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
481 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
482 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
483 /* IVB has funny definitions for which plane to flip. */
484 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
485 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
486 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
487 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
488 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
489 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
491 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
492 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
493 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
494 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
495 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
496 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
497 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
498 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
499 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
500 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
501 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
502 #define MI_SEMAPHORE_UPDATE (1<<21)
503 #define MI_SEMAPHORE_COMPARE (1<<20)
504 #define MI_SEMAPHORE_REGISTER (1<<18)
505 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
506 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
507 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
508 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
509 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
510 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
511 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
512 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
513 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
514 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
515 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
516 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
517 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
518 #define MI_SEMAPHORE_SYNC_MASK (3<<16)
519 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
520 #define MI_MM_SPACE_GTT (1<<8)
521 #define MI_MM_SPACE_PHYSICAL (0<<8)
522 #define MI_SAVE_EXT_STATE_EN (1<<3)
523 #define MI_RESTORE_EXT_STATE_EN (1<<2)
524 #define MI_FORCE_RESTORE (1<<1)
525 #define MI_RESTORE_INHIBIT (1<<0)
526 #define HSW_MI_RS_SAVE_STATE_EN (1<<3)
527 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
528 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
529 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
530 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
531 #define MI_SEMAPHORE_POLL (1<<15)
532 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
533 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
534 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
535 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
536 #define MI_USE_GGTT (1 << 22) /* g4x+ */
537 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
538 #define MI_STORE_DWORD_INDEX_SHIFT 2
539 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
540 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
541 * simply ignores the register load under certain conditions.
542 * - One can actually load arbitrary many arbitrary registers: Simply issue x
543 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
545 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
546 #define MI_LRI_FORCE_POSTED (1<<12)
547 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
548 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
549 #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
550 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
551 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
552 #define MI_INVALIDATE_TLB (1<<18)
553 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
554 #define MI_FLUSH_DW_OP_MASK (3<<14)
555 #define MI_FLUSH_DW_NOTIFY (1<<8)
556 #define MI_INVALIDATE_BSD (1<<7)
557 #define MI_FLUSH_DW_USE_GTT (1<<2)
558 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
559 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
560 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
561 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
562 #define MI_BATCH_NON_SECURE (1)
563 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
564 #define MI_BATCH_NON_SECURE_I965 (1<<8)
565 #define MI_BATCH_PPGTT_HSW (1<<8)
566 #define MI_BATCH_NON_SECURE_HSW (1<<13)
567 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
568 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
569 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
570 #define MI_BATCH_RESOURCE_STREAMER (1<<10)
572 #define MI_PREDICATE_SRC0 _MMIO(0x2400)
573 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
574 #define MI_PREDICATE_SRC1 _MMIO(0x2408)
575 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
577 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
578 #define LOWER_SLICE_ENABLED (1<<0)
579 #define LOWER_SLICE_DISABLED (0<<0)
582 * 3D instructions used by the kernel
584 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
586 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
587 #define GEN9_MEDIA_POOL_ENABLE (1 << 31)
588 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
589 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
590 #define SC_UPDATE_SCISSOR (0x1<<1)
591 #define SC_ENABLE_MASK (0x1<<0)
592 #define SC_ENABLE (0x1<<0)
593 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
594 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
595 #define SCI_YMIN_MASK (0xffff<<16)
596 #define SCI_XMIN_MASK (0xffff<<0)
597 #define SCI_YMAX_MASK (0xffff<<16)
598 #define SCI_XMAX_MASK (0xffff<<0)
599 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
600 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
601 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
602 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
603 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
604 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
605 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
606 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
607 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
609 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
610 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
611 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
612 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
613 #define BLT_WRITE_A (2<<20)
614 #define BLT_WRITE_RGB (1<<20)
615 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
616 #define BLT_DEPTH_8 (0<<24)
617 #define BLT_DEPTH_16_565 (1<<24)
618 #define BLT_DEPTH_16_1555 (2<<24)
619 #define BLT_DEPTH_32 (3<<24)
620 #define BLT_ROP_SRC_COPY (0xcc<<16)
621 #define BLT_ROP_COLOR_COPY (0xf0<<16)
622 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
623 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
624 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
625 #define ASYNC_FLIP (1<<22)
626 #define DISPLAY_PLANE_A (0<<20)
627 #define DISPLAY_PLANE_B (1<<20)
628 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
629 #define PIPE_CONTROL_FLUSH_L3 (1<<27)
630 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
631 #define PIPE_CONTROL_MMIO_WRITE (1<<23)
632 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
633 #define PIPE_CONTROL_CS_STALL (1<<20)
634 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
635 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
636 #define PIPE_CONTROL_QW_WRITE (1<<14)
637 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
638 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
639 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
640 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
641 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
642 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
643 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
644 #define PIPE_CONTROL_NOTIFY (1<<8)
645 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
646 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
647 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
648 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
649 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
650 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
651 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
652 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
655 * Commands used only by the command parser
657 #define MI_SET_PREDICATE MI_INSTR(0x01, 0)
658 #define MI_ARB_CHECK MI_INSTR(0x05, 0)
659 #define MI_RS_CONTROL MI_INSTR(0x06, 0)
660 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
661 #define MI_PREDICATE MI_INSTR(0x0C, 0)
662 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
663 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
664 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
665 #define MI_URB_CLEAR MI_INSTR(0x19, 0)
666 #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
667 #define MI_CLFLUSH MI_INSTR(0x27, 0)
668 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
669 #define MI_REPORT_PERF_COUNT_GGTT (1<<0)
670 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
671 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
672 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
673 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
674 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
676 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
677 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
678 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
679 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
680 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
681 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
682 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
683 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
684 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
685 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
686 #define GFX_OP_3DSTATE_SO_DECL_LIST \
687 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
689 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
690 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
691 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
692 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
693 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
694 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
695 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
696 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
697 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
698 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
700 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
702 #define COLOR_BLT ((0x2<<29)|(0x40<<22))
703 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
706 * Registers used only by the command parser
708 #define BCS_SWCTRL _MMIO(0x22200)
710 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
711 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
712 #define HS_INVOCATION_COUNT _MMIO(0x2300)
713 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
714 #define DS_INVOCATION_COUNT _MMIO(0x2308)
715 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
716 #define IA_VERTICES_COUNT _MMIO(0x2310)
717 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
718 #define IA_PRIMITIVES_COUNT _MMIO(0x2318)
719 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
720 #define VS_INVOCATION_COUNT _MMIO(0x2320)
721 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
722 #define GS_INVOCATION_COUNT _MMIO(0x2328)
723 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
724 #define GS_PRIMITIVES_COUNT _MMIO(0x2330)
725 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
726 #define CL_INVOCATION_COUNT _MMIO(0x2338)
727 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
728 #define CL_PRIMITIVES_COUNT _MMIO(0x2340)
729 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
730 #define PS_INVOCATION_COUNT _MMIO(0x2348)
731 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
732 #define PS_DEPTH_COUNT _MMIO(0x2350)
733 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
735 /* There are the 4 64-bit counter registers, one for each stream output */
736 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
737 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
739 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
740 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
742 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
743 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
744 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
745 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
746 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
747 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
749 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
750 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
751 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
753 /* There are the 16 64-bit CS General Purpose Registers */
754 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
755 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
757 #define GEN7_OACONTROL _MMIO(0x2360)
758 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
759 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
760 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
761 #define GEN7_OACONTROL_TIMER_ENABLE (1<<5)
762 #define GEN7_OACONTROL_FORMAT_A13 (0<<2)
763 #define GEN7_OACONTROL_FORMAT_A29 (1<<2)
764 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2<<2)
765 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3<<2)
766 #define GEN7_OACONTROL_FORMAT_B4_C8 (4<<2)
767 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5<<2)
768 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6<<2)
769 #define GEN7_OACONTROL_FORMAT_C4_B8 (7<<2)
770 #define GEN7_OACONTROL_FORMAT_SHIFT 2
771 #define GEN7_OACONTROL_PER_CTX_ENABLE (1<<1)
772 #define GEN7_OACONTROL_ENABLE (1<<0)
774 #define GEN8_OACTXID _MMIO(0x2364)
776 #define GEN8_OA_DEBUG _MMIO(0x2B04)
777 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1<<5)
778 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1<<6)
779 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1<<2)
780 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1<<1)
782 #define GEN8_OACONTROL _MMIO(0x2B00)
783 #define GEN8_OA_REPORT_FORMAT_A12 (0<<2)
784 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2<<2)
785 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5<<2)
786 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7<<2)
787 #define GEN8_OA_REPORT_FORMAT_SHIFT 2
788 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1<<1)
789 #define GEN8_OA_COUNTER_ENABLE (1<<0)
791 #define GEN8_OACTXCONTROL _MMIO(0x2360)
792 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F
793 #define GEN8_OA_TIMER_PERIOD_SHIFT 2
794 #define GEN8_OA_TIMER_ENABLE (1<<1)
795 #define GEN8_OA_COUNTER_RESUME (1<<0)
797 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
798 #define GEN7_OABUFFER_OVERRUN_DISABLE (1<<3)
799 #define GEN7_OABUFFER_EDGE_TRIGGER (1<<2)
800 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1<<1)
801 #define GEN7_OABUFFER_RESUME (1<<0)
803 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
804 #define GEN8_OABUFFER _MMIO(0x2b14)
806 #define GEN7_OASTATUS1 _MMIO(0x2364)
807 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
808 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1<<2)
809 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1<<1)
810 #define GEN7_OASTATUS1_REPORT_LOST (1<<0)
812 #define GEN7_OASTATUS2 _MMIO(0x2368)
813 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
815 #define GEN8_OASTATUS _MMIO(0x2b08)
816 #define GEN8_OASTATUS_OVERRUN_STATUS (1<<3)
817 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1<<2)
818 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1<<1)
819 #define GEN8_OASTATUS_REPORT_LOST (1<<0)
821 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
822 #define GEN8_OAHEADPTR_MASK 0xffffffc0
823 #define GEN8_OATAILPTR _MMIO(0x2B10)
824 #define GEN8_OATAILPTR_MASK 0xffffffc0
826 #define OABUFFER_SIZE_128K (0<<3)
827 #define OABUFFER_SIZE_256K (1<<3)
828 #define OABUFFER_SIZE_512K (2<<3)
829 #define OABUFFER_SIZE_1M (3<<3)
830 #define OABUFFER_SIZE_2M (4<<3)
831 #define OABUFFER_SIZE_4M (5<<3)
832 #define OABUFFER_SIZE_8M (6<<3)
833 #define OABUFFER_SIZE_16M (7<<3)
835 #define OA_MEM_SELECT_GGTT (1<<0)
838 * Flexible, Aggregate EU Counter Registers.
839 * Note: these aren't contiguous
841 #define EU_PERF_CNTL0 _MMIO(0xe458)
842 #define EU_PERF_CNTL1 _MMIO(0xe558)
843 #define EU_PERF_CNTL2 _MMIO(0xe658)
844 #define EU_PERF_CNTL3 _MMIO(0xe758)
845 #define EU_PERF_CNTL4 _MMIO(0xe45c)
846 #define EU_PERF_CNTL5 _MMIO(0xe55c)
847 #define EU_PERF_CNTL6 _MMIO(0xe65c)
853 #define OASTARTTRIG1 _MMIO(0x2710)
854 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
855 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff
857 #define OASTARTTRIG2 _MMIO(0x2714)
858 #define OASTARTTRIG2_INVERT_A_0 (1<<0)
859 #define OASTARTTRIG2_INVERT_A_1 (1<<1)
860 #define OASTARTTRIG2_INVERT_A_2 (1<<2)
861 #define OASTARTTRIG2_INVERT_A_3 (1<<3)
862 #define OASTARTTRIG2_INVERT_A_4 (1<<4)
863 #define OASTARTTRIG2_INVERT_A_5 (1<<5)
864 #define OASTARTTRIG2_INVERT_A_6 (1<<6)
865 #define OASTARTTRIG2_INVERT_A_7 (1<<7)
866 #define OASTARTTRIG2_INVERT_A_8 (1<<8)
867 #define OASTARTTRIG2_INVERT_A_9 (1<<9)
868 #define OASTARTTRIG2_INVERT_A_10 (1<<10)
869 #define OASTARTTRIG2_INVERT_A_11 (1<<11)
870 #define OASTARTTRIG2_INVERT_A_12 (1<<12)
871 #define OASTARTTRIG2_INVERT_A_13 (1<<13)
872 #define OASTARTTRIG2_INVERT_A_14 (1<<14)
873 #define OASTARTTRIG2_INVERT_A_15 (1<<15)
874 #define OASTARTTRIG2_INVERT_B_0 (1<<16)
875 #define OASTARTTRIG2_INVERT_B_1 (1<<17)
876 #define OASTARTTRIG2_INVERT_B_2 (1<<18)
877 #define OASTARTTRIG2_INVERT_B_3 (1<<19)
878 #define OASTARTTRIG2_INVERT_C_0 (1<<20)
879 #define OASTARTTRIG2_INVERT_C_1 (1<<21)
880 #define OASTARTTRIG2_INVERT_D_0 (1<<22)
881 #define OASTARTTRIG2_THRESHOLD_ENABLE (1<<23)
882 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1<<24)
883 #define OASTARTTRIG2_EVENT_SELECT_0 (1<<28)
884 #define OASTARTTRIG2_EVENT_SELECT_1 (1<<29)
885 #define OASTARTTRIG2_EVENT_SELECT_2 (1<<30)
886 #define OASTARTTRIG2_EVENT_SELECT_3 (1<<31)
888 #define OASTARTTRIG3 _MMIO(0x2718)
889 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf
890 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
891 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
892 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
893 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
894 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
895 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
896 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
897 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
899 #define OASTARTTRIG4 _MMIO(0x271c)
900 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf
901 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
902 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
903 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
904 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
905 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
906 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
907 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
908 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
910 #define OASTARTTRIG5 _MMIO(0x2720)
911 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
912 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff
914 #define OASTARTTRIG6 _MMIO(0x2724)
915 #define OASTARTTRIG6_INVERT_A_0 (1<<0)
916 #define OASTARTTRIG6_INVERT_A_1 (1<<1)
917 #define OASTARTTRIG6_INVERT_A_2 (1<<2)
918 #define OASTARTTRIG6_INVERT_A_3 (1<<3)
919 #define OASTARTTRIG6_INVERT_A_4 (1<<4)
920 #define OASTARTTRIG6_INVERT_A_5 (1<<5)
921 #define OASTARTTRIG6_INVERT_A_6 (1<<6)
922 #define OASTARTTRIG6_INVERT_A_7 (1<<7)
923 #define OASTARTTRIG6_INVERT_A_8 (1<<8)
924 #define OASTARTTRIG6_INVERT_A_9 (1<<9)
925 #define OASTARTTRIG6_INVERT_A_10 (1<<10)
926 #define OASTARTTRIG6_INVERT_A_11 (1<<11)
927 #define OASTARTTRIG6_INVERT_A_12 (1<<12)
928 #define OASTARTTRIG6_INVERT_A_13 (1<<13)
929 #define OASTARTTRIG6_INVERT_A_14 (1<<14)
930 #define OASTARTTRIG6_INVERT_A_15 (1<<15)
931 #define OASTARTTRIG6_INVERT_B_0 (1<<16)
932 #define OASTARTTRIG6_INVERT_B_1 (1<<17)
933 #define OASTARTTRIG6_INVERT_B_2 (1<<18)
934 #define OASTARTTRIG6_INVERT_B_3 (1<<19)
935 #define OASTARTTRIG6_INVERT_C_0 (1<<20)
936 #define OASTARTTRIG6_INVERT_C_1 (1<<21)
937 #define OASTARTTRIG6_INVERT_D_0 (1<<22)
938 #define OASTARTTRIG6_THRESHOLD_ENABLE (1<<23)
939 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1<<24)
940 #define OASTARTTRIG6_EVENT_SELECT_4 (1<<28)
941 #define OASTARTTRIG6_EVENT_SELECT_5 (1<<29)
942 #define OASTARTTRIG6_EVENT_SELECT_6 (1<<30)
943 #define OASTARTTRIG6_EVENT_SELECT_7 (1<<31)
945 #define OASTARTTRIG7 _MMIO(0x2728)
946 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf
947 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
948 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
949 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
950 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
951 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
952 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
953 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
954 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
956 #define OASTARTTRIG8 _MMIO(0x272c)
957 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf
958 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
959 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
960 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
961 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
962 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
963 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
964 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
965 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
967 #define OAREPORTTRIG1 _MMIO(0x2740)
968 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
969 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
971 #define OAREPORTTRIG2 _MMIO(0x2744)
972 #define OAREPORTTRIG2_INVERT_A_0 (1<<0)
973 #define OAREPORTTRIG2_INVERT_A_1 (1<<1)
974 #define OAREPORTTRIG2_INVERT_A_2 (1<<2)
975 #define OAREPORTTRIG2_INVERT_A_3 (1<<3)
976 #define OAREPORTTRIG2_INVERT_A_4 (1<<4)
977 #define OAREPORTTRIG2_INVERT_A_5 (1<<5)
978 #define OAREPORTTRIG2_INVERT_A_6 (1<<6)
979 #define OAREPORTTRIG2_INVERT_A_7 (1<<7)
980 #define OAREPORTTRIG2_INVERT_A_8 (1<<8)
981 #define OAREPORTTRIG2_INVERT_A_9 (1<<9)
982 #define OAREPORTTRIG2_INVERT_A_10 (1<<10)
983 #define OAREPORTTRIG2_INVERT_A_11 (1<<11)
984 #define OAREPORTTRIG2_INVERT_A_12 (1<<12)
985 #define OAREPORTTRIG2_INVERT_A_13 (1<<13)
986 #define OAREPORTTRIG2_INVERT_A_14 (1<<14)
987 #define OAREPORTTRIG2_INVERT_A_15 (1<<15)
988 #define OAREPORTTRIG2_INVERT_B_0 (1<<16)
989 #define OAREPORTTRIG2_INVERT_B_1 (1<<17)
990 #define OAREPORTTRIG2_INVERT_B_2 (1<<18)
991 #define OAREPORTTRIG2_INVERT_B_3 (1<<19)
992 #define OAREPORTTRIG2_INVERT_C_0 (1<<20)
993 #define OAREPORTTRIG2_INVERT_C_1 (1<<21)
994 #define OAREPORTTRIG2_INVERT_D_0 (1<<22)
995 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23)
996 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31)
998 #define OAREPORTTRIG3 _MMIO(0x2748)
999 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
1000 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
1001 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
1002 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
1003 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
1004 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
1005 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
1006 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
1007 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
1009 #define OAREPORTTRIG4 _MMIO(0x274c)
1010 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
1011 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
1012 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
1013 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
1014 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
1015 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
1016 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
1017 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
1018 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
1020 #define OAREPORTTRIG5 _MMIO(0x2750)
1021 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
1022 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
1024 #define OAREPORTTRIG6 _MMIO(0x2754)
1025 #define OAREPORTTRIG6_INVERT_A_0 (1<<0)
1026 #define OAREPORTTRIG6_INVERT_A_1 (1<<1)
1027 #define OAREPORTTRIG6_INVERT_A_2 (1<<2)
1028 #define OAREPORTTRIG6_INVERT_A_3 (1<<3)
1029 #define OAREPORTTRIG6_INVERT_A_4 (1<<4)
1030 #define OAREPORTTRIG6_INVERT_A_5 (1<<5)
1031 #define OAREPORTTRIG6_INVERT_A_6 (1<<6)
1032 #define OAREPORTTRIG6_INVERT_A_7 (1<<7)
1033 #define OAREPORTTRIG6_INVERT_A_8 (1<<8)
1034 #define OAREPORTTRIG6_INVERT_A_9 (1<<9)
1035 #define OAREPORTTRIG6_INVERT_A_10 (1<<10)
1036 #define OAREPORTTRIG6_INVERT_A_11 (1<<11)
1037 #define OAREPORTTRIG6_INVERT_A_12 (1<<12)
1038 #define OAREPORTTRIG6_INVERT_A_13 (1<<13)
1039 #define OAREPORTTRIG6_INVERT_A_14 (1<<14)
1040 #define OAREPORTTRIG6_INVERT_A_15 (1<<15)
1041 #define OAREPORTTRIG6_INVERT_B_0 (1<<16)
1042 #define OAREPORTTRIG6_INVERT_B_1 (1<<17)
1043 #define OAREPORTTRIG6_INVERT_B_2 (1<<18)
1044 #define OAREPORTTRIG6_INVERT_B_3 (1<<19)
1045 #define OAREPORTTRIG6_INVERT_C_0 (1<<20)
1046 #define OAREPORTTRIG6_INVERT_C_1 (1<<21)
1047 #define OAREPORTTRIG6_INVERT_D_0 (1<<22)
1048 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23)
1049 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31)
1051 #define OAREPORTTRIG7 _MMIO(0x2758)
1052 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
1053 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
1054 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
1055 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
1056 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
1057 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
1058 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
1059 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
1060 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
1062 #define OAREPORTTRIG8 _MMIO(0x275c)
1063 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
1064 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
1065 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
1066 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
1067 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
1068 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
1069 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
1070 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
1071 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
1074 #define OACEC_COMPARE_LESS_OR_EQUAL 6
1075 #define OACEC_COMPARE_NOT_EQUAL 5
1076 #define OACEC_COMPARE_LESS_THAN 4
1077 #define OACEC_COMPARE_GREATER_OR_EQUAL 3
1078 #define OACEC_COMPARE_EQUAL 2
1079 #define OACEC_COMPARE_GREATER_THAN 1
1080 #define OACEC_COMPARE_ANY_EQUAL 0
1082 #define OACEC_COMPARE_VALUE_MASK 0xffff
1083 #define OACEC_COMPARE_VALUE_SHIFT 3
1085 #define OACEC_SELECT_NOA (0<<19)
1086 #define OACEC_SELECT_PREV (1<<19)
1087 #define OACEC_SELECT_BOOLEAN (2<<19)
1090 #define OACEC_MASK_MASK 0xffff
1091 #define OACEC_CONSIDERATIONS_MASK 0xffff
1092 #define OACEC_CONSIDERATIONS_SHIFT 16
1094 #define OACEC0_0 _MMIO(0x2770)
1095 #define OACEC0_1 _MMIO(0x2774)
1096 #define OACEC1_0 _MMIO(0x2778)
1097 #define OACEC1_1 _MMIO(0x277c)
1098 #define OACEC2_0 _MMIO(0x2780)
1099 #define OACEC2_1 _MMIO(0x2784)
1100 #define OACEC3_0 _MMIO(0x2788)
1101 #define OACEC3_1 _MMIO(0x278c)
1102 #define OACEC4_0 _MMIO(0x2790)
1103 #define OACEC4_1 _MMIO(0x2794)
1104 #define OACEC5_0 _MMIO(0x2798)
1105 #define OACEC5_1 _MMIO(0x279c)
1106 #define OACEC6_0 _MMIO(0x27a0)
1107 #define OACEC6_1 _MMIO(0x27a4)
1108 #define OACEC7_0 _MMIO(0x27a8)
1109 #define OACEC7_1 _MMIO(0x27ac)
1111 /* OA perf counters */
1112 #define OA_PERFCNT1_LO _MMIO(0x91B8)
1113 #define OA_PERFCNT1_HI _MMIO(0x91BC)
1114 #define OA_PERFCNT2_LO _MMIO(0x91C0)
1115 #define OA_PERFCNT2_HI _MMIO(0x91C4)
1116 #define OA_PERFCNT3_LO _MMIO(0x91C8)
1117 #define OA_PERFCNT3_HI _MMIO(0x91CC)
1118 #define OA_PERFCNT4_LO _MMIO(0x91D8)
1119 #define OA_PERFCNT4_HI _MMIO(0x91DC)
1121 #define OA_PERFMATRIX_LO _MMIO(0x91C8)
1122 #define OA_PERFMATRIX_HI _MMIO(0x91CC)
1124 /* RPM unit config (Gen8+) */
1125 #define RPM_CONFIG0 _MMIO(0x0D00)
1126 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1127 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1128 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1129 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
1130 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1131 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1133 #define RPM_CONFIG1 _MMIO(0x0D04)
1134 #define GEN10_GT_NOA_ENABLE (1 << 9)
1136 /* GPM unit config (Gen9+) */
1137 #define CTC_MODE _MMIO(0xA26C)
1138 #define CTC_SOURCE_PARAMETER_MASK 1
1139 #define CTC_SOURCE_CRYSTAL_CLOCK 0
1140 #define CTC_SOURCE_DIVIDE_LOGIC 1
1141 #define CTC_SHIFT_PARAMETER_SHIFT 1
1142 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1144 /* RCP unit config (Gen8+) */
1145 #define RCP_CONFIG _MMIO(0x0D08)
1148 #define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1149 #define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1150 #define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1151 #define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1152 #define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1153 #define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1154 #define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1155 #define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1156 #define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1157 #define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1159 #define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1162 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1164 #define MICRO_BP0_0 _MMIO(0x9800)
1165 #define MICRO_BP0_2 _MMIO(0x9804)
1166 #define MICRO_BP0_1 _MMIO(0x9808)
1168 #define MICRO_BP1_0 _MMIO(0x980C)
1169 #define MICRO_BP1_2 _MMIO(0x9810)
1170 #define MICRO_BP1_1 _MMIO(0x9814)
1172 #define MICRO_BP2_0 _MMIO(0x9818)
1173 #define MICRO_BP2_2 _MMIO(0x981C)
1174 #define MICRO_BP2_1 _MMIO(0x9820)
1176 #define MICRO_BP3_0 _MMIO(0x9824)
1177 #define MICRO_BP3_2 _MMIO(0x9828)
1178 #define MICRO_BP3_1 _MMIO(0x982C)
1180 #define MICRO_BP_TRIGGER _MMIO(0x9830)
1181 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1182 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1183 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1185 #define GDT_CHICKEN_BITS _MMIO(0x9840)
1186 #define GT_NOA_ENABLE 0x00000080
1188 #define NOA_DATA _MMIO(0x986C)
1189 #define NOA_WRITE _MMIO(0x9888)
1191 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1192 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
1193 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1198 #define DEBUG_RESET_I830 _MMIO(0x6070)
1199 #define DEBUG_RESET_FULL (1<<7)
1200 #define DEBUG_RESET_RENDER (1<<8)
1201 #define DEBUG_RESET_DISPLAY (1<<9)
1206 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
1207 #define IOSF_DEVFN_SHIFT 24
1208 #define IOSF_OPCODE_SHIFT 16
1209 #define IOSF_PORT_SHIFT 8
1210 #define IOSF_BYTE_ENABLES_SHIFT 4
1211 #define IOSF_BAR_SHIFT 1
1212 #define IOSF_SB_BUSY (1<<0)
1213 #define IOSF_PORT_BUNIT 0x03
1214 #define IOSF_PORT_PUNIT 0x04
1215 #define IOSF_PORT_NC 0x11
1216 #define IOSF_PORT_DPIO 0x12
1217 #define IOSF_PORT_GPIO_NC 0x13
1218 #define IOSF_PORT_CCK 0x14
1219 #define IOSF_PORT_DPIO_2 0x1a
1220 #define IOSF_PORT_FLISDSI 0x1b
1221 #define IOSF_PORT_GPIO_SC 0x48
1222 #define IOSF_PORT_GPIO_SUS 0xa8
1223 #define IOSF_PORT_CCU 0xa9
1224 #define CHV_IOSF_PORT_GPIO_N 0x13
1225 #define CHV_IOSF_PORT_GPIO_SE 0x48
1226 #define CHV_IOSF_PORT_GPIO_E 0xa8
1227 #define CHV_IOSF_PORT_GPIO_SW 0xb2
1228 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1229 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1231 /* See configdb bunit SB addr map */
1232 #define BUNIT_REG_BISOC 0x11
1234 #define PUNIT_REG_DSPFREQ 0x36
1235 #define DSPFREQSTAT_SHIFT_CHV 24
1236 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1237 #define DSPFREQGUAR_SHIFT_CHV 8
1238 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1239 #define DSPFREQSTAT_SHIFT 30
1240 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1241 #define DSPFREQGUAR_SHIFT 14
1242 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1243 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1244 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1245 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
1246 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1247 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1248 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1249 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1250 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1251 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1252 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1253 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1254 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1255 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1256 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1257 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1260 * i915_power_well_id:
1262 * Platform specific IDs used to look up power wells and - except for custom
1263 * power wells - to define request/status register flag bit positions. As such
1264 * the set of IDs on a given platform must be unique and except for custom
1265 * power wells their value must stay fixed.
1267 enum i915_power_well_id {
1270 * - custom power well
1272 I830_DISP_PW_PIPES = 0,
1276 * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
1277 * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
1279 PUNIT_POWER_WELL_RENDER = 0,
1280 PUNIT_POWER_WELL_MEDIA = 1,
1281 PUNIT_POWER_WELL_DISP2D = 3,
1282 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
1283 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
1284 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
1285 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
1286 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
1287 PUNIT_POWER_WELL_DPIO_RX0 = 10,
1288 PUNIT_POWER_WELL_DPIO_RX1 = 11,
1289 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
1290 /* - custom power well */
1291 CHV_DISP_PW_PIPE_A, /* 13 */
1295 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
1297 HSW_DISP_PW_GLOBAL = 15,
1301 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
1303 SKL_DISP_PW_MISC_IO = 0,
1304 SKL_DISP_PW_DDI_A_E,
1305 GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1306 CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1310 CNL_DISP_PW_DDI_F = 6,
1312 GLK_DISP_PW_AUX_A = 8,
1315 CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
1316 CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
1317 CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
1324 /* - custom power wells */
1328 GLK_DPIO_CMN_C, /* 19 */
1331 * Multiple platforms.
1332 * Must start following the highest ID of any platform.
1333 * - custom power wells
1335 I915_DISP_PW_ALWAYS_ON = 20,
1338 #define PUNIT_REG_PWRGT_CTRL 0x60
1339 #define PUNIT_REG_PWRGT_STATUS 0x61
1340 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
1341 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
1342 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
1343 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
1344 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
1346 #define PUNIT_REG_GPU_LFM 0xd3
1347 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
1348 #define PUNIT_REG_GPU_FREQ_STS 0xd8
1349 #define GPLLENABLE (1<<4)
1350 #define GENFREQSTATUS (1<<0)
1351 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1352 #define PUNIT_REG_CZ_TIMESTAMP 0xce
1354 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1355 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1357 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1358 #define FB_GFX_FREQ_FUSE_MASK 0xff
1359 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1360 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1361 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1363 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1364 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1366 #define PUNIT_REG_DDR_SETUP2 0x139
1367 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1368 #define FORCE_DDR_LOW_FREQ (1 << 1)
1369 #define FORCE_DDR_HIGH_FREQ (1 << 0)
1371 #define PUNIT_GPU_STATUS_REG 0xdb
1372 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1373 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1374 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1375 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1377 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1378 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1379 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1381 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1382 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1383 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1384 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1385 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1386 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1387 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1388 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1389 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1390 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1392 #define VLV_TURBO_SOC_OVERRIDE 0x04
1393 #define VLV_OVERRIDE_EN 1
1394 #define VLV_SOC_TDP_EN (1 << 1)
1395 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1396 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1398 /* vlv2 north clock has */
1399 #define CCK_FUSE_REG 0x8
1400 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
1401 #define CCK_REG_DSI_PLL_FUSE 0x44
1402 #define CCK_REG_DSI_PLL_CONTROL 0x48
1403 #define DSI_PLL_VCO_EN (1 << 31)
1404 #define DSI_PLL_LDO_GATE (1 << 30)
1405 #define DSI_PLL_P1_POST_DIV_SHIFT 17
1406 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1407 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1408 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1409 #define DSI_PLL_MUX_MASK (3 << 9)
1410 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1411 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1412 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1413 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1414 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1415 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1416 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1417 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1418 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1419 #define DSI_PLL_LOCK (1 << 0)
1420 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
1421 #define DSI_PLL_LFSR (1 << 31)
1422 #define DSI_PLL_FRACTION_EN (1 << 30)
1423 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
1424 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1425 #define DSI_PLL_USYNC_CNT_SHIFT 18
1426 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1427 #define DSI_PLL_N1_DIV_SHIFT 16
1428 #define DSI_PLL_N1_DIV_MASK (3 << 16)
1429 #define DSI_PLL_M1_DIV_SHIFT 0
1430 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1431 #define CCK_CZ_CLOCK_CONTROL 0x62
1432 #define CCK_GPLL_CLOCK_CONTROL 0x67
1433 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1434 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1435 #define CCK_TRUNK_FORCE_ON (1 << 17)
1436 #define CCK_TRUNK_FORCE_OFF (1 << 16)
1437 #define CCK_FREQUENCY_STATUS (0x1f << 8)
1438 #define CCK_FREQUENCY_STATUS_SHIFT 8
1439 #define CCK_FREQUENCY_VALUES (0x1f << 0)
1441 /* DPIO registers */
1442 #define DPIO_DEVFN 0
1444 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1445 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
1446 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
1447 #define DPIO_SFR_BYPASS (1<<1)
1448 #define DPIO_CMNRST (1<<0)
1450 #define DPIO_PHY(pipe) ((pipe) >> 1)
1451 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1454 * Per pipe/PLL DPIO regs
1456 #define _VLV_PLL_DW3_CH0 0x800c
1457 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
1458 #define DPIO_POST_DIV_DAC 0
1459 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1460 #define DPIO_POST_DIV_LVDS1 2
1461 #define DPIO_POST_DIV_LVDS2 3
1462 #define DPIO_K_SHIFT (24) /* 4 bits */
1463 #define DPIO_P1_SHIFT (21) /* 3 bits */
1464 #define DPIO_P2_SHIFT (16) /* 5 bits */
1465 #define DPIO_N_SHIFT (12) /* 4 bits */
1466 #define DPIO_ENABLE_CALIBRATION (1<<11)
1467 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1468 #define DPIO_M2DIV_MASK 0xff
1469 #define _VLV_PLL_DW3_CH1 0x802c
1470 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1472 #define _VLV_PLL_DW5_CH0 0x8014
1473 #define DPIO_REFSEL_OVERRIDE 27
1474 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1475 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1476 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
1477 #define DPIO_PLL_REFCLK_SEL_MASK 3
1478 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1479 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1480 #define _VLV_PLL_DW5_CH1 0x8034
1481 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1483 #define _VLV_PLL_DW7_CH0 0x801c
1484 #define _VLV_PLL_DW7_CH1 0x803c
1485 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1487 #define _VLV_PLL_DW8_CH0 0x8040
1488 #define _VLV_PLL_DW8_CH1 0x8060
1489 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1491 #define VLV_PLL_DW9_BCAST 0xc044
1492 #define _VLV_PLL_DW9_CH0 0x8044
1493 #define _VLV_PLL_DW9_CH1 0x8064
1494 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1496 #define _VLV_PLL_DW10_CH0 0x8048
1497 #define _VLV_PLL_DW10_CH1 0x8068
1498 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1500 #define _VLV_PLL_DW11_CH0 0x804c
1501 #define _VLV_PLL_DW11_CH1 0x806c
1502 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1504 /* Spec for ref block start counts at DW10 */
1505 #define VLV_REF_DW13 0x80ac
1507 #define VLV_CMN_DW0 0x8100
1510 * Per DDI channel DPIO regs
1513 #define _VLV_PCS_DW0_CH0 0x8200
1514 #define _VLV_PCS_DW0_CH1 0x8400
1515 #define DPIO_PCS_TX_LANE2_RESET (1<<16)
1516 #define DPIO_PCS_TX_LANE1_RESET (1<<7)
1517 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
1518 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
1519 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1521 #define _VLV_PCS01_DW0_CH0 0x200
1522 #define _VLV_PCS23_DW0_CH0 0x400
1523 #define _VLV_PCS01_DW0_CH1 0x2600
1524 #define _VLV_PCS23_DW0_CH1 0x2800
1525 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1526 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1528 #define _VLV_PCS_DW1_CH0 0x8204
1529 #define _VLV_PCS_DW1_CH1 0x8404
1530 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
1531 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
1532 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
1533 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1534 #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
1535 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1537 #define _VLV_PCS01_DW1_CH0 0x204
1538 #define _VLV_PCS23_DW1_CH0 0x404
1539 #define _VLV_PCS01_DW1_CH1 0x2604
1540 #define _VLV_PCS23_DW1_CH1 0x2804
1541 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1542 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1544 #define _VLV_PCS_DW8_CH0 0x8220
1545 #define _VLV_PCS_DW8_CH1 0x8420
1546 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1547 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1548 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1550 #define _VLV_PCS01_DW8_CH0 0x0220
1551 #define _VLV_PCS23_DW8_CH0 0x0420
1552 #define _VLV_PCS01_DW8_CH1 0x2620
1553 #define _VLV_PCS23_DW8_CH1 0x2820
1554 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1555 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1557 #define _VLV_PCS_DW9_CH0 0x8224
1558 #define _VLV_PCS_DW9_CH1 0x8424
1559 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
1560 #define DPIO_PCS_TX2MARGIN_000 (0<<13)
1561 #define DPIO_PCS_TX2MARGIN_101 (1<<13)
1562 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
1563 #define DPIO_PCS_TX1MARGIN_000 (0<<10)
1564 #define DPIO_PCS_TX1MARGIN_101 (1<<10)
1565 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1567 #define _VLV_PCS01_DW9_CH0 0x224
1568 #define _VLV_PCS23_DW9_CH0 0x424
1569 #define _VLV_PCS01_DW9_CH1 0x2624
1570 #define _VLV_PCS23_DW9_CH1 0x2824
1571 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1572 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1574 #define _CHV_PCS_DW10_CH0 0x8228
1575 #define _CHV_PCS_DW10_CH1 0x8428
1576 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
1577 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
1578 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
1579 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
1580 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
1581 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
1582 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
1583 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
1584 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1586 #define _VLV_PCS01_DW10_CH0 0x0228
1587 #define _VLV_PCS23_DW10_CH0 0x0428
1588 #define _VLV_PCS01_DW10_CH1 0x2628
1589 #define _VLV_PCS23_DW10_CH1 0x2828
1590 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1591 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1593 #define _VLV_PCS_DW11_CH0 0x822c
1594 #define _VLV_PCS_DW11_CH1 0x842c
1595 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
1596 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
1597 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
1598 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
1599 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1601 #define _VLV_PCS01_DW11_CH0 0x022c
1602 #define _VLV_PCS23_DW11_CH0 0x042c
1603 #define _VLV_PCS01_DW11_CH1 0x262c
1604 #define _VLV_PCS23_DW11_CH1 0x282c
1605 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1606 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1608 #define _VLV_PCS01_DW12_CH0 0x0230
1609 #define _VLV_PCS23_DW12_CH0 0x0430
1610 #define _VLV_PCS01_DW12_CH1 0x2630
1611 #define _VLV_PCS23_DW12_CH1 0x2830
1612 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1613 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1615 #define _VLV_PCS_DW12_CH0 0x8230
1616 #define _VLV_PCS_DW12_CH1 0x8430
1617 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
1618 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
1619 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
1620 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
1621 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
1622 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1624 #define _VLV_PCS_DW14_CH0 0x8238
1625 #define _VLV_PCS_DW14_CH1 0x8438
1626 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1628 #define _VLV_PCS_DW23_CH0 0x825c
1629 #define _VLV_PCS_DW23_CH1 0x845c
1630 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1632 #define _VLV_TX_DW2_CH0 0x8288
1633 #define _VLV_TX_DW2_CH1 0x8488
1634 #define DPIO_SWING_MARGIN000_SHIFT 16
1635 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1636 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1637 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1639 #define _VLV_TX_DW3_CH0 0x828c
1640 #define _VLV_TX_DW3_CH1 0x848c
1641 /* The following bit for CHV phy */
1642 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
1643 #define DPIO_SWING_MARGIN101_SHIFT 16
1644 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1645 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1647 #define _VLV_TX_DW4_CH0 0x8290
1648 #define _VLV_TX_DW4_CH1 0x8490
1649 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
1650 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1651 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
1652 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1653 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1655 #define _VLV_TX3_DW4_CH0 0x690
1656 #define _VLV_TX3_DW4_CH1 0x2a90
1657 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1659 #define _VLV_TX_DW5_CH0 0x8294
1660 #define _VLV_TX_DW5_CH1 0x8494
1661 #define DPIO_TX_OCALINIT_EN (1<<31)
1662 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1664 #define _VLV_TX_DW11_CH0 0x82ac
1665 #define _VLV_TX_DW11_CH1 0x84ac
1666 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1668 #define _VLV_TX_DW14_CH0 0x82b8
1669 #define _VLV_TX_DW14_CH1 0x84b8
1670 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1672 /* CHV dpPhy registers */
1673 #define _CHV_PLL_DW0_CH0 0x8000
1674 #define _CHV_PLL_DW0_CH1 0x8180
1675 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1677 #define _CHV_PLL_DW1_CH0 0x8004
1678 #define _CHV_PLL_DW1_CH1 0x8184
1679 #define DPIO_CHV_N_DIV_SHIFT 8
1680 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1681 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1683 #define _CHV_PLL_DW2_CH0 0x8008
1684 #define _CHV_PLL_DW2_CH1 0x8188
1685 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1687 #define _CHV_PLL_DW3_CH0 0x800c
1688 #define _CHV_PLL_DW3_CH1 0x818c
1689 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1690 #define DPIO_CHV_FIRST_MOD (0 << 8)
1691 #define DPIO_CHV_SECOND_MOD (1 << 8)
1692 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1693 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1694 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1696 #define _CHV_PLL_DW6_CH0 0x8018
1697 #define _CHV_PLL_DW6_CH1 0x8198
1698 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1699 #define DPIO_CHV_INT_COEFF_SHIFT 8
1700 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1701 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1703 #define _CHV_PLL_DW8_CH0 0x8020
1704 #define _CHV_PLL_DW8_CH1 0x81A0
1705 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1706 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1707 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1709 #define _CHV_PLL_DW9_CH0 0x8024
1710 #define _CHV_PLL_DW9_CH1 0x81A4
1711 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1712 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1713 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1714 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1716 #define _CHV_CMN_DW0_CH0 0x8100
1717 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1718 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1719 #define DPIO_ALLDL_POWERDOWN (1 << 1)
1720 #define DPIO_ANYDL_POWERDOWN (1 << 0)
1722 #define _CHV_CMN_DW5_CH0 0x8114
1723 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1724 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1725 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1726 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1727 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1728 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1729 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1730 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1732 #define _CHV_CMN_DW13_CH0 0x8134
1733 #define _CHV_CMN_DW0_CH1 0x8080
1734 #define DPIO_CHV_S1_DIV_SHIFT 21
1735 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1736 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1737 #define DPIO_CHV_K_DIV_SHIFT 4
1738 #define DPIO_PLL_FREQLOCK (1 << 1)
1739 #define DPIO_PLL_LOCK (1 << 0)
1740 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1742 #define _CHV_CMN_DW14_CH0 0x8138
1743 #define _CHV_CMN_DW1_CH1 0x8084
1744 #define DPIO_AFC_RECAL (1 << 14)
1745 #define DPIO_DCLKP_EN (1 << 13)
1746 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1747 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1748 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1749 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1750 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1751 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1752 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1753 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1754 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1756 #define _CHV_CMN_DW19_CH0 0x814c
1757 #define _CHV_CMN_DW6_CH1 0x8098
1758 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1759 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1760 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1761 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1763 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1765 #define CHV_CMN_DW28 0x8170
1766 #define DPIO_CL1POWERDOWNEN (1 << 23)
1767 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1768 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1769 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1770 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1771 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1773 #define CHV_CMN_DW30 0x8178
1774 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1775 #define DPIO_LRC_BYPASS (1 << 3)
1777 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1778 (lane) * 0x200 + (offset))
1780 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1781 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1782 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1783 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1784 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1785 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1786 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1787 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1788 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1789 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1790 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1791 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1792 #define DPIO_FRC_LATENCY_SHFIT 8
1793 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1794 #define DPIO_UPAR_SHIFT 30
1796 /* BXT PHY registers */
1797 #define _BXT_PHY0_BASE 0x6C000
1798 #define _BXT_PHY1_BASE 0x162000
1799 #define _BXT_PHY2_BASE 0x163000
1800 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1804 #define _BXT_PHY(phy, reg) \
1805 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1807 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1808 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1809 (reg_ch1) - _BXT_PHY0_BASE))
1810 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1811 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1813 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1814 #define MIPIO_RST_CTRL (1 << 2)
1816 #define _BXT_PHY_CTL_DDI_A 0x64C00
1817 #define _BXT_PHY_CTL_DDI_B 0x64C10
1818 #define _BXT_PHY_CTL_DDI_C 0x64C20
1819 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1820 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1821 #define BXT_PHY_LANE_ENABLED (1 << 8)
1822 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1825 #define _PHY_CTL_FAMILY_EDP 0x64C80
1826 #define _PHY_CTL_FAMILY_DDI 0x64C90
1827 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1828 #define COMMON_RESET_DIS (1 << 31)
1829 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1830 _PHY_CTL_FAMILY_EDP, \
1831 _PHY_CTL_FAMILY_DDI_C)
1833 /* BXT PHY PLL registers */
1834 #define _PORT_PLL_A 0x46074
1835 #define _PORT_PLL_B 0x46078
1836 #define _PORT_PLL_C 0x4607c
1837 #define PORT_PLL_ENABLE (1 << 31)
1838 #define PORT_PLL_LOCK (1 << 30)
1839 #define PORT_PLL_REF_SEL (1 << 27)
1840 #define PORT_PLL_POWER_ENABLE (1 << 26)
1841 #define PORT_PLL_POWER_STATE (1 << 25)
1842 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1844 #define _PORT_PLL_EBB_0_A 0x162034
1845 #define _PORT_PLL_EBB_0_B 0x6C034
1846 #define _PORT_PLL_EBB_0_C 0x6C340
1847 #define PORT_PLL_P1_SHIFT 13
1848 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1849 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1850 #define PORT_PLL_P2_SHIFT 8
1851 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1852 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1853 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1854 _PORT_PLL_EBB_0_B, \
1857 #define _PORT_PLL_EBB_4_A 0x162038
1858 #define _PORT_PLL_EBB_4_B 0x6C038
1859 #define _PORT_PLL_EBB_4_C 0x6C344
1860 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1861 #define PORT_PLL_RECALIBRATE (1 << 14)
1862 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1863 _PORT_PLL_EBB_4_B, \
1866 #define _PORT_PLL_0_A 0x162100
1867 #define _PORT_PLL_0_B 0x6C100
1868 #define _PORT_PLL_0_C 0x6C380
1870 #define PORT_PLL_M2_MASK 0xFF
1872 #define PORT_PLL_N_SHIFT 8
1873 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1874 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1876 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1878 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1880 #define PORT_PLL_PROP_COEFF_MASK 0xF
1881 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1882 #define PORT_PLL_INT_COEFF(x) ((x) << 8)
1883 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1884 #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1886 #define PORT_PLL_TARGET_CNT_MASK 0x3FF
1888 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1889 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1891 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
1892 #define PORT_PLL_DCO_AMP_DEFAULT 15
1893 #define PORT_PLL_DCO_AMP_MASK 0x3c00
1894 #define PORT_PLL_DCO_AMP(x) ((x)<<10)
1895 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1898 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1901 /* BXT PHY common lane registers */
1902 #define _PORT_CL1CM_DW0_A 0x162000
1903 #define _PORT_CL1CM_DW0_BC 0x6C000
1904 #define PHY_POWER_GOOD (1 << 16)
1905 #define PHY_RESERVED (1 << 7)
1906 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1908 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1909 #define CL_POWER_DOWN_ENABLE (1 << 4)
1910 #define SUS_CLOCK_CONFIG (3 << 0)
1912 #define _ICL_PORT_CL_DW5_A 0x162014
1913 #define _ICL_PORT_CL_DW5_B 0x6C014
1914 #define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
1917 #define _PORT_CL1CM_DW9_A 0x162024
1918 #define _PORT_CL1CM_DW9_BC 0x6C024
1919 #define IREF0RC_OFFSET_SHIFT 8
1920 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1921 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1923 #define _PORT_CL1CM_DW10_A 0x162028
1924 #define _PORT_CL1CM_DW10_BC 0x6C028
1925 #define IREF1RC_OFFSET_SHIFT 8
1926 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1927 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1929 #define _PORT_CL1CM_DW28_A 0x162070
1930 #define _PORT_CL1CM_DW28_BC 0x6C070
1931 #define OCL1_POWER_DOWN_EN (1 << 23)
1932 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1933 #define SUS_CLK_CONFIG 0x3
1934 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1936 #define _PORT_CL1CM_DW30_A 0x162078
1937 #define _PORT_CL1CM_DW30_BC 0x6C078
1938 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1939 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1941 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1942 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1943 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1944 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1945 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1946 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1947 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1948 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1949 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1950 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1951 #define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \
1952 _CNL_PORT_PCS_DW1_GRP_AE, \
1953 _CNL_PORT_PCS_DW1_GRP_B, \
1954 _CNL_PORT_PCS_DW1_GRP_C, \
1955 _CNL_PORT_PCS_DW1_GRP_D, \
1956 _CNL_PORT_PCS_DW1_GRP_AE, \
1957 _CNL_PORT_PCS_DW1_GRP_F)
1958 #define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \
1959 _CNL_PORT_PCS_DW1_LN0_AE, \
1960 _CNL_PORT_PCS_DW1_LN0_B, \
1961 _CNL_PORT_PCS_DW1_LN0_C, \
1962 _CNL_PORT_PCS_DW1_LN0_D, \
1963 _CNL_PORT_PCS_DW1_LN0_AE, \
1964 _CNL_PORT_PCS_DW1_LN0_F)
1965 #define COMMON_KEEPER_EN (1 << 26)
1967 #define _CNL_PORT_TX_DW2_GRP_AE 0x162348
1968 #define _CNL_PORT_TX_DW2_GRP_B 0x1623C8
1969 #define _CNL_PORT_TX_DW2_GRP_C 0x162B48
1970 #define _CNL_PORT_TX_DW2_GRP_D 0x162BC8
1971 #define _CNL_PORT_TX_DW2_GRP_F 0x162A48
1972 #define _CNL_PORT_TX_DW2_LN0_AE 0x162448
1973 #define _CNL_PORT_TX_DW2_LN0_B 0x162648
1974 #define _CNL_PORT_TX_DW2_LN0_C 0x162C48
1975 #define _CNL_PORT_TX_DW2_LN0_D 0x162E48
1976 #define _CNL_PORT_TX_DW2_LN0_F 0x162848
1977 #define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
1978 _CNL_PORT_TX_DW2_GRP_AE, \
1979 _CNL_PORT_TX_DW2_GRP_B, \
1980 _CNL_PORT_TX_DW2_GRP_C, \
1981 _CNL_PORT_TX_DW2_GRP_D, \
1982 _CNL_PORT_TX_DW2_GRP_AE, \
1983 _CNL_PORT_TX_DW2_GRP_F)
1984 #define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \
1985 _CNL_PORT_TX_DW2_LN0_AE, \
1986 _CNL_PORT_TX_DW2_LN0_B, \
1987 _CNL_PORT_TX_DW2_LN0_C, \
1988 _CNL_PORT_TX_DW2_LN0_D, \
1989 _CNL_PORT_TX_DW2_LN0_AE, \
1990 _CNL_PORT_TX_DW2_LN0_F)
1991 #define SWING_SEL_UPPER(x) ((x >> 3) << 15)
1992 #define SWING_SEL_UPPER_MASK (1 << 15)
1993 #define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
1994 #define SWING_SEL_LOWER_MASK (0x7 << 11)
1995 #define RCOMP_SCALAR(x) ((x) << 0)
1996 #define RCOMP_SCALAR_MASK (0xFF << 0)
1998 #define _CNL_PORT_TX_DW4_GRP_AE 0x162350
1999 #define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
2000 #define _CNL_PORT_TX_DW4_GRP_C 0x162B50
2001 #define _CNL_PORT_TX_DW4_GRP_D 0x162BD0
2002 #define _CNL_PORT_TX_DW4_GRP_F 0x162A50
2003 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
2004 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
2005 #define _CNL_PORT_TX_DW4_LN0_B 0x162650
2006 #define _CNL_PORT_TX_DW4_LN0_C 0x162C50
2007 #define _CNL_PORT_TX_DW4_LN0_D 0x162E50
2008 #define _CNL_PORT_TX_DW4_LN0_F 0x162850
2009 #define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \
2010 _CNL_PORT_TX_DW4_GRP_AE, \
2011 _CNL_PORT_TX_DW4_GRP_B, \
2012 _CNL_PORT_TX_DW4_GRP_C, \
2013 _CNL_PORT_TX_DW4_GRP_D, \
2014 _CNL_PORT_TX_DW4_GRP_AE, \
2015 _CNL_PORT_TX_DW4_GRP_F)
2016 #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \
2017 _CNL_PORT_TX_DW4_LN0_AE, \
2018 _CNL_PORT_TX_DW4_LN1_AE, \
2019 _CNL_PORT_TX_DW4_LN0_B, \
2020 _CNL_PORT_TX_DW4_LN0_C, \
2021 _CNL_PORT_TX_DW4_LN0_D, \
2022 _CNL_PORT_TX_DW4_LN0_AE, \
2023 _CNL_PORT_TX_DW4_LN0_F)
2024 #define LOADGEN_SELECT (1 << 31)
2025 #define POST_CURSOR_1(x) ((x) << 12)
2026 #define POST_CURSOR_1_MASK (0x3F << 12)
2027 #define POST_CURSOR_2(x) ((x) << 6)
2028 #define POST_CURSOR_2_MASK (0x3F << 6)
2029 #define CURSOR_COEFF(x) ((x) << 0)
2030 #define CURSOR_COEFF_MASK (0x3F << 0)
2032 #define _CNL_PORT_TX_DW5_GRP_AE 0x162354
2033 #define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
2034 #define _CNL_PORT_TX_DW5_GRP_C 0x162B54
2035 #define _CNL_PORT_TX_DW5_GRP_D 0x162BD4
2036 #define _CNL_PORT_TX_DW5_GRP_F 0x162A54
2037 #define _CNL_PORT_TX_DW5_LN0_AE 0x162454
2038 #define _CNL_PORT_TX_DW5_LN0_B 0x162654
2039 #define _CNL_PORT_TX_DW5_LN0_C 0x162C54
2040 #define _CNL_PORT_TX_DW5_LN0_D 0x162E54
2041 #define _CNL_PORT_TX_DW5_LN0_F 0x162854
2042 #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
2043 _CNL_PORT_TX_DW5_GRP_AE, \
2044 _CNL_PORT_TX_DW5_GRP_B, \
2045 _CNL_PORT_TX_DW5_GRP_C, \
2046 _CNL_PORT_TX_DW5_GRP_D, \
2047 _CNL_PORT_TX_DW5_GRP_AE, \
2048 _CNL_PORT_TX_DW5_GRP_F)
2049 #define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \
2050 _CNL_PORT_TX_DW5_LN0_AE, \
2051 _CNL_PORT_TX_DW5_LN0_B, \
2052 _CNL_PORT_TX_DW5_LN0_C, \
2053 _CNL_PORT_TX_DW5_LN0_D, \
2054 _CNL_PORT_TX_DW5_LN0_AE, \
2055 _CNL_PORT_TX_DW5_LN0_F)
2056 #define TX_TRAINING_EN (1 << 31)
2057 #define TAP3_DISABLE (1 << 29)
2058 #define SCALING_MODE_SEL(x) ((x) << 18)
2059 #define SCALING_MODE_SEL_MASK (0x7 << 18)
2060 #define RTERM_SELECT(x) ((x) << 3)
2061 #define RTERM_SELECT_MASK (0x7 << 3)
2063 #define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
2064 #define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
2065 #define _CNL_PORT_TX_DW7_GRP_C 0x162B5C
2066 #define _CNL_PORT_TX_DW7_GRP_D 0x162BDC
2067 #define _CNL_PORT_TX_DW7_GRP_F 0x162A5C
2068 #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
2069 #define _CNL_PORT_TX_DW7_LN0_B 0x16265C
2070 #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
2071 #define _CNL_PORT_TX_DW7_LN0_D 0x162E5C
2072 #define _CNL_PORT_TX_DW7_LN0_F 0x16285C
2073 #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
2074 _CNL_PORT_TX_DW7_GRP_AE, \
2075 _CNL_PORT_TX_DW7_GRP_B, \
2076 _CNL_PORT_TX_DW7_GRP_C, \
2077 _CNL_PORT_TX_DW7_GRP_D, \
2078 _CNL_PORT_TX_DW7_GRP_AE, \
2079 _CNL_PORT_TX_DW7_GRP_F)
2080 #define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \
2081 _CNL_PORT_TX_DW7_LN0_AE, \
2082 _CNL_PORT_TX_DW7_LN0_B, \
2083 _CNL_PORT_TX_DW7_LN0_C, \
2084 _CNL_PORT_TX_DW7_LN0_D, \
2085 _CNL_PORT_TX_DW7_LN0_AE, \
2086 _CNL_PORT_TX_DW7_LN0_F)
2087 #define N_SCALAR(x) ((x) << 24)
2088 #define N_SCALAR_MASK (0x7F << 24)
2090 /* The spec defines this only for BXT PHY0, but lets assume that this
2091 * would exist for PHY1 too if it had a second channel.
2093 #define _PORT_CL2CM_DW6_A 0x162358
2094 #define _PORT_CL2CM_DW6_BC 0x6C358
2095 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2096 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2098 #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
2099 #define COMP_INIT (1 << 31)
2100 #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
2101 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
2102 #define PROCESS_INFO_DOT_0 (0 << 26)
2103 #define PROCESS_INFO_DOT_1 (1 << 26)
2104 #define PROCESS_INFO_DOT_4 (2 << 26)
2105 #define PROCESS_INFO_MASK (7 << 26)
2106 #define PROCESS_INFO_SHIFT 26
2107 #define VOLTAGE_INFO_0_85V (0 << 24)
2108 #define VOLTAGE_INFO_0_95V (1 << 24)
2109 #define VOLTAGE_INFO_1_05V (2 << 24)
2110 #define VOLTAGE_INFO_MASK (3 << 24)
2111 #define VOLTAGE_INFO_SHIFT 24
2112 #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
2113 #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
2115 #define _ICL_PORT_COMP_DW0_A 0x162100
2116 #define _ICL_PORT_COMP_DW0_B 0x6C100
2117 #define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
2118 _ICL_PORT_COMP_DW0_B)
2119 #define _ICL_PORT_COMP_DW1_A 0x162104
2120 #define _ICL_PORT_COMP_DW1_B 0x6C104
2121 #define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
2122 _ICL_PORT_COMP_DW1_B)
2123 #define _ICL_PORT_COMP_DW3_A 0x16210C
2124 #define _ICL_PORT_COMP_DW3_B 0x6C10C
2125 #define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
2126 _ICL_PORT_COMP_DW3_B)
2127 #define _ICL_PORT_COMP_DW9_A 0x162124
2128 #define _ICL_PORT_COMP_DW9_B 0x6C124
2129 #define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
2130 _ICL_PORT_COMP_DW9_B)
2131 #define _ICL_PORT_COMP_DW10_A 0x162128
2132 #define _ICL_PORT_COMP_DW10_B 0x6C128
2133 #define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
2134 _ICL_PORT_COMP_DW10_A, \
2135 _ICL_PORT_COMP_DW10_B)
2137 /* BXT PHY Ref registers */
2138 #define _PORT_REF_DW3_A 0x16218C
2139 #define _PORT_REF_DW3_BC 0x6C18C
2140 #define GRC_DONE (1 << 22)
2141 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2143 #define _PORT_REF_DW6_A 0x162198
2144 #define _PORT_REF_DW6_BC 0x6C198
2145 #define GRC_CODE_SHIFT 24
2146 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2147 #define GRC_CODE_FAST_SHIFT 16
2148 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2149 #define GRC_CODE_SLOW_SHIFT 8
2150 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2151 #define GRC_CODE_NOM_MASK 0xFF
2152 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2154 #define _PORT_REF_DW8_A 0x1621A0
2155 #define _PORT_REF_DW8_BC 0x6C1A0
2156 #define GRC_DIS (1 << 15)
2157 #define GRC_RDY_OVRD (1 << 1)
2158 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2160 /* BXT PHY PCS registers */
2161 #define _PORT_PCS_DW10_LN01_A 0x162428
2162 #define _PORT_PCS_DW10_LN01_B 0x6C428
2163 #define _PORT_PCS_DW10_LN01_C 0x6C828
2164 #define _PORT_PCS_DW10_GRP_A 0x162C28
2165 #define _PORT_PCS_DW10_GRP_B 0x6CC28
2166 #define _PORT_PCS_DW10_GRP_C 0x6CE28
2167 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2168 _PORT_PCS_DW10_LN01_B, \
2169 _PORT_PCS_DW10_LN01_C)
2170 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2171 _PORT_PCS_DW10_GRP_B, \
2172 _PORT_PCS_DW10_GRP_C)
2174 #define TX2_SWING_CALC_INIT (1 << 31)
2175 #define TX1_SWING_CALC_INIT (1 << 30)
2177 #define _PORT_PCS_DW12_LN01_A 0x162430
2178 #define _PORT_PCS_DW12_LN01_B 0x6C430
2179 #define _PORT_PCS_DW12_LN01_C 0x6C830
2180 #define _PORT_PCS_DW12_LN23_A 0x162630
2181 #define _PORT_PCS_DW12_LN23_B 0x6C630
2182 #define _PORT_PCS_DW12_LN23_C 0x6CA30
2183 #define _PORT_PCS_DW12_GRP_A 0x162c30
2184 #define _PORT_PCS_DW12_GRP_B 0x6CC30
2185 #define _PORT_PCS_DW12_GRP_C 0x6CE30
2186 #define LANESTAGGER_STRAP_OVRD (1 << 6)
2187 #define LANE_STAGGER_MASK 0x1F
2188 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2189 _PORT_PCS_DW12_LN01_B, \
2190 _PORT_PCS_DW12_LN01_C)
2191 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2192 _PORT_PCS_DW12_LN23_B, \
2193 _PORT_PCS_DW12_LN23_C)
2194 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2195 _PORT_PCS_DW12_GRP_B, \
2196 _PORT_PCS_DW12_GRP_C)
2198 /* BXT PHY TX registers */
2199 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2200 ((lane) & 1) * 0x80)
2202 #define _PORT_TX_DW2_LN0_A 0x162508
2203 #define _PORT_TX_DW2_LN0_B 0x6C508
2204 #define _PORT_TX_DW2_LN0_C 0x6C908
2205 #define _PORT_TX_DW2_GRP_A 0x162D08
2206 #define _PORT_TX_DW2_GRP_B 0x6CD08
2207 #define _PORT_TX_DW2_GRP_C 0x6CF08
2208 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2209 _PORT_TX_DW2_LN0_B, \
2211 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2212 _PORT_TX_DW2_GRP_B, \
2214 #define MARGIN_000_SHIFT 16
2215 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2216 #define UNIQ_TRANS_SCALE_SHIFT 8
2217 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2219 #define _PORT_TX_DW3_LN0_A 0x16250C
2220 #define _PORT_TX_DW3_LN0_B 0x6C50C
2221 #define _PORT_TX_DW3_LN0_C 0x6C90C
2222 #define _PORT_TX_DW3_GRP_A 0x162D0C
2223 #define _PORT_TX_DW3_GRP_B 0x6CD0C
2224 #define _PORT_TX_DW3_GRP_C 0x6CF0C
2225 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2226 _PORT_TX_DW3_LN0_B, \
2228 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2229 _PORT_TX_DW3_GRP_B, \
2231 #define SCALE_DCOMP_METHOD (1 << 26)
2232 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2234 #define _PORT_TX_DW4_LN0_A 0x162510
2235 #define _PORT_TX_DW4_LN0_B 0x6C510
2236 #define _PORT_TX_DW4_LN0_C 0x6C910
2237 #define _PORT_TX_DW4_GRP_A 0x162D10
2238 #define _PORT_TX_DW4_GRP_B 0x6CD10
2239 #define _PORT_TX_DW4_GRP_C 0x6CF10
2240 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2241 _PORT_TX_DW4_LN0_B, \
2243 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2244 _PORT_TX_DW4_GRP_B, \
2246 #define DEEMPH_SHIFT 24
2247 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2249 #define _PORT_TX_DW5_LN0_A 0x162514
2250 #define _PORT_TX_DW5_LN0_B 0x6C514
2251 #define _PORT_TX_DW5_LN0_C 0x6C914
2252 #define _PORT_TX_DW5_GRP_A 0x162D14
2253 #define _PORT_TX_DW5_GRP_B 0x6CD14
2254 #define _PORT_TX_DW5_GRP_C 0x6CF14
2255 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2256 _PORT_TX_DW5_LN0_B, \
2258 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2259 _PORT_TX_DW5_GRP_B, \
2261 #define DCC_DELAY_RANGE_1 (1 << 9)
2262 #define DCC_DELAY_RANGE_2 (1 << 8)
2264 #define _PORT_TX_DW14_LN0_A 0x162538
2265 #define _PORT_TX_DW14_LN0_B 0x6C538
2266 #define _PORT_TX_DW14_LN0_C 0x6C938
2267 #define LATENCY_OPTIM_SHIFT 30
2268 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2269 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2270 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2271 _PORT_TX_DW14_LN0_C) + \
2272 _BXT_LANE_OFFSET(lane))
2274 /* UAIMI scratch pad register 1 */
2275 #define UAIMI_SPR1 _MMIO(0x4F074)
2276 /* SKL VccIO mask */
2277 #define SKL_VCCIO_MASK 0x1
2278 /* SKL balance leg register */
2279 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2280 /* I_boost values */
2281 #define BALANCE_LEG_SHIFT(port) (8+3*(port))
2282 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
2283 /* Balance leg disable bits */
2284 #define BALANCE_LEG_DISABLE_SHIFT 23
2285 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2289 * [0-7] @ 0x2000 gen2,gen3
2290 * [8-15] @ 0x3000 945,g33,pnv
2292 * [0-15] @ 0x3000 gen4,gen5
2294 * [0-15] @ 0x100000 gen6,vlv,chv
2295 * [0-31] @ 0x100000 gen7+
2297 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2298 #define I830_FENCE_START_MASK 0x07f80000
2299 #define I830_FENCE_TILING_Y_SHIFT 12
2300 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2301 #define I830_FENCE_PITCH_SHIFT 4
2302 #define I830_FENCE_REG_VALID (1<<0)
2303 #define I915_FENCE_MAX_PITCH_VAL 4
2304 #define I830_FENCE_MAX_PITCH_VAL 6
2305 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
2307 #define I915_FENCE_START_MASK 0x0ff00000
2308 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2310 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2311 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2312 #define I965_FENCE_PITCH_SHIFT 2
2313 #define I965_FENCE_TILING_Y_SHIFT 1
2314 #define I965_FENCE_REG_VALID (1<<0)
2315 #define I965_FENCE_MAX_PITCH_VAL 0x0400
2317 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2318 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2319 #define GEN6_FENCE_PITCH_SHIFT 32
2320 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2323 /* control register for cpu gtt access */
2324 #define TILECTL _MMIO(0x101000)
2325 #define TILECTL_SWZCTL (1 << 0)
2326 #define TILECTL_TLBPF (1 << 1)
2327 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2328 #define TILECTL_BACKSNOOP_DIS (1 << 3)
2331 * Instruction and interrupt control regs
2333 #define PGTBL_CTL _MMIO(0x02020)
2334 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2335 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2336 #define PGTBL_ER _MMIO(0x02024)
2337 #define PRB0_BASE (0x2030-0x30)
2338 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
2339 #define PRB2_BASE (0x2050-0x30) /* gen3 */
2340 #define SRB0_BASE (0x2100-0x30) /* gen2 */
2341 #define SRB1_BASE (0x2110-0x30) /* gen2 */
2342 #define SRB2_BASE (0x2120-0x30) /* 830 */
2343 #define SRB3_BASE (0x2130-0x30) /* 830 */
2344 #define RENDER_RING_BASE 0x02000
2345 #define BSD_RING_BASE 0x04000
2346 #define GEN6_BSD_RING_BASE 0x12000
2347 #define GEN8_BSD2_RING_BASE 0x1c000
2348 #define VEBOX_RING_BASE 0x1a000
2349 #define BLT_RING_BASE 0x22000
2350 #define RING_TAIL(base) _MMIO((base)+0x30)
2351 #define RING_HEAD(base) _MMIO((base)+0x34)
2352 #define RING_START(base) _MMIO((base)+0x38)
2353 #define RING_CTL(base) _MMIO((base)+0x3c)
2354 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2355 #define RING_SYNC_0(base) _MMIO((base)+0x40)
2356 #define RING_SYNC_1(base) _MMIO((base)+0x44)
2357 #define RING_SYNC_2(base) _MMIO((base)+0x48)
2358 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2359 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2360 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2361 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2362 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2363 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2364 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2365 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2366 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2367 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2368 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2369 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2370 #define GEN6_NOSYNC INVALID_MMIO_REG
2371 #define RING_PSMI_CTL(base) _MMIO((base)+0x50)
2372 #define RING_MAX_IDLE(base) _MMIO((base)+0x54)
2373 #define RING_HWS_PGA(base) _MMIO((base)+0x80)
2374 #define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080)
2375 #define RING_RESET_CTL(base) _MMIO((base)+0xd0)
2376 #define RESET_CTL_REQUEST_RESET (1 << 0)
2377 #define RESET_CTL_READY_TO_RESET (1 << 1)
2379 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
2380 #define GTT_CACHE_EN_ALL 0xF0007FFF
2381 #define GEN7_WR_WATERMARK _MMIO(0x4028)
2382 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2383 #define ARB_MODE _MMIO(0x4030)
2384 #define ARB_MODE_SWIZZLE_SNB (1<<4)
2385 #define ARB_MODE_SWIZZLE_IVB (1<<5)
2386 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2387 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2388 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2389 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2390 #define GEN7_LRA_LIMITS_REG_NUM 13
2391 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2392 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2394 #define GAMTARBMODE _MMIO(0x04a08)
2395 #define ARB_MODE_BWGTLB_DISABLE (1<<9)
2396 #define ARB_MODE_SWIZZLE_BDW (1<<1)
2397 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2398 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id)
2399 #define GEN8_RING_FAULT_REG _MMIO(0x4094)
2400 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2401 #define RING_FAULT_GTTSEL_MASK (1<<11)
2402 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2403 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2404 #define RING_FAULT_VALID (1<<0)
2405 #define DONE_REG _MMIO(0x40b0)
2406 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2407 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2408 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index)*4)
2409 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2410 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2411 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2412 #define RING_ACTHD(base) _MMIO((base)+0x74)
2413 #define RING_ACTHD_UDW(base) _MMIO((base)+0x5c)
2414 #define RING_NOPID(base) _MMIO((base)+0x94)
2415 #define RING_IMR(base) _MMIO((base)+0xa8)
2416 #define RING_HWSTAM(base) _MMIO((base)+0x98)
2417 #define RING_TIMESTAMP(base) _MMIO((base)+0x358)
2418 #define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4)
2419 #define TAIL_ADDR 0x001FFFF8
2420 #define HEAD_WRAP_COUNT 0xFFE00000
2421 #define HEAD_WRAP_ONE 0x00200000
2422 #define HEAD_ADDR 0x001FFFFC
2423 #define RING_NR_PAGES 0x001FF000
2424 #define RING_REPORT_MASK 0x00000006
2425 #define RING_REPORT_64K 0x00000002
2426 #define RING_REPORT_128K 0x00000004
2427 #define RING_NO_REPORT 0x00000000
2428 #define RING_VALID_MASK 0x00000001
2429 #define RING_VALID 0x00000001
2430 #define RING_INVALID 0x00000000
2431 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
2432 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
2433 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
2435 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4)
2436 #define RING_MAX_NONPRIV_SLOTS 12
2438 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2440 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2441 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
2443 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2444 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2446 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2447 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
2448 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
2451 #define PRB0_TAIL _MMIO(0x2030)
2452 #define PRB0_HEAD _MMIO(0x2034)
2453 #define PRB0_START _MMIO(0x2038)
2454 #define PRB0_CTL _MMIO(0x203c)
2455 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2456 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2457 #define PRB1_START _MMIO(0x2048) /* 915+ only */
2458 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */
2460 #define IPEIR_I965 _MMIO(0x2064)
2461 #define IPEHR_I965 _MMIO(0x2068)
2462 #define GEN7_SC_INSTDONE _MMIO(0x7100)
2463 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2464 #define GEN7_ROW_INSTDONE _MMIO(0xe164)
2465 #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2466 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2467 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2468 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2469 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2470 #define RING_IPEIR(base) _MMIO((base)+0x64)
2471 #define RING_IPEHR(base) _MMIO((base)+0x68)
2473 * On GEN4, only the render ring INSTDONE exists and has a different
2474 * layout than the GEN7+ version.
2475 * The GEN2 counterpart of this register is GEN2_INSTDONE.
2477 #define RING_INSTDONE(base) _MMIO((base)+0x6c)
2478 #define RING_INSTPS(base) _MMIO((base)+0x70)
2479 #define RING_DMA_FADD(base) _MMIO((base)+0x78)
2480 #define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */
2481 #define RING_INSTPM(base) _MMIO((base)+0xc0)
2482 #define RING_MI_MODE(base) _MMIO((base)+0x9c)
2483 #define INSTPS _MMIO(0x2070) /* 965+ only */
2484 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2485 #define ACTHD_I965 _MMIO(0x2074)
2486 #define HWS_PGA _MMIO(0x2080)
2487 #define HWS_ADDRESS_MASK 0xfffff000
2488 #define HWS_START_ADDRESS_SHIFT 4
2489 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2490 #define PWRCTX_EN (1<<0)
2491 #define IPEIR _MMIO(0x2088)
2492 #define IPEHR _MMIO(0x208c)
2493 #define GEN2_INSTDONE _MMIO(0x2090)
2494 #define NOPID _MMIO(0x2094)
2495 #define HWSTAM _MMIO(0x2098)
2496 #define DMA_FADD_I8XX _MMIO(0x20d0)
2497 #define RING_BBSTATE(base) _MMIO((base)+0x110)
2498 #define RING_BB_PPGTT (1 << 5)
2499 #define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */
2500 #define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */
2501 #define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */
2502 #define RING_BBADDR(base) _MMIO((base)+0x140)
2503 #define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */
2504 #define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */
2505 #define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */
2506 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */
2507 #define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */
2509 #define ERROR_GEN6 _MMIO(0x40a0)
2510 #define GEN7_ERR_INT _MMIO(0x44040)
2511 #define ERR_INT_POISON (1<<31)
2512 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
2513 #define ERR_INT_PIPE_CRC_DONE_C (1<<8)
2514 #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
2515 #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
2516 #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
2517 #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
2518 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
2519 #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
2520 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
2522 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2523 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2524 #define FAULT_VA_HIGH_BITS (0xf << 0)
2525 #define FAULT_GTT_SEL (1 << 4)
2527 #define FPGA_DBG _MMIO(0x42300)
2528 #define FPGA_DBG_RM_NOCLAIM (1<<31)
2530 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2531 #define CLAIM_ER_CLR (1 << 31)
2532 #define CLAIM_ER_OVERFLOW (1 << 16)
2533 #define CLAIM_ER_CTR_MASK 0xffff
2535 #define DERRMR _MMIO(0x44050)
2536 /* Note that HBLANK events are reserved on bdw+ */
2537 #define DERRMR_PIPEA_SCANLINE (1<<0)
2538 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
2539 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
2540 #define DERRMR_PIPEA_VBLANK (1<<3)
2541 #define DERRMR_PIPEA_HBLANK (1<<5)
2542 #define DERRMR_PIPEB_SCANLINE (1<<8)
2543 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
2544 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
2545 #define DERRMR_PIPEB_VBLANK (1<<11)
2546 #define DERRMR_PIPEB_HBLANK (1<<13)
2547 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2548 #define DERRMR_PIPEC_SCANLINE (1<<14)
2549 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
2550 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
2551 #define DERRMR_PIPEC_VBLANK (1<<21)
2552 #define DERRMR_PIPEC_HBLANK (1<<22)
2555 /* GM45+ chicken bits -- debug workaround bits that may be required
2556 * for various sorts of correct behavior. The top 16 bits of each are
2557 * the enables for writing to the corresponding low bit.
2559 #define _3D_CHICKEN _MMIO(0x2084)
2560 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2561 #define _3D_CHICKEN2 _MMIO(0x208c)
2562 /* Disables pipelining of read flushes past the SF-WIZ interface.
2563 * Required on all Ironlake steppings according to the B-Spec, but the
2564 * particular danger of not doing so is not specified.
2566 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2567 #define _3D_CHICKEN3 _MMIO(0x2090)
2568 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2569 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2570 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2571 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
2572 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
2574 #define MI_MODE _MMIO(0x209c)
2575 # define VS_TIMER_DISPATCH (1 << 6)
2576 # define MI_FLUSH_ENABLE (1 << 12)
2577 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2578 # define MODE_IDLE (1 << 9)
2579 # define STOP_RING (1 << 8)
2581 #define GEN6_GT_MODE _MMIO(0x20d0)
2582 #define GEN7_GT_MODE _MMIO(0x7008)
2583 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2584 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2585 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2586 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2587 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2588 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2589 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2590 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2592 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2593 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2594 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2596 /* WaClearTdlStateAckDirtyBits */
2597 #define GEN8_STATE_ACK _MMIO(0x20F0)
2598 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2599 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2600 #define GEN9_STATE_ACK_TDL0 (1 << 12)
2601 #define GEN9_STATE_ACK_TDL1 (1 << 13)
2602 #define GEN9_STATE_ACK_TDL2 (1 << 14)
2603 #define GEN9_STATE_ACK_TDL3 (1 << 15)
2604 #define GEN9_SUBSLICE_TDL_ACK_BITS \
2605 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2606 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2608 #define GFX_MODE _MMIO(0x2520)
2609 #define GFX_MODE_GEN7 _MMIO(0x229c)
2610 #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base+0x29c)
2611 #define GFX_RUN_LIST_ENABLE (1<<15)
2612 #define GFX_INTERRUPT_STEERING (1<<14)
2613 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
2614 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
2615 #define GFX_REPLAY_MODE (1<<11)
2616 #define GFX_PSMI_GRANULARITY (1<<10)
2617 #define GFX_PPGTT_ENABLE (1<<9)
2618 #define GEN8_GFX_PPGTT_48B (1<<7)
2620 #define GFX_FORWARD_VBLANK_MASK (3<<5)
2621 #define GFX_FORWARD_VBLANK_NEVER (0<<5)
2622 #define GFX_FORWARD_VBLANK_ALWAYS (1<<5)
2623 #define GFX_FORWARD_VBLANK_COND (2<<5)
2625 #define GEN11_GFX_DISABLE_LEGACY_MODE (1<<3)
2627 #define VLV_DISPLAY_BASE 0x180000
2628 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
2629 #define BXT_MIPI_BASE 0x60000
2631 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2632 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2633 #define SCPD0 _MMIO(0x209c) /* 915+ only */
2634 #define IER _MMIO(0x20a0)
2635 #define IIR _MMIO(0x20a4)
2636 #define IMR _MMIO(0x20a8)
2637 #define ISR _MMIO(0x20ac)
2638 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2639 #define GINT_DIS (1<<22)
2640 #define GCFG_DIS (1<<8)
2641 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2642 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2643 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2644 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2645 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2646 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2647 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2648 #define VLV_PCBR_ADDR_SHIFT 12
2650 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
2651 #define EIR _MMIO(0x20b0)
2652 #define EMR _MMIO(0x20b4)
2653 #define ESR _MMIO(0x20b8)
2654 #define GM45_ERROR_PAGE_TABLE (1<<5)
2655 #define GM45_ERROR_MEM_PRIV (1<<4)
2656 #define I915_ERROR_PAGE_TABLE (1<<4)
2657 #define GM45_ERROR_CP_PRIV (1<<3)
2658 #define I915_ERROR_MEMORY_REFRESH (1<<1)
2659 #define I915_ERROR_INSTRUCTION (1<<0)
2660 #define INSTPM _MMIO(0x20c0)
2661 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
2662 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
2663 will not assert AGPBUSY# and will only
2664 be delivered when out of C3. */
2665 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
2666 #define INSTPM_TLB_INVALIDATE (1<<9)
2667 #define INSTPM_SYNC_FLUSH (1<<5)
2668 #define ACTHD _MMIO(0x20c8)
2669 #define MEM_MODE _MMIO(0x20cc)
2670 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
2671 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
2672 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
2673 #define FW_BLC _MMIO(0x20d8)
2674 #define FW_BLC2 _MMIO(0x20dc)
2675 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
2676 #define FW_BLC_SELF_EN_MASK (1<<31)
2677 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
2678 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
2679 #define MM_BURST_LENGTH 0x00700000
2680 #define MM_FIFO_WATERMARK 0x0001F000
2681 #define LM_BURST_LENGTH 0x00000700
2682 #define LM_FIFO_WATERMARK 0x0000001F
2683 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
2685 #define MBUS_ABOX_CTL _MMIO(0x45038)
2686 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2687 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2688 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
2689 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
2690 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
2691 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
2692 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
2693 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
2695 #define _PIPEA_MBUS_DBOX_CTL 0x7003C
2696 #define _PIPEB_MBUS_DBOX_CTL 0x7103C
2697 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2698 _PIPEB_MBUS_DBOX_CTL)
2699 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
2700 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
2701 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
2702 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
2703 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
2704 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
2706 #define MBUS_UBOX_CTL _MMIO(0x4503C)
2707 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2708 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
2710 /* Make render/texture TLB fetches lower priorty than associated data
2711 * fetches. This is not turned on by default
2713 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2715 /* Isoch request wait on GTT enable (Display A/B/C streams).
2716 * Make isoch requests stall on the TLB update. May cause
2717 * display underruns (test mode only)
2719 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2721 /* Block grant count for isoch requests when block count is
2722 * set to a finite value.
2724 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2725 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
2726 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
2727 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
2728 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
2730 /* Enable render writes to complete in C2/C3/C4 power states.
2731 * If this isn't enabled, render writes are prevented in low
2732 * power states. That seems bad to me.
2734 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2736 /* This acknowledges an async flip immediately instead
2737 * of waiting for 2TLB fetches.
2739 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2741 /* Enables non-sequential data reads through arbiter
2743 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
2745 /* Disable FSB snooping of cacheable write cycles from binner/render
2748 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2750 /* Arbiter time slice for non-isoch streams */
2751 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
2752 #define MI_ARB_TIME_SLICE_1 (0 << 5)
2753 #define MI_ARB_TIME_SLICE_2 (1 << 5)
2754 #define MI_ARB_TIME_SLICE_4 (2 << 5)
2755 #define MI_ARB_TIME_SLICE_6 (3 << 5)
2756 #define MI_ARB_TIME_SLICE_8 (4 << 5)
2757 #define MI_ARB_TIME_SLICE_10 (5 << 5)
2758 #define MI_ARB_TIME_SLICE_14 (6 << 5)
2759 #define MI_ARB_TIME_SLICE_16 (7 << 5)
2761 /* Low priority grace period page size */
2762 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
2763 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2765 /* Disable display A/B trickle feed */
2766 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2768 /* Set display plane priority */
2769 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
2770 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
2772 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
2773 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
2774 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
2776 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
2777 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
2778 #define CM0_IZ_OPT_DISABLE (1<<6)
2779 #define CM0_ZR_OPT_DISABLE (1<<5)
2780 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
2781 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
2782 #define CM0_COLOR_EVICT_DISABLE (1<<3)
2783 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
2784 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
2785 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
2786 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
2787 #define GFX_FLSH_CNTL_EN (1<<0)
2788 #define ECOSKPD _MMIO(0x21d0)
2789 #define ECO_GATING_CX_ONLY (1<<3)
2790 #define ECO_FLIP_DONE (1<<0)
2792 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
2793 #define RC_OP_FLUSH_ENABLE (1<<0)
2794 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
2795 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
2796 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
2797 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
2798 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
2800 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
2801 #define GEN6_BLITTER_LOCK_SHIFT 16
2802 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
2804 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2805 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
2806 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2807 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
2809 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2810 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2812 /* Fuse readout registers for GT */
2813 #define HSW_PAVP_FUSE1 _MMIO(0x911C)
2814 #define HSW_F1_EU_DIS_SHIFT 16
2815 #define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT)
2816 #define HSW_F1_EU_DIS_10EUS 0
2817 #define HSW_F1_EU_DIS_8EUS 1
2818 #define HSW_F1_EU_DIS_6EUS 2
2820 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2821 #define CHV_FGT_DISABLE_SS0 (1 << 10)
2822 #define CHV_FGT_DISABLE_SS1 (1 << 11)
2823 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2824 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2825 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2826 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2827 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2828 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2829 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2830 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2832 #define GEN8_FUSE2 _MMIO(0x9120)
2833 #define GEN8_F2_SS_DIS_SHIFT 21
2834 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
2835 #define GEN8_F2_S_ENA_SHIFT 25
2836 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2838 #define GEN9_F2_SS_DIS_SHIFT 20
2839 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2841 #define GEN10_F2_S_ENA_SHIFT 22
2842 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
2843 #define GEN10_F2_SS_DIS_SHIFT 18
2844 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
2846 #define GEN8_EU_DISABLE0 _MMIO(0x9134)
2847 #define GEN8_EU_DIS0_S0_MASK 0xffffff
2848 #define GEN8_EU_DIS0_S1_SHIFT 24
2849 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2851 #define GEN8_EU_DISABLE1 _MMIO(0x9138)
2852 #define GEN8_EU_DIS1_S1_MASK 0xffff
2853 #define GEN8_EU_DIS1_S2_SHIFT 16
2854 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2856 #define GEN8_EU_DISABLE2 _MMIO(0x913c)
2857 #define GEN8_EU_DIS2_S2_MASK 0xff
2859 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
2861 #define GEN10_EU_DISABLE3 _MMIO(0x9140)
2862 #define GEN10_EU_DIS_SS_MASK 0xff
2864 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
2865 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2866 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2867 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2868 #define GEN6_BSD_GO_INDICATOR (1 << 4)
2870 /* On modern GEN architectures interrupt control consists of two sets
2871 * of registers. The first set pertains to the ring generating the
2872 * interrupt. The second control is for the functional block generating the
2873 * interrupt. These are PM, GT, DE, etc.
2875 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2876 * GT interrupt bits, so we don't need to duplicate the defines.
2878 * These defines should cover us well from SNB->HSW with minor exceptions
2879 * it can also work on ILK.
2881 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2882 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2883 #define GT_BLT_USER_INTERRUPT (1 << 22)
2884 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2885 #define GT_BSD_USER_INTERRUPT (1 << 12)
2886 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2887 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2888 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2889 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2890 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2891 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2892 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2893 #define GT_RENDER_USER_INTERRUPT (1 << 0)
2895 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2896 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2898 #define GT_PARITY_ERROR(dev_priv) \
2899 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2900 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2902 /* These are all the "old" interrupts */
2903 #define ILK_BSD_USER_INTERRUPT (1<<5)
2905 #define I915_PM_INTERRUPT (1<<31)
2906 #define I915_ISP_INTERRUPT (1<<22)
2907 #define I915_LPE_PIPE_B_INTERRUPT (1<<21)
2908 #define I915_LPE_PIPE_A_INTERRUPT (1<<20)
2909 #define I915_MIPIC_INTERRUPT (1<<19)
2910 #define I915_MIPIA_INTERRUPT (1<<18)
2911 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
2912 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
2913 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
2914 #define I915_MASTER_ERROR_INTERRUPT (1<<15)
2915 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
2916 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
2917 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
2918 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
2919 #define I915_HWB_OOM_INTERRUPT (1<<13)
2920 #define I915_LPE_PIPE_C_INTERRUPT (1<<12)
2921 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
2922 #define I915_MISC_INTERRUPT (1<<11)
2923 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
2924 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
2925 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
2926 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
2927 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
2928 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
2929 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
2930 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
2931 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
2932 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
2933 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
2934 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
2935 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
2936 #define I915_DEBUG_INTERRUPT (1<<2)
2937 #define I915_WINVALID_INTERRUPT (1<<1)
2938 #define I915_USER_INTERRUPT (1<<1)
2939 #define I915_ASLE_INTERRUPT (1<<0)
2940 #define I915_BSD_USER_INTERRUPT (1<<25)
2942 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
2943 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
2945 /* DisplayPort Audio w/ LPE */
2946 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
2947 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
2949 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
2950 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
2951 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
2952 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
2953 _VLV_AUD_PORT_EN_B_DBG, \
2954 _VLV_AUD_PORT_EN_C_DBG, \
2955 _VLV_AUD_PORT_EN_D_DBG)
2956 #define VLV_AMP_MUTE (1 << 1)
2958 #define GEN6_BSD_RNCID _MMIO(0x12198)
2960 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2961 #define GEN7_FF_SCHED_MASK 0x0077070
2962 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2963 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
2964 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
2965 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
2966 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
2967 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
2968 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
2969 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
2970 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
2971 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
2972 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
2973 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
2974 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
2975 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
2978 * Framebuffer compression (915+ only)
2981 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2982 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2983 #define FBC_CONTROL _MMIO(0x3208)
2984 #define FBC_CTL_EN (1<<31)
2985 #define FBC_CTL_PERIODIC (1<<30)
2986 #define FBC_CTL_INTERVAL_SHIFT (16)
2987 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
2988 #define FBC_CTL_C3_IDLE (1<<13)
2989 #define FBC_CTL_STRIDE_SHIFT (5)
2990 #define FBC_CTL_FENCENO_SHIFT (0)
2991 #define FBC_COMMAND _MMIO(0x320c)
2992 #define FBC_CMD_COMPRESS (1<<0)
2993 #define FBC_STATUS _MMIO(0x3210)
2994 #define FBC_STAT_COMPRESSING (1<<31)
2995 #define FBC_STAT_COMPRESSED (1<<30)
2996 #define FBC_STAT_MODIFIED (1<<29)
2997 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
2998 #define FBC_CONTROL2 _MMIO(0x3214)
2999 #define FBC_CTL_FENCE_DBL (0<<4)
3000 #define FBC_CTL_IDLE_IMM (0<<2)
3001 #define FBC_CTL_IDLE_FULL (1<<2)
3002 #define FBC_CTL_IDLE_LINE (2<<2)
3003 #define FBC_CTL_IDLE_DEBUG (3<<2)
3004 #define FBC_CTL_CPU_FENCE (1<<1)
3005 #define FBC_CTL_PLANE(plane) ((plane)<<0)
3006 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
3007 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
3009 #define FBC_LL_SIZE (1536)
3011 #define FBC_LLC_READ_CTRL _MMIO(0x9044)
3012 #define FBC_LLC_FULLY_OPEN (1<<30)
3014 /* Framebuffer compression for GM45+ */
3015 #define DPFC_CB_BASE _MMIO(0x3200)
3016 #define DPFC_CONTROL _MMIO(0x3208)
3017 #define DPFC_CTL_EN (1<<31)
3018 #define DPFC_CTL_PLANE(plane) ((plane)<<30)
3019 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
3020 #define DPFC_CTL_FENCE_EN (1<<29)
3021 #define IVB_DPFC_CTL_FENCE_EN (1<<28)
3022 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
3023 #define DPFC_SR_EN (1<<10)
3024 #define DPFC_CTL_LIMIT_1X (0<<6)
3025 #define DPFC_CTL_LIMIT_2X (1<<6)
3026 #define DPFC_CTL_LIMIT_4X (2<<6)
3027 #define DPFC_RECOMP_CTL _MMIO(0x320c)
3028 #define DPFC_RECOMP_STALL_EN (1<<27)
3029 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
3030 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3031 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3032 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3033 #define DPFC_STATUS _MMIO(0x3210)
3034 #define DPFC_INVAL_SEG_SHIFT (16)
3035 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
3036 #define DPFC_COMP_SEG_SHIFT (0)
3037 #define DPFC_COMP_SEG_MASK (0x000007ff)
3038 #define DPFC_STATUS2 _MMIO(0x3214)
3039 #define DPFC_FENCE_YOFF _MMIO(0x3218)
3040 #define DPFC_CHICKEN _MMIO(0x3224)
3041 #define DPFC_HT_MODIFY (1<<31)
3043 /* Framebuffer compression for Ironlake */
3044 #define ILK_DPFC_CB_BASE _MMIO(0x43200)
3045 #define ILK_DPFC_CONTROL _MMIO(0x43208)
3046 #define FBC_CTL_FALSE_COLOR (1<<10)
3047 /* The bit 28-8 is reserved */
3048 #define DPFC_RESERVED (0x1FFFFF00)
3049 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3050 #define ILK_DPFC_STATUS _MMIO(0x43210)
3051 #define ILK_DPFC_COMP_SEG_MASK 0x7ff
3052 #define IVB_FBC_STATUS2 _MMIO(0x43214)
3053 #define IVB_FBC_COMP_SEG_MASK 0x7ff
3054 #define BDW_FBC_COMP_SEG_MASK 0xfff
3055 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3056 #define ILK_DPFC_CHICKEN _MMIO(0x43224)
3057 #define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
3058 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
3059 #define ILK_FBC_RT_BASE _MMIO(0x2128)
3060 #define ILK_FBC_RT_VALID (1<<0)
3061 #define SNB_FBC_FRONT_BUFFER (1<<1)
3063 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3064 #define ILK_FBCQ_DIS (1<<22)
3065 #define ILK_PABSTRETCH_DIS (1<<21)
3069 * Framebuffer compression for Sandybridge
3071 * The following two registers are of type GTTMMADR
3073 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
3074 #define SNB_CPU_FENCE_ENABLE (1<<29)
3075 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3077 /* Framebuffer compression for Ivybridge */
3078 #define IVB_FBC_RT_BASE _MMIO(0x7020)
3080 #define IPS_CTL _MMIO(0x43408)
3081 #define IPS_ENABLE (1 << 31)
3083 #define MSG_FBC_REND_STATE _MMIO(0x50380)
3084 #define FBC_REND_NUKE (1<<2)
3085 #define FBC_REND_CACHE_CLEAN (1<<1)
3090 #define GPIOA _MMIO(0x5010)
3091 #define GPIOB _MMIO(0x5014)
3092 #define GPIOC _MMIO(0x5018)
3093 #define GPIOD _MMIO(0x501c)
3094 #define GPIOE _MMIO(0x5020)
3095 #define GPIOF _MMIO(0x5024)
3096 #define GPIOG _MMIO(0x5028)
3097 #define GPIOH _MMIO(0x502c)
3098 # define GPIO_CLOCK_DIR_MASK (1 << 0)
3099 # define GPIO_CLOCK_DIR_IN (0 << 1)
3100 # define GPIO_CLOCK_DIR_OUT (1 << 1)
3101 # define GPIO_CLOCK_VAL_MASK (1 << 2)
3102 # define GPIO_CLOCK_VAL_OUT (1 << 3)
3103 # define GPIO_CLOCK_VAL_IN (1 << 4)
3104 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3105 # define GPIO_DATA_DIR_MASK (1 << 8)
3106 # define GPIO_DATA_DIR_IN (0 << 9)
3107 # define GPIO_DATA_DIR_OUT (1 << 9)
3108 # define GPIO_DATA_VAL_MASK (1 << 10)
3109 # define GPIO_DATA_VAL_OUT (1 << 11)
3110 # define GPIO_DATA_VAL_IN (1 << 12)
3111 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3113 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3114 #define GMBUS_AKSV_SELECT (1<<11)
3115 #define GMBUS_RATE_100KHZ (0<<8)
3116 #define GMBUS_RATE_50KHZ (1<<8)
3117 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
3118 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
3119 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
3120 #define GMBUS_PIN_DISABLED 0
3121 #define GMBUS_PIN_SSC 1
3122 #define GMBUS_PIN_VGADDC 2
3123 #define GMBUS_PIN_PANEL 3
3124 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
3125 #define GMBUS_PIN_DPC 4 /* HDMIC */
3126 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
3127 #define GMBUS_PIN_DPD 6 /* HDMID */
3128 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */
3129 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
3130 #define GMBUS_PIN_2_BXT 2
3131 #define GMBUS_PIN_3_BXT 3
3132 #define GMBUS_PIN_4_CNP 4
3133 #define GMBUS_PIN_9_TC1_ICP 9
3134 #define GMBUS_PIN_10_TC2_ICP 10
3135 #define GMBUS_PIN_11_TC3_ICP 11
3136 #define GMBUS_PIN_12_TC4_ICP 12
3138 #define GMBUS_NUM_PINS 13 /* including 0 */
3139 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3140 #define GMBUS_SW_CLR_INT (1<<31)
3141 #define GMBUS_SW_RDY (1<<30)
3142 #define GMBUS_ENT (1<<29) /* enable timeout */
3143 #define GMBUS_CYCLE_NONE (0<<25)
3144 #define GMBUS_CYCLE_WAIT (1<<25)
3145 #define GMBUS_CYCLE_INDEX (2<<25)
3146 #define GMBUS_CYCLE_STOP (4<<25)
3147 #define GMBUS_BYTE_COUNT_SHIFT 16
3148 #define GMBUS_BYTE_COUNT_MAX 256U
3149 #define GMBUS_SLAVE_INDEX_SHIFT 8
3150 #define GMBUS_SLAVE_ADDR_SHIFT 1
3151 #define GMBUS_SLAVE_READ (1<<0)
3152 #define GMBUS_SLAVE_WRITE (0<<0)
3153 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3154 #define GMBUS_INUSE (1<<15)
3155 #define GMBUS_HW_WAIT_PHASE (1<<14)
3156 #define GMBUS_STALL_TIMEOUT (1<<13)
3157 #define GMBUS_INT (1<<12)
3158 #define GMBUS_HW_RDY (1<<11)
3159 #define GMBUS_SATOER (1<<10)
3160 #define GMBUS_ACTIVE (1<<9)
3161 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3162 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3163 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
3164 #define GMBUS_NAK_EN (1<<3)
3165 #define GMBUS_IDLE_EN (1<<2)
3166 #define GMBUS_HW_WAIT_EN (1<<1)
3167 #define GMBUS_HW_RDY_EN (1<<0)
3168 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3169 #define GMBUS_2BYTE_INDEX_EN (1<<31)
3172 * Clock control & power management
3174 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
3175 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
3176 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
3177 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3179 #define VGA0 _MMIO(0x6000)
3180 #define VGA1 _MMIO(0x6004)
3181 #define VGA_PD _MMIO(0x6010)
3182 #define VGA0_PD_P2_DIV_4 (1 << 7)
3183 #define VGA0_PD_P1_DIV_2 (1 << 5)
3184 #define VGA0_PD_P1_SHIFT 0
3185 #define VGA0_PD_P1_MASK (0x1f << 0)
3186 #define VGA1_PD_P2_DIV_4 (1 << 15)
3187 #define VGA1_PD_P1_DIV_2 (1 << 13)
3188 #define VGA1_PD_P1_SHIFT 8
3189 #define VGA1_PD_P1_MASK (0x1f << 8)
3190 #define DPLL_VCO_ENABLE (1 << 31)
3191 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
3192 #define DPLL_DVO_2X_MODE (1 << 30)
3193 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3194 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
3195 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3196 #define DPLL_VGA_MODE_DIS (1 << 28)
3197 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3198 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3199 #define DPLL_MODE_MASK (3 << 26)
3200 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3201 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3202 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3203 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3204 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3205 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
3206 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
3207 #define DPLL_LOCK_VLV (1<<15)
3208 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
3209 #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
3210 #define DPLL_SSC_REF_CLK_CHV (1<<13)
3211 #define DPLL_PORTC_READY_MASK (0xf << 4)
3212 #define DPLL_PORTB_READY_MASK (0xf)
3214 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3216 /* Additional CHV pll/phy registers */
3217 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3218 #define DPLL_PORTD_READY_MASK (0xf)
3219 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3220 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))
3221 #define PHY_LDO_DELAY_0NS 0x0
3222 #define PHY_LDO_DELAY_200NS 0x1
3223 #define PHY_LDO_DELAY_600NS 0x2
3224 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
3225 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11))
3226 #define PHY_CH_SU_PSR 0x1
3227 #define PHY_CH_DEEP_PSR 0x7
3228 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
3229 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3230 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3231 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
3232 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch))))
3233 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline))))
3236 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3237 * this field (only one bit may be set).
3239 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3240 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3241 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3242 /* i830, required in DVO non-gang */
3243 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
3244 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3245 #define PLL_REF_INPUT_DREFCLK (0 << 13)
3246 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3247 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3248 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3249 #define PLL_REF_INPUT_MASK (3 << 13)
3250 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
3252 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3253 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3254 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
3255 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3256 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3259 * Parallel to Serial Load Pulse phase selection.
3260 * Selects the phase for the 10X DPLL clock for the PCIe
3261 * digital display port. The range is 4 to 13; 10 or more
3262 * is just a flip delay. The default is 6
3264 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3265 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3267 * SDVO multiplier for 945G/GM. Not used on 965.
3269 #define SDVO_MULTIPLIER_MASK 0x000000ff
3270 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
3271 #define SDVO_MULTIPLIER_SHIFT_VGA 0
3273 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
3274 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
3275 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
3276 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3279 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3281 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3283 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3284 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
3285 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3286 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3287 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3289 * SDVO/UDI pixel multiplier.
3291 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3292 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3293 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3294 * dummy bytes in the datastream at an increased clock rate, with both sides of
3295 * the link knowing how many bytes are fill.
3297 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3298 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3299 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3300 * through an SDVO command.
3302 * This register field has values of multiplication factor minus 1, with
3303 * a maximum multiplier of 5 for SDVO.
3305 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3306 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3308 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3309 * This best be set to the default value (3) or the CRT won't work. No,
3310 * I don't entirely understand what this does...
3312 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3313 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3315 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3317 #define _FPA0 0x6040
3318 #define _FPA1 0x6044
3319 #define _FPB0 0x6048
3320 #define _FPB1 0x604c
3321 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3322 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3323 #define FP_N_DIV_MASK 0x003f0000
3324 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3325 #define FP_N_DIV_SHIFT 16
3326 #define FP_M1_DIV_MASK 0x00003f00
3327 #define FP_M1_DIV_SHIFT 8
3328 #define FP_M2_DIV_MASK 0x0000003f
3329 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3330 #define FP_M2_DIV_SHIFT 0
3331 #define DPLL_TEST _MMIO(0x606c)
3332 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3333 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3334 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3335 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3336 #define DPLLB_TEST_N_BYPASS (1 << 19)
3337 #define DPLLB_TEST_M_BYPASS (1 << 18)
3338 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3339 #define DPLLA_TEST_N_BYPASS (1 << 3)
3340 #define DPLLA_TEST_M_BYPASS (1 << 2)
3341 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3342 #define D_STATE _MMIO(0x6104)
3343 #define DSTATE_GFX_RESET_I830 (1<<6)
3344 #define DSTATE_PLL_D3_OFF (1<<3)
3345 #define DSTATE_GFX_CLOCK_GATING (1<<1)
3346 #define DSTATE_DOT_CLOCK_GATING (1<<0)
3347 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
3348 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3349 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3350 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3351 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3352 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3353 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3354 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
3355 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
3356 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3357 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3358 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3359 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3360 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3361 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3362 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3363 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3364 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3365 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3366 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3367 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3368 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3369 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3370 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3371 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3372 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3373 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3374 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3375 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3376 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3378 * This bit must be set on the 830 to prevent hangs when turning off the
3381 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3382 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3383 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3384 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3385 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3387 #define RENCLK_GATE_D1 _MMIO(0x6204)
3388 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3389 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3390 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3391 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3392 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3393 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3394 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3395 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3396 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
3397 /* This bit must be unset on 855,865 */
3398 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
3399 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3400 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
3401 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
3402 /* This bit must be set on 855,865. */
3403 # define SV_CLOCK_GATE_DISABLE (1 << 0)
3404 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3405 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3406 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3407 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3408 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3409 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3410 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3411 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3412 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3413 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3414 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3415 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3416 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3417 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3418 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3419 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3420 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3422 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3423 /* This bit must always be set on 965G/965GM */
3424 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3425 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3426 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3427 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3428 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3429 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3430 /* This bit must always be set on 965G */
3431 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3432 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3433 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3434 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3435 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3436 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3437 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3438 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3439 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3440 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3441 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3442 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3443 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3444 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3445 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3446 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3447 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3448 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3449 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3451 #define RENCLK_GATE_D2 _MMIO(0x6208)
3452 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3453 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3454 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3456 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
3457 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3459 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3460 #define DEUC _MMIO(0x6214) /* CRL only */
3462 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3463 #define FW_CSPWRDWNEN (1<<15)
3465 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3467 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3468 #define CDCLK_FREQ_SHIFT 4
3469 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3470 #define CZCLK_FREQ_MASK 0xf
3472 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3473 #define PFI_CREDIT_63 (9 << 28) /* chv only */
3474 #define PFI_CREDIT_31 (8 << 28) /* chv only */
3475 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3476 #define PFI_CREDIT_RESEND (1 << 27)
3477 #define VGA_FAST_MODE_DISABLE (1 << 14)
3479 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3484 #define PALETTE_A_OFFSET 0xa000
3485 #define PALETTE_B_OFFSET 0xa800
3486 #define CHV_PALETTE_C_OFFSET 0xc000
3487 #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
3488 dev_priv->info.display_mmio_offset + (i) * 4)
3490 /* MCH MMIO space */
3495 * This mirrors the MCHBAR MMIO space whose location is determined by
3496 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3497 * every way. It is not accessible from the CP register read instructions.
3499 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3502 #define MCHBAR_MIRROR_BASE 0x10000
3504 #define MCHBAR_MIRROR_BASE_SNB 0x140000
3506 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3507 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3508 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3509 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3510 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3512 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3513 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3515 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3516 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3517 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3518 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3519 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3520 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
3521 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3522 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3523 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3524 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3526 /* Pineview MCH register contains DDR3 setting */
3527 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3528 #define CSHRDDR3CTL_DDR3 (1 << 2)
3530 /* 965 MCH register controlling DRAM channel configuration */
3531 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3532 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3534 /* snb MCH registers for reading the DRAM channel configuration */
3535 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3536 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3537 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3538 #define MAD_DIMM_ECC_MASK (0x3 << 24)
3539 #define MAD_DIMM_ECC_OFF (0x0 << 24)
3540 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3541 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3542 #define MAD_DIMM_ECC_ON (0x3 << 24)
3543 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3544 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3545 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3546 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3547 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3548 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3549 #define MAD_DIMM_A_SELECT (0x1 << 16)
3550 /* DIMM sizes are in multiples of 256mb. */
3551 #define MAD_DIMM_B_SIZE_SHIFT 8
3552 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3553 #define MAD_DIMM_A_SIZE_SHIFT 0
3554 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3556 /* snb MCH registers for priority tuning */
3557 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3558 #define MCH_SSKPD_WM0_MASK 0x3f
3559 #define MCH_SSKPD_WM0_VAL 0xc
3561 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3563 /* Clocking configuration register */
3564 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3565 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
3566 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3567 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3568 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3569 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
3570 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
3571 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
3573 * Note that on at least on ELK the below value is reported for both
3574 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3575 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3577 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
3578 #define CLKCFG_FSB_MASK (7 << 0)
3579 #define CLKCFG_MEM_533 (1 << 4)
3580 #define CLKCFG_MEM_667 (2 << 4)
3581 #define CLKCFG_MEM_800 (3 << 4)
3582 #define CLKCFG_MEM_MASK (7 << 4)
3584 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3585 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3587 #define TSC1 _MMIO(0x11001)
3589 #define TR1 _MMIO(0x11006)
3590 #define TSFS _MMIO(0x11020)
3591 #define TSFS_SLOPE_MASK 0x0000ff00
3592 #define TSFS_SLOPE_SHIFT 8
3593 #define TSFS_INTR_MASK 0x000000ff
3595 #define CRSTANDVID _MMIO(0x11100)
3596 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3597 #define PXVFREQ_PX_MASK 0x7f000000
3598 #define PXVFREQ_PX_SHIFT 24
3599 #define VIDFREQ_BASE _MMIO(0x11110)
3600 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3601 #define VIDFREQ2 _MMIO(0x11114)
3602 #define VIDFREQ3 _MMIO(0x11118)
3603 #define VIDFREQ4 _MMIO(0x1111c)
3604 #define VIDFREQ_P0_MASK 0x1f000000
3605 #define VIDFREQ_P0_SHIFT 24
3606 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3607 #define VIDFREQ_P0_CSCLK_SHIFT 20
3608 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3609 #define VIDFREQ_P0_CRCLK_SHIFT 16
3610 #define VIDFREQ_P1_MASK 0x00001f00
3611 #define VIDFREQ_P1_SHIFT 8
3612 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3613 #define VIDFREQ_P1_CSCLK_SHIFT 4
3614 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3615 #define INTTOEXT_BASE_ILK _MMIO(0x11300)
3616 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3617 #define INTTOEXT_MAP3_SHIFT 24
3618 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3619 #define INTTOEXT_MAP2_SHIFT 16
3620 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3621 #define INTTOEXT_MAP1_SHIFT 8
3622 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3623 #define INTTOEXT_MAP0_SHIFT 0
3624 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
3625 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
3626 #define MEMCTL_CMD_MASK 0xe000
3627 #define MEMCTL_CMD_SHIFT 13
3628 #define MEMCTL_CMD_RCLK_OFF 0
3629 #define MEMCTL_CMD_RCLK_ON 1
3630 #define MEMCTL_CMD_CHFREQ 2
3631 #define MEMCTL_CMD_CHVID 3
3632 #define MEMCTL_CMD_VMMOFF 4
3633 #define MEMCTL_CMD_VMMON 5
3634 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
3635 when command complete */
3636 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3637 #define MEMCTL_FREQ_SHIFT 8
3638 #define MEMCTL_SFCAVM (1<<7)
3639 #define MEMCTL_TGT_VID_MASK 0x007f
3640 #define MEMIHYST _MMIO(0x1117c)
3641 #define MEMINTREN _MMIO(0x11180) /* 16 bits */
3642 #define MEMINT_RSEXIT_EN (1<<8)
3643 #define MEMINT_CX_SUPR_EN (1<<7)
3644 #define MEMINT_CONT_BUSY_EN (1<<6)
3645 #define MEMINT_AVG_BUSY_EN (1<<5)
3646 #define MEMINT_EVAL_CHG_EN (1<<4)
3647 #define MEMINT_MON_IDLE_EN (1<<3)
3648 #define MEMINT_UP_EVAL_EN (1<<2)
3649 #define MEMINT_DOWN_EVAL_EN (1<<1)
3650 #define MEMINT_SW_CMD_EN (1<<0)
3651 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
3652 #define MEM_RSEXIT_MASK 0xc000
3653 #define MEM_RSEXIT_SHIFT 14
3654 #define MEM_CONT_BUSY_MASK 0x3000
3655 #define MEM_CONT_BUSY_SHIFT 12
3656 #define MEM_AVG_BUSY_MASK 0x0c00
3657 #define MEM_AVG_BUSY_SHIFT 10
3658 #define MEM_EVAL_CHG_MASK 0x0300
3659 #define MEM_EVAL_BUSY_SHIFT 8
3660 #define MEM_MON_IDLE_MASK 0x00c0
3661 #define MEM_MON_IDLE_SHIFT 6
3662 #define MEM_UP_EVAL_MASK 0x0030
3663 #define MEM_UP_EVAL_SHIFT 4
3664 #define MEM_DOWN_EVAL_MASK 0x000c
3665 #define MEM_DOWN_EVAL_SHIFT 2
3666 #define MEM_SW_CMD_MASK 0x0003
3667 #define MEM_INT_STEER_GFX 0
3668 #define MEM_INT_STEER_CMR 1
3669 #define MEM_INT_STEER_SMI 2
3670 #define MEM_INT_STEER_SCI 3
3671 #define MEMINTRSTS _MMIO(0x11184)
3672 #define MEMINT_RSEXIT (1<<7)
3673 #define MEMINT_CONT_BUSY (1<<6)
3674 #define MEMINT_AVG_BUSY (1<<5)
3675 #define MEMINT_EVAL_CHG (1<<4)
3676 #define MEMINT_MON_IDLE (1<<3)
3677 #define MEMINT_UP_EVAL (1<<2)
3678 #define MEMINT_DOWN_EVAL (1<<1)
3679 #define MEMINT_SW_CMD (1<<0)
3680 #define MEMMODECTL _MMIO(0x11190)
3681 #define MEMMODE_BOOST_EN (1<<31)
3682 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3683 #define MEMMODE_BOOST_FREQ_SHIFT 24
3684 #define MEMMODE_IDLE_MODE_MASK 0x00030000
3685 #define MEMMODE_IDLE_MODE_SHIFT 16
3686 #define MEMMODE_IDLE_MODE_EVAL 0
3687 #define MEMMODE_IDLE_MODE_CONT 1
3688 #define MEMMODE_HWIDLE_EN (1<<15)
3689 #define MEMMODE_SWMODE_EN (1<<14)
3690 #define MEMMODE_RCLK_GATE (1<<13)
3691 #define MEMMODE_HW_UPDATE (1<<12)
3692 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3693 #define MEMMODE_FSTART_SHIFT 8
3694 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3695 #define MEMMODE_FMAX_SHIFT 4
3696 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3697 #define RCBMAXAVG _MMIO(0x1119c)
3698 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
3699 #define SWMEMCMD_RENDER_OFF (0 << 13)
3700 #define SWMEMCMD_RENDER_ON (1 << 13)
3701 #define SWMEMCMD_SWFREQ (2 << 13)
3702 #define SWMEMCMD_TARVID (3 << 13)
3703 #define SWMEMCMD_VRM_OFF (4 << 13)
3704 #define SWMEMCMD_VRM_ON (5 << 13)
3705 #define CMDSTS (1<<12)
3706 #define SFCAVM (1<<11)
3707 #define SWFREQ_MASK 0x0380 /* P0-7 */
3708 #define SWFREQ_SHIFT 7
3709 #define TARVID_MASK 0x001f
3710 #define MEMSTAT_CTG _MMIO(0x111a0)
3711 #define RCBMINAVG _MMIO(0x111a0)
3712 #define RCUPEI _MMIO(0x111b0)
3713 #define RCDNEI _MMIO(0x111b4)
3714 #define RSTDBYCTL _MMIO(0x111b8)
3715 #define RS1EN (1<<31)
3716 #define RS2EN (1<<30)
3717 #define RS3EN (1<<29)
3718 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
3719 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
3720 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
3721 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
3722 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
3723 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
3724 #define RSX_STATUS_MASK (7<<20)
3725 #define RSX_STATUS_ON (0<<20)
3726 #define RSX_STATUS_RC1 (1<<20)
3727 #define RSX_STATUS_RC1E (2<<20)
3728 #define RSX_STATUS_RS1 (3<<20)
3729 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
3730 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
3731 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
3732 #define RSX_STATUS_RSVD2 (7<<20)
3733 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
3734 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
3735 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
3736 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
3737 #define RS1CONTSAV_MASK (3<<14)
3738 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
3739 #define RS1CONTSAV_RSVD (1<<14)
3740 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
3741 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
3742 #define NORMSLEXLAT_MASK (3<<12)
3743 #define SLOW_RS123 (0<<12)
3744 #define SLOW_RS23 (1<<12)
3745 #define SLOW_RS3 (2<<12)
3746 #define NORMAL_RS123 (3<<12)
3747 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
3748 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3749 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
3750 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
3751 #define RS_CSTATE_MASK (3<<4)
3752 #define RS_CSTATE_C367_RS1 (0<<4)
3753 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
3754 #define RS_CSTATE_RSVD (2<<4)
3755 #define RS_CSTATE_C367_RS2 (3<<4)
3756 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
3757 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
3758 #define VIDCTL _MMIO(0x111c0)
3759 #define VIDSTS _MMIO(0x111c8)
3760 #define VIDSTART _MMIO(0x111cc) /* 8 bits */
3761 #define MEMSTAT_ILK _MMIO(0x111f8)
3762 #define MEMSTAT_VID_MASK 0x7f00
3763 #define MEMSTAT_VID_SHIFT 8
3764 #define MEMSTAT_PSTATE_MASK 0x00f8
3765 #define MEMSTAT_PSTATE_SHIFT 3
3766 #define MEMSTAT_MON_ACTV (1<<2)
3767 #define MEMSTAT_SRC_CTL_MASK 0x0003
3768 #define MEMSTAT_SRC_CTL_CORE 0
3769 #define MEMSTAT_SRC_CTL_TRB 1
3770 #define MEMSTAT_SRC_CTL_THM 2
3771 #define MEMSTAT_SRC_CTL_STDBY 3
3772 #define RCPREVBSYTUPAVG _MMIO(0x113b8)
3773 #define RCPREVBSYTDNAVG _MMIO(0x113bc)
3774 #define PMMISC _MMIO(0x11214)
3775 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
3776 #define SDEW _MMIO(0x1124c)
3777 #define CSIEW0 _MMIO(0x11250)
3778 #define CSIEW1 _MMIO(0x11254)
3779 #define CSIEW2 _MMIO(0x11258)
3780 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
3781 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
3782 #define MCHAFE _MMIO(0x112c0)
3783 #define CSIEC _MMIO(0x112e0)
3784 #define DMIEC _MMIO(0x112e4)
3785 #define DDREC _MMIO(0x112e8)
3786 #define PEG0EC _MMIO(0x112ec)
3787 #define PEG1EC _MMIO(0x112f0)
3788 #define GFXEC _MMIO(0x112f4)
3789 #define RPPREVBSYTUPAVG _MMIO(0x113b8)
3790 #define RPPREVBSYTDNAVG _MMIO(0x113bc)
3791 #define ECR _MMIO(0x11600)
3792 #define ECR_GPFE (1<<31)
3793 #define ECR_IMONE (1<<30)
3794 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
3795 #define OGW0 _MMIO(0x11608)
3796 #define OGW1 _MMIO(0x1160c)
3797 #define EG0 _MMIO(0x11610)
3798 #define EG1 _MMIO(0x11614)
3799 #define EG2 _MMIO(0x11618)
3800 #define EG3 _MMIO(0x1161c)
3801 #define EG4 _MMIO(0x11620)
3802 #define EG5 _MMIO(0x11624)
3803 #define EG6 _MMIO(0x11628)
3804 #define EG7 _MMIO(0x1162c)
3805 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
3806 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
3807 #define LCFUSE02 _MMIO(0x116c0)
3808 #define LCFUSE_HIV_MASK 0x000000ff
3809 #define CSIPLL0 _MMIO(0x12c10)
3810 #define DDRMPLL1 _MMIO(0X12c20)
3811 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
3813 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3814 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3816 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3817 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3818 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3819 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3820 #define BXT_RP_STATE_CAP _MMIO(0x138170)
3823 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3824 * 8300) freezing up around GPU hangs. Looks as if even
3825 * scheduling/timer interrupts start misbehaving if the RPS
3826 * EI/thresholds are "bad", leading to a very sluggish or even
3829 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
3830 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
3831 #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
3832 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3833 (IS_GEN9_LP(dev_priv) ? \
3834 INTERVAL_0_833_US(us) : \
3835 INTERVAL_1_33_US(us)) : \
3836 INTERVAL_1_28_US(us))
3838 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3839 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3840 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3841 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3842 (IS_GEN9_LP(dev_priv) ? \
3843 INTERVAL_0_833_TO_US(interval) : \
3844 INTERVAL_1_33_TO_US(interval)) : \
3845 INTERVAL_1_28_TO_US(interval))
3848 * Logical Context regs
3850 #define CCID _MMIO(0x2180)
3851 #define CCID_EN BIT(0)
3852 #define CCID_EXTENDED_STATE_RESTORE BIT(2)
3853 #define CCID_EXTENDED_STATE_SAVE BIT(3)
3855 * Notes on SNB/IVB/VLV context size:
3856 * - Power context is saved elsewhere (LLC or stolen)
3857 * - Ring/execlist context is saved on SNB, not on IVB
3858 * - Extended context size already includes render context size
3859 * - We always need to follow the extended context size.
3860 * SNB BSpec has comments indicating that we should use the
3861 * render context size instead if execlists are disabled, but
3862 * based on empirical testing that's just nonsense.
3863 * - Pipelined/VF state is saved on SNB/IVB respectively
3864 * - GT1 size just indicates how much of render context
3865 * doesn't need saving on GT1
3867 #define CXT_SIZE _MMIO(0x21a0)
3868 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3869 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3870 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3871 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3872 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
3873 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
3874 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3875 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3876 #define GEN7_CXT_SIZE _MMIO(0x21a8)
3877 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3878 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3879 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3880 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3881 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3882 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
3883 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3884 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3887 INTEL_ADVANCED_CONTEXT = 0,
3888 INTEL_LEGACY_32B_CONTEXT,
3889 INTEL_ADVANCED_AD_CONTEXT,
3890 INTEL_LEGACY_64B_CONTEXT
3895 FAULT_AND_HALT, /* Debug only */
3897 FAULT_AND_CONTINUE /* Unsupported */
3900 #define GEN8_CTX_VALID (1<<0)
3901 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
3902 #define GEN8_CTX_FORCE_RESTORE (1<<2)
3903 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
3904 #define GEN8_CTX_PRIVILEGE (1<<8)
3905 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3907 #define GEN8_CTX_ID_SHIFT 32
3908 #define GEN8_CTX_ID_WIDTH 21
3910 #define CHV_CLK_CTL1 _MMIO(0x101100)
3911 #define VLV_CLK_CTL2 _MMIO(0x101104)
3912 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
3918 #define OVADD _MMIO(0x30000)
3919 #define DOVSTA _MMIO(0x30008)
3920 #define OC_BUF (0x3<<20)
3921 #define OGAMC5 _MMIO(0x30010)
3922 #define OGAMC4 _MMIO(0x30014)
3923 #define OGAMC3 _MMIO(0x30018)
3924 #define OGAMC2 _MMIO(0x3001c)
3925 #define OGAMC1 _MMIO(0x30020)
3926 #define OGAMC0 _MMIO(0x30024)
3929 * GEN9 clock gating regs
3931 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
3932 #define DARBF_GATING_DIS (1 << 27)
3933 #define PWM2_GATING_DIS (1 << 14)
3934 #define PWM1_GATING_DIS (1 << 13)
3936 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
3937 #define BXT_GMBUS_GATING_DIS (1 << 14)
3939 #define _CLKGATE_DIS_PSL_A 0x46520
3940 #define _CLKGATE_DIS_PSL_B 0x46524
3941 #define _CLKGATE_DIS_PSL_C 0x46528
3942 #define DPF_GATING_DIS (1 << 10)
3943 #define DPF_RAM_GATING_DIS (1 << 9)
3944 #define DPFR_GATING_DIS (1 << 8)
3946 #define CLKGATE_DIS_PSL(pipe) \
3947 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
3950 * GEN10 clock gating regs
3952 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
3953 #define SARBUNIT_CLKGATE_DIS (1 << 5)
3954 #define RCCUNIT_CLKGATE_DIS (1 << 7)
3956 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
3957 #define VFUNIT_CLKGATE_DIS (1 << 20)
3960 * Display engine regs
3963 /* Pipe A CRC regs */
3964 #define _PIPE_CRC_CTL_A 0x60050
3965 #define PIPE_CRC_ENABLE (1 << 31)
3966 /* ivb+ source selection */
3967 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3968 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3969 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
3970 /* ilk+ source selection */
3971 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3972 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3973 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
3974 /* embedded DP port on the north display block, reserved on ivb */
3975 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
3976 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
3977 /* vlv source selection */
3978 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
3979 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
3980 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
3981 /* with DP port the pipe source is invalid */
3982 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
3983 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
3984 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
3985 /* gen3+ source selection */
3986 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
3987 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
3988 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
3989 /* with DP/TV port the pipe source is invalid */
3990 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
3991 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
3992 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
3993 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
3994 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
3995 /* gen2 doesn't have source selection bits */
3996 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
3998 #define _PIPE_CRC_RES_1_A_IVB 0x60064
3999 #define _PIPE_CRC_RES_2_A_IVB 0x60068
4000 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
4001 #define _PIPE_CRC_RES_4_A_IVB 0x60070
4002 #define _PIPE_CRC_RES_5_A_IVB 0x60074
4004 #define _PIPE_CRC_RES_RED_A 0x60060
4005 #define _PIPE_CRC_RES_GREEN_A 0x60064
4006 #define _PIPE_CRC_RES_BLUE_A 0x60068
4007 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4008 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
4010 /* Pipe B CRC regs */
4011 #define _PIPE_CRC_RES_1_B_IVB 0x61064
4012 #define _PIPE_CRC_RES_2_B_IVB 0x61068
4013 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
4014 #define _PIPE_CRC_RES_4_B_IVB 0x61070
4015 #define _PIPE_CRC_RES_5_B_IVB 0x61074
4017 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4018 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4019 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4020 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4021 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4022 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4024 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4025 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4026 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4027 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4028 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4030 /* Pipe A timing regs */
4031 #define _HTOTAL_A 0x60000
4032 #define _HBLANK_A 0x60004
4033 #define _HSYNC_A 0x60008
4034 #define _VTOTAL_A 0x6000c
4035 #define _VBLANK_A 0x60010
4036 #define _VSYNC_A 0x60014
4037 #define _PIPEASRC 0x6001c
4038 #define _BCLRPAT_A 0x60020
4039 #define _VSYNCSHIFT_A 0x60028
4040 #define _PIPE_MULT_A 0x6002c
4042 /* Pipe B timing regs */
4043 #define _HTOTAL_B 0x61000
4044 #define _HBLANK_B 0x61004
4045 #define _HSYNC_B 0x61008
4046 #define _VTOTAL_B 0x6100c
4047 #define _VBLANK_B 0x61010
4048 #define _VSYNC_B 0x61014
4049 #define _PIPEBSRC 0x6101c
4050 #define _BCLRPAT_B 0x61020
4051 #define _VSYNCSHIFT_B 0x61028
4052 #define _PIPE_MULT_B 0x6102c
4054 #define TRANSCODER_A_OFFSET 0x60000
4055 #define TRANSCODER_B_OFFSET 0x61000
4056 #define TRANSCODER_C_OFFSET 0x62000
4057 #define CHV_TRANSCODER_C_OFFSET 0x63000
4058 #define TRANSCODER_EDP_OFFSET 0x6f000
4060 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
4061 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
4062 dev_priv->info.display_mmio_offset)
4064 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4065 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4066 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4067 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4068 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4069 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4070 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4071 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4072 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4073 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4075 /* VLV eDP PSR registers */
4076 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
4077 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
4078 #define VLV_EDP_PSR_ENABLE (1<<0)
4079 #define VLV_EDP_PSR_RESET (1<<1)
4080 #define VLV_EDP_PSR_MODE_MASK (7<<2)
4081 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
4082 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
4083 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
4084 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
4085 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
4086 #define VLV_EDP_PSR_DBL_FRAME (1<<10)
4087 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
4088 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
4089 #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
4091 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
4092 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
4093 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
4094 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
4095 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
4096 #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
4098 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
4099 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
4100 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
4101 #define VLV_EDP_PSR_CURR_STATE_MASK 7
4102 #define VLV_EDP_PSR_DISABLED (0<<0)
4103 #define VLV_EDP_PSR_INACTIVE (1<<0)
4104 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
4105 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
4106 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
4107 #define VLV_EDP_PSR_EXIT (5<<0)
4108 #define VLV_EDP_PSR_IN_TRANS (1<<7)
4109 #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
4111 /* HSW+ eDP PSR registers */
4112 #define HSW_EDP_PSR_BASE 0x64800
4113 #define BDW_EDP_PSR_BASE 0x6f800
4114 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
4115 #define EDP_PSR_ENABLE (1<<31)
4116 #define BDW_PSR_SINGLE_FRAME (1<<30)
4117 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */
4118 #define EDP_PSR_LINK_STANDBY (1<<27)
4119 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
4120 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
4121 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
4122 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
4123 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
4124 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4125 #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
4126 #define EDP_PSR_TP1_TP2_SEL (0<<11)
4127 #define EDP_PSR_TP1_TP3_SEL (1<<11)
4128 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
4129 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
4130 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
4131 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
4132 #define EDP_PSR_TP1_TIME_500us (0<<4)
4133 #define EDP_PSR_TP1_TIME_100us (1<<4)
4134 #define EDP_PSR_TP1_TIME_2500us (2<<4)
4135 #define EDP_PSR_TP1_TIME_0us (3<<4)
4136 #define EDP_PSR_IDLE_FRAME_SHIFT 0
4138 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4139 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4141 #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
4142 #define EDP_PSR_STATUS_STATE_MASK (7<<29)
4143 #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
4144 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
4145 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
4146 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
4147 #define EDP_PSR_STATUS_STATE_BUFON (4<<29)
4148 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
4149 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
4150 #define EDP_PSR_STATUS_LINK_MASK (3<<26)
4151 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
4152 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
4153 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
4154 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4155 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4156 #define EDP_PSR_STATUS_COUNT_SHIFT 16
4157 #define EDP_PSR_STATUS_COUNT_MASK 0xf
4158 #define EDP_PSR_STATUS_AUX_ERROR (1<<15)
4159 #define EDP_PSR_STATUS_AUX_SENDING (1<<12)
4160 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
4161 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
4162 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
4163 #define EDP_PSR_STATUS_IDLE_MASK 0xf
4165 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
4166 #define EDP_PSR_PERF_CNT_MASK 0xffffff
4168 #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60)
4169 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28)
4170 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
4171 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
4172 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
4173 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1<<16)
4174 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
4176 #define EDP_PSR2_CTL _MMIO(0x6f900)
4177 #define EDP_PSR2_ENABLE (1<<31)
4178 #define EDP_SU_TRACK_ENABLE (1<<30)
4179 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
4180 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
4181 #define EDP_PSR2_TP2_TIME_500 (0<<8)
4182 #define EDP_PSR2_TP2_TIME_100 (1<<8)
4183 #define EDP_PSR2_TP2_TIME_2500 (2<<8)
4184 #define EDP_PSR2_TP2_TIME_50 (3<<8)
4185 #define EDP_PSR2_TP2_TIME_MASK (3<<8)
4186 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4187 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
4188 #define EDP_PSR2_IDLE_MASK 0xf
4189 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
4191 #define EDP_PSR2_STATUS _MMIO(0x6f940)
4192 #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
4193 #define EDP_PSR2_STATUS_STATE_SHIFT 28
4195 /* VGA port control */
4196 #define ADPA _MMIO(0x61100)
4197 #define PCH_ADPA _MMIO(0xe1100)
4198 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4200 #define ADPA_DAC_ENABLE (1<<31)
4201 #define ADPA_DAC_DISABLE 0
4202 #define ADPA_PIPE_SELECT_MASK (1<<30)
4203 #define ADPA_PIPE_A_SELECT 0
4204 #define ADPA_PIPE_B_SELECT (1<<30)
4205 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
4206 /* CPT uses bits 29:30 for pch transcoder select */
4207 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4208 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
4209 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
4210 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
4211 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
4212 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
4213 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
4214 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
4215 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
4216 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
4217 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
4218 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
4219 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
4220 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
4221 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
4222 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
4223 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
4224 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
4225 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
4226 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
4227 #define ADPA_SETS_HVPOLARITY 0
4228 #define ADPA_VSYNC_CNTL_DISABLE (1<<10)
4229 #define ADPA_VSYNC_CNTL_ENABLE 0
4230 #define ADPA_HSYNC_CNTL_DISABLE (1<<11)
4231 #define ADPA_HSYNC_CNTL_ENABLE 0
4232 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
4233 #define ADPA_VSYNC_ACTIVE_LOW 0
4234 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
4235 #define ADPA_HSYNC_ACTIVE_LOW 0
4236 #define ADPA_DPMS_MASK (~(3<<10))
4237 #define ADPA_DPMS_ON (0<<10)
4238 #define ADPA_DPMS_SUSPEND (1<<10)
4239 #define ADPA_DPMS_STANDBY (2<<10)
4240 #define ADPA_DPMS_OFF (3<<10)
4243 /* Hotplug control (945+ only) */
4244 #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
4245 #define PORTB_HOTPLUG_INT_EN (1 << 29)
4246 #define PORTC_HOTPLUG_INT_EN (1 << 28)
4247 #define PORTD_HOTPLUG_INT_EN (1 << 27)
4248 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
4249 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
4250 #define TV_HOTPLUG_INT_EN (1 << 18)
4251 #define CRT_HOTPLUG_INT_EN (1 << 9)
4252 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4253 PORTC_HOTPLUG_INT_EN | \
4254 PORTD_HOTPLUG_INT_EN | \
4255 SDVOC_HOTPLUG_INT_EN | \
4256 SDVOB_HOTPLUG_INT_EN | \
4258 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
4259 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4260 /* must use period 64 on GM45 according to docs */
4261 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4262 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4263 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4264 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4265 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4266 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4267 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4268 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4269 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4270 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4271 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4272 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4274 #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
4276 * HDMI/DP bits are g4x+
4278 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4279 * Please check the detailed lore in the commit message for for experimental
4282 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4283 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4284 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4285 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4286 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4287 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
4288 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
4289 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
4290 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
4291 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4292 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
4293 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
4294 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4295 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
4296 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
4297 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4298 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
4299 /* CRT/TV common between gen3+ */
4300 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
4301 #define TV_HOTPLUG_INT_STATUS (1 << 10)
4302 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4303 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4304 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4305 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4306 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4307 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4308 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
4309 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4311 /* SDVO is different across gen3/4 */
4312 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4313 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4315 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4316 * since reality corrobates that they're the same as on gen3. But keep these
4317 * bits here (and the comment!) to help any other lost wanderers back onto the
4320 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4321 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4322 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4323 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
4324 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4325 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4326 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4327 PORTB_HOTPLUG_INT_STATUS | \
4328 PORTC_HOTPLUG_INT_STATUS | \
4329 PORTD_HOTPLUG_INT_STATUS)
4331 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4332 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4333 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4334 PORTB_HOTPLUG_INT_STATUS | \
4335 PORTC_HOTPLUG_INT_STATUS | \
4336 PORTD_HOTPLUG_INT_STATUS)
4338 /* SDVO and HDMI port control.
4339 * The same register may be used for SDVO or HDMI */
4340 #define _GEN3_SDVOB 0x61140
4341 #define _GEN3_SDVOC 0x61160
4342 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4343 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
4344 #define GEN4_HDMIB GEN3_SDVOB
4345 #define GEN4_HDMIC GEN3_SDVOC
4346 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4347 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4348 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4349 #define PCH_SDVOB _MMIO(0xe1140)
4350 #define PCH_HDMIB PCH_SDVOB
4351 #define PCH_HDMIC _MMIO(0xe1150)
4352 #define PCH_HDMID _MMIO(0xe1160)
4354 #define PORT_DFT_I9XX _MMIO(0x61150)
4355 #define DC_BALANCE_RESET (1 << 25)
4356 #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
4357 #define DC_BALANCE_RESET_VLV (1 << 31)
4358 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4359 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
4360 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
4361 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
4363 /* Gen 3 SDVO bits: */
4364 #define SDVO_ENABLE (1 << 31)
4365 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4366 #define SDVO_PIPE_SEL_MASK (1 << 30)
4367 #define SDVO_PIPE_B_SELECT (1 << 30)
4368 #define SDVO_STALL_SELECT (1 << 29)
4369 #define SDVO_INTERRUPT_ENABLE (1 << 26)
4371 * 915G/GM SDVO pixel multiplier.
4372 * Programmed value is multiplier - 1, up to 5x.
4373 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4375 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
4376 #define SDVO_PORT_MULTIPLY_SHIFT 23
4377 #define SDVO_PHASE_SELECT_MASK (15 << 19)
4378 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4379 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4380 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
4381 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
4382 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
4383 #define SDVO_DETECTED (1 << 2)
4384 /* Bits to be preserved when writing */
4385 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4386 SDVO_INTERRUPT_ENABLE)
4387 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4389 /* Gen 4 SDVO/HDMI bits: */
4390 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
4391 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
4392 #define SDVO_ENCODING_SDVO (0 << 10)
4393 #define SDVO_ENCODING_HDMI (2 << 10)
4394 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4395 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4396 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
4397 #define SDVO_AUDIO_ENABLE (1 << 6)
4398 /* VSYNC/HSYNC bits new with 965, default is to be set */
4399 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4400 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4402 /* Gen 5 (IBX) SDVO/HDMI bits: */
4403 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
4404 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
4406 /* Gen 6 (CPT) SDVO/HDMI bits: */
4407 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4408 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
4410 /* CHV SDVO/HDMI bits: */
4411 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4412 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4415 /* DVO port control */
4416 #define _DVOA 0x61120
4417 #define DVOA _MMIO(_DVOA)
4418 #define _DVOB 0x61140
4419 #define DVOB _MMIO(_DVOB)
4420 #define _DVOC 0x61160
4421 #define DVOC _MMIO(_DVOC)
4422 #define DVO_ENABLE (1 << 31)
4423 #define DVO_PIPE_B_SELECT (1 << 30)
4424 #define DVO_PIPE_STALL_UNUSED (0 << 28)
4425 #define DVO_PIPE_STALL (1 << 28)
4426 #define DVO_PIPE_STALL_TV (2 << 28)
4427 #define DVO_PIPE_STALL_MASK (3 << 28)
4428 #define DVO_USE_VGA_SYNC (1 << 15)
4429 #define DVO_DATA_ORDER_I740 (0 << 14)
4430 #define DVO_DATA_ORDER_FP (1 << 14)
4431 #define DVO_VSYNC_DISABLE (1 << 11)
4432 #define DVO_HSYNC_DISABLE (1 << 10)
4433 #define DVO_VSYNC_TRISTATE (1 << 9)
4434 #define DVO_HSYNC_TRISTATE (1 << 8)
4435 #define DVO_BORDER_ENABLE (1 << 7)
4436 #define DVO_DATA_ORDER_GBRG (1 << 6)
4437 #define DVO_DATA_ORDER_RGGB (0 << 6)
4438 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4439 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4440 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4441 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4442 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4443 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
4444 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
4445 #define DVO_PRESERVE_MASK (0x7<<24)
4446 #define DVOA_SRCDIM _MMIO(0x61124)
4447 #define DVOB_SRCDIM _MMIO(0x61144)
4448 #define DVOC_SRCDIM _MMIO(0x61164)
4449 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4450 #define DVO_SRCDIM_VERTICAL_SHIFT 0
4452 /* LVDS port control */
4453 #define LVDS _MMIO(0x61180)
4455 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4456 * the DPLL semantics change when the LVDS is assigned to that pipe.
4458 #define LVDS_PORT_EN (1 << 31)
4459 /* Selects pipe B for LVDS data. Must be set on pre-965. */
4460 #define LVDS_PIPEB_SELECT (1 << 30)
4461 #define LVDS_PIPE_MASK (1 << 30)
4462 #define LVDS_PIPE(pipe) ((pipe) << 30)
4463 /* LVDS dithering flag on 965/g4x platform */
4464 #define LVDS_ENABLE_DITHER (1 << 25)
4465 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4466 #define LVDS_VSYNC_POLARITY (1 << 21)
4467 #define LVDS_HSYNC_POLARITY (1 << 20)
4469 /* Enable border for unscaled (or aspect-scaled) display */
4470 #define LVDS_BORDER_ENABLE (1 << 15)
4472 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4475 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
4476 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
4477 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
4479 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4480 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4483 #define LVDS_A3_POWER_MASK (3 << 6)
4484 #define LVDS_A3_POWER_DOWN (0 << 6)
4485 #define LVDS_A3_POWER_UP (3 << 6)
4487 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
4490 #define LVDS_CLKB_POWER_MASK (3 << 4)
4491 #define LVDS_CLKB_POWER_DOWN (0 << 4)
4492 #define LVDS_CLKB_POWER_UP (3 << 4)
4494 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4495 * setting for whether we are in dual-channel mode. The B3 pair will
4496 * additionally only be powered up when LVDS_A3_POWER_UP is set.
4498 #define LVDS_B0B3_POWER_MASK (3 << 2)
4499 #define LVDS_B0B3_POWER_DOWN (0 << 2)
4500 #define LVDS_B0B3_POWER_UP (3 << 2)
4502 /* Video Data Island Packet control */
4503 #define VIDEO_DIP_DATA _MMIO(0x61178)
4504 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4505 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4506 * of the infoframe structure specified by CEA-861. */
4507 #define VIDEO_DIP_DATA_SIZE 32
4508 #define VIDEO_DIP_VSC_DATA_SIZE 36
4509 #define VIDEO_DIP_CTL _MMIO(0x61170)
4511 #define VIDEO_DIP_ENABLE (1 << 31)
4512 #define VIDEO_DIP_PORT(port) ((port) << 29)
4513 #define VIDEO_DIP_PORT_MASK (3 << 29)
4514 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
4515 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
4516 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
4517 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
4518 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
4519 #define VIDEO_DIP_SELECT_AVI (0 << 19)
4520 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
4521 #define VIDEO_DIP_SELECT_SPD (3 << 19)
4522 #define VIDEO_DIP_SELECT_MASK (3 << 19)
4523 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
4524 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
4525 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4526 #define VIDEO_DIP_FREQ_MASK (3 << 16)
4527 /* HSW and later: */
4528 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4529 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4530 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
4531 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4532 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4533 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4535 /* Panel power sequencing */
4536 #define PPS_BASE 0x61200
4537 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
4538 #define PCH_PPS_BASE 0xC7200
4540 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4541 PPS_BASE + (reg) + \
4544 #define _PP_STATUS 0x61200
4545 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4546 #define PP_ON (1 << 31)
4548 * Indicates that all dependencies of the panel are on:
4552 * - LVDS/DVOB/DVOC on
4554 #define PP_READY (1 << 30)
4555 #define PP_SEQUENCE_NONE (0 << 28)
4556 #define PP_SEQUENCE_POWER_UP (1 << 28)
4557 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
4558 #define PP_SEQUENCE_MASK (3 << 28)
4559 #define PP_SEQUENCE_SHIFT 28
4560 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
4561 #define PP_SEQUENCE_STATE_MASK 0x0000000f
4562 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
4563 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
4564 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
4565 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
4566 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
4567 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
4568 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
4569 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
4570 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
4572 #define _PP_CONTROL 0x61204
4573 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4574 #define PANEL_UNLOCK_REGS (0xabcd << 16)
4575 #define PANEL_UNLOCK_MASK (0xffff << 16)
4576 #define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
4577 #define BXT_POWER_CYCLE_DELAY_SHIFT 4
4578 #define EDP_FORCE_VDD (1 << 3)
4579 #define EDP_BLC_ENABLE (1 << 2)
4580 #define PANEL_POWER_RESET (1 << 1)
4581 #define PANEL_POWER_OFF (0 << 0)
4582 #define PANEL_POWER_ON (1 << 0)
4584 #define _PP_ON_DELAYS 0x61208
4585 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4586 #define PANEL_PORT_SELECT_SHIFT 30
4587 #define PANEL_PORT_SELECT_MASK (3 << 30)
4588 #define PANEL_PORT_SELECT_LVDS (0 << 30)
4589 #define PANEL_PORT_SELECT_DPA (1 << 30)
4590 #define PANEL_PORT_SELECT_DPC (2 << 30)
4591 #define PANEL_PORT_SELECT_DPD (3 << 30)
4592 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
4593 #define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
4594 #define PANEL_POWER_UP_DELAY_SHIFT 16
4595 #define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
4596 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
4598 #define _PP_OFF_DELAYS 0x6120C
4599 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4600 #define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
4601 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
4602 #define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
4603 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4605 #define _PP_DIVISOR 0x61210
4606 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4607 #define PP_REFERENCE_DIVIDER_MASK 0xffffff00
4608 #define PP_REFERENCE_DIVIDER_SHIFT 8
4609 #define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
4610 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4613 #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
4614 #define PFIT_ENABLE (1 << 31)
4615 #define PFIT_PIPE_MASK (3 << 29)
4616 #define PFIT_PIPE_SHIFT 29
4617 #define VERT_INTERP_DISABLE (0 << 10)
4618 #define VERT_INTERP_BILINEAR (1 << 10)
4619 #define VERT_INTERP_MASK (3 << 10)
4620 #define VERT_AUTO_SCALE (1 << 9)
4621 #define HORIZ_INTERP_DISABLE (0 << 6)
4622 #define HORIZ_INTERP_BILINEAR (1 << 6)
4623 #define HORIZ_INTERP_MASK (3 << 6)
4624 #define HORIZ_AUTO_SCALE (1 << 5)
4625 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
4626 #define PFIT_FILTER_FUZZY (0 << 24)
4627 #define PFIT_SCALING_AUTO (0 << 26)
4628 #define PFIT_SCALING_PROGRAMMED (1 << 26)
4629 #define PFIT_SCALING_PILLAR (2 << 26)
4630 #define PFIT_SCALING_LETTER (3 << 26)
4631 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
4633 #define PFIT_VERT_SCALE_SHIFT 20
4634 #define PFIT_VERT_SCALE_MASK 0xfff00000
4635 #define PFIT_HORIZ_SCALE_SHIFT 4
4636 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
4638 #define PFIT_VERT_SCALE_SHIFT_965 16
4639 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
4640 #define PFIT_HORIZ_SCALE_SHIFT_965 0
4641 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4643 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
4645 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
4646 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
4647 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4648 _VLV_BLC_PWM_CTL2_B)
4650 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
4651 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
4652 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4655 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
4656 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
4657 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4658 _VLV_BLC_HIST_CTL_B)
4660 /* Backlight control */
4661 #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
4662 #define BLM_PWM_ENABLE (1 << 31)
4663 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
4664 #define BLM_PIPE_SELECT (1 << 29)
4665 #define BLM_PIPE_SELECT_IVB (3 << 29)
4666 #define BLM_PIPE_A (0 << 29)
4667 #define BLM_PIPE_B (1 << 29)
4668 #define BLM_PIPE_C (2 << 29) /* ivb + */
4669 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
4670 #define BLM_TRANSCODER_B BLM_PIPE_B
4671 #define BLM_TRANSCODER_C BLM_PIPE_C
4672 #define BLM_TRANSCODER_EDP (3 << 29)
4673 #define BLM_PIPE(pipe) ((pipe) << 29)
4674 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
4675 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
4676 #define BLM_PHASE_IN_ENABLE (1 << 25)
4677 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
4678 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
4679 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
4680 #define BLM_PHASE_IN_COUNT_SHIFT (8)
4681 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4682 #define BLM_PHASE_IN_INCR_SHIFT (0)
4683 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
4684 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
4686 * This is the most significant 15 bits of the number of backlight cycles in a
4687 * complete cycle of the modulated backlight control.
4689 * The actual value is this field multiplied by two.
4691 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
4692 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
4693 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
4695 * This is the number of cycles out of the backlight modulation cycle for which
4696 * the backlight is on.
4698 * This field must be no greater than the number of cycles in the complete
4699 * backlight modulation cycle.
4701 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
4702 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
4703 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4704 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
4706 #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
4707 #define BLM_HISTOGRAM_ENABLE (1 << 31)
4709 /* New registers for PCH-split platforms. Safe where new bits show up, the
4710 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
4711 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
4712 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
4714 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
4716 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4717 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
4718 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
4719 #define BLM_PCH_PWM_ENABLE (1 << 31)
4720 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
4721 #define BLM_PCH_POLARITY (1 << 29)
4722 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
4724 #define UTIL_PIN_CTL _MMIO(0x48400)
4725 #define UTIL_PIN_ENABLE (1 << 31)
4727 #define UTIL_PIN_PIPE(x) ((x) << 29)
4728 #define UTIL_PIN_PIPE_MASK (3 << 29)
4729 #define UTIL_PIN_MODE_PWM (1 << 24)
4730 #define UTIL_PIN_MODE_MASK (0xf << 24)
4731 #define UTIL_PIN_POLARITY (1 << 22)
4733 /* BXT backlight register definition. */
4734 #define _BXT_BLC_PWM_CTL1 0xC8250
4735 #define BXT_BLC_PWM_ENABLE (1 << 31)
4736 #define BXT_BLC_PWM_POLARITY (1 << 29)
4737 #define _BXT_BLC_PWM_FREQ1 0xC8254
4738 #define _BXT_BLC_PWM_DUTY1 0xC8258
4740 #define _BXT_BLC_PWM_CTL2 0xC8350
4741 #define _BXT_BLC_PWM_FREQ2 0xC8354
4742 #define _BXT_BLC_PWM_DUTY2 0xC8358
4744 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
4745 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4746 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
4747 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4748 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
4749 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4751 #define PCH_GTC_CTL _MMIO(0xe7000)
4752 #define PCH_GTC_ENABLE (1 << 31)
4754 /* TV port control */
4755 #define TV_CTL _MMIO(0x68000)
4756 /* Enables the TV encoder */
4757 # define TV_ENC_ENABLE (1 << 31)
4758 /* Sources the TV encoder input from pipe B instead of A. */
4759 # define TV_ENC_PIPEB_SELECT (1 << 30)
4760 /* Outputs composite video (DAC A only) */
4761 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
4762 /* Outputs SVideo video (DAC B/C) */
4763 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
4764 /* Outputs Component video (DAC A/B/C) */
4765 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
4766 /* Outputs Composite and SVideo (DAC A/B/C) */
4767 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4768 # define TV_TRILEVEL_SYNC (1 << 21)
4769 /* Enables slow sync generation (945GM only) */
4770 # define TV_SLOW_SYNC (1 << 20)
4771 /* Selects 4x oversampling for 480i and 576p */
4772 # define TV_OVERSAMPLE_4X (0 << 18)
4773 /* Selects 2x oversampling for 720p and 1080i */
4774 # define TV_OVERSAMPLE_2X (1 << 18)
4775 /* Selects no oversampling for 1080p */
4776 # define TV_OVERSAMPLE_NONE (2 << 18)
4777 /* Selects 8x oversampling */
4778 # define TV_OVERSAMPLE_8X (3 << 18)
4779 /* Selects progressive mode rather than interlaced */
4780 # define TV_PROGRESSIVE (1 << 17)
4781 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
4782 # define TV_PAL_BURST (1 << 16)
4783 /* Field for setting delay of Y compared to C */
4784 # define TV_YC_SKEW_MASK (7 << 12)
4785 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
4786 # define TV_ENC_SDP_FIX (1 << 11)
4788 * Enables a fix for the 915GM only.
4790 * Not sure what it does.
4792 # define TV_ENC_C0_FIX (1 << 10)
4793 /* Bits that must be preserved by software */
4794 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
4795 # define TV_FUSE_STATE_MASK (3 << 4)
4796 /* Read-only state that reports all features enabled */
4797 # define TV_FUSE_STATE_ENABLED (0 << 4)
4798 /* Read-only state that reports that Macrovision is disabled in hardware*/
4799 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
4800 /* Read-only state that reports that TV-out is disabled in hardware. */
4801 # define TV_FUSE_STATE_DISABLED (2 << 4)
4802 /* Normal operation */
4803 # define TV_TEST_MODE_NORMAL (0 << 0)
4804 /* Encoder test pattern 1 - combo pattern */
4805 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
4806 /* Encoder test pattern 2 - full screen vertical 75% color bars */
4807 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
4808 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
4809 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
4810 /* Encoder test pattern 4 - random noise */
4811 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
4812 /* Encoder test pattern 5 - linear color ramps */
4813 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
4815 * This test mode forces the DACs to 50% of full output.
4817 * This is used for load detection in combination with TVDAC_SENSE_MASK
4819 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
4820 # define TV_TEST_MODE_MASK (7 << 0)
4822 #define TV_DAC _MMIO(0x68004)
4823 # define TV_DAC_SAVE 0x00ffff00
4825 * Reports that DAC state change logic has reported change (RO).
4827 * This gets cleared when TV_DAC_STATE_EN is cleared
4829 # define TVDAC_STATE_CHG (1 << 31)
4830 # define TVDAC_SENSE_MASK (7 << 28)
4831 /* Reports that DAC A voltage is above the detect threshold */
4832 # define TVDAC_A_SENSE (1 << 30)
4833 /* Reports that DAC B voltage is above the detect threshold */
4834 # define TVDAC_B_SENSE (1 << 29)
4835 /* Reports that DAC C voltage is above the detect threshold */
4836 # define TVDAC_C_SENSE (1 << 28)
4838 * Enables DAC state detection logic, for load-based TV detection.
4840 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
4841 * to off, for load detection to work.
4843 # define TVDAC_STATE_CHG_EN (1 << 27)
4844 /* Sets the DAC A sense value to high */
4845 # define TVDAC_A_SENSE_CTL (1 << 26)
4846 /* Sets the DAC B sense value to high */
4847 # define TVDAC_B_SENSE_CTL (1 << 25)
4848 /* Sets the DAC C sense value to high */
4849 # define TVDAC_C_SENSE_CTL (1 << 24)
4850 /* Overrides the ENC_ENABLE and DAC voltage levels */
4851 # define DAC_CTL_OVERRIDE (1 << 7)
4852 /* Sets the slew rate. Must be preserved in software */
4853 # define ENC_TVDAC_SLEW_FAST (1 << 6)
4854 # define DAC_A_1_3_V (0 << 4)
4855 # define DAC_A_1_1_V (1 << 4)
4856 # define DAC_A_0_7_V (2 << 4)
4857 # define DAC_A_MASK (3 << 4)
4858 # define DAC_B_1_3_V (0 << 2)
4859 # define DAC_B_1_1_V (1 << 2)
4860 # define DAC_B_0_7_V (2 << 2)
4861 # define DAC_B_MASK (3 << 2)
4862 # define DAC_C_1_3_V (0 << 0)
4863 # define DAC_C_1_1_V (1 << 0)
4864 # define DAC_C_0_7_V (2 << 0)
4865 # define DAC_C_MASK (3 << 0)
4868 * CSC coefficients are stored in a floating point format with 9 bits of
4869 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
4870 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
4871 * -1 (0x3) being the only legal negative value.
4873 #define TV_CSC_Y _MMIO(0x68010)
4874 # define TV_RY_MASK 0x07ff0000
4875 # define TV_RY_SHIFT 16
4876 # define TV_GY_MASK 0x00000fff
4877 # define TV_GY_SHIFT 0
4879 #define TV_CSC_Y2 _MMIO(0x68014)
4880 # define TV_BY_MASK 0x07ff0000
4881 # define TV_BY_SHIFT 16
4883 * Y attenuation for component video.
4885 * Stored in 1.9 fixed point.
4887 # define TV_AY_MASK 0x000003ff
4888 # define TV_AY_SHIFT 0
4890 #define TV_CSC_U _MMIO(0x68018)
4891 # define TV_RU_MASK 0x07ff0000
4892 # define TV_RU_SHIFT 16
4893 # define TV_GU_MASK 0x000007ff
4894 # define TV_GU_SHIFT 0
4896 #define TV_CSC_U2 _MMIO(0x6801c)
4897 # define TV_BU_MASK 0x07ff0000
4898 # define TV_BU_SHIFT 16
4900 * U attenuation for component video.
4902 * Stored in 1.9 fixed point.
4904 # define TV_AU_MASK 0x000003ff
4905 # define TV_AU_SHIFT 0
4907 #define TV_CSC_V _MMIO(0x68020)
4908 # define TV_RV_MASK 0x0fff0000
4909 # define TV_RV_SHIFT 16
4910 # define TV_GV_MASK 0x000007ff
4911 # define TV_GV_SHIFT 0
4913 #define TV_CSC_V2 _MMIO(0x68024)
4914 # define TV_BV_MASK 0x07ff0000
4915 # define TV_BV_SHIFT 16
4917 * V attenuation for component video.
4919 * Stored in 1.9 fixed point.
4921 # define TV_AV_MASK 0x000007ff
4922 # define TV_AV_SHIFT 0
4924 #define TV_CLR_KNOBS _MMIO(0x68028)
4925 /* 2s-complement brightness adjustment */
4926 # define TV_BRIGHTNESS_MASK 0xff000000
4927 # define TV_BRIGHTNESS_SHIFT 24
4928 /* Contrast adjustment, as a 2.6 unsigned floating point number */
4929 # define TV_CONTRAST_MASK 0x00ff0000
4930 # define TV_CONTRAST_SHIFT 16
4931 /* Saturation adjustment, as a 2.6 unsigned floating point number */
4932 # define TV_SATURATION_MASK 0x0000ff00
4933 # define TV_SATURATION_SHIFT 8
4934 /* Hue adjustment, as an integer phase angle in degrees */
4935 # define TV_HUE_MASK 0x000000ff
4936 # define TV_HUE_SHIFT 0
4938 #define TV_CLR_LEVEL _MMIO(0x6802c)
4939 /* Controls the DAC level for black */
4940 # define TV_BLACK_LEVEL_MASK 0x01ff0000
4941 # define TV_BLACK_LEVEL_SHIFT 16
4942 /* Controls the DAC level for blanking */
4943 # define TV_BLANK_LEVEL_MASK 0x000001ff
4944 # define TV_BLANK_LEVEL_SHIFT 0
4946 #define TV_H_CTL_1 _MMIO(0x68030)
4947 /* Number of pixels in the hsync. */
4948 # define TV_HSYNC_END_MASK 0x1fff0000
4949 # define TV_HSYNC_END_SHIFT 16
4950 /* Total number of pixels minus one in the line (display and blanking). */
4951 # define TV_HTOTAL_MASK 0x00001fff
4952 # define TV_HTOTAL_SHIFT 0
4954 #define TV_H_CTL_2 _MMIO(0x68034)
4955 /* Enables the colorburst (needed for non-component color) */
4956 # define TV_BURST_ENA (1 << 31)
4957 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
4958 # define TV_HBURST_START_SHIFT 16
4959 # define TV_HBURST_START_MASK 0x1fff0000
4960 /* Length of the colorburst */
4961 # define TV_HBURST_LEN_SHIFT 0
4962 # define TV_HBURST_LEN_MASK 0x0001fff
4964 #define TV_H_CTL_3 _MMIO(0x68038)
4965 /* End of hblank, measured in pixels minus one from start of hsync */
4966 # define TV_HBLANK_END_SHIFT 16
4967 # define TV_HBLANK_END_MASK 0x1fff0000
4968 /* Start of hblank, measured in pixels minus one from start of hsync */
4969 # define TV_HBLANK_START_SHIFT 0
4970 # define TV_HBLANK_START_MASK 0x0001fff
4972 #define TV_V_CTL_1 _MMIO(0x6803c)
4974 # define TV_NBR_END_SHIFT 16
4975 # define TV_NBR_END_MASK 0x07ff0000
4977 # define TV_VI_END_F1_SHIFT 8
4978 # define TV_VI_END_F1_MASK 0x00003f00
4980 # define TV_VI_END_F2_SHIFT 0
4981 # define TV_VI_END_F2_MASK 0x0000003f
4983 #define TV_V_CTL_2 _MMIO(0x68040)
4984 /* Length of vsync, in half lines */
4985 # define TV_VSYNC_LEN_MASK 0x07ff0000
4986 # define TV_VSYNC_LEN_SHIFT 16
4987 /* Offset of the start of vsync in field 1, measured in one less than the
4988 * number of half lines.
4990 # define TV_VSYNC_START_F1_MASK 0x00007f00
4991 # define TV_VSYNC_START_F1_SHIFT 8
4993 * Offset of the start of vsync in field 2, measured in one less than the
4994 * number of half lines.
4996 # define TV_VSYNC_START_F2_MASK 0x0000007f
4997 # define TV_VSYNC_START_F2_SHIFT 0
4999 #define TV_V_CTL_3 _MMIO(0x68044)
5000 /* Enables generation of the equalization signal */
5001 # define TV_EQUAL_ENA (1 << 31)
5002 /* Length of vsync, in half lines */
5003 # define TV_VEQ_LEN_MASK 0x007f0000
5004 # define TV_VEQ_LEN_SHIFT 16
5005 /* Offset of the start of equalization in field 1, measured in one less than
5006 * the number of half lines.
5008 # define TV_VEQ_START_F1_MASK 0x0007f00
5009 # define TV_VEQ_START_F1_SHIFT 8
5011 * Offset of the start of equalization in field 2, measured in one less than
5012 * the number of half lines.
5014 # define TV_VEQ_START_F2_MASK 0x000007f
5015 # define TV_VEQ_START_F2_SHIFT 0
5017 #define TV_V_CTL_4 _MMIO(0x68048)
5019 * Offset to start of vertical colorburst, measured in one less than the
5020 * number of lines from vertical start.
5022 # define TV_VBURST_START_F1_MASK 0x003f0000
5023 # define TV_VBURST_START_F1_SHIFT 16
5025 * Offset to the end of vertical colorburst, measured in one less than the
5026 * number of lines from the start of NBR.
5028 # define TV_VBURST_END_F1_MASK 0x000000ff
5029 # define TV_VBURST_END_F1_SHIFT 0
5031 #define TV_V_CTL_5 _MMIO(0x6804c)
5033 * Offset to start of vertical colorburst, measured in one less than the
5034 * number of lines from vertical start.
5036 # define TV_VBURST_START_F2_MASK 0x003f0000
5037 # define TV_VBURST_START_F2_SHIFT 16
5039 * Offset to the end of vertical colorburst, measured in one less than the
5040 * number of lines from the start of NBR.
5042 # define TV_VBURST_END_F2_MASK 0x000000ff
5043 # define TV_VBURST_END_F2_SHIFT 0
5045 #define TV_V_CTL_6 _MMIO(0x68050)
5047 * Offset to start of vertical colorburst, measured in one less than the
5048 * number of lines from vertical start.
5050 # define TV_VBURST_START_F3_MASK 0x003f0000
5051 # define TV_VBURST_START_F3_SHIFT 16
5053 * Offset to the end of vertical colorburst, measured in one less than the
5054 * number of lines from the start of NBR.
5056 # define TV_VBURST_END_F3_MASK 0x000000ff
5057 # define TV_VBURST_END_F3_SHIFT 0
5059 #define TV_V_CTL_7 _MMIO(0x68054)
5061 * Offset to start of vertical colorburst, measured in one less than the
5062 * number of lines from vertical start.
5064 # define TV_VBURST_START_F4_MASK 0x003f0000
5065 # define TV_VBURST_START_F4_SHIFT 16
5067 * Offset to the end of vertical colorburst, measured in one less than the
5068 * number of lines from the start of NBR.
5070 # define TV_VBURST_END_F4_MASK 0x000000ff
5071 # define TV_VBURST_END_F4_SHIFT 0
5073 #define TV_SC_CTL_1 _MMIO(0x68060)
5074 /* Turns on the first subcarrier phase generation DDA */
5075 # define TV_SC_DDA1_EN (1 << 31)
5076 /* Turns on the first subcarrier phase generation DDA */
5077 # define TV_SC_DDA2_EN (1 << 30)
5078 /* Turns on the first subcarrier phase generation DDA */
5079 # define TV_SC_DDA3_EN (1 << 29)
5080 /* Sets the subcarrier DDA to reset frequency every other field */
5081 # define TV_SC_RESET_EVERY_2 (0 << 24)
5082 /* Sets the subcarrier DDA to reset frequency every fourth field */
5083 # define TV_SC_RESET_EVERY_4 (1 << 24)
5084 /* Sets the subcarrier DDA to reset frequency every eighth field */
5085 # define TV_SC_RESET_EVERY_8 (2 << 24)
5086 /* Sets the subcarrier DDA to never reset the frequency */
5087 # define TV_SC_RESET_NEVER (3 << 24)
5088 /* Sets the peak amplitude of the colorburst.*/
5089 # define TV_BURST_LEVEL_MASK 0x00ff0000
5090 # define TV_BURST_LEVEL_SHIFT 16
5091 /* Sets the increment of the first subcarrier phase generation DDA */
5092 # define TV_SCDDA1_INC_MASK 0x00000fff
5093 # define TV_SCDDA1_INC_SHIFT 0
5095 #define TV_SC_CTL_2 _MMIO(0x68064)
5096 /* Sets the rollover for the second subcarrier phase generation DDA */
5097 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
5098 # define TV_SCDDA2_SIZE_SHIFT 16
5099 /* Sets the increent of the second subcarrier phase generation DDA */
5100 # define TV_SCDDA2_INC_MASK 0x00007fff
5101 # define TV_SCDDA2_INC_SHIFT 0
5103 #define TV_SC_CTL_3 _MMIO(0x68068)
5104 /* Sets the rollover for the third subcarrier phase generation DDA */
5105 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
5106 # define TV_SCDDA3_SIZE_SHIFT 16
5107 /* Sets the increent of the third subcarrier phase generation DDA */
5108 # define TV_SCDDA3_INC_MASK 0x00007fff
5109 # define TV_SCDDA3_INC_SHIFT 0
5111 #define TV_WIN_POS _MMIO(0x68070)
5112 /* X coordinate of the display from the start of horizontal active */
5113 # define TV_XPOS_MASK 0x1fff0000
5114 # define TV_XPOS_SHIFT 16
5115 /* Y coordinate of the display from the start of vertical active (NBR) */
5116 # define TV_YPOS_MASK 0x00000fff
5117 # define TV_YPOS_SHIFT 0
5119 #define TV_WIN_SIZE _MMIO(0x68074)
5120 /* Horizontal size of the display window, measured in pixels*/
5121 # define TV_XSIZE_MASK 0x1fff0000
5122 # define TV_XSIZE_SHIFT 16
5124 * Vertical size of the display window, measured in pixels.
5126 * Must be even for interlaced modes.
5128 # define TV_YSIZE_MASK 0x00000fff
5129 # define TV_YSIZE_SHIFT 0
5131 #define TV_FILTER_CTL_1 _MMIO(0x68080)
5133 * Enables automatic scaling calculation.
5135 * If set, the rest of the registers are ignored, and the calculated values can
5136 * be read back from the register.
5138 # define TV_AUTO_SCALE (1 << 31)
5140 * Disables the vertical filter.
5142 * This is required on modes more than 1024 pixels wide */
5143 # define TV_V_FILTER_BYPASS (1 << 29)
5144 /* Enables adaptive vertical filtering */
5145 # define TV_VADAPT (1 << 28)
5146 # define TV_VADAPT_MODE_MASK (3 << 26)
5147 /* Selects the least adaptive vertical filtering mode */
5148 # define TV_VADAPT_MODE_LEAST (0 << 26)
5149 /* Selects the moderately adaptive vertical filtering mode */
5150 # define TV_VADAPT_MODE_MODERATE (1 << 26)
5151 /* Selects the most adaptive vertical filtering mode */
5152 # define TV_VADAPT_MODE_MOST (3 << 26)
5154 * Sets the horizontal scaling factor.
5156 * This should be the fractional part of the horizontal scaling factor divided
5157 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5159 * (src width - 1) / ((oversample * dest width) - 1)
5161 # define TV_HSCALE_FRAC_MASK 0x00003fff
5162 # define TV_HSCALE_FRAC_SHIFT 0
5164 #define TV_FILTER_CTL_2 _MMIO(0x68084)
5166 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5168 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5170 # define TV_VSCALE_INT_MASK 0x00038000
5171 # define TV_VSCALE_INT_SHIFT 15
5173 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5175 * \sa TV_VSCALE_INT_MASK
5177 # define TV_VSCALE_FRAC_MASK 0x00007fff
5178 # define TV_VSCALE_FRAC_SHIFT 0
5180 #define TV_FILTER_CTL_3 _MMIO(0x68088)
5182 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5184 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5186 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5188 # define TV_VSCALE_IP_INT_MASK 0x00038000
5189 # define TV_VSCALE_IP_INT_SHIFT 15
5191 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5193 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5195 * \sa TV_VSCALE_IP_INT_MASK
5197 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5198 # define TV_VSCALE_IP_FRAC_SHIFT 0
5200 #define TV_CC_CONTROL _MMIO(0x68090)
5201 # define TV_CC_ENABLE (1 << 31)
5203 * Specifies which field to send the CC data in.
5205 * CC data is usually sent in field 0.
5207 # define TV_CC_FID_MASK (1 << 27)
5208 # define TV_CC_FID_SHIFT 27
5209 /* Sets the horizontal position of the CC data. Usually 135. */
5210 # define TV_CC_HOFF_MASK 0x03ff0000
5211 # define TV_CC_HOFF_SHIFT 16
5212 /* Sets the vertical position of the CC data. Usually 21 */
5213 # define TV_CC_LINE_MASK 0x0000003f
5214 # define TV_CC_LINE_SHIFT 0
5216 #define TV_CC_DATA _MMIO(0x68094)
5217 # define TV_CC_RDY (1 << 31)
5218 /* Second word of CC data to be transmitted. */
5219 # define TV_CC_DATA_2_MASK 0x007f0000
5220 # define TV_CC_DATA_2_SHIFT 16
5221 /* First word of CC data to be transmitted. */
5222 # define TV_CC_DATA_1_MASK 0x0000007f
5223 # define TV_CC_DATA_1_SHIFT 0
5225 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5226 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5227 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5228 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
5231 #define DP_A _MMIO(0x64000) /* eDP */
5232 #define DP_B _MMIO(0x64100)
5233 #define DP_C _MMIO(0x64200)
5234 #define DP_D _MMIO(0x64300)
5236 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5237 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5238 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5240 #define DP_PORT_EN (1 << 31)
5241 #define DP_PIPEB_SELECT (1 << 30)
5242 #define DP_PIPE_MASK (1 << 30)
5243 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
5244 #define DP_PIPE_MASK_CHV (3 << 16)
5246 /* Link training mode - select a suitable mode for each stage */
5247 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
5248 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
5249 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5250 #define DP_LINK_TRAIN_OFF (3 << 28)
5251 #define DP_LINK_TRAIN_MASK (3 << 28)
5252 #define DP_LINK_TRAIN_SHIFT 28
5253 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
5254 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
5256 /* CPT Link training mode */
5257 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5258 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5259 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5260 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5261 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5262 #define DP_LINK_TRAIN_SHIFT_CPT 8
5264 /* Signal voltages. These are mostly controlled by the other end */
5265 #define DP_VOLTAGE_0_4 (0 << 25)
5266 #define DP_VOLTAGE_0_6 (1 << 25)
5267 #define DP_VOLTAGE_0_8 (2 << 25)
5268 #define DP_VOLTAGE_1_2 (3 << 25)
5269 #define DP_VOLTAGE_MASK (7 << 25)
5270 #define DP_VOLTAGE_SHIFT 25
5272 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5275 #define DP_PRE_EMPHASIS_0 (0 << 22)
5276 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
5277 #define DP_PRE_EMPHASIS_6 (2 << 22)
5278 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
5279 #define DP_PRE_EMPHASIS_MASK (7 << 22)
5280 #define DP_PRE_EMPHASIS_SHIFT 22
5282 /* How many wires to use. I guess 3 was too hard */
5283 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5284 #define DP_PORT_WIDTH_MASK (7 << 19)
5285 #define DP_PORT_WIDTH_SHIFT 19
5287 /* Mystic DPCD version 1.1 special mode */
5288 #define DP_ENHANCED_FRAMING (1 << 18)
5291 #define DP_PLL_FREQ_270MHZ (0 << 16)
5292 #define DP_PLL_FREQ_162MHZ (1 << 16)
5293 #define DP_PLL_FREQ_MASK (3 << 16)
5295 /* locked once port is enabled */
5296 #define DP_PORT_REVERSAL (1 << 15)
5299 #define DP_PLL_ENABLE (1 << 14)
5301 /* sends the clock on lane 15 of the PEG for debug */
5302 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5304 #define DP_SCRAMBLING_DISABLE (1 << 12)
5305 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
5307 /* limit RGB values to avoid confusing TVs */
5308 #define DP_COLOR_RANGE_16_235 (1 << 8)
5310 /* Turn on the audio link */
5311 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5313 /* vs and hs sync polarity */
5314 #define DP_SYNC_VS_HIGH (1 << 4)
5315 #define DP_SYNC_HS_HIGH (1 << 3)
5318 #define DP_DETECTED (1 << 2)
5320 /* The aux channel provides a way to talk to the
5321 * signal sink for DDC etc. Max packet size supported
5322 * is 20 bytes in each direction, hence the 5 fixed
5325 #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
5326 #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
5327 #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
5328 #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
5329 #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
5330 #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
5332 #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
5333 #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
5334 #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
5335 #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
5336 #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
5337 #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
5339 #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
5340 #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
5341 #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
5342 #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
5343 #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
5344 #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
5346 #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
5347 #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
5348 #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
5349 #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
5350 #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
5351 #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
5353 #define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
5354 #define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
5355 #define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
5356 #define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
5357 #define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
5358 #define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
5360 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5361 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5363 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5364 #define DP_AUX_CH_CTL_DONE (1 << 30)
5365 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5366 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5367 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5368 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5369 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
5370 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
5371 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5372 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5373 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5374 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5375 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5376 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5377 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5378 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5379 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5380 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5381 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5382 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5383 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
5384 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5385 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5386 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5387 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5388 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5389 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5392 * Computing GMCH M and N values for the Display Port link
5394 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5396 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5398 * The GMCH value is used internally
5400 * bytes_per_pixel is the number of bytes coming out of the plane,
5401 * which is after the LUTs, so we want the bytes for our color format.
5402 * For our current usage, this is always 3, one byte for R, G and B.
5404 #define _PIPEA_DATA_M_G4X 0x70050
5405 #define _PIPEB_DATA_M_G4X 0x71050
5407 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5408 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
5409 #define TU_SIZE_SHIFT 25
5410 #define TU_SIZE_MASK (0x3f << 25)
5412 #define DATA_LINK_M_N_MASK (0xffffff)
5413 #define DATA_LINK_N_MAX (0x800000)
5415 #define _PIPEA_DATA_N_G4X 0x70054
5416 #define _PIPEB_DATA_N_G4X 0x71054
5417 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
5420 * Computing Link M and N values for the Display Port link
5422 * Link M / N = pixel_clock / ls_clk
5424 * (the DP spec calls pixel_clock the 'strm_clk')
5426 * The Link value is transmitted in the Main Stream
5427 * Attributes and VB-ID.
5430 #define _PIPEA_LINK_M_G4X 0x70060
5431 #define _PIPEB_LINK_M_G4X 0x71060
5432 #define PIPEA_DP_LINK_M_MASK (0xffffff)
5434 #define _PIPEA_LINK_N_G4X 0x70064
5435 #define _PIPEB_LINK_N_G4X 0x71064
5436 #define PIPEA_DP_LINK_N_MASK (0xffffff)
5438 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5439 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5440 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5441 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5443 /* Display & cursor control */
5446 #define _PIPEADSL 0x70000
5447 #define DSL_LINEMASK_GEN2 0x00000fff
5448 #define DSL_LINEMASK_GEN3 0x00001fff
5449 #define _PIPEACONF 0x70008
5450 #define PIPECONF_ENABLE (1<<31)
5451 #define PIPECONF_DISABLE 0
5452 #define PIPECONF_DOUBLE_WIDE (1<<30)
5453 #define I965_PIPECONF_ACTIVE (1<<30)
5454 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
5455 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
5456 #define PIPECONF_SINGLE_WIDE 0
5457 #define PIPECONF_PIPE_UNLOCKED 0
5458 #define PIPECONF_PIPE_LOCKED (1<<25)
5459 #define PIPECONF_PALETTE 0
5460 #define PIPECONF_GAMMA (1<<24)
5461 #define PIPECONF_FORCE_BORDER (1<<25)
5462 #define PIPECONF_INTERLACE_MASK (7 << 21)
5463 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
5464 /* Note that pre-gen3 does not support interlaced display directly. Panel
5465 * fitting must be disabled on pre-ilk for interlaced. */
5466 #define PIPECONF_PROGRESSIVE (0 << 21)
5467 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5468 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
5469 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5470 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
5471 /* Ironlake and later have a complete new set of values for interlaced. PFIT
5472 * means panel fitter required, PF means progressive fetch, DBL means power
5473 * saving pixel doubling. */
5474 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
5475 #define PIPECONF_INTERLACED_ILK (3 << 21)
5476 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
5477 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
5478 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
5479 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
5480 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
5481 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
5482 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
5483 #define PIPECONF_BPC_MASK (0x7 << 5)
5484 #define PIPECONF_8BPC (0<<5)
5485 #define PIPECONF_10BPC (1<<5)
5486 #define PIPECONF_6BPC (2<<5)
5487 #define PIPECONF_12BPC (3<<5)
5488 #define PIPECONF_DITHER_EN (1<<4)
5489 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5490 #define PIPECONF_DITHER_TYPE_SP (0<<2)
5491 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
5492 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
5493 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
5494 #define _PIPEASTAT 0x70024
5495 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
5496 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
5497 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
5498 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
5499 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
5500 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
5501 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
5502 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
5503 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
5504 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
5505 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
5506 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
5507 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
5508 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
5509 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
5510 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
5511 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
5512 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
5513 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
5514 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
5515 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
5516 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
5517 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
5518 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
5519 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
5520 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
5521 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
5522 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
5523 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
5524 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
5525 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
5526 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
5527 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
5528 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
5529 #define PIPE_A_PSR_STATUS_VLV (1UL<<6)
5530 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
5531 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
5532 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
5533 #define PIPE_B_PSR_STATUS_VLV (1UL<<3)
5534 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
5535 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
5536 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
5537 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
5538 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
5539 #define PIPE_HBLANK_INT_STATUS (1UL<<0)
5540 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
5542 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
5543 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
5545 #define PIPE_A_OFFSET 0x70000
5546 #define PIPE_B_OFFSET 0x71000
5547 #define PIPE_C_OFFSET 0x72000
5548 #define CHV_PIPE_C_OFFSET 0x74000
5550 * There's actually no pipe EDP. Some pipe registers have
5551 * simply shifted from the pipe to the transcoder, while
5552 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5553 * to access such registers in transcoder EDP.
5555 #define PIPE_EDP_OFFSET 0x7f000
5557 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
5558 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
5559 dev_priv->info.display_mmio_offset)
5561 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5562 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
5563 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5564 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5565 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
5567 #define _PIPE_MISC_A 0x70030
5568 #define _PIPE_MISC_B 0x71030
5569 #define PIPEMISC_YUV420_ENABLE (1<<27)
5570 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1<<26)
5571 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1<<11)
5572 #define PIPEMISC_DITHER_BPC_MASK (7<<5)
5573 #define PIPEMISC_DITHER_8_BPC (0<<5)
5574 #define PIPEMISC_DITHER_10_BPC (1<<5)
5575 #define PIPEMISC_DITHER_6_BPC (2<<5)
5576 #define PIPEMISC_DITHER_12_BPC (3<<5)
5577 #define PIPEMISC_DITHER_ENABLE (1<<4)
5578 #define PIPEMISC_DITHER_TYPE_MASK (3<<2)
5579 #define PIPEMISC_DITHER_TYPE_SP (0<<2)
5580 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5582 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5583 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
5584 #define PIPEB_HLINE_INT_EN (1<<28)
5585 #define PIPEB_VBLANK_INT_EN (1<<27)
5586 #define SPRITED_FLIP_DONE_INT_EN (1<<26)
5587 #define SPRITEC_FLIP_DONE_INT_EN (1<<25)
5588 #define PLANEB_FLIP_DONE_INT_EN (1<<24)
5589 #define PIPE_PSR_INT_EN (1<<22)
5590 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
5591 #define PIPEA_HLINE_INT_EN (1<<20)
5592 #define PIPEA_VBLANK_INT_EN (1<<19)
5593 #define SPRITEB_FLIP_DONE_INT_EN (1<<18)
5594 #define SPRITEA_FLIP_DONE_INT_EN (1<<17)
5595 #define PLANEA_FLIPDONE_INT_EN (1<<16)
5596 #define PIPEC_LINE_COMPARE_INT_EN (1<<13)
5597 #define PIPEC_HLINE_INT_EN (1<<12)
5598 #define PIPEC_VBLANK_INT_EN (1<<11)
5599 #define SPRITEF_FLIPDONE_INT_EN (1<<10)
5600 #define SPRITEE_FLIPDONE_INT_EN (1<<9)
5601 #define PLANEC_FLIPDONE_INT_EN (1<<8)
5603 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5604 #define SPRITEF_INVALID_GTT_INT_EN (1<<27)
5605 #define SPRITEE_INVALID_GTT_INT_EN (1<<26)
5606 #define PLANEC_INVALID_GTT_INT_EN (1<<25)
5607 #define CURSORC_INVALID_GTT_INT_EN (1<<24)
5608 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
5609 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
5610 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
5611 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
5612 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
5613 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
5614 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
5615 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
5616 #define DPINVGTT_EN_MASK 0xff0000
5617 #define DPINVGTT_EN_MASK_CHV 0xfff0000
5618 #define SPRITEF_INVALID_GTT_STATUS (1<<11)
5619 #define SPRITEE_INVALID_GTT_STATUS (1<<10)
5620 #define PLANEC_INVALID_GTT_STATUS (1<<9)
5621 #define CURSORC_INVALID_GTT_STATUS (1<<8)
5622 #define CURSORB_INVALID_GTT_STATUS (1<<7)
5623 #define CURSORA_INVALID_GTT_STATUS (1<<6)
5624 #define SPRITED_INVALID_GTT_STATUS (1<<5)
5625 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
5626 #define PLANEB_INVALID_GTT_STATUS (1<<3)
5627 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
5628 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
5629 #define PLANEA_INVALID_GTT_STATUS (1<<0)
5630 #define DPINVGTT_STATUS_MASK 0xff
5631 #define DPINVGTT_STATUS_MASK_CHV 0xfff
5633 #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
5634 #define DSPARB_CSTART_MASK (0x7f << 7)
5635 #define DSPARB_CSTART_SHIFT 7
5636 #define DSPARB_BSTART_MASK (0x7f)
5637 #define DSPARB_BSTART_SHIFT 0
5638 #define DSPARB_BEND_SHIFT 9 /* on 855 */
5639 #define DSPARB_AEND_SHIFT 0
5640 #define DSPARB_SPRITEA_SHIFT_VLV 0
5641 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
5642 #define DSPARB_SPRITEB_SHIFT_VLV 8
5643 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
5644 #define DSPARB_SPRITEC_SHIFT_VLV 16
5645 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
5646 #define DSPARB_SPRITED_SHIFT_VLV 24
5647 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
5648 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5649 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
5650 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
5651 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
5652 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
5653 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
5654 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
5655 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
5656 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
5657 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
5658 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
5659 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
5660 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
5661 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5662 #define DSPARB_SPRITEE_SHIFT_VLV 0
5663 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
5664 #define DSPARB_SPRITEF_SHIFT_VLV 8
5665 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
5667 /* pnv/gen4/g4x/vlv/chv */
5668 #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
5669 #define DSPFW_SR_SHIFT 23
5670 #define DSPFW_SR_MASK (0x1ff<<23)
5671 #define DSPFW_CURSORB_SHIFT 16
5672 #define DSPFW_CURSORB_MASK (0x3f<<16)
5673 #define DSPFW_PLANEB_SHIFT 8
5674 #define DSPFW_PLANEB_MASK (0x7f<<8)
5675 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
5676 #define DSPFW_PLANEA_SHIFT 0
5677 #define DSPFW_PLANEA_MASK (0x7f<<0)
5678 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
5679 #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
5680 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */
5681 #define DSPFW_FBC_SR_SHIFT 28
5682 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
5683 #define DSPFW_FBC_HPLL_SR_SHIFT 24
5684 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
5685 #define DSPFW_SPRITEB_SHIFT (16)
5686 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
5687 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
5688 #define DSPFW_CURSORA_SHIFT 8
5689 #define DSPFW_CURSORA_MASK (0x3f<<8)
5690 #define DSPFW_PLANEC_OLD_SHIFT 0
5691 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
5692 #define DSPFW_SPRITEA_SHIFT 0
5693 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
5694 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
5695 #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
5696 #define DSPFW_HPLL_SR_EN (1<<31)
5697 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
5698 #define DSPFW_CURSOR_SR_SHIFT 24
5699 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
5700 #define DSPFW_HPLL_CURSOR_SHIFT 16
5701 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
5702 #define DSPFW_HPLL_SR_SHIFT 0
5703 #define DSPFW_HPLL_SR_MASK (0x1ff<<0)
5706 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5707 #define DSPFW_SPRITEB_WM1_SHIFT 16
5708 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
5709 #define DSPFW_CURSORA_WM1_SHIFT 8
5710 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
5711 #define DSPFW_SPRITEA_WM1_SHIFT 0
5712 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
5713 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5714 #define DSPFW_PLANEB_WM1_SHIFT 24
5715 #define DSPFW_PLANEB_WM1_MASK (0xff<<24)
5716 #define DSPFW_PLANEA_WM1_SHIFT 16
5717 #define DSPFW_PLANEA_WM1_MASK (0xff<<16)
5718 #define DSPFW_CURSORB_WM1_SHIFT 8
5719 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
5720 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
5721 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
5722 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5723 #define DSPFW_SR_WM1_SHIFT 0
5724 #define DSPFW_SR_WM1_MASK (0x1ff<<0)
5725 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5726 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5727 #define DSPFW_SPRITED_WM1_SHIFT 24
5728 #define DSPFW_SPRITED_WM1_MASK (0xff<<24)
5729 #define DSPFW_SPRITED_SHIFT 16
5730 #define DSPFW_SPRITED_MASK_VLV (0xff<<16)
5731 #define DSPFW_SPRITEC_WM1_SHIFT 8
5732 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
5733 #define DSPFW_SPRITEC_SHIFT 0
5734 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
5735 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5736 #define DSPFW_SPRITEF_WM1_SHIFT 24
5737 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
5738 #define DSPFW_SPRITEF_SHIFT 16
5739 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
5740 #define DSPFW_SPRITEE_WM1_SHIFT 8
5741 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
5742 #define DSPFW_SPRITEE_SHIFT 0
5743 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
5744 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5745 #define DSPFW_PLANEC_WM1_SHIFT 24
5746 #define DSPFW_PLANEC_WM1_MASK (0xff<<24)
5747 #define DSPFW_PLANEC_SHIFT 16
5748 #define DSPFW_PLANEC_MASK_VLV (0xff<<16)
5749 #define DSPFW_CURSORC_WM1_SHIFT 8
5750 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
5751 #define DSPFW_CURSORC_SHIFT 0
5752 #define DSPFW_CURSORC_MASK (0x3f<<0)
5754 /* vlv/chv high order bits */
5755 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
5756 #define DSPFW_SR_HI_SHIFT 24
5757 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
5758 #define DSPFW_SPRITEF_HI_SHIFT 23
5759 #define DSPFW_SPRITEF_HI_MASK (1<<23)
5760 #define DSPFW_SPRITEE_HI_SHIFT 22
5761 #define DSPFW_SPRITEE_HI_MASK (1<<22)
5762 #define DSPFW_PLANEC_HI_SHIFT 21
5763 #define DSPFW_PLANEC_HI_MASK (1<<21)
5764 #define DSPFW_SPRITED_HI_SHIFT 20
5765 #define DSPFW_SPRITED_HI_MASK (1<<20)
5766 #define DSPFW_SPRITEC_HI_SHIFT 16
5767 #define DSPFW_SPRITEC_HI_MASK (1<<16)
5768 #define DSPFW_PLANEB_HI_SHIFT 12
5769 #define DSPFW_PLANEB_HI_MASK (1<<12)
5770 #define DSPFW_SPRITEB_HI_SHIFT 8
5771 #define DSPFW_SPRITEB_HI_MASK (1<<8)
5772 #define DSPFW_SPRITEA_HI_SHIFT 4
5773 #define DSPFW_SPRITEA_HI_MASK (1<<4)
5774 #define DSPFW_PLANEA_HI_SHIFT 0
5775 #define DSPFW_PLANEA_HI_MASK (1<<0)
5776 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
5777 #define DSPFW_SR_WM1_HI_SHIFT 24
5778 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
5779 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
5780 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
5781 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
5782 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
5783 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
5784 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
5785 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
5786 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
5787 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
5788 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
5789 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
5790 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
5791 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
5792 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
5793 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
5794 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
5795 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
5796 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
5798 /* drain latency register values*/
5799 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5800 #define DDL_CURSOR_SHIFT 24
5801 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
5802 #define DDL_PLANE_SHIFT 0
5803 #define DDL_PRECISION_HIGH (1<<7)
5804 #define DDL_PRECISION_LOW (0<<7)
5805 #define DRAIN_LATENCY_MASK 0x7f
5807 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
5808 #define CBR_PND_DEADLINE_DISABLE (1<<31)
5809 #define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
5811 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
5812 #define CBR_DPLLBMD_PIPE(pipe) (1<<(7+(pipe)*11)) /* pipes B and C */
5814 /* FIFO watermark sizes etc */
5815 #define G4X_FIFO_LINE_SIZE 64
5816 #define I915_FIFO_LINE_SIZE 64
5817 #define I830_FIFO_LINE_SIZE 32
5819 #define VALLEYVIEW_FIFO_SIZE 255
5820 #define G4X_FIFO_SIZE 127
5821 #define I965_FIFO_SIZE 512
5822 #define I945_FIFO_SIZE 127
5823 #define I915_FIFO_SIZE 95
5824 #define I855GM_FIFO_SIZE 127 /* In cachelines */
5825 #define I830_FIFO_SIZE 95
5827 #define VALLEYVIEW_MAX_WM 0xff
5828 #define G4X_MAX_WM 0x3f
5829 #define I915_MAX_WM 0x3f
5831 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
5832 #define PINEVIEW_FIFO_LINE_SIZE 64
5833 #define PINEVIEW_MAX_WM 0x1ff
5834 #define PINEVIEW_DFT_WM 0x3f
5835 #define PINEVIEW_DFT_HPLLOFF_WM 0
5836 #define PINEVIEW_GUARD_WM 10
5837 #define PINEVIEW_CURSOR_FIFO 64
5838 #define PINEVIEW_CURSOR_MAX_WM 0x3f
5839 #define PINEVIEW_CURSOR_DFT_WM 0
5840 #define PINEVIEW_CURSOR_GUARD_WM 5
5842 #define VALLEYVIEW_CURSOR_MAX_WM 64
5843 #define I965_CURSOR_FIFO 64
5844 #define I965_CURSOR_MAX_WM 32
5845 #define I965_CURSOR_DFT_WM 8
5847 /* Watermark register definitions for SKL */
5848 #define _CUR_WM_A_0 0x70140
5849 #define _CUR_WM_B_0 0x71140
5850 #define _PLANE_WM_1_A_0 0x70240
5851 #define _PLANE_WM_1_B_0 0x71240
5852 #define _PLANE_WM_2_A_0 0x70340
5853 #define _PLANE_WM_2_B_0 0x71340
5854 #define _PLANE_WM_TRANS_1_A_0 0x70268
5855 #define _PLANE_WM_TRANS_1_B_0 0x71268
5856 #define _PLANE_WM_TRANS_2_A_0 0x70368
5857 #define _PLANE_WM_TRANS_2_B_0 0x71368
5858 #define _CUR_WM_TRANS_A_0 0x70168
5859 #define _CUR_WM_TRANS_B_0 0x71168
5860 #define PLANE_WM_EN (1 << 31)
5861 #define PLANE_WM_LINES_SHIFT 14
5862 #define PLANE_WM_LINES_MASK 0x1f
5863 #define PLANE_WM_BLOCKS_MASK 0x3ff
5865 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
5866 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
5867 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
5869 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
5870 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
5871 #define _PLANE_WM_BASE(pipe, plane) \
5872 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
5873 #define PLANE_WM(pipe, plane, level) \
5874 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
5875 #define _PLANE_WM_TRANS_1(pipe) \
5876 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
5877 #define _PLANE_WM_TRANS_2(pipe) \
5878 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
5879 #define PLANE_WM_TRANS(pipe, plane) \
5880 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
5882 /* define the Watermark register on Ironlake */
5883 #define WM0_PIPEA_ILK _MMIO(0x45100)
5884 #define WM0_PIPE_PLANE_MASK (0xffff<<16)
5885 #define WM0_PIPE_PLANE_SHIFT 16
5886 #define WM0_PIPE_SPRITE_MASK (0xff<<8)
5887 #define WM0_PIPE_SPRITE_SHIFT 8
5888 #define WM0_PIPE_CURSOR_MASK (0xff)
5890 #define WM0_PIPEB_ILK _MMIO(0x45104)
5891 #define WM0_PIPEC_IVB _MMIO(0x45200)
5892 #define WM1_LP_ILK _MMIO(0x45108)
5893 #define WM1_LP_SR_EN (1<<31)
5894 #define WM1_LP_LATENCY_SHIFT 24
5895 #define WM1_LP_LATENCY_MASK (0x7f<<24)
5896 #define WM1_LP_FBC_MASK (0xf<<20)
5897 #define WM1_LP_FBC_SHIFT 20
5898 #define WM1_LP_FBC_SHIFT_BDW 19
5899 #define WM1_LP_SR_MASK (0x7ff<<8)
5900 #define WM1_LP_SR_SHIFT 8
5901 #define WM1_LP_CURSOR_MASK (0xff)
5902 #define WM2_LP_ILK _MMIO(0x4510c)
5903 #define WM2_LP_EN (1<<31)
5904 #define WM3_LP_ILK _MMIO(0x45110)
5905 #define WM3_LP_EN (1<<31)
5906 #define WM1S_LP_ILK _MMIO(0x45120)
5907 #define WM2S_LP_IVB _MMIO(0x45124)
5908 #define WM3S_LP_IVB _MMIO(0x45128)
5909 #define WM1S_LP_EN (1<<31)
5911 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
5912 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
5913 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
5915 /* Memory latency timer register */
5916 #define MLTR_ILK _MMIO(0x11222)
5917 #define MLTR_WM1_SHIFT 0
5918 #define MLTR_WM2_SHIFT 8
5919 /* the unit of memory self-refresh latency time is 0.5us */
5920 #define ILK_SRLT_MASK 0x3f
5923 /* the address where we get all kinds of latency value */
5924 #define SSKPD _MMIO(0x5d10)
5925 #define SSKPD_WM_MASK 0x3f
5926 #define SSKPD_WM0_SHIFT 0
5927 #define SSKPD_WM1_SHIFT 8
5928 #define SSKPD_WM2_SHIFT 16
5929 #define SSKPD_WM3_SHIFT 24
5932 * The two pipe frame counter registers are not synchronized, so
5933 * reading a stable value is somewhat tricky. The following code
5937 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5938 * PIPE_FRAME_HIGH_SHIFT;
5939 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
5940 * PIPE_FRAME_LOW_SHIFT);
5941 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5942 * PIPE_FRAME_HIGH_SHIFT);
5943 * } while (high1 != high2);
5944 * frame = (high1 << 8) | low1;
5946 #define _PIPEAFRAMEHIGH 0x70040
5947 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
5948 #define PIPE_FRAME_HIGH_SHIFT 0
5949 #define _PIPEAFRAMEPIXEL 0x70044
5950 #define PIPE_FRAME_LOW_MASK 0xff000000
5951 #define PIPE_FRAME_LOW_SHIFT 24
5952 #define PIPE_PIXEL_MASK 0x00ffffff
5953 #define PIPE_PIXEL_SHIFT 0
5954 /* GM45+ just has to be different */
5955 #define _PIPEA_FRMCOUNT_G4X 0x70040
5956 #define _PIPEA_FLIPCOUNT_G4X 0x70044
5957 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
5958 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
5960 /* Cursor A & B regs */
5961 #define _CURACNTR 0x70080
5962 /* Old style CUR*CNTR flags (desktop 8xx) */
5963 #define CURSOR_ENABLE 0x80000000
5964 #define CURSOR_GAMMA_ENABLE 0x40000000
5965 #define CURSOR_STRIDE_SHIFT 28
5966 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
5967 #define CURSOR_PIPE_CSC_ENABLE (1<<24)
5968 #define CURSOR_FORMAT_SHIFT 24
5969 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
5970 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
5971 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
5972 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
5973 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
5974 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
5975 /* New style CUR*CNTR flags */
5976 #define CURSOR_MODE 0x27
5977 #define CURSOR_MODE_DISABLE 0x00
5978 #define CURSOR_MODE_128_32B_AX 0x02
5979 #define CURSOR_MODE_256_32B_AX 0x03
5980 #define CURSOR_MODE_64_32B_AX 0x07
5981 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
5982 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
5983 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
5984 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
5985 #define MCURSOR_GAMMA_ENABLE (1 << 26)
5986 #define CURSOR_ROTATE_180 (1<<15)
5987 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
5988 #define _CURABASE 0x70084
5989 #define _CURAPOS 0x70088
5990 #define CURSOR_POS_MASK 0x007FF
5991 #define CURSOR_POS_SIGN 0x8000
5992 #define CURSOR_X_SHIFT 0
5993 #define CURSOR_Y_SHIFT 16
5994 #define CURSIZE _MMIO(0x700a0) /* 845/865 */
5995 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
5996 #define CUR_FBC_CTL_EN (1 << 31)
5997 #define _CURBCNTR 0x700c0
5998 #define _CURBBASE 0x700c4
5999 #define _CURBPOS 0x700c8
6001 #define _CURBCNTR_IVB 0x71080
6002 #define _CURBBASE_IVB 0x71084
6003 #define _CURBPOS_IVB 0x71088
6005 #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
6006 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
6007 dev_priv->info.display_mmio_offset)
6009 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6010 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6011 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6012 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6014 #define CURSOR_A_OFFSET 0x70080
6015 #define CURSOR_B_OFFSET 0x700c0
6016 #define CHV_CURSOR_C_OFFSET 0x700e0
6017 #define IVB_CURSOR_B_OFFSET 0x71080
6018 #define IVB_CURSOR_C_OFFSET 0x72080
6020 /* Display A control */
6021 #define _DSPACNTR 0x70180
6022 #define DISPLAY_PLANE_ENABLE (1<<31)
6023 #define DISPLAY_PLANE_DISABLE 0
6024 #define DISPPLANE_GAMMA_ENABLE (1<<30)
6025 #define DISPPLANE_GAMMA_DISABLE 0
6026 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
6027 #define DISPPLANE_YUV422 (0x0<<26)
6028 #define DISPPLANE_8BPP (0x2<<26)
6029 #define DISPPLANE_BGRA555 (0x3<<26)
6030 #define DISPPLANE_BGRX555 (0x4<<26)
6031 #define DISPPLANE_BGRX565 (0x5<<26)
6032 #define DISPPLANE_BGRX888 (0x6<<26)
6033 #define DISPPLANE_BGRA888 (0x7<<26)
6034 #define DISPPLANE_RGBX101010 (0x8<<26)
6035 #define DISPPLANE_RGBA101010 (0x9<<26)
6036 #define DISPPLANE_BGRX101010 (0xa<<26)
6037 #define DISPPLANE_RGBX161616 (0xc<<26)
6038 #define DISPPLANE_RGBX888 (0xe<<26)
6039 #define DISPPLANE_RGBA888 (0xf<<26)
6040 #define DISPPLANE_STEREO_ENABLE (1<<25)
6041 #define DISPPLANE_STEREO_DISABLE 0
6042 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
6043 #define DISPPLANE_SEL_PIPE_SHIFT 24
6044 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
6045 #define DISPPLANE_SEL_PIPE(pipe) ((pipe)<<DISPPLANE_SEL_PIPE_SHIFT)
6046 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
6047 #define DISPPLANE_SRC_KEY_DISABLE 0
6048 #define DISPPLANE_LINE_DOUBLE (1<<20)
6049 #define DISPPLANE_NO_LINE_DOUBLE 0
6050 #define DISPPLANE_STEREO_POLARITY_FIRST 0
6051 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
6052 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
6053 #define DISPPLANE_ROTATE_180 (1<<15)
6054 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
6055 #define DISPPLANE_TILED (1<<10)
6056 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
6057 #define _DSPAADDR 0x70184
6058 #define _DSPASTRIDE 0x70188
6059 #define _DSPAPOS 0x7018C /* reserved */
6060 #define _DSPASIZE 0x70190
6061 #define _DSPASURF 0x7019C /* 965+ only */
6062 #define _DSPATILEOFF 0x701A4 /* 965+ only */
6063 #define _DSPAOFFSET 0x701A4 /* HSW */
6064 #define _DSPASURFLIVE 0x701AC
6066 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6067 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6068 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6069 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6070 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6071 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6072 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6073 #define DSPLINOFF(plane) DSPADDR(plane)
6074 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6075 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6077 /* CHV pipe B blender and primary plane */
6078 #define _CHV_BLEND_A 0x60a00
6079 #define CHV_BLEND_LEGACY (0<<30)
6080 #define CHV_BLEND_ANDROID (1<<30)
6081 #define CHV_BLEND_MPO (2<<30)
6082 #define CHV_BLEND_MASK (3<<30)
6083 #define _CHV_CANVAS_A 0x60a04
6084 #define _PRIMPOS_A 0x60a08
6085 #define _PRIMSIZE_A 0x60a0c
6086 #define _PRIMCNSTALPHA_A 0x60a10
6087 #define PRIM_CONST_ALPHA_ENABLE (1<<31)
6089 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6090 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6091 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6092 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6093 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6095 /* Display/Sprite base address macros */
6096 #define DISP_BASEADDR_MASK (0xfffff000)
6097 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
6098 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
6111 #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
6112 #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
6113 #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
6114 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6117 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
6118 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
6119 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
6120 #define _PIPEBFRAMEHIGH 0x71040
6121 #define _PIPEBFRAMEPIXEL 0x71044
6122 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
6123 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
6126 /* Display B control */
6127 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
6128 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
6129 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
6130 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6131 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6132 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
6133 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
6134 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
6135 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
6136 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
6137 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
6138 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
6139 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
6141 /* Sprite A control */
6142 #define _DVSACNTR 0x72180
6143 #define DVS_ENABLE (1<<31)
6144 #define DVS_GAMMA_ENABLE (1<<30)
6145 #define DVS_PIXFORMAT_MASK (3<<25)
6146 #define DVS_FORMAT_YUV422 (0<<25)
6147 #define DVS_FORMAT_RGBX101010 (1<<25)
6148 #define DVS_FORMAT_RGBX888 (2<<25)
6149 #define DVS_FORMAT_RGBX161616 (3<<25)
6150 #define DVS_PIPE_CSC_ENABLE (1<<24)
6151 #define DVS_SOURCE_KEY (1<<22)
6152 #define DVS_RGB_ORDER_XBGR (1<<20)
6153 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
6154 #define DVS_YUV_ORDER_YUYV (0<<16)
6155 #define DVS_YUV_ORDER_UYVY (1<<16)
6156 #define DVS_YUV_ORDER_YVYU (2<<16)
6157 #define DVS_YUV_ORDER_VYUY (3<<16)
6158 #define DVS_ROTATE_180 (1<<15)
6159 #define DVS_DEST_KEY (1<<2)
6160 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
6161 #define DVS_TILED (1<<10)
6162 #define _DVSALINOFF 0x72184
6163 #define _DVSASTRIDE 0x72188
6164 #define _DVSAPOS 0x7218c
6165 #define _DVSASIZE 0x72190
6166 #define _DVSAKEYVAL 0x72194
6167 #define _DVSAKEYMSK 0x72198
6168 #define _DVSASURF 0x7219c
6169 #define _DVSAKEYMAXVAL 0x721a0
6170 #define _DVSATILEOFF 0x721a4
6171 #define _DVSASURFLIVE 0x721ac
6172 #define _DVSASCALE 0x72204
6173 #define DVS_SCALE_ENABLE (1<<31)
6174 #define DVS_FILTER_MASK (3<<29)
6175 #define DVS_FILTER_MEDIUM (0<<29)
6176 #define DVS_FILTER_ENHANCING (1<<29)
6177 #define DVS_FILTER_SOFTENING (2<<29)
6178 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
6179 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
6180 #define _DVSAGAMC 0x72300
6182 #define _DVSBCNTR 0x73180
6183 #define _DVSBLINOFF 0x73184
6184 #define _DVSBSTRIDE 0x73188
6185 #define _DVSBPOS 0x7318c
6186 #define _DVSBSIZE 0x73190
6187 #define _DVSBKEYVAL 0x73194
6188 #define _DVSBKEYMSK 0x73198
6189 #define _DVSBSURF 0x7319c
6190 #define _DVSBKEYMAXVAL 0x731a0
6191 #define _DVSBTILEOFF 0x731a4
6192 #define _DVSBSURFLIVE 0x731ac
6193 #define _DVSBSCALE 0x73204
6194 #define _DVSBGAMC 0x73300
6196 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6197 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6198 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6199 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6200 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6201 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6202 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6203 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6204 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6205 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6206 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6207 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6209 #define _SPRA_CTL 0x70280
6210 #define SPRITE_ENABLE (1<<31)
6211 #define SPRITE_GAMMA_ENABLE (1<<30)
6212 #define SPRITE_PIXFORMAT_MASK (7<<25)
6213 #define SPRITE_FORMAT_YUV422 (0<<25)
6214 #define SPRITE_FORMAT_RGBX101010 (1<<25)
6215 #define SPRITE_FORMAT_RGBX888 (2<<25)
6216 #define SPRITE_FORMAT_RGBX161616 (3<<25)
6217 #define SPRITE_FORMAT_YUV444 (4<<25)
6218 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
6219 #define SPRITE_PIPE_CSC_ENABLE (1<<24)
6220 #define SPRITE_SOURCE_KEY (1<<22)
6221 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
6222 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
6223 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
6224 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
6225 #define SPRITE_YUV_ORDER_YUYV (0<<16)
6226 #define SPRITE_YUV_ORDER_UYVY (1<<16)
6227 #define SPRITE_YUV_ORDER_YVYU (2<<16)
6228 #define SPRITE_YUV_ORDER_VYUY (3<<16)
6229 #define SPRITE_ROTATE_180 (1<<15)
6230 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
6231 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
6232 #define SPRITE_TILED (1<<10)
6233 #define SPRITE_DEST_KEY (1<<2)
6234 #define _SPRA_LINOFF 0x70284
6235 #define _SPRA_STRIDE 0x70288
6236 #define _SPRA_POS 0x7028c
6237 #define _SPRA_SIZE 0x70290
6238 #define _SPRA_KEYVAL 0x70294
6239 #define _SPRA_KEYMSK 0x70298
6240 #define _SPRA_SURF 0x7029c
6241 #define _SPRA_KEYMAX 0x702a0
6242 #define _SPRA_TILEOFF 0x702a4
6243 #define _SPRA_OFFSET 0x702a4
6244 #define _SPRA_SURFLIVE 0x702ac
6245 #define _SPRA_SCALE 0x70304
6246 #define SPRITE_SCALE_ENABLE (1<<31)
6247 #define SPRITE_FILTER_MASK (3<<29)
6248 #define SPRITE_FILTER_MEDIUM (0<<29)
6249 #define SPRITE_FILTER_ENHANCING (1<<29)
6250 #define SPRITE_FILTER_SOFTENING (2<<29)
6251 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
6252 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
6253 #define _SPRA_GAMC 0x70400
6255 #define _SPRB_CTL 0x71280
6256 #define _SPRB_LINOFF 0x71284
6257 #define _SPRB_STRIDE 0x71288
6258 #define _SPRB_POS 0x7128c
6259 #define _SPRB_SIZE 0x71290
6260 #define _SPRB_KEYVAL 0x71294
6261 #define _SPRB_KEYMSK 0x71298
6262 #define _SPRB_SURF 0x7129c
6263 #define _SPRB_KEYMAX 0x712a0
6264 #define _SPRB_TILEOFF 0x712a4
6265 #define _SPRB_OFFSET 0x712a4
6266 #define _SPRB_SURFLIVE 0x712ac
6267 #define _SPRB_SCALE 0x71304
6268 #define _SPRB_GAMC 0x71400
6270 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6271 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6272 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6273 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6274 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6275 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6276 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6277 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6278 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6279 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6280 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6281 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6282 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
6283 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6285 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6286 #define SP_ENABLE (1<<31)
6287 #define SP_GAMMA_ENABLE (1<<30)
6288 #define SP_PIXFORMAT_MASK (0xf<<26)
6289 #define SP_FORMAT_YUV422 (0<<26)
6290 #define SP_FORMAT_BGR565 (5<<26)
6291 #define SP_FORMAT_BGRX8888 (6<<26)
6292 #define SP_FORMAT_BGRA8888 (7<<26)
6293 #define SP_FORMAT_RGBX1010102 (8<<26)
6294 #define SP_FORMAT_RGBA1010102 (9<<26)
6295 #define SP_FORMAT_RGBX8888 (0xe<<26)
6296 #define SP_FORMAT_RGBA8888 (0xf<<26)
6297 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
6298 #define SP_SOURCE_KEY (1<<22)
6299 #define SP_YUV_BYTE_ORDER_MASK (3<<16)
6300 #define SP_YUV_ORDER_YUYV (0<<16)
6301 #define SP_YUV_ORDER_UYVY (1<<16)
6302 #define SP_YUV_ORDER_YVYU (2<<16)
6303 #define SP_YUV_ORDER_VYUY (3<<16)
6304 #define SP_ROTATE_180 (1<<15)
6305 #define SP_TILED (1<<10)
6306 #define SP_MIRROR (1<<8) /* CHV pipe B */
6307 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6308 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6309 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6310 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6311 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6312 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6313 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6314 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6315 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6316 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6317 #define SP_CONST_ALPHA_ENABLE (1<<31)
6318 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
6320 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6321 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6322 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6323 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6324 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6325 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6326 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6327 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6328 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6329 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6330 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6331 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
6333 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6334 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6336 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6337 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6338 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6339 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6340 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6341 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6342 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6343 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6344 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6345 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6346 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6347 #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
6350 * CHV pipe B sprite CSC
6352 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6353 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6354 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6356 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6357 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6359 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6360 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6361 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6362 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
6363 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
6365 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6366 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6367 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6368 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6369 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6370 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
6371 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
6373 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6374 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6375 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6376 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
6377 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
6379 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6380 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6381 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6382 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
6383 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
6385 /* Skylake plane registers */
6387 #define _PLANE_CTL_1_A 0x70180
6388 #define _PLANE_CTL_2_A 0x70280
6389 #define _PLANE_CTL_3_A 0x70380
6390 #define PLANE_CTL_ENABLE (1 << 31)
6391 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
6393 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6394 * expanded to include bit 23 as well. However, the shift-24 based values
6395 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6397 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
6398 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
6399 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
6400 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
6401 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
6402 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
6403 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
6404 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
6405 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
6406 #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
6407 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
6408 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6409 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
6410 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
6411 #define PLANE_CTL_ORDER_BGRX (0 << 20)
6412 #define PLANE_CTL_ORDER_RGBX (1 << 20)
6413 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6414 #define PLANE_CTL_YUV422_YUYV ( 0 << 16)
6415 #define PLANE_CTL_YUV422_UYVY ( 1 << 16)
6416 #define PLANE_CTL_YUV422_YVYU ( 2 << 16)
6417 #define PLANE_CTL_YUV422_VYUY ( 3 << 16)
6418 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
6419 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
6420 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
6421 #define PLANE_CTL_TILED_MASK (0x7 << 10)
6422 #define PLANE_CTL_TILED_LINEAR ( 0 << 10)
6423 #define PLANE_CTL_TILED_X ( 1 << 10)
6424 #define PLANE_CTL_TILED_Y ( 4 << 10)
6425 #define PLANE_CTL_TILED_YF ( 5 << 10)
6426 #define PLANE_CTL_FLIP_HORIZONTAL ( 1 << 8)
6427 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
6428 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
6429 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
6430 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
6431 #define PLANE_CTL_ROTATE_MASK 0x3
6432 #define PLANE_CTL_ROTATE_0 0x0
6433 #define PLANE_CTL_ROTATE_90 0x1
6434 #define PLANE_CTL_ROTATE_180 0x2
6435 #define PLANE_CTL_ROTATE_270 0x3
6436 #define _PLANE_STRIDE_1_A 0x70188
6437 #define _PLANE_STRIDE_2_A 0x70288
6438 #define _PLANE_STRIDE_3_A 0x70388
6439 #define _PLANE_POS_1_A 0x7018c
6440 #define _PLANE_POS_2_A 0x7028c
6441 #define _PLANE_POS_3_A 0x7038c
6442 #define _PLANE_SIZE_1_A 0x70190
6443 #define _PLANE_SIZE_2_A 0x70290
6444 #define _PLANE_SIZE_3_A 0x70390
6445 #define _PLANE_SURF_1_A 0x7019c
6446 #define _PLANE_SURF_2_A 0x7029c
6447 #define _PLANE_SURF_3_A 0x7039c
6448 #define _PLANE_OFFSET_1_A 0x701a4
6449 #define _PLANE_OFFSET_2_A 0x702a4
6450 #define _PLANE_OFFSET_3_A 0x703a4
6451 #define _PLANE_KEYVAL_1_A 0x70194
6452 #define _PLANE_KEYVAL_2_A 0x70294
6453 #define _PLANE_KEYMSK_1_A 0x70198
6454 #define _PLANE_KEYMSK_2_A 0x70298
6455 #define _PLANE_KEYMAX_1_A 0x701a0
6456 #define _PLANE_KEYMAX_2_A 0x702a0
6457 #define _PLANE_AUX_DIST_1_A 0x701c0
6458 #define _PLANE_AUX_DIST_2_A 0x702c0
6459 #define _PLANE_AUX_OFFSET_1_A 0x701c4
6460 #define _PLANE_AUX_OFFSET_2_A 0x702c4
6461 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6462 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6463 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6464 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
6465 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
6466 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
6467 #define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
6468 #define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
6469 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
6470 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
6471 #define _PLANE_BUF_CFG_1_A 0x7027c
6472 #define _PLANE_BUF_CFG_2_A 0x7037c
6473 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
6474 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
6477 #define _PLANE_CTL_1_B 0x71180
6478 #define _PLANE_CTL_2_B 0x71280
6479 #define _PLANE_CTL_3_B 0x71380
6480 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6481 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6482 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6483 #define PLANE_CTL(pipe, plane) \
6484 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6486 #define _PLANE_STRIDE_1_B 0x71188
6487 #define _PLANE_STRIDE_2_B 0x71288
6488 #define _PLANE_STRIDE_3_B 0x71388
6489 #define _PLANE_STRIDE_1(pipe) \
6490 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6491 #define _PLANE_STRIDE_2(pipe) \
6492 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6493 #define _PLANE_STRIDE_3(pipe) \
6494 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6495 #define PLANE_STRIDE(pipe, plane) \
6496 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6498 #define _PLANE_POS_1_B 0x7118c
6499 #define _PLANE_POS_2_B 0x7128c
6500 #define _PLANE_POS_3_B 0x7138c
6501 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6502 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6503 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6504 #define PLANE_POS(pipe, plane) \
6505 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6507 #define _PLANE_SIZE_1_B 0x71190
6508 #define _PLANE_SIZE_2_B 0x71290
6509 #define _PLANE_SIZE_3_B 0x71390
6510 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6511 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6512 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6513 #define PLANE_SIZE(pipe, plane) \
6514 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6516 #define _PLANE_SURF_1_B 0x7119c
6517 #define _PLANE_SURF_2_B 0x7129c
6518 #define _PLANE_SURF_3_B 0x7139c
6519 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6520 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6521 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6522 #define PLANE_SURF(pipe, plane) \
6523 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6525 #define _PLANE_OFFSET_1_B 0x711a4
6526 #define _PLANE_OFFSET_2_B 0x712a4
6527 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6528 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6529 #define PLANE_OFFSET(pipe, plane) \
6530 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6532 #define _PLANE_KEYVAL_1_B 0x71194
6533 #define _PLANE_KEYVAL_2_B 0x71294
6534 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6535 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6536 #define PLANE_KEYVAL(pipe, plane) \
6537 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6539 #define _PLANE_KEYMSK_1_B 0x71198
6540 #define _PLANE_KEYMSK_2_B 0x71298
6541 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6542 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6543 #define PLANE_KEYMSK(pipe, plane) \
6544 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6546 #define _PLANE_KEYMAX_1_B 0x711a0
6547 #define _PLANE_KEYMAX_2_B 0x712a0
6548 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6549 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6550 #define PLANE_KEYMAX(pipe, plane) \
6551 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6553 #define _PLANE_BUF_CFG_1_B 0x7127c
6554 #define _PLANE_BUF_CFG_2_B 0x7137c
6555 #define _PLANE_BUF_CFG_1(pipe) \
6556 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6557 #define _PLANE_BUF_CFG_2(pipe) \
6558 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6559 #define PLANE_BUF_CFG(pipe, plane) \
6560 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6562 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
6563 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
6564 #define _PLANE_NV12_BUF_CFG_1(pipe) \
6565 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6566 #define _PLANE_NV12_BUF_CFG_2(pipe) \
6567 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6568 #define PLANE_NV12_BUF_CFG(pipe, plane) \
6569 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6571 #define _PLANE_AUX_DIST_1_B 0x711c0
6572 #define _PLANE_AUX_DIST_2_B 0x712c0
6573 #define _PLANE_AUX_DIST_1(pipe) \
6574 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6575 #define _PLANE_AUX_DIST_2(pipe) \
6576 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6577 #define PLANE_AUX_DIST(pipe, plane) \
6578 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6580 #define _PLANE_AUX_OFFSET_1_B 0x711c4
6581 #define _PLANE_AUX_OFFSET_2_B 0x712c4
6582 #define _PLANE_AUX_OFFSET_1(pipe) \
6583 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6584 #define _PLANE_AUX_OFFSET_2(pipe) \
6585 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6586 #define PLANE_AUX_OFFSET(pipe, plane) \
6587 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6589 #define _PLANE_COLOR_CTL_1_B 0x711CC
6590 #define _PLANE_COLOR_CTL_2_B 0x712CC
6591 #define _PLANE_COLOR_CTL_3_B 0x713CC
6592 #define _PLANE_COLOR_CTL_1(pipe) \
6593 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6594 #define _PLANE_COLOR_CTL_2(pipe) \
6595 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6596 #define PLANE_COLOR_CTL(pipe, plane) \
6597 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6599 #/* SKL new cursor registers */
6600 #define _CUR_BUF_CFG_A 0x7017c
6601 #define _CUR_BUF_CFG_B 0x7117c
6602 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6605 #define VGACNTRL _MMIO(0x71400)
6606 # define VGA_DISP_DISABLE (1 << 31)
6607 # define VGA_2X_MODE (1 << 30)
6608 # define VGA_PIPE_B_SELECT (1 << 29)
6610 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
6614 #define CPU_VGACNTRL _MMIO(0x41000)
6616 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
6617 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
6618 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
6619 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
6620 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
6621 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
6622 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
6623 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
6624 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
6625 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
6626 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
6628 /* refresh rate hardware control */
6629 #define RR_HW_CTL _MMIO(0x45300)
6630 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
6631 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
6633 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
6634 #define FDI_PLL_FB_CLOCK_MASK 0xff
6635 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
6636 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
6637 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
6638 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
6639 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
6641 #define PCH_3DCGDIS0 _MMIO(0x46020)
6642 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
6643 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
6645 #define PCH_3DCGDIS1 _MMIO(0x46024)
6646 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
6648 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
6649 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
6650 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
6651 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
6654 #define _PIPEA_DATA_M1 0x60030
6655 #define PIPE_DATA_M1_OFFSET 0
6656 #define _PIPEA_DATA_N1 0x60034
6657 #define PIPE_DATA_N1_OFFSET 0
6659 #define _PIPEA_DATA_M2 0x60038
6660 #define PIPE_DATA_M2_OFFSET 0
6661 #define _PIPEA_DATA_N2 0x6003c
6662 #define PIPE_DATA_N2_OFFSET 0
6664 #define _PIPEA_LINK_M1 0x60040
6665 #define PIPE_LINK_M1_OFFSET 0
6666 #define _PIPEA_LINK_N1 0x60044
6667 #define PIPE_LINK_N1_OFFSET 0
6669 #define _PIPEA_LINK_M2 0x60048
6670 #define PIPE_LINK_M2_OFFSET 0
6671 #define _PIPEA_LINK_N2 0x6004c
6672 #define PIPE_LINK_N2_OFFSET 0
6674 /* PIPEB timing regs are same start from 0x61000 */
6676 #define _PIPEB_DATA_M1 0x61030
6677 #define _PIPEB_DATA_N1 0x61034
6678 #define _PIPEB_DATA_M2 0x61038
6679 #define _PIPEB_DATA_N2 0x6103c
6680 #define _PIPEB_LINK_M1 0x61040
6681 #define _PIPEB_LINK_N1 0x61044
6682 #define _PIPEB_LINK_M2 0x61048
6683 #define _PIPEB_LINK_N2 0x6104c
6685 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
6686 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
6687 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
6688 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
6689 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
6690 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
6691 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
6692 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
6694 /* CPU panel fitter */
6695 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
6696 #define _PFA_CTL_1 0x68080
6697 #define _PFB_CTL_1 0x68880
6698 #define PF_ENABLE (1<<31)
6699 #define PF_PIPE_SEL_MASK_IVB (3<<29)
6700 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
6701 #define PF_FILTER_MASK (3<<23)
6702 #define PF_FILTER_PROGRAMMED (0<<23)
6703 #define PF_FILTER_MED_3x3 (1<<23)
6704 #define PF_FILTER_EDGE_ENHANCE (2<<23)
6705 #define PF_FILTER_EDGE_SOFTEN (3<<23)
6706 #define _PFA_WIN_SZ 0x68074
6707 #define _PFB_WIN_SZ 0x68874
6708 #define _PFA_WIN_POS 0x68070
6709 #define _PFB_WIN_POS 0x68870
6710 #define _PFA_VSCALE 0x68084
6711 #define _PFB_VSCALE 0x68884
6712 #define _PFA_HSCALE 0x68090
6713 #define _PFB_HSCALE 0x68890
6715 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
6716 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
6717 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
6718 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
6719 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
6721 #define _PSA_CTL 0x68180
6722 #define _PSB_CTL 0x68980
6723 #define PS_ENABLE (1<<31)
6724 #define _PSA_WIN_SZ 0x68174
6725 #define _PSB_WIN_SZ 0x68974
6726 #define _PSA_WIN_POS 0x68170
6727 #define _PSB_WIN_POS 0x68970
6729 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
6730 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
6731 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
6736 #define _PS_1A_CTRL 0x68180
6737 #define _PS_2A_CTRL 0x68280
6738 #define _PS_1B_CTRL 0x68980
6739 #define _PS_2B_CTRL 0x68A80
6740 #define _PS_1C_CTRL 0x69180
6741 #define PS_SCALER_EN (1 << 31)
6742 #define PS_SCALER_MODE_MASK (3 << 28)
6743 #define PS_SCALER_MODE_DYN (0 << 28)
6744 #define PS_SCALER_MODE_HQ (1 << 28)
6745 #define PS_PLANE_SEL_MASK (7 << 25)
6746 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
6747 #define PS_FILTER_MASK (3 << 23)
6748 #define PS_FILTER_MEDIUM (0 << 23)
6749 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
6750 #define PS_FILTER_BILINEAR (3 << 23)
6751 #define PS_VERT3TAP (1 << 21)
6752 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
6753 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
6754 #define PS_PWRUP_PROGRESS (1 << 17)
6755 #define PS_V_FILTER_BYPASS (1 << 8)
6756 #define PS_VADAPT_EN (1 << 7)
6757 #define PS_VADAPT_MODE_MASK (3 << 5)
6758 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
6759 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
6760 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
6762 #define _PS_PWR_GATE_1A 0x68160
6763 #define _PS_PWR_GATE_2A 0x68260
6764 #define _PS_PWR_GATE_1B 0x68960
6765 #define _PS_PWR_GATE_2B 0x68A60
6766 #define _PS_PWR_GATE_1C 0x69160
6767 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
6768 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
6769 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
6770 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
6771 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
6772 #define PS_PWR_GATE_SLPEN_8 0
6773 #define PS_PWR_GATE_SLPEN_16 1
6774 #define PS_PWR_GATE_SLPEN_24 2
6775 #define PS_PWR_GATE_SLPEN_32 3
6777 #define _PS_WIN_POS_1A 0x68170
6778 #define _PS_WIN_POS_2A 0x68270
6779 #define _PS_WIN_POS_1B 0x68970
6780 #define _PS_WIN_POS_2B 0x68A70
6781 #define _PS_WIN_POS_1C 0x69170
6783 #define _PS_WIN_SZ_1A 0x68174
6784 #define _PS_WIN_SZ_2A 0x68274
6785 #define _PS_WIN_SZ_1B 0x68974
6786 #define _PS_WIN_SZ_2B 0x68A74
6787 #define _PS_WIN_SZ_1C 0x69174
6789 #define _PS_VSCALE_1A 0x68184
6790 #define _PS_VSCALE_2A 0x68284
6791 #define _PS_VSCALE_1B 0x68984
6792 #define _PS_VSCALE_2B 0x68A84
6793 #define _PS_VSCALE_1C 0x69184
6795 #define _PS_HSCALE_1A 0x68190
6796 #define _PS_HSCALE_2A 0x68290
6797 #define _PS_HSCALE_1B 0x68990
6798 #define _PS_HSCALE_2B 0x68A90
6799 #define _PS_HSCALE_1C 0x69190
6801 #define _PS_VPHASE_1A 0x68188
6802 #define _PS_VPHASE_2A 0x68288
6803 #define _PS_VPHASE_1B 0x68988
6804 #define _PS_VPHASE_2B 0x68A88
6805 #define _PS_VPHASE_1C 0x69188
6807 #define _PS_HPHASE_1A 0x68194
6808 #define _PS_HPHASE_2A 0x68294
6809 #define _PS_HPHASE_1B 0x68994
6810 #define _PS_HPHASE_2B 0x68A94
6811 #define _PS_HPHASE_1C 0x69194
6813 #define _PS_ECC_STAT_1A 0x681D0
6814 #define _PS_ECC_STAT_2A 0x682D0
6815 #define _PS_ECC_STAT_1B 0x689D0
6816 #define _PS_ECC_STAT_2B 0x68AD0
6817 #define _PS_ECC_STAT_1C 0x691D0
6819 #define _ID(id, a, b) ((a) + (id)*((b)-(a)))
6820 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
6821 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
6822 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
6823 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
6824 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
6825 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
6826 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
6827 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
6828 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
6829 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
6830 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
6831 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
6832 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
6833 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
6834 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
6835 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
6836 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
6837 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
6838 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
6839 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
6840 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
6841 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
6842 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
6843 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
6844 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
6845 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
6846 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
6848 /* legacy palette */
6849 #define _LGC_PALETTE_A 0x4a000
6850 #define _LGC_PALETTE_B 0x4a800
6851 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
6853 #define _GAMMA_MODE_A 0x4a480
6854 #define _GAMMA_MODE_B 0x4ac80
6855 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
6856 #define GAMMA_MODE_MODE_MASK (3 << 0)
6857 #define GAMMA_MODE_MODE_8BIT (0 << 0)
6858 #define GAMMA_MODE_MODE_10BIT (1 << 0)
6859 #define GAMMA_MODE_MODE_12BIT (2 << 0)
6860 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
6863 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
6864 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
6865 #define CSR_HTP_ADDR_SKL 0x00500034
6866 #define CSR_SSP_BASE _MMIO(0x8F074)
6867 #define CSR_HTP_SKL _MMIO(0x8F004)
6868 #define CSR_LAST_WRITE _MMIO(0x8F034)
6869 #define CSR_LAST_WRITE_VALUE 0xc003b400
6870 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
6871 #define CSR_MMIO_START_RANGE 0x80000
6872 #define CSR_MMIO_END_RANGE 0x8FFFF
6873 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
6874 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
6875 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
6878 #define DE_MASTER_IRQ_CONTROL (1 << 31)
6879 #define DE_SPRITEB_FLIP_DONE (1 << 29)
6880 #define DE_SPRITEA_FLIP_DONE (1 << 28)
6881 #define DE_PLANEB_FLIP_DONE (1 << 27)
6882 #define DE_PLANEA_FLIP_DONE (1 << 26)
6883 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
6884 #define DE_PCU_EVENT (1 << 25)
6885 #define DE_GTT_FAULT (1 << 24)
6886 #define DE_POISON (1 << 23)
6887 #define DE_PERFORM_COUNTER (1 << 22)
6888 #define DE_PCH_EVENT (1 << 21)
6889 #define DE_AUX_CHANNEL_A (1 << 20)
6890 #define DE_DP_A_HOTPLUG (1 << 19)
6891 #define DE_GSE (1 << 18)
6892 #define DE_PIPEB_VBLANK (1 << 15)
6893 #define DE_PIPEB_EVEN_FIELD (1 << 14)
6894 #define DE_PIPEB_ODD_FIELD (1 << 13)
6895 #define DE_PIPEB_LINE_COMPARE (1 << 12)
6896 #define DE_PIPEB_VSYNC (1 << 11)
6897 #define DE_PIPEB_CRC_DONE (1 << 10)
6898 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
6899 #define DE_PIPEA_VBLANK (1 << 7)
6900 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
6901 #define DE_PIPEA_EVEN_FIELD (1 << 6)
6902 #define DE_PIPEA_ODD_FIELD (1 << 5)
6903 #define DE_PIPEA_LINE_COMPARE (1 << 4)
6904 #define DE_PIPEA_VSYNC (1 << 3)
6905 #define DE_PIPEA_CRC_DONE (1 << 2)
6906 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
6907 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
6908 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
6910 /* More Ivybridge lolz */
6911 #define DE_ERR_INT_IVB (1<<30)
6912 #define DE_GSE_IVB (1<<29)
6913 #define DE_PCH_EVENT_IVB (1<<28)
6914 #define DE_DP_A_HOTPLUG_IVB (1<<27)
6915 #define DE_AUX_CHANNEL_A_IVB (1<<26)
6916 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
6917 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
6918 #define DE_PIPEC_VBLANK_IVB (1<<10)
6919 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
6920 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
6921 #define DE_PIPEB_VBLANK_IVB (1<<5)
6922 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
6923 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
6924 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
6925 #define DE_PIPEA_VBLANK_IVB (1<<0)
6926 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
6928 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
6929 #define MASTER_INTERRUPT_ENABLE (1<<31)
6931 #define DEISR _MMIO(0x44000)
6932 #define DEIMR _MMIO(0x44004)
6933 #define DEIIR _MMIO(0x44008)
6934 #define DEIER _MMIO(0x4400c)
6936 #define GTISR _MMIO(0x44010)
6937 #define GTIMR _MMIO(0x44014)
6938 #define GTIIR _MMIO(0x44018)
6939 #define GTIER _MMIO(0x4401c)
6941 #define GEN8_MASTER_IRQ _MMIO(0x44200)
6942 #define GEN8_MASTER_IRQ_CONTROL (1<<31)
6943 #define GEN8_PCU_IRQ (1<<30)
6944 #define GEN8_DE_PCH_IRQ (1<<23)
6945 #define GEN8_DE_MISC_IRQ (1<<22)
6946 #define GEN8_DE_PORT_IRQ (1<<20)
6947 #define GEN8_DE_PIPE_C_IRQ (1<<18)
6948 #define GEN8_DE_PIPE_B_IRQ (1<<17)
6949 #define GEN8_DE_PIPE_A_IRQ (1<<16)
6950 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
6951 #define GEN8_GT_VECS_IRQ (1<<6)
6952 #define GEN8_GT_GUC_IRQ (1<<5)
6953 #define GEN8_GT_PM_IRQ (1<<4)
6954 #define GEN8_GT_VCS2_IRQ (1<<3)
6955 #define GEN8_GT_VCS1_IRQ (1<<2)
6956 #define GEN8_GT_BCS_IRQ (1<<1)
6957 #define GEN8_GT_RCS_IRQ (1<<0)
6959 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
6960 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
6961 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
6962 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
6964 #define GEN9_GUC_TO_HOST_INT_EVENT (1<<31)
6965 #define GEN9_GUC_EXEC_ERROR_EVENT (1<<30)
6966 #define GEN9_GUC_DISPLAY_EVENT (1<<29)
6967 #define GEN9_GUC_SEMA_SIGNAL_EVENT (1<<28)
6968 #define GEN9_GUC_IOMMU_MSG_EVENT (1<<27)
6969 #define GEN9_GUC_DB_RING_EVENT (1<<26)
6970 #define GEN9_GUC_DMA_DONE_EVENT (1<<25)
6971 #define GEN9_GUC_FATAL_ERROR_EVENT (1<<24)
6972 #define GEN9_GUC_NOTIFICATION_EVENT (1<<23)
6974 #define GEN8_RCS_IRQ_SHIFT 0
6975 #define GEN8_BCS_IRQ_SHIFT 16
6976 #define GEN8_VCS1_IRQ_SHIFT 0
6977 #define GEN8_VCS2_IRQ_SHIFT 16
6978 #define GEN8_VECS_IRQ_SHIFT 0
6979 #define GEN8_WD_IRQ_SHIFT 16
6981 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
6982 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
6983 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
6984 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
6985 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
6986 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
6987 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
6988 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
6989 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
6990 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
6991 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
6992 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
6993 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
6994 #define GEN8_PIPE_VSYNC (1 << 1)
6995 #define GEN8_PIPE_VBLANK (1 << 0)
6996 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
6997 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
6998 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
6999 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
7000 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
7001 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
7002 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
7003 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
7004 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
7005 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
7006 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7007 (GEN8_PIPE_CURSOR_FAULT | \
7008 GEN8_PIPE_SPRITE_FAULT | \
7009 GEN8_PIPE_PRIMARY_FAULT)
7010 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7011 (GEN9_PIPE_CURSOR_FAULT | \
7012 GEN9_PIPE_PLANE4_FAULT | \
7013 GEN9_PIPE_PLANE3_FAULT | \
7014 GEN9_PIPE_PLANE2_FAULT | \
7015 GEN9_PIPE_PLANE1_FAULT)
7017 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7018 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7019 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7020 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7021 #define CNL_AUX_CHANNEL_F (1 << 28)
7022 #define GEN9_AUX_CHANNEL_D (1 << 27)
7023 #define GEN9_AUX_CHANNEL_C (1 << 26)
7024 #define GEN9_AUX_CHANNEL_B (1 << 25)
7025 #define BXT_DE_PORT_HP_DDIC (1 << 5)
7026 #define BXT_DE_PORT_HP_DDIB (1 << 4)
7027 #define BXT_DE_PORT_HP_DDIA (1 << 3)
7028 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
7029 BXT_DE_PORT_HP_DDIB | \
7030 BXT_DE_PORT_HP_DDIC)
7031 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
7032 #define BXT_DE_PORT_GMBUS (1 << 1)
7033 #define GEN8_AUX_CHANNEL_A (1 << 0)
7035 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7036 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7037 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7038 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7039 #define GEN8_DE_MISC_GSE (1 << 27)
7041 #define GEN8_PCU_ISR _MMIO(0x444e0)
7042 #define GEN8_PCU_IMR _MMIO(0x444e4)
7043 #define GEN8_PCU_IIR _MMIO(0x444e8)
7044 #define GEN8_PCU_IER _MMIO(0x444ec)
7046 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
7047 #define GEN11_MASTER_IRQ (1 << 31)
7048 #define GEN11_PCU_IRQ (1 << 30)
7049 #define GEN11_DISPLAY_IRQ (1 << 16)
7050 #define GEN11_GT_DW_IRQ(x) (1 << (x))
7051 #define GEN11_GT_DW1_IRQ (1 << 1)
7052 #define GEN11_GT_DW0_IRQ (1 << 0)
7054 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7055 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7056 #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
7057 #define GEN11_DE_PCH_IRQ (1 << 23)
7058 #define GEN11_DE_MISC_IRQ (1 << 22)
7059 #define GEN11_DE_PORT_IRQ (1 << 20)
7060 #define GEN11_DE_PIPE_C (1 << 18)
7061 #define GEN11_DE_PIPE_B (1 << 17)
7062 #define GEN11_DE_PIPE_A (1 << 16)
7064 #define GEN11_GT_INTR_DW0 _MMIO(0x190018)
7065 #define GEN11_CSME (31)
7066 #define GEN11_GUNIT (28)
7067 #define GEN11_GUC (25)
7068 #define GEN11_WDPERF (20)
7069 #define GEN11_KCR (19)
7070 #define GEN11_GTPM (16)
7071 #define GEN11_BCS (15)
7072 #define GEN11_RCS0 (0)
7074 #define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7075 #define GEN11_VECS(x) (31 - (x))
7076 #define GEN11_VCS(x) (x)
7078 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + (x * 4))
7080 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7081 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7082 #define GEN11_INTR_DATA_VALID (1 << 31)
7083 #define GEN11_INTR_ENGINE_MASK (0xffff)
7085 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + (x * 4))
7087 #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7088 #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7090 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + (x * 4))
7092 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7093 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7094 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7095 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7096 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7097 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7099 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7100 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7101 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7102 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7103 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7104 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7105 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7106 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7107 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7109 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7110 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7111 #define ILK_ELPIN_409_SELECT (1 << 25)
7112 #define ILK_DPARB_GATE (1<<22)
7113 #define ILK_VSDPFD_FULL (1<<21)
7114 #define FUSE_STRAP _MMIO(0x42014)
7115 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7116 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7117 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
7118 #define IVB_PIPE_C_DISABLE (1 << 28)
7119 #define ILK_HDCP_DISABLE (1 << 25)
7120 #define ILK_eDP_A_DISABLE (1 << 24)
7121 #define HSW_CDCLK_LIMIT (1 << 24)
7122 #define ILK_DESKTOP (1 << 23)
7124 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7125 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7126 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7127 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7128 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7129 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7131 #define IVB_CHICKEN3 _MMIO(0x4200c)
7132 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7133 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7135 #define CHICKEN_PAR1_1 _MMIO(0x42080)
7136 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
7137 #define DPA_MASK_VBLANK_SRD (1 << 15)
7138 #define FORCE_ARB_IDLE_PLANES (1 << 14)
7139 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7141 #define CHICKEN_PAR2_1 _MMIO(0x42090)
7142 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
7144 #define CHICKEN_MISC_2 _MMIO(0x42084)
7145 #define CNL_COMP_PWR_DOWN (1 << 23)
7146 #define GLK_CL2_PWR_DOWN (1 << 12)
7147 #define GLK_CL1_PWR_DOWN (1 << 11)
7148 #define GLK_CL0_PWR_DOWN (1 << 10)
7150 #define CHICKEN_MISC_4 _MMIO(0x4208c)
7151 #define FBC_STRIDE_OVERRIDE (1 << 13)
7152 #define FBC_STRIDE_MASK 0x1FFF
7154 #define _CHICKEN_PIPESL_1_A 0x420b0
7155 #define _CHICKEN_PIPESL_1_B 0x420b4
7156 #define HSW_FBCQ_DIS (1 << 22)
7157 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7158 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7160 #define CHICKEN_TRANS_A 0x420c0
7161 #define CHICKEN_TRANS_B 0x420c4
7162 #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
7163 #define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
7164 #define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
7165 #define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
7166 #define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
7167 #define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
7168 #define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
7170 #define DISP_ARB_CTL _MMIO(0x45000)
7171 #define DISP_FBC_MEMORY_WAKE (1<<31)
7172 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
7173 #define DISP_FBC_WM_DIS (1<<15)
7174 #define DISP_ARB_CTL2 _MMIO(0x45004)
7175 #define DISP_DATA_PARTITION_5_6 (1<<6)
7176 #define DISP_IPC_ENABLE (1<<3)
7177 #define DBUF_CTL _MMIO(0x45008)
7178 #define DBUF_CTL_S1 _MMIO(0x45008)
7179 #define DBUF_CTL_S2 _MMIO(0x44FE8)
7180 #define DBUF_POWER_REQUEST (1<<31)
7181 #define DBUF_POWER_STATE (1<<30)
7182 #define GEN7_MSG_CTL _MMIO(0x45010)
7183 #define WAIT_FOR_PCH_RESET_ACK (1<<1)
7184 #define WAIT_FOR_PCH_FLR_ACK (1<<0)
7185 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
7186 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
7188 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
7189 #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
7190 #define MASK_WAKEMEM (1 << 13)
7191 #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
7193 #define SKL_DFSM _MMIO(0x51000)
7194 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7195 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7196 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7197 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7198 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
7199 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7200 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7201 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
7203 #define SKL_DSSM _MMIO(0x51004)
7204 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
7205 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
7206 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
7207 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
7208 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
7210 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
7211 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
7213 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
7214 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
7215 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1<<10)
7217 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
7218 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
7219 #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
7220 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1<<0)
7221 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
7222 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7223 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7224 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7225 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7228 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
7229 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
7230 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
7231 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
7232 # define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
7233 # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
7234 # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
7235 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
7237 #define HIZ_CHICKEN _MMIO(0x7018)
7238 # define CHV_HZ_8X8_MODE_IN_1X (1<<15)
7239 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
7241 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
7242 #define DISABLE_PIXEL_MASK_CAMMING (1<<14)
7244 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7246 #define GEN7_L3SQCREG1 _MMIO(0xB010)
7247 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7249 #define GEN8_L3SQCREG1 _MMIO(0xB100)
7251 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7252 * Using the formula in BSpec leads to a hang, while the formula here works
7253 * fine and matches the formulas for all other platforms. A BSpec change
7254 * request has been filed to clarify this.
7256 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
7257 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
7258 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
7260 #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
7261 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
7262 #define GEN7_L3AGDIS (1<<19)
7263 #define GEN7_L3CNTLREG2 _MMIO(0xB020)
7264 #define GEN7_L3CNTLREG3 _MMIO(0xB024)
7266 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
7267 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
7269 #define GEN7_L3SQCREG4 _MMIO(0xb034)
7270 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
7272 #define GEN8_L3SQCREG4 _MMIO(0xb118)
7273 #define GEN8_LQSC_RO_PERF_DIS (1<<27)
7274 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
7277 #define HDC_CHICKEN0 _MMIO(0x7300)
7278 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
7279 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
7280 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
7281 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
7282 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
7283 #define HDC_FORCE_NON_COHERENT (1<<4)
7284 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
7286 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
7289 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
7290 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
7292 /* WaCatErrorRejectionIssue */
7293 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
7294 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
7296 #define HSW_SCRATCH1 _MMIO(0xb038)
7297 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
7299 #define BDW_SCRATCH1 _MMIO(0xb11c)
7300 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
7304 /* south display engine interrupt: IBX */
7305 #define SDE_AUDIO_POWER_D (1 << 27)
7306 #define SDE_AUDIO_POWER_C (1 << 26)
7307 #define SDE_AUDIO_POWER_B (1 << 25)
7308 #define SDE_AUDIO_POWER_SHIFT (25)
7309 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
7310 #define SDE_GMBUS (1 << 24)
7311 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
7312 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
7313 #define SDE_AUDIO_HDCP_MASK (3 << 22)
7314 #define SDE_AUDIO_TRANSB (1 << 21)
7315 #define SDE_AUDIO_TRANSA (1 << 20)
7316 #define SDE_AUDIO_TRANS_MASK (3 << 20)
7317 #define SDE_POISON (1 << 19)
7319 #define SDE_FDI_RXB (1 << 17)
7320 #define SDE_FDI_RXA (1 << 16)
7321 #define SDE_FDI_MASK (3 << 16)
7322 #define SDE_AUXD (1 << 15)
7323 #define SDE_AUXC (1 << 14)
7324 #define SDE_AUXB (1 << 13)
7325 #define SDE_AUX_MASK (7 << 13)
7327 #define SDE_CRT_HOTPLUG (1 << 11)
7328 #define SDE_PORTD_HOTPLUG (1 << 10)
7329 #define SDE_PORTC_HOTPLUG (1 << 9)
7330 #define SDE_PORTB_HOTPLUG (1 << 8)
7331 #define SDE_SDVOB_HOTPLUG (1 << 6)
7332 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
7333 SDE_SDVOB_HOTPLUG | \
7334 SDE_PORTB_HOTPLUG | \
7335 SDE_PORTC_HOTPLUG | \
7337 #define SDE_TRANSB_CRC_DONE (1 << 5)
7338 #define SDE_TRANSB_CRC_ERR (1 << 4)
7339 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
7340 #define SDE_TRANSA_CRC_DONE (1 << 2)
7341 #define SDE_TRANSA_CRC_ERR (1 << 1)
7342 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
7343 #define SDE_TRANS_MASK (0x3f)
7345 /* south display engine interrupt: CPT/PPT */
7346 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
7347 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
7348 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
7349 #define SDE_AUDIO_POWER_SHIFT_CPT 29
7350 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
7351 #define SDE_AUXD_CPT (1 << 27)
7352 #define SDE_AUXC_CPT (1 << 26)
7353 #define SDE_AUXB_CPT (1 << 25)
7354 #define SDE_AUX_MASK_CPT (7 << 25)
7355 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
7356 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
7357 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
7358 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
7359 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
7360 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
7361 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
7362 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
7363 SDE_SDVOB_HOTPLUG_CPT | \
7364 SDE_PORTD_HOTPLUG_CPT | \
7365 SDE_PORTC_HOTPLUG_CPT | \
7366 SDE_PORTB_HOTPLUG_CPT)
7367 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
7368 SDE_PORTD_HOTPLUG_CPT | \
7369 SDE_PORTC_HOTPLUG_CPT | \
7370 SDE_PORTB_HOTPLUG_CPT | \
7371 SDE_PORTA_HOTPLUG_SPT)
7372 #define SDE_GMBUS_CPT (1 << 17)
7373 #define SDE_ERROR_CPT (1 << 16)
7374 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
7375 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
7376 #define SDE_FDI_RXC_CPT (1 << 8)
7377 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
7378 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
7379 #define SDE_FDI_RXB_CPT (1 << 4)
7380 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
7381 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
7382 #define SDE_FDI_RXA_CPT (1 << 0)
7383 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
7384 SDE_AUDIO_CP_REQ_B_CPT | \
7385 SDE_AUDIO_CP_REQ_A_CPT)
7386 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
7387 SDE_AUDIO_CP_CHG_B_CPT | \
7388 SDE_AUDIO_CP_CHG_A_CPT)
7389 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
7393 #define SDEISR _MMIO(0xc4000)
7394 #define SDEIMR _MMIO(0xc4004)
7395 #define SDEIIR _MMIO(0xc4008)
7396 #define SDEIER _MMIO(0xc400c)
7398 #define SERR_INT _MMIO(0xc4040)
7399 #define SERR_INT_POISON (1<<31)
7400 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
7402 /* digital port hotplug */
7403 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
7404 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
7405 #define BXT_DDIA_HPD_INVERT (1 << 27)
7406 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
7407 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
7408 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
7409 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
7410 #define PORTD_HOTPLUG_ENABLE (1 << 20)
7411 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
7412 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
7413 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
7414 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
7415 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
7416 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
7417 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
7418 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
7419 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
7420 #define PORTC_HOTPLUG_ENABLE (1 << 12)
7421 #define BXT_DDIC_HPD_INVERT (1 << 11)
7422 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
7423 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
7424 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
7425 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
7426 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
7427 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
7428 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
7429 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
7430 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
7431 #define PORTB_HOTPLUG_ENABLE (1 << 4)
7432 #define BXT_DDIB_HPD_INVERT (1 << 3)
7433 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
7434 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
7435 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
7436 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
7437 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
7438 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
7439 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
7440 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
7441 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
7442 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
7443 BXT_DDIB_HPD_INVERT | \
7444 BXT_DDIC_HPD_INVERT)
7446 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
7447 #define PORTE_HOTPLUG_ENABLE (1 << 4)
7448 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
7449 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
7450 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
7451 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
7453 #define PCH_GPIOA _MMIO(0xc5010)
7454 #define PCH_GPIOB _MMIO(0xc5014)
7455 #define PCH_GPIOC _MMIO(0xc5018)
7456 #define PCH_GPIOD _MMIO(0xc501c)
7457 #define PCH_GPIOE _MMIO(0xc5020)
7458 #define PCH_GPIOF _MMIO(0xc5024)
7460 #define PCH_GMBUS0 _MMIO(0xc5100)
7461 #define PCH_GMBUS1 _MMIO(0xc5104)
7462 #define PCH_GMBUS2 _MMIO(0xc5108)
7463 #define PCH_GMBUS3 _MMIO(0xc510c)
7464 #define PCH_GMBUS4 _MMIO(0xc5110)
7465 #define PCH_GMBUS5 _MMIO(0xc5120)
7467 #define _PCH_DPLL_A 0xc6014
7468 #define _PCH_DPLL_B 0xc6018
7469 #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
7471 #define _PCH_FPA0 0xc6040
7472 #define FP_CB_TUNE (0x3<<22)
7473 #define _PCH_FPA1 0xc6044
7474 #define _PCH_FPB0 0xc6048
7475 #define _PCH_FPB1 0xc604c
7476 #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
7477 #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
7479 #define PCH_DPLL_TEST _MMIO(0xc606c)
7481 #define PCH_DREF_CONTROL _MMIO(0xC6200)
7482 #define DREF_CONTROL_MASK 0x7fc3
7483 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
7484 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
7485 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
7486 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
7487 #define DREF_SSC_SOURCE_DISABLE (0<<11)
7488 #define DREF_SSC_SOURCE_ENABLE (2<<11)
7489 #define DREF_SSC_SOURCE_MASK (3<<11)
7490 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
7491 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
7492 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
7493 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
7494 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
7495 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
7496 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
7497 #define DREF_SSC4_DOWNSPREAD (0<<6)
7498 #define DREF_SSC4_CENTERSPREAD (1<<6)
7499 #define DREF_SSC1_DISABLE (0<<1)
7500 #define DREF_SSC1_ENABLE (1<<1)
7501 #define DREF_SSC4_DISABLE (0)
7502 #define DREF_SSC4_ENABLE (1)
7504 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
7505 #define FDL_TP1_TIMER_SHIFT 12
7506 #define FDL_TP1_TIMER_MASK (3<<12)
7507 #define FDL_TP2_TIMER_SHIFT 10
7508 #define FDL_TP2_TIMER_MASK (3<<10)
7509 #define RAWCLK_FREQ_MASK 0x3ff
7510 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
7511 #define CNP_RAWCLK_DIV(div) ((div) << 16)
7512 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
7513 #define CNP_RAWCLK_FRAC(frac) ((frac) << 26)
7514 #define ICP_RAWCLK_DEN(den) ((den) << 26)
7515 #define ICP_RAWCLK_NUM(num) ((num) << 11)
7517 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
7519 #define PCH_SSC4_PARMS _MMIO(0xc6210)
7520 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
7522 #define PCH_DPLL_SEL _MMIO(0xc7000)
7523 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
7524 #define TRANS_DPLLA_SEL(pipe) 0
7525 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
7529 #define _PCH_TRANS_HTOTAL_A 0xe0000
7530 #define TRANS_HTOTAL_SHIFT 16
7531 #define TRANS_HACTIVE_SHIFT 0
7532 #define _PCH_TRANS_HBLANK_A 0xe0004
7533 #define TRANS_HBLANK_END_SHIFT 16
7534 #define TRANS_HBLANK_START_SHIFT 0
7535 #define _PCH_TRANS_HSYNC_A 0xe0008
7536 #define TRANS_HSYNC_END_SHIFT 16
7537 #define TRANS_HSYNC_START_SHIFT 0
7538 #define _PCH_TRANS_VTOTAL_A 0xe000c
7539 #define TRANS_VTOTAL_SHIFT 16
7540 #define TRANS_VACTIVE_SHIFT 0
7541 #define _PCH_TRANS_VBLANK_A 0xe0010
7542 #define TRANS_VBLANK_END_SHIFT 16
7543 #define TRANS_VBLANK_START_SHIFT 0
7544 #define _PCH_TRANS_VSYNC_A 0xe0014
7545 #define TRANS_VSYNC_END_SHIFT 16
7546 #define TRANS_VSYNC_START_SHIFT 0
7547 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
7549 #define _PCH_TRANSA_DATA_M1 0xe0030
7550 #define _PCH_TRANSA_DATA_N1 0xe0034
7551 #define _PCH_TRANSA_DATA_M2 0xe0038
7552 #define _PCH_TRANSA_DATA_N2 0xe003c
7553 #define _PCH_TRANSA_LINK_M1 0xe0040
7554 #define _PCH_TRANSA_LINK_N1 0xe0044
7555 #define _PCH_TRANSA_LINK_M2 0xe0048
7556 #define _PCH_TRANSA_LINK_N2 0xe004c
7558 /* Per-transcoder DIP controls (PCH) */
7559 #define _VIDEO_DIP_CTL_A 0xe0200
7560 #define _VIDEO_DIP_DATA_A 0xe0208
7561 #define _VIDEO_DIP_GCP_A 0xe0210
7562 #define GCP_COLOR_INDICATION (1 << 2)
7563 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
7564 #define GCP_AV_MUTE (1 << 0)
7566 #define _VIDEO_DIP_CTL_B 0xe1200
7567 #define _VIDEO_DIP_DATA_B 0xe1208
7568 #define _VIDEO_DIP_GCP_B 0xe1210
7570 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
7571 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
7572 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
7574 /* Per-transcoder DIP controls (VLV) */
7575 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
7576 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
7577 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
7579 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
7580 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
7581 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
7583 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
7584 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
7585 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
7587 #define VLV_TVIDEO_DIP_CTL(pipe) \
7588 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
7589 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
7590 #define VLV_TVIDEO_DIP_DATA(pipe) \
7591 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
7592 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
7593 #define VLV_TVIDEO_DIP_GCP(pipe) \
7594 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
7595 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
7597 /* Haswell DIP controls */
7599 #define _HSW_VIDEO_DIP_CTL_A 0x60200
7600 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
7601 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
7602 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
7603 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
7604 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
7605 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
7606 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
7607 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
7608 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
7609 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
7610 #define _HSW_VIDEO_DIP_GCP_A 0x60210
7612 #define _HSW_VIDEO_DIP_CTL_B 0x61200
7613 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
7614 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
7615 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
7616 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
7617 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
7618 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
7619 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
7620 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
7621 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
7622 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
7623 #define _HSW_VIDEO_DIP_GCP_B 0x61210
7625 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
7626 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
7627 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
7628 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
7629 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
7630 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
7632 #define _HSW_STEREO_3D_CTL_A 0x70020
7633 #define S3D_ENABLE (1<<31)
7634 #define _HSW_STEREO_3D_CTL_B 0x71020
7636 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
7638 #define _PCH_TRANS_HTOTAL_B 0xe1000
7639 #define _PCH_TRANS_HBLANK_B 0xe1004
7640 #define _PCH_TRANS_HSYNC_B 0xe1008
7641 #define _PCH_TRANS_VTOTAL_B 0xe100c
7642 #define _PCH_TRANS_VBLANK_B 0xe1010
7643 #define _PCH_TRANS_VSYNC_B 0xe1014
7644 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
7646 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
7647 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
7648 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
7649 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
7650 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
7651 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
7652 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
7654 #define _PCH_TRANSB_DATA_M1 0xe1030
7655 #define _PCH_TRANSB_DATA_N1 0xe1034
7656 #define _PCH_TRANSB_DATA_M2 0xe1038
7657 #define _PCH_TRANSB_DATA_N2 0xe103c
7658 #define _PCH_TRANSB_LINK_M1 0xe1040
7659 #define _PCH_TRANSB_LINK_N1 0xe1044
7660 #define _PCH_TRANSB_LINK_M2 0xe1048
7661 #define _PCH_TRANSB_LINK_N2 0xe104c
7663 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
7664 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
7665 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
7666 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
7667 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
7668 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
7669 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
7670 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
7672 #define _PCH_TRANSACONF 0xf0008
7673 #define _PCH_TRANSBCONF 0xf1008
7674 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
7675 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
7676 #define TRANS_DISABLE (0<<31)
7677 #define TRANS_ENABLE (1<<31)
7678 #define TRANS_STATE_MASK (1<<30)
7679 #define TRANS_STATE_DISABLE (0<<30)
7680 #define TRANS_STATE_ENABLE (1<<30)
7681 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
7682 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
7683 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
7684 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
7685 #define TRANS_INTERLACE_MASK (7<<21)
7686 #define TRANS_PROGRESSIVE (0<<21)
7687 #define TRANS_INTERLACED (3<<21)
7688 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
7689 #define TRANS_8BPC (0<<5)
7690 #define TRANS_10BPC (1<<5)
7691 #define TRANS_6BPC (2<<5)
7692 #define TRANS_12BPC (3<<5)
7694 #define _TRANSA_CHICKEN1 0xf0060
7695 #define _TRANSB_CHICKEN1 0xf1060
7696 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
7697 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
7698 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
7699 #define _TRANSA_CHICKEN2 0xf0064
7700 #define _TRANSB_CHICKEN2 0xf1064
7701 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
7702 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
7703 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
7704 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
7705 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
7706 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
7708 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
7709 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
7710 #define FDIA_PHASE_SYNC_SHIFT_EN 18
7711 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
7712 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
7713 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
7714 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
7715 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
7716 #define SPT_PWM_GRANULARITY (1<<0)
7717 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
7718 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
7719 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
7720 #define LPT_PWM_GRANULARITY (1<<5)
7721 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
7723 #define _FDI_RXA_CHICKEN 0xc200c
7724 #define _FDI_RXB_CHICKEN 0xc2010
7725 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
7726 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
7727 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
7729 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
7730 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1<<31)
7731 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
7732 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
7733 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
7734 #define CNP_PWM_CGE_GATING_DISABLE (1<<13)
7735 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
7738 #define _FDI_TXA_CTL 0x60100
7739 #define _FDI_TXB_CTL 0x61100
7740 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
7741 #define FDI_TX_DISABLE (0<<31)
7742 #define FDI_TX_ENABLE (1<<31)
7743 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
7744 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
7745 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
7746 #define FDI_LINK_TRAIN_NONE (3<<28)
7747 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
7748 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
7749 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
7750 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
7751 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
7752 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
7753 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
7754 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
7755 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
7756 SNB has different settings. */
7757 /* SNB A-stepping */
7758 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
7759 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
7760 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
7761 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
7762 /* SNB B-stepping */
7763 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
7764 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
7765 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
7766 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
7767 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
7768 #define FDI_DP_PORT_WIDTH_SHIFT 19
7769 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
7770 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
7771 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
7772 /* Ironlake: hardwired to 1 */
7773 #define FDI_TX_PLL_ENABLE (1<<14)
7775 /* Ivybridge has different bits for lolz */
7776 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
7777 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
7778 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
7779 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
7781 /* both Tx and Rx */
7782 #define FDI_COMPOSITE_SYNC (1<<11)
7783 #define FDI_LINK_TRAIN_AUTO (1<<10)
7784 #define FDI_SCRAMBLING_ENABLE (0<<7)
7785 #define FDI_SCRAMBLING_DISABLE (1<<7)
7787 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
7788 #define _FDI_RXA_CTL 0xf000c
7789 #define _FDI_RXB_CTL 0xf100c
7790 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
7791 #define FDI_RX_ENABLE (1<<31)
7792 /* train, dp width same as FDI_TX */
7793 #define FDI_FS_ERRC_ENABLE (1<<27)
7794 #define FDI_FE_ERRC_ENABLE (1<<26)
7795 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
7796 #define FDI_8BPC (0<<16)
7797 #define FDI_10BPC (1<<16)
7798 #define FDI_6BPC (2<<16)
7799 #define FDI_12BPC (3<<16)
7800 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
7801 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
7802 #define FDI_RX_PLL_ENABLE (1<<13)
7803 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
7804 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
7805 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
7806 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
7807 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
7808 #define FDI_PCDCLK (1<<4)
7810 #define FDI_AUTO_TRAINING (1<<10)
7811 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
7812 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
7813 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
7814 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
7815 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
7817 #define _FDI_RXA_MISC 0xf0010
7818 #define _FDI_RXB_MISC 0xf1010
7819 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
7820 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
7821 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
7822 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
7823 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
7824 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
7825 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
7826 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
7828 #define _FDI_RXA_TUSIZE1 0xf0030
7829 #define _FDI_RXA_TUSIZE2 0xf0038
7830 #define _FDI_RXB_TUSIZE1 0xf1030
7831 #define _FDI_RXB_TUSIZE2 0xf1038
7832 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
7833 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
7835 /* FDI_RX interrupt register format */
7836 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
7837 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
7838 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
7839 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
7840 #define FDI_RX_FS_CODE_ERR (1<<6)
7841 #define FDI_RX_FE_CODE_ERR (1<<5)
7842 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
7843 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
7844 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
7845 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
7846 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
7848 #define _FDI_RXA_IIR 0xf0014
7849 #define _FDI_RXA_IMR 0xf0018
7850 #define _FDI_RXB_IIR 0xf1014
7851 #define _FDI_RXB_IMR 0xf1018
7852 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
7853 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
7855 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
7856 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
7858 #define PCH_LVDS _MMIO(0xe1180)
7859 #define LVDS_DETECTED (1 << 1)
7861 #define _PCH_DP_B 0xe4100
7862 #define PCH_DP_B _MMIO(_PCH_DP_B)
7863 #define _PCH_DPB_AUX_CH_CTL 0xe4110
7864 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
7865 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
7866 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
7867 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
7868 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
7870 #define _PCH_DP_C 0xe4200
7871 #define PCH_DP_C _MMIO(_PCH_DP_C)
7872 #define _PCH_DPC_AUX_CH_CTL 0xe4210
7873 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
7874 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
7875 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
7876 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
7877 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
7879 #define _PCH_DP_D 0xe4300
7880 #define PCH_DP_D _MMIO(_PCH_DP_D)
7881 #define _PCH_DPD_AUX_CH_CTL 0xe4310
7882 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
7883 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
7884 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
7885 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
7886 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
7888 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
7889 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
7892 #define PORT_TRANS_A_SEL_CPT 0
7893 #define PORT_TRANS_B_SEL_CPT (1<<29)
7894 #define PORT_TRANS_C_SEL_CPT (2<<29)
7895 #define PORT_TRANS_SEL_MASK (3<<29)
7896 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
7897 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
7898 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
7899 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
7900 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
7902 #define _TRANS_DP_CTL_A 0xe0300
7903 #define _TRANS_DP_CTL_B 0xe1300
7904 #define _TRANS_DP_CTL_C 0xe2300
7905 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
7906 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
7907 #define TRANS_DP_PORT_SEL_B (0<<29)
7908 #define TRANS_DP_PORT_SEL_C (1<<29)
7909 #define TRANS_DP_PORT_SEL_D (2<<29)
7910 #define TRANS_DP_PORT_SEL_NONE (3<<29)
7911 #define TRANS_DP_PORT_SEL_MASK (3<<29)
7912 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
7913 #define TRANS_DP_AUDIO_ONLY (1<<26)
7914 #define TRANS_DP_ENH_FRAMING (1<<18)
7915 #define TRANS_DP_8BPC (0<<9)
7916 #define TRANS_DP_10BPC (1<<9)
7917 #define TRANS_DP_6BPC (2<<9)
7918 #define TRANS_DP_12BPC (3<<9)
7919 #define TRANS_DP_BPC_MASK (3<<9)
7920 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
7921 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
7922 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
7923 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
7924 #define TRANS_DP_SYNC_MASK (3<<3)
7926 /* SNB eDP training params */
7927 /* SNB A-stepping */
7928 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
7929 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
7930 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
7931 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
7932 /* SNB B-stepping */
7933 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
7934 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
7935 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
7936 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
7937 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
7938 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
7941 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
7942 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
7943 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
7944 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
7945 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
7946 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
7947 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
7950 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
7951 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
7952 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
7953 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
7954 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
7956 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
7958 #define VLV_PMWGICZ _MMIO(0x1300a4)
7960 #define RC6_LOCATION _MMIO(0xD40)
7961 #define RC6_CTX_IN_DRAM (1 << 0)
7962 #define RC6_CTX_BASE _MMIO(0xD48)
7963 #define RC6_CTX_BASE_MASK 0xFFFFFFF0
7964 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
7965 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
7966 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
7967 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
7968 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
7969 #define IDLE_TIME_MASK 0xFFFFF
7970 #define FORCEWAKE _MMIO(0xA18C)
7971 #define FORCEWAKE_VLV _MMIO(0x1300b0)
7972 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
7973 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
7974 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
7975 #define FORCEWAKE_ACK_HSW _MMIO(0x130044)
7976 #define FORCEWAKE_ACK _MMIO(0x130090)
7977 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
7978 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
7979 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
7980 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
7982 #define VLV_GTLC_PW_STATUS _MMIO(0x130094)
7983 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
7984 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
7985 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
7986 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
7987 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
7988 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
7989 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
7990 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
7991 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
7992 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
7993 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
7994 #define FORCEWAKE_KERNEL BIT(0)
7995 #define FORCEWAKE_USER BIT(1)
7996 #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
7997 #define FORCEWAKE_MT_ACK _MMIO(0x130040)
7998 #define ECOBUS _MMIO(0xa180)
7999 #define FORCEWAKE_MT_ENABLE (1<<5)
8000 #define VLV_SPAREG2H _MMIO(0xA194)
8001 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
8002 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
8003 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
8005 #define GTFIFODBG _MMIO(0x120000)
8006 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
8007 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
8008 #define GT_FIFO_SBDROPERR (1<<6)
8009 #define GT_FIFO_BLOBDROPERR (1<<5)
8010 #define GT_FIFO_SB_READ_ABORTERR (1<<4)
8011 #define GT_FIFO_DROPERR (1<<3)
8012 #define GT_FIFO_OVFERR (1<<2)
8013 #define GT_FIFO_IAWRERR (1<<1)
8014 #define GT_FIFO_IARDERR (1<<0)
8016 #define GTFIFOCTL _MMIO(0x120008)
8017 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
8018 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
8019 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
8020 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
8022 #define HSW_IDICR _MMIO(0x9008)
8023 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
8024 #define HSW_EDRAM_CAP _MMIO(0x120010)
8025 #define EDRAM_ENABLED 0x1
8026 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
8027 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
8028 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
8030 #define GEN6_UCGCTL1 _MMIO(0x9400)
8031 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
8032 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
8033 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
8034 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
8036 #define GEN6_UCGCTL2 _MMIO(0x9404)
8037 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
8038 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
8039 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
8040 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
8041 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
8042 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
8044 #define GEN6_UCGCTL3 _MMIO(0x9408)
8045 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
8047 #define GEN7_UCGCTL4 _MMIO(0x940c)
8048 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
8049 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
8051 #define GEN6_RCGCTL1 _MMIO(0x9410)
8052 #define GEN6_RCGCTL2 _MMIO(0x9414)
8053 #define GEN6_RSTCTL _MMIO(0x9420)
8055 #define GEN8_UCGCTL6 _MMIO(0x9430)
8056 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
8057 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
8058 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
8060 #define GEN6_GFXPAUSE _MMIO(0xA000)
8061 #define GEN6_RPNSWREQ _MMIO(0xA008)
8062 #define GEN6_TURBO_DISABLE (1<<31)
8063 #define GEN6_FREQUENCY(x) ((x)<<25)
8064 #define HSW_FREQUENCY(x) ((x)<<24)
8065 #define GEN9_FREQUENCY(x) ((x)<<23)
8066 #define GEN6_OFFSET(x) ((x)<<19)
8067 #define GEN6_AGGRESSIVE_TURBO (0<<15)
8068 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
8069 #define GEN6_RC_CONTROL _MMIO(0xA090)
8070 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
8071 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
8072 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
8073 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
8074 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
8075 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
8076 #define GEN7_RC_CTL_TO_MODE (1<<28)
8077 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
8078 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
8079 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
8080 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
8081 #define GEN6_RPSTAT1 _MMIO(0xA01C)
8082 #define GEN6_CAGF_SHIFT 8
8083 #define HSW_CAGF_SHIFT 7
8084 #define GEN9_CAGF_SHIFT 23
8085 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
8086 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
8087 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
8088 #define GEN6_RP_CONTROL _MMIO(0xA024)
8089 #define GEN6_RP_MEDIA_TURBO (1<<11)
8090 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
8091 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
8092 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
8093 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
8094 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
8095 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
8096 #define GEN6_RP_ENABLE (1<<7)
8097 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
8098 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
8099 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
8100 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
8101 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
8102 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
8103 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
8104 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
8105 #define GEN6_RP_EI_MASK 0xffffff
8106 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
8107 #define GEN6_RP_CUR_UP _MMIO(0xA054)
8108 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
8109 #define GEN6_RP_PREV_UP _MMIO(0xA058)
8110 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
8111 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
8112 #define GEN6_RP_CUR_DOWN _MMIO(0xA060)
8113 #define GEN6_RP_PREV_DOWN _MMIO(0xA064)
8114 #define GEN6_RP_UP_EI _MMIO(0xA068)
8115 #define GEN6_RP_DOWN_EI _MMIO(0xA06C)
8116 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
8117 #define GEN6_RPDEUHWTC _MMIO(0xA080)
8118 #define GEN6_RPDEUC _MMIO(0xA084)
8119 #define GEN6_RPDEUCSW _MMIO(0xA088)
8120 #define GEN6_RC_STATE _MMIO(0xA094)
8121 #define RC_SW_TARGET_STATE_SHIFT 16
8122 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
8123 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
8124 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
8125 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8126 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8127 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
8128 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
8129 #define GEN6_RC_SLEEP _MMIO(0xA0B0)
8130 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
8131 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
8132 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
8133 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
8134 #define VLV_RCEDATA _MMIO(0xA0BC)
8135 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
8136 #define GEN6_PMINTRMSK _MMIO(0xA168)
8137 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1<<31)
8138 #define ARAT_EXPIRED_INTRMSK (1<<9)
8139 #define GEN8_MISC_CTRL0 _MMIO(0xA180)
8140 #define VLV_PWRDWNUPCTL _MMIO(0xA294)
8141 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8142 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8143 #define GEN9_PG_ENABLE _MMIO(0xA210)
8144 #define GEN9_RENDER_PG_ENABLE (1<<0)
8145 #define GEN9_MEDIA_PG_ENABLE (1<<1)
8146 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8147 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8148 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
8150 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8151 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
8152 #define PIXEL_OVERLAP_CNT_SHIFT 30
8154 #define GEN6_PMISR _MMIO(0x44020)
8155 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
8156 #define GEN6_PMIIR _MMIO(0x44028)
8157 #define GEN6_PMIER _MMIO(0x4402C)
8158 #define GEN6_PM_MBOX_EVENT (1<<25)
8159 #define GEN6_PM_THERMAL_EVENT (1<<24)
8160 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
8161 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
8162 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
8163 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
8164 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
8165 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
8166 GEN6_PM_RP_DOWN_THRESHOLD | \
8167 GEN6_PM_RP_DOWN_TIMEOUT)
8169 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
8170 #define GEN7_GT_SCRATCH_REG_NUM 8
8172 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
8173 #define VLV_GFX_CLK_STATUS_BIT (1<<3)
8174 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
8176 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
8177 #define VLV_COUNTER_CONTROL _MMIO(0x138104)
8178 #define VLV_COUNT_RANGE_HIGH (1<<15)
8179 #define VLV_MEDIA_RC0_COUNT_EN (1<<5)
8180 #define VLV_RENDER_RC0_COUNT_EN (1<<4)
8181 #define VLV_MEDIA_RC6_COUNT_EN (1<<1)
8182 #define VLV_RENDER_RC6_COUNT_EN (1<<0)
8183 #define GEN6_GT_GFX_RC6 _MMIO(0x138108)
8184 #define VLV_GT_RENDER_RC6 _MMIO(0x138108)
8185 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
8187 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
8188 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
8189 #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
8190 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
8192 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8193 #define GEN6_PCODE_READY (1<<31)
8194 #define GEN6_PCODE_ERROR_MASK 0xFF
8195 #define GEN6_PCODE_SUCCESS 0x0
8196 #define GEN6_PCODE_ILLEGAL_CMD 0x1
8197 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8198 #define GEN6_PCODE_TIMEOUT 0x3
8199 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8200 #define GEN7_PCODE_TIMEOUT 0x2
8201 #define GEN7_PCODE_ILLEGAL_DATA 0x3
8202 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8203 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
8204 #define GEN6_PCODE_READ_RC6VIDS 0x5
8205 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
8206 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
8207 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
8208 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
8209 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
8210 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
8211 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
8212 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
8213 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
8214 #define SKL_PCODE_CDCLK_CONTROL 0x7
8215 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
8216 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
8217 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8218 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8219 #define GEN6_READ_OC_PARAMS 0xc
8220 #define GEN6_PCODE_READ_D_COMP 0x10
8221 #define GEN6_PCODE_WRITE_D_COMP 0x11
8222 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
8223 #define DISPLAY_IPS_CONTROL 0x19
8224 /* See also IPS_CTL */
8225 #define IPS_PCODE_CONTROL (1 << 30)
8226 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
8227 #define GEN9_PCODE_SAGV_CONTROL 0x21
8228 #define GEN9_SAGV_DISABLE 0x0
8229 #define GEN9_SAGV_IS_DISABLED 0x1
8230 #define GEN9_SAGV_ENABLE 0x3
8231 #define GEN6_PCODE_DATA _MMIO(0x138128)
8232 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
8233 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
8234 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
8236 #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
8237 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
8238 #define GEN6_RCn_MASK 7
8244 #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
8245 #define GEN8_LSLICESTAT_MASK 0x7
8247 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
8248 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
8249 #define CHV_SS_PG_ENABLE (1<<1)
8250 #define CHV_EU08_PG_ENABLE (1<<9)
8251 #define CHV_EU19_PG_ENABLE (1<<17)
8252 #define CHV_EU210_PG_ENABLE (1<<25)
8254 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
8255 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
8256 #define CHV_EU311_PG_ENABLE (1<<1)
8258 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
8259 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8260 ((slice) % 3) * 0x4)
8261 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
8262 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
8263 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8265 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
8266 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8267 ((slice) % 3) * 0x8)
8268 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
8269 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8270 ((slice) % 3) * 0x8)
8271 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
8272 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
8273 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
8274 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
8275 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
8276 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
8277 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
8278 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
8280 #define GEN7_MISCCPCTL _MMIO(0x9424)
8281 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
8282 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
8283 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
8284 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
8286 #define GEN8_GARBCNTL _MMIO(0xB004)
8287 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
8290 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
8291 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
8292 #define GEN7_PARITY_ERROR_VALID (1<<13)
8293 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
8294 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
8295 #define GEN7_PARITY_ERROR_ROW(reg) \
8296 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8297 #define GEN7_PARITY_ERROR_BANK(reg) \
8298 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8299 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
8300 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8301 #define GEN7_L3CDERRST1_ENABLE (1<<7)
8303 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8304 #define GEN7_L3LOG_SIZE 0x80
8306 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
8307 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
8308 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
8309 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
8310 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
8311 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
8313 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
8314 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
8315 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
8317 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
8318 #define FLOW_CONTROL_ENABLE (1<<15)
8319 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
8320 #define STALL_DOP_GATING_DISABLE (1<<5)
8321 #define THROTTLE_12_5 (7<<2)
8322 #define DISABLE_EARLY_EOT (1<<1)
8324 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
8325 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
8326 #define DOP_CLOCK_GATING_DISABLE (1<<0)
8327 #define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
8329 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
8330 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
8332 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
8333 #define GEN8_ST_PO_DISABLE (1<<13)
8335 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
8336 #define HSW_SAMPLE_C_PERFORMANCE (1<<9)
8337 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
8338 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
8339 #define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
8340 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
8342 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
8343 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1<<8)
8344 #define GEN9_ENABLE_YV12_BUGFIX (1<<4)
8345 #define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2)
8348 #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
8349 #define INTEL_AUDIO_DEVCL 0x808629FB
8350 #define INTEL_AUDIO_DEVBLC 0x80862801
8351 #define INTEL_AUDIO_DEVCTG 0x80862802
8353 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
8354 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
8355 #define G4X_ELDV_DEVCTG (1 << 14)
8356 #define G4X_ELD_ADDR_MASK (0xf << 5)
8357 #define G4X_ELD_ACK (1 << 4)
8358 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
8360 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
8361 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
8362 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
8363 _IBX_HDMIW_HDMIEDID_B)
8364 #define _IBX_AUD_CNTL_ST_A 0xE20B4
8365 #define _IBX_AUD_CNTL_ST_B 0xE21B4
8366 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
8368 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
8369 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
8370 #define IBX_ELD_ACK (1 << 4)
8371 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
8372 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
8373 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
8375 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
8376 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
8377 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
8378 #define _CPT_AUD_CNTL_ST_A 0xE50B4
8379 #define _CPT_AUD_CNTL_ST_B 0xE51B4
8380 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
8381 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
8383 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
8384 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
8385 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
8386 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
8387 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
8388 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
8389 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
8391 /* These are the 4 32-bit write offset registers for each stream
8392 * output buffer. It determines the offset from the
8393 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
8395 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
8397 #define _IBX_AUD_CONFIG_A 0xe2000
8398 #define _IBX_AUD_CONFIG_B 0xe2100
8399 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
8400 #define _CPT_AUD_CONFIG_A 0xe5000
8401 #define _CPT_AUD_CONFIG_B 0xe5100
8402 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
8403 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
8404 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
8405 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
8407 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
8408 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
8409 #define AUD_CONFIG_UPPER_N_SHIFT 20
8410 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
8411 #define AUD_CONFIG_LOWER_N_SHIFT 4
8412 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
8413 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
8414 #define AUD_CONFIG_N(n) \
8415 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
8416 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
8417 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
8418 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
8419 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
8420 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
8421 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
8422 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
8423 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
8424 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
8425 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
8426 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
8427 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
8428 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
8429 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
8432 #define _HSW_AUD_CONFIG_A 0x65000
8433 #define _HSW_AUD_CONFIG_B 0x65100
8434 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
8436 #define _HSW_AUD_MISC_CTRL_A 0x65010
8437 #define _HSW_AUD_MISC_CTRL_B 0x65110
8438 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
8440 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028
8441 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128
8442 #define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
8443 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
8444 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
8445 #define AUD_CONFIG_M_MASK 0xfffff
8447 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
8448 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
8449 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
8451 /* Audio Digital Converter */
8452 #define _HSW_AUD_DIG_CNVT_1 0x65080
8453 #define _HSW_AUD_DIG_CNVT_2 0x65180
8454 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
8455 #define DIP_PORT_SEL_MASK 0x3
8457 #define _HSW_AUD_EDID_DATA_A 0x65050
8458 #define _HSW_AUD_EDID_DATA_B 0x65150
8459 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
8461 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
8462 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
8463 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
8464 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
8465 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
8466 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
8468 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
8469 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
8471 /* HSW Power Wells */
8472 #define _HSW_PWR_WELL_CTL1 0x45400
8473 #define _HSW_PWR_WELL_CTL2 0x45404
8474 #define _HSW_PWR_WELL_CTL3 0x45408
8475 #define _HSW_PWR_WELL_CTL4 0x4540C
8478 * Each power well control register contains up to 16 (request, status) HW
8479 * flag tuples. The register index and HW flag shift is determined by the
8480 * power well ID (see i915_power_well_id). There are 4 possible sources of
8481 * power well requests each source having its own set of control registers:
8482 * BIOS, DRIVER, KVMR, DEBUG.
8484 #define _HSW_PW_REG_IDX(pw) ((pw) >> 4)
8485 #define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2)
8486 /* TODO: Add all PWR_WELL_CTL registers below for new platforms */
8487 #define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8488 _HSW_PWR_WELL_CTL1))
8489 #define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8490 _HSW_PWR_WELL_CTL2))
8491 #define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3)
8492 #define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8493 _HSW_PWR_WELL_CTL4))
8495 #define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1))
8496 #define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw))
8497 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
8498 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
8499 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
8500 #define HSW_PWR_WELL_FORCE_ON (1<<19)
8501 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
8503 /* SKL Fuse Status */
8504 enum skl_power_gate {
8510 #define SKL_FUSE_STATUS _MMIO(0x42000)
8511 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
8512 /* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
8513 #define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
8514 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
8516 #define _CNL_AUX_REG_IDX(pw) ((pw) - 9)
8517 #define _CNL_AUX_ANAOVRD1_B 0x162250
8518 #define _CNL_AUX_ANAOVRD1_C 0x162210
8519 #define _CNL_AUX_ANAOVRD1_D 0x1622D0
8520 #define _CNL_AUX_ANAOVRD1_F 0x162A90
8521 #define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
8522 _CNL_AUX_ANAOVRD1_B, \
8523 _CNL_AUX_ANAOVRD1_C, \
8524 _CNL_AUX_ANAOVRD1_D, \
8525 _CNL_AUX_ANAOVRD1_F))
8526 #define CNL_AUX_ANAOVRD1_ENABLE (1<<16)
8527 #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
8529 /* HDCP Key Registers */
8530 #define HDCP_KEY_CONF _MMIO(0x66c00)
8531 #define HDCP_AKSV_SEND_TRIGGER BIT(31)
8532 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
8533 #define HDCP_KEY_LOAD_TRIGGER BIT(8)
8534 #define HDCP_KEY_STATUS _MMIO(0x66c04)
8535 #define HDCP_FUSE_IN_PROGRESS BIT(7)
8536 #define HDCP_FUSE_ERROR BIT(6)
8537 #define HDCP_FUSE_DONE BIT(5)
8538 #define HDCP_KEY_LOAD_STATUS BIT(1)
8539 #define HDCP_KEY_LOAD_DONE BIT(0)
8540 #define HDCP_AKSV_LO _MMIO(0x66c10)
8541 #define HDCP_AKSV_HI _MMIO(0x66c14)
8543 /* HDCP Repeater Registers */
8544 #define HDCP_REP_CTL _MMIO(0x66d00)
8545 #define HDCP_DDIB_REP_PRESENT BIT(30)
8546 #define HDCP_DDIA_REP_PRESENT BIT(29)
8547 #define HDCP_DDIC_REP_PRESENT BIT(28)
8548 #define HDCP_DDID_REP_PRESENT BIT(27)
8549 #define HDCP_DDIF_REP_PRESENT BIT(26)
8550 #define HDCP_DDIE_REP_PRESENT BIT(25)
8551 #define HDCP_DDIB_SHA1_M0 (1 << 20)
8552 #define HDCP_DDIA_SHA1_M0 (2 << 20)
8553 #define HDCP_DDIC_SHA1_M0 (3 << 20)
8554 #define HDCP_DDID_SHA1_M0 (4 << 20)
8555 #define HDCP_DDIF_SHA1_M0 (5 << 20)
8556 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
8557 #define HDCP_SHA1_BUSY BIT(16)
8558 #define HDCP_SHA1_READY BIT(17)
8559 #define HDCP_SHA1_COMPLETE BIT(18)
8560 #define HDCP_SHA1_V_MATCH BIT(19)
8561 #define HDCP_SHA1_TEXT_32 (1 << 1)
8562 #define HDCP_SHA1_COMPLETE_HASH (2 << 1)
8563 #define HDCP_SHA1_TEXT_24 (4 << 1)
8564 #define HDCP_SHA1_TEXT_16 (5 << 1)
8565 #define HDCP_SHA1_TEXT_8 (6 << 1)
8566 #define HDCP_SHA1_TEXT_0 (7 << 1)
8567 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
8568 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
8569 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
8570 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
8571 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
8572 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + h * 4))
8573 #define HDCP_SHA_TEXT _MMIO(0x66d18)
8575 /* HDCP Auth Registers */
8576 #define _PORTA_HDCP_AUTHENC 0x66800
8577 #define _PORTB_HDCP_AUTHENC 0x66500
8578 #define _PORTC_HDCP_AUTHENC 0x66600
8579 #define _PORTD_HDCP_AUTHENC 0x66700
8580 #define _PORTE_HDCP_AUTHENC 0x66A00
8581 #define _PORTF_HDCP_AUTHENC 0x66900
8582 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
8583 _PORTA_HDCP_AUTHENC, \
8584 _PORTB_HDCP_AUTHENC, \
8585 _PORTC_HDCP_AUTHENC, \
8586 _PORTD_HDCP_AUTHENC, \
8587 _PORTE_HDCP_AUTHENC, \
8588 _PORTF_HDCP_AUTHENC) + x)
8589 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
8590 #define HDCP_CONF_CAPTURE_AN BIT(0)
8591 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
8592 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
8593 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
8594 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
8595 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
8596 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
8597 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
8598 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
8599 #define HDCP_STATUS_STREAM_A_ENC BIT(31)
8600 #define HDCP_STATUS_STREAM_B_ENC BIT(30)
8601 #define HDCP_STATUS_STREAM_C_ENC BIT(29)
8602 #define HDCP_STATUS_STREAM_D_ENC BIT(28)
8603 #define HDCP_STATUS_AUTH BIT(21)
8604 #define HDCP_STATUS_ENC BIT(20)
8605 #define HDCP_STATUS_RI_MATCH BIT(19)
8606 #define HDCP_STATUS_R0_READY BIT(18)
8607 #define HDCP_STATUS_AN_READY BIT(17)
8608 #define HDCP_STATUS_CIPHER BIT(16)
8609 #define HDCP_STATUS_FRAME_CNT(x) ((x >> 8) & 0xff)
8611 /* Per-pipe DDI Function Control */
8612 #define _TRANS_DDI_FUNC_CTL_A 0x60400
8613 #define _TRANS_DDI_FUNC_CTL_B 0x61400
8614 #define _TRANS_DDI_FUNC_CTL_C 0x62400
8615 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
8616 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
8618 #define TRANS_DDI_FUNC_ENABLE (1<<31)
8619 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
8620 #define TRANS_DDI_PORT_MASK (7<<28)
8621 #define TRANS_DDI_PORT_SHIFT 28
8622 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
8623 #define TRANS_DDI_PORT_NONE (0<<28)
8624 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
8625 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
8626 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
8627 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
8628 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
8629 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
8630 #define TRANS_DDI_BPC_MASK (7<<20)
8631 #define TRANS_DDI_BPC_8 (0<<20)
8632 #define TRANS_DDI_BPC_10 (1<<20)
8633 #define TRANS_DDI_BPC_6 (2<<20)
8634 #define TRANS_DDI_BPC_12 (3<<20)
8635 #define TRANS_DDI_PVSYNC (1<<17)
8636 #define TRANS_DDI_PHSYNC (1<<16)
8637 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
8638 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
8639 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
8640 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
8641 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
8642 #define TRANS_DDI_HDCP_SIGNALLING (1<<9)
8643 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
8644 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7)
8645 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6)
8646 #define TRANS_DDI_BFI_ENABLE (1<<4)
8647 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4)
8648 #define TRANS_DDI_HDMI_SCRAMBLING (1<<0)
8649 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
8650 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
8651 | TRANS_DDI_HDMI_SCRAMBLING)
8653 /* DisplayPort Transport Control */
8654 #define _DP_TP_CTL_A 0x64040
8655 #define _DP_TP_CTL_B 0x64140
8656 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
8657 #define DP_TP_CTL_ENABLE (1<<31)
8658 #define DP_TP_CTL_MODE_SST (0<<27)
8659 #define DP_TP_CTL_MODE_MST (1<<27)
8660 #define DP_TP_CTL_FORCE_ACT (1<<25)
8661 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
8662 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
8663 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
8664 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
8665 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
8666 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
8667 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
8668 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
8669 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
8671 /* DisplayPort Transport Status */
8672 #define _DP_TP_STATUS_A 0x64044
8673 #define _DP_TP_STATUS_B 0x64144
8674 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
8675 #define DP_TP_STATUS_IDLE_DONE (1<<25)
8676 #define DP_TP_STATUS_ACT_SENT (1<<24)
8677 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
8678 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
8679 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
8680 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
8681 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
8683 /* DDI Buffer Control */
8684 #define _DDI_BUF_CTL_A 0x64000
8685 #define _DDI_BUF_CTL_B 0x64100
8686 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
8687 #define DDI_BUF_CTL_ENABLE (1<<31)
8688 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
8689 #define DDI_BUF_EMP_MASK (0xf<<24)
8690 #define DDI_BUF_PORT_REVERSAL (1<<16)
8691 #define DDI_BUF_IS_IDLE (1<<7)
8692 #define DDI_A_4_LANES (1<<4)
8693 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
8694 #define DDI_PORT_WIDTH_MASK (7 << 1)
8695 #define DDI_PORT_WIDTH_SHIFT 1
8696 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
8698 /* DDI Buffer Translations */
8699 #define _DDI_BUF_TRANS_A 0x64E00
8700 #define _DDI_BUF_TRANS_B 0x64E60
8701 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
8702 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
8703 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
8705 /* Sideband Interface (SBI) is programmed indirectly, via
8706 * SBI_ADDR, which contains the register offset; and SBI_DATA,
8707 * which contains the payload */
8708 #define SBI_ADDR _MMIO(0xC6000)
8709 #define SBI_DATA _MMIO(0xC6004)
8710 #define SBI_CTL_STAT _MMIO(0xC6008)
8711 #define SBI_CTL_DEST_ICLK (0x0<<16)
8712 #define SBI_CTL_DEST_MPHY (0x1<<16)
8713 #define SBI_CTL_OP_IORD (0x2<<8)
8714 #define SBI_CTL_OP_IOWR (0x3<<8)
8715 #define SBI_CTL_OP_CRRD (0x6<<8)
8716 #define SBI_CTL_OP_CRWR (0x7<<8)
8717 #define SBI_RESPONSE_FAIL (0x1<<1)
8718 #define SBI_RESPONSE_SUCCESS (0x0<<1)
8719 #define SBI_BUSY (0x1<<0)
8720 #define SBI_READY (0x0<<0)
8723 #define SBI_SSCDIVINTPHASE 0x0200
8724 #define SBI_SSCDIVINTPHASE6 0x0600
8725 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
8726 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1)
8727 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
8728 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
8729 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8)
8730 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
8731 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
8732 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
8733 #define SBI_SSCDITHPHASE 0x0204
8734 #define SBI_SSCCTL 0x020c
8735 #define SBI_SSCCTL6 0x060C
8736 #define SBI_SSCCTL_PATHALT (1<<3)
8737 #define SBI_SSCCTL_DISABLE (1<<0)
8738 #define SBI_SSCAUXDIV6 0x0610
8739 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
8740 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4)
8741 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
8742 #define SBI_DBUFF0 0x2a00
8743 #define SBI_GEN0 0x1f00
8744 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
8746 /* LPT PIXCLK_GATE */
8747 #define PIXCLK_GATE _MMIO(0xC6020)
8748 #define PIXCLK_GATE_UNGATE (1<<0)
8749 #define PIXCLK_GATE_GATE (0<<0)
8752 #define SPLL_CTL _MMIO(0x46020)
8753 #define SPLL_PLL_ENABLE (1<<31)
8754 #define SPLL_PLL_SSC (1<<28)
8755 #define SPLL_PLL_NON_SSC (2<<28)
8756 #define SPLL_PLL_LCPLL (3<<28)
8757 #define SPLL_PLL_REF_MASK (3<<28)
8758 #define SPLL_PLL_FREQ_810MHz (0<<26)
8759 #define SPLL_PLL_FREQ_1350MHz (1<<26)
8760 #define SPLL_PLL_FREQ_2700MHz (2<<26)
8761 #define SPLL_PLL_FREQ_MASK (3<<26)
8764 #define _WRPLL_CTL1 0x46040
8765 #define _WRPLL_CTL2 0x46060
8766 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
8767 #define WRPLL_PLL_ENABLE (1<<31)
8768 #define WRPLL_PLL_SSC (1<<28)
8769 #define WRPLL_PLL_NON_SSC (2<<28)
8770 #define WRPLL_PLL_LCPLL (3<<28)
8771 #define WRPLL_PLL_REF_MASK (3<<28)
8772 /* WRPLL divider programming */
8773 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
8774 #define WRPLL_DIVIDER_REF_MASK (0xff)
8775 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
8776 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
8777 #define WRPLL_DIVIDER_POST_SHIFT 8
8778 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
8779 #define WRPLL_DIVIDER_FB_SHIFT 16
8780 #define WRPLL_DIVIDER_FB_MASK (0xff<<16)
8782 /* Port clock selection */
8783 #define _PORT_CLK_SEL_A 0x46100
8784 #define _PORT_CLK_SEL_B 0x46104
8785 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
8786 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
8787 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
8788 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
8789 #define PORT_CLK_SEL_SPLL (3<<29)
8790 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
8791 #define PORT_CLK_SEL_WRPLL1 (4<<29)
8792 #define PORT_CLK_SEL_WRPLL2 (5<<29)
8793 #define PORT_CLK_SEL_NONE (7<<29)
8794 #define PORT_CLK_SEL_MASK (7<<29)
8796 /* Transcoder clock selection */
8797 #define _TRANS_CLK_SEL_A 0x46140
8798 #define _TRANS_CLK_SEL_B 0x46144
8799 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
8800 /* For each transcoder, we need to select the corresponding port clock */
8801 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
8802 #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
8804 #define CDCLK_FREQ _MMIO(0x46200)
8806 #define _TRANSA_MSA_MISC 0x60410
8807 #define _TRANSB_MSA_MISC 0x61410
8808 #define _TRANSC_MSA_MISC 0x62410
8809 #define _TRANS_EDP_MSA_MISC 0x6f410
8810 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
8812 #define TRANS_MSA_SYNC_CLK (1<<0)
8813 #define TRANS_MSA_6_BPC (0<<5)
8814 #define TRANS_MSA_8_BPC (1<<5)
8815 #define TRANS_MSA_10_BPC (2<<5)
8816 #define TRANS_MSA_12_BPC (3<<5)
8817 #define TRANS_MSA_16_BPC (4<<5)
8820 #define LCPLL_CTL _MMIO(0x130040)
8821 #define LCPLL_PLL_DISABLE (1<<31)
8822 #define LCPLL_PLL_LOCK (1<<30)
8823 #define LCPLL_CLK_FREQ_MASK (3<<26)
8824 #define LCPLL_CLK_FREQ_450 (0<<26)
8825 #define LCPLL_CLK_FREQ_54O_BDW (1<<26)
8826 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
8827 #define LCPLL_CLK_FREQ_675_BDW (3<<26)
8828 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
8829 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
8830 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
8831 #define LCPLL_POWER_DOWN_ALLOW (1<<22)
8832 #define LCPLL_CD_SOURCE_FCLK (1<<21)
8833 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
8840 #define CDCLK_CTL _MMIO(0x46000)
8841 #define CDCLK_FREQ_SEL_MASK (3 << 26)
8842 #define CDCLK_FREQ_450_432 (0 << 26)
8843 #define CDCLK_FREQ_540 (1 << 26)
8844 #define CDCLK_FREQ_337_308 (2 << 26)
8845 #define CDCLK_FREQ_675_617 (3 << 26)
8846 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
8847 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
8848 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
8849 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
8850 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
8851 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
8852 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
8853 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
8854 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
8855 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
8856 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
8859 #define LCPLL1_CTL _MMIO(0x46010)
8860 #define LCPLL2_CTL _MMIO(0x46014)
8861 #define LCPLL_PLL_ENABLE (1<<31)
8864 #define DPLL_CTRL1 _MMIO(0x6C058)
8865 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
8866 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
8867 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
8868 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
8869 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
8870 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
8871 #define DPLL_CTRL1_LINK_RATE_2700 0
8872 #define DPLL_CTRL1_LINK_RATE_1350 1
8873 #define DPLL_CTRL1_LINK_RATE_810 2
8874 #define DPLL_CTRL1_LINK_RATE_1620 3
8875 #define DPLL_CTRL1_LINK_RATE_1080 4
8876 #define DPLL_CTRL1_LINK_RATE_2160 5
8879 #define DPLL_CTRL2 _MMIO(0x6C05C)
8880 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
8881 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
8882 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
8883 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
8884 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
8887 #define DPLL_STATUS _MMIO(0x6C060)
8888 #define DPLL_LOCK(id) (1<<((id)*8))
8891 #define _DPLL1_CFGCR1 0x6C040
8892 #define _DPLL2_CFGCR1 0x6C048
8893 #define _DPLL3_CFGCR1 0x6C050
8894 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
8895 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
8896 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
8897 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
8899 #define _DPLL1_CFGCR2 0x6C044
8900 #define _DPLL2_CFGCR2 0x6C04C
8901 #define _DPLL3_CFGCR2 0x6C054
8902 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
8903 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
8904 #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
8905 #define DPLL_CFGCR2_KDIV_MASK (3<<5)
8906 #define DPLL_CFGCR2_KDIV(x) ((x)<<5)
8907 #define DPLL_CFGCR2_KDIV_5 (0<<5)
8908 #define DPLL_CFGCR2_KDIV_2 (1<<5)
8909 #define DPLL_CFGCR2_KDIV_3 (2<<5)
8910 #define DPLL_CFGCR2_KDIV_1 (3<<5)
8911 #define DPLL_CFGCR2_PDIV_MASK (7<<2)
8912 #define DPLL_CFGCR2_PDIV(x) ((x)<<2)
8913 #define DPLL_CFGCR2_PDIV_1 (0<<2)
8914 #define DPLL_CFGCR2_PDIV_2 (1<<2)
8915 #define DPLL_CFGCR2_PDIV_3 (2<<2)
8916 #define DPLL_CFGCR2_PDIV_7 (4<<2)
8917 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
8919 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
8920 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
8925 #define DPCLKA_CFGCR0 _MMIO(0x6C200)
8926 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
8928 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
8930 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
8931 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
8934 #define DPLL0_ENABLE 0x46010
8935 #define DPLL1_ENABLE 0x46014
8936 #define PLL_ENABLE (1 << 31)
8937 #define PLL_LOCK (1 << 30)
8938 #define PLL_POWER_ENABLE (1 << 27)
8939 #define PLL_POWER_STATE (1 << 26)
8940 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
8942 #define _CNL_DPLL0_CFGCR0 0x6C000
8943 #define _CNL_DPLL1_CFGCR0 0x6C080
8944 #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
8945 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
8946 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
8947 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
8948 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
8949 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
8950 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
8951 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
8952 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
8953 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
8954 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
8955 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
8956 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
8957 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
8958 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
8959 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
8961 #define _CNL_DPLL0_CFGCR1 0x6C004
8962 #define _CNL_DPLL1_CFGCR1 0x6C084
8963 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
8964 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
8965 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
8966 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
8967 #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
8968 #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
8969 #define DPLL_CFGCR1_KDIV_1 (1 << 6)
8970 #define DPLL_CFGCR1_KDIV_2 (2 << 6)
8971 #define DPLL_CFGCR1_KDIV_4 (4 << 6)
8972 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
8973 #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
8974 #define DPLL_CFGCR1_PDIV_2 (1 << 2)
8975 #define DPLL_CFGCR1_PDIV_3 (2 << 2)
8976 #define DPLL_CFGCR1_PDIV_5 (4 << 2)
8977 #define DPLL_CFGCR1_PDIV_7 (8 << 2)
8978 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
8979 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
8981 /* BXT display engine PLL */
8982 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
8983 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
8984 #define BXT_DE_PLL_RATIO_MASK 0xff
8986 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
8987 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
8988 #define BXT_DE_PLL_LOCK (1 << 30)
8989 #define CNL_CDCLK_PLL_RATIO(x) (x)
8990 #define CNL_CDCLK_PLL_RATIO_MASK 0xff
8993 #define DC_STATE_EN _MMIO(0x45504)
8994 #define DC_STATE_DISABLE 0
8995 #define DC_STATE_EN_UPTO_DC5 (1<<0)
8996 #define DC_STATE_EN_DC9 (1<<3)
8997 #define DC_STATE_EN_UPTO_DC6 (2<<0)
8998 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
9000 #define DC_STATE_DEBUG _MMIO(0x45520)
9001 #define DC_STATE_DEBUG_MASK_CORES (1<<0)
9002 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
9004 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
9005 * since on HSW we can't write to it using I915_WRITE. */
9006 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
9007 #define D_COMP_BDW _MMIO(0x138144)
9008 #define D_COMP_RCOMP_IN_PROGRESS (1<<9)
9009 #define D_COMP_COMP_FORCE (1<<8)
9010 #define D_COMP_COMP_DISABLE (1<<0)
9012 /* Pipe WM_LINETIME - watermark line time */
9013 #define _PIPE_WM_LINETIME_A 0x45270
9014 #define _PIPE_WM_LINETIME_B 0x45274
9015 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
9016 #define PIPE_WM_LINETIME_MASK (0x1ff)
9017 #define PIPE_WM_LINETIME_TIME(x) ((x))
9018 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
9019 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
9022 #define SFUSE_STRAP _MMIO(0xc2014)
9023 #define SFUSE_STRAP_FUSE_LOCK (1<<13)
9024 #define SFUSE_STRAP_RAW_FREQUENCY (1<<8)
9025 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
9026 #define SFUSE_STRAP_CRT_DISABLED (1<<6)
9027 #define SFUSE_STRAP_DDIF_DETECTED (1<<3)
9028 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
9029 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
9030 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
9032 #define WM_MISC _MMIO(0x45260)
9033 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
9035 #define WM_DBG _MMIO(0x45280)
9036 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
9037 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
9038 #define WM_DBG_DISALLOW_SPRITE (1<<2)
9041 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
9042 #define _PIPE_A_CSC_COEFF_BY 0x49014
9043 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
9044 #define _PIPE_A_CSC_COEFF_BU 0x4901c
9045 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
9046 #define _PIPE_A_CSC_COEFF_BV 0x49024
9047 #define _PIPE_A_CSC_MODE 0x49028
9048 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
9049 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
9050 #define CSC_MODE_YUV_TO_RGB (1 << 0)
9051 #define _PIPE_A_CSC_PREOFF_HI 0x49030
9052 #define _PIPE_A_CSC_PREOFF_ME 0x49034
9053 #define _PIPE_A_CSC_PREOFF_LO 0x49038
9054 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
9055 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
9056 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
9058 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
9059 #define _PIPE_B_CSC_COEFF_BY 0x49114
9060 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
9061 #define _PIPE_B_CSC_COEFF_BU 0x4911c
9062 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
9063 #define _PIPE_B_CSC_COEFF_BV 0x49124
9064 #define _PIPE_B_CSC_MODE 0x49128
9065 #define _PIPE_B_CSC_PREOFF_HI 0x49130
9066 #define _PIPE_B_CSC_PREOFF_ME 0x49134
9067 #define _PIPE_B_CSC_PREOFF_LO 0x49138
9068 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
9069 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
9070 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
9072 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
9073 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
9074 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
9075 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
9076 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
9077 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
9078 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
9079 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
9080 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
9081 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
9082 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
9083 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
9084 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
9086 /* pipe degamma/gamma LUTs on IVB+ */
9087 #define _PAL_PREC_INDEX_A 0x4A400
9088 #define _PAL_PREC_INDEX_B 0x4AC00
9089 #define _PAL_PREC_INDEX_C 0x4B400
9090 #define PAL_PREC_10_12_BIT (0 << 31)
9091 #define PAL_PREC_SPLIT_MODE (1 << 31)
9092 #define PAL_PREC_AUTO_INCREMENT (1 << 15)
9093 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
9094 #define _PAL_PREC_DATA_A 0x4A404
9095 #define _PAL_PREC_DATA_B 0x4AC04
9096 #define _PAL_PREC_DATA_C 0x4B404
9097 #define _PAL_PREC_GC_MAX_A 0x4A410
9098 #define _PAL_PREC_GC_MAX_B 0x4AC10
9099 #define _PAL_PREC_GC_MAX_C 0x4B410
9100 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
9101 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
9102 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
9103 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
9104 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
9105 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
9107 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
9108 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
9109 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
9110 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
9112 #define _PRE_CSC_GAMC_INDEX_A 0x4A484
9113 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
9114 #define _PRE_CSC_GAMC_INDEX_C 0x4B484
9115 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
9116 #define _PRE_CSC_GAMC_DATA_A 0x4A488
9117 #define _PRE_CSC_GAMC_DATA_B 0x4AC88
9118 #define _PRE_CSC_GAMC_DATA_C 0x4B488
9120 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
9121 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
9123 /* pipe CSC & degamma/gamma LUTs on CHV */
9124 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
9125 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
9126 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
9127 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
9128 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
9129 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
9130 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
9131 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
9132 #define CGM_PIPE_MODE_GAMMA (1 << 2)
9133 #define CGM_PIPE_MODE_CSC (1 << 1)
9134 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
9136 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
9137 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
9138 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
9139 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
9140 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
9141 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
9142 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
9143 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
9145 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
9146 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
9147 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
9148 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
9149 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
9150 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
9151 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
9152 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
9154 /* MIPI DSI registers */
9156 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
9157 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
9159 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
9160 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
9161 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
9162 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
9164 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
9165 #define GEN4_TIMESTAMP _MMIO(0x2358)
9166 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
9167 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
9169 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
9170 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
9171 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
9172 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
9173 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
9175 #define _PIPE_FRMTMSTMP_A 0x70048
9176 #define PIPE_FRMTMSTMP(pipe) \
9177 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
9179 /* BXT MIPI clock controls */
9180 #define BXT_MAX_VAR_OUTPUT_KHZ 39500
9182 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
9183 #define BXT_MIPI1_DIV_SHIFT 26
9184 #define BXT_MIPI2_DIV_SHIFT 10
9185 #define BXT_MIPI_DIV_SHIFT(port) \
9186 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
9187 BXT_MIPI2_DIV_SHIFT)
9189 /* TX control divider to select actual TX clock output from (8x/var) */
9190 #define BXT_MIPI1_TX_ESCLK_SHIFT 26
9191 #define BXT_MIPI2_TX_ESCLK_SHIFT 10
9192 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
9193 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
9194 BXT_MIPI2_TX_ESCLK_SHIFT)
9195 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
9196 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
9197 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
9198 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
9199 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
9200 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
9201 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
9202 /* RX upper control divider to select actual RX clock output from 8x */
9203 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
9204 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
9205 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
9206 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
9207 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
9208 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
9209 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
9210 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
9211 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
9212 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
9213 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
9214 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
9215 /* 8/3X divider to select the actual 8/3X clock output from 8x */
9216 #define BXT_MIPI1_8X_BY3_SHIFT 19
9217 #define BXT_MIPI2_8X_BY3_SHIFT 3
9218 #define BXT_MIPI_8X_BY3_SHIFT(port) \
9219 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
9220 BXT_MIPI2_8X_BY3_SHIFT)
9221 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
9222 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
9223 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
9224 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
9225 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
9226 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
9227 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
9228 /* RX lower control divider to select actual RX clock output from 8x */
9229 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
9230 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
9231 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
9232 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
9233 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
9234 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
9235 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
9236 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
9237 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
9238 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
9239 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
9240 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
9242 #define RX_DIVIDER_BIT_1_2 0x3
9243 #define RX_DIVIDER_BIT_3_4 0xC
9245 /* BXT MIPI mode configure */
9246 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
9247 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
9248 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
9249 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
9251 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
9252 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
9253 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
9254 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
9256 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
9257 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
9258 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
9259 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
9261 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
9262 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
9263 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9264 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9265 #define BXT_DSIC_16X_BY1 (0 << 10)
9266 #define BXT_DSIC_16X_BY2 (1 << 10)
9267 #define BXT_DSIC_16X_BY3 (2 << 10)
9268 #define BXT_DSIC_16X_BY4 (3 << 10)
9269 #define BXT_DSIC_16X_MASK (3 << 10)
9270 #define BXT_DSIA_16X_BY1 (0 << 8)
9271 #define BXT_DSIA_16X_BY2 (1 << 8)
9272 #define BXT_DSIA_16X_BY3 (2 << 8)
9273 #define BXT_DSIA_16X_BY4 (3 << 8)
9274 #define BXT_DSIA_16X_MASK (3 << 8)
9275 #define BXT_DSI_FREQ_SEL_SHIFT 8
9276 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
9278 #define BXT_DSI_PLL_RATIO_MAX 0x7D
9279 #define BXT_DSI_PLL_RATIO_MIN 0x22
9280 #define GLK_DSI_PLL_RATIO_MAX 0x6F
9281 #define GLK_DSI_PLL_RATIO_MIN 0x22
9282 #define BXT_DSI_PLL_RATIO_MASK 0xFF
9283 #define BXT_REF_CLOCK_KHZ 19200
9285 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
9286 #define BXT_DSI_PLL_DO_ENABLE (1 << 31)
9287 #define BXT_DSI_PLL_LOCKED (1 << 30)
9289 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
9290 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
9291 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
9293 /* BXT port control */
9294 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0
9295 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
9296 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
9298 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
9299 #define STAP_SELECT (1 << 0)
9301 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
9302 #define HS_IO_CTRL_SELECT (1 << 0)
9304 #define DPI_ENABLE (1 << 31) /* A + C */
9305 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
9306 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
9307 #define DUAL_LINK_MODE_SHIFT 26
9308 #define DUAL_LINK_MODE_MASK (1 << 26)
9309 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
9310 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
9311 #define DITHERING_ENABLE (1 << 25) /* A + C */
9312 #define FLOPPED_HSTX (1 << 23)
9313 #define DE_INVERT (1 << 19) /* XXX */
9314 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
9315 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
9316 #define AFE_LATCHOUT (1 << 17)
9317 #define LP_OUTPUT_HOLD (1 << 16)
9318 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
9319 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
9320 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
9321 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
9323 #define CSB_MASK (3 << 9)
9324 #define CSB_20MHZ (0 << 9)
9325 #define CSB_10MHZ (1 << 9)
9326 #define CSB_40MHZ (2 << 9)
9327 #define BANDGAP_MASK (1 << 8)
9328 #define BANDGAP_PNW_CIRCUIT (0 << 8)
9329 #define BANDGAP_LNC_CIRCUIT (1 << 8)
9330 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
9331 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
9332 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
9333 #define TEARING_EFFECT_SHIFT 2 /* A + C */
9334 #define TEARING_EFFECT_MASK (3 << 2)
9335 #define TEARING_EFFECT_OFF (0 << 2)
9336 #define TEARING_EFFECT_DSI (1 << 2)
9337 #define TEARING_EFFECT_GPIO (2 << 2)
9338 #define LANE_CONFIGURATION_SHIFT 0
9339 #define LANE_CONFIGURATION_MASK (3 << 0)
9340 #define LANE_CONFIGURATION_4LANE (0 << 0)
9341 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
9342 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
9344 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
9345 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
9346 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
9347 #define TEARING_EFFECT_DELAY_SHIFT 0
9348 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
9350 /* XXX: all bits reserved */
9351 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
9353 /* MIPI DSI Controller and D-PHY registers */
9355 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
9356 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
9357 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
9358 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
9359 #define ULPS_STATE_MASK (3 << 1)
9360 #define ULPS_STATE_ENTER (2 << 1)
9361 #define ULPS_STATE_EXIT (1 << 1)
9362 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
9363 #define DEVICE_READY (1 << 0)
9365 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
9366 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
9367 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
9368 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
9369 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
9370 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
9371 #define TEARING_EFFECT (1 << 31)
9372 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
9373 #define GEN_READ_DATA_AVAIL (1 << 29)
9374 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
9375 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
9376 #define RX_PROT_VIOLATION (1 << 26)
9377 #define RX_INVALID_TX_LENGTH (1 << 25)
9378 #define ACK_WITH_NO_ERROR (1 << 24)
9379 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
9380 #define LP_RX_TIMEOUT (1 << 22)
9381 #define HS_TX_TIMEOUT (1 << 21)
9382 #define DPI_FIFO_UNDERRUN (1 << 20)
9383 #define LOW_CONTENTION (1 << 19)
9384 #define HIGH_CONTENTION (1 << 18)
9385 #define TXDSI_VC_ID_INVALID (1 << 17)
9386 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
9387 #define TXCHECKSUM_ERROR (1 << 15)
9388 #define TXECC_MULTIBIT_ERROR (1 << 14)
9389 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
9390 #define TXFALSE_CONTROL_ERROR (1 << 12)
9391 #define RXDSI_VC_ID_INVALID (1 << 11)
9392 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
9393 #define RXCHECKSUM_ERROR (1 << 9)
9394 #define RXECC_MULTIBIT_ERROR (1 << 8)
9395 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
9396 #define RXFALSE_CONTROL_ERROR (1 << 6)
9397 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
9398 #define RX_LP_TX_SYNC_ERROR (1 << 4)
9399 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
9400 #define RXEOT_SYNC_ERROR (1 << 2)
9401 #define RXSOT_SYNC_ERROR (1 << 1)
9402 #define RXSOT_ERROR (1 << 0)
9404 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
9405 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
9406 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
9407 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
9408 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
9409 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
9410 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
9411 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
9412 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
9413 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
9414 #define VID_MODE_FORMAT_MASK (0xf << 7)
9415 #define VID_MODE_NOT_SUPPORTED (0 << 7)
9416 #define VID_MODE_FORMAT_RGB565 (1 << 7)
9417 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
9418 #define VID_MODE_FORMAT_RGB666 (3 << 7)
9419 #define VID_MODE_FORMAT_RGB888 (4 << 7)
9420 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
9421 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
9422 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
9423 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
9424 #define DATA_LANES_PRG_REG_SHIFT 0
9425 #define DATA_LANES_PRG_REG_MASK (7 << 0)
9427 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
9428 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
9429 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
9430 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
9432 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
9433 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
9434 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
9435 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
9437 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
9438 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
9439 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
9440 #define TURN_AROUND_TIMEOUT_MASK 0x3f
9442 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
9443 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
9444 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
9445 #define DEVICE_RESET_TIMER_MASK 0xffff
9447 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
9448 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
9449 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
9450 #define VERTICAL_ADDRESS_SHIFT 16
9451 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
9452 #define HORIZONTAL_ADDRESS_SHIFT 0
9453 #define HORIZONTAL_ADDRESS_MASK 0xffff
9455 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
9456 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
9457 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
9458 #define DBI_FIFO_EMPTY_HALF (0 << 0)
9459 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
9460 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
9462 /* regs below are bits 15:0 */
9463 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
9464 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
9465 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
9467 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
9468 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
9469 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
9471 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
9472 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
9473 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
9475 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
9476 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
9477 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
9479 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
9480 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
9481 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
9483 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
9484 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
9485 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
9487 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
9488 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
9489 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
9491 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
9492 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
9493 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
9495 /* regs above are bits 15:0 */
9497 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
9498 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
9499 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
9500 #define DPI_LP_MODE (1 << 6)
9501 #define BACKLIGHT_OFF (1 << 5)
9502 #define BACKLIGHT_ON (1 << 4)
9503 #define COLOR_MODE_OFF (1 << 3)
9504 #define COLOR_MODE_ON (1 << 2)
9505 #define TURN_ON (1 << 1)
9506 #define SHUTDOWN (1 << 0)
9508 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
9509 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
9510 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
9511 #define COMMAND_BYTE_SHIFT 0
9512 #define COMMAND_BYTE_MASK (0x3f << 0)
9514 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
9515 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
9516 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
9517 #define MASTER_INIT_TIMER_SHIFT 0
9518 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
9520 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
9521 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
9522 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
9523 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
9524 #define MAX_RETURN_PKT_SIZE_SHIFT 0
9525 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
9527 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
9528 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
9529 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
9530 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
9531 #define DISABLE_VIDEO_BTA (1 << 3)
9532 #define IP_TG_CONFIG (1 << 2)
9533 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
9534 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
9535 #define VIDEO_MODE_BURST (3 << 0)
9537 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
9538 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
9539 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
9540 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
9541 #define BXT_DPHY_DEFEATURE_EN (1 << 8)
9542 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
9543 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
9544 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
9545 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
9546 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
9547 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
9548 #define CLOCKSTOP (1 << 1)
9549 #define EOT_DISABLE (1 << 0)
9551 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
9552 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
9553 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
9554 #define LP_BYTECLK_SHIFT 0
9555 #define LP_BYTECLK_MASK (0xffff << 0)
9557 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
9558 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
9559 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
9561 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
9562 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
9563 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
9566 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
9567 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
9568 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
9571 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
9572 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
9573 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
9575 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
9576 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
9577 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
9578 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
9579 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
9580 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
9581 #define LONG_PACKET_WORD_COUNT_SHIFT 8
9582 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
9583 #define SHORT_PACKET_PARAM_SHIFT 8
9584 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
9585 #define VIRTUAL_CHANNEL_SHIFT 6
9586 #define VIRTUAL_CHANNEL_MASK (3 << 6)
9587 #define DATA_TYPE_SHIFT 0
9588 #define DATA_TYPE_MASK (0x3f << 0)
9589 /* data type values, see include/video/mipi_display.h */
9591 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
9592 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
9593 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
9594 #define DPI_FIFO_EMPTY (1 << 28)
9595 #define DBI_FIFO_EMPTY (1 << 27)
9596 #define LP_CTRL_FIFO_EMPTY (1 << 26)
9597 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
9598 #define LP_CTRL_FIFO_FULL (1 << 24)
9599 #define HS_CTRL_FIFO_EMPTY (1 << 18)
9600 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
9601 #define HS_CTRL_FIFO_FULL (1 << 16)
9602 #define LP_DATA_FIFO_EMPTY (1 << 10)
9603 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
9604 #define LP_DATA_FIFO_FULL (1 << 8)
9605 #define HS_DATA_FIFO_EMPTY (1 << 2)
9606 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
9607 #define HS_DATA_FIFO_FULL (1 << 0)
9609 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
9610 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
9611 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
9612 #define DBI_HS_LP_MODE_MASK (1 << 0)
9613 #define DBI_LP_MODE (1 << 0)
9614 #define DBI_HS_MODE (0 << 0)
9616 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
9617 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
9618 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
9619 #define EXIT_ZERO_COUNT_SHIFT 24
9620 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
9621 #define TRAIL_COUNT_SHIFT 16
9622 #define TRAIL_COUNT_MASK (0x1f << 16)
9623 #define CLK_ZERO_COUNT_SHIFT 8
9624 #define CLK_ZERO_COUNT_MASK (0xff << 8)
9625 #define PREPARE_COUNT_SHIFT 0
9626 #define PREPARE_COUNT_MASK (0x3f << 0)
9629 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
9630 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
9631 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
9633 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
9634 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
9635 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
9636 #define LP_HS_SSW_CNT_SHIFT 16
9637 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
9638 #define HS_LP_PWR_SW_CNT_SHIFT 0
9639 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
9641 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
9642 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
9643 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
9644 #define STOP_STATE_STALL_COUNTER_SHIFT 0
9645 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
9647 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
9648 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
9649 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
9650 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
9651 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
9652 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
9653 #define RX_CONTENTION_DETECTED (1 << 0)
9655 /* XXX: only pipe A ?!? */
9656 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
9657 #define DBI_TYPEC_ENABLE (1 << 31)
9658 #define DBI_TYPEC_WIP (1 << 30)
9659 #define DBI_TYPEC_OPTION_SHIFT 28
9660 #define DBI_TYPEC_OPTION_MASK (3 << 28)
9661 #define DBI_TYPEC_FREQ_SHIFT 24
9662 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
9663 #define DBI_TYPEC_OVERRIDE (1 << 8)
9664 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
9665 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
9668 /* MIPI adapter registers */
9670 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
9671 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
9672 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
9673 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
9674 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
9675 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
9676 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
9677 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
9678 #define READ_REQUEST_PRIORITY_SHIFT 3
9679 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
9680 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
9681 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
9682 #define RGB_FLIP_TO_BGR (1 << 2)
9684 #define BXT_PIPE_SELECT_SHIFT 7
9685 #define BXT_PIPE_SELECT_MASK (7 << 7)
9686 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
9687 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
9688 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
9689 #define GLK_MIPIIO_RESET_RELEASED (1 << 28)
9690 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
9691 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
9692 #define GLK_LP_WAKE (1 << 22)
9693 #define GLK_LP11_LOW_PWR_MODE (1 << 21)
9694 #define GLK_LP00_LOW_PWR_MODE (1 << 20)
9695 #define GLK_FIREWALL_ENABLE (1 << 16)
9696 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
9697 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
9698 #define BXT_DSC_ENABLE (1 << 3)
9699 #define BXT_RGB_FLIP (1 << 2)
9700 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
9701 #define GLK_MIPIIO_ENABLE (1 << 0)
9703 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
9704 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
9705 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
9706 #define DATA_MEM_ADDRESS_SHIFT 5
9707 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
9708 #define DATA_VALID (1 << 0)
9710 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
9711 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
9712 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
9713 #define DATA_LENGTH_SHIFT 0
9714 #define DATA_LENGTH_MASK (0xfffff << 0)
9716 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
9717 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
9718 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
9719 #define COMMAND_MEM_ADDRESS_SHIFT 5
9720 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
9721 #define AUTO_PWG_ENABLE (1 << 2)
9722 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
9723 #define COMMAND_VALID (1 << 0)
9725 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
9726 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
9727 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
9728 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
9729 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
9731 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
9732 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
9733 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
9735 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
9736 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
9737 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
9738 #define READ_DATA_VALID(n) (1 << (n))
9740 /* For UMS only (deprecated): */
9741 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
9742 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
9744 /* MOCS (Memory Object Control State) registers */
9745 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
9747 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
9748 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
9749 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
9750 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
9751 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
9754 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
9755 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
9756 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
9757 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
9758 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
9760 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
9761 #define MMCD_PCLA (1 << 31)
9762 #define MMCD_HOTSPOT_EN (1 << 27)
9764 #define _ICL_PHY_MISC_A 0x64C00
9765 #define _ICL_PHY_MISC_B 0x64C04
9766 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
9768 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
9770 #endif /* _I915_REG_H_ */