1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <linux/bitfield.h>
29 #include <linux/bits.h>
32 * DOC: The i915 register macro definition style guide
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
40 * Keep helper macros near the top. For example, _PIPE() and friends.
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
54 * For single registers, define the register offset first, followed by register
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
123 * Local wrapper for BIT() to force u32, with compile time checks.
125 * @return: Value with bit @__n set.
127 #define REG_BIT(__n) \
129 BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
130 ((__n) < 0 || (__n) > 31))))
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
135 * @__low: 0-based low bit
137 * Local wrapper for GENMASK() to force u32, with compile time checks.
139 * @return: Continuous bitmask from @__high to @__low, inclusive.
141 #define REG_GENMASK(__high, __low) \
142 ((u32)(GENMASK(__high, __low) + \
143 BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
144 __is_constexpr(__low) && \
145 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
148 * Local integer constant expression version of is_power_of_2().
150 #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
153 * REG_FIELD_PREP() - Prepare a u32 bitfield value
154 * @__mask: shifted mask defining the field's length and position
155 * @__val: value to put in the field
157 * Local copy of FIELD_PREP() to generate an integer constant expression, force
158 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
160 * @return: @__val masked and shifted into the field defined by @__mask.
162 #define REG_FIELD_PREP(__mask, __val) \
163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
170 * REG_FIELD_GET() - Extract a u32 bitfield value
171 * @__mask: shifted mask defining the field's length and position
172 * @__val: value to extract the bitfield value from
174 * Local wrapper for FIELD_GET() to force u32 and for consistency with
175 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
177 * @return: Masked and shifted value of the field defined by @__mask in @__val.
179 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
187 #define INVALID_MMIO_REG _MMIO(0)
189 static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
194 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
199 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
204 #define VLV_DISPLAY_BASE 0x180000
205 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
206 #define BXT_MIPI_BASE 0x60000
208 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
211 * Given the first two numbers __a and __b of arbitrarily many evenly spaced
212 * numbers, pick the 0-based __index'th value.
214 * Always prefer this over _PICK() if the numbers are evenly spaced.
216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
221 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
223 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
226 * Named helper wrappers around _PICK_EVEN() and _PICK().
228 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
229 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
230 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
231 #define _PORT(port, a, b) _PICK_EVEN(port, a, b)
232 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
234 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
235 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
236 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
237 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
238 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
240 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
242 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
243 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
244 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
245 #define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
248 * Device info offset array based helpers for groups of registers with unevenly
249 * spaced base offsets.
251 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
252 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
253 DISPLAY_MMIO_BASE(dev_priv))
254 #define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
255 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
256 DISPLAY_MMIO_BASE(dev_priv))
257 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
258 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
259 DISPLAY_MMIO_BASE(dev_priv))
261 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
262 #define _MASKED_FIELD(mask, value) ({ \
263 if (__builtin_constant_p(mask)) \
264 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
265 if (__builtin_constant_p(value)) \
266 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
267 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
268 BUILD_BUG_ON_MSG((value) & ~(mask), \
269 "Incorrect value for mask"); \
270 __MASKED_FIELD(mask, value); })
271 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
272 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
287 #define RENDER_CLASS 0
288 #define VIDEO_DECODE_CLASS 1
289 #define VIDEO_ENHANCEMENT_CLASS 2
290 #define COPY_ENGINE_CLASS 3
291 #define OTHER_CLASS 4
292 #define MAX_ENGINE_CLASS 4
294 #define OTHER_GUC_INSTANCE 0
295 #define OTHER_GTPM_INSTANCE 1
296 #define MAX_ENGINE_INSTANCE 3
298 /* PCI config space */
300 #define MCHBAR_I915 0x44
301 #define MCHBAR_I965 0x48
302 #define MCHBAR_SIZE (4 * 4096)
305 #define DEVEN_MCHBAR_EN (1 << 28)
307 /* BSM in include/drm/i915_drm.h */
309 #define HPLLCC 0xc0 /* 85x only */
310 #define GC_CLOCK_CONTROL_MASK (0x7 << 0)
311 #define GC_CLOCK_133_200 (0 << 0)
312 #define GC_CLOCK_100_200 (1 << 0)
313 #define GC_CLOCK_100_133 (2 << 0)
314 #define GC_CLOCK_133_266 (3 << 0)
315 #define GC_CLOCK_133_200_2 (4 << 0)
316 #define GC_CLOCK_133_266_2 (5 << 0)
317 #define GC_CLOCK_166_266 (6 << 0)
318 #define GC_CLOCK_166_250 (7 << 0)
320 #define I915_GDRST 0xc0 /* PCI config register */
321 #define GRDOM_FULL (0 << 2)
322 #define GRDOM_RENDER (1 << 2)
323 #define GRDOM_MEDIA (3 << 2)
324 #define GRDOM_MASK (3 << 2)
325 #define GRDOM_RESET_STATUS (1 << 1)
326 #define GRDOM_RESET_ENABLE (1 << 0)
328 /* BSpec only has register offset, PCI device and bit found empirically */
329 #define I830_CLOCK_GATE 0xc8 /* device 0 */
330 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
332 #define GCDGMBUS 0xcc
335 #define GCFGC 0xf0 /* 915+ only */
336 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
337 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
338 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
339 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
340 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
341 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
342 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
343 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
344 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
345 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
346 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
347 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
348 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
349 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
350 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
351 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
352 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
353 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
354 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
355 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
356 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
357 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
358 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
359 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
360 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
361 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
362 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
363 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
364 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
370 #define SWSCI_SCISEL (1 << 15)
371 #define SWSCI_GSSCIE (1 << 0)
373 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
376 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
377 #define ILK_GRDOM_FULL (0 << 1)
378 #define ILK_GRDOM_RENDER (1 << 1)
379 #define ILK_GRDOM_MEDIA (3 << 1)
380 #define ILK_GRDOM_MASK (3 << 1)
381 #define ILK_GRDOM_RESET_ENABLE (1 << 0)
383 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
384 #define GEN6_MBC_SNPCR_SHIFT 21
385 #define GEN6_MBC_SNPCR_MASK (3 << 21)
386 #define GEN6_MBC_SNPCR_MAX (0 << 21)
387 #define GEN6_MBC_SNPCR_MED (1 << 21)
388 #define GEN6_MBC_SNPCR_LOW (2 << 21)
389 #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */
391 #define VLV_G3DCTL _MMIO(0x9024)
392 #define VLV_GSCKGCTL _MMIO(0x9028)
394 #define GEN6_MBCTL _MMIO(0x0907c)
395 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
396 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
397 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
398 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
399 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
401 #define GEN6_GDRST _MMIO(0x941c)
402 #define GEN6_GRDOM_FULL (1 << 0)
403 #define GEN6_GRDOM_RENDER (1 << 1)
404 #define GEN6_GRDOM_MEDIA (1 << 2)
405 #define GEN6_GRDOM_BLT (1 << 3)
406 #define GEN6_GRDOM_VECS (1 << 4)
407 #define GEN9_GRDOM_GUC (1 << 5)
408 #define GEN8_GRDOM_MEDIA2 (1 << 7)
409 /* GEN11 changed all bit defs except for FULL & RENDER */
410 #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
411 #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
412 #define GEN11_GRDOM_BLT (1 << 2)
413 #define GEN11_GRDOM_GUC (1 << 3)
414 #define GEN11_GRDOM_MEDIA (1 << 5)
415 #define GEN11_GRDOM_MEDIA2 (1 << 6)
416 #define GEN11_GRDOM_MEDIA3 (1 << 7)
417 #define GEN11_GRDOM_MEDIA4 (1 << 8)
418 #define GEN11_GRDOM_VECS (1 << 13)
419 #define GEN11_GRDOM_VECS2 (1 << 14)
420 #define GEN11_GRDOM_SFC0 (1 << 17)
421 #define GEN11_GRDOM_SFC1 (1 << 18)
423 #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
424 #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
426 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
427 #define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
428 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
429 #define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
430 #define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
432 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
433 #define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
434 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
435 #define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
436 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
437 #define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
439 #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
440 #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
441 #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
442 #define PP_DIR_DCLV_2G 0xffffffff
444 #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
445 #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
447 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
448 #define GEN8_RPCS_ENABLE (1 << 31)
449 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
450 #define GEN8_RPCS_S_CNT_SHIFT 15
451 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
452 #define GEN11_RPCS_S_CNT_SHIFT 12
453 #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
454 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
455 #define GEN8_RPCS_SS_CNT_SHIFT 8
456 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
457 #define GEN8_RPCS_EU_MAX_SHIFT 4
458 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
459 #define GEN8_RPCS_EU_MIN_SHIFT 0
460 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
462 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
464 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
465 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
466 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
467 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
469 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
470 #define HSW_RCS_CONTEXT_ENABLE (1 << 7)
471 #define HSW_RCS_INHIBIT (1 << 8)
473 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
474 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
475 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
476 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
477 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
478 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
479 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
480 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
481 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
482 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
484 #define GAM_ECOCHK _MMIO(0x4090)
485 #define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
486 #define ECOCHK_SNB_BIT (1 << 10)
487 #define ECOCHK_DIS_TLB (1 << 8)
488 #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
489 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
490 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
491 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
492 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
493 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
494 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
495 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
497 #define GAC_ECO_BITS _MMIO(0x14090)
498 #define ECOBITS_SNB_BIT (1 << 13)
499 #define ECOBITS_PPGTT_CACHE64B (3 << 8)
500 #define ECOBITS_PPGTT_CACHE4B (0 << 8)
502 #define GAB_CTL _MMIO(0x24000)
503 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
505 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
506 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
507 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
508 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
509 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
510 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
511 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
512 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
513 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
514 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
515 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
516 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
517 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
518 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
519 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
520 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
521 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
522 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
526 #define VGA_ST01_MDA 0x3ba
527 #define VGA_ST01_CGA 0x3da
529 #define _VGA_MSR_WRITE _MMIO(0x3c2)
530 #define VGA_MSR_WRITE 0x3c2
531 #define VGA_MSR_READ 0x3cc
532 #define VGA_MSR_MEM_EN (1 << 1)
533 #define VGA_MSR_CGA_MODE (1 << 0)
535 #define VGA_SR_INDEX 0x3c4
537 #define VGA_SR_DATA 0x3c5
539 #define VGA_AR_INDEX 0x3c0
540 #define VGA_AR_VID_EN (1 << 5)
541 #define VGA_AR_DATA_WRITE 0x3c0
542 #define VGA_AR_DATA_READ 0x3c1
544 #define VGA_GR_INDEX 0x3ce
545 #define VGA_GR_DATA 0x3cf
547 #define VGA_GR_MEM_READ_MODE_SHIFT 3
548 #define VGA_GR_MEM_READ_MODE_PLANE 1
550 #define VGA_GR_MEM_MODE_MASK 0xc
551 #define VGA_GR_MEM_MODE_SHIFT 2
552 #define VGA_GR_MEM_A0000_AFFFF 0
553 #define VGA_GR_MEM_A0000_BFFFF 1
554 #define VGA_GR_MEM_B0000_B7FFF 2
555 #define VGA_GR_MEM_B0000_BFFFF 3
557 #define VGA_DACMASK 0x3c6
558 #define VGA_DACRX 0x3c7
559 #define VGA_DACWX 0x3c8
560 #define VGA_DACDATA 0x3c9
562 #define VGA_CR_INDEX_MDA 0x3b4
563 #define VGA_CR_DATA_MDA 0x3b5
564 #define VGA_CR_INDEX_CGA 0x3d4
565 #define VGA_CR_DATA_CGA 0x3d5
567 #define MI_PREDICATE_SRC0 _MMIO(0x2400)
568 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
569 #define MI_PREDICATE_SRC1 _MMIO(0x2408)
570 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
572 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
573 #define LOWER_SLICE_ENABLED (1 << 0)
574 #define LOWER_SLICE_DISABLED (0 << 0)
577 * Registers used only by the command parser
579 #define BCS_SWCTRL _MMIO(0x22200)
581 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
582 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
583 #define HS_INVOCATION_COUNT _MMIO(0x2300)
584 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
585 #define DS_INVOCATION_COUNT _MMIO(0x2308)
586 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
587 #define IA_VERTICES_COUNT _MMIO(0x2310)
588 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
589 #define IA_PRIMITIVES_COUNT _MMIO(0x2318)
590 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
591 #define VS_INVOCATION_COUNT _MMIO(0x2320)
592 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
593 #define GS_INVOCATION_COUNT _MMIO(0x2328)
594 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
595 #define GS_PRIMITIVES_COUNT _MMIO(0x2330)
596 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
597 #define CL_INVOCATION_COUNT _MMIO(0x2338)
598 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
599 #define CL_PRIMITIVES_COUNT _MMIO(0x2340)
600 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
601 #define PS_INVOCATION_COUNT _MMIO(0x2348)
602 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
603 #define PS_DEPTH_COUNT _MMIO(0x2350)
604 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
606 /* There are the 4 64-bit counter registers, one for each stream output */
607 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
608 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
610 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
611 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
613 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
614 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
615 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
616 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
617 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
618 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
620 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
621 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
622 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
624 /* There are the 16 64-bit CS General Purpose Registers */
625 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
626 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
628 #define GEN7_OACONTROL _MMIO(0x2360)
629 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
630 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
631 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
632 #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
633 #define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
634 #define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
635 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
636 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
637 #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
638 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
639 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
640 #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
641 #define GEN7_OACONTROL_FORMAT_SHIFT 2
642 #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
643 #define GEN7_OACONTROL_ENABLE (1 << 0)
645 #define GEN8_OACTXID _MMIO(0x2364)
647 #define GEN8_OA_DEBUG _MMIO(0x2B04)
648 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
649 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
650 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
651 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
653 #define GEN8_OACONTROL _MMIO(0x2B00)
654 #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
655 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
656 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
657 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
658 #define GEN8_OA_REPORT_FORMAT_SHIFT 2
659 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
660 #define GEN8_OA_COUNTER_ENABLE (1 << 0)
662 #define GEN8_OACTXCONTROL _MMIO(0x2360)
663 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F
664 #define GEN8_OA_TIMER_PERIOD_SHIFT 2
665 #define GEN8_OA_TIMER_ENABLE (1 << 1)
666 #define GEN8_OA_COUNTER_RESUME (1 << 0)
668 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
669 #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
670 #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
671 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
672 #define GEN7_OABUFFER_RESUME (1 << 0)
674 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
675 #define GEN8_OABUFFER _MMIO(0x2b14)
676 #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
678 #define GEN7_OASTATUS1 _MMIO(0x2364)
679 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
680 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
681 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
682 #define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
684 #define GEN7_OASTATUS2 _MMIO(0x2368)
685 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
686 #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
688 #define GEN8_OASTATUS _MMIO(0x2b08)
689 #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
690 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
691 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
692 #define GEN8_OASTATUS_REPORT_LOST (1 << 0)
694 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
695 #define GEN8_OAHEADPTR_MASK 0xffffffc0
696 #define GEN8_OATAILPTR _MMIO(0x2B10)
697 #define GEN8_OATAILPTR_MASK 0xffffffc0
699 #define OABUFFER_SIZE_128K (0 << 3)
700 #define OABUFFER_SIZE_256K (1 << 3)
701 #define OABUFFER_SIZE_512K (2 << 3)
702 #define OABUFFER_SIZE_1M (3 << 3)
703 #define OABUFFER_SIZE_2M (4 << 3)
704 #define OABUFFER_SIZE_4M (5 << 3)
705 #define OABUFFER_SIZE_8M (6 << 3)
706 #define OABUFFER_SIZE_16M (7 << 3)
709 * Flexible, Aggregate EU Counter Registers.
710 * Note: these aren't contiguous
712 #define EU_PERF_CNTL0 _MMIO(0xe458)
713 #define EU_PERF_CNTL1 _MMIO(0xe558)
714 #define EU_PERF_CNTL2 _MMIO(0xe658)
715 #define EU_PERF_CNTL3 _MMIO(0xe758)
716 #define EU_PERF_CNTL4 _MMIO(0xe45c)
717 #define EU_PERF_CNTL5 _MMIO(0xe55c)
718 #define EU_PERF_CNTL6 _MMIO(0xe65c)
724 #define OASTARTTRIG1 _MMIO(0x2710)
725 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
726 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff
728 #define OASTARTTRIG2 _MMIO(0x2714)
729 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
730 #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
731 #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
732 #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
733 #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
734 #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
735 #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
736 #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
737 #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
738 #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
739 #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
740 #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
741 #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
742 #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
743 #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
744 #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
745 #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
746 #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
747 #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
748 #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
749 #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
750 #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
751 #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
752 #define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
753 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
754 #define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
755 #define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
756 #define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
757 #define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
759 #define OASTARTTRIG3 _MMIO(0x2718)
760 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf
761 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
762 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
763 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
764 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
765 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
766 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
767 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
768 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
770 #define OASTARTTRIG4 _MMIO(0x271c)
771 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf
772 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
773 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
774 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
775 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
776 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
777 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
778 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
779 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
781 #define OASTARTTRIG5 _MMIO(0x2720)
782 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
783 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff
785 #define OASTARTTRIG6 _MMIO(0x2724)
786 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
787 #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
788 #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
789 #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
790 #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
791 #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
792 #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
793 #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
794 #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
795 #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
796 #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
797 #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
798 #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
799 #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
800 #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
801 #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
802 #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
803 #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
804 #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
805 #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
806 #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
807 #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
808 #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
809 #define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
810 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
811 #define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
812 #define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
813 #define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
814 #define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
816 #define OASTARTTRIG7 _MMIO(0x2728)
817 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf
818 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
819 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
820 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
821 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
822 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
823 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
824 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
825 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
827 #define OASTARTTRIG8 _MMIO(0x272c)
828 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf
829 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
830 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
831 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
832 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
833 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
834 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
835 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
836 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
838 #define OAREPORTTRIG1 _MMIO(0x2740)
839 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
840 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
842 #define OAREPORTTRIG2 _MMIO(0x2744)
843 #define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
844 #define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
845 #define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
846 #define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
847 #define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
848 #define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
849 #define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
850 #define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
851 #define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
852 #define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
853 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
854 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
855 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
856 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
857 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
858 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
859 #define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
860 #define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
861 #define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
862 #define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
863 #define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
864 #define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
865 #define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
866 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
867 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
869 #define OAREPORTTRIG3 _MMIO(0x2748)
870 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
871 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
872 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
873 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
874 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
875 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
876 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
877 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
878 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
880 #define OAREPORTTRIG4 _MMIO(0x274c)
881 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
882 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
883 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
884 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
885 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
886 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
887 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
888 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
889 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
891 #define OAREPORTTRIG5 _MMIO(0x2750)
892 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
893 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
895 #define OAREPORTTRIG6 _MMIO(0x2754)
896 #define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
897 #define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
898 #define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
899 #define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
900 #define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
901 #define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
902 #define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
903 #define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
904 #define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
905 #define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
906 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
907 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
908 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
909 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
910 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
911 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
912 #define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
913 #define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
914 #define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
915 #define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
916 #define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
917 #define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
918 #define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
919 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
920 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
922 #define OAREPORTTRIG7 _MMIO(0x2758)
923 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
924 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
925 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
926 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
927 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
928 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
929 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
930 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
931 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
933 #define OAREPORTTRIG8 _MMIO(0x275c)
934 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
935 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
936 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
937 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
938 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
939 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
940 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
941 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
942 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
945 #define OACEC_COMPARE_LESS_OR_EQUAL 6
946 #define OACEC_COMPARE_NOT_EQUAL 5
947 #define OACEC_COMPARE_LESS_THAN 4
948 #define OACEC_COMPARE_GREATER_OR_EQUAL 3
949 #define OACEC_COMPARE_EQUAL 2
950 #define OACEC_COMPARE_GREATER_THAN 1
951 #define OACEC_COMPARE_ANY_EQUAL 0
953 #define OACEC_COMPARE_VALUE_MASK 0xffff
954 #define OACEC_COMPARE_VALUE_SHIFT 3
956 #define OACEC_SELECT_NOA (0 << 19)
957 #define OACEC_SELECT_PREV (1 << 19)
958 #define OACEC_SELECT_BOOLEAN (2 << 19)
961 #define OACEC_MASK_MASK 0xffff
962 #define OACEC_CONSIDERATIONS_MASK 0xffff
963 #define OACEC_CONSIDERATIONS_SHIFT 16
965 #define OACEC0_0 _MMIO(0x2770)
966 #define OACEC0_1 _MMIO(0x2774)
967 #define OACEC1_0 _MMIO(0x2778)
968 #define OACEC1_1 _MMIO(0x277c)
969 #define OACEC2_0 _MMIO(0x2780)
970 #define OACEC2_1 _MMIO(0x2784)
971 #define OACEC3_0 _MMIO(0x2788)
972 #define OACEC3_1 _MMIO(0x278c)
973 #define OACEC4_0 _MMIO(0x2790)
974 #define OACEC4_1 _MMIO(0x2794)
975 #define OACEC5_0 _MMIO(0x2798)
976 #define OACEC5_1 _MMIO(0x279c)
977 #define OACEC6_0 _MMIO(0x27a0)
978 #define OACEC6_1 _MMIO(0x27a4)
979 #define OACEC7_0 _MMIO(0x27a8)
980 #define OACEC7_1 _MMIO(0x27ac)
982 /* OA perf counters */
983 #define OA_PERFCNT1_LO _MMIO(0x91B8)
984 #define OA_PERFCNT1_HI _MMIO(0x91BC)
985 #define OA_PERFCNT2_LO _MMIO(0x91C0)
986 #define OA_PERFCNT2_HI _MMIO(0x91C4)
987 #define OA_PERFCNT3_LO _MMIO(0x91C8)
988 #define OA_PERFCNT3_HI _MMIO(0x91CC)
989 #define OA_PERFCNT4_LO _MMIO(0x91D8)
990 #define OA_PERFCNT4_HI _MMIO(0x91DC)
992 #define OA_PERFMATRIX_LO _MMIO(0x91C8)
993 #define OA_PERFMATRIX_HI _MMIO(0x91CC)
995 /* RPM unit config (Gen8+) */
996 #define RPM_CONFIG0 _MMIO(0x0D00)
997 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
998 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
999 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1000 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
1001 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1002 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1003 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
1004 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
1005 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
1006 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
1007 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1008 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1010 #define RPM_CONFIG1 _MMIO(0x0D04)
1011 #define GEN10_GT_NOA_ENABLE (1 << 9)
1013 /* GPM unit config (Gen9+) */
1014 #define CTC_MODE _MMIO(0xA26C)
1015 #define CTC_SOURCE_PARAMETER_MASK 1
1016 #define CTC_SOURCE_CRYSTAL_CLOCK 0
1017 #define CTC_SOURCE_DIVIDE_LOGIC 1
1018 #define CTC_SHIFT_PARAMETER_SHIFT 1
1019 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1021 /* RCP unit config (Gen8+) */
1022 #define RCP_CONFIG _MMIO(0x0D08)
1025 #define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1026 #define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1027 #define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1028 #define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1029 #define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1030 #define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1031 #define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1032 #define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1033 #define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1034 #define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1036 #define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1039 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1041 #define MICRO_BP0_0 _MMIO(0x9800)
1042 #define MICRO_BP0_2 _MMIO(0x9804)
1043 #define MICRO_BP0_1 _MMIO(0x9808)
1045 #define MICRO_BP1_0 _MMIO(0x980C)
1046 #define MICRO_BP1_2 _MMIO(0x9810)
1047 #define MICRO_BP1_1 _MMIO(0x9814)
1049 #define MICRO_BP2_0 _MMIO(0x9818)
1050 #define MICRO_BP2_2 _MMIO(0x981C)
1051 #define MICRO_BP2_1 _MMIO(0x9820)
1053 #define MICRO_BP3_0 _MMIO(0x9824)
1054 #define MICRO_BP3_2 _MMIO(0x9828)
1055 #define MICRO_BP3_1 _MMIO(0x982C)
1057 #define MICRO_BP_TRIGGER _MMIO(0x9830)
1058 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1059 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1060 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1062 #define GDT_CHICKEN_BITS _MMIO(0x9840)
1063 #define GT_NOA_ENABLE 0x00000080
1065 #define NOA_DATA _MMIO(0x986C)
1066 #define NOA_WRITE _MMIO(0x9888)
1067 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1069 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1070 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
1071 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1076 #define DEBUG_RESET_I830 _MMIO(0x6070)
1077 #define DEBUG_RESET_FULL (1 << 7)
1078 #define DEBUG_RESET_RENDER (1 << 8)
1079 #define DEBUG_RESET_DISPLAY (1 << 9)
1084 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
1085 #define IOSF_DEVFN_SHIFT 24
1086 #define IOSF_OPCODE_SHIFT 16
1087 #define IOSF_PORT_SHIFT 8
1088 #define IOSF_BYTE_ENABLES_SHIFT 4
1089 #define IOSF_BAR_SHIFT 1
1090 #define IOSF_SB_BUSY (1 << 0)
1091 #define IOSF_PORT_BUNIT 0x03
1092 #define IOSF_PORT_PUNIT 0x04
1093 #define IOSF_PORT_NC 0x11
1094 #define IOSF_PORT_DPIO 0x12
1095 #define IOSF_PORT_GPIO_NC 0x13
1096 #define IOSF_PORT_CCK 0x14
1097 #define IOSF_PORT_DPIO_2 0x1a
1098 #define IOSF_PORT_FLISDSI 0x1b
1099 #define IOSF_PORT_GPIO_SC 0x48
1100 #define IOSF_PORT_GPIO_SUS 0xa8
1101 #define IOSF_PORT_CCU 0xa9
1102 #define CHV_IOSF_PORT_GPIO_N 0x13
1103 #define CHV_IOSF_PORT_GPIO_SE 0x48
1104 #define CHV_IOSF_PORT_GPIO_E 0xa8
1105 #define CHV_IOSF_PORT_GPIO_SW 0xb2
1106 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1107 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1109 /* See configdb bunit SB addr map */
1110 #define BUNIT_REG_BISOC 0x11
1112 /* PUNIT_REG_*SSPM0 */
1113 #define _SSPM0_SSC(val) ((val) << 0)
1114 #define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
1115 #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
1116 #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
1117 #define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
1118 #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
1119 #define _SSPM0_SSS(val) ((val) << 24)
1120 #define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
1121 #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
1122 #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
1123 #define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
1124 #define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
1126 /* PUNIT_REG_*SSPM1 */
1127 #define SSPM1_FREQSTAT_SHIFT 24
1128 #define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
1129 #define SSPM1_FREQGUAR_SHIFT 8
1130 #define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
1131 #define SSPM1_FREQ_SHIFT 0
1132 #define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
1134 #define PUNIT_REG_VEDSSPM0 0x32
1135 #define PUNIT_REG_VEDSSPM1 0x33
1137 #define PUNIT_REG_DSPSSPM 0x36
1138 #define DSPFREQSTAT_SHIFT_CHV 24
1139 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1140 #define DSPFREQGUAR_SHIFT_CHV 8
1141 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1142 #define DSPFREQSTAT_SHIFT 30
1143 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1144 #define DSPFREQGUAR_SHIFT 14
1145 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1146 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1147 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1148 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
1149 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1150 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1151 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1152 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1153 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1154 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1155 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1156 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1157 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1158 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1159 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1160 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1162 #define PUNIT_REG_ISPSSPM0 0x39
1163 #define PUNIT_REG_ISPSSPM1 0x3a
1166 * i915_power_well_id:
1168 * IDs used to look up power wells. Power wells accessed directly bypassing
1169 * the power domains framework must be assigned a unique ID. The rest of power
1170 * wells must be assigned DISP_PW_ID_NONE.
1172 enum i915_power_well_id {
1176 BXT_DISP_PW_DPIO_CMN_A,
1177 VLV_DISP_PW_DPIO_CMN_BC,
1178 GLK_DISP_PW_DPIO_CMN_C,
1179 CHV_DISP_PW_DPIO_CMN_D,
1181 SKL_DISP_PW_MISC_IO,
1186 #define PUNIT_REG_PWRGT_CTRL 0x60
1187 #define PUNIT_REG_PWRGT_STATUS 0x61
1188 #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1189 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1190 #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1191 #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1192 #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1194 #define PUNIT_PWGT_IDX_RENDER 0
1195 #define PUNIT_PWGT_IDX_MEDIA 1
1196 #define PUNIT_PWGT_IDX_DISP2D 3
1197 #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1198 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1199 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1200 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1201 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1202 #define PUNIT_PWGT_IDX_DPIO_RX0 10
1203 #define PUNIT_PWGT_IDX_DPIO_RX1 11
1204 #define PUNIT_PWGT_IDX_DPIO_CMN_D 12
1206 #define PUNIT_REG_GPU_LFM 0xd3
1207 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
1208 #define PUNIT_REG_GPU_FREQ_STS 0xd8
1209 #define GPLLENABLE (1 << 4)
1210 #define GENFREQSTATUS (1 << 0)
1211 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1212 #define PUNIT_REG_CZ_TIMESTAMP 0xce
1214 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1215 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1217 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1218 #define FB_GFX_FREQ_FUSE_MASK 0xff
1219 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1220 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1221 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1223 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1224 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1226 #define PUNIT_REG_DDR_SETUP2 0x139
1227 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1228 #define FORCE_DDR_LOW_FREQ (1 << 1)
1229 #define FORCE_DDR_HIGH_FREQ (1 << 0)
1231 #define PUNIT_GPU_STATUS_REG 0xdb
1232 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1233 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1234 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1235 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1237 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1238 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1239 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1241 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1242 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1243 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1244 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1245 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1246 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1247 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1248 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1249 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1250 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1252 #define VLV_TURBO_SOC_OVERRIDE 0x04
1253 #define VLV_OVERRIDE_EN 1
1254 #define VLV_SOC_TDP_EN (1 << 1)
1255 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1256 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1258 /* vlv2 north clock has */
1259 #define CCK_FUSE_REG 0x8
1260 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
1261 #define CCK_REG_DSI_PLL_FUSE 0x44
1262 #define CCK_REG_DSI_PLL_CONTROL 0x48
1263 #define DSI_PLL_VCO_EN (1 << 31)
1264 #define DSI_PLL_LDO_GATE (1 << 30)
1265 #define DSI_PLL_P1_POST_DIV_SHIFT 17
1266 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1267 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1268 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1269 #define DSI_PLL_MUX_MASK (3 << 9)
1270 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1271 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1272 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1273 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1274 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1275 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1276 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1277 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1278 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1279 #define DSI_PLL_LOCK (1 << 0)
1280 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
1281 #define DSI_PLL_LFSR (1 << 31)
1282 #define DSI_PLL_FRACTION_EN (1 << 30)
1283 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
1284 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1285 #define DSI_PLL_USYNC_CNT_SHIFT 18
1286 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1287 #define DSI_PLL_N1_DIV_SHIFT 16
1288 #define DSI_PLL_N1_DIV_MASK (3 << 16)
1289 #define DSI_PLL_M1_DIV_SHIFT 0
1290 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1291 #define CCK_CZ_CLOCK_CONTROL 0x62
1292 #define CCK_GPLL_CLOCK_CONTROL 0x67
1293 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1294 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1295 #define CCK_TRUNK_FORCE_ON (1 << 17)
1296 #define CCK_TRUNK_FORCE_OFF (1 << 16)
1297 #define CCK_FREQUENCY_STATUS (0x1f << 8)
1298 #define CCK_FREQUENCY_STATUS_SHIFT 8
1299 #define CCK_FREQUENCY_VALUES (0x1f << 0)
1301 /* DPIO registers */
1302 #define DPIO_DEVFN 0
1304 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1305 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
1306 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
1307 #define DPIO_SFR_BYPASS (1 << 1)
1308 #define DPIO_CMNRST (1 << 0)
1310 #define DPIO_PHY(pipe) ((pipe) >> 1)
1311 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1314 * Per pipe/PLL DPIO regs
1316 #define _VLV_PLL_DW3_CH0 0x800c
1317 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
1318 #define DPIO_POST_DIV_DAC 0
1319 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1320 #define DPIO_POST_DIV_LVDS1 2
1321 #define DPIO_POST_DIV_LVDS2 3
1322 #define DPIO_K_SHIFT (24) /* 4 bits */
1323 #define DPIO_P1_SHIFT (21) /* 3 bits */
1324 #define DPIO_P2_SHIFT (16) /* 5 bits */
1325 #define DPIO_N_SHIFT (12) /* 4 bits */
1326 #define DPIO_ENABLE_CALIBRATION (1 << 11)
1327 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1328 #define DPIO_M2DIV_MASK 0xff
1329 #define _VLV_PLL_DW3_CH1 0x802c
1330 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1332 #define _VLV_PLL_DW5_CH0 0x8014
1333 #define DPIO_REFSEL_OVERRIDE 27
1334 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1335 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1336 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
1337 #define DPIO_PLL_REFCLK_SEL_MASK 3
1338 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1339 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1340 #define _VLV_PLL_DW5_CH1 0x8034
1341 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1343 #define _VLV_PLL_DW7_CH0 0x801c
1344 #define _VLV_PLL_DW7_CH1 0x803c
1345 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1347 #define _VLV_PLL_DW8_CH0 0x8040
1348 #define _VLV_PLL_DW8_CH1 0x8060
1349 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1351 #define VLV_PLL_DW9_BCAST 0xc044
1352 #define _VLV_PLL_DW9_CH0 0x8044
1353 #define _VLV_PLL_DW9_CH1 0x8064
1354 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1356 #define _VLV_PLL_DW10_CH0 0x8048
1357 #define _VLV_PLL_DW10_CH1 0x8068
1358 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1360 #define _VLV_PLL_DW11_CH0 0x804c
1361 #define _VLV_PLL_DW11_CH1 0x806c
1362 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1364 /* Spec for ref block start counts at DW10 */
1365 #define VLV_REF_DW13 0x80ac
1367 #define VLV_CMN_DW0 0x8100
1370 * Per DDI channel DPIO regs
1373 #define _VLV_PCS_DW0_CH0 0x8200
1374 #define _VLV_PCS_DW0_CH1 0x8400
1375 #define DPIO_PCS_TX_LANE2_RESET (1 << 16)
1376 #define DPIO_PCS_TX_LANE1_RESET (1 << 7)
1377 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
1378 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
1379 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1381 #define _VLV_PCS01_DW0_CH0 0x200
1382 #define _VLV_PCS23_DW0_CH0 0x400
1383 #define _VLV_PCS01_DW0_CH1 0x2600
1384 #define _VLV_PCS23_DW0_CH1 0x2800
1385 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1386 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1388 #define _VLV_PCS_DW1_CH0 0x8204
1389 #define _VLV_PCS_DW1_CH1 0x8404
1390 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
1391 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1392 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1393 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1394 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
1395 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1397 #define _VLV_PCS01_DW1_CH0 0x204
1398 #define _VLV_PCS23_DW1_CH0 0x404
1399 #define _VLV_PCS01_DW1_CH1 0x2604
1400 #define _VLV_PCS23_DW1_CH1 0x2804
1401 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1402 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1404 #define _VLV_PCS_DW8_CH0 0x8220
1405 #define _VLV_PCS_DW8_CH1 0x8420
1406 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1407 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1408 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1410 #define _VLV_PCS01_DW8_CH0 0x0220
1411 #define _VLV_PCS23_DW8_CH0 0x0420
1412 #define _VLV_PCS01_DW8_CH1 0x2620
1413 #define _VLV_PCS23_DW8_CH1 0x2820
1414 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1415 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1417 #define _VLV_PCS_DW9_CH0 0x8224
1418 #define _VLV_PCS_DW9_CH1 0x8424
1419 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
1420 #define DPIO_PCS_TX2MARGIN_000 (0 << 13)
1421 #define DPIO_PCS_TX2MARGIN_101 (1 << 13)
1422 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
1423 #define DPIO_PCS_TX1MARGIN_000 (0 << 10)
1424 #define DPIO_PCS_TX1MARGIN_101 (1 << 10)
1425 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1427 #define _VLV_PCS01_DW9_CH0 0x224
1428 #define _VLV_PCS23_DW9_CH0 0x424
1429 #define _VLV_PCS01_DW9_CH1 0x2624
1430 #define _VLV_PCS23_DW9_CH1 0x2824
1431 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1432 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1434 #define _CHV_PCS_DW10_CH0 0x8228
1435 #define _CHV_PCS_DW10_CH1 0x8428
1436 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
1437 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
1438 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
1439 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
1440 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
1441 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
1442 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
1443 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
1444 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1446 #define _VLV_PCS01_DW10_CH0 0x0228
1447 #define _VLV_PCS23_DW10_CH0 0x0428
1448 #define _VLV_PCS01_DW10_CH1 0x2628
1449 #define _VLV_PCS23_DW10_CH1 0x2828
1450 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1451 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1453 #define _VLV_PCS_DW11_CH0 0x822c
1454 #define _VLV_PCS_DW11_CH1 0x842c
1455 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
1456 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
1457 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
1458 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
1459 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1461 #define _VLV_PCS01_DW11_CH0 0x022c
1462 #define _VLV_PCS23_DW11_CH0 0x042c
1463 #define _VLV_PCS01_DW11_CH1 0x262c
1464 #define _VLV_PCS23_DW11_CH1 0x282c
1465 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1466 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1468 #define _VLV_PCS01_DW12_CH0 0x0230
1469 #define _VLV_PCS23_DW12_CH0 0x0430
1470 #define _VLV_PCS01_DW12_CH1 0x2630
1471 #define _VLV_PCS23_DW12_CH1 0x2830
1472 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1473 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1475 #define _VLV_PCS_DW12_CH0 0x8230
1476 #define _VLV_PCS_DW12_CH1 0x8430
1477 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
1478 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
1479 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
1480 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
1481 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
1482 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1484 #define _VLV_PCS_DW14_CH0 0x8238
1485 #define _VLV_PCS_DW14_CH1 0x8438
1486 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1488 #define _VLV_PCS_DW23_CH0 0x825c
1489 #define _VLV_PCS_DW23_CH1 0x845c
1490 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1492 #define _VLV_TX_DW2_CH0 0x8288
1493 #define _VLV_TX_DW2_CH1 0x8488
1494 #define DPIO_SWING_MARGIN000_SHIFT 16
1495 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1496 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1497 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1499 #define _VLV_TX_DW3_CH0 0x828c
1500 #define _VLV_TX_DW3_CH1 0x848c
1501 /* The following bit for CHV phy */
1502 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
1503 #define DPIO_SWING_MARGIN101_SHIFT 16
1504 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1505 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1507 #define _VLV_TX_DW4_CH0 0x8290
1508 #define _VLV_TX_DW4_CH1 0x8490
1509 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
1510 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1511 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
1512 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1513 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1515 #define _VLV_TX3_DW4_CH0 0x690
1516 #define _VLV_TX3_DW4_CH1 0x2a90
1517 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1519 #define _VLV_TX_DW5_CH0 0x8294
1520 #define _VLV_TX_DW5_CH1 0x8494
1521 #define DPIO_TX_OCALINIT_EN (1 << 31)
1522 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1524 #define _VLV_TX_DW11_CH0 0x82ac
1525 #define _VLV_TX_DW11_CH1 0x84ac
1526 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1528 #define _VLV_TX_DW14_CH0 0x82b8
1529 #define _VLV_TX_DW14_CH1 0x84b8
1530 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1532 /* CHV dpPhy registers */
1533 #define _CHV_PLL_DW0_CH0 0x8000
1534 #define _CHV_PLL_DW0_CH1 0x8180
1535 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1537 #define _CHV_PLL_DW1_CH0 0x8004
1538 #define _CHV_PLL_DW1_CH1 0x8184
1539 #define DPIO_CHV_N_DIV_SHIFT 8
1540 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1541 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1543 #define _CHV_PLL_DW2_CH0 0x8008
1544 #define _CHV_PLL_DW2_CH1 0x8188
1545 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1547 #define _CHV_PLL_DW3_CH0 0x800c
1548 #define _CHV_PLL_DW3_CH1 0x818c
1549 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1550 #define DPIO_CHV_FIRST_MOD (0 << 8)
1551 #define DPIO_CHV_SECOND_MOD (1 << 8)
1552 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1553 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1554 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1556 #define _CHV_PLL_DW6_CH0 0x8018
1557 #define _CHV_PLL_DW6_CH1 0x8198
1558 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1559 #define DPIO_CHV_INT_COEFF_SHIFT 8
1560 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1561 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1563 #define _CHV_PLL_DW8_CH0 0x8020
1564 #define _CHV_PLL_DW8_CH1 0x81A0
1565 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1566 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1567 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1569 #define _CHV_PLL_DW9_CH0 0x8024
1570 #define _CHV_PLL_DW9_CH1 0x81A4
1571 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1572 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1573 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1574 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1576 #define _CHV_CMN_DW0_CH0 0x8100
1577 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1578 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1579 #define DPIO_ALLDL_POWERDOWN (1 << 1)
1580 #define DPIO_ANYDL_POWERDOWN (1 << 0)
1582 #define _CHV_CMN_DW5_CH0 0x8114
1583 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1584 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1585 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1586 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1587 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1588 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1589 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1590 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1592 #define _CHV_CMN_DW13_CH0 0x8134
1593 #define _CHV_CMN_DW0_CH1 0x8080
1594 #define DPIO_CHV_S1_DIV_SHIFT 21
1595 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1596 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1597 #define DPIO_CHV_K_DIV_SHIFT 4
1598 #define DPIO_PLL_FREQLOCK (1 << 1)
1599 #define DPIO_PLL_LOCK (1 << 0)
1600 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1602 #define _CHV_CMN_DW14_CH0 0x8138
1603 #define _CHV_CMN_DW1_CH1 0x8084
1604 #define DPIO_AFC_RECAL (1 << 14)
1605 #define DPIO_DCLKP_EN (1 << 13)
1606 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1607 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1608 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1609 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1610 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1611 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1612 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1613 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1614 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1616 #define _CHV_CMN_DW19_CH0 0x814c
1617 #define _CHV_CMN_DW6_CH1 0x8098
1618 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1619 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1620 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1621 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1623 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1625 #define CHV_CMN_DW28 0x8170
1626 #define DPIO_CL1POWERDOWNEN (1 << 23)
1627 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1628 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1629 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1630 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1631 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1633 #define CHV_CMN_DW30 0x8178
1634 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1635 #define DPIO_LRC_BYPASS (1 << 3)
1637 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1638 (lane) * 0x200 + (offset))
1640 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1641 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1642 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1643 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1644 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1645 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1646 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1647 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1648 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1649 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1650 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1651 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1652 #define DPIO_FRC_LATENCY_SHFIT 8
1653 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1654 #define DPIO_UPAR_SHIFT 30
1656 /* BXT PHY registers */
1657 #define _BXT_PHY0_BASE 0x6C000
1658 #define _BXT_PHY1_BASE 0x162000
1659 #define _BXT_PHY2_BASE 0x163000
1660 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1664 #define _BXT_PHY(phy, reg) \
1665 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1667 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1668 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1669 (reg_ch1) - _BXT_PHY0_BASE))
1670 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1671 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1673 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1674 #define MIPIO_RST_CTRL (1 << 2)
1676 #define _BXT_PHY_CTL_DDI_A 0x64C00
1677 #define _BXT_PHY_CTL_DDI_B 0x64C10
1678 #define _BXT_PHY_CTL_DDI_C 0x64C20
1679 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1680 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1681 #define BXT_PHY_LANE_ENABLED (1 << 8)
1682 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1685 #define _PHY_CTL_FAMILY_EDP 0x64C80
1686 #define _PHY_CTL_FAMILY_DDI 0x64C90
1687 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1688 #define COMMON_RESET_DIS (1 << 31)
1689 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1690 _PHY_CTL_FAMILY_EDP, \
1691 _PHY_CTL_FAMILY_DDI_C)
1693 /* BXT PHY PLL registers */
1694 #define _PORT_PLL_A 0x46074
1695 #define _PORT_PLL_B 0x46078
1696 #define _PORT_PLL_C 0x4607c
1697 #define PORT_PLL_ENABLE (1 << 31)
1698 #define PORT_PLL_LOCK (1 << 30)
1699 #define PORT_PLL_REF_SEL (1 << 27)
1700 #define PORT_PLL_POWER_ENABLE (1 << 26)
1701 #define PORT_PLL_POWER_STATE (1 << 25)
1702 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1704 #define _PORT_PLL_EBB_0_A 0x162034
1705 #define _PORT_PLL_EBB_0_B 0x6C034
1706 #define _PORT_PLL_EBB_0_C 0x6C340
1707 #define PORT_PLL_P1_SHIFT 13
1708 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1709 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1710 #define PORT_PLL_P2_SHIFT 8
1711 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1712 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1713 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1714 _PORT_PLL_EBB_0_B, \
1717 #define _PORT_PLL_EBB_4_A 0x162038
1718 #define _PORT_PLL_EBB_4_B 0x6C038
1719 #define _PORT_PLL_EBB_4_C 0x6C344
1720 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1721 #define PORT_PLL_RECALIBRATE (1 << 14)
1722 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1723 _PORT_PLL_EBB_4_B, \
1726 #define _PORT_PLL_0_A 0x162100
1727 #define _PORT_PLL_0_B 0x6C100
1728 #define _PORT_PLL_0_C 0x6C380
1730 #define PORT_PLL_M2_MASK 0xFF
1732 #define PORT_PLL_N_SHIFT 8
1733 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1734 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1736 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1738 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1740 #define PORT_PLL_PROP_COEFF_MASK 0xF
1741 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1742 #define PORT_PLL_INT_COEFF(x) ((x) << 8)
1743 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1744 #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1746 #define PORT_PLL_TARGET_CNT_MASK 0x3FF
1748 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1749 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1751 #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
1752 #define PORT_PLL_DCO_AMP_DEFAULT 15
1753 #define PORT_PLL_DCO_AMP_MASK 0x3c00
1754 #define PORT_PLL_DCO_AMP(x) ((x) << 10)
1755 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1758 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1761 /* BXT PHY common lane registers */
1762 #define _PORT_CL1CM_DW0_A 0x162000
1763 #define _PORT_CL1CM_DW0_BC 0x6C000
1764 #define PHY_POWER_GOOD (1 << 16)
1765 #define PHY_RESERVED (1 << 7)
1766 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1768 #define _PORT_CL1CM_DW9_A 0x162024
1769 #define _PORT_CL1CM_DW9_BC 0x6C024
1770 #define IREF0RC_OFFSET_SHIFT 8
1771 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1772 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1774 #define _PORT_CL1CM_DW10_A 0x162028
1775 #define _PORT_CL1CM_DW10_BC 0x6C028
1776 #define IREF1RC_OFFSET_SHIFT 8
1777 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1778 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1780 #define _PORT_CL1CM_DW28_A 0x162070
1781 #define _PORT_CL1CM_DW28_BC 0x6C070
1782 #define OCL1_POWER_DOWN_EN (1 << 23)
1783 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1784 #define SUS_CLK_CONFIG 0x3
1785 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1787 #define _PORT_CL1CM_DW30_A 0x162078
1788 #define _PORT_CL1CM_DW30_BC 0x6C078
1789 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1790 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1793 * CNL/ICL Port/COMBO-PHY Registers
1795 #define _ICL_COMBOPHY_A 0x162000
1796 #define _ICL_COMBOPHY_B 0x6C000
1797 #define _EHL_COMBOPHY_C 0x160000
1798 #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
1802 /* CNL/ICL Port CL_DW registers */
1803 #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1806 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1807 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
1808 #define CL_POWER_DOWN_ENABLE (1 << 4)
1809 #define SUS_CLOCK_CONFIG (3 << 0)
1811 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
1812 #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1813 #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1814 #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1815 #define PWR_UP_ALL_LANES (0x0 << 4)
1816 #define PWR_DOWN_LN_3_2_1 (0xe << 4)
1817 #define PWR_DOWN_LN_3_2 (0xc << 4)
1818 #define PWR_DOWN_LN_3 (0x8 << 4)
1819 #define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1820 #define PWR_DOWN_LN_1_0 (0x3 << 4)
1821 #define PWR_DOWN_LN_3_1 (0xa << 4)
1822 #define PWR_DOWN_LN_3_1_0 (0xb << 4)
1823 #define PWR_DOWN_LN_MASK (0xf << 4)
1824 #define PWR_DOWN_LN_SHIFT 4
1826 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
1827 #define ICL_LANE_ENABLE_AUX (1 << 0)
1829 /* CNL/ICL Port COMP_DW registers */
1830 #define _ICL_PORT_COMP 0x100
1831 #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1832 _ICL_PORT_COMP + 4 * (dw))
1834 #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
1835 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
1836 #define COMP_INIT (1 << 31)
1838 #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
1839 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
1841 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
1842 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
1843 #define PROCESS_INFO_DOT_0 (0 << 26)
1844 #define PROCESS_INFO_DOT_1 (1 << 26)
1845 #define PROCESS_INFO_DOT_4 (2 << 26)
1846 #define PROCESS_INFO_MASK (7 << 26)
1847 #define PROCESS_INFO_SHIFT 26
1848 #define VOLTAGE_INFO_0_85V (0 << 24)
1849 #define VOLTAGE_INFO_0_95V (1 << 24)
1850 #define VOLTAGE_INFO_1_05V (2 << 24)
1851 #define VOLTAGE_INFO_MASK (3 << 24)
1852 #define VOLTAGE_INFO_SHIFT 24
1854 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
1855 #define IREFGEN (1 << 24)
1857 #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
1858 #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
1860 #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
1861 #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
1863 /* CNL/ICL Port PCS registers */
1864 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1865 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1866 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1867 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1868 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1869 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1870 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1871 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1872 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1873 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1874 #define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
1875 _CNL_PORT_PCS_DW1_GRP_AE, \
1876 _CNL_PORT_PCS_DW1_GRP_B, \
1877 _CNL_PORT_PCS_DW1_GRP_C, \
1878 _CNL_PORT_PCS_DW1_GRP_D, \
1879 _CNL_PORT_PCS_DW1_GRP_AE, \
1880 _CNL_PORT_PCS_DW1_GRP_F))
1881 #define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
1882 _CNL_PORT_PCS_DW1_LN0_AE, \
1883 _CNL_PORT_PCS_DW1_LN0_B, \
1884 _CNL_PORT_PCS_DW1_LN0_C, \
1885 _CNL_PORT_PCS_DW1_LN0_D, \
1886 _CNL_PORT_PCS_DW1_LN0_AE, \
1887 _CNL_PORT_PCS_DW1_LN0_F))
1889 #define _ICL_PORT_PCS_AUX 0x300
1890 #define _ICL_PORT_PCS_GRP 0x600
1891 #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
1892 #define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
1893 _ICL_PORT_PCS_AUX + 4 * (dw))
1894 #define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
1895 _ICL_PORT_PCS_GRP + 4 * (dw))
1896 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1897 _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1898 #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1899 #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
1900 #define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
1901 #define COMMON_KEEPER_EN (1 << 26)
1902 #define LATENCY_OPTIM_MASK (0x3 << 2)
1903 #define LATENCY_OPTIM_VAL(x) ((x) << 2)
1905 /* CNL/ICL Port TX registers */
1906 #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
1907 #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
1908 #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
1909 #define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
1910 #define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
1911 #define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
1912 #define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
1913 #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
1914 #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
1915 #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
1916 #define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
1917 _CNL_PORT_TX_AE_GRP_OFFSET, \
1918 _CNL_PORT_TX_B_GRP_OFFSET, \
1919 _CNL_PORT_TX_B_GRP_OFFSET, \
1920 _CNL_PORT_TX_D_GRP_OFFSET, \
1921 _CNL_PORT_TX_AE_GRP_OFFSET, \
1922 _CNL_PORT_TX_F_GRP_OFFSET) + \
1924 #define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
1925 _CNL_PORT_TX_AE_LN0_OFFSET, \
1926 _CNL_PORT_TX_B_LN0_OFFSET, \
1927 _CNL_PORT_TX_B_LN0_OFFSET, \
1928 _CNL_PORT_TX_D_LN0_OFFSET, \
1929 _CNL_PORT_TX_AE_LN0_OFFSET, \
1930 _CNL_PORT_TX_F_LN0_OFFSET) + \
1933 #define _ICL_PORT_TX_AUX 0x380
1934 #define _ICL_PORT_TX_GRP 0x680
1935 #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
1937 #define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
1938 _ICL_PORT_TX_AUX + 4 * (dw))
1939 #define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
1940 _ICL_PORT_TX_GRP + 4 * (dw))
1941 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1942 _ICL_PORT_TX_LN(ln) + 4 * (dw))
1944 #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
1945 #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
1946 #define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
1947 #define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
1948 #define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
1949 #define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
1950 #define SWING_SEL_UPPER_MASK (1 << 15)
1951 #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
1952 #define SWING_SEL_LOWER_MASK (0x7 << 11)
1953 #define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
1954 #define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
1955 #define RCOMP_SCALAR(x) ((x) << 0)
1956 #define RCOMP_SCALAR_MASK (0xFF << 0)
1958 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
1959 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
1960 #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
1961 #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
1962 #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
1963 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1964 _CNL_PORT_TX_DW4_LN0_AE)))
1965 #define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
1966 #define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
1967 #define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
1968 #define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
1969 #define LOADGEN_SELECT (1 << 31)
1970 #define POST_CURSOR_1(x) ((x) << 12)
1971 #define POST_CURSOR_1_MASK (0x3F << 12)
1972 #define POST_CURSOR_2(x) ((x) << 6)
1973 #define POST_CURSOR_2_MASK (0x3F << 6)
1974 #define CURSOR_COEFF(x) ((x) << 0)
1975 #define CURSOR_COEFF_MASK (0x3F << 0)
1977 #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
1978 #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
1979 #define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
1980 #define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
1981 #define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
1982 #define TX_TRAINING_EN (1 << 31)
1983 #define TAP2_DISABLE (1 << 30)
1984 #define TAP3_DISABLE (1 << 29)
1985 #define SCALING_MODE_SEL(x) ((x) << 18)
1986 #define SCALING_MODE_SEL_MASK (0x7 << 18)
1987 #define RTERM_SELECT(x) ((x) << 3)
1988 #define RTERM_SELECT_MASK (0x7 << 3)
1990 #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
1991 #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
1992 #define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
1993 #define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
1994 #define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
1995 #define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
1996 #define N_SCALAR(x) ((x) << 24)
1997 #define N_SCALAR_MASK (0x7F << 24)
1999 #define _ICL_DPHY_CHKN_REG 0x194
2000 #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
2001 #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
2003 #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
2004 _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2006 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
2007 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
2008 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
2009 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
2010 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
2011 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
2012 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
2013 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
2014 #define MG_TX1_LINK_PARAMS(ln, port) \
2015 MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2016 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
2017 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
2019 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
2020 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
2021 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
2022 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
2023 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
2024 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
2025 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
2026 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
2027 #define MG_TX2_LINK_PARAMS(ln, port) \
2028 MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2029 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
2030 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
2031 #define CRI_USE_FS32 (1 << 5)
2033 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
2034 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
2035 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
2036 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
2037 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
2038 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
2039 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
2040 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
2041 #define MG_TX1_PISO_READLOAD(ln, port) \
2042 MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2043 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2044 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2046 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
2047 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
2048 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
2049 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
2050 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
2051 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
2052 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
2053 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
2054 #define MG_TX2_PISO_READLOAD(ln, port) \
2055 MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2056 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2057 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
2058 #define CRI_CALCINIT (1 << 1)
2060 #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
2061 #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
2062 #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
2063 #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
2064 #define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
2065 #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
2066 #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
2067 #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
2068 #define MG_TX1_SWINGCTRL(ln, port) \
2069 MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2070 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2071 MG_TX_SWINGCTRL_TX1LN1_PORT1)
2073 #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
2074 #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
2075 #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
2076 #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
2077 #define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
2078 #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
2079 #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
2080 #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
2081 #define MG_TX2_SWINGCTRL(ln, port) \
2082 MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2083 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2084 MG_TX_SWINGCTRL_TX2LN1_PORT1)
2085 #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
2086 #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
2088 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
2089 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
2090 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
2091 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
2092 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
2093 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
2094 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
2095 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
2096 #define MG_TX1_DRVCTRL(ln, port) \
2097 MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2098 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2099 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
2101 #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
2102 #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
2103 #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
2104 #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
2105 #define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
2106 #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
2107 #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
2108 #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
2109 #define MG_TX2_DRVCTRL(ln, port) \
2110 MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2111 MG_TX_DRVCTRL_TX2LN0_PORT2, \
2112 MG_TX_DRVCTRL_TX2LN1_PORT1)
2113 #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
2114 #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
2115 #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
2116 #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
2117 #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
2118 #define CRI_LOADGEN_SEL(x) ((x) << 12)
2119 #define CRI_LOADGEN_SEL_MASK (0x3 << 12)
2121 #define MG_CLKHUB_LN0_PORT1 0x16839C
2122 #define MG_CLKHUB_LN1_PORT1 0x16879C
2123 #define MG_CLKHUB_LN0_PORT2 0x16939C
2124 #define MG_CLKHUB_LN1_PORT2 0x16979C
2125 #define MG_CLKHUB_LN0_PORT3 0x16A39C
2126 #define MG_CLKHUB_LN1_PORT3 0x16A79C
2127 #define MG_CLKHUB_LN0_PORT4 0x16B39C
2128 #define MG_CLKHUB_LN1_PORT4 0x16B79C
2129 #define MG_CLKHUB(ln, port) \
2130 MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \
2131 MG_CLKHUB_LN0_PORT2, \
2132 MG_CLKHUB_LN1_PORT1)
2133 #define CFG_LOW_RATE_LKREN_EN (1 << 11)
2135 #define MG_TX_DCC_TX1LN0_PORT1 0x168110
2136 #define MG_TX_DCC_TX1LN1_PORT1 0x168510
2137 #define MG_TX_DCC_TX1LN0_PORT2 0x169110
2138 #define MG_TX_DCC_TX1LN1_PORT2 0x169510
2139 #define MG_TX_DCC_TX1LN0_PORT3 0x16A110
2140 #define MG_TX_DCC_TX1LN1_PORT3 0x16A510
2141 #define MG_TX_DCC_TX1LN0_PORT4 0x16B110
2142 #define MG_TX_DCC_TX1LN1_PORT4 0x16B510
2143 #define MG_TX1_DCC(ln, port) \
2144 MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \
2145 MG_TX_DCC_TX1LN0_PORT2, \
2146 MG_TX_DCC_TX1LN1_PORT1)
2147 #define MG_TX_DCC_TX2LN0_PORT1 0x168090
2148 #define MG_TX_DCC_TX2LN1_PORT1 0x168490
2149 #define MG_TX_DCC_TX2LN0_PORT2 0x169090
2150 #define MG_TX_DCC_TX2LN1_PORT2 0x169490
2151 #define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2152 #define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2153 #define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2154 #define MG_TX_DCC_TX2LN1_PORT4 0x16B490
2155 #define MG_TX2_DCC(ln, port) \
2156 MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \
2157 MG_TX_DCC_TX2LN0_PORT2, \
2158 MG_TX_DCC_TX2LN1_PORT1)
2159 #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2160 #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2161 #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
2163 #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2164 #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2165 #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2166 #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2167 #define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2168 #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2169 #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2170 #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
2171 #define MG_DP_MODE(ln, port) \
2172 MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \
2173 MG_DP_MODE_LN0_ACU_PORT2, \
2174 MG_DP_MODE_LN1_ACU_PORT1)
2175 #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2176 #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2177 #define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
2178 #define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4)
2179 #define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
2180 #define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
2181 #define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
2183 #define MG_MISC_SUS0_PORT1 0x168814
2184 #define MG_MISC_SUS0_PORT2 0x169814
2185 #define MG_MISC_SUS0_PORT3 0x16A814
2186 #define MG_MISC_SUS0_PORT4 0x16B814
2187 #define MG_MISC_SUS0(tc_port) \
2188 _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
2189 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14)
2190 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14)
2191 #define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12)
2192 #define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11)
2193 #define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10)
2194 #define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7)
2195 #define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6)
2196 #define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5)
2198 /* The spec defines this only for BXT PHY0, but lets assume that this
2199 * would exist for PHY1 too if it had a second channel.
2201 #define _PORT_CL2CM_DW6_A 0x162358
2202 #define _PORT_CL2CM_DW6_BC 0x6C358
2203 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2204 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2206 #define FIA1_BASE 0x163000
2207 #define FIA2_BASE 0x16E000
2208 #define FIA3_BASE 0x16F000
2209 #define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2210 #define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
2212 /* ICL PHY DFLEX registers */
2213 #define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
2214 #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
2215 #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
2216 #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
2217 #define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
2218 #define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
2219 #define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
2221 /* BXT PHY Ref registers */
2222 #define _PORT_REF_DW3_A 0x16218C
2223 #define _PORT_REF_DW3_BC 0x6C18C
2224 #define GRC_DONE (1 << 22)
2225 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2227 #define _PORT_REF_DW6_A 0x162198
2228 #define _PORT_REF_DW6_BC 0x6C198
2229 #define GRC_CODE_SHIFT 24
2230 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2231 #define GRC_CODE_FAST_SHIFT 16
2232 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2233 #define GRC_CODE_SLOW_SHIFT 8
2234 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2235 #define GRC_CODE_NOM_MASK 0xFF
2236 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2238 #define _PORT_REF_DW8_A 0x1621A0
2239 #define _PORT_REF_DW8_BC 0x6C1A0
2240 #define GRC_DIS (1 << 15)
2241 #define GRC_RDY_OVRD (1 << 1)
2242 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2244 /* BXT PHY PCS registers */
2245 #define _PORT_PCS_DW10_LN01_A 0x162428
2246 #define _PORT_PCS_DW10_LN01_B 0x6C428
2247 #define _PORT_PCS_DW10_LN01_C 0x6C828
2248 #define _PORT_PCS_DW10_GRP_A 0x162C28
2249 #define _PORT_PCS_DW10_GRP_B 0x6CC28
2250 #define _PORT_PCS_DW10_GRP_C 0x6CE28
2251 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2252 _PORT_PCS_DW10_LN01_B, \
2253 _PORT_PCS_DW10_LN01_C)
2254 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2255 _PORT_PCS_DW10_GRP_B, \
2256 _PORT_PCS_DW10_GRP_C)
2258 #define TX2_SWING_CALC_INIT (1 << 31)
2259 #define TX1_SWING_CALC_INIT (1 << 30)
2261 #define _PORT_PCS_DW12_LN01_A 0x162430
2262 #define _PORT_PCS_DW12_LN01_B 0x6C430
2263 #define _PORT_PCS_DW12_LN01_C 0x6C830
2264 #define _PORT_PCS_DW12_LN23_A 0x162630
2265 #define _PORT_PCS_DW12_LN23_B 0x6C630
2266 #define _PORT_PCS_DW12_LN23_C 0x6CA30
2267 #define _PORT_PCS_DW12_GRP_A 0x162c30
2268 #define _PORT_PCS_DW12_GRP_B 0x6CC30
2269 #define _PORT_PCS_DW12_GRP_C 0x6CE30
2270 #define LANESTAGGER_STRAP_OVRD (1 << 6)
2271 #define LANE_STAGGER_MASK 0x1F
2272 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2273 _PORT_PCS_DW12_LN01_B, \
2274 _PORT_PCS_DW12_LN01_C)
2275 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2276 _PORT_PCS_DW12_LN23_B, \
2277 _PORT_PCS_DW12_LN23_C)
2278 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2279 _PORT_PCS_DW12_GRP_B, \
2280 _PORT_PCS_DW12_GRP_C)
2282 /* BXT PHY TX registers */
2283 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2284 ((lane) & 1) * 0x80)
2286 #define _PORT_TX_DW2_LN0_A 0x162508
2287 #define _PORT_TX_DW2_LN0_B 0x6C508
2288 #define _PORT_TX_DW2_LN0_C 0x6C908
2289 #define _PORT_TX_DW2_GRP_A 0x162D08
2290 #define _PORT_TX_DW2_GRP_B 0x6CD08
2291 #define _PORT_TX_DW2_GRP_C 0x6CF08
2292 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2293 _PORT_TX_DW2_LN0_B, \
2295 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2296 _PORT_TX_DW2_GRP_B, \
2298 #define MARGIN_000_SHIFT 16
2299 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2300 #define UNIQ_TRANS_SCALE_SHIFT 8
2301 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2303 #define _PORT_TX_DW3_LN0_A 0x16250C
2304 #define _PORT_TX_DW3_LN0_B 0x6C50C
2305 #define _PORT_TX_DW3_LN0_C 0x6C90C
2306 #define _PORT_TX_DW3_GRP_A 0x162D0C
2307 #define _PORT_TX_DW3_GRP_B 0x6CD0C
2308 #define _PORT_TX_DW3_GRP_C 0x6CF0C
2309 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2310 _PORT_TX_DW3_LN0_B, \
2312 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2313 _PORT_TX_DW3_GRP_B, \
2315 #define SCALE_DCOMP_METHOD (1 << 26)
2316 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2318 #define _PORT_TX_DW4_LN0_A 0x162510
2319 #define _PORT_TX_DW4_LN0_B 0x6C510
2320 #define _PORT_TX_DW4_LN0_C 0x6C910
2321 #define _PORT_TX_DW4_GRP_A 0x162D10
2322 #define _PORT_TX_DW4_GRP_B 0x6CD10
2323 #define _PORT_TX_DW4_GRP_C 0x6CF10
2324 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2325 _PORT_TX_DW4_LN0_B, \
2327 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2328 _PORT_TX_DW4_GRP_B, \
2330 #define DEEMPH_SHIFT 24
2331 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2333 #define _PORT_TX_DW5_LN0_A 0x162514
2334 #define _PORT_TX_DW5_LN0_B 0x6C514
2335 #define _PORT_TX_DW5_LN0_C 0x6C914
2336 #define _PORT_TX_DW5_GRP_A 0x162D14
2337 #define _PORT_TX_DW5_GRP_B 0x6CD14
2338 #define _PORT_TX_DW5_GRP_C 0x6CF14
2339 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2340 _PORT_TX_DW5_LN0_B, \
2342 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2343 _PORT_TX_DW5_GRP_B, \
2345 #define DCC_DELAY_RANGE_1 (1 << 9)
2346 #define DCC_DELAY_RANGE_2 (1 << 8)
2348 #define _PORT_TX_DW14_LN0_A 0x162538
2349 #define _PORT_TX_DW14_LN0_B 0x6C538
2350 #define _PORT_TX_DW14_LN0_C 0x6C938
2351 #define LATENCY_OPTIM_SHIFT 30
2352 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2353 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2354 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2355 _PORT_TX_DW14_LN0_C) + \
2356 _BXT_LANE_OFFSET(lane))
2358 /* UAIMI scratch pad register 1 */
2359 #define UAIMI_SPR1 _MMIO(0x4F074)
2360 /* SKL VccIO mask */
2361 #define SKL_VCCIO_MASK 0x1
2362 /* SKL balance leg register */
2363 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2364 /* I_boost values */
2365 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
2366 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
2367 /* Balance leg disable bits */
2368 #define BALANCE_LEG_DISABLE_SHIFT 23
2369 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2373 * [0-7] @ 0x2000 gen2,gen3
2374 * [8-15] @ 0x3000 945,g33,pnv
2376 * [0-15] @ 0x3000 gen4,gen5
2378 * [0-15] @ 0x100000 gen6,vlv,chv
2379 * [0-31] @ 0x100000 gen7+
2381 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2382 #define I830_FENCE_START_MASK 0x07f80000
2383 #define I830_FENCE_TILING_Y_SHIFT 12
2384 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2385 #define I830_FENCE_PITCH_SHIFT 4
2386 #define I830_FENCE_REG_VALID (1 << 0)
2387 #define I915_FENCE_MAX_PITCH_VAL 4
2388 #define I830_FENCE_MAX_PITCH_VAL 6
2389 #define I830_FENCE_MAX_SIZE_VAL (1 << 8)
2391 #define I915_FENCE_START_MASK 0x0ff00000
2392 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2394 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2395 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2396 #define I965_FENCE_PITCH_SHIFT 2
2397 #define I965_FENCE_TILING_Y_SHIFT 1
2398 #define I965_FENCE_REG_VALID (1 << 0)
2399 #define I965_FENCE_MAX_PITCH_VAL 0x0400
2401 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2402 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2403 #define GEN6_FENCE_PITCH_SHIFT 32
2404 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2407 /* control register for cpu gtt access */
2408 #define TILECTL _MMIO(0x101000)
2409 #define TILECTL_SWZCTL (1 << 0)
2410 #define TILECTL_TLBPF (1 << 1)
2411 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2412 #define TILECTL_BACKSNOOP_DIS (1 << 3)
2415 * Instruction and interrupt control regs
2417 #define PGTBL_CTL _MMIO(0x02020)
2418 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2419 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2420 #define PGTBL_ER _MMIO(0x02024)
2421 #define PRB0_BASE (0x2030 - 0x30)
2422 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
2423 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
2424 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
2425 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
2426 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
2427 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
2428 #define RENDER_RING_BASE 0x02000
2429 #define BSD_RING_BASE 0x04000
2430 #define GEN6_BSD_RING_BASE 0x12000
2431 #define GEN8_BSD2_RING_BASE 0x1c000
2432 #define GEN11_BSD_RING_BASE 0x1c0000
2433 #define GEN11_BSD2_RING_BASE 0x1c4000
2434 #define GEN11_BSD3_RING_BASE 0x1d0000
2435 #define GEN11_BSD4_RING_BASE 0x1d4000
2436 #define VEBOX_RING_BASE 0x1a000
2437 #define GEN11_VEBOX_RING_BASE 0x1c8000
2438 #define GEN11_VEBOX2_RING_BASE 0x1d8000
2439 #define BLT_RING_BASE 0x22000
2440 #define RING_TAIL(base) _MMIO((base) + 0x30)
2441 #define RING_HEAD(base) _MMIO((base) + 0x34)
2442 #define RING_START(base) _MMIO((base) + 0x38)
2443 #define RING_CTL(base) _MMIO((base) + 0x3c)
2444 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2445 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
2446 #define RING_SYNC_1(base) _MMIO((base) + 0x44)
2447 #define RING_SYNC_2(base) _MMIO((base) + 0x48)
2448 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2449 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2450 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2451 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2452 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2453 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2454 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2455 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2456 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2457 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2458 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2459 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2460 #define GEN6_NOSYNC INVALID_MMIO_REG
2461 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
2462 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
2463 #define RING_HWS_PGA(base) _MMIO((base) + 0x80)
2464 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2465 #define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
2466 #define RESET_CTL_CAT_ERROR REG_BIT(2)
2467 #define RESET_CTL_READY_TO_RESET REG_BIT(1)
2468 #define RESET_CTL_REQUEST_RESET REG_BIT(0)
2470 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2472 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
2473 #define GTT_CACHE_EN_ALL 0xF0007FFF
2474 #define GEN7_WR_WATERMARK _MMIO(0x4028)
2475 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2476 #define ARB_MODE _MMIO(0x4030)
2477 #define ARB_MODE_SWIZZLE_SNB (1 << 4)
2478 #define ARB_MODE_SWIZZLE_IVB (1 << 5)
2479 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2480 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2481 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2482 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2483 #define GEN7_LRA_LIMITS_REG_NUM 13
2484 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2485 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2487 #define GAMTARBMODE _MMIO(0x04a08)
2488 #define ARB_MODE_BWGTLB_DISABLE (1 << 9)
2489 #define ARB_MODE_SWIZZLE_BDW (1 << 1)
2490 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2491 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2492 #define GEN8_RING_FAULT_REG _MMIO(0x4094)
2493 #define GEN12_RING_FAULT_REG _MMIO(0xcec4)
2494 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2495 #define RING_FAULT_GTTSEL_MASK (1 << 11)
2496 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2497 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2498 #define RING_FAULT_VALID (1 << 0)
2499 #define DONE_REG _MMIO(0x40b0)
2500 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2501 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2502 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
2503 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2504 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2505 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2506 #define RING_ACTHD(base) _MMIO((base) + 0x74)
2507 #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
2508 #define RING_NOPID(base) _MMIO((base) + 0x94)
2509 #define RING_IMR(base) _MMIO((base) + 0xa8)
2510 #define RING_HWSTAM(base) _MMIO((base) + 0x98)
2511 #define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
2512 #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
2513 #define TAIL_ADDR 0x001FFFF8
2514 #define HEAD_WRAP_COUNT 0xFFE00000
2515 #define HEAD_WRAP_ONE 0x00200000
2516 #define HEAD_ADDR 0x001FFFFC
2517 #define RING_NR_PAGES 0x001FF000
2518 #define RING_REPORT_MASK 0x00000006
2519 #define RING_REPORT_64K 0x00000002
2520 #define RING_REPORT_128K 0x00000004
2521 #define RING_NO_REPORT 0x00000000
2522 #define RING_VALID_MASK 0x00000001
2523 #define RING_VALID 0x00000001
2524 #define RING_INVALID 0x00000000
2525 #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
2526 #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
2527 #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
2529 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2530 #define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
2531 #define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
2532 #define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
2533 #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
2534 #define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
2535 #define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
2536 #define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
2537 #define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
2538 #define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
2539 #define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
2540 #define RING_FORCE_TO_NONPRIV_MASK_VALID \
2541 (RING_FORCE_TO_NONPRIV_RANGE_MASK \
2542 | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2543 #define RING_MAX_NONPRIV_SLOTS 12
2545 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2547 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2548 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
2550 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2551 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2552 #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
2554 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2555 #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
2556 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
2557 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
2560 #define PRB0_TAIL _MMIO(0x2030)
2561 #define PRB0_HEAD _MMIO(0x2034)
2562 #define PRB0_START _MMIO(0x2038)
2563 #define PRB0_CTL _MMIO(0x203c)
2564 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2565 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2566 #define PRB1_START _MMIO(0x2048) /* 915+ only */
2567 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */
2569 #define IPEIR_I965 _MMIO(0x2064)
2570 #define IPEHR_I965 _MMIO(0x2068)
2571 #define GEN7_SC_INSTDONE _MMIO(0x7100)
2572 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2573 #define GEN7_ROW_INSTDONE _MMIO(0xe164)
2574 #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2575 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2576 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2577 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2578 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2579 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2580 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2581 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2582 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
2583 #define RING_IPEIR(base) _MMIO((base) + 0x64)
2584 #define RING_IPEHR(base) _MMIO((base) + 0x68)
2586 * On GEN4, only the render ring INSTDONE exists and has a different
2587 * layout than the GEN7+ version.
2588 * The GEN2 counterpart of this register is GEN2_INSTDONE.
2590 #define RING_INSTDONE(base) _MMIO((base) + 0x6c)
2591 #define RING_INSTPS(base) _MMIO((base) + 0x70)
2592 #define RING_DMA_FADD(base) _MMIO((base) + 0x78)
2593 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2594 #define RING_INSTPM(base) _MMIO((base) + 0xc0)
2595 #define RING_MI_MODE(base) _MMIO((base) + 0x9c)
2596 #define INSTPS _MMIO(0x2070) /* 965+ only */
2597 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2598 #define ACTHD_I965 _MMIO(0x2074)
2599 #define HWS_PGA _MMIO(0x2080)
2600 #define HWS_ADDRESS_MASK 0xfffff000
2601 #define HWS_START_ADDRESS_SHIFT 4
2602 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2603 #define PWRCTX_EN (1 << 0)
2604 #define IPEIR(base) _MMIO((base) + 0x88)
2605 #define IPEHR(base) _MMIO((base) + 0x8c)
2606 #define GEN2_INSTDONE _MMIO(0x2090)
2607 #define NOPID _MMIO(0x2094)
2608 #define HWSTAM _MMIO(0x2098)
2609 #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
2610 #define RING_BBSTATE(base) _MMIO((base) + 0x110)
2611 #define RING_BB_PPGTT (1 << 5)
2612 #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
2613 #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
2614 #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
2615 #define RING_BBADDR(base) _MMIO((base) + 0x140)
2616 #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
2617 #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
2618 #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
2619 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
2620 #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
2622 #define ERROR_GEN6 _MMIO(0x40a0)
2623 #define GEN7_ERR_INT _MMIO(0x44040)
2624 #define ERR_INT_POISON (1 << 31)
2625 #define ERR_INT_MMIO_UNCLAIMED (1 << 13)
2626 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
2627 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
2628 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
2629 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
2630 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
2631 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
2632 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
2633 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
2635 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2636 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2637 #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
2638 #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
2639 #define FAULT_VA_HIGH_BITS (0xf << 0)
2640 #define FAULT_GTT_SEL (1 << 4)
2642 #define FPGA_DBG _MMIO(0x42300)
2643 #define FPGA_DBG_RM_NOCLAIM (1 << 31)
2645 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2646 #define CLAIM_ER_CLR (1 << 31)
2647 #define CLAIM_ER_OVERFLOW (1 << 16)
2648 #define CLAIM_ER_CTR_MASK 0xffff
2650 #define DERRMR _MMIO(0x44050)
2651 /* Note that HBLANK events are reserved on bdw+ */
2652 #define DERRMR_PIPEA_SCANLINE (1 << 0)
2653 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
2654 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
2655 #define DERRMR_PIPEA_VBLANK (1 << 3)
2656 #define DERRMR_PIPEA_HBLANK (1 << 5)
2657 #define DERRMR_PIPEB_SCANLINE (1 << 8)
2658 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
2659 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
2660 #define DERRMR_PIPEB_VBLANK (1 << 11)
2661 #define DERRMR_PIPEB_HBLANK (1 << 13)
2662 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2663 #define DERRMR_PIPEC_SCANLINE (1 << 14)
2664 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
2665 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
2666 #define DERRMR_PIPEC_VBLANK (1 << 21)
2667 #define DERRMR_PIPEC_HBLANK (1 << 22)
2670 /* GM45+ chicken bits -- debug workaround bits that may be required
2671 * for various sorts of correct behavior. The top 16 bits of each are
2672 * the enables for writing to the corresponding low bit.
2674 #define _3D_CHICKEN _MMIO(0x2084)
2675 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2676 #define _3D_CHICKEN2 _MMIO(0x208c)
2678 #define FF_SLICE_CHICKEN _MMIO(0x2088)
2679 #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
2681 /* Disables pipelining of read flushes past the SF-WIZ interface.
2682 * Required on all Ironlake steppings according to the B-Spec, but the
2683 * particular danger of not doing so is not specified.
2685 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2686 #define _3D_CHICKEN3 _MMIO(0x2090)
2687 #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
2688 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2689 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2690 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2691 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
2692 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
2694 #define MI_MODE _MMIO(0x209c)
2695 # define VS_TIMER_DISPATCH (1 << 6)
2696 # define MI_FLUSH_ENABLE (1 << 12)
2697 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2698 # define MODE_IDLE (1 << 9)
2699 # define STOP_RING (1 << 8)
2701 #define GEN6_GT_MODE _MMIO(0x20d0)
2702 #define GEN7_GT_MODE _MMIO(0x7008)
2703 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2704 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2705 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2706 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2707 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2708 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2709 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2710 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2712 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2713 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2714 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2715 #define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2717 /* WaClearTdlStateAckDirtyBits */
2718 #define GEN8_STATE_ACK _MMIO(0x20F0)
2719 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2720 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2721 #define GEN9_STATE_ACK_TDL0 (1 << 12)
2722 #define GEN9_STATE_ACK_TDL1 (1 << 13)
2723 #define GEN9_STATE_ACK_TDL2 (1 << 14)
2724 #define GEN9_STATE_ACK_TDL3 (1 << 15)
2725 #define GEN9_SUBSLICE_TDL_ACK_BITS \
2726 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2727 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2729 #define GFX_MODE _MMIO(0x2520)
2730 #define GFX_MODE_GEN7 _MMIO(0x229c)
2731 #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
2732 #define GFX_RUN_LIST_ENABLE (1 << 15)
2733 #define GFX_INTERRUPT_STEERING (1 << 14)
2734 #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
2735 #define GFX_SURFACE_FAULT_ENABLE (1 << 12)
2736 #define GFX_REPLAY_MODE (1 << 11)
2737 #define GFX_PSMI_GRANULARITY (1 << 10)
2738 #define GFX_PPGTT_ENABLE (1 << 9)
2739 #define GEN8_GFX_PPGTT_48B (1 << 7)
2741 #define GFX_FORWARD_VBLANK_MASK (3 << 5)
2742 #define GFX_FORWARD_VBLANK_NEVER (0 << 5)
2743 #define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
2744 #define GFX_FORWARD_VBLANK_COND (2 << 5)
2746 #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2748 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2749 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2750 #define SCPD0 _MMIO(0x209c) /* 915+ only */
2751 #define GEN2_IER _MMIO(0x20a0)
2752 #define GEN2_IIR _MMIO(0x20a4)
2753 #define GEN2_IMR _MMIO(0x20a8)
2754 #define GEN2_ISR _MMIO(0x20ac)
2755 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2756 #define GINT_DIS (1 << 22)
2757 #define GCFG_DIS (1 << 8)
2758 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2759 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2760 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2761 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2762 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2763 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2764 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2765 #define VLV_PCBR_ADDR_SHIFT 12
2767 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2768 #define EIR _MMIO(0x20b0)
2769 #define EMR _MMIO(0x20b4)
2770 #define ESR _MMIO(0x20b8)
2771 #define GM45_ERROR_PAGE_TABLE (1 << 5)
2772 #define GM45_ERROR_MEM_PRIV (1 << 4)
2773 #define I915_ERROR_PAGE_TABLE (1 << 4)
2774 #define GM45_ERROR_CP_PRIV (1 << 3)
2775 #define I915_ERROR_MEMORY_REFRESH (1 << 1)
2776 #define I915_ERROR_INSTRUCTION (1 << 0)
2777 #define INSTPM _MMIO(0x20c0)
2778 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */
2779 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2780 will not assert AGPBUSY# and will only
2781 be delivered when out of C3. */
2782 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
2783 #define INSTPM_TLB_INVALIDATE (1 << 9)
2784 #define INSTPM_SYNC_FLUSH (1 << 5)
2785 #define ACTHD(base) _MMIO((base) + 0xc8)
2786 #define MEM_MODE _MMIO(0x20cc)
2787 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2788 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2789 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2790 #define FW_BLC _MMIO(0x20d8)
2791 #define FW_BLC2 _MMIO(0x20dc)
2792 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
2793 #define FW_BLC_SELF_EN_MASK (1 << 31)
2794 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
2795 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */
2796 #define MM_BURST_LENGTH 0x00700000
2797 #define MM_FIFO_WATERMARK 0x0001F000
2798 #define LM_BURST_LENGTH 0x00000700
2799 #define LM_FIFO_WATERMARK 0x0000001F
2800 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
2802 #define MBUS_ABOX_CTL _MMIO(0x45038)
2803 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2804 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2805 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
2806 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
2807 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
2808 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
2809 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
2810 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
2812 #define _PIPEA_MBUS_DBOX_CTL 0x7003C
2813 #define _PIPEB_MBUS_DBOX_CTL 0x7103C
2814 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2815 _PIPEB_MBUS_DBOX_CTL)
2816 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
2817 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
2818 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
2819 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
2820 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
2821 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
2823 #define MBUS_UBOX_CTL _MMIO(0x4503C)
2824 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2825 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
2827 /* Make render/texture TLB fetches lower priorty than associated data
2828 * fetches. This is not turned on by default
2830 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2832 /* Isoch request wait on GTT enable (Display A/B/C streams).
2833 * Make isoch requests stall on the TLB update. May cause
2834 * display underruns (test mode only)
2836 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2838 /* Block grant count for isoch requests when block count is
2839 * set to a finite value.
2841 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2842 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
2843 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
2844 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
2845 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
2847 /* Enable render writes to complete in C2/C3/C4 power states.
2848 * If this isn't enabled, render writes are prevented in low
2849 * power states. That seems bad to me.
2851 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2853 /* This acknowledges an async flip immediately instead
2854 * of waiting for 2TLB fetches.
2856 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2858 /* Enables non-sequential data reads through arbiter
2860 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
2862 /* Disable FSB snooping of cacheable write cycles from binner/render
2865 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2867 /* Arbiter time slice for non-isoch streams */
2868 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
2869 #define MI_ARB_TIME_SLICE_1 (0 << 5)
2870 #define MI_ARB_TIME_SLICE_2 (1 << 5)
2871 #define MI_ARB_TIME_SLICE_4 (2 << 5)
2872 #define MI_ARB_TIME_SLICE_6 (3 << 5)
2873 #define MI_ARB_TIME_SLICE_8 (4 << 5)
2874 #define MI_ARB_TIME_SLICE_10 (5 << 5)
2875 #define MI_ARB_TIME_SLICE_14 (6 << 5)
2876 #define MI_ARB_TIME_SLICE_16 (7 << 5)
2878 /* Low priority grace period page size */
2879 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
2880 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2882 /* Disable display A/B trickle feed */
2883 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2885 /* Set display plane priority */
2886 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
2887 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
2889 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
2890 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
2891 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
2893 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
2894 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
2895 #define CM0_IZ_OPT_DISABLE (1 << 6)
2896 #define CM0_ZR_OPT_DISABLE (1 << 5)
2897 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
2898 #define CM0_DEPTH_EVICT_DISABLE (1 << 4)
2899 #define CM0_COLOR_EVICT_DISABLE (1 << 3)
2900 #define CM0_DEPTH_WRITE_DISABLE (1 << 1)
2901 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
2902 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
2903 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
2904 #define GFX_FLSH_CNTL_EN (1 << 0)
2905 #define ECOSKPD _MMIO(0x21d0)
2906 #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
2907 #define ECO_GATING_CX_ONLY (1 << 3)
2908 #define ECO_FLIP_DONE (1 << 0)
2910 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
2911 #define RC_OP_FLUSH_ENABLE (1 << 0)
2912 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
2913 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
2914 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
2915 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
2916 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
2918 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
2919 #define GEN6_BLITTER_LOCK_SHIFT 16
2920 #define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
2922 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2923 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
2924 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2925 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
2927 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2928 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2930 #define GEN10_CACHE_MODE_SS _MMIO(0xe420)
2931 #define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
2933 /* Fuse readout registers for GT */
2934 #define HSW_PAVP_FUSE1 _MMIO(0x911C)
2935 #define HSW_F1_EU_DIS_SHIFT 16
2936 #define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT)
2937 #define HSW_F1_EU_DIS_10EUS 0
2938 #define HSW_F1_EU_DIS_8EUS 1
2939 #define HSW_F1_EU_DIS_6EUS 2
2941 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2942 #define CHV_FGT_DISABLE_SS0 (1 << 10)
2943 #define CHV_FGT_DISABLE_SS1 (1 << 11)
2944 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2945 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2946 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2947 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2948 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2949 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2950 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2951 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2953 #define GEN8_FUSE2 _MMIO(0x9120)
2954 #define GEN8_F2_SS_DIS_SHIFT 21
2955 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
2956 #define GEN8_F2_S_ENA_SHIFT 25
2957 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2959 #define GEN9_F2_SS_DIS_SHIFT 20
2960 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2962 #define GEN10_F2_S_ENA_SHIFT 22
2963 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
2964 #define GEN10_F2_SS_DIS_SHIFT 18
2965 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
2967 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
2968 #define GEN10_L3BANK_PAIR_COUNT 4
2969 #define GEN10_L3BANK_MASK 0x0F
2971 #define GEN8_EU_DISABLE0 _MMIO(0x9134)
2972 #define GEN8_EU_DIS0_S0_MASK 0xffffff
2973 #define GEN8_EU_DIS0_S1_SHIFT 24
2974 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2976 #define GEN8_EU_DISABLE1 _MMIO(0x9138)
2977 #define GEN8_EU_DIS1_S1_MASK 0xffff
2978 #define GEN8_EU_DIS1_S2_SHIFT 16
2979 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2981 #define GEN8_EU_DISABLE2 _MMIO(0x913c)
2982 #define GEN8_EU_DIS2_S2_MASK 0xff
2984 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
2986 #define GEN10_EU_DISABLE3 _MMIO(0x9140)
2987 #define GEN10_EU_DIS_SS_MASK 0xff
2989 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
2990 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff
2991 #define GEN11_GT_VEBOX_DISABLE_SHIFT 16
2992 #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
2994 #define GEN11_EU_DISABLE _MMIO(0x9134)
2995 #define GEN11_EU_DIS_MASK 0xFF
2997 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
2998 #define GEN11_GT_S_ENA_MASK 0xFF
3000 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3002 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
3003 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
3004 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
3005 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
3006 #define GEN6_BSD_GO_INDICATOR (1 << 4)
3008 /* On modern GEN architectures interrupt control consists of two sets
3009 * of registers. The first set pertains to the ring generating the
3010 * interrupt. The second control is for the functional block generating the
3011 * interrupt. These are PM, GT, DE, etc.
3013 * Luckily *knocks on wood* all the ring interrupt bits match up with the
3014 * GT interrupt bits, so we don't need to duplicate the defines.
3016 * These defines should cover us well from SNB->HSW with minor exceptions
3017 * it can also work on ILK.
3019 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
3020 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
3021 #define GT_BLT_USER_INTERRUPT (1 << 22)
3022 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
3023 #define GT_BSD_USER_INTERRUPT (1 << 12)
3024 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
3025 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
3026 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
3027 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
3028 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
3029 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
3030 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
3031 #define GT_RENDER_USER_INTERRUPT (1 << 0)
3033 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
3034 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
3036 #define GT_PARITY_ERROR(dev_priv) \
3037 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
3038 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3040 /* These are all the "old" interrupts */
3041 #define ILK_BSD_USER_INTERRUPT (1 << 5)
3043 #define I915_PM_INTERRUPT (1 << 31)
3044 #define I915_ISP_INTERRUPT (1 << 22)
3045 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
3046 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
3047 #define I915_MIPIC_INTERRUPT (1 << 19)
3048 #define I915_MIPIA_INTERRUPT (1 << 18)
3049 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
3050 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
3051 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
3052 #define I915_MASTER_ERROR_INTERRUPT (1 << 15)
3053 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
3054 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
3055 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
3056 #define I915_HWB_OOM_INTERRUPT (1 << 13)
3057 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
3058 #define I915_SYNC_STATUS_INTERRUPT (1 << 12)
3059 #define I915_MISC_INTERRUPT (1 << 11)
3060 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
3061 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
3062 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
3063 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
3064 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
3065 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
3066 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
3067 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
3068 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
3069 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
3070 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
3071 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
3072 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
3073 #define I915_DEBUG_INTERRUPT (1 << 2)
3074 #define I915_WINVALID_INTERRUPT (1 << 1)
3075 #define I915_USER_INTERRUPT (1 << 1)
3076 #define I915_ASLE_INTERRUPT (1 << 0)
3077 #define I915_BSD_USER_INTERRUPT (1 << 25)
3079 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
3080 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
3082 /* DisplayPort Audio w/ LPE */
3083 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
3084 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
3086 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
3087 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
3088 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
3089 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
3090 _VLV_AUD_PORT_EN_B_DBG, \
3091 _VLV_AUD_PORT_EN_C_DBG, \
3092 _VLV_AUD_PORT_EN_D_DBG)
3093 #define VLV_AMP_MUTE (1 << 1)
3095 #define GEN6_BSD_RNCID _MMIO(0x12198)
3097 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
3098 #define GEN7_FF_SCHED_MASK 0x0077070
3099 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
3100 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
3101 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
3102 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
3103 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
3104 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
3105 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
3106 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
3107 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
3108 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
3109 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
3110 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
3111 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
3112 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
3115 * Framebuffer compression (915+ only)
3118 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
3119 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
3120 #define FBC_CONTROL _MMIO(0x3208)
3121 #define FBC_CTL_EN (1 << 31)
3122 #define FBC_CTL_PERIODIC (1 << 30)
3123 #define FBC_CTL_INTERVAL_SHIFT (16)
3124 #define FBC_CTL_UNCOMPRESSIBLE (1 << 14)
3125 #define FBC_CTL_C3_IDLE (1 << 13)
3126 #define FBC_CTL_STRIDE_SHIFT (5)
3127 #define FBC_CTL_FENCENO_SHIFT (0)
3128 #define FBC_COMMAND _MMIO(0x320c)
3129 #define FBC_CMD_COMPRESS (1 << 0)
3130 #define FBC_STATUS _MMIO(0x3210)
3131 #define FBC_STAT_COMPRESSING (1 << 31)
3132 #define FBC_STAT_COMPRESSED (1 << 30)
3133 #define FBC_STAT_MODIFIED (1 << 29)
3134 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
3135 #define FBC_CONTROL2 _MMIO(0x3214)
3136 #define FBC_CTL_FENCE_DBL (0 << 4)
3137 #define FBC_CTL_IDLE_IMM (0 << 2)
3138 #define FBC_CTL_IDLE_FULL (1 << 2)
3139 #define FBC_CTL_IDLE_LINE (2 << 2)
3140 #define FBC_CTL_IDLE_DEBUG (3 << 2)
3141 #define FBC_CTL_CPU_FENCE (1 << 1)
3142 #define FBC_CTL_PLANE(plane) ((plane) << 0)
3143 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
3144 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
3146 #define FBC_LL_SIZE (1536)
3148 #define FBC_LLC_READ_CTRL _MMIO(0x9044)
3149 #define FBC_LLC_FULLY_OPEN (1 << 30)
3151 /* Framebuffer compression for GM45+ */
3152 #define DPFC_CB_BASE _MMIO(0x3200)
3153 #define DPFC_CONTROL _MMIO(0x3208)
3154 #define DPFC_CTL_EN (1 << 31)
3155 #define DPFC_CTL_PLANE(plane) ((plane) << 30)
3156 #define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29)
3157 #define DPFC_CTL_FENCE_EN (1 << 29)
3158 #define IVB_DPFC_CTL_FENCE_EN (1 << 28)
3159 #define DPFC_CTL_PERSISTENT_MODE (1 << 25)
3160 #define DPFC_SR_EN (1 << 10)
3161 #define DPFC_CTL_LIMIT_1X (0 << 6)
3162 #define DPFC_CTL_LIMIT_2X (1 << 6)
3163 #define DPFC_CTL_LIMIT_4X (2 << 6)
3164 #define DPFC_RECOMP_CTL _MMIO(0x320c)
3165 #define DPFC_RECOMP_STALL_EN (1 << 27)
3166 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
3167 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3168 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3169 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3170 #define DPFC_STATUS _MMIO(0x3210)
3171 #define DPFC_INVAL_SEG_SHIFT (16)
3172 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
3173 #define DPFC_COMP_SEG_SHIFT (0)
3174 #define DPFC_COMP_SEG_MASK (0x000007ff)
3175 #define DPFC_STATUS2 _MMIO(0x3214)
3176 #define DPFC_FENCE_YOFF _MMIO(0x3218)
3177 #define DPFC_CHICKEN _MMIO(0x3224)
3178 #define DPFC_HT_MODIFY (1 << 31)
3180 /* Framebuffer compression for Ironlake */
3181 #define ILK_DPFC_CB_BASE _MMIO(0x43200)
3182 #define ILK_DPFC_CONTROL _MMIO(0x43208)
3183 #define FBC_CTL_FALSE_COLOR (1 << 10)
3184 /* The bit 28-8 is reserved */
3185 #define DPFC_RESERVED (0x1FFFFF00)
3186 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3187 #define ILK_DPFC_STATUS _MMIO(0x43210)
3188 #define ILK_DPFC_COMP_SEG_MASK 0x7ff
3189 #define IVB_FBC_STATUS2 _MMIO(0x43214)
3190 #define IVB_FBC_COMP_SEG_MASK 0x7ff
3191 #define BDW_FBC_COMP_SEG_MASK 0xfff
3192 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3193 #define ILK_DPFC_CHICKEN _MMIO(0x43224)
3194 #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3195 #define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14)
3196 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
3197 #define ILK_FBC_RT_BASE _MMIO(0x2128)
3198 #define ILK_FBC_RT_VALID (1 << 0)
3199 #define SNB_FBC_FRONT_BUFFER (1 << 1)
3201 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3202 #define ILK_FBCQ_DIS (1 << 22)
3203 #define ILK_PABSTRETCH_DIS (1 << 21)
3207 * Framebuffer compression for Sandybridge
3209 * The following two registers are of type GTTMMADR
3211 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
3212 #define SNB_CPU_FENCE_ENABLE (1 << 29)
3213 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3215 /* Framebuffer compression for Ivybridge */
3216 #define IVB_FBC_RT_BASE _MMIO(0x7020)
3218 #define IPS_CTL _MMIO(0x43408)
3219 #define IPS_ENABLE (1 << 31)
3221 #define MSG_FBC_REND_STATE _MMIO(0x50380)
3222 #define FBC_REND_NUKE (1 << 2)
3223 #define FBC_REND_CACHE_CLEAN (1 << 1)
3228 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3231 # define GPIO_CLOCK_DIR_MASK (1 << 0)
3232 # define GPIO_CLOCK_DIR_IN (0 << 1)
3233 # define GPIO_CLOCK_DIR_OUT (1 << 1)
3234 # define GPIO_CLOCK_VAL_MASK (1 << 2)
3235 # define GPIO_CLOCK_VAL_OUT (1 << 3)
3236 # define GPIO_CLOCK_VAL_IN (1 << 4)
3237 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3238 # define GPIO_DATA_DIR_MASK (1 << 8)
3239 # define GPIO_DATA_DIR_IN (0 << 9)
3240 # define GPIO_DATA_DIR_OUT (1 << 9)
3241 # define GPIO_DATA_VAL_MASK (1 << 10)
3242 # define GPIO_DATA_VAL_OUT (1 << 11)
3243 # define GPIO_DATA_VAL_IN (1 << 12)
3244 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3246 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3247 #define GMBUS_AKSV_SELECT (1 << 11)
3248 #define GMBUS_RATE_100KHZ (0 << 8)
3249 #define GMBUS_RATE_50KHZ (1 << 8)
3250 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */
3251 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
3252 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
3253 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3254 #define GMBUS_PIN_DISABLED 0
3255 #define GMBUS_PIN_SSC 1
3256 #define GMBUS_PIN_VGADDC 2
3257 #define GMBUS_PIN_PANEL 3
3258 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
3259 #define GMBUS_PIN_DPC 4 /* HDMIC */
3260 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
3261 #define GMBUS_PIN_DPD 6 /* HDMID */
3262 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */
3263 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
3264 #define GMBUS_PIN_2_BXT 2
3265 #define GMBUS_PIN_3_BXT 3
3266 #define GMBUS_PIN_4_CNP 4
3267 #define GMBUS_PIN_9_TC1_ICP 9
3268 #define GMBUS_PIN_10_TC2_ICP 10
3269 #define GMBUS_PIN_11_TC3_ICP 11
3270 #define GMBUS_PIN_12_TC4_ICP 12
3271 #define GMBUS_PIN_13_TC5_TGP 13
3272 #define GMBUS_PIN_14_TC6_TGP 14
3274 #define GMBUS_NUM_PINS 15 /* including 0 */
3275 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3276 #define GMBUS_SW_CLR_INT (1 << 31)
3277 #define GMBUS_SW_RDY (1 << 30)
3278 #define GMBUS_ENT (1 << 29) /* enable timeout */
3279 #define GMBUS_CYCLE_NONE (0 << 25)
3280 #define GMBUS_CYCLE_WAIT (1 << 25)
3281 #define GMBUS_CYCLE_INDEX (2 << 25)
3282 #define GMBUS_CYCLE_STOP (4 << 25)
3283 #define GMBUS_BYTE_COUNT_SHIFT 16
3284 #define GMBUS_BYTE_COUNT_MAX 256U
3285 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U
3286 #define GMBUS_SLAVE_INDEX_SHIFT 8
3287 #define GMBUS_SLAVE_ADDR_SHIFT 1
3288 #define GMBUS_SLAVE_READ (1 << 0)
3289 #define GMBUS_SLAVE_WRITE (0 << 0)
3290 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3291 #define GMBUS_INUSE (1 << 15)
3292 #define GMBUS_HW_WAIT_PHASE (1 << 14)
3293 #define GMBUS_STALL_TIMEOUT (1 << 13)
3294 #define GMBUS_INT (1 << 12)
3295 #define GMBUS_HW_RDY (1 << 11)
3296 #define GMBUS_SATOER (1 << 10)
3297 #define GMBUS_ACTIVE (1 << 9)
3298 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3299 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3300 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3301 #define GMBUS_NAK_EN (1 << 3)
3302 #define GMBUS_IDLE_EN (1 << 2)
3303 #define GMBUS_HW_WAIT_EN (1 << 1)
3304 #define GMBUS_HW_RDY_EN (1 << 0)
3305 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3306 #define GMBUS_2BYTE_INDEX_EN (1 << 31)
3309 * Clock control & power management
3311 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3312 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3313 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3314 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3316 #define VGA0 _MMIO(0x6000)
3317 #define VGA1 _MMIO(0x6004)
3318 #define VGA_PD _MMIO(0x6010)
3319 #define VGA0_PD_P2_DIV_4 (1 << 7)
3320 #define VGA0_PD_P1_DIV_2 (1 << 5)
3321 #define VGA0_PD_P1_SHIFT 0
3322 #define VGA0_PD_P1_MASK (0x1f << 0)
3323 #define VGA1_PD_P2_DIV_4 (1 << 15)
3324 #define VGA1_PD_P1_DIV_2 (1 << 13)
3325 #define VGA1_PD_P1_SHIFT 8
3326 #define VGA1_PD_P1_MASK (0x1f << 8)
3327 #define DPLL_VCO_ENABLE (1 << 31)
3328 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
3329 #define DPLL_DVO_2X_MODE (1 << 30)
3330 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3331 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
3332 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3333 #define DPLL_VGA_MODE_DIS (1 << 28)
3334 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3335 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3336 #define DPLL_MODE_MASK (3 << 26)
3337 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3338 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3339 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3340 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3341 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3342 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
3343 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
3344 #define DPLL_LOCK_VLV (1 << 15)
3345 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
3346 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
3347 #define DPLL_SSC_REF_CLK_CHV (1 << 13)
3348 #define DPLL_PORTC_READY_MASK (0xf << 4)
3349 #define DPLL_PORTB_READY_MASK (0xf)
3351 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3353 /* Additional CHV pll/phy registers */
3354 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3355 #define DPLL_PORTD_READY_MASK (0xf)
3356 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3357 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
3358 #define PHY_LDO_DELAY_0NS 0x0
3359 #define PHY_LDO_DELAY_200NS 0x1
3360 #define PHY_LDO_DELAY_600NS 0x2
3361 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
3362 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3363 #define PHY_CH_SU_PSR 0x1
3364 #define PHY_CH_DEEP_PSR 0x7
3365 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
3366 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3367 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3368 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3369 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3370 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3373 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3374 * this field (only one bit may be set).
3376 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3377 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3378 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3379 /* i830, required in DVO non-gang */
3380 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
3381 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3382 #define PLL_REF_INPUT_DREFCLK (0 << 13)
3383 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3384 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3385 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3386 #define PLL_REF_INPUT_MASK (3 << 13)
3387 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
3389 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3390 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3391 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
3392 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3393 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3396 * Parallel to Serial Load Pulse phase selection.
3397 * Selects the phase for the 10X DPLL clock for the PCIe
3398 * digital display port. The range is 4 to 13; 10 or more
3399 * is just a flip delay. The default is 6
3401 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3402 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3404 * SDVO multiplier for 945G/GM. Not used on 965.
3406 #define SDVO_MULTIPLIER_MASK 0x000000ff
3407 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
3408 #define SDVO_MULTIPLIER_SHIFT_VGA 0
3410 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3411 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3412 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3413 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3416 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3418 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3420 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3421 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
3422 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3423 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3424 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3426 * SDVO/UDI pixel multiplier.
3428 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3429 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3430 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3431 * dummy bytes in the datastream at an increased clock rate, with both sides of
3432 * the link knowing how many bytes are fill.
3434 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3435 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3436 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3437 * through an SDVO command.
3439 * This register field has values of multiplication factor minus 1, with
3440 * a maximum multiplier of 5 for SDVO.
3442 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3443 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3445 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3446 * This best be set to the default value (3) or the CRT won't work. No,
3447 * I don't entirely understand what this does...
3449 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3450 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3452 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3454 #define _FPA0 0x6040
3455 #define _FPA1 0x6044
3456 #define _FPB0 0x6048
3457 #define _FPB1 0x604c
3458 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3459 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3460 #define FP_N_DIV_MASK 0x003f0000
3461 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3462 #define FP_N_DIV_SHIFT 16
3463 #define FP_M1_DIV_MASK 0x00003f00
3464 #define FP_M1_DIV_SHIFT 8
3465 #define FP_M2_DIV_MASK 0x0000003f
3466 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3467 #define FP_M2_DIV_SHIFT 0
3468 #define DPLL_TEST _MMIO(0x606c)
3469 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3470 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3471 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3472 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3473 #define DPLLB_TEST_N_BYPASS (1 << 19)
3474 #define DPLLB_TEST_M_BYPASS (1 << 18)
3475 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3476 #define DPLLA_TEST_N_BYPASS (1 << 3)
3477 #define DPLLA_TEST_M_BYPASS (1 << 2)
3478 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3479 #define D_STATE _MMIO(0x6104)
3480 #define DSTATE_GFX_RESET_I830 (1 << 6)
3481 #define DSTATE_PLL_D3_OFF (1 << 3)
3482 #define DSTATE_GFX_CLOCK_GATING (1 << 1)
3483 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
3484 #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3485 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3486 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3487 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3488 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3489 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3490 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3491 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
3492 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
3493 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3494 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3495 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3496 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3497 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3498 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3499 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3500 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3501 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3502 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3503 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3504 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3505 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3506 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3507 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3508 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3509 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3510 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3511 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3512 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3513 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3515 * This bit must be set on the 830 to prevent hangs when turning off the
3518 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3519 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3520 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3521 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3522 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3524 #define RENCLK_GATE_D1 _MMIO(0x6204)
3525 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3526 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3527 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3528 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3529 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3530 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3531 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3532 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3533 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
3534 /* This bit must be unset on 855,865 */
3535 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
3536 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3537 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
3538 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
3539 /* This bit must be set on 855,865. */
3540 # define SV_CLOCK_GATE_DISABLE (1 << 0)
3541 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3542 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3543 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3544 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3545 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3546 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3547 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3548 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3549 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3550 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3551 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3552 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3553 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3554 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3555 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3556 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3557 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3559 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3560 /* This bit must always be set on 965G/965GM */
3561 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3562 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3563 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3564 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3565 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3566 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3567 /* This bit must always be set on 965G */
3568 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3569 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3570 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3571 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3572 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3573 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3574 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3575 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3576 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3577 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3578 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3579 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3580 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3581 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3582 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3583 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3584 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3585 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3586 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3588 #define RENCLK_GATE_D2 _MMIO(0x6208)
3589 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3590 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3591 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3593 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
3594 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3596 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3597 #define DEUC _MMIO(0x6214) /* CRL only */
3599 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3600 #define FW_CSPWRDWNEN (1 << 15)
3602 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3604 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3605 #define CDCLK_FREQ_SHIFT 4
3606 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3607 #define CZCLK_FREQ_MASK 0xf
3609 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3610 #define PFI_CREDIT_63 (9 << 28) /* chv only */
3611 #define PFI_CREDIT_31 (8 << 28) /* chv only */
3612 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3613 #define PFI_CREDIT_RESEND (1 << 27)
3614 #define VGA_FAST_MODE_DISABLE (1 << 14)
3616 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3621 #define _PALETTE_A 0xa000
3622 #define _PALETTE_B 0xa800
3623 #define _CHV_PALETTE_C 0xc000
3624 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
3625 _PICK((pipe), _PALETTE_A, \
3626 _PALETTE_B, _CHV_PALETTE_C) + \
3629 /* MCH MMIO space */
3634 * This mirrors the MCHBAR MMIO space whose location is determined by
3635 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3636 * every way. It is not accessible from the CP register read instructions.
3638 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3641 #define MCHBAR_MIRROR_BASE 0x10000
3643 #define MCHBAR_MIRROR_BASE_SNB 0x140000
3645 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3646 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3647 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3648 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3649 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3651 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3652 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3654 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3655 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3656 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3657 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3658 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3659 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
3660 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3661 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3662 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3663 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3665 /* Pineview MCH register contains DDR3 setting */
3666 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3667 #define CSHRDDR3CTL_DDR3 (1 << 2)
3669 /* 965 MCH register controlling DRAM channel configuration */
3670 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3671 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3673 /* snb MCH registers for reading the DRAM channel configuration */
3674 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3675 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3676 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3677 #define MAD_DIMM_ECC_MASK (0x3 << 24)
3678 #define MAD_DIMM_ECC_OFF (0x0 << 24)
3679 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3680 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3681 #define MAD_DIMM_ECC_ON (0x3 << 24)
3682 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3683 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3684 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3685 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3686 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3687 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3688 #define MAD_DIMM_A_SELECT (0x1 << 16)
3689 /* DIMM sizes are in multiples of 256mb. */
3690 #define MAD_DIMM_B_SIZE_SHIFT 8
3691 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3692 #define MAD_DIMM_A_SIZE_SHIFT 0
3693 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3695 /* snb MCH registers for priority tuning */
3696 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3697 #define MCH_SSKPD_WM0_MASK 0x3f
3698 #define MCH_SSKPD_WM0_VAL 0xc
3700 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3702 /* Clocking configuration register */
3703 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3704 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
3705 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3706 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3707 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3708 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
3709 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
3710 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
3712 * Note that on at least on ELK the below value is reported for both
3713 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3714 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3716 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
3717 #define CLKCFG_FSB_MASK (7 << 0)
3718 #define CLKCFG_MEM_533 (1 << 4)
3719 #define CLKCFG_MEM_667 (2 << 4)
3720 #define CLKCFG_MEM_800 (3 << 4)
3721 #define CLKCFG_MEM_MASK (7 << 4)
3723 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3724 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3726 #define TSC1 _MMIO(0x11001)
3727 #define TSE (1 << 0)
3728 #define TR1 _MMIO(0x11006)
3729 #define TSFS _MMIO(0x11020)
3730 #define TSFS_SLOPE_MASK 0x0000ff00
3731 #define TSFS_SLOPE_SHIFT 8
3732 #define TSFS_INTR_MASK 0x000000ff
3734 #define CRSTANDVID _MMIO(0x11100)
3735 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3736 #define PXVFREQ_PX_MASK 0x7f000000
3737 #define PXVFREQ_PX_SHIFT 24
3738 #define VIDFREQ_BASE _MMIO(0x11110)
3739 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3740 #define VIDFREQ2 _MMIO(0x11114)
3741 #define VIDFREQ3 _MMIO(0x11118)
3742 #define VIDFREQ4 _MMIO(0x1111c)
3743 #define VIDFREQ_P0_MASK 0x1f000000
3744 #define VIDFREQ_P0_SHIFT 24
3745 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3746 #define VIDFREQ_P0_CSCLK_SHIFT 20
3747 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3748 #define VIDFREQ_P0_CRCLK_SHIFT 16
3749 #define VIDFREQ_P1_MASK 0x00001f00
3750 #define VIDFREQ_P1_SHIFT 8
3751 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3752 #define VIDFREQ_P1_CSCLK_SHIFT 4
3753 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3754 #define INTTOEXT_BASE_ILK _MMIO(0x11300)
3755 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3756 #define INTTOEXT_MAP3_SHIFT 24
3757 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3758 #define INTTOEXT_MAP2_SHIFT 16
3759 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3760 #define INTTOEXT_MAP1_SHIFT 8
3761 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3762 #define INTTOEXT_MAP0_SHIFT 0
3763 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
3764 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
3765 #define MEMCTL_CMD_MASK 0xe000
3766 #define MEMCTL_CMD_SHIFT 13
3767 #define MEMCTL_CMD_RCLK_OFF 0
3768 #define MEMCTL_CMD_RCLK_ON 1
3769 #define MEMCTL_CMD_CHFREQ 2
3770 #define MEMCTL_CMD_CHVID 3
3771 #define MEMCTL_CMD_VMMOFF 4
3772 #define MEMCTL_CMD_VMMON 5
3773 #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
3774 when command complete */
3775 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3776 #define MEMCTL_FREQ_SHIFT 8
3777 #define MEMCTL_SFCAVM (1 << 7)
3778 #define MEMCTL_TGT_VID_MASK 0x007f
3779 #define MEMIHYST _MMIO(0x1117c)
3780 #define MEMINTREN _MMIO(0x11180) /* 16 bits */
3781 #define MEMINT_RSEXIT_EN (1 << 8)
3782 #define MEMINT_CX_SUPR_EN (1 << 7)
3783 #define MEMINT_CONT_BUSY_EN (1 << 6)
3784 #define MEMINT_AVG_BUSY_EN (1 << 5)
3785 #define MEMINT_EVAL_CHG_EN (1 << 4)
3786 #define MEMINT_MON_IDLE_EN (1 << 3)
3787 #define MEMINT_UP_EVAL_EN (1 << 2)
3788 #define MEMINT_DOWN_EVAL_EN (1 << 1)
3789 #define MEMINT_SW_CMD_EN (1 << 0)
3790 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
3791 #define MEM_RSEXIT_MASK 0xc000
3792 #define MEM_RSEXIT_SHIFT 14
3793 #define MEM_CONT_BUSY_MASK 0x3000
3794 #define MEM_CONT_BUSY_SHIFT 12
3795 #define MEM_AVG_BUSY_MASK 0x0c00
3796 #define MEM_AVG_BUSY_SHIFT 10
3797 #define MEM_EVAL_CHG_MASK 0x0300
3798 #define MEM_EVAL_BUSY_SHIFT 8
3799 #define MEM_MON_IDLE_MASK 0x00c0
3800 #define MEM_MON_IDLE_SHIFT 6
3801 #define MEM_UP_EVAL_MASK 0x0030
3802 #define MEM_UP_EVAL_SHIFT 4
3803 #define MEM_DOWN_EVAL_MASK 0x000c
3804 #define MEM_DOWN_EVAL_SHIFT 2
3805 #define MEM_SW_CMD_MASK 0x0003
3806 #define MEM_INT_STEER_GFX 0
3807 #define MEM_INT_STEER_CMR 1
3808 #define MEM_INT_STEER_SMI 2
3809 #define MEM_INT_STEER_SCI 3
3810 #define MEMINTRSTS _MMIO(0x11184)
3811 #define MEMINT_RSEXIT (1 << 7)
3812 #define MEMINT_CONT_BUSY (1 << 6)
3813 #define MEMINT_AVG_BUSY (1 << 5)
3814 #define MEMINT_EVAL_CHG (1 << 4)
3815 #define MEMINT_MON_IDLE (1 << 3)
3816 #define MEMINT_UP_EVAL (1 << 2)
3817 #define MEMINT_DOWN_EVAL (1 << 1)
3818 #define MEMINT_SW_CMD (1 << 0)
3819 #define MEMMODECTL _MMIO(0x11190)
3820 #define MEMMODE_BOOST_EN (1 << 31)
3821 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3822 #define MEMMODE_BOOST_FREQ_SHIFT 24
3823 #define MEMMODE_IDLE_MODE_MASK 0x00030000
3824 #define MEMMODE_IDLE_MODE_SHIFT 16
3825 #define MEMMODE_IDLE_MODE_EVAL 0
3826 #define MEMMODE_IDLE_MODE_CONT 1
3827 #define MEMMODE_HWIDLE_EN (1 << 15)
3828 #define MEMMODE_SWMODE_EN (1 << 14)
3829 #define MEMMODE_RCLK_GATE (1 << 13)
3830 #define MEMMODE_HW_UPDATE (1 << 12)
3831 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3832 #define MEMMODE_FSTART_SHIFT 8
3833 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3834 #define MEMMODE_FMAX_SHIFT 4
3835 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3836 #define RCBMAXAVG _MMIO(0x1119c)
3837 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
3838 #define SWMEMCMD_RENDER_OFF (0 << 13)
3839 #define SWMEMCMD_RENDER_ON (1 << 13)
3840 #define SWMEMCMD_SWFREQ (2 << 13)
3841 #define SWMEMCMD_TARVID (3 << 13)
3842 #define SWMEMCMD_VRM_OFF (4 << 13)
3843 #define SWMEMCMD_VRM_ON (5 << 13)
3844 #define CMDSTS (1 << 12)
3845 #define SFCAVM (1 << 11)
3846 #define SWFREQ_MASK 0x0380 /* P0-7 */
3847 #define SWFREQ_SHIFT 7
3848 #define TARVID_MASK 0x001f
3849 #define MEMSTAT_CTG _MMIO(0x111a0)
3850 #define RCBMINAVG _MMIO(0x111a0)
3851 #define RCUPEI _MMIO(0x111b0)
3852 #define RCDNEI _MMIO(0x111b4)
3853 #define RSTDBYCTL _MMIO(0x111b8)
3854 #define RS1EN (1 << 31)
3855 #define RS2EN (1 << 30)
3856 #define RS3EN (1 << 29)
3857 #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */
3858 #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */
3859 #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */
3860 #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */
3861 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
3862 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
3863 #define RSX_STATUS_MASK (7 << 20)
3864 #define RSX_STATUS_ON (0 << 20)
3865 #define RSX_STATUS_RC1 (1 << 20)
3866 #define RSX_STATUS_RC1E (2 << 20)
3867 #define RSX_STATUS_RS1 (3 << 20)
3868 #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */
3869 #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */
3870 #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */
3871 #define RSX_STATUS_RSVD2 (7 << 20)
3872 #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */
3873 #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */
3874 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */
3875 #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */
3876 #define RS1CONTSAV_MASK (3 << 14)
3877 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
3878 #define RS1CONTSAV_RSVD (1 << 14)
3879 #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */
3880 #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */
3881 #define NORMSLEXLAT_MASK (3 << 12)
3882 #define SLOW_RS123 (0 << 12)
3883 #define SLOW_RS23 (1 << 12)
3884 #define SLOW_RS3 (2 << 12)
3885 #define NORMAL_RS123 (3 << 12)
3886 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
3887 #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3888 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3889 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
3890 #define RS_CSTATE_MASK (3 << 4)
3891 #define RS_CSTATE_C367_RS1 (0 << 4)
3892 #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3893 #define RS_CSTATE_RSVD (2 << 4)
3894 #define RS_CSTATE_C367_RS2 (3 << 4)
3895 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
3896 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
3897 #define VIDCTL _MMIO(0x111c0)
3898 #define VIDSTS _MMIO(0x111c8)
3899 #define VIDSTART _MMIO(0x111cc) /* 8 bits */
3900 #define MEMSTAT_ILK _MMIO(0x111f8)
3901 #define MEMSTAT_VID_MASK 0x7f00
3902 #define MEMSTAT_VID_SHIFT 8
3903 #define MEMSTAT_PSTATE_MASK 0x00f8
3904 #define MEMSTAT_PSTATE_SHIFT 3
3905 #define MEMSTAT_MON_ACTV (1 << 2)
3906 #define MEMSTAT_SRC_CTL_MASK 0x0003
3907 #define MEMSTAT_SRC_CTL_CORE 0
3908 #define MEMSTAT_SRC_CTL_TRB 1
3909 #define MEMSTAT_SRC_CTL_THM 2
3910 #define MEMSTAT_SRC_CTL_STDBY 3
3911 #define RCPREVBSYTUPAVG _MMIO(0x113b8)
3912 #define RCPREVBSYTDNAVG _MMIO(0x113bc)
3913 #define PMMISC _MMIO(0x11214)
3914 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
3915 #define SDEW _MMIO(0x1124c)
3916 #define CSIEW0 _MMIO(0x11250)
3917 #define CSIEW1 _MMIO(0x11254)
3918 #define CSIEW2 _MMIO(0x11258)
3919 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
3920 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
3921 #define MCHAFE _MMIO(0x112c0)
3922 #define CSIEC _MMIO(0x112e0)
3923 #define DMIEC _MMIO(0x112e4)
3924 #define DDREC _MMIO(0x112e8)
3925 #define PEG0EC _MMIO(0x112ec)
3926 #define PEG1EC _MMIO(0x112f0)
3927 #define GFXEC _MMIO(0x112f4)
3928 #define RPPREVBSYTUPAVG _MMIO(0x113b8)
3929 #define RPPREVBSYTDNAVG _MMIO(0x113bc)
3930 #define ECR _MMIO(0x11600)
3931 #define ECR_GPFE (1 << 31)
3932 #define ECR_IMONE (1 << 30)
3933 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
3934 #define OGW0 _MMIO(0x11608)
3935 #define OGW1 _MMIO(0x1160c)
3936 #define EG0 _MMIO(0x11610)
3937 #define EG1 _MMIO(0x11614)
3938 #define EG2 _MMIO(0x11618)
3939 #define EG3 _MMIO(0x1161c)
3940 #define EG4 _MMIO(0x11620)
3941 #define EG5 _MMIO(0x11624)
3942 #define EG6 _MMIO(0x11628)
3943 #define EG7 _MMIO(0x1162c)
3944 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
3945 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
3946 #define LCFUSE02 _MMIO(0x116c0)
3947 #define LCFUSE_HIV_MASK 0x000000ff
3948 #define CSIPLL0 _MMIO(0x12c10)
3949 #define DDRMPLL1 _MMIO(0X12c20)
3950 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
3952 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3953 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3955 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3956 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3957 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3958 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3959 #define BXT_RP_STATE_CAP _MMIO(0x138170)
3962 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3963 * 8300) freezing up around GPU hangs. Looks as if even
3964 * scheduling/timer interrupts start misbehaving if the RPS
3965 * EI/thresholds are "bad", leading to a very sluggish or even
3968 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
3969 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
3970 #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
3971 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3972 (IS_GEN9_LP(dev_priv) ? \
3973 INTERVAL_0_833_US(us) : \
3974 INTERVAL_1_33_US(us)) : \
3975 INTERVAL_1_28_US(us))
3977 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3978 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3979 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3980 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3981 (IS_GEN9_LP(dev_priv) ? \
3982 INTERVAL_0_833_TO_US(interval) : \
3983 INTERVAL_1_33_TO_US(interval)) : \
3984 INTERVAL_1_28_TO_US(interval))
3987 * Logical Context regs
3989 #define CCID(base) _MMIO((base) + 0x180)
3990 #define CCID_EN BIT(0)
3991 #define CCID_EXTENDED_STATE_RESTORE BIT(2)
3992 #define CCID_EXTENDED_STATE_SAVE BIT(3)
3994 * Notes on SNB/IVB/VLV context size:
3995 * - Power context is saved elsewhere (LLC or stolen)
3996 * - Ring/execlist context is saved on SNB, not on IVB
3997 * - Extended context size already includes render context size
3998 * - We always need to follow the extended context size.
3999 * SNB BSpec has comments indicating that we should use the
4000 * render context size instead if execlists are disabled, but
4001 * based on empirical testing that's just nonsense.
4002 * - Pipelined/VF state is saved on SNB/IVB respectively
4003 * - GT1 size just indicates how much of render context
4004 * doesn't need saving on GT1
4006 #define CXT_SIZE _MMIO(0x21a0)
4007 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
4008 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
4009 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
4010 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
4011 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
4012 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
4013 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
4014 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
4015 #define GEN7_CXT_SIZE _MMIO(0x21a8)
4016 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
4017 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
4018 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
4019 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
4020 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
4021 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
4022 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
4023 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
4026 INTEL_ADVANCED_CONTEXT = 0,
4027 INTEL_LEGACY_32B_CONTEXT,
4028 INTEL_ADVANCED_AD_CONTEXT,
4029 INTEL_LEGACY_64B_CONTEXT
4034 FAULT_AND_HALT, /* Debug only */
4036 FAULT_AND_CONTINUE /* Unsupported */
4039 #define GEN8_CTX_VALID (1 << 0)
4040 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
4041 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
4042 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
4043 #define GEN8_CTX_PRIVILEGE (1 << 8)
4044 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
4046 #define GEN8_CTX_ID_SHIFT 32
4047 #define GEN8_CTX_ID_WIDTH 21
4048 #define GEN11_SW_CTX_ID_SHIFT 37
4049 #define GEN11_SW_CTX_ID_WIDTH 11
4050 #define GEN11_ENGINE_CLASS_SHIFT 61
4051 #define GEN11_ENGINE_CLASS_WIDTH 3
4052 #define GEN11_ENGINE_INSTANCE_SHIFT 48
4053 #define GEN11_ENGINE_INSTANCE_WIDTH 6
4055 #define CHV_CLK_CTL1 _MMIO(0x101100)
4056 #define VLV_CLK_CTL2 _MMIO(0x101104)
4057 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
4063 #define OVADD _MMIO(0x30000)
4064 #define DOVSTA _MMIO(0x30008)
4065 #define OC_BUF (0x3 << 20)
4066 #define OGAMC5 _MMIO(0x30010)
4067 #define OGAMC4 _MMIO(0x30014)
4068 #define OGAMC3 _MMIO(0x30018)
4069 #define OGAMC2 _MMIO(0x3001c)
4070 #define OGAMC1 _MMIO(0x30020)
4071 #define OGAMC0 _MMIO(0x30024)
4074 * GEN9 clock gating regs
4076 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
4077 #define DARBF_GATING_DIS (1 << 27)
4078 #define PWM2_GATING_DIS (1 << 14)
4079 #define PWM1_GATING_DIS (1 << 13)
4081 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
4082 #define BXT_GMBUS_GATING_DIS (1 << 14)
4084 #define _CLKGATE_DIS_PSL_A 0x46520
4085 #define _CLKGATE_DIS_PSL_B 0x46524
4086 #define _CLKGATE_DIS_PSL_C 0x46528
4087 #define DUPS1_GATING_DIS (1 << 15)
4088 #define DUPS2_GATING_DIS (1 << 19)
4089 #define DUPS3_GATING_DIS (1 << 23)
4090 #define DPF_GATING_DIS (1 << 10)
4091 #define DPF_RAM_GATING_DIS (1 << 9)
4092 #define DPFR_GATING_DIS (1 << 8)
4094 #define CLKGATE_DIS_PSL(pipe) \
4095 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
4098 * GEN10 clock gating regs
4100 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
4101 #define SARBUNIT_CLKGATE_DIS (1 << 5)
4102 #define RCCUNIT_CLKGATE_DIS (1 << 7)
4103 #define MSCUNIT_CLKGATE_DIS (1 << 10)
4105 #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
4106 #define GWUNIT_CLKGATE_DIS (1 << 16)
4108 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
4109 #define VFUNIT_CLKGATE_DIS (1 << 20)
4111 #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
4112 #define CGPSF_CLKGATE_DIS (1 << 3)
4115 * Display engine regs
4118 /* Pipe A CRC regs */
4119 #define _PIPE_CRC_CTL_A 0x60050
4120 #define PIPE_CRC_ENABLE (1 << 31)
4121 /* skl+ source selection */
4122 #define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28)
4123 #define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28)
4124 #define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28)
4125 #define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28)
4126 #define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28)
4127 #define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28)
4128 #define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28)
4129 #define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28)
4130 /* ivb+ source selection */
4131 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
4132 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
4133 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
4134 /* ilk+ source selection */
4135 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
4136 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
4137 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
4138 /* embedded DP port on the north display block, reserved on ivb */
4139 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
4140 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
4141 /* vlv source selection */
4142 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
4143 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
4144 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
4145 /* with DP port the pipe source is invalid */
4146 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
4147 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
4148 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
4149 /* gen3+ source selection */
4150 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
4151 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
4152 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
4153 /* with DP/TV port the pipe source is invalid */
4154 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
4155 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
4156 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
4157 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
4158 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
4159 /* gen2 doesn't have source selection bits */
4160 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
4162 #define _PIPE_CRC_RES_1_A_IVB 0x60064
4163 #define _PIPE_CRC_RES_2_A_IVB 0x60068
4164 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
4165 #define _PIPE_CRC_RES_4_A_IVB 0x60070
4166 #define _PIPE_CRC_RES_5_A_IVB 0x60074
4168 #define _PIPE_CRC_RES_RED_A 0x60060
4169 #define _PIPE_CRC_RES_GREEN_A 0x60064
4170 #define _PIPE_CRC_RES_BLUE_A 0x60068
4171 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4172 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
4174 /* Pipe B CRC regs */
4175 #define _PIPE_CRC_RES_1_B_IVB 0x61064
4176 #define _PIPE_CRC_RES_2_B_IVB 0x61068
4177 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
4178 #define _PIPE_CRC_RES_4_B_IVB 0x61070
4179 #define _PIPE_CRC_RES_5_B_IVB 0x61074
4181 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4182 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4183 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4184 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4185 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4186 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4188 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4189 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4190 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4191 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4192 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4194 /* Pipe A timing regs */
4195 #define _HTOTAL_A 0x60000
4196 #define _HBLANK_A 0x60004
4197 #define _HSYNC_A 0x60008
4198 #define _VTOTAL_A 0x6000c
4199 #define _VBLANK_A 0x60010
4200 #define _VSYNC_A 0x60014
4201 #define _PIPEASRC 0x6001c
4202 #define _BCLRPAT_A 0x60020
4203 #define _VSYNCSHIFT_A 0x60028
4204 #define _PIPE_MULT_A 0x6002c
4206 /* Pipe B timing regs */
4207 #define _HTOTAL_B 0x61000
4208 #define _HBLANK_B 0x61004
4209 #define _HSYNC_B 0x61008
4210 #define _VTOTAL_B 0x6100c
4211 #define _VBLANK_B 0x61010
4212 #define _VSYNC_B 0x61014
4213 #define _PIPEBSRC 0x6101c
4214 #define _BCLRPAT_B 0x61020
4215 #define _VSYNCSHIFT_B 0x61028
4216 #define _PIPE_MULT_B 0x6102c
4218 /* DSI 0 timing regs */
4219 #define _HTOTAL_DSI0 0x6b000
4220 #define _HSYNC_DSI0 0x6b008
4221 #define _VTOTAL_DSI0 0x6b00c
4222 #define _VSYNC_DSI0 0x6b014
4223 #define _VSYNCSHIFT_DSI0 0x6b028
4225 /* DSI 1 timing regs */
4226 #define _HTOTAL_DSI1 0x6b800
4227 #define _HSYNC_DSI1 0x6b808
4228 #define _VTOTAL_DSI1 0x6b80c
4229 #define _VSYNC_DSI1 0x6b814
4230 #define _VSYNCSHIFT_DSI1 0x6b828
4232 #define TRANSCODER_A_OFFSET 0x60000
4233 #define TRANSCODER_B_OFFSET 0x61000
4234 #define TRANSCODER_C_OFFSET 0x62000
4235 #define CHV_TRANSCODER_C_OFFSET 0x63000
4236 #define TRANSCODER_D_OFFSET 0x63000
4237 #define TRANSCODER_EDP_OFFSET 0x6f000
4238 #define TRANSCODER_DSI0_OFFSET 0x6b000
4239 #define TRANSCODER_DSI1_OFFSET 0x6b800
4241 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4242 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4243 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4244 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4245 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4246 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4247 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4248 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4249 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4250 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4252 /* HSW+ eDP PSR registers */
4253 #define HSW_EDP_PSR_BASE 0x64800
4254 #define BDW_EDP_PSR_BASE 0x6f800
4255 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
4256 #define EDP_PSR_ENABLE (1 << 31)
4257 #define BDW_PSR_SINGLE_FRAME (1 << 30)
4258 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
4259 #define EDP_PSR_LINK_STANDBY (1 << 27)
4260 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
4261 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
4262 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
4263 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
4264 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
4265 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4266 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
4267 #define EDP_PSR_TP1_TP2_SEL (0 << 11)
4268 #define EDP_PSR_TP1_TP3_SEL (1 << 11)
4269 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
4270 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
4271 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
4272 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
4273 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
4274 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */
4275 #define EDP_PSR_TP1_TIME_500us (0 << 4)
4276 #define EDP_PSR_TP1_TIME_100us (1 << 4)
4277 #define EDP_PSR_TP1_TIME_2500us (2 << 4)
4278 #define EDP_PSR_TP1_TIME_0us (3 << 4)
4279 #define EDP_PSR_IDLE_FRAME_SHIFT 0
4281 /* Bspec claims those aren't shifted but stay at 0x64800 */
4282 #define EDP_PSR_IMR _MMIO(0x64834)
4283 #define EDP_PSR_IIR _MMIO(0x64838)
4284 #define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
4285 #define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
4286 #define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
4287 #define EDP_PSR_TRANSCODER_C_SHIFT 24
4288 #define EDP_PSR_TRANSCODER_B_SHIFT 16
4289 #define EDP_PSR_TRANSCODER_A_SHIFT 8
4290 #define EDP_PSR_TRANSCODER_EDP_SHIFT 0
4292 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4293 #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
4294 #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4295 #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
4296 #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
4297 #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4299 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4301 #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
4302 #define EDP_PSR_STATUS_STATE_MASK (7 << 29)
4303 #define EDP_PSR_STATUS_STATE_SHIFT 29
4304 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
4305 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
4306 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
4307 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
4308 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
4309 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
4310 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
4311 #define EDP_PSR_STATUS_LINK_MASK (3 << 26)
4312 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
4313 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
4314 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
4315 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4316 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4317 #define EDP_PSR_STATUS_COUNT_SHIFT 16
4318 #define EDP_PSR_STATUS_COUNT_MASK 0xf
4319 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
4320 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
4321 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
4322 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
4323 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
4324 #define EDP_PSR_STATUS_IDLE_MASK 0xf
4326 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
4327 #define EDP_PSR_PERF_CNT_MASK 0xffffff
4329 #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
4330 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
4331 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4332 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4333 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
4334 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
4335 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4337 #define EDP_PSR2_CTL _MMIO(0x6f900)
4338 #define EDP_PSR2_ENABLE (1 << 31)
4339 #define EDP_SU_TRACK_ENABLE (1 << 30)
4340 #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
4341 #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */
4342 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
4343 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
4344 #define EDP_PSR2_TP2_TIME_500us (0 << 8)
4345 #define EDP_PSR2_TP2_TIME_100us (1 << 8)
4346 #define EDP_PSR2_TP2_TIME_2500us (2 << 8)
4347 #define EDP_PSR2_TP2_TIME_50us (3 << 8)
4348 #define EDP_PSR2_TP2_TIME_MASK (3 << 8)
4349 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4350 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4351 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
4352 #define EDP_PSR2_IDLE_FRAME_MASK 0xf
4353 #define EDP_PSR2_IDLE_FRAME_SHIFT 0
4355 #define _PSR_EVENT_TRANS_A 0x60848
4356 #define _PSR_EVENT_TRANS_B 0x61848
4357 #define _PSR_EVENT_TRANS_C 0x62848
4358 #define _PSR_EVENT_TRANS_D 0x63848
4359 #define _PSR_EVENT_TRANS_EDP 0x6F848
4360 #define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
4361 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
4362 #define PSR_EVENT_PSR2_DISABLED (1 << 16)
4363 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
4364 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
4365 #define PSR_EVENT_GRAPHICS_RESET (1 << 12)
4366 #define PSR_EVENT_PCH_INTERRUPT (1 << 11)
4367 #define PSR_EVENT_MEMORY_UP (1 << 10)
4368 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4369 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4370 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
4371 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
4372 #define PSR_EVENT_HDCP_ENABLE (1 << 4)
4373 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4374 #define PSR_EVENT_VBI_ENABLE (1 << 2)
4375 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
4376 #define PSR_EVENT_PSR_DISABLE (1 << 0)
4378 #define EDP_PSR2_STATUS _MMIO(0x6f940)
4379 #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
4380 #define EDP_PSR2_STATUS_STATE_SHIFT 28
4382 #define _PSR2_SU_STATUS_0 0x6F914
4383 #define _PSR2_SU_STATUS_1 0x6F918
4384 #define _PSR2_SU_STATUS_2 0x6F91C
4385 #define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
4386 #define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
4387 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
4388 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4389 #define PSR2_SU_STATUS_FRAMES 8
4391 /* VGA port control */
4392 #define ADPA _MMIO(0x61100)
4393 #define PCH_ADPA _MMIO(0xe1100)
4394 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4396 #define ADPA_DAC_ENABLE (1 << 31)
4397 #define ADPA_DAC_DISABLE 0
4398 #define ADPA_PIPE_SEL_SHIFT 30
4399 #define ADPA_PIPE_SEL_MASK (1 << 30)
4400 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
4401 #define ADPA_PIPE_SEL_SHIFT_CPT 29
4402 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
4403 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4404 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4405 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
4406 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
4407 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4408 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
4409 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
4410 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
4411 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
4412 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
4413 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
4414 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
4415 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
4416 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
4417 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
4418 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
4419 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
4420 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
4421 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
4422 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4423 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
4424 #define ADPA_SETS_HVPOLARITY 0
4425 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4426 #define ADPA_VSYNC_CNTL_ENABLE 0
4427 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4428 #define ADPA_HSYNC_CNTL_ENABLE 0
4429 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4430 #define ADPA_VSYNC_ACTIVE_LOW 0
4431 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4432 #define ADPA_HSYNC_ACTIVE_LOW 0
4433 #define ADPA_DPMS_MASK (~(3 << 10))
4434 #define ADPA_DPMS_ON (0 << 10)
4435 #define ADPA_DPMS_SUSPEND (1 << 10)
4436 #define ADPA_DPMS_STANDBY (2 << 10)
4437 #define ADPA_DPMS_OFF (3 << 10)
4440 /* Hotplug control (945+ only) */
4441 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4442 #define PORTB_HOTPLUG_INT_EN (1 << 29)
4443 #define PORTC_HOTPLUG_INT_EN (1 << 28)
4444 #define PORTD_HOTPLUG_INT_EN (1 << 27)
4445 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
4446 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
4447 #define TV_HOTPLUG_INT_EN (1 << 18)
4448 #define CRT_HOTPLUG_INT_EN (1 << 9)
4449 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4450 PORTC_HOTPLUG_INT_EN | \
4451 PORTD_HOTPLUG_INT_EN | \
4452 SDVOC_HOTPLUG_INT_EN | \
4453 SDVOB_HOTPLUG_INT_EN | \
4455 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
4456 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4457 /* must use period 64 on GM45 according to docs */
4458 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4459 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4460 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4461 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4462 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4463 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4464 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4465 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4466 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4467 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4468 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4469 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4471 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4473 * HDMI/DP bits are g4x+
4475 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4476 * Please check the detailed lore in the commit message for for experimental
4479 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4480 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4481 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4482 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4483 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4484 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
4485 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
4486 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
4487 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
4488 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4489 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
4490 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
4491 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4492 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
4493 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
4494 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4495 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
4496 /* CRT/TV common between gen3+ */
4497 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
4498 #define TV_HOTPLUG_INT_STATUS (1 << 10)
4499 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4500 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4501 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4502 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4503 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4504 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4505 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
4506 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4508 /* SDVO is different across gen3/4 */
4509 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4510 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4512 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4513 * since reality corrobates that they're the same as on gen3. But keep these
4514 * bits here (and the comment!) to help any other lost wanderers back onto the
4517 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4518 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4519 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4520 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
4521 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4522 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4523 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4524 PORTB_HOTPLUG_INT_STATUS | \
4525 PORTC_HOTPLUG_INT_STATUS | \
4526 PORTD_HOTPLUG_INT_STATUS)
4528 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4529 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4530 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4531 PORTB_HOTPLUG_INT_STATUS | \
4532 PORTC_HOTPLUG_INT_STATUS | \
4533 PORTD_HOTPLUG_INT_STATUS)
4535 /* SDVO and HDMI port control.
4536 * The same register may be used for SDVO or HDMI */
4537 #define _GEN3_SDVOB 0x61140
4538 #define _GEN3_SDVOC 0x61160
4539 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4540 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
4541 #define GEN4_HDMIB GEN3_SDVOB
4542 #define GEN4_HDMIC GEN3_SDVOC
4543 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4544 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4545 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4546 #define PCH_SDVOB _MMIO(0xe1140)
4547 #define PCH_HDMIB PCH_SDVOB
4548 #define PCH_HDMIC _MMIO(0xe1150)
4549 #define PCH_HDMID _MMIO(0xe1160)
4551 #define PORT_DFT_I9XX _MMIO(0x61150)
4552 #define DC_BALANCE_RESET (1 << 25)
4553 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4554 #define DC_BALANCE_RESET_VLV (1 << 31)
4555 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4556 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
4557 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
4558 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
4560 /* Gen 3 SDVO bits: */
4561 #define SDVO_ENABLE (1 << 31)
4562 #define SDVO_PIPE_SEL_SHIFT 30
4563 #define SDVO_PIPE_SEL_MASK (1 << 30)
4564 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4565 #define SDVO_STALL_SELECT (1 << 29)
4566 #define SDVO_INTERRUPT_ENABLE (1 << 26)
4568 * 915G/GM SDVO pixel multiplier.
4569 * Programmed value is multiplier - 1, up to 5x.
4570 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4572 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
4573 #define SDVO_PORT_MULTIPLY_SHIFT 23
4574 #define SDVO_PHASE_SELECT_MASK (15 << 19)
4575 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4576 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4577 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
4578 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
4579 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
4580 #define SDVO_DETECTED (1 << 2)
4581 /* Bits to be preserved when writing */
4582 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4583 SDVO_INTERRUPT_ENABLE)
4584 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4586 /* Gen 4 SDVO/HDMI bits: */
4587 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
4588 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
4589 #define SDVO_ENCODING_SDVO (0 << 10)
4590 #define SDVO_ENCODING_HDMI (2 << 10)
4591 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4592 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4593 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
4594 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
4595 /* VSYNC/HSYNC bits new with 965, default is to be set */
4596 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4597 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4599 /* Gen 5 (IBX) SDVO/HDMI bits: */
4600 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
4601 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
4603 /* Gen 6 (CPT) SDVO/HDMI bits: */
4604 #define SDVO_PIPE_SEL_SHIFT_CPT 29
4605 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
4606 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4608 /* CHV SDVO/HDMI bits: */
4609 #define SDVO_PIPE_SEL_SHIFT_CHV 24
4610 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4611 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4614 /* DVO port control */
4615 #define _DVOA 0x61120
4616 #define DVOA _MMIO(_DVOA)
4617 #define _DVOB 0x61140
4618 #define DVOB _MMIO(_DVOB)
4619 #define _DVOC 0x61160
4620 #define DVOC _MMIO(_DVOC)
4621 #define DVO_ENABLE (1 << 31)
4622 #define DVO_PIPE_SEL_SHIFT 30
4623 #define DVO_PIPE_SEL_MASK (1 << 30)
4624 #define DVO_PIPE_SEL(pipe) ((pipe) << 30)
4625 #define DVO_PIPE_STALL_UNUSED (0 << 28)
4626 #define DVO_PIPE_STALL (1 << 28)
4627 #define DVO_PIPE_STALL_TV (2 << 28)
4628 #define DVO_PIPE_STALL_MASK (3 << 28)
4629 #define DVO_USE_VGA_SYNC (1 << 15)
4630 #define DVO_DATA_ORDER_I740 (0 << 14)
4631 #define DVO_DATA_ORDER_FP (1 << 14)
4632 #define DVO_VSYNC_DISABLE (1 << 11)
4633 #define DVO_HSYNC_DISABLE (1 << 10)
4634 #define DVO_VSYNC_TRISTATE (1 << 9)
4635 #define DVO_HSYNC_TRISTATE (1 << 8)
4636 #define DVO_BORDER_ENABLE (1 << 7)
4637 #define DVO_DATA_ORDER_GBRG (1 << 6)
4638 #define DVO_DATA_ORDER_RGGB (0 << 6)
4639 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4640 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4641 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4642 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4643 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4644 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
4645 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
4646 #define DVO_PRESERVE_MASK (0x7 << 24)
4647 #define DVOA_SRCDIM _MMIO(0x61124)
4648 #define DVOB_SRCDIM _MMIO(0x61144)
4649 #define DVOC_SRCDIM _MMIO(0x61164)
4650 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4651 #define DVO_SRCDIM_VERTICAL_SHIFT 0
4653 /* LVDS port control */
4654 #define LVDS _MMIO(0x61180)
4656 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4657 * the DPLL semantics change when the LVDS is assigned to that pipe.
4659 #define LVDS_PORT_EN (1 << 31)
4660 /* Selects pipe B for LVDS data. Must be set on pre-965. */
4661 #define LVDS_PIPE_SEL_SHIFT 30
4662 #define LVDS_PIPE_SEL_MASK (1 << 30)
4663 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
4664 #define LVDS_PIPE_SEL_SHIFT_CPT 29
4665 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
4666 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4667 /* LVDS dithering flag on 965/g4x platform */
4668 #define LVDS_ENABLE_DITHER (1 << 25)
4669 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4670 #define LVDS_VSYNC_POLARITY (1 << 21)
4671 #define LVDS_HSYNC_POLARITY (1 << 20)
4673 /* Enable border for unscaled (or aspect-scaled) display */
4674 #define LVDS_BORDER_ENABLE (1 << 15)
4676 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4679 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
4680 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
4681 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
4683 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4684 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4687 #define LVDS_A3_POWER_MASK (3 << 6)
4688 #define LVDS_A3_POWER_DOWN (0 << 6)
4689 #define LVDS_A3_POWER_UP (3 << 6)
4691 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
4694 #define LVDS_CLKB_POWER_MASK (3 << 4)
4695 #define LVDS_CLKB_POWER_DOWN (0 << 4)
4696 #define LVDS_CLKB_POWER_UP (3 << 4)
4698 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4699 * setting for whether we are in dual-channel mode. The B3 pair will
4700 * additionally only be powered up when LVDS_A3_POWER_UP is set.
4702 #define LVDS_B0B3_POWER_MASK (3 << 2)
4703 #define LVDS_B0B3_POWER_DOWN (0 << 2)
4704 #define LVDS_B0B3_POWER_UP (3 << 2)
4706 /* Video Data Island Packet control */
4707 #define VIDEO_DIP_DATA _MMIO(0x61178)
4708 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4709 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4710 * of the infoframe structure specified by CEA-861. */
4711 #define VIDEO_DIP_DATA_SIZE 32
4712 #define VIDEO_DIP_VSC_DATA_SIZE 36
4713 #define VIDEO_DIP_PPS_DATA_SIZE 132
4714 #define VIDEO_DIP_CTL _MMIO(0x61170)
4716 #define VIDEO_DIP_ENABLE (1 << 31)
4717 #define VIDEO_DIP_PORT(port) ((port) << 29)
4718 #define VIDEO_DIP_PORT_MASK (3 << 29)
4719 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
4720 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
4721 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
4722 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
4723 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
4724 #define VIDEO_DIP_SELECT_AVI (0 << 19)
4725 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
4726 #define VIDEO_DIP_SELECT_GAMUT (2 << 19)
4727 #define VIDEO_DIP_SELECT_SPD (3 << 19)
4728 #define VIDEO_DIP_SELECT_MASK (3 << 19)
4729 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
4730 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
4731 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4732 #define VIDEO_DIP_FREQ_MASK (3 << 16)
4733 /* HSW and later: */
4734 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
4735 #define PSR_VSC_BIT_7_SET (1 << 27)
4736 #define VSC_SELECT_MASK (0x3 << 25)
4737 #define VSC_SELECT_SHIFT 25
4738 #define VSC_DIP_HW_HEA_DATA (0 << 25)
4739 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
4740 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
4741 #define VSC_DIP_SW_HEA_DATA (3 << 25)
4742 #define VDIP_ENABLE_PPS (1 << 24)
4743 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4744 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4745 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
4746 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4747 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4748 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4750 /* Panel power sequencing */
4751 #define PPS_BASE 0x61200
4752 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
4753 #define PCH_PPS_BASE 0xC7200
4755 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4756 PPS_BASE + (reg) + \
4759 #define _PP_STATUS 0x61200
4760 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4761 #define PP_ON REG_BIT(31)
4763 #define _PP_CONTROL_1 0xc7204
4764 #define _PP_CONTROL_2 0xc7304
4765 #define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
4767 #define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
4768 #define VDD_OVERRIDE_FORCE REG_BIT(3)
4769 #define BACKLIGHT_ENABLE REG_BIT(2)
4770 #define PWR_DOWN_ON_RESET REG_BIT(1)
4771 #define PWR_STATE_TARGET REG_BIT(0)
4773 * Indicates that all dependencies of the panel are on:
4777 * - LVDS/DVOB/DVOC on
4779 #define PP_READY REG_BIT(30)
4780 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
4781 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
4782 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
4783 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
4784 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
4785 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
4786 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
4787 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
4788 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
4789 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
4790 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
4791 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
4792 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
4793 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
4794 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
4796 #define _PP_CONTROL 0x61204
4797 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4798 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
4799 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
4800 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
4801 #define EDP_FORCE_VDD REG_BIT(3)
4802 #define EDP_BLC_ENABLE REG_BIT(2)
4803 #define PANEL_POWER_RESET REG_BIT(1)
4804 #define PANEL_POWER_ON REG_BIT(0)
4806 #define _PP_ON_DELAYS 0x61208
4807 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4808 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
4809 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
4810 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
4811 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
4812 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
4813 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
4814 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
4815 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
4817 #define _PP_OFF_DELAYS 0x6120C
4818 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4819 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
4820 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
4822 #define _PP_DIVISOR 0x61210
4823 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4824 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
4825 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
4828 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
4829 #define PFIT_ENABLE (1 << 31)
4830 #define PFIT_PIPE_MASK (3 << 29)
4831 #define PFIT_PIPE_SHIFT 29
4832 #define VERT_INTERP_DISABLE (0 << 10)
4833 #define VERT_INTERP_BILINEAR (1 << 10)
4834 #define VERT_INTERP_MASK (3 << 10)
4835 #define VERT_AUTO_SCALE (1 << 9)
4836 #define HORIZ_INTERP_DISABLE (0 << 6)
4837 #define HORIZ_INTERP_BILINEAR (1 << 6)
4838 #define HORIZ_INTERP_MASK (3 << 6)
4839 #define HORIZ_AUTO_SCALE (1 << 5)
4840 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
4841 #define PFIT_FILTER_FUZZY (0 << 24)
4842 #define PFIT_SCALING_AUTO (0 << 26)
4843 #define PFIT_SCALING_PROGRAMMED (1 << 26)
4844 #define PFIT_SCALING_PILLAR (2 << 26)
4845 #define PFIT_SCALING_LETTER (3 << 26)
4846 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
4848 #define PFIT_VERT_SCALE_SHIFT 20
4849 #define PFIT_VERT_SCALE_MASK 0xfff00000
4850 #define PFIT_HORIZ_SCALE_SHIFT 4
4851 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
4853 #define PFIT_VERT_SCALE_SHIFT_965 16
4854 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
4855 #define PFIT_HORIZ_SCALE_SHIFT_965 0
4856 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4858 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
4860 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
4861 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
4862 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4863 _VLV_BLC_PWM_CTL2_B)
4865 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4866 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
4867 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4870 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4871 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
4872 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4873 _VLV_BLC_HIST_CTL_B)
4875 /* Backlight control */
4876 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
4877 #define BLM_PWM_ENABLE (1 << 31)
4878 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
4879 #define BLM_PIPE_SELECT (1 << 29)
4880 #define BLM_PIPE_SELECT_IVB (3 << 29)
4881 #define BLM_PIPE_A (0 << 29)
4882 #define BLM_PIPE_B (1 << 29)
4883 #define BLM_PIPE_C (2 << 29) /* ivb + */
4884 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
4885 #define BLM_TRANSCODER_B BLM_PIPE_B
4886 #define BLM_TRANSCODER_C BLM_PIPE_C
4887 #define BLM_TRANSCODER_EDP (3 << 29)
4888 #define BLM_PIPE(pipe) ((pipe) << 29)
4889 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
4890 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
4891 #define BLM_PHASE_IN_ENABLE (1 << 25)
4892 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
4893 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
4894 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
4895 #define BLM_PHASE_IN_COUNT_SHIFT (8)
4896 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4897 #define BLM_PHASE_IN_INCR_SHIFT (0)
4898 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
4899 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4901 * This is the most significant 15 bits of the number of backlight cycles in a
4902 * complete cycle of the modulated backlight control.
4904 * The actual value is this field multiplied by two.
4906 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
4907 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
4908 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
4910 * This is the number of cycles out of the backlight modulation cycle for which
4911 * the backlight is on.
4913 * This field must be no greater than the number of cycles in the complete
4914 * backlight modulation cycle.
4916 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
4917 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
4918 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4919 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
4921 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4922 #define BLM_HISTOGRAM_ENABLE (1 << 31)
4924 /* New registers for PCH-split platforms. Safe where new bits show up, the
4925 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
4926 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
4927 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
4929 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
4931 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4932 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
4933 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
4934 #define BLM_PCH_PWM_ENABLE (1 << 31)
4935 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
4936 #define BLM_PCH_POLARITY (1 << 29)
4937 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
4939 #define UTIL_PIN_CTL _MMIO(0x48400)
4940 #define UTIL_PIN_ENABLE (1 << 31)
4942 #define UTIL_PIN_PIPE(x) ((x) << 29)
4943 #define UTIL_PIN_PIPE_MASK (3 << 29)
4944 #define UTIL_PIN_MODE_PWM (1 << 24)
4945 #define UTIL_PIN_MODE_MASK (0xf << 24)
4946 #define UTIL_PIN_POLARITY (1 << 22)
4948 /* BXT backlight register definition. */
4949 #define _BXT_BLC_PWM_CTL1 0xC8250
4950 #define BXT_BLC_PWM_ENABLE (1 << 31)
4951 #define BXT_BLC_PWM_POLARITY (1 << 29)
4952 #define _BXT_BLC_PWM_FREQ1 0xC8254
4953 #define _BXT_BLC_PWM_DUTY1 0xC8258
4955 #define _BXT_BLC_PWM_CTL2 0xC8350
4956 #define _BXT_BLC_PWM_FREQ2 0xC8354
4957 #define _BXT_BLC_PWM_DUTY2 0xC8358
4959 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
4960 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4961 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
4962 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4963 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
4964 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4966 #define PCH_GTC_CTL _MMIO(0xe7000)
4967 #define PCH_GTC_ENABLE (1 << 31)
4969 /* TV port control */
4970 #define TV_CTL _MMIO(0x68000)
4971 /* Enables the TV encoder */
4972 # define TV_ENC_ENABLE (1 << 31)
4973 /* Sources the TV encoder input from pipe B instead of A. */
4974 # define TV_ENC_PIPE_SEL_SHIFT 30
4975 # define TV_ENC_PIPE_SEL_MASK (1 << 30)
4976 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
4977 /* Outputs composite video (DAC A only) */
4978 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
4979 /* Outputs SVideo video (DAC B/C) */
4980 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
4981 /* Outputs Component video (DAC A/B/C) */
4982 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
4983 /* Outputs Composite and SVideo (DAC A/B/C) */
4984 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4985 # define TV_TRILEVEL_SYNC (1 << 21)
4986 /* Enables slow sync generation (945GM only) */
4987 # define TV_SLOW_SYNC (1 << 20)
4988 /* Selects 4x oversampling for 480i and 576p */
4989 # define TV_OVERSAMPLE_4X (0 << 18)
4990 /* Selects 2x oversampling for 720p and 1080i */
4991 # define TV_OVERSAMPLE_2X (1 << 18)
4992 /* Selects no oversampling for 1080p */
4993 # define TV_OVERSAMPLE_NONE (2 << 18)
4994 /* Selects 8x oversampling */
4995 # define TV_OVERSAMPLE_8X (3 << 18)
4996 # define TV_OVERSAMPLE_MASK (3 << 18)
4997 /* Selects progressive mode rather than interlaced */
4998 # define TV_PROGRESSIVE (1 << 17)
4999 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
5000 # define TV_PAL_BURST (1 << 16)
5001 /* Field for setting delay of Y compared to C */
5002 # define TV_YC_SKEW_MASK (7 << 12)
5003 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
5004 # define TV_ENC_SDP_FIX (1 << 11)
5006 * Enables a fix for the 915GM only.
5008 * Not sure what it does.
5010 # define TV_ENC_C0_FIX (1 << 10)
5011 /* Bits that must be preserved by software */
5012 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
5013 # define TV_FUSE_STATE_MASK (3 << 4)
5014 /* Read-only state that reports all features enabled */
5015 # define TV_FUSE_STATE_ENABLED (0 << 4)
5016 /* Read-only state that reports that Macrovision is disabled in hardware*/
5017 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
5018 /* Read-only state that reports that TV-out is disabled in hardware. */
5019 # define TV_FUSE_STATE_DISABLED (2 << 4)
5020 /* Normal operation */
5021 # define TV_TEST_MODE_NORMAL (0 << 0)
5022 /* Encoder test pattern 1 - combo pattern */
5023 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
5024 /* Encoder test pattern 2 - full screen vertical 75% color bars */
5025 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
5026 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
5027 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
5028 /* Encoder test pattern 4 - random noise */
5029 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
5030 /* Encoder test pattern 5 - linear color ramps */
5031 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
5033 * This test mode forces the DACs to 50% of full output.
5035 * This is used for load detection in combination with TVDAC_SENSE_MASK
5037 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
5038 # define TV_TEST_MODE_MASK (7 << 0)
5040 #define TV_DAC _MMIO(0x68004)
5041 # define TV_DAC_SAVE 0x00ffff00
5043 * Reports that DAC state change logic has reported change (RO).
5045 * This gets cleared when TV_DAC_STATE_EN is cleared
5047 # define TVDAC_STATE_CHG (1 << 31)
5048 # define TVDAC_SENSE_MASK (7 << 28)
5049 /* Reports that DAC A voltage is above the detect threshold */
5050 # define TVDAC_A_SENSE (1 << 30)
5051 /* Reports that DAC B voltage is above the detect threshold */
5052 # define TVDAC_B_SENSE (1 << 29)
5053 /* Reports that DAC C voltage is above the detect threshold */
5054 # define TVDAC_C_SENSE (1 << 28)
5056 * Enables DAC state detection logic, for load-based TV detection.
5058 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
5059 * to off, for load detection to work.
5061 # define TVDAC_STATE_CHG_EN (1 << 27)
5062 /* Sets the DAC A sense value to high */
5063 # define TVDAC_A_SENSE_CTL (1 << 26)
5064 /* Sets the DAC B sense value to high */
5065 # define TVDAC_B_SENSE_CTL (1 << 25)
5066 /* Sets the DAC C sense value to high */
5067 # define TVDAC_C_SENSE_CTL (1 << 24)
5068 /* Overrides the ENC_ENABLE and DAC voltage levels */
5069 # define DAC_CTL_OVERRIDE (1 << 7)
5070 /* Sets the slew rate. Must be preserved in software */
5071 # define ENC_TVDAC_SLEW_FAST (1 << 6)
5072 # define DAC_A_1_3_V (0 << 4)
5073 # define DAC_A_1_1_V (1 << 4)
5074 # define DAC_A_0_7_V (2 << 4)
5075 # define DAC_A_MASK (3 << 4)
5076 # define DAC_B_1_3_V (0 << 2)
5077 # define DAC_B_1_1_V (1 << 2)
5078 # define DAC_B_0_7_V (2 << 2)
5079 # define DAC_B_MASK (3 << 2)
5080 # define DAC_C_1_3_V (0 << 0)
5081 # define DAC_C_1_1_V (1 << 0)
5082 # define DAC_C_0_7_V (2 << 0)
5083 # define DAC_C_MASK (3 << 0)
5086 * CSC coefficients are stored in a floating point format with 9 bits of
5087 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
5088 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5089 * -1 (0x3) being the only legal negative value.
5091 #define TV_CSC_Y _MMIO(0x68010)
5092 # define TV_RY_MASK 0x07ff0000
5093 # define TV_RY_SHIFT 16
5094 # define TV_GY_MASK 0x00000fff
5095 # define TV_GY_SHIFT 0
5097 #define TV_CSC_Y2 _MMIO(0x68014)
5098 # define TV_BY_MASK 0x07ff0000
5099 # define TV_BY_SHIFT 16
5101 * Y attenuation for component video.
5103 * Stored in 1.9 fixed point.
5105 # define TV_AY_MASK 0x000003ff
5106 # define TV_AY_SHIFT 0
5108 #define TV_CSC_U _MMIO(0x68018)
5109 # define TV_RU_MASK 0x07ff0000
5110 # define TV_RU_SHIFT 16
5111 # define TV_GU_MASK 0x000007ff
5112 # define TV_GU_SHIFT 0
5114 #define TV_CSC_U2 _MMIO(0x6801c)
5115 # define TV_BU_MASK 0x07ff0000
5116 # define TV_BU_SHIFT 16
5118 * U attenuation for component video.
5120 * Stored in 1.9 fixed point.
5122 # define TV_AU_MASK 0x000003ff
5123 # define TV_AU_SHIFT 0
5125 #define TV_CSC_V _MMIO(0x68020)
5126 # define TV_RV_MASK 0x0fff0000
5127 # define TV_RV_SHIFT 16
5128 # define TV_GV_MASK 0x000007ff
5129 # define TV_GV_SHIFT 0
5131 #define TV_CSC_V2 _MMIO(0x68024)
5132 # define TV_BV_MASK 0x07ff0000
5133 # define TV_BV_SHIFT 16
5135 * V attenuation for component video.
5137 * Stored in 1.9 fixed point.
5139 # define TV_AV_MASK 0x000007ff
5140 # define TV_AV_SHIFT 0
5142 #define TV_CLR_KNOBS _MMIO(0x68028)
5143 /* 2s-complement brightness adjustment */
5144 # define TV_BRIGHTNESS_MASK 0xff000000
5145 # define TV_BRIGHTNESS_SHIFT 24
5146 /* Contrast adjustment, as a 2.6 unsigned floating point number */
5147 # define TV_CONTRAST_MASK 0x00ff0000
5148 # define TV_CONTRAST_SHIFT 16
5149 /* Saturation adjustment, as a 2.6 unsigned floating point number */
5150 # define TV_SATURATION_MASK 0x0000ff00
5151 # define TV_SATURATION_SHIFT 8
5152 /* Hue adjustment, as an integer phase angle in degrees */
5153 # define TV_HUE_MASK 0x000000ff
5154 # define TV_HUE_SHIFT 0
5156 #define TV_CLR_LEVEL _MMIO(0x6802c)
5157 /* Controls the DAC level for black */
5158 # define TV_BLACK_LEVEL_MASK 0x01ff0000
5159 # define TV_BLACK_LEVEL_SHIFT 16
5160 /* Controls the DAC level for blanking */
5161 # define TV_BLANK_LEVEL_MASK 0x000001ff
5162 # define TV_BLANK_LEVEL_SHIFT 0
5164 #define TV_H_CTL_1 _MMIO(0x68030)
5165 /* Number of pixels in the hsync. */
5166 # define TV_HSYNC_END_MASK 0x1fff0000
5167 # define TV_HSYNC_END_SHIFT 16
5168 /* Total number of pixels minus one in the line (display and blanking). */
5169 # define TV_HTOTAL_MASK 0x00001fff
5170 # define TV_HTOTAL_SHIFT 0
5172 #define TV_H_CTL_2 _MMIO(0x68034)
5173 /* Enables the colorburst (needed for non-component color) */
5174 # define TV_BURST_ENA (1 << 31)
5175 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5176 # define TV_HBURST_START_SHIFT 16
5177 # define TV_HBURST_START_MASK 0x1fff0000
5178 /* Length of the colorburst */
5179 # define TV_HBURST_LEN_SHIFT 0
5180 # define TV_HBURST_LEN_MASK 0x0001fff
5182 #define TV_H_CTL_3 _MMIO(0x68038)
5183 /* End of hblank, measured in pixels minus one from start of hsync */
5184 # define TV_HBLANK_END_SHIFT 16
5185 # define TV_HBLANK_END_MASK 0x1fff0000
5186 /* Start of hblank, measured in pixels minus one from start of hsync */
5187 # define TV_HBLANK_START_SHIFT 0
5188 # define TV_HBLANK_START_MASK 0x0001fff
5190 #define TV_V_CTL_1 _MMIO(0x6803c)
5192 # define TV_NBR_END_SHIFT 16
5193 # define TV_NBR_END_MASK 0x07ff0000
5195 # define TV_VI_END_F1_SHIFT 8
5196 # define TV_VI_END_F1_MASK 0x00003f00
5198 # define TV_VI_END_F2_SHIFT 0
5199 # define TV_VI_END_F2_MASK 0x0000003f
5201 #define TV_V_CTL_2 _MMIO(0x68040)
5202 /* Length of vsync, in half lines */
5203 # define TV_VSYNC_LEN_MASK 0x07ff0000
5204 # define TV_VSYNC_LEN_SHIFT 16
5205 /* Offset of the start of vsync in field 1, measured in one less than the
5206 * number of half lines.
5208 # define TV_VSYNC_START_F1_MASK 0x00007f00
5209 # define TV_VSYNC_START_F1_SHIFT 8
5211 * Offset of the start of vsync in field 2, measured in one less than the
5212 * number of half lines.
5214 # define TV_VSYNC_START_F2_MASK 0x0000007f
5215 # define TV_VSYNC_START_F2_SHIFT 0
5217 #define TV_V_CTL_3 _MMIO(0x68044)
5218 /* Enables generation of the equalization signal */
5219 # define TV_EQUAL_ENA (1 << 31)
5220 /* Length of vsync, in half lines */
5221 # define TV_VEQ_LEN_MASK 0x007f0000
5222 # define TV_VEQ_LEN_SHIFT 16
5223 /* Offset of the start of equalization in field 1, measured in one less than
5224 * the number of half lines.
5226 # define TV_VEQ_START_F1_MASK 0x0007f00
5227 # define TV_VEQ_START_F1_SHIFT 8
5229 * Offset of the start of equalization in field 2, measured in one less than
5230 * the number of half lines.
5232 # define TV_VEQ_START_F2_MASK 0x000007f
5233 # define TV_VEQ_START_F2_SHIFT 0
5235 #define TV_V_CTL_4 _MMIO(0x68048)
5237 * Offset to start of vertical colorburst, measured in one less than the
5238 * number of lines from vertical start.
5240 # define TV_VBURST_START_F1_MASK 0x003f0000
5241 # define TV_VBURST_START_F1_SHIFT 16
5243 * Offset to the end of vertical colorburst, measured in one less than the
5244 * number of lines from the start of NBR.
5246 # define TV_VBURST_END_F1_MASK 0x000000ff
5247 # define TV_VBURST_END_F1_SHIFT 0
5249 #define TV_V_CTL_5 _MMIO(0x6804c)
5251 * Offset to start of vertical colorburst, measured in one less than the
5252 * number of lines from vertical start.
5254 # define TV_VBURST_START_F2_MASK 0x003f0000
5255 # define TV_VBURST_START_F2_SHIFT 16
5257 * Offset to the end of vertical colorburst, measured in one less than the
5258 * number of lines from the start of NBR.
5260 # define TV_VBURST_END_F2_MASK 0x000000ff
5261 # define TV_VBURST_END_F2_SHIFT 0
5263 #define TV_V_CTL_6 _MMIO(0x68050)
5265 * Offset to start of vertical colorburst, measured in one less than the
5266 * number of lines from vertical start.
5268 # define TV_VBURST_START_F3_MASK 0x003f0000
5269 # define TV_VBURST_START_F3_SHIFT 16
5271 * Offset to the end of vertical colorburst, measured in one less than the
5272 * number of lines from the start of NBR.
5274 # define TV_VBURST_END_F3_MASK 0x000000ff
5275 # define TV_VBURST_END_F3_SHIFT 0
5277 #define TV_V_CTL_7 _MMIO(0x68054)
5279 * Offset to start of vertical colorburst, measured in one less than the
5280 * number of lines from vertical start.
5282 # define TV_VBURST_START_F4_MASK 0x003f0000
5283 # define TV_VBURST_START_F4_SHIFT 16
5285 * Offset to the end of vertical colorburst, measured in one less than the
5286 * number of lines from the start of NBR.
5288 # define TV_VBURST_END_F4_MASK 0x000000ff
5289 # define TV_VBURST_END_F4_SHIFT 0
5291 #define TV_SC_CTL_1 _MMIO(0x68060)
5292 /* Turns on the first subcarrier phase generation DDA */
5293 # define TV_SC_DDA1_EN (1 << 31)
5294 /* Turns on the first subcarrier phase generation DDA */
5295 # define TV_SC_DDA2_EN (1 << 30)
5296 /* Turns on the first subcarrier phase generation DDA */
5297 # define TV_SC_DDA3_EN (1 << 29)
5298 /* Sets the subcarrier DDA to reset frequency every other field */
5299 # define TV_SC_RESET_EVERY_2 (0 << 24)
5300 /* Sets the subcarrier DDA to reset frequency every fourth field */
5301 # define TV_SC_RESET_EVERY_4 (1 << 24)
5302 /* Sets the subcarrier DDA to reset frequency every eighth field */
5303 # define TV_SC_RESET_EVERY_8 (2 << 24)
5304 /* Sets the subcarrier DDA to never reset the frequency */
5305 # define TV_SC_RESET_NEVER (3 << 24)
5306 /* Sets the peak amplitude of the colorburst.*/
5307 # define TV_BURST_LEVEL_MASK 0x00ff0000
5308 # define TV_BURST_LEVEL_SHIFT 16
5309 /* Sets the increment of the first subcarrier phase generation DDA */
5310 # define TV_SCDDA1_INC_MASK 0x00000fff
5311 # define TV_SCDDA1_INC_SHIFT 0
5313 #define TV_SC_CTL_2 _MMIO(0x68064)
5314 /* Sets the rollover for the second subcarrier phase generation DDA */
5315 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
5316 # define TV_SCDDA2_SIZE_SHIFT 16
5317 /* Sets the increent of the second subcarrier phase generation DDA */
5318 # define TV_SCDDA2_INC_MASK 0x00007fff
5319 # define TV_SCDDA2_INC_SHIFT 0
5321 #define TV_SC_CTL_3 _MMIO(0x68068)
5322 /* Sets the rollover for the third subcarrier phase generation DDA */
5323 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
5324 # define TV_SCDDA3_SIZE_SHIFT 16
5325 /* Sets the increent of the third subcarrier phase generation DDA */
5326 # define TV_SCDDA3_INC_MASK 0x00007fff
5327 # define TV_SCDDA3_INC_SHIFT 0
5329 #define TV_WIN_POS _MMIO(0x68070)
5330 /* X coordinate of the display from the start of horizontal active */
5331 # define TV_XPOS_MASK 0x1fff0000
5332 # define TV_XPOS_SHIFT 16
5333 /* Y coordinate of the display from the start of vertical active (NBR) */
5334 # define TV_YPOS_MASK 0x00000fff
5335 # define TV_YPOS_SHIFT 0
5337 #define TV_WIN_SIZE _MMIO(0x68074)
5338 /* Horizontal size of the display window, measured in pixels*/
5339 # define TV_XSIZE_MASK 0x1fff0000
5340 # define TV_XSIZE_SHIFT 16
5342 * Vertical size of the display window, measured in pixels.
5344 * Must be even for interlaced modes.
5346 # define TV_YSIZE_MASK 0x00000fff
5347 # define TV_YSIZE_SHIFT 0
5349 #define TV_FILTER_CTL_1 _MMIO(0x68080)
5351 * Enables automatic scaling calculation.
5353 * If set, the rest of the registers are ignored, and the calculated values can
5354 * be read back from the register.
5356 # define TV_AUTO_SCALE (1 << 31)
5358 * Disables the vertical filter.
5360 * This is required on modes more than 1024 pixels wide */
5361 # define TV_V_FILTER_BYPASS (1 << 29)
5362 /* Enables adaptive vertical filtering */
5363 # define TV_VADAPT (1 << 28)
5364 # define TV_VADAPT_MODE_MASK (3 << 26)
5365 /* Selects the least adaptive vertical filtering mode */
5366 # define TV_VADAPT_MODE_LEAST (0 << 26)
5367 /* Selects the moderately adaptive vertical filtering mode */
5368 # define TV_VADAPT_MODE_MODERATE (1 << 26)
5369 /* Selects the most adaptive vertical filtering mode */
5370 # define TV_VADAPT_MODE_MOST (3 << 26)
5372 * Sets the horizontal scaling factor.
5374 * This should be the fractional part of the horizontal scaling factor divided
5375 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5377 * (src width - 1) / ((oversample * dest width) - 1)
5379 # define TV_HSCALE_FRAC_MASK 0x00003fff
5380 # define TV_HSCALE_FRAC_SHIFT 0
5382 #define TV_FILTER_CTL_2 _MMIO(0x68084)
5384 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5386 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5388 # define TV_VSCALE_INT_MASK 0x00038000
5389 # define TV_VSCALE_INT_SHIFT 15
5391 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5393 * \sa TV_VSCALE_INT_MASK
5395 # define TV_VSCALE_FRAC_MASK 0x00007fff
5396 # define TV_VSCALE_FRAC_SHIFT 0
5398 #define TV_FILTER_CTL_3 _MMIO(0x68088)
5400 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5402 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5404 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5406 # define TV_VSCALE_IP_INT_MASK 0x00038000
5407 # define TV_VSCALE_IP_INT_SHIFT 15
5409 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5411 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5413 * \sa TV_VSCALE_IP_INT_MASK
5415 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5416 # define TV_VSCALE_IP_FRAC_SHIFT 0
5418 #define TV_CC_CONTROL _MMIO(0x68090)
5419 # define TV_CC_ENABLE (1 << 31)
5421 * Specifies which field to send the CC data in.
5423 * CC data is usually sent in field 0.
5425 # define TV_CC_FID_MASK (1 << 27)
5426 # define TV_CC_FID_SHIFT 27
5427 /* Sets the horizontal position of the CC data. Usually 135. */
5428 # define TV_CC_HOFF_MASK 0x03ff0000
5429 # define TV_CC_HOFF_SHIFT 16
5430 /* Sets the vertical position of the CC data. Usually 21 */
5431 # define TV_CC_LINE_MASK 0x0000003f
5432 # define TV_CC_LINE_SHIFT 0
5434 #define TV_CC_DATA _MMIO(0x68094)
5435 # define TV_CC_RDY (1 << 31)
5436 /* Second word of CC data to be transmitted. */
5437 # define TV_CC_DATA_2_MASK 0x007f0000
5438 # define TV_CC_DATA_2_SHIFT 16
5439 /* First word of CC data to be transmitted. */
5440 # define TV_CC_DATA_1_MASK 0x0000007f
5441 # define TV_CC_DATA_1_SHIFT 0
5443 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5444 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5445 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5446 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
5449 #define DP_A _MMIO(0x64000) /* eDP */
5450 #define DP_B _MMIO(0x64100)
5451 #define DP_C _MMIO(0x64200)
5452 #define DP_D _MMIO(0x64300)
5454 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5455 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5456 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5458 #define DP_PORT_EN (1 << 31)
5459 #define DP_PIPE_SEL_SHIFT 30
5460 #define DP_PIPE_SEL_MASK (1 << 30)
5461 #define DP_PIPE_SEL(pipe) ((pipe) << 30)
5462 #define DP_PIPE_SEL_SHIFT_IVB 29
5463 #define DP_PIPE_SEL_MASK_IVB (3 << 29)
5464 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
5465 #define DP_PIPE_SEL_SHIFT_CHV 16
5466 #define DP_PIPE_SEL_MASK_CHV (3 << 16)
5467 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
5469 /* Link training mode - select a suitable mode for each stage */
5470 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
5471 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
5472 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5473 #define DP_LINK_TRAIN_OFF (3 << 28)
5474 #define DP_LINK_TRAIN_MASK (3 << 28)
5475 #define DP_LINK_TRAIN_SHIFT 28
5477 /* CPT Link training mode */
5478 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5479 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5480 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5481 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5482 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5483 #define DP_LINK_TRAIN_SHIFT_CPT 8
5485 /* Signal voltages. These are mostly controlled by the other end */
5486 #define DP_VOLTAGE_0_4 (0 << 25)
5487 #define DP_VOLTAGE_0_6 (1 << 25)
5488 #define DP_VOLTAGE_0_8 (2 << 25)
5489 #define DP_VOLTAGE_1_2 (3 << 25)
5490 #define DP_VOLTAGE_MASK (7 << 25)
5491 #define DP_VOLTAGE_SHIFT 25
5493 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5496 #define DP_PRE_EMPHASIS_0 (0 << 22)
5497 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
5498 #define DP_PRE_EMPHASIS_6 (2 << 22)
5499 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
5500 #define DP_PRE_EMPHASIS_MASK (7 << 22)
5501 #define DP_PRE_EMPHASIS_SHIFT 22
5503 /* How many wires to use. I guess 3 was too hard */
5504 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5505 #define DP_PORT_WIDTH_MASK (7 << 19)
5506 #define DP_PORT_WIDTH_SHIFT 19
5508 /* Mystic DPCD version 1.1 special mode */
5509 #define DP_ENHANCED_FRAMING (1 << 18)
5512 #define DP_PLL_FREQ_270MHZ (0 << 16)
5513 #define DP_PLL_FREQ_162MHZ (1 << 16)
5514 #define DP_PLL_FREQ_MASK (3 << 16)
5516 /* locked once port is enabled */
5517 #define DP_PORT_REVERSAL (1 << 15)
5520 #define DP_PLL_ENABLE (1 << 14)
5522 /* sends the clock on lane 15 of the PEG for debug */
5523 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5525 #define DP_SCRAMBLING_DISABLE (1 << 12)
5526 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
5528 /* limit RGB values to avoid confusing TVs */
5529 #define DP_COLOR_RANGE_16_235 (1 << 8)
5531 /* Turn on the audio link */
5532 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5534 /* vs and hs sync polarity */
5535 #define DP_SYNC_VS_HIGH (1 << 4)
5536 #define DP_SYNC_HS_HIGH (1 << 3)
5539 #define DP_DETECTED (1 << 2)
5541 /* The aux channel provides a way to talk to the
5542 * signal sink for DDC etc. Max packet size supported
5543 * is 20 bytes in each direction, hence the 5 fixed
5546 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5547 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5548 #define _DPA_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64018)
5549 #define _DPA_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c)
5550 #define _DPA_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64020)
5551 #define _DPA_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64024)
5553 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5554 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5555 #define _DPB_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64118)
5556 #define _DPB_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c)
5557 #define _DPB_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64120)
5558 #define _DPB_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64124)
5560 #define _DPC_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64210)
5561 #define _DPC_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64214)
5562 #define _DPC_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64218)
5563 #define _DPC_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c)
5564 #define _DPC_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64220)
5565 #define _DPC_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64224)
5567 #define _DPD_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64310)
5568 #define _DPD_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64314)
5569 #define _DPD_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64318)
5570 #define _DPD_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c)
5571 #define _DPD_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64320)
5572 #define _DPD_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64324)
5574 #define _DPE_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64410)
5575 #define _DPE_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64414)
5576 #define _DPE_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64418)
5577 #define _DPE_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c)
5578 #define _DPE_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64420)
5579 #define _DPE_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64424)
5581 #define _DPF_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64510)
5582 #define _DPF_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64514)
5583 #define _DPF_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64518)
5584 #define _DPF_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c)
5585 #define _DPF_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64520)
5586 #define _DPF_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64524)
5588 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5589 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5591 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5592 #define DP_AUX_CH_CTL_DONE (1 << 30)
5593 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5594 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5595 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5596 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5597 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
5598 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
5599 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5600 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5601 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5602 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5603 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5604 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5605 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5606 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5607 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5608 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5609 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5610 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5611 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
5612 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5613 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5614 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5615 #define DP_AUX_CH_CTL_TBT_IO (1 << 11)
5616 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5617 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5618 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5621 * Computing GMCH M and N values for the Display Port link
5623 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5625 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5627 * The GMCH value is used internally
5629 * bytes_per_pixel is the number of bytes coming out of the plane,
5630 * which is after the LUTs, so we want the bytes for our color format.
5631 * For our current usage, this is always 3, one byte for R, G and B.
5633 #define _PIPEA_DATA_M_G4X 0x70050
5634 #define _PIPEB_DATA_M_G4X 0x71050
5636 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5637 #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
5638 #define TU_SIZE_SHIFT 25
5639 #define TU_SIZE_MASK (0x3f << 25)
5641 #define DATA_LINK_M_N_MASK (0xffffff)
5642 #define DATA_LINK_N_MAX (0x800000)
5644 #define _PIPEA_DATA_N_G4X 0x70054
5645 #define _PIPEB_DATA_N_G4X 0x71054
5646 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
5649 * Computing Link M and N values for the Display Port link
5651 * Link M / N = pixel_clock / ls_clk
5653 * (the DP spec calls pixel_clock the 'strm_clk')
5655 * The Link value is transmitted in the Main Stream
5656 * Attributes and VB-ID.
5659 #define _PIPEA_LINK_M_G4X 0x70060
5660 #define _PIPEB_LINK_M_G4X 0x71060
5661 #define PIPEA_DP_LINK_M_MASK (0xffffff)
5663 #define _PIPEA_LINK_N_G4X 0x70064
5664 #define _PIPEB_LINK_N_G4X 0x71064
5665 #define PIPEA_DP_LINK_N_MASK (0xffffff)
5667 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5668 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5669 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5670 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5672 /* Display & cursor control */
5675 #define _PIPEADSL 0x70000
5676 #define DSL_LINEMASK_GEN2 0x00000fff
5677 #define DSL_LINEMASK_GEN3 0x00001fff
5678 #define _PIPEACONF 0x70008
5679 #define PIPECONF_ENABLE (1 << 31)
5680 #define PIPECONF_DISABLE 0
5681 #define PIPECONF_DOUBLE_WIDE (1 << 30)
5682 #define I965_PIPECONF_ACTIVE (1 << 30)
5683 #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
5684 #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
5685 #define PIPECONF_SINGLE_WIDE 0
5686 #define PIPECONF_PIPE_UNLOCKED 0
5687 #define PIPECONF_PIPE_LOCKED (1 << 25)
5688 #define PIPECONF_FORCE_BORDER (1 << 25)
5689 #define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
5690 #define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
5691 #define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
5692 #define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
5693 #define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
5694 #define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */
5695 #define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
5696 #define PIPECONF_GAMMA_MODE_SHIFT 24
5697 #define PIPECONF_INTERLACE_MASK (7 << 21)
5698 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
5699 /* Note that pre-gen3 does not support interlaced display directly. Panel
5700 * fitting must be disabled on pre-ilk for interlaced. */
5701 #define PIPECONF_PROGRESSIVE (0 << 21)
5702 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5703 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
5704 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5705 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
5706 /* Ironlake and later have a complete new set of values for interlaced. PFIT
5707 * means panel fitter required, PF means progressive fetch, DBL means power
5708 * saving pixel doubling. */
5709 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
5710 #define PIPECONF_INTERLACED_ILK (3 << 21)
5711 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
5712 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
5713 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
5714 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
5715 #define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
5716 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
5717 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
5718 #define PIPECONF_BPC_MASK (0x7 << 5)
5719 #define PIPECONF_8BPC (0 << 5)
5720 #define PIPECONF_10BPC (1 << 5)
5721 #define PIPECONF_6BPC (2 << 5)
5722 #define PIPECONF_12BPC (3 << 5)
5723 #define PIPECONF_DITHER_EN (1 << 4)
5724 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5725 #define PIPECONF_DITHER_TYPE_SP (0 << 2)
5726 #define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
5727 #define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
5728 #define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
5729 #define _PIPEASTAT 0x70024
5730 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
5731 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
5732 #define PIPE_CRC_ERROR_ENABLE (1UL << 29)
5733 #define PIPE_CRC_DONE_ENABLE (1UL << 28)
5734 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
5735 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
5736 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
5737 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
5738 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
5739 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
5740 #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
5741 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
5742 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
5743 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
5744 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
5745 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
5746 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
5747 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
5748 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
5749 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
5750 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
5751 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
5752 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
5753 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
5754 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
5755 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
5756 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
5757 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
5758 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
5759 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
5760 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
5761 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
5762 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
5763 #define PIPE_DPST_EVENT_STATUS (1UL << 7)
5764 #define PIPE_A_PSR_STATUS_VLV (1UL << 6)
5765 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
5766 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
5767 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
5768 #define PIPE_B_PSR_STATUS_VLV (1UL << 3)
5769 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
5770 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
5771 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
5772 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
5773 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
5774 #define PIPE_HBLANK_INT_STATUS (1UL << 0)
5775 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
5777 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
5778 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
5780 #define PIPE_A_OFFSET 0x70000
5781 #define PIPE_B_OFFSET 0x71000
5782 #define PIPE_C_OFFSET 0x72000
5783 #define PIPE_D_OFFSET 0x73000
5784 #define CHV_PIPE_C_OFFSET 0x74000
5786 * There's actually no pipe EDP. Some pipe registers have
5787 * simply shifted from the pipe to the transcoder, while
5788 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5789 * to access such registers in transcoder EDP.
5791 #define PIPE_EDP_OFFSET 0x7f000
5793 /* ICL DSI 0 and 1 */
5794 #define PIPE_DSI0_OFFSET 0x7b000
5795 #define PIPE_DSI1_OFFSET 0x7b800
5797 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5798 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
5799 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5800 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5801 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
5803 #define _PIPEAGCMAX 0x70010
5804 #define _PIPEBGCMAX 0x71010
5805 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
5807 #define _PIPE_MISC_A 0x70030
5808 #define _PIPE_MISC_B 0x71030
5809 #define PIPEMISC_YUV420_ENABLE (1 << 27)
5810 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
5811 #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
5812 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
5813 #define PIPEMISC_DITHER_BPC_MASK (7 << 5)
5814 #define PIPEMISC_DITHER_8_BPC (0 << 5)
5815 #define PIPEMISC_DITHER_10_BPC (1 << 5)
5816 #define PIPEMISC_DITHER_6_BPC (2 << 5)
5817 #define PIPEMISC_DITHER_12_BPC (3 << 5)
5818 #define PIPEMISC_DITHER_ENABLE (1 << 4)
5819 #define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
5820 #define PIPEMISC_DITHER_TYPE_SP (0 << 2)
5821 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5823 /* Skylake+ pipe bottom (background) color */
5824 #define _SKL_BOTTOM_COLOR_A 0x70034
5825 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
5826 #define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
5827 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
5829 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5830 #define PIPEB_LINE_COMPARE_INT_EN (1 << 29)
5831 #define PIPEB_HLINE_INT_EN (1 << 28)
5832 #define PIPEB_VBLANK_INT_EN (1 << 27)
5833 #define SPRITED_FLIP_DONE_INT_EN (1 << 26)
5834 #define SPRITEC_FLIP_DONE_INT_EN (1 << 25)
5835 #define PLANEB_FLIP_DONE_INT_EN (1 << 24)
5836 #define PIPE_PSR_INT_EN (1 << 22)
5837 #define PIPEA_LINE_COMPARE_INT_EN (1 << 21)
5838 #define PIPEA_HLINE_INT_EN (1 << 20)
5839 #define PIPEA_VBLANK_INT_EN (1 << 19)
5840 #define SPRITEB_FLIP_DONE_INT_EN (1 << 18)
5841 #define SPRITEA_FLIP_DONE_INT_EN (1 << 17)
5842 #define PLANEA_FLIPDONE_INT_EN (1 << 16)
5843 #define PIPEC_LINE_COMPARE_INT_EN (1 << 13)
5844 #define PIPEC_HLINE_INT_EN (1 << 12)
5845 #define PIPEC_VBLANK_INT_EN (1 << 11)
5846 #define SPRITEF_FLIPDONE_INT_EN (1 << 10)
5847 #define SPRITEE_FLIPDONE_INT_EN (1 << 9)
5848 #define PLANEC_FLIPDONE_INT_EN (1 << 8)
5850 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5851 #define SPRITEF_INVALID_GTT_INT_EN (1 << 27)
5852 #define SPRITEE_INVALID_GTT_INT_EN (1 << 26)
5853 #define PLANEC_INVALID_GTT_INT_EN (1 << 25)
5854 #define CURSORC_INVALID_GTT_INT_EN (1 << 24)
5855 #define CURSORB_INVALID_GTT_INT_EN (1 << 23)
5856 #define CURSORA_INVALID_GTT_INT_EN (1 << 22)
5857 #define SPRITED_INVALID_GTT_INT_EN (1 << 21)
5858 #define SPRITEC_INVALID_GTT_INT_EN (1 << 20)
5859 #define PLANEB_INVALID_GTT_INT_EN (1 << 19)
5860 #define SPRITEB_INVALID_GTT_INT_EN (1 << 18)
5861 #define SPRITEA_INVALID_GTT_INT_EN (1 << 17)
5862 #define PLANEA_INVALID_GTT_INT_EN (1 << 16)
5863 #define DPINVGTT_EN_MASK 0xff0000
5864 #define DPINVGTT_EN_MASK_CHV 0xfff0000
5865 #define SPRITEF_INVALID_GTT_STATUS (1 << 11)
5866 #define SPRITEE_INVALID_GTT_STATUS (1 << 10)
5867 #define PLANEC_INVALID_GTT_STATUS (1 << 9)
5868 #define CURSORC_INVALID_GTT_STATUS (1 << 8)
5869 #define CURSORB_INVALID_GTT_STATUS (1 << 7)
5870 #define CURSORA_INVALID_GTT_STATUS (1 << 6)
5871 #define SPRITED_INVALID_GTT_STATUS (1 << 5)
5872 #define SPRITEC_INVALID_GTT_STATUS (1 << 4)
5873 #define PLANEB_INVALID_GTT_STATUS (1 << 3)
5874 #define SPRITEB_INVALID_GTT_STATUS (1 << 2)
5875 #define SPRITEA_INVALID_GTT_STATUS (1 << 1)
5876 #define PLANEA_INVALID_GTT_STATUS (1 << 0)
5877 #define DPINVGTT_STATUS_MASK 0xff
5878 #define DPINVGTT_STATUS_MASK_CHV 0xfff
5880 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
5881 #define DSPARB_CSTART_MASK (0x7f << 7)
5882 #define DSPARB_CSTART_SHIFT 7
5883 #define DSPARB_BSTART_MASK (0x7f)
5884 #define DSPARB_BSTART_SHIFT 0
5885 #define DSPARB_BEND_SHIFT 9 /* on 855 */
5886 #define DSPARB_AEND_SHIFT 0
5887 #define DSPARB_SPRITEA_SHIFT_VLV 0
5888 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
5889 #define DSPARB_SPRITEB_SHIFT_VLV 8
5890 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
5891 #define DSPARB_SPRITEC_SHIFT_VLV 16
5892 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
5893 #define DSPARB_SPRITED_SHIFT_VLV 24
5894 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
5895 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5896 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
5897 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
5898 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
5899 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
5900 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
5901 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
5902 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
5903 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
5904 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
5905 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
5906 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
5907 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
5908 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5909 #define DSPARB_SPRITEE_SHIFT_VLV 0
5910 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
5911 #define DSPARB_SPRITEF_SHIFT_VLV 8
5912 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
5914 /* pnv/gen4/g4x/vlv/chv */
5915 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
5916 #define DSPFW_SR_SHIFT 23
5917 #define DSPFW_SR_MASK (0x1ff << 23)
5918 #define DSPFW_CURSORB_SHIFT 16
5919 #define DSPFW_CURSORB_MASK (0x3f << 16)
5920 #define DSPFW_PLANEB_SHIFT 8
5921 #define DSPFW_PLANEB_MASK (0x7f << 8)
5922 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
5923 #define DSPFW_PLANEA_SHIFT 0
5924 #define DSPFW_PLANEA_MASK (0x7f << 0)
5925 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
5926 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
5927 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
5928 #define DSPFW_FBC_SR_SHIFT 28
5929 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
5930 #define DSPFW_FBC_HPLL_SR_SHIFT 24
5931 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
5932 #define DSPFW_SPRITEB_SHIFT (16)
5933 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
5934 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
5935 #define DSPFW_CURSORA_SHIFT 8
5936 #define DSPFW_CURSORA_MASK (0x3f << 8)
5937 #define DSPFW_PLANEC_OLD_SHIFT 0
5938 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
5939 #define DSPFW_SPRITEA_SHIFT 0
5940 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
5941 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
5942 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
5943 #define DSPFW_HPLL_SR_EN (1 << 31)
5944 #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
5945 #define DSPFW_CURSOR_SR_SHIFT 24
5946 #define DSPFW_CURSOR_SR_MASK (0x3f << 24)
5947 #define DSPFW_HPLL_CURSOR_SHIFT 16
5948 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
5949 #define DSPFW_HPLL_SR_SHIFT 0
5950 #define DSPFW_HPLL_SR_MASK (0x1ff << 0)
5953 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5954 #define DSPFW_SPRITEB_WM1_SHIFT 16
5955 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
5956 #define DSPFW_CURSORA_WM1_SHIFT 8
5957 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
5958 #define DSPFW_SPRITEA_WM1_SHIFT 0
5959 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
5960 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5961 #define DSPFW_PLANEB_WM1_SHIFT 24
5962 #define DSPFW_PLANEB_WM1_MASK (0xff << 24)
5963 #define DSPFW_PLANEA_WM1_SHIFT 16
5964 #define DSPFW_PLANEA_WM1_MASK (0xff << 16)
5965 #define DSPFW_CURSORB_WM1_SHIFT 8
5966 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
5967 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
5968 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
5969 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5970 #define DSPFW_SR_WM1_SHIFT 0
5971 #define DSPFW_SR_WM1_MASK (0x1ff << 0)
5972 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5973 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5974 #define DSPFW_SPRITED_WM1_SHIFT 24
5975 #define DSPFW_SPRITED_WM1_MASK (0xff << 24)
5976 #define DSPFW_SPRITED_SHIFT 16
5977 #define DSPFW_SPRITED_MASK_VLV (0xff << 16)
5978 #define DSPFW_SPRITEC_WM1_SHIFT 8
5979 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
5980 #define DSPFW_SPRITEC_SHIFT 0
5981 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
5982 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5983 #define DSPFW_SPRITEF_WM1_SHIFT 24
5984 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
5985 #define DSPFW_SPRITEF_SHIFT 16
5986 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
5987 #define DSPFW_SPRITEE_WM1_SHIFT 8
5988 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
5989 #define DSPFW_SPRITEE_SHIFT 0
5990 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
5991 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5992 #define DSPFW_PLANEC_WM1_SHIFT 24
5993 #define DSPFW_PLANEC_WM1_MASK (0xff << 24)
5994 #define DSPFW_PLANEC_SHIFT 16
5995 #define DSPFW_PLANEC_MASK_VLV (0xff << 16)
5996 #define DSPFW_CURSORC_WM1_SHIFT 8
5997 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
5998 #define DSPFW_CURSORC_SHIFT 0
5999 #define DSPFW_CURSORC_MASK (0x3f << 0)
6001 /* vlv/chv high order bits */
6002 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
6003 #define DSPFW_SR_HI_SHIFT 24
6004 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
6005 #define DSPFW_SPRITEF_HI_SHIFT 23
6006 #define DSPFW_SPRITEF_HI_MASK (1 << 23)
6007 #define DSPFW_SPRITEE_HI_SHIFT 22
6008 #define DSPFW_SPRITEE_HI_MASK (1 << 22)
6009 #define DSPFW_PLANEC_HI_SHIFT 21
6010 #define DSPFW_PLANEC_HI_MASK (1 << 21)
6011 #define DSPFW_SPRITED_HI_SHIFT 20
6012 #define DSPFW_SPRITED_HI_MASK (1 << 20)
6013 #define DSPFW_SPRITEC_HI_SHIFT 16
6014 #define DSPFW_SPRITEC_HI_MASK (1 << 16)
6015 #define DSPFW_PLANEB_HI_SHIFT 12
6016 #define DSPFW_PLANEB_HI_MASK (1 << 12)
6017 #define DSPFW_SPRITEB_HI_SHIFT 8
6018 #define DSPFW_SPRITEB_HI_MASK (1 << 8)
6019 #define DSPFW_SPRITEA_HI_SHIFT 4
6020 #define DSPFW_SPRITEA_HI_MASK (1 << 4)
6021 #define DSPFW_PLANEA_HI_SHIFT 0
6022 #define DSPFW_PLANEA_HI_MASK (1 << 0)
6023 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
6024 #define DSPFW_SR_WM1_HI_SHIFT 24
6025 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
6026 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
6027 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
6028 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
6029 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
6030 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
6031 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
6032 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
6033 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
6034 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
6035 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
6036 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
6037 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
6038 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
6039 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
6040 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
6041 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
6042 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
6043 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
6045 /* drain latency register values*/
6046 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
6047 #define DDL_CURSOR_SHIFT 24
6048 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
6049 #define DDL_PLANE_SHIFT 0
6050 #define DDL_PRECISION_HIGH (1 << 7)
6051 #define DDL_PRECISION_LOW (0 << 7)
6052 #define DRAIN_LATENCY_MASK 0x7f
6054 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
6055 #define CBR_PND_DEADLINE_DISABLE (1 << 31)
6056 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
6058 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
6059 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
6061 /* FIFO watermark sizes etc */
6062 #define G4X_FIFO_LINE_SIZE 64
6063 #define I915_FIFO_LINE_SIZE 64
6064 #define I830_FIFO_LINE_SIZE 32
6066 #define VALLEYVIEW_FIFO_SIZE 255
6067 #define G4X_FIFO_SIZE 127
6068 #define I965_FIFO_SIZE 512
6069 #define I945_FIFO_SIZE 127
6070 #define I915_FIFO_SIZE 95
6071 #define I855GM_FIFO_SIZE 127 /* In cachelines */
6072 #define I830_FIFO_SIZE 95
6074 #define VALLEYVIEW_MAX_WM 0xff
6075 #define G4X_MAX_WM 0x3f
6076 #define I915_MAX_WM 0x3f
6078 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
6079 #define PINEVIEW_FIFO_LINE_SIZE 64
6080 #define PINEVIEW_MAX_WM 0x1ff
6081 #define PINEVIEW_DFT_WM 0x3f
6082 #define PINEVIEW_DFT_HPLLOFF_WM 0
6083 #define PINEVIEW_GUARD_WM 10
6084 #define PINEVIEW_CURSOR_FIFO 64
6085 #define PINEVIEW_CURSOR_MAX_WM 0x3f
6086 #define PINEVIEW_CURSOR_DFT_WM 0
6087 #define PINEVIEW_CURSOR_GUARD_WM 5
6089 #define VALLEYVIEW_CURSOR_MAX_WM 64
6090 #define I965_CURSOR_FIFO 64
6091 #define I965_CURSOR_MAX_WM 32
6092 #define I965_CURSOR_DFT_WM 8
6094 /* Watermark register definitions for SKL */
6095 #define _CUR_WM_A_0 0x70140
6096 #define _CUR_WM_B_0 0x71140
6097 #define _PLANE_WM_1_A_0 0x70240
6098 #define _PLANE_WM_1_B_0 0x71240
6099 #define _PLANE_WM_2_A_0 0x70340
6100 #define _PLANE_WM_2_B_0 0x71340
6101 #define _PLANE_WM_TRANS_1_A_0 0x70268
6102 #define _PLANE_WM_TRANS_1_B_0 0x71268
6103 #define _PLANE_WM_TRANS_2_A_0 0x70368
6104 #define _PLANE_WM_TRANS_2_B_0 0x71368
6105 #define _CUR_WM_TRANS_A_0 0x70168
6106 #define _CUR_WM_TRANS_B_0 0x71168
6107 #define PLANE_WM_EN (1 << 31)
6108 #define PLANE_WM_IGNORE_LINES (1 << 30)
6109 #define PLANE_WM_LINES_SHIFT 14
6110 #define PLANE_WM_LINES_MASK 0x1f
6111 #define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
6113 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
6114 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
6115 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
6117 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6118 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
6119 #define _PLANE_WM_BASE(pipe, plane) \
6120 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6121 #define PLANE_WM(pipe, plane, level) \
6122 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6123 #define _PLANE_WM_TRANS_1(pipe) \
6124 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
6125 #define _PLANE_WM_TRANS_2(pipe) \
6126 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
6127 #define PLANE_WM_TRANS(pipe, plane) \
6128 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
6130 /* define the Watermark register on Ironlake */
6131 #define WM0_PIPEA_ILK _MMIO(0x45100)
6132 #define WM0_PIPE_PLANE_MASK (0xffff << 16)
6133 #define WM0_PIPE_PLANE_SHIFT 16
6134 #define WM0_PIPE_SPRITE_MASK (0xff << 8)
6135 #define WM0_PIPE_SPRITE_SHIFT 8
6136 #define WM0_PIPE_CURSOR_MASK (0xff)
6138 #define WM0_PIPEB_ILK _MMIO(0x45104)
6139 #define WM0_PIPEC_IVB _MMIO(0x45200)
6140 #define WM1_LP_ILK _MMIO(0x45108)
6141 #define WM1_LP_SR_EN (1 << 31)
6142 #define WM1_LP_LATENCY_SHIFT 24
6143 #define WM1_LP_LATENCY_MASK (0x7f << 24)
6144 #define WM1_LP_FBC_MASK (0xf << 20)
6145 #define WM1_LP_FBC_SHIFT 20
6146 #define WM1_LP_FBC_SHIFT_BDW 19
6147 #define WM1_LP_SR_MASK (0x7ff << 8)
6148 #define WM1_LP_SR_SHIFT 8
6149 #define WM1_LP_CURSOR_MASK (0xff)
6150 #define WM2_LP_ILK _MMIO(0x4510c)
6151 #define WM2_LP_EN (1 << 31)
6152 #define WM3_LP_ILK _MMIO(0x45110)
6153 #define WM3_LP_EN (1 << 31)
6154 #define WM1S_LP_ILK _MMIO(0x45120)
6155 #define WM2S_LP_IVB _MMIO(0x45124)
6156 #define WM3S_LP_IVB _MMIO(0x45128)
6157 #define WM1S_LP_EN (1 << 31)
6159 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6160 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6161 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6163 /* Memory latency timer register */
6164 #define MLTR_ILK _MMIO(0x11222)
6165 #define MLTR_WM1_SHIFT 0
6166 #define MLTR_WM2_SHIFT 8
6167 /* the unit of memory self-refresh latency time is 0.5us */
6168 #define ILK_SRLT_MASK 0x3f
6171 /* the address where we get all kinds of latency value */
6172 #define SSKPD _MMIO(0x5d10)
6173 #define SSKPD_WM_MASK 0x3f
6174 #define SSKPD_WM0_SHIFT 0
6175 #define SSKPD_WM1_SHIFT 8
6176 #define SSKPD_WM2_SHIFT 16
6177 #define SSKPD_WM3_SHIFT 24
6180 * The two pipe frame counter registers are not synchronized, so
6181 * reading a stable value is somewhat tricky. The following code
6185 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6186 * PIPE_FRAME_HIGH_SHIFT;
6187 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6188 * PIPE_FRAME_LOW_SHIFT);
6189 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6190 * PIPE_FRAME_HIGH_SHIFT);
6191 * } while (high1 != high2);
6192 * frame = (high1 << 8) | low1;
6194 #define _PIPEAFRAMEHIGH 0x70040
6195 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
6196 #define PIPE_FRAME_HIGH_SHIFT 0
6197 #define _PIPEAFRAMEPIXEL 0x70044
6198 #define PIPE_FRAME_LOW_MASK 0xff000000
6199 #define PIPE_FRAME_LOW_SHIFT 24
6200 #define PIPE_PIXEL_MASK 0x00ffffff
6201 #define PIPE_PIXEL_SHIFT 0
6202 /* GM45+ just has to be different */
6203 #define _PIPEA_FRMCOUNT_G4X 0x70040
6204 #define _PIPEA_FLIPCOUNT_G4X 0x70044
6205 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6206 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6208 /* Cursor A & B regs */
6209 #define _CURACNTR 0x70080
6210 /* Old style CUR*CNTR flags (desktop 8xx) */
6211 #define CURSOR_ENABLE 0x80000000
6212 #define CURSOR_GAMMA_ENABLE 0x40000000
6213 #define CURSOR_STRIDE_SHIFT 28
6214 #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6215 #define CURSOR_FORMAT_SHIFT 24
6216 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
6217 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
6218 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
6219 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
6220 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
6221 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
6222 /* New style CUR*CNTR flags */
6223 #define MCURSOR_MODE 0x27
6224 #define MCURSOR_MODE_DISABLE 0x00
6225 #define MCURSOR_MODE_128_32B_AX 0x02
6226 #define MCURSOR_MODE_256_32B_AX 0x03
6227 #define MCURSOR_MODE_64_32B_AX 0x07
6228 #define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6229 #define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6230 #define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6231 #define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
6232 #define MCURSOR_PIPE_SELECT_SHIFT 28
6233 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6234 #define MCURSOR_GAMMA_ENABLE (1 << 26)
6235 #define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6236 #define MCURSOR_ROTATE_180 (1 << 15)
6237 #define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
6238 #define _CURABASE 0x70084
6239 #define _CURAPOS 0x70088
6240 #define CURSOR_POS_MASK 0x007FF
6241 #define CURSOR_POS_SIGN 0x8000
6242 #define CURSOR_X_SHIFT 0
6243 #define CURSOR_Y_SHIFT 16
6244 #define CURSIZE _MMIO(0x700a0) /* 845/865 */
6245 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
6246 #define CUR_FBC_CTL_EN (1 << 31)
6247 #define _CURASURFLIVE 0x700ac /* g4x+ */
6248 #define _CURBCNTR 0x700c0
6249 #define _CURBBASE 0x700c4
6250 #define _CURBPOS 0x700c8
6252 #define _CURBCNTR_IVB 0x71080
6253 #define _CURBBASE_IVB 0x71084
6254 #define _CURBPOS_IVB 0x71088
6256 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6257 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6258 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6259 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6260 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6262 #define CURSOR_A_OFFSET 0x70080
6263 #define CURSOR_B_OFFSET 0x700c0
6264 #define CHV_CURSOR_C_OFFSET 0x700e0
6265 #define IVB_CURSOR_B_OFFSET 0x71080
6266 #define IVB_CURSOR_C_OFFSET 0x72080
6268 /* Display A control */
6269 #define _DSPACNTR 0x70180
6270 #define DISPLAY_PLANE_ENABLE (1 << 31)
6271 #define DISPLAY_PLANE_DISABLE 0
6272 #define DISPPLANE_GAMMA_ENABLE (1 << 30)
6273 #define DISPPLANE_GAMMA_DISABLE 0
6274 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
6275 #define DISPPLANE_YUV422 (0x0 << 26)
6276 #define DISPPLANE_8BPP (0x2 << 26)
6277 #define DISPPLANE_BGRA555 (0x3 << 26)
6278 #define DISPPLANE_BGRX555 (0x4 << 26)
6279 #define DISPPLANE_BGRX565 (0x5 << 26)
6280 #define DISPPLANE_BGRX888 (0x6 << 26)
6281 #define DISPPLANE_BGRA888 (0x7 << 26)
6282 #define DISPPLANE_RGBX101010 (0x8 << 26)
6283 #define DISPPLANE_RGBA101010 (0x9 << 26)
6284 #define DISPPLANE_BGRX101010 (0xa << 26)
6285 #define DISPPLANE_RGBX161616 (0xc << 26)
6286 #define DISPPLANE_RGBX888 (0xe << 26)
6287 #define DISPPLANE_RGBA888 (0xf << 26)
6288 #define DISPPLANE_STEREO_ENABLE (1 << 25)
6289 #define DISPPLANE_STEREO_DISABLE 0
6290 #define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6291 #define DISPPLANE_SEL_PIPE_SHIFT 24
6292 #define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6293 #define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6294 #define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
6295 #define DISPPLANE_SRC_KEY_DISABLE 0
6296 #define DISPPLANE_LINE_DOUBLE (1 << 20)
6297 #define DISPPLANE_NO_LINE_DOUBLE 0
6298 #define DISPPLANE_STEREO_POLARITY_FIRST 0
6299 #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
6300 #define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
6301 #define DISPPLANE_ROTATE_180 (1 << 15)
6302 #define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
6303 #define DISPPLANE_TILED (1 << 10)
6304 #define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
6305 #define _DSPAADDR 0x70184
6306 #define _DSPASTRIDE 0x70188
6307 #define _DSPAPOS 0x7018C /* reserved */
6308 #define _DSPASIZE 0x70190
6309 #define _DSPASURF 0x7019C /* 965+ only */
6310 #define _DSPATILEOFF 0x701A4 /* 965+ only */
6311 #define _DSPAOFFSET 0x701A4 /* HSW */
6312 #define _DSPASURFLIVE 0x701AC
6313 #define _DSPAGAMC 0x701E0
6315 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6316 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6317 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6318 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6319 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6320 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6321 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6322 #define DSPLINOFF(plane) DSPADDR(plane)
6323 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6324 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6325 #define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
6327 /* CHV pipe B blender and primary plane */
6328 #define _CHV_BLEND_A 0x60a00
6329 #define CHV_BLEND_LEGACY (0 << 30)
6330 #define CHV_BLEND_ANDROID (1 << 30)
6331 #define CHV_BLEND_MPO (2 << 30)
6332 #define CHV_BLEND_MASK (3 << 30)
6333 #define _CHV_CANVAS_A 0x60a04
6334 #define _PRIMPOS_A 0x60a08
6335 #define _PRIMSIZE_A 0x60a0c
6336 #define _PRIMCNSTALPHA_A 0x60a10
6337 #define PRIM_CONST_ALPHA_ENABLE (1 << 31)
6339 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6340 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6341 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6342 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6343 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6345 /* Display/Sprite base address macros */
6346 #define DISP_BASEADDR_MASK (0xfffff000)
6347 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
6348 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
6361 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6362 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6363 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6364 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6367 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6368 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6369 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6370 #define _PIPEBFRAMEHIGH 0x71040
6371 #define _PIPEBFRAMEPIXEL 0x71044
6372 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6373 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6376 /* Display B control */
6377 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6378 #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
6379 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
6380 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6381 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6382 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6383 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6384 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6385 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6386 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6387 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6388 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6389 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6391 /* ICL DSI 0 and 1 */
6392 #define _PIPEDSI0CONF 0x7b008
6393 #define _PIPEDSI1CONF 0x7b808
6395 /* Sprite A control */
6396 #define _DVSACNTR 0x72180
6397 #define DVS_ENABLE (1 << 31)
6398 #define DVS_GAMMA_ENABLE (1 << 30)
6399 #define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
6400 #define DVS_PIXFORMAT_MASK (3 << 25)
6401 #define DVS_FORMAT_YUV422 (0 << 25)
6402 #define DVS_FORMAT_RGBX101010 (1 << 25)
6403 #define DVS_FORMAT_RGBX888 (2 << 25)
6404 #define DVS_FORMAT_RGBX161616 (3 << 25)
6405 #define DVS_PIPE_CSC_ENABLE (1 << 24)
6406 #define DVS_SOURCE_KEY (1 << 22)
6407 #define DVS_RGB_ORDER_XBGR (1 << 20)
6408 #define DVS_YUV_FORMAT_BT709 (1 << 18)
6409 #define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6410 #define DVS_YUV_ORDER_YUYV (0 << 16)
6411 #define DVS_YUV_ORDER_UYVY (1 << 16)
6412 #define DVS_YUV_ORDER_YVYU (2 << 16)
6413 #define DVS_YUV_ORDER_VYUY (3 << 16)
6414 #define DVS_ROTATE_180 (1 << 15)
6415 #define DVS_DEST_KEY (1 << 2)
6416 #define DVS_TRICKLE_FEED_DISABLE (1 << 14)
6417 #define DVS_TILED (1 << 10)
6418 #define _DVSALINOFF 0x72184
6419 #define _DVSASTRIDE 0x72188
6420 #define _DVSAPOS 0x7218c
6421 #define _DVSASIZE 0x72190
6422 #define _DVSAKEYVAL 0x72194
6423 #define _DVSAKEYMSK 0x72198
6424 #define _DVSASURF 0x7219c
6425 #define _DVSAKEYMAXVAL 0x721a0
6426 #define _DVSATILEOFF 0x721a4
6427 #define _DVSASURFLIVE 0x721ac
6428 #define _DVSAGAMC_G4X 0x721e0 /* g4x */
6429 #define _DVSASCALE 0x72204
6430 #define DVS_SCALE_ENABLE (1 << 31)
6431 #define DVS_FILTER_MASK (3 << 29)
6432 #define DVS_FILTER_MEDIUM (0 << 29)
6433 #define DVS_FILTER_ENHANCING (1 << 29)
6434 #define DVS_FILTER_SOFTENING (2 << 29)
6435 #define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6436 #define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6437 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
6438 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
6440 #define _DVSBCNTR 0x73180
6441 #define _DVSBLINOFF 0x73184
6442 #define _DVSBSTRIDE 0x73188
6443 #define _DVSBPOS 0x7318c
6444 #define _DVSBSIZE 0x73190
6445 #define _DVSBKEYVAL 0x73194
6446 #define _DVSBKEYMSK 0x73198
6447 #define _DVSBSURF 0x7319c
6448 #define _DVSBKEYMAXVAL 0x731a0
6449 #define _DVSBTILEOFF 0x731a4
6450 #define _DVSBSURFLIVE 0x731ac
6451 #define _DVSBGAMC_G4X 0x731e0 /* g4x */
6452 #define _DVSBSCALE 0x73204
6453 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
6454 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
6456 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6457 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6458 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6459 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6460 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6461 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6462 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6463 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6464 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6465 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6466 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6467 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6468 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
6469 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
6470 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
6472 #define _SPRA_CTL 0x70280
6473 #define SPRITE_ENABLE (1 << 31)
6474 #define SPRITE_GAMMA_ENABLE (1 << 30)
6475 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6476 #define SPRITE_PIXFORMAT_MASK (7 << 25)
6477 #define SPRITE_FORMAT_YUV422 (0 << 25)
6478 #define SPRITE_FORMAT_RGBX101010 (1 << 25)
6479 #define SPRITE_FORMAT_RGBX888 (2 << 25)
6480 #define SPRITE_FORMAT_RGBX161616 (3 << 25)
6481 #define SPRITE_FORMAT_YUV444 (4 << 25)
6482 #define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
6483 #define SPRITE_PIPE_CSC_ENABLE (1 << 24)
6484 #define SPRITE_SOURCE_KEY (1 << 22)
6485 #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
6486 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
6487 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
6488 #define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
6489 #define SPRITE_YUV_ORDER_YUYV (0 << 16)
6490 #define SPRITE_YUV_ORDER_UYVY (1 << 16)
6491 #define SPRITE_YUV_ORDER_YVYU (2 << 16)
6492 #define SPRITE_YUV_ORDER_VYUY (3 << 16)
6493 #define SPRITE_ROTATE_180 (1 << 15)
6494 #define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
6495 #define SPRITE_INT_GAMMA_DISABLE (1 << 13)
6496 #define SPRITE_TILED (1 << 10)
6497 #define SPRITE_DEST_KEY (1 << 2)
6498 #define _SPRA_LINOFF 0x70284
6499 #define _SPRA_STRIDE 0x70288
6500 #define _SPRA_POS 0x7028c
6501 #define _SPRA_SIZE 0x70290
6502 #define _SPRA_KEYVAL 0x70294
6503 #define _SPRA_KEYMSK 0x70298
6504 #define _SPRA_SURF 0x7029c
6505 #define _SPRA_KEYMAX 0x702a0
6506 #define _SPRA_TILEOFF 0x702a4
6507 #define _SPRA_OFFSET 0x702a4
6508 #define _SPRA_SURFLIVE 0x702ac
6509 #define _SPRA_SCALE 0x70304
6510 #define SPRITE_SCALE_ENABLE (1 << 31)
6511 #define SPRITE_FILTER_MASK (3 << 29)
6512 #define SPRITE_FILTER_MEDIUM (0 << 29)
6513 #define SPRITE_FILTER_ENHANCING (1 << 29)
6514 #define SPRITE_FILTER_SOFTENING (2 << 29)
6515 #define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6516 #define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
6517 #define _SPRA_GAMC 0x70400
6518 #define _SPRA_GAMC16 0x70440
6519 #define _SPRA_GAMC17 0x7044c
6521 #define _SPRB_CTL 0x71280
6522 #define _SPRB_LINOFF 0x71284
6523 #define _SPRB_STRIDE 0x71288
6524 #define _SPRB_POS 0x7128c
6525 #define _SPRB_SIZE 0x71290
6526 #define _SPRB_KEYVAL 0x71294
6527 #define _SPRB_KEYMSK 0x71298
6528 #define _SPRB_SURF 0x7129c
6529 #define _SPRB_KEYMAX 0x712a0
6530 #define _SPRB_TILEOFF 0x712a4
6531 #define _SPRB_OFFSET 0x712a4
6532 #define _SPRB_SURFLIVE 0x712ac
6533 #define _SPRB_SCALE 0x71304
6534 #define _SPRB_GAMC 0x71400
6535 #define _SPRB_GAMC16 0x71440
6536 #define _SPRB_GAMC17 0x7144c
6538 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6539 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6540 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6541 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6542 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6543 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6544 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6545 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6546 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6547 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6548 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6549 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6550 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
6551 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
6552 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
6553 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6555 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6556 #define SP_ENABLE (1 << 31)
6557 #define SP_GAMMA_ENABLE (1 << 30)
6558 #define SP_PIXFORMAT_MASK (0xf << 26)
6559 #define SP_FORMAT_YUV422 (0 << 26)
6560 #define SP_FORMAT_BGR565 (5 << 26)
6561 #define SP_FORMAT_BGRX8888 (6 << 26)
6562 #define SP_FORMAT_BGRA8888 (7 << 26)
6563 #define SP_FORMAT_RGBX1010102 (8 << 26)
6564 #define SP_FORMAT_RGBA1010102 (9 << 26)
6565 #define SP_FORMAT_RGBX8888 (0xe << 26)
6566 #define SP_FORMAT_RGBA8888 (0xf << 26)
6567 #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
6568 #define SP_SOURCE_KEY (1 << 22)
6569 #define SP_YUV_FORMAT_BT709 (1 << 18)
6570 #define SP_YUV_BYTE_ORDER_MASK (3 << 16)
6571 #define SP_YUV_ORDER_YUYV (0 << 16)
6572 #define SP_YUV_ORDER_UYVY (1 << 16)
6573 #define SP_YUV_ORDER_YVYU (2 << 16)
6574 #define SP_YUV_ORDER_VYUY (3 << 16)
6575 #define SP_ROTATE_180 (1 << 15)
6576 #define SP_TILED (1 << 10)
6577 #define SP_MIRROR (1 << 8) /* CHV pipe B */
6578 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6579 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6580 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6581 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6582 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6583 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6584 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6585 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6586 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6587 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6588 #define SP_CONST_ALPHA_ENABLE (1 << 31)
6589 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
6590 #define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
6591 #define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
6592 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6593 #define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
6594 #define SP_SH_COS(x) (x) /* u3.7 */
6595 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
6597 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6598 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6599 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6600 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6601 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6602 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6603 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6604 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6605 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6606 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6607 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6608 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6609 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6610 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
6612 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6613 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6614 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6615 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
6617 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6618 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6619 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6620 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6621 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6622 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6623 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6624 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6625 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6626 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6627 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6628 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6629 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6630 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
6633 * CHV pipe B sprite CSC
6635 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6636 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6637 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6639 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6640 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6642 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6643 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6644 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6645 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
6646 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
6648 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6649 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6650 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6651 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6652 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6653 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
6654 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
6656 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6657 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6658 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6659 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
6660 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
6662 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6663 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6664 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6665 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
6666 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
6668 /* Skylake plane registers */
6670 #define _PLANE_CTL_1_A 0x70180
6671 #define _PLANE_CTL_2_A 0x70280
6672 #define _PLANE_CTL_3_A 0x70380
6673 #define PLANE_CTL_ENABLE (1 << 31)
6674 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
6675 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6677 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6678 * expanded to include bit 23 as well. However, the shift-24 based values
6679 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6681 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
6682 #define PLANE_CTL_FORMAT_YUV422 (0 << 24)
6683 #define PLANE_CTL_FORMAT_NV12 (1 << 24)
6684 #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
6685 #define PLANE_CTL_FORMAT_P010 (3 << 24)
6686 #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
6687 #define PLANE_CTL_FORMAT_P012 (5 << 24)
6688 #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
6689 #define PLANE_CTL_FORMAT_P016 (7 << 24)
6690 #define PLANE_CTL_FORMAT_AYUV (8 << 24)
6691 #define PLANE_CTL_FORMAT_INDEXED (12 << 24)
6692 #define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
6693 #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
6694 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
6695 #define PLANE_CTL_FORMAT_Y210 (1 << 23)
6696 #define PLANE_CTL_FORMAT_Y212 (3 << 23)
6697 #define PLANE_CTL_FORMAT_Y216 (5 << 23)
6698 #define PLANE_CTL_FORMAT_Y410 (7 << 23)
6699 #define PLANE_CTL_FORMAT_Y412 (9 << 23)
6700 #define PLANE_CTL_FORMAT_Y416 (0xb << 23)
6701 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6702 #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
6703 #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
6704 #define PLANE_CTL_ORDER_BGRX (0 << 20)
6705 #define PLANE_CTL_ORDER_RGBX (1 << 20)
6706 #define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
6707 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6708 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6709 #define PLANE_CTL_YUV422_YUYV (0 << 16)
6710 #define PLANE_CTL_YUV422_UYVY (1 << 16)
6711 #define PLANE_CTL_YUV422_YVYU (2 << 16)
6712 #define PLANE_CTL_YUV422_VYUY (3 << 16)
6713 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
6714 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
6715 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
6716 #define PLANE_CTL_TILED_MASK (0x7 << 10)
6717 #define PLANE_CTL_TILED_LINEAR (0 << 10)
6718 #define PLANE_CTL_TILED_X (1 << 10)
6719 #define PLANE_CTL_TILED_Y (4 << 10)
6720 #define PLANE_CTL_TILED_YF (5 << 10)
6721 #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
6722 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
6723 #define PLANE_CTL_ALPHA_DISABLE (0 << 4)
6724 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
6725 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
6726 #define PLANE_CTL_ROTATE_MASK 0x3
6727 #define PLANE_CTL_ROTATE_0 0x0
6728 #define PLANE_CTL_ROTATE_90 0x1
6729 #define PLANE_CTL_ROTATE_180 0x2
6730 #define PLANE_CTL_ROTATE_270 0x3
6731 #define _PLANE_STRIDE_1_A 0x70188
6732 #define _PLANE_STRIDE_2_A 0x70288
6733 #define _PLANE_STRIDE_3_A 0x70388
6734 #define _PLANE_POS_1_A 0x7018c
6735 #define _PLANE_POS_2_A 0x7028c
6736 #define _PLANE_POS_3_A 0x7038c
6737 #define _PLANE_SIZE_1_A 0x70190
6738 #define _PLANE_SIZE_2_A 0x70290
6739 #define _PLANE_SIZE_3_A 0x70390
6740 #define _PLANE_SURF_1_A 0x7019c
6741 #define _PLANE_SURF_2_A 0x7029c
6742 #define _PLANE_SURF_3_A 0x7039c
6743 #define _PLANE_OFFSET_1_A 0x701a4
6744 #define _PLANE_OFFSET_2_A 0x702a4
6745 #define _PLANE_OFFSET_3_A 0x703a4
6746 #define _PLANE_KEYVAL_1_A 0x70194
6747 #define _PLANE_KEYVAL_2_A 0x70294
6748 #define _PLANE_KEYMSK_1_A 0x70198
6749 #define _PLANE_KEYMSK_2_A 0x70298
6750 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
6751 #define _PLANE_KEYMAX_1_A 0x701a0
6752 #define _PLANE_KEYMAX_2_A 0x702a0
6753 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
6754 #define _PLANE_AUX_DIST_1_A 0x701c0
6755 #define _PLANE_AUX_DIST_2_A 0x702c0
6756 #define _PLANE_AUX_OFFSET_1_A 0x701c4
6757 #define _PLANE_AUX_OFFSET_2_A 0x702c4
6758 #define _PLANE_CUS_CTL_1_A 0x701c8
6759 #define _PLANE_CUS_CTL_2_A 0x702c8
6760 #define PLANE_CUS_ENABLE (1 << 31)
6761 #define PLANE_CUS_PLANE_6 (0 << 30)
6762 #define PLANE_CUS_PLANE_7 (1 << 30)
6763 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
6764 #define PLANE_CUS_HPHASE_0 (0 << 16)
6765 #define PLANE_CUS_HPHASE_0_25 (1 << 16)
6766 #define PLANE_CUS_HPHASE_0_5 (2 << 16)
6767 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
6768 #define PLANE_CUS_VPHASE_0 (0 << 12)
6769 #define PLANE_CUS_VPHASE_0_25 (1 << 12)
6770 #define PLANE_CUS_VPHASE_0_5 (2 << 12)
6771 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6772 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6773 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6774 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
6775 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6776 #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
6777 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
6778 #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
6779 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
6780 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
6781 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
6782 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
6783 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
6784 #define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
6785 #define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
6786 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
6787 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
6788 #define _PLANE_BUF_CFG_1_A 0x7027c
6789 #define _PLANE_BUF_CFG_2_A 0x7037c
6790 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
6791 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
6793 /* Input CSC Register Definitions */
6794 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
6795 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
6797 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
6798 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
6800 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
6801 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
6802 _PLANE_INPUT_CSC_RY_GY_1_B)
6803 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
6804 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
6805 _PLANE_INPUT_CSC_RY_GY_2_B)
6807 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
6808 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
6809 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
6811 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
6812 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
6814 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
6815 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
6817 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
6818 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
6819 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
6820 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
6821 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
6822 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
6823 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
6824 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
6825 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
6827 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
6828 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
6830 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
6831 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
6833 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
6834 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
6835 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
6836 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
6837 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
6838 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
6839 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
6840 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
6841 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
6843 #define _PLANE_CTL_1_B 0x71180
6844 #define _PLANE_CTL_2_B 0x71280
6845 #define _PLANE_CTL_3_B 0x71380
6846 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6847 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6848 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6849 #define PLANE_CTL(pipe, plane) \
6850 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6852 #define _PLANE_STRIDE_1_B 0x71188
6853 #define _PLANE_STRIDE_2_B 0x71288
6854 #define _PLANE_STRIDE_3_B 0x71388
6855 #define _PLANE_STRIDE_1(pipe) \
6856 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6857 #define _PLANE_STRIDE_2(pipe) \
6858 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6859 #define _PLANE_STRIDE_3(pipe) \
6860 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6861 #define PLANE_STRIDE(pipe, plane) \
6862 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6864 #define _PLANE_POS_1_B 0x7118c
6865 #define _PLANE_POS_2_B 0x7128c
6866 #define _PLANE_POS_3_B 0x7138c
6867 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6868 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6869 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6870 #define PLANE_POS(pipe, plane) \
6871 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6873 #define _PLANE_SIZE_1_B 0x71190
6874 #define _PLANE_SIZE_2_B 0x71290
6875 #define _PLANE_SIZE_3_B 0x71390
6876 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6877 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6878 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6879 #define PLANE_SIZE(pipe, plane) \
6880 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6882 #define _PLANE_SURF_1_B 0x7119c
6883 #define _PLANE_SURF_2_B 0x7129c
6884 #define _PLANE_SURF_3_B 0x7139c
6885 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6886 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6887 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6888 #define PLANE_SURF(pipe, plane) \
6889 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6891 #define _PLANE_OFFSET_1_B 0x711a4
6892 #define _PLANE_OFFSET_2_B 0x712a4
6893 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6894 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6895 #define PLANE_OFFSET(pipe, plane) \
6896 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6898 #define _PLANE_KEYVAL_1_B 0x71194
6899 #define _PLANE_KEYVAL_2_B 0x71294
6900 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6901 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6902 #define PLANE_KEYVAL(pipe, plane) \
6903 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6905 #define _PLANE_KEYMSK_1_B 0x71198
6906 #define _PLANE_KEYMSK_2_B 0x71298
6907 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6908 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6909 #define PLANE_KEYMSK(pipe, plane) \
6910 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6912 #define _PLANE_KEYMAX_1_B 0x711a0
6913 #define _PLANE_KEYMAX_2_B 0x712a0
6914 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6915 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6916 #define PLANE_KEYMAX(pipe, plane) \
6917 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6919 #define _PLANE_BUF_CFG_1_B 0x7127c
6920 #define _PLANE_BUF_CFG_2_B 0x7137c
6921 #define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */
6922 #define DDB_ENTRY_END_SHIFT 16
6923 #define _PLANE_BUF_CFG_1(pipe) \
6924 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6925 #define _PLANE_BUF_CFG_2(pipe) \
6926 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6927 #define PLANE_BUF_CFG(pipe, plane) \
6928 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6930 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
6931 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
6932 #define _PLANE_NV12_BUF_CFG_1(pipe) \
6933 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6934 #define _PLANE_NV12_BUF_CFG_2(pipe) \
6935 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6936 #define PLANE_NV12_BUF_CFG(pipe, plane) \
6937 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6939 #define _PLANE_AUX_DIST_1_B 0x711c0
6940 #define _PLANE_AUX_DIST_2_B 0x712c0
6941 #define _PLANE_AUX_DIST_1(pipe) \
6942 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6943 #define _PLANE_AUX_DIST_2(pipe) \
6944 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6945 #define PLANE_AUX_DIST(pipe, plane) \
6946 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6948 #define _PLANE_AUX_OFFSET_1_B 0x711c4
6949 #define _PLANE_AUX_OFFSET_2_B 0x712c4
6950 #define _PLANE_AUX_OFFSET_1(pipe) \
6951 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6952 #define _PLANE_AUX_OFFSET_2(pipe) \
6953 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6954 #define PLANE_AUX_OFFSET(pipe, plane) \
6955 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6957 #define _PLANE_CUS_CTL_1_B 0x711c8
6958 #define _PLANE_CUS_CTL_2_B 0x712c8
6959 #define _PLANE_CUS_CTL_1(pipe) \
6960 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
6961 #define _PLANE_CUS_CTL_2(pipe) \
6962 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
6963 #define PLANE_CUS_CTL(pipe, plane) \
6964 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
6966 #define _PLANE_COLOR_CTL_1_B 0x711CC
6967 #define _PLANE_COLOR_CTL_2_B 0x712CC
6968 #define _PLANE_COLOR_CTL_3_B 0x713CC
6969 #define _PLANE_COLOR_CTL_1(pipe) \
6970 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6971 #define _PLANE_COLOR_CTL_2(pipe) \
6972 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6973 #define PLANE_COLOR_CTL(pipe, plane) \
6974 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6976 #/* SKL new cursor registers */
6977 #define _CUR_BUF_CFG_A 0x7017c
6978 #define _CUR_BUF_CFG_B 0x7117c
6979 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6982 #define VGACNTRL _MMIO(0x71400)
6983 # define VGA_DISP_DISABLE (1 << 31)
6984 # define VGA_2X_MODE (1 << 30)
6985 # define VGA_PIPE_B_SELECT (1 << 29)
6987 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
6991 #define CPU_VGACNTRL _MMIO(0x41000)
6993 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
6994 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
6995 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
6996 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
6997 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
6998 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
6999 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
7000 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
7001 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
7002 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
7003 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
7005 /* refresh rate hardware control */
7006 #define RR_HW_CTL _MMIO(0x45300)
7007 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
7008 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
7010 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
7011 #define FDI_PLL_FB_CLOCK_MASK 0xff
7012 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
7013 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
7014 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
7015 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
7016 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
7018 #define PCH_3DCGDIS0 _MMIO(0x46020)
7019 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
7020 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
7022 #define PCH_3DCGDIS1 _MMIO(0x46024)
7023 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
7025 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
7026 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
7027 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
7028 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
7031 #define _PIPEA_DATA_M1 0x60030
7032 #define PIPE_DATA_M1_OFFSET 0
7033 #define _PIPEA_DATA_N1 0x60034
7034 #define PIPE_DATA_N1_OFFSET 0
7036 #define _PIPEA_DATA_M2 0x60038
7037 #define PIPE_DATA_M2_OFFSET 0
7038 #define _PIPEA_DATA_N2 0x6003c
7039 #define PIPE_DATA_N2_OFFSET 0
7041 #define _PIPEA_LINK_M1 0x60040
7042 #define PIPE_LINK_M1_OFFSET 0
7043 #define _PIPEA_LINK_N1 0x60044
7044 #define PIPE_LINK_N1_OFFSET 0
7046 #define _PIPEA_LINK_M2 0x60048
7047 #define PIPE_LINK_M2_OFFSET 0
7048 #define _PIPEA_LINK_N2 0x6004c
7049 #define PIPE_LINK_N2_OFFSET 0
7051 /* PIPEB timing regs are same start from 0x61000 */
7053 #define _PIPEB_DATA_M1 0x61030
7054 #define _PIPEB_DATA_N1 0x61034
7055 #define _PIPEB_DATA_M2 0x61038
7056 #define _PIPEB_DATA_N2 0x6103c
7057 #define _PIPEB_LINK_M1 0x61040
7058 #define _PIPEB_LINK_N1 0x61044
7059 #define _PIPEB_LINK_M2 0x61048
7060 #define _PIPEB_LINK_N2 0x6104c
7062 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
7063 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
7064 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
7065 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
7066 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
7067 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
7068 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
7069 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
7071 /* CPU panel fitter */
7072 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7073 #define _PFA_CTL_1 0x68080
7074 #define _PFB_CTL_1 0x68880
7075 #define PF_ENABLE (1 << 31)
7076 #define PF_PIPE_SEL_MASK_IVB (3 << 29)
7077 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
7078 #define PF_FILTER_MASK (3 << 23)
7079 #define PF_FILTER_PROGRAMMED (0 << 23)
7080 #define PF_FILTER_MED_3x3 (1 << 23)
7081 #define PF_FILTER_EDGE_ENHANCE (2 << 23)
7082 #define PF_FILTER_EDGE_SOFTEN (3 << 23)
7083 #define _PFA_WIN_SZ 0x68074
7084 #define _PFB_WIN_SZ 0x68874
7085 #define _PFA_WIN_POS 0x68070
7086 #define _PFB_WIN_POS 0x68870
7087 #define _PFA_VSCALE 0x68084
7088 #define _PFB_VSCALE 0x68884
7089 #define _PFA_HSCALE 0x68090
7090 #define _PFB_HSCALE 0x68890
7092 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
7093 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
7094 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
7095 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
7096 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
7098 #define _PSA_CTL 0x68180
7099 #define _PSB_CTL 0x68980
7100 #define PS_ENABLE (1 << 31)
7101 #define _PSA_WIN_SZ 0x68174
7102 #define _PSB_WIN_SZ 0x68974
7103 #define _PSA_WIN_POS 0x68170
7104 #define _PSB_WIN_POS 0x68970
7106 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
7107 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
7108 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
7113 #define _PS_1A_CTRL 0x68180
7114 #define _PS_2A_CTRL 0x68280
7115 #define _PS_1B_CTRL 0x68980
7116 #define _PS_2B_CTRL 0x68A80
7117 #define _PS_1C_CTRL 0x69180
7118 #define PS_SCALER_EN (1 << 31)
7119 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
7120 #define SKL_PS_SCALER_MODE_DYN (0 << 28)
7121 #define SKL_PS_SCALER_MODE_HQ (1 << 28)
7122 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
7123 #define PS_SCALER_MODE_PLANAR (1 << 29)
7124 #define PS_SCALER_MODE_NORMAL (0 << 29)
7125 #define PS_PLANE_SEL_MASK (7 << 25)
7126 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
7127 #define PS_FILTER_MASK (3 << 23)
7128 #define PS_FILTER_MEDIUM (0 << 23)
7129 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
7130 #define PS_FILTER_BILINEAR (3 << 23)
7131 #define PS_VERT3TAP (1 << 21)
7132 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7133 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7134 #define PS_PWRUP_PROGRESS (1 << 17)
7135 #define PS_V_FILTER_BYPASS (1 << 8)
7136 #define PS_VADAPT_EN (1 << 7)
7137 #define PS_VADAPT_MODE_MASK (3 << 5)
7138 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7139 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
7140 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
7141 #define PS_PLANE_Y_SEL_MASK (7 << 5)
7142 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
7144 #define _PS_PWR_GATE_1A 0x68160
7145 #define _PS_PWR_GATE_2A 0x68260
7146 #define _PS_PWR_GATE_1B 0x68960
7147 #define _PS_PWR_GATE_2B 0x68A60
7148 #define _PS_PWR_GATE_1C 0x69160
7149 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
7150 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
7151 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
7152 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
7153 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
7154 #define PS_PWR_GATE_SLPEN_8 0
7155 #define PS_PWR_GATE_SLPEN_16 1
7156 #define PS_PWR_GATE_SLPEN_24 2
7157 #define PS_PWR_GATE_SLPEN_32 3
7159 #define _PS_WIN_POS_1A 0x68170
7160 #define _PS_WIN_POS_2A 0x68270
7161 #define _PS_WIN_POS_1B 0x68970
7162 #define _PS_WIN_POS_2B 0x68A70
7163 #define _PS_WIN_POS_1C 0x69170
7165 #define _PS_WIN_SZ_1A 0x68174
7166 #define _PS_WIN_SZ_2A 0x68274
7167 #define _PS_WIN_SZ_1B 0x68974
7168 #define _PS_WIN_SZ_2B 0x68A74
7169 #define _PS_WIN_SZ_1C 0x69174
7171 #define _PS_VSCALE_1A 0x68184
7172 #define _PS_VSCALE_2A 0x68284
7173 #define _PS_VSCALE_1B 0x68984
7174 #define _PS_VSCALE_2B 0x68A84
7175 #define _PS_VSCALE_1C 0x69184
7177 #define _PS_HSCALE_1A 0x68190
7178 #define _PS_HSCALE_2A 0x68290
7179 #define _PS_HSCALE_1B 0x68990
7180 #define _PS_HSCALE_2B 0x68A90
7181 #define _PS_HSCALE_1C 0x69190
7183 #define _PS_VPHASE_1A 0x68188
7184 #define _PS_VPHASE_2A 0x68288
7185 #define _PS_VPHASE_1B 0x68988
7186 #define _PS_VPHASE_2B 0x68A88
7187 #define _PS_VPHASE_1C 0x69188
7188 #define PS_Y_PHASE(x) ((x) << 16)
7189 #define PS_UV_RGB_PHASE(x) ((x) << 0)
7190 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
7191 #define PS_PHASE_TRIP (1 << 0)
7193 #define _PS_HPHASE_1A 0x68194
7194 #define _PS_HPHASE_2A 0x68294
7195 #define _PS_HPHASE_1B 0x68994
7196 #define _PS_HPHASE_2B 0x68A94
7197 #define _PS_HPHASE_1C 0x69194
7199 #define _PS_ECC_STAT_1A 0x681D0
7200 #define _PS_ECC_STAT_2A 0x682D0
7201 #define _PS_ECC_STAT_1B 0x689D0
7202 #define _PS_ECC_STAT_2B 0x68AD0
7203 #define _PS_ECC_STAT_1C 0x691D0
7205 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
7206 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
7207 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
7208 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7209 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
7210 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7211 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7212 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
7213 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7214 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7215 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
7216 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
7217 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7218 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
7219 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
7220 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7221 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
7222 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
7223 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7224 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
7225 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
7226 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7227 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
7228 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
7229 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7230 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
7231 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
7232 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7234 /* legacy palette */
7235 #define _LGC_PALETTE_A 0x4a000
7236 #define _LGC_PALETTE_B 0x4a800
7237 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7239 /* ilk/snb precision palette */
7240 #define _PREC_PALETTE_A 0x4b000
7241 #define _PREC_PALETTE_B 0x4c000
7242 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
7244 #define _PREC_PIPEAGCMAX 0x4d000
7245 #define _PREC_PIPEBGCMAX 0x4d010
7246 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
7248 #define _GAMMA_MODE_A 0x4a480
7249 #define _GAMMA_MODE_B 0x4ac80
7250 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7251 #define PRE_CSC_GAMMA_ENABLE (1 << 31)
7252 #define POST_CSC_GAMMA_ENABLE (1 << 30)
7253 #define GAMMA_MODE_MODE_MASK (3 << 0)
7254 #define GAMMA_MODE_MODE_8BIT (0 << 0)
7255 #define GAMMA_MODE_MODE_10BIT (1 << 0)
7256 #define GAMMA_MODE_MODE_12BIT (2 << 0)
7257 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
7258 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
7261 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
7262 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
7263 #define CSR_HTP_ADDR_SKL 0x00500034
7264 #define CSR_SSP_BASE _MMIO(0x8F074)
7265 #define CSR_HTP_SKL _MMIO(0x8F004)
7266 #define CSR_LAST_WRITE _MMIO(0x8F034)
7267 #define CSR_LAST_WRITE_VALUE 0xc003b400
7268 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7269 #define CSR_MMIO_START_RANGE 0x80000
7270 #define CSR_MMIO_END_RANGE 0x8FFFF
7271 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
7272 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
7273 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
7274 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
7275 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
7278 #define DE_MASTER_IRQ_CONTROL (1 << 31)
7279 #define DE_SPRITEB_FLIP_DONE (1 << 29)
7280 #define DE_SPRITEA_FLIP_DONE (1 << 28)
7281 #define DE_PLANEB_FLIP_DONE (1 << 27)
7282 #define DE_PLANEA_FLIP_DONE (1 << 26)
7283 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7284 #define DE_PCU_EVENT (1 << 25)
7285 #define DE_GTT_FAULT (1 << 24)
7286 #define DE_POISON (1 << 23)
7287 #define DE_PERFORM_COUNTER (1 << 22)
7288 #define DE_PCH_EVENT (1 << 21)
7289 #define DE_AUX_CHANNEL_A (1 << 20)
7290 #define DE_DP_A_HOTPLUG (1 << 19)
7291 #define DE_GSE (1 << 18)
7292 #define DE_PIPEB_VBLANK (1 << 15)
7293 #define DE_PIPEB_EVEN_FIELD (1 << 14)
7294 #define DE_PIPEB_ODD_FIELD (1 << 13)
7295 #define DE_PIPEB_LINE_COMPARE (1 << 12)
7296 #define DE_PIPEB_VSYNC (1 << 11)
7297 #define DE_PIPEB_CRC_DONE (1 << 10)
7298 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
7299 #define DE_PIPEA_VBLANK (1 << 7)
7300 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
7301 #define DE_PIPEA_EVEN_FIELD (1 << 6)
7302 #define DE_PIPEA_ODD_FIELD (1 << 5)
7303 #define DE_PIPEA_LINE_COMPARE (1 << 4)
7304 #define DE_PIPEA_VSYNC (1 << 3)
7305 #define DE_PIPEA_CRC_DONE (1 << 2)
7306 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
7307 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
7308 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
7310 /* More Ivybridge lolz */
7311 #define DE_ERR_INT_IVB (1 << 30)
7312 #define DE_GSE_IVB (1 << 29)
7313 #define DE_PCH_EVENT_IVB (1 << 28)
7314 #define DE_DP_A_HOTPLUG_IVB (1 << 27)
7315 #define DE_AUX_CHANNEL_A_IVB (1 << 26)
7316 #define DE_EDP_PSR_INT_HSW (1 << 19)
7317 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
7318 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
7319 #define DE_PIPEC_VBLANK_IVB (1 << 10)
7320 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
7321 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
7322 #define DE_PIPEB_VBLANK_IVB (1 << 5)
7323 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
7324 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
7325 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
7326 #define DE_PIPEA_VBLANK_IVB (1 << 0)
7327 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
7329 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
7330 #define MASTER_INTERRUPT_ENABLE (1 << 31)
7332 #define DEISR _MMIO(0x44000)
7333 #define DEIMR _MMIO(0x44004)
7334 #define DEIIR _MMIO(0x44008)
7335 #define DEIER _MMIO(0x4400c)
7337 #define GTISR _MMIO(0x44010)
7338 #define GTIMR _MMIO(0x44014)
7339 #define GTIIR _MMIO(0x44018)
7340 #define GTIER _MMIO(0x4401c)
7342 #define GEN8_MASTER_IRQ _MMIO(0x44200)
7343 #define GEN8_MASTER_IRQ_CONTROL (1 << 31)
7344 #define GEN8_PCU_IRQ (1 << 30)
7345 #define GEN8_DE_PCH_IRQ (1 << 23)
7346 #define GEN8_DE_MISC_IRQ (1 << 22)
7347 #define GEN8_DE_PORT_IRQ (1 << 20)
7348 #define GEN8_DE_PIPE_C_IRQ (1 << 18)
7349 #define GEN8_DE_PIPE_B_IRQ (1 << 17)
7350 #define GEN8_DE_PIPE_A_IRQ (1 << 16)
7351 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
7352 #define GEN8_GT_VECS_IRQ (1 << 6)
7353 #define GEN8_GT_GUC_IRQ (1 << 5)
7354 #define GEN8_GT_PM_IRQ (1 << 4)
7355 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
7356 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
7357 #define GEN8_GT_BCS_IRQ (1 << 1)
7358 #define GEN8_GT_RCS_IRQ (1 << 0)
7360 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7361 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7362 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7363 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7365 #define GEN8_RCS_IRQ_SHIFT 0
7366 #define GEN8_BCS_IRQ_SHIFT 16
7367 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
7368 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
7369 #define GEN8_VECS_IRQ_SHIFT 0
7370 #define GEN8_WD_IRQ_SHIFT 16
7372 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7373 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7374 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7375 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7376 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
7377 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
7378 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
7379 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
7380 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
7381 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
7382 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
7383 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
7384 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
7385 #define GEN8_PIPE_VSYNC (1 << 1)
7386 #define GEN8_PIPE_VBLANK (1 << 0)
7387 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
7388 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
7389 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
7390 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
7391 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
7392 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
7393 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
7394 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
7395 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
7396 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
7397 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7398 (GEN8_PIPE_CURSOR_FAULT | \
7399 GEN8_PIPE_SPRITE_FAULT | \
7400 GEN8_PIPE_PRIMARY_FAULT)
7401 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7402 (GEN9_PIPE_CURSOR_FAULT | \
7403 GEN9_PIPE_PLANE4_FAULT | \
7404 GEN9_PIPE_PLANE3_FAULT | \
7405 GEN9_PIPE_PLANE2_FAULT | \
7406 GEN9_PIPE_PLANE1_FAULT)
7408 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7409 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7410 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7411 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7412 #define ICL_AUX_CHANNEL_E (1 << 29)
7413 #define CNL_AUX_CHANNEL_F (1 << 28)
7414 #define GEN9_AUX_CHANNEL_D (1 << 27)
7415 #define GEN9_AUX_CHANNEL_C (1 << 26)
7416 #define GEN9_AUX_CHANNEL_B (1 << 25)
7417 #define BXT_DE_PORT_HP_DDIC (1 << 5)
7418 #define BXT_DE_PORT_HP_DDIB (1 << 4)
7419 #define BXT_DE_PORT_HP_DDIA (1 << 3)
7420 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
7421 BXT_DE_PORT_HP_DDIB | \
7422 BXT_DE_PORT_HP_DDIC)
7423 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
7424 #define BXT_DE_PORT_GMBUS (1 << 1)
7425 #define GEN8_AUX_CHANNEL_A (1 << 0)
7426 #define TGL_DE_PORT_AUX_DDIC (1 << 2)
7427 #define TGL_DE_PORT_AUX_DDIB (1 << 1)
7428 #define TGL_DE_PORT_AUX_DDIA (1 << 0)
7430 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7431 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7432 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7433 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7434 #define GEN8_DE_MISC_GSE (1 << 27)
7435 #define GEN8_DE_EDP_PSR (1 << 19)
7437 #define GEN8_PCU_ISR _MMIO(0x444e0)
7438 #define GEN8_PCU_IMR _MMIO(0x444e4)
7439 #define GEN8_PCU_IIR _MMIO(0x444e8)
7440 #define GEN8_PCU_IER _MMIO(0x444ec)
7442 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
7443 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
7444 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
7445 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
7446 #define GEN11_GU_MISC_GSE (1 << 27)
7448 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
7449 #define GEN11_MASTER_IRQ (1 << 31)
7450 #define GEN11_PCU_IRQ (1 << 30)
7451 #define GEN11_GU_MISC_IRQ (1 << 29)
7452 #define GEN11_DISPLAY_IRQ (1 << 16)
7453 #define GEN11_GT_DW_IRQ(x) (1 << (x))
7454 #define GEN11_GT_DW1_IRQ (1 << 1)
7455 #define GEN11_GT_DW0_IRQ (1 << 0)
7457 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7458 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7459 #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
7460 #define GEN11_DE_PCH_IRQ (1 << 23)
7461 #define GEN11_DE_MISC_IRQ (1 << 22)
7462 #define GEN11_DE_HPD_IRQ (1 << 21)
7463 #define GEN11_DE_PORT_IRQ (1 << 20)
7464 #define GEN11_DE_PIPE_C (1 << 18)
7465 #define GEN11_DE_PIPE_B (1 << 17)
7466 #define GEN11_DE_PIPE_A (1 << 16)
7468 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
7469 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
7470 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
7471 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
7472 #define GEN12_TC6_HOTPLUG (1 << 21)
7473 #define GEN12_TC5_HOTPLUG (1 << 20)
7474 #define GEN11_TC4_HOTPLUG (1 << 19)
7475 #define GEN11_TC3_HOTPLUG (1 << 18)
7476 #define GEN11_TC2_HOTPLUG (1 << 17)
7477 #define GEN11_TC1_HOTPLUG (1 << 16)
7478 #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
7479 #define GEN11_DE_TC_HOTPLUG_MASK (GEN12_TC6_HOTPLUG | \
7480 GEN12_TC5_HOTPLUG | \
7481 GEN11_TC4_HOTPLUG | \
7482 GEN11_TC3_HOTPLUG | \
7483 GEN11_TC2_HOTPLUG | \
7485 #define GEN12_TBT6_HOTPLUG (1 << 5)
7486 #define GEN12_TBT5_HOTPLUG (1 << 4)
7487 #define GEN11_TBT4_HOTPLUG (1 << 3)
7488 #define GEN11_TBT3_HOTPLUG (1 << 2)
7489 #define GEN11_TBT2_HOTPLUG (1 << 1)
7490 #define GEN11_TBT1_HOTPLUG (1 << 0)
7491 #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
7492 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN12_TBT6_HOTPLUG | \
7493 GEN12_TBT5_HOTPLUG | \
7494 GEN11_TBT4_HOTPLUG | \
7495 GEN11_TBT3_HOTPLUG | \
7496 GEN11_TBT2_HOTPLUG | \
7499 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
7500 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
7501 #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
7502 #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
7503 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
7504 #define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4)
7506 #define GEN11_GT_INTR_DW0 _MMIO(0x190018)
7507 #define GEN11_CSME (31)
7508 #define GEN11_GUNIT (28)
7509 #define GEN11_GUC (25)
7510 #define GEN11_WDPERF (20)
7511 #define GEN11_KCR (19)
7512 #define GEN11_GTPM (16)
7513 #define GEN11_BCS (15)
7514 #define GEN11_RCS0 (0)
7516 #define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7517 #define GEN11_VECS(x) (31 - (x))
7518 #define GEN11_VCS(x) (x)
7520 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
7522 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7523 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7524 #define GEN11_INTR_DATA_VALID (1 << 31)
7525 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
7526 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
7527 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
7529 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
7531 #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7532 #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7534 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
7536 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7537 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7538 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7539 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7540 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7541 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7543 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7544 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7545 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7546 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7547 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7548 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7549 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7550 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7551 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7553 #define ENGINE1_MASK REG_GENMASK(31, 16)
7554 #define ENGINE0_MASK REG_GENMASK(15, 0)
7556 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7557 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7558 #define ILK_ELPIN_409_SELECT (1 << 25)
7559 #define ILK_DPARB_GATE (1 << 22)
7560 #define ILK_VSDPFD_FULL (1 << 21)
7561 #define FUSE_STRAP _MMIO(0x42014)
7562 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7563 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7564 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
7565 #define IVB_PIPE_C_DISABLE (1 << 28)
7566 #define ILK_HDCP_DISABLE (1 << 25)
7567 #define ILK_eDP_A_DISABLE (1 << 24)
7568 #define HSW_CDCLK_LIMIT (1 << 24)
7569 #define ILK_DESKTOP (1 << 23)
7570 #define HSW_CPU_SSC_ENABLE (1 << 21)
7572 #define FUSE_STRAP3 _MMIO(0x42020)
7573 #define HSW_REF_CLK_SELECT (1 << 1)
7575 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7576 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7577 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7578 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7579 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7580 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7582 #define IVB_CHICKEN3 _MMIO(0x4200c)
7583 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7584 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7586 #define CHICKEN_PAR1_1 _MMIO(0x42080)
7587 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
7588 #define DPA_MASK_VBLANK_SRD (1 << 15)
7589 #define FORCE_ARB_IDLE_PLANES (1 << 14)
7590 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7592 #define CHICKEN_PAR2_1 _MMIO(0x42090)
7593 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
7595 #define CHICKEN_MISC_2 _MMIO(0x42084)
7596 #define CNL_COMP_PWR_DOWN (1 << 23)
7597 #define GLK_CL2_PWR_DOWN (1 << 12)
7598 #define GLK_CL1_PWR_DOWN (1 << 11)
7599 #define GLK_CL0_PWR_DOWN (1 << 10)
7601 #define CHICKEN_MISC_4 _MMIO(0x4208c)
7602 #define FBC_STRIDE_OVERRIDE (1 << 13)
7603 #define FBC_STRIDE_MASK 0x1FFF
7605 #define _CHICKEN_PIPESL_1_A 0x420b0
7606 #define _CHICKEN_PIPESL_1_B 0x420b4
7607 #define HSW_FBCQ_DIS (1 << 22)
7608 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7609 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7611 #define CHICKEN_TRANS_A _MMIO(0x420c0)
7612 #define CHICKEN_TRANS_B _MMIO(0x420c4)
7613 #define CHICKEN_TRANS_C _MMIO(0x420c8)
7614 #define CHICKEN_TRANS_EDP _MMIO(0x420cc)
7615 #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
7616 #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
7617 #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
7618 #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */
7619 #define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */
7620 #define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15)
7621 #define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12)
7623 #define DISP_ARB_CTL _MMIO(0x45000)
7624 #define DISP_FBC_MEMORY_WAKE (1 << 31)
7625 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
7626 #define DISP_FBC_WM_DIS (1 << 15)
7627 #define DISP_ARB_CTL2 _MMIO(0x45004)
7628 #define DISP_DATA_PARTITION_5_6 (1 << 6)
7629 #define DISP_IPC_ENABLE (1 << 3)
7630 #define DBUF_CTL _MMIO(0x45008)
7631 #define DBUF_CTL_S1 _MMIO(0x45008)
7632 #define DBUF_CTL_S2 _MMIO(0x44FE8)
7633 #define DBUF_POWER_REQUEST (1 << 31)
7634 #define DBUF_POWER_STATE (1 << 30)
7635 #define GEN7_MSG_CTL _MMIO(0x45010)
7636 #define WAIT_FOR_PCH_RESET_ACK (1 << 1)
7637 #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
7638 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
7639 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
7641 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
7642 #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
7643 #define MASK_WAKEMEM (1 << 13)
7644 #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
7646 #define SKL_DFSM _MMIO(0x51000)
7647 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7648 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7649 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7650 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7651 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
7652 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7653 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7654 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
7655 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
7657 #define SKL_DSSM _MMIO(0x51004)
7658 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
7659 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
7660 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
7661 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
7662 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
7664 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
7665 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
7667 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
7668 #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
7669 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
7671 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
7672 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
7673 #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
7674 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
7675 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
7676 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7677 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7678 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7679 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7682 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
7683 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
7684 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
7686 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
7687 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
7688 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
7689 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
7690 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
7692 #define GEN8_L3CNTLREG _MMIO(0x7034)
7693 #define GEN8_ERRDETBCTRL (1 << 9)
7695 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
7696 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
7698 #define HIZ_CHICKEN _MMIO(0x7018)
7699 # define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
7700 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
7702 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
7703 #define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
7705 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7706 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
7708 #define GEN7_SARCHKMD _MMIO(0xB000)
7709 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
7710 #define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
7712 #define GEN7_L3SQCREG1 _MMIO(0xB010)
7713 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7715 #define GEN8_L3SQCREG1 _MMIO(0xB100)
7717 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7718 * Using the formula in BSpec leads to a hang, while the formula here works
7719 * fine and matches the formulas for all other platforms. A BSpec change
7720 * request has been filed to clarify this.
7722 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
7723 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
7724 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
7726 #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
7727 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
7728 #define GEN7_L3AGDIS (1 << 19)
7729 #define GEN7_L3CNTLREG2 _MMIO(0xB020)
7730 #define GEN7_L3CNTLREG3 _MMIO(0xB024)
7732 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
7733 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
7734 #define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
7735 #define GEN11_I2M_WRITE_DISABLE (1 << 28)
7737 #define GEN7_L3SQCREG4 _MMIO(0xb034)
7738 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
7740 #define GEN11_SCRATCH2 _MMIO(0xb140)
7741 #define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
7743 #define GEN8_L3SQCREG4 _MMIO(0xb118)
7744 #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
7745 #define GEN8_LQSC_RO_PERF_DIS (1 << 27)
7746 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
7749 #define HDC_CHICKEN0 _MMIO(0x7300)
7750 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
7751 #define ICL_HDC_MODE _MMIO(0xE5F4)
7752 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
7753 #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
7754 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
7755 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
7756 #define HDC_FORCE_NON_COHERENT (1 << 4)
7757 #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
7759 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
7762 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
7763 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
7765 #define GEN9_WM_CHICKEN3 _MMIO(0x5588)
7766 #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
7768 /* WaCatErrorRejectionIssue */
7769 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
7770 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
7772 #define HSW_SCRATCH1 _MMIO(0xb038)
7773 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
7775 #define BDW_SCRATCH1 _MMIO(0xb11c)
7776 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
7779 #define _PIPEA_CHICKEN 0x70038
7780 #define _PIPEB_CHICKEN 0x71038
7781 #define _PIPEC_CHICKEN 0x72038
7782 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7784 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
7785 #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
7789 #define PCH_DISPLAY_BASE 0xc0000u
7791 /* south display engine interrupt: IBX */
7792 #define SDE_AUDIO_POWER_D (1 << 27)
7793 #define SDE_AUDIO_POWER_C (1 << 26)
7794 #define SDE_AUDIO_POWER_B (1 << 25)
7795 #define SDE_AUDIO_POWER_SHIFT (25)
7796 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
7797 #define SDE_GMBUS (1 << 24)
7798 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
7799 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
7800 #define SDE_AUDIO_HDCP_MASK (3 << 22)
7801 #define SDE_AUDIO_TRANSB (1 << 21)
7802 #define SDE_AUDIO_TRANSA (1 << 20)
7803 #define SDE_AUDIO_TRANS_MASK (3 << 20)
7804 #define SDE_POISON (1 << 19)
7806 #define SDE_FDI_RXB (1 << 17)
7807 #define SDE_FDI_RXA (1 << 16)
7808 #define SDE_FDI_MASK (3 << 16)
7809 #define SDE_AUXD (1 << 15)
7810 #define SDE_AUXC (1 << 14)
7811 #define SDE_AUXB (1 << 13)
7812 #define SDE_AUX_MASK (7 << 13)
7814 #define SDE_CRT_HOTPLUG (1 << 11)
7815 #define SDE_PORTD_HOTPLUG (1 << 10)
7816 #define SDE_PORTC_HOTPLUG (1 << 9)
7817 #define SDE_PORTB_HOTPLUG (1 << 8)
7818 #define SDE_SDVOB_HOTPLUG (1 << 6)
7819 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
7820 SDE_SDVOB_HOTPLUG | \
7821 SDE_PORTB_HOTPLUG | \
7822 SDE_PORTC_HOTPLUG | \
7824 #define SDE_TRANSB_CRC_DONE (1 << 5)
7825 #define SDE_TRANSB_CRC_ERR (1 << 4)
7826 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
7827 #define SDE_TRANSA_CRC_DONE (1 << 2)
7828 #define SDE_TRANSA_CRC_ERR (1 << 1)
7829 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
7830 #define SDE_TRANS_MASK (0x3f)
7832 /* south display engine interrupt: CPT - CNP */
7833 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
7834 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
7835 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
7836 #define SDE_AUDIO_POWER_SHIFT_CPT 29
7837 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
7838 #define SDE_AUXD_CPT (1 << 27)
7839 #define SDE_AUXC_CPT (1 << 26)
7840 #define SDE_AUXB_CPT (1 << 25)
7841 #define SDE_AUX_MASK_CPT (7 << 25)
7842 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
7843 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
7844 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
7845 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
7846 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
7847 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
7848 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
7849 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
7850 SDE_SDVOB_HOTPLUG_CPT | \
7851 SDE_PORTD_HOTPLUG_CPT | \
7852 SDE_PORTC_HOTPLUG_CPT | \
7853 SDE_PORTB_HOTPLUG_CPT)
7854 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
7855 SDE_PORTD_HOTPLUG_CPT | \
7856 SDE_PORTC_HOTPLUG_CPT | \
7857 SDE_PORTB_HOTPLUG_CPT | \
7858 SDE_PORTA_HOTPLUG_SPT)
7859 #define SDE_GMBUS_CPT (1 << 17)
7860 #define SDE_ERROR_CPT (1 << 16)
7861 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
7862 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
7863 #define SDE_FDI_RXC_CPT (1 << 8)
7864 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
7865 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
7866 #define SDE_FDI_RXB_CPT (1 << 4)
7867 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
7868 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
7869 #define SDE_FDI_RXA_CPT (1 << 0)
7870 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
7871 SDE_AUDIO_CP_REQ_B_CPT | \
7872 SDE_AUDIO_CP_REQ_A_CPT)
7873 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
7874 SDE_AUDIO_CP_CHG_B_CPT | \
7875 SDE_AUDIO_CP_CHG_A_CPT)
7876 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
7880 /* south display engine interrupt: ICP/TGP */
7881 #define SDE_TC6_HOTPLUG_TGP (1 << 29)
7882 #define SDE_TC5_HOTPLUG_TGP (1 << 28)
7883 #define SDE_TC4_HOTPLUG_ICP (1 << 27)
7884 #define SDE_TC3_HOTPLUG_ICP (1 << 26)
7885 #define SDE_TC2_HOTPLUG_ICP (1 << 25)
7886 #define SDE_TC1_HOTPLUG_ICP (1 << 24)
7887 #define SDE_GMBUS_ICP (1 << 23)
7888 #define SDE_DDIC_HOTPLUG_TGP (1 << 18)
7889 #define SDE_DDIB_HOTPLUG_ICP (1 << 17)
7890 #define SDE_DDIA_HOTPLUG_ICP (1 << 16)
7891 #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
7892 #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
7893 #define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \
7894 SDE_DDIA_HOTPLUG_ICP)
7895 #define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \
7896 SDE_TC3_HOTPLUG_ICP | \
7897 SDE_TC2_HOTPLUG_ICP | \
7898 SDE_TC1_HOTPLUG_ICP)
7899 #define SDE_DDI_MASK_TGP (SDE_DDIC_HOTPLUG_TGP | \
7901 #define SDE_TC_MASK_TGP (SDE_TC6_HOTPLUG_TGP | \
7902 SDE_TC5_HOTPLUG_TGP | \
7905 #define SDEISR _MMIO(0xc4000)
7906 #define SDEIMR _MMIO(0xc4004)
7907 #define SDEIIR _MMIO(0xc4008)
7908 #define SDEIER _MMIO(0xc400c)
7910 #define SERR_INT _MMIO(0xc4040)
7911 #define SERR_INT_POISON (1 << 31)
7912 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
7914 /* digital port hotplug */
7915 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
7916 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
7917 #define BXT_DDIA_HPD_INVERT (1 << 27)
7918 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
7919 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
7920 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
7921 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
7922 #define PORTD_HOTPLUG_ENABLE (1 << 20)
7923 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
7924 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
7925 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
7926 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
7927 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
7928 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
7929 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
7930 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
7931 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
7932 #define PORTC_HOTPLUG_ENABLE (1 << 12)
7933 #define BXT_DDIC_HPD_INVERT (1 << 11)
7934 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
7935 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
7936 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
7937 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
7938 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
7939 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
7940 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
7941 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
7942 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
7943 #define PORTB_HOTPLUG_ENABLE (1 << 4)
7944 #define BXT_DDIB_HPD_INVERT (1 << 3)
7945 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
7946 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
7947 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
7948 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
7949 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
7950 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
7951 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
7952 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
7953 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
7954 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
7955 BXT_DDIB_HPD_INVERT | \
7956 BXT_DDIC_HPD_INVERT)
7958 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
7959 #define PORTE_HOTPLUG_ENABLE (1 << 4)
7960 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
7961 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
7962 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
7963 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
7965 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
7966 * functionality covered in PCH_PORT_HOTPLUG is split into
7967 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
7970 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
7971 #define TGP_DDIC_HPD_ENABLE (1 << 11)
7972 #define TGP_DDIC_HPD_STATUS_MASK (3 << 8)
7973 #define TGP_DDIC_HPD_NO_DETECT (0 << 8)
7974 #define TGP_DDIC_HPD_SHORT_DETECT (1 << 8)
7975 #define TGP_DDIC_HPD_LONG_DETECT (2 << 8)
7976 #define TGP_DDIC_HPD_SHORT_LONG_DETECT (3 << 8)
7977 #define ICP_DDIB_HPD_ENABLE (1 << 7)
7978 #define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
7979 #define ICP_DDIB_HPD_NO_DETECT (0 << 4)
7980 #define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
7981 #define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
7982 #define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
7983 #define ICP_DDIA_HPD_ENABLE (1 << 3)
7984 #define ICP_DDIA_HPD_OP_DRIVE_1 (1 << 2)
7985 #define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
7986 #define ICP_DDIA_HPD_NO_DETECT (0 << 0)
7987 #define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
7988 #define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
7989 #define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
7991 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
7992 #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
7993 /* Icelake DSC Rate Control Range Parameter Registers */
7994 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
7995 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
7996 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
7997 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
7998 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
7999 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
8000 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
8001 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
8002 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
8003 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
8004 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
8005 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
8006 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8007 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
8008 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
8009 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8010 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
8011 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
8012 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8013 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
8014 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
8015 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8016 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
8017 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
8018 #define RC_BPG_OFFSET_SHIFT 10
8019 #define RC_MAX_QP_SHIFT 5
8020 #define RC_MIN_QP_SHIFT 0
8022 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
8023 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
8024 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
8025 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
8026 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
8027 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
8028 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
8029 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
8030 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
8031 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
8032 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
8033 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
8034 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8035 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
8036 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
8037 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8038 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
8039 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
8040 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8041 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
8042 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
8043 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8044 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
8045 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
8047 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
8048 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
8049 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
8050 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
8051 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
8052 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
8053 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
8054 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
8055 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
8056 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
8057 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
8058 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
8059 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8060 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
8061 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
8062 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8063 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
8064 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
8065 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8066 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
8067 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
8068 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8069 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
8070 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
8072 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
8073 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
8074 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
8075 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
8076 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
8077 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
8078 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
8079 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
8080 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
8081 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
8082 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
8083 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
8084 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8085 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
8086 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
8087 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8088 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
8089 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
8090 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8091 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
8092 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
8093 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8094 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
8095 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
8097 #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
8098 #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
8100 #define ICP_DDI_HPD_ENABLE_MASK (ICP_DDIB_HPD_ENABLE | \
8101 ICP_DDIA_HPD_ENABLE)
8102 #define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
8103 ICP_TC_HPD_ENABLE(PORT_TC3) | \
8104 ICP_TC_HPD_ENABLE(PORT_TC2) | \
8105 ICP_TC_HPD_ENABLE(PORT_TC1))
8106 #define TGP_DDI_HPD_ENABLE_MASK (TGP_DDIC_HPD_ENABLE | \
8107 ICP_DDI_HPD_ENABLE_MASK)
8108 #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
8109 ICP_TC_HPD_ENABLE(PORT_TC5) | \
8110 ICP_TC_HPD_ENABLE_MASK)
8112 #define _PCH_DPLL_A 0xc6014
8113 #define _PCH_DPLL_B 0xc6018
8114 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8116 #define _PCH_FPA0 0xc6040
8117 #define FP_CB_TUNE (0x3 << 22)
8118 #define _PCH_FPA1 0xc6044
8119 #define _PCH_FPB0 0xc6048
8120 #define _PCH_FPB1 0xc604c
8121 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8122 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8124 #define PCH_DPLL_TEST _MMIO(0xc606c)
8126 #define PCH_DREF_CONTROL _MMIO(0xC6200)
8127 #define DREF_CONTROL_MASK 0x7fc3
8128 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
8129 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
8130 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
8131 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
8132 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
8133 #define DREF_SSC_SOURCE_ENABLE (2 << 11)
8134 #define DREF_SSC_SOURCE_MASK (3 << 11)
8135 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
8136 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
8137 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
8138 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
8139 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
8140 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
8141 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
8142 #define DREF_SSC4_DOWNSPREAD (0 << 6)
8143 #define DREF_SSC4_CENTERSPREAD (1 << 6)
8144 #define DREF_SSC1_DISABLE (0 << 1)
8145 #define DREF_SSC1_ENABLE (1 << 1)
8146 #define DREF_SSC4_DISABLE (0)
8147 #define DREF_SSC4_ENABLE (1)
8149 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
8150 #define FDL_TP1_TIMER_SHIFT 12
8151 #define FDL_TP1_TIMER_MASK (3 << 12)
8152 #define FDL_TP2_TIMER_SHIFT 10
8153 #define FDL_TP2_TIMER_MASK (3 << 10)
8154 #define RAWCLK_FREQ_MASK 0x3ff
8155 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
8156 #define CNP_RAWCLK_DIV(div) ((div) << 16)
8157 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
8158 #define CNP_RAWCLK_DEN(den) ((den) << 26)
8159 #define ICP_RAWCLK_NUM(num) ((num) << 11)
8161 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
8163 #define PCH_SSC4_PARMS _MMIO(0xc6210)
8164 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
8166 #define PCH_DPLL_SEL _MMIO(0xc7000)
8167 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
8168 #define TRANS_DPLLA_SEL(pipe) 0
8169 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
8173 #define _PCH_TRANS_HTOTAL_A 0xe0000
8174 #define TRANS_HTOTAL_SHIFT 16
8175 #define TRANS_HACTIVE_SHIFT 0
8176 #define _PCH_TRANS_HBLANK_A 0xe0004
8177 #define TRANS_HBLANK_END_SHIFT 16
8178 #define TRANS_HBLANK_START_SHIFT 0
8179 #define _PCH_TRANS_HSYNC_A 0xe0008
8180 #define TRANS_HSYNC_END_SHIFT 16
8181 #define TRANS_HSYNC_START_SHIFT 0
8182 #define _PCH_TRANS_VTOTAL_A 0xe000c
8183 #define TRANS_VTOTAL_SHIFT 16
8184 #define TRANS_VACTIVE_SHIFT 0
8185 #define _PCH_TRANS_VBLANK_A 0xe0010
8186 #define TRANS_VBLANK_END_SHIFT 16
8187 #define TRANS_VBLANK_START_SHIFT 0
8188 #define _PCH_TRANS_VSYNC_A 0xe0014
8189 #define TRANS_VSYNC_END_SHIFT 16
8190 #define TRANS_VSYNC_START_SHIFT 0
8191 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
8193 #define _PCH_TRANSA_DATA_M1 0xe0030
8194 #define _PCH_TRANSA_DATA_N1 0xe0034
8195 #define _PCH_TRANSA_DATA_M2 0xe0038
8196 #define _PCH_TRANSA_DATA_N2 0xe003c
8197 #define _PCH_TRANSA_LINK_M1 0xe0040
8198 #define _PCH_TRANSA_LINK_N1 0xe0044
8199 #define _PCH_TRANSA_LINK_M2 0xe0048
8200 #define _PCH_TRANSA_LINK_N2 0xe004c
8202 /* Per-transcoder DIP controls (PCH) */
8203 #define _VIDEO_DIP_CTL_A 0xe0200
8204 #define _VIDEO_DIP_DATA_A 0xe0208
8205 #define _VIDEO_DIP_GCP_A 0xe0210
8206 #define GCP_COLOR_INDICATION (1 << 2)
8207 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
8208 #define GCP_AV_MUTE (1 << 0)
8210 #define _VIDEO_DIP_CTL_B 0xe1200
8211 #define _VIDEO_DIP_DATA_B 0xe1208
8212 #define _VIDEO_DIP_GCP_B 0xe1210
8214 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8215 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8216 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
8218 /* Per-transcoder DIP controls (VLV) */
8219 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
8220 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
8221 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
8223 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
8224 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
8225 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
8227 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
8228 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
8229 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
8231 #define VLV_TVIDEO_DIP_CTL(pipe) \
8232 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8233 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8234 #define VLV_TVIDEO_DIP_DATA(pipe) \
8235 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8236 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8237 #define VLV_TVIDEO_DIP_GCP(pipe) \
8238 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8239 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8241 /* Haswell DIP controls */
8243 #define _HSW_VIDEO_DIP_CTL_A 0x60200
8244 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
8245 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
8246 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
8247 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
8248 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
8249 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
8250 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
8251 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
8252 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
8253 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
8254 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
8255 #define _HSW_VIDEO_DIP_GCP_A 0x60210
8257 #define _HSW_VIDEO_DIP_CTL_B 0x61200
8258 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
8259 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
8260 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
8261 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
8262 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
8263 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
8264 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
8265 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
8266 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
8267 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
8268 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
8269 #define _HSW_VIDEO_DIP_GCP_B 0x61210
8271 /* Icelake PPS_DATA and _ECC DIP Registers.
8272 * These are available for transcoders B,C and eDP.
8273 * Adding the _A so as to reuse the _MMIO_TRANS2
8274 * definition, with which it offsets to the right location.
8277 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
8278 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
8279 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
8280 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
8282 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8283 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8284 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8285 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8286 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8287 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
8288 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8289 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
8290 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8291 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8293 #define _HSW_STEREO_3D_CTL_A 0x70020
8294 #define S3D_ENABLE (1 << 31)
8295 #define _HSW_STEREO_3D_CTL_B 0x71020
8297 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8299 #define _PCH_TRANS_HTOTAL_B 0xe1000
8300 #define _PCH_TRANS_HBLANK_B 0xe1004
8301 #define _PCH_TRANS_HSYNC_B 0xe1008
8302 #define _PCH_TRANS_VTOTAL_B 0xe100c
8303 #define _PCH_TRANS_VBLANK_B 0xe1010
8304 #define _PCH_TRANS_VSYNC_B 0xe1014
8305 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8307 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8308 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8309 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8310 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8311 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8312 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8313 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8315 #define _PCH_TRANSB_DATA_M1 0xe1030
8316 #define _PCH_TRANSB_DATA_N1 0xe1034
8317 #define _PCH_TRANSB_DATA_M2 0xe1038
8318 #define _PCH_TRANSB_DATA_N2 0xe103c
8319 #define _PCH_TRANSB_LINK_M1 0xe1040
8320 #define _PCH_TRANSB_LINK_N1 0xe1044
8321 #define _PCH_TRANSB_LINK_M2 0xe1048
8322 #define _PCH_TRANSB_LINK_N2 0xe104c
8324 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
8325 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
8326 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8327 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8328 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8329 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8330 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8331 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8333 #define _PCH_TRANSACONF 0xf0008
8334 #define _PCH_TRANSBCONF 0xf1008
8335 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8336 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8337 #define TRANS_DISABLE (0 << 31)
8338 #define TRANS_ENABLE (1 << 31)
8339 #define TRANS_STATE_MASK (1 << 30)
8340 #define TRANS_STATE_DISABLE (0 << 30)
8341 #define TRANS_STATE_ENABLE (1 << 30)
8342 #define TRANS_FSYNC_DELAY_HB1 (0 << 27)
8343 #define TRANS_FSYNC_DELAY_HB2 (1 << 27)
8344 #define TRANS_FSYNC_DELAY_HB3 (2 << 27)
8345 #define TRANS_FSYNC_DELAY_HB4 (3 << 27)
8346 #define TRANS_INTERLACE_MASK (7 << 21)
8347 #define TRANS_PROGRESSIVE (0 << 21)
8348 #define TRANS_INTERLACED (3 << 21)
8349 #define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8350 #define TRANS_8BPC (0 << 5)
8351 #define TRANS_10BPC (1 << 5)
8352 #define TRANS_6BPC (2 << 5)
8353 #define TRANS_12BPC (3 << 5)
8355 #define _TRANSA_CHICKEN1 0xf0060
8356 #define _TRANSB_CHICKEN1 0xf1060
8357 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8358 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
8359 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
8360 #define _TRANSA_CHICKEN2 0xf0064
8361 #define _TRANSB_CHICKEN2 0xf1064
8362 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8363 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
8364 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
8365 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
8366 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
8367 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
8369 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
8370 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
8371 #define FDIA_PHASE_SYNC_SHIFT_EN 18
8372 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8373 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8374 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
8375 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
8376 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
8377 #define SPT_PWM_GRANULARITY (1 << 0)
8378 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
8379 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
8380 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
8381 #define LPT_PWM_GRANULARITY (1 << 5)
8382 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
8384 #define _FDI_RXA_CHICKEN 0xc200c
8385 #define _FDI_RXB_CHICKEN 0xc2010
8386 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
8387 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
8388 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8390 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
8391 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8392 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8393 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8394 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8395 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8396 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
8399 #define _FDI_TXA_CTL 0x60100
8400 #define _FDI_TXB_CTL 0x61100
8401 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8402 #define FDI_TX_DISABLE (0 << 31)
8403 #define FDI_TX_ENABLE (1 << 31)
8404 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
8405 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
8406 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
8407 #define FDI_LINK_TRAIN_NONE (3 << 28)
8408 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
8409 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
8410 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
8411 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
8412 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8413 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8414 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
8415 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
8416 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8417 SNB has different settings. */
8418 /* SNB A-stepping */
8419 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8420 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8421 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8422 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8423 /* SNB B-stepping */
8424 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
8425 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
8426 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
8427 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
8428 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
8429 #define FDI_DP_PORT_WIDTH_SHIFT 19
8430 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
8431 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8432 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
8433 /* Ironlake: hardwired to 1 */
8434 #define FDI_TX_PLL_ENABLE (1 << 14)
8436 /* Ivybridge has different bits for lolz */
8437 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
8438 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
8439 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
8440 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
8442 /* both Tx and Rx */
8443 #define FDI_COMPOSITE_SYNC (1 << 11)
8444 #define FDI_LINK_TRAIN_AUTO (1 << 10)
8445 #define FDI_SCRAMBLING_ENABLE (0 << 7)
8446 #define FDI_SCRAMBLING_DISABLE (1 << 7)
8448 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8449 #define _FDI_RXA_CTL 0xf000c
8450 #define _FDI_RXB_CTL 0xf100c
8451 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8452 #define FDI_RX_ENABLE (1 << 31)
8453 /* train, dp width same as FDI_TX */
8454 #define FDI_FS_ERRC_ENABLE (1 << 27)
8455 #define FDI_FE_ERRC_ENABLE (1 << 26)
8456 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
8457 #define FDI_8BPC (0 << 16)
8458 #define FDI_10BPC (1 << 16)
8459 #define FDI_6BPC (2 << 16)
8460 #define FDI_12BPC (3 << 16)
8461 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
8462 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
8463 #define FDI_RX_PLL_ENABLE (1 << 13)
8464 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
8465 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
8466 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
8467 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
8468 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
8469 #define FDI_PCDCLK (1 << 4)
8471 #define FDI_AUTO_TRAINING (1 << 10)
8472 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
8473 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
8474 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
8475 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
8476 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
8478 #define _FDI_RXA_MISC 0xf0010
8479 #define _FDI_RXB_MISC 0xf1010
8480 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
8481 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
8482 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
8483 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
8484 #define FDI_RX_TP1_TO_TP2_48 (2 << 20)
8485 #define FDI_RX_TP1_TO_TP2_64 (3 << 20)
8486 #define FDI_RX_FDI_DELAY_90 (0x90 << 0)
8487 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8489 #define _FDI_RXA_TUSIZE1 0xf0030
8490 #define _FDI_RXA_TUSIZE2 0xf0038
8491 #define _FDI_RXB_TUSIZE1 0xf1030
8492 #define _FDI_RXB_TUSIZE2 0xf1038
8493 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8494 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8496 /* FDI_RX interrupt register format */
8497 #define FDI_RX_INTER_LANE_ALIGN (1 << 10)
8498 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */
8499 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */
8500 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
8501 #define FDI_RX_FS_CODE_ERR (1 << 6)
8502 #define FDI_RX_FE_CODE_ERR (1 << 5)
8503 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
8504 #define FDI_RX_HDCP_LINK_FAIL (1 << 3)
8505 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
8506 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
8507 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
8509 #define _FDI_RXA_IIR 0xf0014
8510 #define _FDI_RXA_IMR 0xf0018
8511 #define _FDI_RXB_IIR 0xf1014
8512 #define _FDI_RXB_IMR 0xf1018
8513 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8514 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8516 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
8517 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
8519 #define PCH_LVDS _MMIO(0xe1180)
8520 #define LVDS_DETECTED (1 << 1)
8522 #define _PCH_DP_B 0xe4100
8523 #define PCH_DP_B _MMIO(_PCH_DP_B)
8524 #define _PCH_DPB_AUX_CH_CTL 0xe4110
8525 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
8526 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
8527 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
8528 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
8529 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
8531 #define _PCH_DP_C 0xe4200
8532 #define PCH_DP_C _MMIO(_PCH_DP_C)
8533 #define _PCH_DPC_AUX_CH_CTL 0xe4210
8534 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
8535 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
8536 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
8537 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
8538 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
8540 #define _PCH_DP_D 0xe4300
8541 #define PCH_DP_D _MMIO(_PCH_DP_D)
8542 #define _PCH_DPD_AUX_CH_CTL 0xe4310
8543 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
8544 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
8545 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
8546 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
8547 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
8549 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8550 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
8553 #define _TRANS_DP_CTL_A 0xe0300
8554 #define _TRANS_DP_CTL_B 0xe1300
8555 #define _TRANS_DP_CTL_C 0xe2300
8556 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8557 #define TRANS_DP_OUTPUT_ENABLE (1 << 31)
8558 #define TRANS_DP_PORT_SEL_MASK (3 << 29)
8559 #define TRANS_DP_PORT_SEL_NONE (3 << 29)
8560 #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
8561 #define TRANS_DP_AUDIO_ONLY (1 << 26)
8562 #define TRANS_DP_ENH_FRAMING (1 << 18)
8563 #define TRANS_DP_8BPC (0 << 9)
8564 #define TRANS_DP_10BPC (1 << 9)
8565 #define TRANS_DP_6BPC (2 << 9)
8566 #define TRANS_DP_12BPC (3 << 9)
8567 #define TRANS_DP_BPC_MASK (3 << 9)
8568 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
8569 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
8570 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
8571 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
8572 #define TRANS_DP_SYNC_MASK (3 << 3)
8574 /* SNB eDP training params */
8575 /* SNB A-stepping */
8576 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8577 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8578 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8579 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8580 /* SNB B-stepping */
8581 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
8582 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
8583 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
8584 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
8585 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
8586 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
8589 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
8590 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
8591 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
8592 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
8593 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
8594 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
8595 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
8598 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
8599 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
8600 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
8601 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
8602 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
8604 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
8606 #define VLV_PMWGICZ _MMIO(0x1300a4)
8608 #define RC6_LOCATION _MMIO(0xD40)
8609 #define RC6_CTX_IN_DRAM (1 << 0)
8610 #define RC6_CTX_BASE _MMIO(0xD48)
8611 #define RC6_CTX_BASE_MASK 0xFFFFFFF0
8612 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
8613 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
8614 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
8615 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
8616 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
8617 #define IDLE_TIME_MASK 0xFFFFF
8618 #define FORCEWAKE _MMIO(0xA18C)
8619 #define FORCEWAKE_VLV _MMIO(0x1300b0)
8620 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
8621 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
8622 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
8623 #define FORCEWAKE_ACK_HSW _MMIO(0x130044)
8624 #define FORCEWAKE_ACK _MMIO(0x130090)
8625 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
8626 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
8627 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
8628 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
8630 #define VLV_GTLC_PW_STATUS _MMIO(0x130094)
8631 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
8632 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
8633 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
8634 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
8635 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
8636 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
8637 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
8638 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
8639 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
8640 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
8641 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
8642 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
8643 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
8644 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
8645 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
8646 #define FORCEWAKE_KERNEL BIT(0)
8647 #define FORCEWAKE_USER BIT(1)
8648 #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
8649 #define FORCEWAKE_MT_ACK _MMIO(0x130040)
8650 #define ECOBUS _MMIO(0xa180)
8651 #define FORCEWAKE_MT_ENABLE (1 << 5)
8652 #define VLV_SPAREG2H _MMIO(0xA194)
8653 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
8654 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
8655 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
8657 #define GTFIFODBG _MMIO(0x120000)
8658 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
8659 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
8660 #define GT_FIFO_SBDROPERR (1 << 6)
8661 #define GT_FIFO_BLOBDROPERR (1 << 5)
8662 #define GT_FIFO_SB_READ_ABORTERR (1 << 4)
8663 #define GT_FIFO_DROPERR (1 << 3)
8664 #define GT_FIFO_OVFERR (1 << 2)
8665 #define GT_FIFO_IAWRERR (1 << 1)
8666 #define GT_FIFO_IARDERR (1 << 0)
8668 #define GTFIFOCTL _MMIO(0x120008)
8669 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
8670 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
8671 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
8672 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
8674 #define HSW_IDICR _MMIO(0x9008)
8675 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
8676 #define HSW_EDRAM_CAP _MMIO(0x120010)
8677 #define EDRAM_ENABLED 0x1
8678 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
8679 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
8680 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
8682 #define GEN6_UCGCTL1 _MMIO(0x9400)
8683 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
8684 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
8685 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
8686 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
8688 #define GEN6_UCGCTL2 _MMIO(0x9404)
8689 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
8690 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
8691 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
8692 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
8693 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
8694 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
8696 #define GEN6_UCGCTL3 _MMIO(0x9408)
8697 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
8699 #define GEN7_UCGCTL4 _MMIO(0x940c)
8700 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
8701 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
8703 #define GEN6_RCGCTL1 _MMIO(0x9410)
8704 #define GEN6_RCGCTL2 _MMIO(0x9414)
8705 #define GEN6_RSTCTL _MMIO(0x9420)
8707 #define GEN8_UCGCTL6 _MMIO(0x9430)
8708 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
8709 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
8710 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
8712 #define GEN6_GFXPAUSE _MMIO(0xA000)
8713 #define GEN6_RPNSWREQ _MMIO(0xA008)
8714 #define GEN6_TURBO_DISABLE (1 << 31)
8715 #define GEN6_FREQUENCY(x) ((x) << 25)
8716 #define HSW_FREQUENCY(x) ((x) << 24)
8717 #define GEN9_FREQUENCY(x) ((x) << 23)
8718 #define GEN6_OFFSET(x) ((x) << 19)
8719 #define GEN6_AGGRESSIVE_TURBO (0 << 15)
8720 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
8721 #define GEN6_RC_CONTROL _MMIO(0xA090)
8722 #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
8723 #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
8724 #define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
8725 #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
8726 #define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
8727 #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
8728 #define GEN7_RC_CTL_TO_MODE (1 << 28)
8729 #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
8730 #define GEN6_RC_CTL_HW_ENABLE (1 << 31)
8731 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
8732 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
8733 #define GEN6_RPSTAT1 _MMIO(0xA01C)
8734 #define GEN6_CAGF_SHIFT 8
8735 #define HSW_CAGF_SHIFT 7
8736 #define GEN9_CAGF_SHIFT 23
8737 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
8738 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
8739 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
8740 #define GEN6_RP_CONTROL _MMIO(0xA024)
8741 #define GEN6_RP_MEDIA_TURBO (1 << 11)
8742 #define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
8743 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
8744 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
8745 #define GEN6_RP_MEDIA_HW_MODE (1 << 9)
8746 #define GEN6_RP_MEDIA_SW_MODE (0 << 9)
8747 #define GEN6_RP_MEDIA_IS_GFX (1 << 8)
8748 #define GEN6_RP_ENABLE (1 << 7)
8749 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
8750 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
8751 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
8752 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
8753 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
8754 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
8755 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
8756 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
8757 #define GEN6_RP_EI_MASK 0xffffff
8758 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
8759 #define GEN6_RP_CUR_UP _MMIO(0xA054)
8760 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
8761 #define GEN6_RP_PREV_UP _MMIO(0xA058)
8762 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
8763 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
8764 #define GEN6_RP_CUR_DOWN _MMIO(0xA060)
8765 #define GEN6_RP_PREV_DOWN _MMIO(0xA064)
8766 #define GEN6_RP_UP_EI _MMIO(0xA068)
8767 #define GEN6_RP_DOWN_EI _MMIO(0xA06C)
8768 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
8769 #define GEN6_RPDEUHWTC _MMIO(0xA080)
8770 #define GEN6_RPDEUC _MMIO(0xA084)
8771 #define GEN6_RPDEUCSW _MMIO(0xA088)
8772 #define GEN6_RC_STATE _MMIO(0xA094)
8773 #define RC_SW_TARGET_STATE_SHIFT 16
8774 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
8775 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
8776 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
8777 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8778 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8779 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
8780 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
8781 #define GEN6_RC_SLEEP _MMIO(0xA0B0)
8782 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
8783 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
8784 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
8785 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
8786 #define VLV_RCEDATA _MMIO(0xA0BC)
8787 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
8788 #define GEN6_PMINTRMSK _MMIO(0xA168)
8789 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
8790 #define ARAT_EXPIRED_INTRMSK (1 << 9)
8791 #define GEN8_MISC_CTRL0 _MMIO(0xA180)
8792 #define VLV_PWRDWNUPCTL _MMIO(0xA294)
8793 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8794 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8795 #define GEN9_PG_ENABLE _MMIO(0xA210)
8796 #define GEN9_RENDER_PG_ENABLE REG_BIT(0)
8797 #define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
8798 #define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
8799 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8800 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8801 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
8803 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8804 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
8805 #define PIXEL_OVERLAP_CNT_SHIFT 30
8807 #define GEN6_PMISR _MMIO(0x44020)
8808 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
8809 #define GEN6_PMIIR _MMIO(0x44028)
8810 #define GEN6_PMIER _MMIO(0x4402C)
8811 #define GEN6_PM_MBOX_EVENT (1 << 25)
8812 #define GEN6_PM_THERMAL_EVENT (1 << 24)
8815 * For Gen11 these are in the upper word of the GPM_WGBOXPERF
8816 * registers. Shifting is handled on accessing the imr and ier.
8818 #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
8819 #define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
8820 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
8821 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
8822 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
8823 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
8824 GEN6_PM_RP_UP_THRESHOLD | \
8825 GEN6_PM_RP_DOWN_EI_EXPIRED | \
8826 GEN6_PM_RP_DOWN_THRESHOLD | \
8827 GEN6_PM_RP_DOWN_TIMEOUT)
8829 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
8830 #define GEN7_GT_SCRATCH_REG_NUM 8
8832 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
8833 #define VLV_GFX_CLK_STATUS_BIT (1 << 3)
8834 #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
8836 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
8837 #define VLV_COUNTER_CONTROL _MMIO(0x138104)
8838 #define VLV_COUNT_RANGE_HIGH (1 << 15)
8839 #define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
8840 #define VLV_RENDER_RC0_COUNT_EN (1 << 4)
8841 #define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
8842 #define VLV_RENDER_RC6_COUNT_EN (1 << 0)
8843 #define GEN6_GT_GFX_RC6 _MMIO(0x138108)
8844 #define VLV_GT_RENDER_RC6 _MMIO(0x138108)
8845 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
8847 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
8848 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
8849 #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
8850 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
8852 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8853 #define GEN6_PCODE_READY (1 << 31)
8854 #define GEN6_PCODE_ERROR_MASK 0xFF
8855 #define GEN6_PCODE_SUCCESS 0x0
8856 #define GEN6_PCODE_ILLEGAL_CMD 0x1
8857 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8858 #define GEN6_PCODE_TIMEOUT 0x3
8859 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8860 #define GEN7_PCODE_TIMEOUT 0x2
8861 #define GEN7_PCODE_ILLEGAL_DATA 0x3
8862 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8863 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
8864 #define GEN6_PCODE_READ_RC6VIDS 0x5
8865 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
8866 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
8867 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
8868 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
8869 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
8870 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
8871 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
8872 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
8873 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
8874 #define SKL_PCODE_CDCLK_CONTROL 0x7
8875 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
8876 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
8877 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8878 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8879 #define GEN6_READ_OC_PARAMS 0xc
8880 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
8881 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
8882 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
8883 #define GEN6_PCODE_READ_D_COMP 0x10
8884 #define GEN6_PCODE_WRITE_D_COMP 0x11
8885 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
8886 #define DISPLAY_IPS_CONTROL 0x19
8887 /* See also IPS_CTL */
8888 #define IPS_PCODE_CONTROL (1 << 30)
8889 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
8890 #define GEN9_PCODE_SAGV_CONTROL 0x21
8891 #define GEN9_SAGV_DISABLE 0x0
8892 #define GEN9_SAGV_IS_DISABLED 0x1
8893 #define GEN9_SAGV_ENABLE 0x3
8894 #define GEN6_PCODE_DATA _MMIO(0x138128)
8895 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
8896 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
8897 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
8899 #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
8900 #define GEN6_CORE_CPD_STATE_MASK (7 << 4)
8901 #define GEN6_RCn_MASK 7
8907 #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
8908 #define GEN8_LSLICESTAT_MASK 0x7
8910 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
8911 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
8912 #define CHV_SS_PG_ENABLE (1 << 1)
8913 #define CHV_EU08_PG_ENABLE (1 << 9)
8914 #define CHV_EU19_PG_ENABLE (1 << 17)
8915 #define CHV_EU210_PG_ENABLE (1 << 25)
8917 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
8918 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
8919 #define CHV_EU311_PG_ENABLE (1 << 1)
8921 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
8922 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8923 ((slice) % 3) * 0x4)
8924 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
8925 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
8926 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8928 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
8929 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8930 ((slice) % 3) * 0x8)
8931 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
8932 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8933 ((slice) % 3) * 0x8)
8934 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
8935 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
8936 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
8937 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
8938 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
8939 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
8940 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
8941 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
8943 #define GEN7_MISCCPCTL _MMIO(0x9424)
8944 #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
8945 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
8946 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
8947 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
8949 #define GEN8_GARBCNTL _MMIO(0xB004)
8950 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
8951 #define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
8952 #define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
8953 #define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
8955 #define GEN11_GLBLINVL _MMIO(0xB404)
8956 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
8957 #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
8959 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
8960 #define DFR_DISABLE (1 << 9)
8962 #define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
8963 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
8964 #define GEN11_HASH_CTRL_BIT0 (1 << 0)
8965 #define GEN11_HASH_CTRL_BIT4 (1 << 12)
8967 #define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
8968 #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
8969 #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
8971 #define GEN10_SAMPLER_MODE _MMIO(0xE18C)
8972 #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
8975 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
8976 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
8977 #define GEN7_PARITY_ERROR_VALID (1 << 13)
8978 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
8979 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
8980 #define GEN7_PARITY_ERROR_ROW(reg) \
8981 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8982 #define GEN7_PARITY_ERROR_BANK(reg) \
8983 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8984 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
8985 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8986 #define GEN7_L3CDERRST1_ENABLE (1 << 7)
8988 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8989 #define GEN7_L3LOG_SIZE 0x80
8991 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
8992 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
8993 #define GEN7_MAX_PS_THREAD_DEP (8 << 12)
8994 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
8995 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
8996 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
8998 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
8999 #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
9000 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
9002 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
9003 #define FLOW_CONTROL_ENABLE (1 << 15)
9004 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
9005 #define STALL_DOP_GATING_DISABLE (1 << 5)
9006 #define THROTTLE_12_5 (7 << 2)
9007 #define DISABLE_EARLY_EOT (1 << 1)
9009 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
9010 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
9011 #define DOP_CLOCK_GATING_DISABLE (1 << 0)
9012 #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
9013 #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
9015 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
9016 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
9018 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
9019 #define GEN8_ST_PO_DISABLE (1 << 13)
9021 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
9022 #define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
9023 #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
9024 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
9025 #define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
9026 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
9028 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
9029 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8)
9030 #define GEN9_ENABLE_YV12_BUGFIX (1 << 4)
9031 #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
9034 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
9035 #define INTEL_AUDIO_DEVCL 0x808629FB
9036 #define INTEL_AUDIO_DEVBLC 0x80862801
9037 #define INTEL_AUDIO_DEVCTG 0x80862802
9039 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
9040 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
9041 #define G4X_ELDV_DEVCTG (1 << 14)
9042 #define G4X_ELD_ADDR_MASK (0xf << 5)
9043 #define G4X_ELD_ACK (1 << 4)
9044 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
9046 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
9047 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
9048 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
9049 _IBX_HDMIW_HDMIEDID_B)
9050 #define _IBX_AUD_CNTL_ST_A 0xE20B4
9051 #define _IBX_AUD_CNTL_ST_B 0xE21B4
9052 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
9054 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
9055 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
9056 #define IBX_ELD_ACK (1 << 4)
9057 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
9058 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
9059 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
9061 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
9062 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
9063 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
9064 #define _CPT_AUD_CNTL_ST_A 0xE50B4
9065 #define _CPT_AUD_CNTL_ST_B 0xE51B4
9066 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
9067 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
9069 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
9070 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
9071 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
9072 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
9073 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
9074 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
9075 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
9077 /* These are the 4 32-bit write offset registers for each stream
9078 * output buffer. It determines the offset from the
9079 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9081 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
9083 #define _IBX_AUD_CONFIG_A 0xe2000
9084 #define _IBX_AUD_CONFIG_B 0xe2100
9085 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
9086 #define _CPT_AUD_CONFIG_A 0xe5000
9087 #define _CPT_AUD_CONFIG_B 0xe5100
9088 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
9089 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
9090 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
9091 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
9093 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
9094 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
9095 #define AUD_CONFIG_UPPER_N_SHIFT 20
9096 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
9097 #define AUD_CONFIG_LOWER_N_SHIFT 4
9098 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
9099 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
9100 #define AUD_CONFIG_N(n) \
9101 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
9102 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9103 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
9104 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
9105 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
9106 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
9107 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
9108 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
9109 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
9110 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
9111 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
9112 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
9113 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
9114 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
9115 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
9118 #define _HSW_AUD_CONFIG_A 0x65000
9119 #define _HSW_AUD_CONFIG_B 0x65100
9120 #define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
9122 #define _HSW_AUD_MISC_CTRL_A 0x65010
9123 #define _HSW_AUD_MISC_CTRL_B 0x65110
9124 #define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
9126 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028
9127 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128
9128 #define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
9129 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
9130 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
9131 #define AUD_CONFIG_M_MASK 0xfffff
9133 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
9134 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
9135 #define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
9137 /* Audio Digital Converter */
9138 #define _HSW_AUD_DIG_CNVT_1 0x65080
9139 #define _HSW_AUD_DIG_CNVT_2 0x65180
9140 #define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
9141 #define DIP_PORT_SEL_MASK 0x3
9143 #define _HSW_AUD_EDID_DATA_A 0x65050
9144 #define _HSW_AUD_EDID_DATA_B 0x65150
9145 #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
9147 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
9148 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
9149 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
9150 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
9151 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
9152 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
9154 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
9155 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
9158 * HSW - ICL power wells
9160 * Platforms have up to 3 power well control register sets, each set
9161 * controlling up to 16 power wells via a request/status HW flag tuple:
9162 * - main (HSW_PWR_WELL_CTL[1-4])
9163 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
9164 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
9165 * Each control register set consists of up to 4 registers used by different
9166 * sources that can request a power well to be enabled:
9167 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9168 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9169 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
9170 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9172 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
9173 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
9174 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
9175 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
9176 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
9177 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
9179 /* HSW/BDW power well */
9180 #define HSW_PW_CTL_IDX_GLOBAL 15
9182 /* SKL/BXT/GLK/CNL power wells */
9183 #define SKL_PW_CTL_IDX_PW_2 15
9184 #define SKL_PW_CTL_IDX_PW_1 14
9185 #define CNL_PW_CTL_IDX_AUX_F 12
9186 #define CNL_PW_CTL_IDX_AUX_D 11
9187 #define GLK_PW_CTL_IDX_AUX_C 10
9188 #define GLK_PW_CTL_IDX_AUX_B 9
9189 #define GLK_PW_CTL_IDX_AUX_A 8
9190 #define CNL_PW_CTL_IDX_DDI_F 6
9191 #define SKL_PW_CTL_IDX_DDI_D 4
9192 #define SKL_PW_CTL_IDX_DDI_C 3
9193 #define SKL_PW_CTL_IDX_DDI_B 2
9194 #define SKL_PW_CTL_IDX_DDI_A_E 1
9195 #define GLK_PW_CTL_IDX_DDI_A 1
9196 #define SKL_PW_CTL_IDX_MISC_IO 0
9198 /* ICL/TGL - power wells */
9199 #define TGL_PW_CTL_IDX_PW_5 4
9200 #define ICL_PW_CTL_IDX_PW_4 3
9201 #define ICL_PW_CTL_IDX_PW_3 2
9202 #define ICL_PW_CTL_IDX_PW_2 1
9203 #define ICL_PW_CTL_IDX_PW_1 0
9205 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
9206 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
9207 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
9208 #define TGL_PW_CTL_IDX_AUX_TBT6 14
9209 #define TGL_PW_CTL_IDX_AUX_TBT5 13
9210 #define TGL_PW_CTL_IDX_AUX_TBT4 12
9211 #define ICL_PW_CTL_IDX_AUX_TBT4 11
9212 #define TGL_PW_CTL_IDX_AUX_TBT3 11
9213 #define ICL_PW_CTL_IDX_AUX_TBT3 10
9214 #define TGL_PW_CTL_IDX_AUX_TBT2 10
9215 #define ICL_PW_CTL_IDX_AUX_TBT2 9
9216 #define TGL_PW_CTL_IDX_AUX_TBT1 9
9217 #define ICL_PW_CTL_IDX_AUX_TBT1 8
9218 #define TGL_PW_CTL_IDX_AUX_TC6 8
9219 #define TGL_PW_CTL_IDX_AUX_TC5 7
9220 #define TGL_PW_CTL_IDX_AUX_TC4 6
9221 #define ICL_PW_CTL_IDX_AUX_F 5
9222 #define TGL_PW_CTL_IDX_AUX_TC3 5
9223 #define ICL_PW_CTL_IDX_AUX_E 4
9224 #define TGL_PW_CTL_IDX_AUX_TC2 4
9225 #define ICL_PW_CTL_IDX_AUX_D 3
9226 #define TGL_PW_CTL_IDX_AUX_TC1 3
9227 #define ICL_PW_CTL_IDX_AUX_C 2
9228 #define ICL_PW_CTL_IDX_AUX_B 1
9229 #define ICL_PW_CTL_IDX_AUX_A 0
9231 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
9232 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
9233 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
9234 #define TGL_PW_CTL_IDX_DDI_TC6 8
9235 #define TGL_PW_CTL_IDX_DDI_TC5 7
9236 #define TGL_PW_CTL_IDX_DDI_TC4 6
9237 #define ICL_PW_CTL_IDX_DDI_F 5
9238 #define TGL_PW_CTL_IDX_DDI_TC3 5
9239 #define ICL_PW_CTL_IDX_DDI_E 4
9240 #define TGL_PW_CTL_IDX_DDI_TC2 4
9241 #define ICL_PW_CTL_IDX_DDI_D 3
9242 #define TGL_PW_CTL_IDX_DDI_TC1 3
9243 #define ICL_PW_CTL_IDX_DDI_C 2
9244 #define ICL_PW_CTL_IDX_DDI_B 1
9245 #define ICL_PW_CTL_IDX_DDI_A 0
9247 /* HSW - power well misc debug registers */
9248 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
9249 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
9250 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
9251 #define HSW_PWR_WELL_FORCE_ON (1 << 19)
9252 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
9254 /* SKL Fuse Status */
9255 enum skl_power_gate {
9263 #define SKL_FUSE_STATUS _MMIO(0x42000)
9264 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
9266 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9267 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9269 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
9270 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9272 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9273 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9275 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
9276 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9277 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
9279 #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
9280 #define _CNL_AUX_ANAOVRD1_B 0x162250
9281 #define _CNL_AUX_ANAOVRD1_C 0x162210
9282 #define _CNL_AUX_ANAOVRD1_D 0x1622D0
9283 #define _CNL_AUX_ANAOVRD1_F 0x162A90
9284 #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
9285 _CNL_AUX_ANAOVRD1_B, \
9286 _CNL_AUX_ANAOVRD1_C, \
9287 _CNL_AUX_ANAOVRD1_D, \
9288 _CNL_AUX_ANAOVRD1_F))
9289 #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
9290 #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
9292 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9293 #define _ICL_AUX_ANAOVRD1_A 0x162398
9294 #define _ICL_AUX_ANAOVRD1_B 0x6C398
9295 #define _TGL_AUX_ANAOVRD1_C 0x160398
9296 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9297 _ICL_AUX_ANAOVRD1_A, \
9298 _ICL_AUX_ANAOVRD1_B, \
9299 _TGL_AUX_ANAOVRD1_C))
9300 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
9301 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
9303 /* HDCP Key Registers */
9304 #define HDCP_KEY_CONF _MMIO(0x66c00)
9305 #define HDCP_AKSV_SEND_TRIGGER BIT(31)
9306 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
9307 #define HDCP_KEY_LOAD_TRIGGER BIT(8)
9308 #define HDCP_KEY_STATUS _MMIO(0x66c04)
9309 #define HDCP_FUSE_IN_PROGRESS BIT(7)
9310 #define HDCP_FUSE_ERROR BIT(6)
9311 #define HDCP_FUSE_DONE BIT(5)
9312 #define HDCP_KEY_LOAD_STATUS BIT(1)
9313 #define HDCP_KEY_LOAD_DONE BIT(0)
9314 #define HDCP_AKSV_LO _MMIO(0x66c10)
9315 #define HDCP_AKSV_HI _MMIO(0x66c14)
9317 /* HDCP Repeater Registers */
9318 #define HDCP_REP_CTL _MMIO(0x66d00)
9319 #define HDCP_DDIB_REP_PRESENT BIT(30)
9320 #define HDCP_DDIA_REP_PRESENT BIT(29)
9321 #define HDCP_DDIC_REP_PRESENT BIT(28)
9322 #define HDCP_DDID_REP_PRESENT BIT(27)
9323 #define HDCP_DDIF_REP_PRESENT BIT(26)
9324 #define HDCP_DDIE_REP_PRESENT BIT(25)
9325 #define HDCP_DDIB_SHA1_M0 (1 << 20)
9326 #define HDCP_DDIA_SHA1_M0 (2 << 20)
9327 #define HDCP_DDIC_SHA1_M0 (3 << 20)
9328 #define HDCP_DDID_SHA1_M0 (4 << 20)
9329 #define HDCP_DDIF_SHA1_M0 (5 << 20)
9330 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
9331 #define HDCP_SHA1_BUSY BIT(16)
9332 #define HDCP_SHA1_READY BIT(17)
9333 #define HDCP_SHA1_COMPLETE BIT(18)
9334 #define HDCP_SHA1_V_MATCH BIT(19)
9335 #define HDCP_SHA1_TEXT_32 (1 << 1)
9336 #define HDCP_SHA1_COMPLETE_HASH (2 << 1)
9337 #define HDCP_SHA1_TEXT_24 (4 << 1)
9338 #define HDCP_SHA1_TEXT_16 (5 << 1)
9339 #define HDCP_SHA1_TEXT_8 (6 << 1)
9340 #define HDCP_SHA1_TEXT_0 (7 << 1)
9341 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
9342 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
9343 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
9344 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
9345 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
9346 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
9347 #define HDCP_SHA_TEXT _MMIO(0x66d18)
9349 /* HDCP Auth Registers */
9350 #define _PORTA_HDCP_AUTHENC 0x66800
9351 #define _PORTB_HDCP_AUTHENC 0x66500
9352 #define _PORTC_HDCP_AUTHENC 0x66600
9353 #define _PORTD_HDCP_AUTHENC 0x66700
9354 #define _PORTE_HDCP_AUTHENC 0x66A00
9355 #define _PORTF_HDCP_AUTHENC 0x66900
9356 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
9357 _PORTA_HDCP_AUTHENC, \
9358 _PORTB_HDCP_AUTHENC, \
9359 _PORTC_HDCP_AUTHENC, \
9360 _PORTD_HDCP_AUTHENC, \
9361 _PORTE_HDCP_AUTHENC, \
9362 _PORTF_HDCP_AUTHENC) + (x))
9363 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
9364 #define HDCP_CONF_CAPTURE_AN BIT(0)
9365 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
9366 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
9367 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
9368 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
9369 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
9370 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
9371 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
9372 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
9373 #define HDCP_STATUS_STREAM_A_ENC BIT(31)
9374 #define HDCP_STATUS_STREAM_B_ENC BIT(30)
9375 #define HDCP_STATUS_STREAM_C_ENC BIT(29)
9376 #define HDCP_STATUS_STREAM_D_ENC BIT(28)
9377 #define HDCP_STATUS_AUTH BIT(21)
9378 #define HDCP_STATUS_ENC BIT(20)
9379 #define HDCP_STATUS_RI_MATCH BIT(19)
9380 #define HDCP_STATUS_R0_READY BIT(18)
9381 #define HDCP_STATUS_AN_READY BIT(17)
9382 #define HDCP_STATUS_CIPHER BIT(16)
9383 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
9385 /* HDCP2.2 Registers */
9386 #define _PORTA_HDCP2_BASE 0x66800
9387 #define _PORTB_HDCP2_BASE 0x66500
9388 #define _PORTC_HDCP2_BASE 0x66600
9389 #define _PORTD_HDCP2_BASE 0x66700
9390 #define _PORTE_HDCP2_BASE 0x66A00
9391 #define _PORTF_HDCP2_BASE 0x66900
9392 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
9393 _PORTA_HDCP2_BASE, \
9394 _PORTB_HDCP2_BASE, \
9395 _PORTC_HDCP2_BASE, \
9396 _PORTD_HDCP2_BASE, \
9397 _PORTE_HDCP2_BASE, \
9398 _PORTF_HDCP2_BASE) + (x))
9400 #define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
9401 #define AUTH_LINK_AUTHENTICATED BIT(31)
9402 #define AUTH_LINK_TYPE BIT(30)
9403 #define AUTH_FORCE_CLR_INPUTCTR BIT(19)
9404 #define AUTH_CLR_KEYS BIT(18)
9406 #define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
9407 #define CTL_LINK_ENCRYPTION_REQ BIT(31)
9409 #define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
9410 #define STREAM_ENCRYPTION_STATUS_A BIT(31)
9411 #define STREAM_ENCRYPTION_STATUS_B BIT(30)
9412 #define STREAM_ENCRYPTION_STATUS_C BIT(29)
9413 #define LINK_TYPE_STATUS BIT(22)
9414 #define LINK_AUTH_STATUS BIT(21)
9415 #define LINK_ENCRYPTION_STATUS BIT(20)
9417 /* Per-pipe DDI Function Control */
9418 #define _TRANS_DDI_FUNC_CTL_A 0x60400
9419 #define _TRANS_DDI_FUNC_CTL_B 0x61400
9420 #define _TRANS_DDI_FUNC_CTL_C 0x62400
9421 #define _TRANS_DDI_FUNC_CTL_D 0x63400
9422 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
9423 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
9424 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
9425 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9427 #define TRANS_DDI_FUNC_ENABLE (1 << 31)
9428 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9429 #define TRANS_DDI_PORT_SHIFT 28
9430 #define TGL_TRANS_DDI_PORT_SHIFT 27
9431 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
9432 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
9433 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
9434 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
9435 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
9436 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
9437 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
9438 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
9439 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
9440 #define TRANS_DDI_MODE_SELECT_FDI (4 << 24)
9441 #define TRANS_DDI_BPC_MASK (7 << 20)
9442 #define TRANS_DDI_BPC_8 (0 << 20)
9443 #define TRANS_DDI_BPC_10 (1 << 20)
9444 #define TRANS_DDI_BPC_6 (2 << 20)
9445 #define TRANS_DDI_BPC_12 (3 << 20)
9446 #define TRANS_DDI_PVSYNC (1 << 17)
9447 #define TRANS_DDI_PHSYNC (1 << 16)
9448 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
9449 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
9450 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
9451 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
9452 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
9453 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
9454 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
9455 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9456 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9457 #define TRANS_DDI_BFI_ENABLE (1 << 4)
9458 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
9459 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
9460 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9461 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9462 | TRANS_DDI_HDMI_SCRAMBLING)
9464 #define _TRANS_DDI_FUNC_CTL2_A 0x60404
9465 #define _TRANS_DDI_FUNC_CTL2_B 0x61404
9466 #define _TRANS_DDI_FUNC_CTL2_C 0x62404
9467 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
9468 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
9469 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
9470 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \
9471 _TRANS_DDI_FUNC_CTL2_A)
9472 #define PORT_SYNC_MODE_ENABLE (1 << 4)
9473 #define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) << 0)
9474 #define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0)
9475 #define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0
9477 /* DisplayPort Transport Control */
9478 #define _DP_TP_CTL_A 0x64040
9479 #define _DP_TP_CTL_B 0x64140
9480 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9481 #define DP_TP_CTL_ENABLE (1 << 31)
9482 #define DP_TP_CTL_FEC_ENABLE (1 << 30)
9483 #define DP_TP_CTL_MODE_SST (0 << 27)
9484 #define DP_TP_CTL_MODE_MST (1 << 27)
9485 #define DP_TP_CTL_FORCE_ACT (1 << 25)
9486 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
9487 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
9488 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
9489 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
9490 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
9491 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
9492 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
9493 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
9494 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
9495 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
9497 /* DisplayPort Transport Status */
9498 #define _DP_TP_STATUS_A 0x64044
9499 #define _DP_TP_STATUS_B 0x64144
9500 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
9501 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
9502 #define DP_TP_STATUS_IDLE_DONE (1 << 25)
9503 #define DP_TP_STATUS_ACT_SENT (1 << 24)
9504 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
9505 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
9506 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
9507 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
9508 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
9510 /* DDI Buffer Control */
9511 #define _DDI_BUF_CTL_A 0x64000
9512 #define _DDI_BUF_CTL_B 0x64100
9513 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
9514 #define DDI_BUF_CTL_ENABLE (1 << 31)
9515 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
9516 #define DDI_BUF_EMP_MASK (0xf << 24)
9517 #define DDI_BUF_PORT_REVERSAL (1 << 16)
9518 #define DDI_BUF_IS_IDLE (1 << 7)
9519 #define DDI_A_4_LANES (1 << 4)
9520 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
9521 #define DDI_PORT_WIDTH_MASK (7 << 1)
9522 #define DDI_PORT_WIDTH_SHIFT 1
9523 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
9525 /* DDI Buffer Translations */
9526 #define _DDI_BUF_TRANS_A 0x64E00
9527 #define _DDI_BUF_TRANS_B 0x64E60
9528 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9529 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
9530 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
9532 /* Sideband Interface (SBI) is programmed indirectly, via
9533 * SBI_ADDR, which contains the register offset; and SBI_DATA,
9534 * which contains the payload */
9535 #define SBI_ADDR _MMIO(0xC6000)
9536 #define SBI_DATA _MMIO(0xC6004)
9537 #define SBI_CTL_STAT _MMIO(0xC6008)
9538 #define SBI_CTL_DEST_ICLK (0x0 << 16)
9539 #define SBI_CTL_DEST_MPHY (0x1 << 16)
9540 #define SBI_CTL_OP_IORD (0x2 << 8)
9541 #define SBI_CTL_OP_IOWR (0x3 << 8)
9542 #define SBI_CTL_OP_CRRD (0x6 << 8)
9543 #define SBI_CTL_OP_CRWR (0x7 << 8)
9544 #define SBI_RESPONSE_FAIL (0x1 << 1)
9545 #define SBI_RESPONSE_SUCCESS (0x0 << 1)
9546 #define SBI_BUSY (0x1 << 0)
9547 #define SBI_READY (0x0 << 0)
9550 #define SBI_SSCDIVINTPHASE 0x0200
9551 #define SBI_SSCDIVINTPHASE6 0x0600
9552 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
9553 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
9554 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
9555 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
9556 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
9557 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
9558 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
9559 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
9560 #define SBI_SSCDITHPHASE 0x0204
9561 #define SBI_SSCCTL 0x020c
9562 #define SBI_SSCCTL6 0x060C
9563 #define SBI_SSCCTL_PATHALT (1 << 3)
9564 #define SBI_SSCCTL_DISABLE (1 << 0)
9565 #define SBI_SSCAUXDIV6 0x0610
9566 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
9567 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
9568 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
9569 #define SBI_DBUFF0 0x2a00
9570 #define SBI_GEN0 0x1f00
9571 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
9573 /* LPT PIXCLK_GATE */
9574 #define PIXCLK_GATE _MMIO(0xC6020)
9575 #define PIXCLK_GATE_UNGATE (1 << 0)
9576 #define PIXCLK_GATE_GATE (0 << 0)
9579 #define SPLL_CTL _MMIO(0x46020)
9580 #define SPLL_PLL_ENABLE (1 << 31)
9581 #define SPLL_REF_BCLK (0 << 28)
9582 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9583 #define SPLL_REF_NON_SSC_HSW (2 << 28)
9584 #define SPLL_REF_PCH_SSC_BDW (2 << 28)
9585 #define SPLL_REF_LCPLL (3 << 28)
9586 #define SPLL_REF_MASK (3 << 28)
9587 #define SPLL_FREQ_810MHz (0 << 26)
9588 #define SPLL_FREQ_1350MHz (1 << 26)
9589 #define SPLL_FREQ_2700MHz (2 << 26)
9590 #define SPLL_FREQ_MASK (3 << 26)
9593 #define _WRPLL_CTL1 0x46040
9594 #define _WRPLL_CTL2 0x46060
9595 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9596 #define WRPLL_PLL_ENABLE (1 << 31)
9597 #define WRPLL_REF_BCLK (0 << 28)
9598 #define WRPLL_REF_PCH_SSC (1 << 28)
9599 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9600 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
9601 #define WRPLL_REF_LCPLL (3 << 28)
9602 #define WRPLL_REF_MASK (3 << 28)
9603 /* WRPLL divider programming */
9604 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
9605 #define WRPLL_DIVIDER_REF_MASK (0xff)
9606 #define WRPLL_DIVIDER_POST(x) ((x) << 8)
9607 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
9608 #define WRPLL_DIVIDER_POST_SHIFT 8
9609 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
9610 #define WRPLL_DIVIDER_FB_SHIFT 16
9611 #define WRPLL_DIVIDER_FB_MASK (0xff << 16)
9613 /* Port clock selection */
9614 #define _PORT_CLK_SEL_A 0x46100
9615 #define _PORT_CLK_SEL_B 0x46104
9616 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9617 #define PORT_CLK_SEL_LCPLL_2700 (0 << 29)
9618 #define PORT_CLK_SEL_LCPLL_1350 (1 << 29)
9619 #define PORT_CLK_SEL_LCPLL_810 (2 << 29)
9620 #define PORT_CLK_SEL_SPLL (3 << 29)
9621 #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29)
9622 #define PORT_CLK_SEL_WRPLL1 (4 << 29)
9623 #define PORT_CLK_SEL_WRPLL2 (5 << 29)
9624 #define PORT_CLK_SEL_NONE (7 << 29)
9625 #define PORT_CLK_SEL_MASK (7 << 29)
9627 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
9628 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
9629 #define DDI_CLK_SEL_NONE (0x0 << 28)
9630 #define DDI_CLK_SEL_MG (0x8 << 28)
9631 #define DDI_CLK_SEL_TBT_162 (0xC << 28)
9632 #define DDI_CLK_SEL_TBT_270 (0xD << 28)
9633 #define DDI_CLK_SEL_TBT_540 (0xE << 28)
9634 #define DDI_CLK_SEL_TBT_810 (0xF << 28)
9635 #define DDI_CLK_SEL_MASK (0xF << 28)
9637 /* Transcoder clock selection */
9638 #define _TRANS_CLK_SEL_A 0x46140
9639 #define _TRANS_CLK_SEL_B 0x46144
9640 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
9641 /* For each transcoder, we need to select the corresponding port clock */
9642 #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
9643 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
9644 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
9645 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
9648 #define CDCLK_FREQ _MMIO(0x46200)
9650 #define _TRANSA_MSA_MISC 0x60410
9651 #define _TRANSB_MSA_MISC 0x61410
9652 #define _TRANSC_MSA_MISC 0x62410
9653 #define _TRANS_EDP_MSA_MISC 0x6f410
9654 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9656 #define TRANS_MSA_SYNC_CLK (1 << 0)
9657 #define TRANS_MSA_SAMPLING_444 (2 << 1)
9658 #define TRANS_MSA_CLRSP_YCBCR (2 << 3)
9659 #define TRANS_MSA_6_BPC (0 << 5)
9660 #define TRANS_MSA_8_BPC (1 << 5)
9661 #define TRANS_MSA_10_BPC (2 << 5)
9662 #define TRANS_MSA_12_BPC (3 << 5)
9663 #define TRANS_MSA_16_BPC (4 << 5)
9664 #define TRANS_MSA_CEA_RANGE (1 << 3)
9665 #define TRANS_MSA_USE_VSC_SDP (1 << 14)
9668 #define LCPLL_CTL _MMIO(0x130040)
9669 #define LCPLL_PLL_DISABLE (1 << 31)
9670 #define LCPLL_PLL_LOCK (1 << 30)
9671 #define LCPLL_REF_NON_SSC (0 << 28)
9672 #define LCPLL_REF_BCLK (2 << 28)
9673 #define LCPLL_REF_PCH_SSC (3 << 28)
9674 #define LCPLL_REF_MASK (3 << 28)
9675 #define LCPLL_CLK_FREQ_MASK (3 << 26)
9676 #define LCPLL_CLK_FREQ_450 (0 << 26)
9677 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
9678 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
9679 #define LCPLL_CLK_FREQ_675_BDW (3 << 26)
9680 #define LCPLL_CD_CLOCK_DISABLE (1 << 25)
9681 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
9682 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
9683 #define LCPLL_POWER_DOWN_ALLOW (1 << 22)
9684 #define LCPLL_CD_SOURCE_FCLK (1 << 21)
9685 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
9692 #define CDCLK_CTL _MMIO(0x46000)
9693 #define CDCLK_FREQ_SEL_MASK (3 << 26)
9694 #define CDCLK_FREQ_450_432 (0 << 26)
9695 #define CDCLK_FREQ_540 (1 << 26)
9696 #define CDCLK_FREQ_337_308 (2 << 26)
9697 #define CDCLK_FREQ_675_617 (3 << 26)
9698 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
9699 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
9700 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
9701 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
9702 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
9703 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
9704 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
9705 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
9706 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
9707 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
9708 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
9711 #define LCPLL1_CTL _MMIO(0x46010)
9712 #define LCPLL2_CTL _MMIO(0x46014)
9713 #define LCPLL_PLL_ENABLE (1 << 31)
9716 #define DPLL_CTRL1 _MMIO(0x6C058)
9717 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
9718 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
9719 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
9720 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
9721 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
9722 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
9723 #define DPLL_CTRL1_LINK_RATE_2700 0
9724 #define DPLL_CTRL1_LINK_RATE_1350 1
9725 #define DPLL_CTRL1_LINK_RATE_810 2
9726 #define DPLL_CTRL1_LINK_RATE_1620 3
9727 #define DPLL_CTRL1_LINK_RATE_1080 4
9728 #define DPLL_CTRL1_LINK_RATE_2160 5
9731 #define DPLL_CTRL2 _MMIO(0x6C05C)
9732 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
9733 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
9734 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
9735 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
9736 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
9739 #define DPLL_STATUS _MMIO(0x6C060)
9740 #define DPLL_LOCK(id) (1 << ((id) * 8))
9743 #define _DPLL1_CFGCR1 0x6C040
9744 #define _DPLL2_CFGCR1 0x6C048
9745 #define _DPLL3_CFGCR1 0x6C050
9746 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
9747 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
9748 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
9749 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
9751 #define _DPLL1_CFGCR2 0x6C044
9752 #define _DPLL2_CFGCR2 0x6C04C
9753 #define _DPLL3_CFGCR2 0x6C054
9754 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
9755 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
9756 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
9757 #define DPLL_CFGCR2_KDIV_MASK (3 << 5)
9758 #define DPLL_CFGCR2_KDIV(x) ((x) << 5)
9759 #define DPLL_CFGCR2_KDIV_5 (0 << 5)
9760 #define DPLL_CFGCR2_KDIV_2 (1 << 5)
9761 #define DPLL_CFGCR2_KDIV_3 (2 << 5)
9762 #define DPLL_CFGCR2_KDIV_1 (3 << 5)
9763 #define DPLL_CFGCR2_PDIV_MASK (7 << 2)
9764 #define DPLL_CFGCR2_PDIV(x) ((x) << 2)
9765 #define DPLL_CFGCR2_PDIV_1 (0 << 2)
9766 #define DPLL_CFGCR2_PDIV_2 (1 << 2)
9767 #define DPLL_CFGCR2_PDIV_3 (2 << 2)
9768 #define DPLL_CFGCR2_PDIV_7 (4 << 2)
9769 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
9771 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
9772 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
9777 #define DPCLKA_CFGCR0 _MMIO(0x6C200)
9778 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
9780 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
9782 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9783 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9785 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
9786 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
9787 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
9789 (tc_port) - PORT_TC4 + 21))
9790 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
9791 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
9792 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
9795 #define DPLL0_ENABLE 0x46010
9796 #define DPLL1_ENABLE 0x46014
9797 #define PLL_ENABLE (1 << 31)
9798 #define PLL_LOCK (1 << 30)
9799 #define PLL_POWER_ENABLE (1 << 27)
9800 #define PLL_POWER_STATE (1 << 26)
9801 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
9803 #define TBT_PLL_ENABLE _MMIO(0x46020)
9805 #define _MG_PLL1_ENABLE 0x46030
9806 #define _MG_PLL2_ENABLE 0x46034
9807 #define _MG_PLL3_ENABLE 0x46038
9808 #define _MG_PLL4_ENABLE 0x4603C
9809 /* Bits are the same as DPLL0_ENABLE */
9810 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
9813 #define _MG_REFCLKIN_CTL_PORT1 0x16892C
9814 #define _MG_REFCLKIN_CTL_PORT2 0x16992C
9815 #define _MG_REFCLKIN_CTL_PORT3 0x16A92C
9816 #define _MG_REFCLKIN_CTL_PORT4 0x16B92C
9817 #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
9818 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
9819 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
9820 _MG_REFCLKIN_CTL_PORT1, \
9821 _MG_REFCLKIN_CTL_PORT2)
9823 #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
9824 #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
9825 #define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
9826 #define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
9827 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
9828 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
9829 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
9830 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
9831 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
9832 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
9833 _MG_CLKTOP2_CORECLKCTL1_PORT2)
9835 #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
9836 #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
9837 #define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
9838 #define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
9839 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
9840 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
9841 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
9842 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
9843 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
9844 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
9845 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
9846 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
9847 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
9848 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
9849 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
9850 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
9851 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
9852 _MG_CLKTOP2_HSCLKCTL_PORT1, \
9853 _MG_CLKTOP2_HSCLKCTL_PORT2)
9855 #define _MG_PLL_DIV0_PORT1 0x168A00
9856 #define _MG_PLL_DIV0_PORT2 0x169A00
9857 #define _MG_PLL_DIV0_PORT3 0x16AA00
9858 #define _MG_PLL_DIV0_PORT4 0x16BA00
9859 #define MG_PLL_DIV0_FRACNEN_H (1 << 30)
9860 #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
9861 #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
9862 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
9863 #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
9864 #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
9865 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
9868 #define _MG_PLL_DIV1_PORT1 0x168A04
9869 #define _MG_PLL_DIV1_PORT2 0x169A04
9870 #define _MG_PLL_DIV1_PORT3 0x16AA04
9871 #define _MG_PLL_DIV1_PORT4 0x16BA04
9872 #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
9873 #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
9874 #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
9875 #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
9876 #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
9877 #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
9878 #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
9879 #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
9880 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
9883 #define _MG_PLL_LF_PORT1 0x168A08
9884 #define _MG_PLL_LF_PORT2 0x169A08
9885 #define _MG_PLL_LF_PORT3 0x16AA08
9886 #define _MG_PLL_LF_PORT4 0x16BA08
9887 #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
9888 #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
9889 #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
9890 #define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
9891 #define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
9892 #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
9893 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
9896 #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
9897 #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
9898 #define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
9899 #define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
9900 #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
9901 #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
9902 #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
9903 #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
9904 #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
9905 #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
9906 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
9907 _MG_PLL_FRAC_LOCK_PORT1, \
9908 _MG_PLL_FRAC_LOCK_PORT2)
9910 #define _MG_PLL_SSC_PORT1 0x168A10
9911 #define _MG_PLL_SSC_PORT2 0x169A10
9912 #define _MG_PLL_SSC_PORT3 0x16AA10
9913 #define _MG_PLL_SSC_PORT4 0x16BA10
9914 #define MG_PLL_SSC_EN (1 << 28)
9915 #define MG_PLL_SSC_TYPE(x) ((x) << 26)
9916 #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
9917 #define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
9918 #define MG_PLL_SSC_FLLEN (1 << 9)
9919 #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
9920 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
9923 #define _MG_PLL_BIAS_PORT1 0x168A14
9924 #define _MG_PLL_BIAS_PORT2 0x169A14
9925 #define _MG_PLL_BIAS_PORT3 0x16AA14
9926 #define _MG_PLL_BIAS_PORT4 0x16BA14
9927 #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
9928 #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
9929 #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
9930 #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
9931 #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
9932 #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
9933 #define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
9934 #define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
9935 #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
9936 #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
9937 #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
9938 #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
9939 #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
9940 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
9943 #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
9944 #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
9945 #define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
9946 #define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
9947 #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
9948 #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
9949 #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
9950 #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
9951 #define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
9952 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
9953 _MG_PLL_TDC_COLDST_BIAS_PORT1, \
9954 _MG_PLL_TDC_COLDST_BIAS_PORT2)
9956 #define _CNL_DPLL0_CFGCR0 0x6C000
9957 #define _CNL_DPLL1_CFGCR0 0x6C080
9958 #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
9959 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
9960 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
9961 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
9962 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
9963 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
9964 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
9965 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
9966 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
9967 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
9968 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
9969 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
9970 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
9971 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
9972 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
9973 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
9974 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
9976 #define _CNL_DPLL0_CFGCR1 0x6C004
9977 #define _CNL_DPLL1_CFGCR1 0x6C084
9978 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
9979 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
9980 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
9981 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
9982 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
9983 #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
9984 #define DPLL_CFGCR1_KDIV_SHIFT (6)
9985 #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
9986 #define DPLL_CFGCR1_KDIV_1 (1 << 6)
9987 #define DPLL_CFGCR1_KDIV_2 (2 << 6)
9988 #define DPLL_CFGCR1_KDIV_3 (4 << 6)
9989 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
9990 #define DPLL_CFGCR1_PDIV_SHIFT (2)
9991 #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
9992 #define DPLL_CFGCR1_PDIV_2 (1 << 2)
9993 #define DPLL_CFGCR1_PDIV_3 (2 << 2)
9994 #define DPLL_CFGCR1_PDIV_5 (4 << 2)
9995 #define DPLL_CFGCR1_PDIV_7 (8 << 2)
9996 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
9997 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
9998 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
9999 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
10001 #define _ICL_DPLL0_CFGCR0 0x164000
10002 #define _ICL_DPLL1_CFGCR0 0x164080
10003 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
10006 #define _ICL_DPLL0_CFGCR1 0x164004
10007 #define _ICL_DPLL1_CFGCR1 0x164084
10008 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
10011 #define _TGL_DPLL0_CFGCR0 0x164284
10012 #define _TGL_DPLL1_CFGCR0 0x16428C
10013 /* TODO: add DPLL4 */
10014 #define _TGL_TBTPLL_CFGCR0 0x16429C
10015 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
10016 _TGL_DPLL1_CFGCR0, \
10017 _TGL_TBTPLL_CFGCR0)
10019 #define _TGL_DPLL0_CFGCR1 0x164288
10020 #define _TGL_DPLL1_CFGCR1 0x164290
10021 /* TODO: add DPLL4 */
10022 #define _TGL_TBTPLL_CFGCR1 0x1642A0
10023 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
10024 _TGL_DPLL1_CFGCR1, \
10025 _TGL_TBTPLL_CFGCR1)
10027 /* BXT display engine PLL */
10028 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
10029 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
10030 #define BXT_DE_PLL_RATIO_MASK 0xff
10032 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
10033 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
10034 #define BXT_DE_PLL_LOCK (1 << 30)
10035 #define CNL_CDCLK_PLL_RATIO(x) (x)
10036 #define CNL_CDCLK_PLL_RATIO_MASK 0xff
10039 #define DC_STATE_EN _MMIO(0x45504)
10040 #define DC_STATE_DISABLE 0
10041 #define DC_STATE_EN_UPTO_DC5 (1 << 0)
10042 #define DC_STATE_EN_DC9 (1 << 3)
10043 #define DC_STATE_EN_UPTO_DC6 (2 << 0)
10044 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
10046 #define DC_STATE_DEBUG _MMIO(0x45520)
10047 #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
10048 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
10050 #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
10051 #define BXT_REQ_DATA_MASK 0x3F
10052 #define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12
10053 #define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12)
10054 #define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333
10056 #define BXT_D_CR_DRP0_DUNIT8 0x1000
10057 #define BXT_D_CR_DRP0_DUNIT9 0x1200
10058 #define BXT_D_CR_DRP0_DUNIT_START 8
10059 #define BXT_D_CR_DRP0_DUNIT_END 11
10060 #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
10061 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
10062 BXT_D_CR_DRP0_DUNIT9))
10063 #define BXT_DRAM_RANK_MASK 0x3
10064 #define BXT_DRAM_RANK_SINGLE 0x1
10065 #define BXT_DRAM_RANK_DUAL 0x3
10066 #define BXT_DRAM_WIDTH_MASK (0x3 << 4)
10067 #define BXT_DRAM_WIDTH_SHIFT 4
10068 #define BXT_DRAM_WIDTH_X8 (0x0 << 4)
10069 #define BXT_DRAM_WIDTH_X16 (0x1 << 4)
10070 #define BXT_DRAM_WIDTH_X32 (0x2 << 4)
10071 #define BXT_DRAM_WIDTH_X64 (0x3 << 4)
10072 #define BXT_DRAM_SIZE_MASK (0x7 << 6)
10073 #define BXT_DRAM_SIZE_SHIFT 6
10074 #define BXT_DRAM_SIZE_4GBIT (0x0 << 6)
10075 #define BXT_DRAM_SIZE_6GBIT (0x1 << 6)
10076 #define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
10077 #define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
10078 #define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
10079 #define BXT_DRAM_TYPE_MASK (0x7 << 22)
10080 #define BXT_DRAM_TYPE_SHIFT 22
10081 #define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
10082 #define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
10083 #define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
10084 #define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
10086 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
10087 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
10088 #define SKL_REQ_DATA_MASK (0xF << 0)
10090 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
10091 #define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
10092 #define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
10093 #define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
10094 #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
10095 #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
10097 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
10098 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
10099 #define SKL_DRAM_S_SHIFT 16
10100 #define SKL_DRAM_SIZE_MASK 0x3F
10101 #define SKL_DRAM_WIDTH_MASK (0x3 << 8)
10102 #define SKL_DRAM_WIDTH_SHIFT 8
10103 #define SKL_DRAM_WIDTH_X8 (0x0 << 8)
10104 #define SKL_DRAM_WIDTH_X16 (0x1 << 8)
10105 #define SKL_DRAM_WIDTH_X32 (0x2 << 8)
10106 #define SKL_DRAM_RANK_MASK (0x1 << 10)
10107 #define SKL_DRAM_RANK_SHIFT 10
10108 #define SKL_DRAM_RANK_1 (0x0 << 10)
10109 #define SKL_DRAM_RANK_2 (0x1 << 10)
10110 #define SKL_DRAM_RANK_MASK (0x1 << 10)
10111 #define CNL_DRAM_SIZE_MASK 0x7F
10112 #define CNL_DRAM_WIDTH_MASK (0x3 << 7)
10113 #define CNL_DRAM_WIDTH_SHIFT 7
10114 #define CNL_DRAM_WIDTH_X8 (0x0 << 7)
10115 #define CNL_DRAM_WIDTH_X16 (0x1 << 7)
10116 #define CNL_DRAM_WIDTH_X32 (0x2 << 7)
10117 #define CNL_DRAM_RANK_MASK (0x3 << 9)
10118 #define CNL_DRAM_RANK_SHIFT 9
10119 #define CNL_DRAM_RANK_1 (0x0 << 9)
10120 #define CNL_DRAM_RANK_2 (0x1 << 9)
10121 #define CNL_DRAM_RANK_3 (0x2 << 9)
10122 #define CNL_DRAM_RANK_4 (0x3 << 9)
10124 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
10125 * since on HSW we can't write to it using I915_WRITE. */
10126 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
10127 #define D_COMP_BDW _MMIO(0x138144)
10128 #define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
10129 #define D_COMP_COMP_FORCE (1 << 8)
10130 #define D_COMP_COMP_DISABLE (1 << 0)
10132 /* Pipe WM_LINETIME - watermark line time */
10133 #define _PIPE_WM_LINETIME_A 0x45270
10134 #define _PIPE_WM_LINETIME_B 0x45274
10135 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
10136 #define PIPE_WM_LINETIME_MASK (0x1ff)
10137 #define PIPE_WM_LINETIME_TIME(x) ((x))
10138 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16)
10139 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16)
10142 #define SFUSE_STRAP _MMIO(0xc2014)
10143 #define SFUSE_STRAP_FUSE_LOCK (1 << 13)
10144 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
10145 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
10146 #define SFUSE_STRAP_CRT_DISABLED (1 << 6)
10147 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
10148 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
10149 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
10150 #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
10152 #define WM_MISC _MMIO(0x45260)
10153 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
10155 #define WM_DBG _MMIO(0x45280)
10156 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
10157 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
10158 #define WM_DBG_DISALLOW_SPRITE (1 << 2)
10161 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
10162 #define _PIPE_A_CSC_COEFF_BY 0x49014
10163 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
10164 #define _PIPE_A_CSC_COEFF_BU 0x4901c
10165 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
10166 #define _PIPE_A_CSC_COEFF_BV 0x49024
10168 #define _PIPE_A_CSC_MODE 0x49028
10169 #define ICL_CSC_ENABLE (1 << 31)
10170 #define ICL_OUTPUT_CSC_ENABLE (1 << 30)
10171 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
10172 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
10173 #define CSC_MODE_YUV_TO_RGB (1 << 0)
10175 #define _PIPE_A_CSC_PREOFF_HI 0x49030
10176 #define _PIPE_A_CSC_PREOFF_ME 0x49034
10177 #define _PIPE_A_CSC_PREOFF_LO 0x49038
10178 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
10179 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
10180 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
10182 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
10183 #define _PIPE_B_CSC_COEFF_BY 0x49114
10184 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
10185 #define _PIPE_B_CSC_COEFF_BU 0x4911c
10186 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
10187 #define _PIPE_B_CSC_COEFF_BV 0x49124
10188 #define _PIPE_B_CSC_MODE 0x49128
10189 #define _PIPE_B_CSC_PREOFF_HI 0x49130
10190 #define _PIPE_B_CSC_PREOFF_ME 0x49134
10191 #define _PIPE_B_CSC_PREOFF_LO 0x49138
10192 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
10193 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
10194 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
10196 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
10197 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
10198 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
10199 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
10200 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
10201 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
10202 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
10203 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
10204 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
10205 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
10206 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
10207 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
10208 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
10210 /* Pipe Output CSC */
10211 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
10212 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
10213 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
10214 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
10215 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
10216 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
10217 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
10218 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
10219 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
10220 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
10221 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
10222 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
10224 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
10225 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
10226 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
10227 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
10228 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
10229 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
10230 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
10231 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
10232 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
10233 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
10234 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
10235 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
10237 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
10238 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
10239 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
10240 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
10241 _PIPE_A_OUTPUT_CSC_COEFF_BY, \
10242 _PIPE_B_OUTPUT_CSC_COEFF_BY)
10243 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
10244 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
10245 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
10246 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
10247 _PIPE_A_OUTPUT_CSC_COEFF_BU, \
10248 _PIPE_B_OUTPUT_CSC_COEFF_BU)
10249 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
10250 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
10251 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
10252 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
10253 _PIPE_A_OUTPUT_CSC_COEFF_BV, \
10254 _PIPE_B_OUTPUT_CSC_COEFF_BV)
10255 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
10256 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
10257 _PIPE_B_OUTPUT_CSC_PREOFF_HI)
10258 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
10259 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
10260 _PIPE_B_OUTPUT_CSC_PREOFF_ME)
10261 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
10262 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
10263 _PIPE_B_OUTPUT_CSC_PREOFF_LO)
10264 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
10265 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
10266 _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
10267 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
10268 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
10269 _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
10270 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
10271 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
10272 _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
10274 /* pipe degamma/gamma LUTs on IVB+ */
10275 #define _PAL_PREC_INDEX_A 0x4A400
10276 #define _PAL_PREC_INDEX_B 0x4AC00
10277 #define _PAL_PREC_INDEX_C 0x4B400
10278 #define PAL_PREC_10_12_BIT (0 << 31)
10279 #define PAL_PREC_SPLIT_MODE (1 << 31)
10280 #define PAL_PREC_AUTO_INCREMENT (1 << 15)
10281 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
10282 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
10283 #define _PAL_PREC_DATA_A 0x4A404
10284 #define _PAL_PREC_DATA_B 0x4AC04
10285 #define _PAL_PREC_DATA_C 0x4B404
10286 #define _PAL_PREC_GC_MAX_A 0x4A410
10287 #define _PAL_PREC_GC_MAX_B 0x4AC10
10288 #define _PAL_PREC_GC_MAX_C 0x4B410
10289 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
10290 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
10291 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
10292 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
10293 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
10294 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
10296 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
10297 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
10298 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
10299 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
10300 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
10302 #define _PRE_CSC_GAMC_INDEX_A 0x4A484
10303 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
10304 #define _PRE_CSC_GAMC_INDEX_C 0x4B484
10305 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
10306 #define _PRE_CSC_GAMC_DATA_A 0x4A488
10307 #define _PRE_CSC_GAMC_DATA_B 0x4AC88
10308 #define _PRE_CSC_GAMC_DATA_C 0x4B488
10310 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
10311 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
10313 /* ICL Multi segmented gamma */
10314 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
10315 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
10316 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
10317 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
10319 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
10320 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
10322 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
10323 _PAL_PREC_MULTI_SEG_INDEX_A, \
10324 _PAL_PREC_MULTI_SEG_INDEX_B)
10325 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
10326 _PAL_PREC_MULTI_SEG_DATA_A, \
10327 _PAL_PREC_MULTI_SEG_DATA_B)
10329 /* pipe CSC & degamma/gamma LUTs on CHV */
10330 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
10331 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
10332 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
10333 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
10334 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
10335 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
10336 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
10337 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
10338 #define CGM_PIPE_MODE_GAMMA (1 << 2)
10339 #define CGM_PIPE_MODE_CSC (1 << 1)
10340 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
10342 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
10343 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
10344 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
10345 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
10346 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
10347 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
10348 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
10349 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
10351 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
10352 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
10353 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
10354 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
10355 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
10356 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
10357 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
10358 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
10360 /* MIPI DSI registers */
10362 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
10363 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
10366 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
10369 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
10370 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
10371 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
10372 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
10374 #define _ICL_DSI_ESC_CLK_DIV0 0x6b090
10375 #define _ICL_DSI_ESC_CLK_DIV1 0x6b890
10376 #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \
10377 _ICL_DSI_ESC_CLK_DIV0, \
10378 _ICL_DSI_ESC_CLK_DIV1)
10379 #define _ICL_DPHY_ESC_CLK_DIV0 0x162190
10380 #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190
10381 #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \
10382 _ICL_DPHY_ESC_CLK_DIV0, \
10383 _ICL_DPHY_ESC_CLK_DIV1)
10384 #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16)
10385 #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
10386 #define ICL_ESC_CLK_DIV_MASK 0x1ff
10387 #define ICL_ESC_CLK_DIV_SHIFT 0
10388 #define DSI_MAX_ESC_CLK 20000 /* in KHz */
10390 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
10391 #define GEN4_TIMESTAMP _MMIO(0x2358)
10392 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
10393 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
10395 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
10396 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
10397 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
10398 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
10399 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
10401 #define _PIPE_FRMTMSTMP_A 0x70048
10402 #define PIPE_FRMTMSTMP(pipe) \
10403 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
10405 /* BXT MIPI clock controls */
10406 #define BXT_MAX_VAR_OUTPUT_KHZ 39500
10408 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
10409 #define BXT_MIPI1_DIV_SHIFT 26
10410 #define BXT_MIPI2_DIV_SHIFT 10
10411 #define BXT_MIPI_DIV_SHIFT(port) \
10412 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
10413 BXT_MIPI2_DIV_SHIFT)
10415 /* TX control divider to select actual TX clock output from (8x/var) */
10416 #define BXT_MIPI1_TX_ESCLK_SHIFT 26
10417 #define BXT_MIPI2_TX_ESCLK_SHIFT 10
10418 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
10419 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
10420 BXT_MIPI2_TX_ESCLK_SHIFT)
10421 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
10422 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
10423 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
10424 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
10425 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
10426 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
10427 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
10428 /* RX upper control divider to select actual RX clock output from 8x */
10429 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
10430 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
10431 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
10432 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
10433 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
10434 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
10435 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
10436 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
10437 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
10438 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
10439 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
10440 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
10441 /* 8/3X divider to select the actual 8/3X clock output from 8x */
10442 #define BXT_MIPI1_8X_BY3_SHIFT 19
10443 #define BXT_MIPI2_8X_BY3_SHIFT 3
10444 #define BXT_MIPI_8X_BY3_SHIFT(port) \
10445 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
10446 BXT_MIPI2_8X_BY3_SHIFT)
10447 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
10448 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
10449 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
10450 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
10451 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
10452 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
10453 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
10454 /* RX lower control divider to select actual RX clock output from 8x */
10455 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
10456 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
10457 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
10458 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
10459 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
10460 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
10461 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
10462 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
10463 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
10464 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
10465 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
10466 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
10468 #define RX_DIVIDER_BIT_1_2 0x3
10469 #define RX_DIVIDER_BIT_3_4 0xC
10471 /* BXT MIPI mode configure */
10472 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
10473 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
10474 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
10475 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
10477 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
10478 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
10479 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
10480 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
10482 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
10483 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
10484 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
10485 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
10487 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
10488 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
10489 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10490 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10491 #define BXT_DSIC_16X_BY1 (0 << 10)
10492 #define BXT_DSIC_16X_BY2 (1 << 10)
10493 #define BXT_DSIC_16X_BY3 (2 << 10)
10494 #define BXT_DSIC_16X_BY4 (3 << 10)
10495 #define BXT_DSIC_16X_MASK (3 << 10)
10496 #define BXT_DSIA_16X_BY1 (0 << 8)
10497 #define BXT_DSIA_16X_BY2 (1 << 8)
10498 #define BXT_DSIA_16X_BY3 (2 << 8)
10499 #define BXT_DSIA_16X_BY4 (3 << 8)
10500 #define BXT_DSIA_16X_MASK (3 << 8)
10501 #define BXT_DSI_FREQ_SEL_SHIFT 8
10502 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
10504 #define BXT_DSI_PLL_RATIO_MAX 0x7D
10505 #define BXT_DSI_PLL_RATIO_MIN 0x22
10506 #define GLK_DSI_PLL_RATIO_MAX 0x6F
10507 #define GLK_DSI_PLL_RATIO_MIN 0x22
10508 #define BXT_DSI_PLL_RATIO_MASK 0xFF
10509 #define BXT_REF_CLOCK_KHZ 19200
10511 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
10512 #define BXT_DSI_PLL_DO_ENABLE (1 << 31)
10513 #define BXT_DSI_PLL_LOCKED (1 << 30)
10515 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
10516 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
10517 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
10519 /* BXT port control */
10520 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0
10521 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
10522 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
10524 /* ICL DSI MODE control */
10525 #define _ICL_DSI_IO_MODECTL_0 0x6B094
10526 #define _ICL_DSI_IO_MODECTL_1 0x6B894
10527 #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \
10528 _ICL_DSI_IO_MODECTL_0, \
10529 _ICL_DSI_IO_MODECTL_1)
10530 #define COMBO_PHY_MODE_DSI (1 << 0)
10532 /* Display Stream Splitter Control */
10533 #define DSS_CTL1 _MMIO(0x67400)
10534 #define SPLITTER_ENABLE (1 << 31)
10535 #define JOINER_ENABLE (1 << 30)
10536 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
10537 #define DUAL_LINK_MODE_FRONTBACK (0 << 24)
10538 #define OVERLAP_PIXELS_MASK (0xf << 16)
10539 #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
10540 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
10541 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
10542 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
10544 #define DSS_CTL2 _MMIO(0x67404)
10545 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
10546 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
10547 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
10548 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
10550 #define _ICL_PIPE_DSS_CTL1_PB 0x78200
10551 #define _ICL_PIPE_DSS_CTL1_PC 0x78400
10552 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10553 _ICL_PIPE_DSS_CTL1_PB, \
10554 _ICL_PIPE_DSS_CTL1_PC)
10555 #define BIG_JOINER_ENABLE (1 << 29)
10556 #define MASTER_BIG_JOINER_ENABLE (1 << 28)
10557 #define VGA_CENTERING_ENABLE (1 << 27)
10559 #define _ICL_PIPE_DSS_CTL2_PB 0x78204
10560 #define _ICL_PIPE_DSS_CTL2_PC 0x78404
10561 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10562 _ICL_PIPE_DSS_CTL2_PB, \
10563 _ICL_PIPE_DSS_CTL2_PC)
10565 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
10566 #define STAP_SELECT (1 << 0)
10568 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
10569 #define HS_IO_CTRL_SELECT (1 << 0)
10571 #define DPI_ENABLE (1 << 31) /* A + C */
10572 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
10573 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
10574 #define DUAL_LINK_MODE_SHIFT 26
10575 #define DUAL_LINK_MODE_MASK (1 << 26)
10576 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
10577 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
10578 #define DITHERING_ENABLE (1 << 25) /* A + C */
10579 #define FLOPPED_HSTX (1 << 23)
10580 #define DE_INVERT (1 << 19) /* XXX */
10581 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
10582 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
10583 #define AFE_LATCHOUT (1 << 17)
10584 #define LP_OUTPUT_HOLD (1 << 16)
10585 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
10586 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
10587 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
10588 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
10589 #define CSB_SHIFT 9
10590 #define CSB_MASK (3 << 9)
10591 #define CSB_20MHZ (0 << 9)
10592 #define CSB_10MHZ (1 << 9)
10593 #define CSB_40MHZ (2 << 9)
10594 #define BANDGAP_MASK (1 << 8)
10595 #define BANDGAP_PNW_CIRCUIT (0 << 8)
10596 #define BANDGAP_LNC_CIRCUIT (1 << 8)
10597 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
10598 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
10599 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
10600 #define TEARING_EFFECT_SHIFT 2 /* A + C */
10601 #define TEARING_EFFECT_MASK (3 << 2)
10602 #define TEARING_EFFECT_OFF (0 << 2)
10603 #define TEARING_EFFECT_DSI (1 << 2)
10604 #define TEARING_EFFECT_GPIO (2 << 2)
10605 #define LANE_CONFIGURATION_SHIFT 0
10606 #define LANE_CONFIGURATION_MASK (3 << 0)
10607 #define LANE_CONFIGURATION_4LANE (0 << 0)
10608 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
10609 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
10611 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
10612 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
10613 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
10614 #define TEARING_EFFECT_DELAY_SHIFT 0
10615 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
10617 /* XXX: all bits reserved */
10618 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
10620 /* MIPI DSI Controller and D-PHY registers */
10622 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
10623 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
10624 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
10625 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
10626 #define ULPS_STATE_MASK (3 << 1)
10627 #define ULPS_STATE_ENTER (2 << 1)
10628 #define ULPS_STATE_EXIT (1 << 1)
10629 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
10630 #define DEVICE_READY (1 << 0)
10632 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
10633 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
10634 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
10635 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
10636 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
10637 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
10638 #define TEARING_EFFECT (1 << 31)
10639 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
10640 #define GEN_READ_DATA_AVAIL (1 << 29)
10641 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
10642 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
10643 #define RX_PROT_VIOLATION (1 << 26)
10644 #define RX_INVALID_TX_LENGTH (1 << 25)
10645 #define ACK_WITH_NO_ERROR (1 << 24)
10646 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
10647 #define LP_RX_TIMEOUT (1 << 22)
10648 #define HS_TX_TIMEOUT (1 << 21)
10649 #define DPI_FIFO_UNDERRUN (1 << 20)
10650 #define LOW_CONTENTION (1 << 19)
10651 #define HIGH_CONTENTION (1 << 18)
10652 #define TXDSI_VC_ID_INVALID (1 << 17)
10653 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
10654 #define TXCHECKSUM_ERROR (1 << 15)
10655 #define TXECC_MULTIBIT_ERROR (1 << 14)
10656 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
10657 #define TXFALSE_CONTROL_ERROR (1 << 12)
10658 #define RXDSI_VC_ID_INVALID (1 << 11)
10659 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
10660 #define RXCHECKSUM_ERROR (1 << 9)
10661 #define RXECC_MULTIBIT_ERROR (1 << 8)
10662 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
10663 #define RXFALSE_CONTROL_ERROR (1 << 6)
10664 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
10665 #define RX_LP_TX_SYNC_ERROR (1 << 4)
10666 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
10667 #define RXEOT_SYNC_ERROR (1 << 2)
10668 #define RXSOT_SYNC_ERROR (1 << 1)
10669 #define RXSOT_ERROR (1 << 0)
10671 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
10672 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
10673 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
10674 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
10675 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
10676 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
10677 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
10678 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
10679 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
10680 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
10681 #define VID_MODE_FORMAT_MASK (0xf << 7)
10682 #define VID_MODE_NOT_SUPPORTED (0 << 7)
10683 #define VID_MODE_FORMAT_RGB565 (1 << 7)
10684 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
10685 #define VID_MODE_FORMAT_RGB666 (3 << 7)
10686 #define VID_MODE_FORMAT_RGB888 (4 << 7)
10687 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
10688 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
10689 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
10690 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
10691 #define DATA_LANES_PRG_REG_SHIFT 0
10692 #define DATA_LANES_PRG_REG_MASK (7 << 0)
10694 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
10695 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
10696 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
10697 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
10699 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
10700 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
10701 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
10702 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
10704 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
10705 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
10706 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
10707 #define TURN_AROUND_TIMEOUT_MASK 0x3f
10709 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
10710 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
10711 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
10712 #define DEVICE_RESET_TIMER_MASK 0xffff
10714 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
10715 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
10716 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
10717 #define VERTICAL_ADDRESS_SHIFT 16
10718 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
10719 #define HORIZONTAL_ADDRESS_SHIFT 0
10720 #define HORIZONTAL_ADDRESS_MASK 0xffff
10722 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
10723 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
10724 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
10725 #define DBI_FIFO_EMPTY_HALF (0 << 0)
10726 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
10727 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
10729 /* regs below are bits 15:0 */
10730 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
10731 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
10732 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
10734 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
10735 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
10736 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
10738 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
10739 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
10740 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
10742 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
10743 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
10744 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
10746 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
10747 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
10748 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
10750 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
10751 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
10752 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
10754 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
10755 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
10756 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
10758 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
10759 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
10760 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
10762 /* regs above are bits 15:0 */
10764 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
10765 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
10766 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
10767 #define DPI_LP_MODE (1 << 6)
10768 #define BACKLIGHT_OFF (1 << 5)
10769 #define BACKLIGHT_ON (1 << 4)
10770 #define COLOR_MODE_OFF (1 << 3)
10771 #define COLOR_MODE_ON (1 << 2)
10772 #define TURN_ON (1 << 1)
10773 #define SHUTDOWN (1 << 0)
10775 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
10776 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
10777 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
10778 #define COMMAND_BYTE_SHIFT 0
10779 #define COMMAND_BYTE_MASK (0x3f << 0)
10781 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
10782 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
10783 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
10784 #define MASTER_INIT_TIMER_SHIFT 0
10785 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
10787 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
10788 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
10789 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
10790 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
10791 #define MAX_RETURN_PKT_SIZE_SHIFT 0
10792 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
10794 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
10795 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
10796 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
10797 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
10798 #define DISABLE_VIDEO_BTA (1 << 3)
10799 #define IP_TG_CONFIG (1 << 2)
10800 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
10801 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
10802 #define VIDEO_MODE_BURST (3 << 0)
10804 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
10805 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
10806 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
10807 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
10808 #define BXT_DPHY_DEFEATURE_EN (1 << 8)
10809 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
10810 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
10811 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
10812 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
10813 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
10814 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
10815 #define CLOCKSTOP (1 << 1)
10816 #define EOT_DISABLE (1 << 0)
10818 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
10819 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
10820 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
10821 #define LP_BYTECLK_SHIFT 0
10822 #define LP_BYTECLK_MASK (0xffff << 0)
10824 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
10825 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
10826 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
10828 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
10829 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
10830 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
10833 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
10834 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
10835 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
10838 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
10839 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
10840 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
10842 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
10843 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
10844 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
10845 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
10846 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
10847 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
10848 #define LONG_PACKET_WORD_COUNT_SHIFT 8
10849 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
10850 #define SHORT_PACKET_PARAM_SHIFT 8
10851 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
10852 #define VIRTUAL_CHANNEL_SHIFT 6
10853 #define VIRTUAL_CHANNEL_MASK (3 << 6)
10854 #define DATA_TYPE_SHIFT 0
10855 #define DATA_TYPE_MASK (0x3f << 0)
10856 /* data type values, see include/video/mipi_display.h */
10858 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
10859 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
10860 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
10861 #define DPI_FIFO_EMPTY (1 << 28)
10862 #define DBI_FIFO_EMPTY (1 << 27)
10863 #define LP_CTRL_FIFO_EMPTY (1 << 26)
10864 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
10865 #define LP_CTRL_FIFO_FULL (1 << 24)
10866 #define HS_CTRL_FIFO_EMPTY (1 << 18)
10867 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
10868 #define HS_CTRL_FIFO_FULL (1 << 16)
10869 #define LP_DATA_FIFO_EMPTY (1 << 10)
10870 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
10871 #define LP_DATA_FIFO_FULL (1 << 8)
10872 #define HS_DATA_FIFO_EMPTY (1 << 2)
10873 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
10874 #define HS_DATA_FIFO_FULL (1 << 0)
10876 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
10877 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
10878 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
10879 #define DBI_HS_LP_MODE_MASK (1 << 0)
10880 #define DBI_LP_MODE (1 << 0)
10881 #define DBI_HS_MODE (0 << 0)
10883 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
10884 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
10885 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
10886 #define EXIT_ZERO_COUNT_SHIFT 24
10887 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
10888 #define TRAIL_COUNT_SHIFT 16
10889 #define TRAIL_COUNT_MASK (0x1f << 16)
10890 #define CLK_ZERO_COUNT_SHIFT 8
10891 #define CLK_ZERO_COUNT_MASK (0xff << 8)
10892 #define PREPARE_COUNT_SHIFT 0
10893 #define PREPARE_COUNT_MASK (0x3f << 0)
10895 #define _ICL_DSI_T_INIT_MASTER_0 0x6b088
10896 #define _ICL_DSI_T_INIT_MASTER_1 0x6b888
10897 #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \
10898 _ICL_DSI_T_INIT_MASTER_0,\
10899 _ICL_DSI_T_INIT_MASTER_1)
10901 #define _DPHY_CLK_TIMING_PARAM_0 0x162180
10902 #define _DPHY_CLK_TIMING_PARAM_1 0x6c180
10903 #define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10904 _DPHY_CLK_TIMING_PARAM_0,\
10905 _DPHY_CLK_TIMING_PARAM_1)
10906 #define _DSI_CLK_TIMING_PARAM_0 0x6b080
10907 #define _DSI_CLK_TIMING_PARAM_1 0x6b880
10908 #define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10909 _DSI_CLK_TIMING_PARAM_0,\
10910 _DSI_CLK_TIMING_PARAM_1)
10911 #define CLK_PREPARE_OVERRIDE (1 << 31)
10912 #define CLK_PREPARE(x) ((x) << 28)
10913 #define CLK_PREPARE_MASK (0x7 << 28)
10914 #define CLK_PREPARE_SHIFT 28
10915 #define CLK_ZERO_OVERRIDE (1 << 27)
10916 #define CLK_ZERO(x) ((x) << 20)
10917 #define CLK_ZERO_MASK (0xf << 20)
10918 #define CLK_ZERO_SHIFT 20
10919 #define CLK_PRE_OVERRIDE (1 << 19)
10920 #define CLK_PRE(x) ((x) << 16)
10921 #define CLK_PRE_MASK (0x3 << 16)
10922 #define CLK_PRE_SHIFT 16
10923 #define CLK_POST_OVERRIDE (1 << 15)
10924 #define CLK_POST(x) ((x) << 8)
10925 #define CLK_POST_MASK (0x7 << 8)
10926 #define CLK_POST_SHIFT 8
10927 #define CLK_TRAIL_OVERRIDE (1 << 7)
10928 #define CLK_TRAIL(x) ((x) << 0)
10929 #define CLK_TRAIL_MASK (0xf << 0)
10930 #define CLK_TRAIL_SHIFT 0
10932 #define _DPHY_DATA_TIMING_PARAM_0 0x162184
10933 #define _DPHY_DATA_TIMING_PARAM_1 0x6c184
10934 #define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10935 _DPHY_DATA_TIMING_PARAM_0,\
10936 _DPHY_DATA_TIMING_PARAM_1)
10937 #define _DSI_DATA_TIMING_PARAM_0 0x6B084
10938 #define _DSI_DATA_TIMING_PARAM_1 0x6B884
10939 #define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10940 _DSI_DATA_TIMING_PARAM_0,\
10941 _DSI_DATA_TIMING_PARAM_1)
10942 #define HS_PREPARE_OVERRIDE (1 << 31)
10943 #define HS_PREPARE(x) ((x) << 24)
10944 #define HS_PREPARE_MASK (0x7 << 24)
10945 #define HS_PREPARE_SHIFT 24
10946 #define HS_ZERO_OVERRIDE (1 << 23)
10947 #define HS_ZERO(x) ((x) << 16)
10948 #define HS_ZERO_MASK (0xf << 16)
10949 #define HS_ZERO_SHIFT 16
10950 #define HS_TRAIL_OVERRIDE (1 << 15)
10951 #define HS_TRAIL(x) ((x) << 8)
10952 #define HS_TRAIL_MASK (0x7 << 8)
10953 #define HS_TRAIL_SHIFT 8
10954 #define HS_EXIT_OVERRIDE (1 << 7)
10955 #define HS_EXIT(x) ((x) << 0)
10956 #define HS_EXIT_MASK (0x7 << 0)
10957 #define HS_EXIT_SHIFT 0
10959 #define _DPHY_TA_TIMING_PARAM_0 0x162188
10960 #define _DPHY_TA_TIMING_PARAM_1 0x6c188
10961 #define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10962 _DPHY_TA_TIMING_PARAM_0,\
10963 _DPHY_TA_TIMING_PARAM_1)
10964 #define _DSI_TA_TIMING_PARAM_0 0x6b098
10965 #define _DSI_TA_TIMING_PARAM_1 0x6b898
10966 #define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10967 _DSI_TA_TIMING_PARAM_0,\
10968 _DSI_TA_TIMING_PARAM_1)
10969 #define TA_SURE_OVERRIDE (1 << 31)
10970 #define TA_SURE(x) ((x) << 16)
10971 #define TA_SURE_MASK (0x1f << 16)
10972 #define TA_SURE_SHIFT 16
10973 #define TA_GO_OVERRIDE (1 << 15)
10974 #define TA_GO(x) ((x) << 8)
10975 #define TA_GO_MASK (0xf << 8)
10976 #define TA_GO_SHIFT 8
10977 #define TA_GET_OVERRIDE (1 << 7)
10978 #define TA_GET(x) ((x) << 0)
10979 #define TA_GET_MASK (0xf << 0)
10980 #define TA_GET_SHIFT 0
10982 /* DSI transcoder configuration */
10983 #define _DSI_TRANS_FUNC_CONF_0 0x6b030
10984 #define _DSI_TRANS_FUNC_CONF_1 0x6b830
10985 #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
10986 _DSI_TRANS_FUNC_CONF_0,\
10987 _DSI_TRANS_FUNC_CONF_1)
10988 #define OP_MODE_MASK (0x3 << 28)
10989 #define OP_MODE_SHIFT 28
10990 #define CMD_MODE_NO_GATE (0x0 << 28)
10991 #define CMD_MODE_TE_GATE (0x1 << 28)
10992 #define VIDEO_MODE_SYNC_EVENT (0x2 << 28)
10993 #define VIDEO_MODE_SYNC_PULSE (0x3 << 28)
10994 #define LINK_READY (1 << 20)
10995 #define PIX_FMT_MASK (0x3 << 16)
10996 #define PIX_FMT_SHIFT 16
10997 #define PIX_FMT_RGB565 (0x0 << 16)
10998 #define PIX_FMT_RGB666_PACKED (0x1 << 16)
10999 #define PIX_FMT_RGB666_LOOSE (0x2 << 16)
11000 #define PIX_FMT_RGB888 (0x3 << 16)
11001 #define PIX_FMT_RGB101010 (0x4 << 16)
11002 #define PIX_FMT_RGB121212 (0x5 << 16)
11003 #define PIX_FMT_COMPRESSED (0x6 << 16)
11004 #define BGR_TRANSMISSION (1 << 15)
11005 #define PIX_VIRT_CHAN(x) ((x) << 12)
11006 #define PIX_VIRT_CHAN_MASK (0x3 << 12)
11007 #define PIX_VIRT_CHAN_SHIFT 12
11008 #define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
11009 #define PIX_BUF_THRESHOLD_SHIFT 10
11010 #define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)
11011 #define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)
11012 #define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)
11013 #define PIX_BUF_THRESHOLD_FULL (0x3 << 10)
11014 #define CONTINUOUS_CLK_MASK (0x3 << 8)
11015 #define CONTINUOUS_CLK_SHIFT 8
11016 #define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
11017 #define CLK_HS_OR_LP (0x2 << 8)
11018 #define CLK_HS_CONTINUOUS (0x3 << 8)
11019 #define LINK_CALIBRATION_MASK (0x3 << 4)
11020 #define LINK_CALIBRATION_SHIFT 4
11021 #define CALIBRATION_DISABLED (0x0 << 4)
11022 #define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
11023 #define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
11024 #define BLANKING_PACKET_ENABLE (1 << 2)
11025 #define S3D_ORIENTATION_LANDSCAPE (1 << 1)
11026 #define EOTP_DISABLED (1 << 0)
11028 #define _DSI_CMD_RXCTL_0 0x6b0d4
11029 #define _DSI_CMD_RXCTL_1 0x6b8d4
11030 #define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \
11033 #define READ_UNLOADS_DW (1 << 16)
11034 #define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)
11035 #define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)
11036 #define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)
11037 #define RECEIVED_RESET_TRIGGER (1 << 12)
11038 #define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)
11039 #define RECEIVED_CRC_WAS_LOST (1 << 10)
11040 #define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)
11041 #define NUMBER_RX_PLOAD_DW_SHIFT 0
11043 #define _DSI_CMD_TXCTL_0 0x6b0d0
11044 #define _DSI_CMD_TXCTL_1 0x6b8d0
11045 #define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \
11048 #define KEEP_LINK_IN_HS (1 << 24)
11049 #define FREE_HEADER_CREDIT_MASK (0x1f << 8)
11050 #define FREE_HEADER_CREDIT_SHIFT 0x8
11051 #define FREE_PLOAD_CREDIT_MASK (0xff << 0)
11052 #define FREE_PLOAD_CREDIT_SHIFT 0
11053 #define MAX_HEADER_CREDIT 0x10
11054 #define MAX_PLOAD_CREDIT 0x40
11056 #define _DSI_CMD_TXHDR_0 0x6b100
11057 #define _DSI_CMD_TXHDR_1 0x6b900
11058 #define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
11061 #define PAYLOAD_PRESENT (1 << 31)
11062 #define LP_DATA_TRANSFER (1 << 30)
11063 #define VBLANK_FENCE (1 << 29)
11064 #define PARAM_WC_MASK (0xffff << 8)
11065 #define PARAM_WC_LOWER_SHIFT 8
11066 #define PARAM_WC_UPPER_SHIFT 16
11067 #define VC_MASK (0x3 << 6)
11069 #define DT_MASK (0x3f << 0)
11072 #define _DSI_CMD_TXPYLD_0 0x6b104
11073 #define _DSI_CMD_TXPYLD_1 0x6b904
11074 #define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
11075 _DSI_CMD_TXPYLD_0,\
11078 #define _DSI_LP_MSG_0 0x6b0d8
11079 #define _DSI_LP_MSG_1 0x6b8d8
11080 #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
11083 #define LPTX_IN_PROGRESS (1 << 17)
11084 #define LINK_IN_ULPS (1 << 16)
11085 #define LINK_ULPS_TYPE_LP11 (1 << 8)
11086 #define LINK_ENTER_ULPS (1 << 0)
11088 /* DSI timeout registers */
11089 #define _DSI_HSTX_TO_0 0x6b044
11090 #define _DSI_HSTX_TO_1 0x6b844
11091 #define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
11094 #define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
11095 #define HSTX_TIMEOUT_VALUE_SHIFT 16
11096 #define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
11097 #define HSTX_TIMED_OUT (1 << 0)
11099 #define _DSI_LPRX_HOST_TO_0 0x6b048
11100 #define _DSI_LPRX_HOST_TO_1 0x6b848
11101 #define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
11102 _DSI_LPRX_HOST_TO_0,\
11103 _DSI_LPRX_HOST_TO_1)
11104 #define LPRX_TIMED_OUT (1 << 16)
11105 #define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
11106 #define LPRX_TIMEOUT_VALUE_SHIFT 0
11107 #define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
11109 #define _DSI_PWAIT_TO_0 0x6b040
11110 #define _DSI_PWAIT_TO_1 0x6b840
11111 #define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
11114 #define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
11115 #define PRESET_TIMEOUT_VALUE_SHIFT 16
11116 #define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
11117 #define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
11118 #define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
11119 #define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
11121 #define _DSI_TA_TO_0 0x6b04c
11122 #define _DSI_TA_TO_1 0x6b84c
11123 #define DSI_TA_TO(tc) _MMIO_DSI(tc, \
11126 #define TA_TIMED_OUT (1 << 16)
11127 #define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
11128 #define TA_TIMEOUT_VALUE_SHIFT 0
11129 #define TA_TIMEOUT_VALUE(x) ((x) << 0)
11132 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
11133 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
11134 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
11136 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
11137 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
11138 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
11139 #define LP_HS_SSW_CNT_SHIFT 16
11140 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
11141 #define HS_LP_PWR_SW_CNT_SHIFT 0
11142 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
11144 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
11145 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
11146 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
11147 #define STOP_STATE_STALL_COUNTER_SHIFT 0
11148 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
11150 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
11151 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
11152 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
11153 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
11154 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
11155 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
11156 #define RX_CONTENTION_DETECTED (1 << 0)
11158 /* XXX: only pipe A ?!? */
11159 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
11160 #define DBI_TYPEC_ENABLE (1 << 31)
11161 #define DBI_TYPEC_WIP (1 << 30)
11162 #define DBI_TYPEC_OPTION_SHIFT 28
11163 #define DBI_TYPEC_OPTION_MASK (3 << 28)
11164 #define DBI_TYPEC_FREQ_SHIFT 24
11165 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
11166 #define DBI_TYPEC_OVERRIDE (1 << 8)
11167 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
11168 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
11171 /* MIPI adapter registers */
11173 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
11174 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
11175 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
11176 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
11177 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
11178 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
11179 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
11180 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
11181 #define READ_REQUEST_PRIORITY_SHIFT 3
11182 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
11183 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
11184 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
11185 #define RGB_FLIP_TO_BGR (1 << 2)
11187 #define BXT_PIPE_SELECT_SHIFT 7
11188 #define BXT_PIPE_SELECT_MASK (7 << 7)
11189 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
11190 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
11191 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
11192 #define GLK_MIPIIO_RESET_RELEASED (1 << 28)
11193 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
11194 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
11195 #define GLK_LP_WAKE (1 << 22)
11196 #define GLK_LP11_LOW_PWR_MODE (1 << 21)
11197 #define GLK_LP00_LOW_PWR_MODE (1 << 20)
11198 #define GLK_FIREWALL_ENABLE (1 << 16)
11199 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
11200 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
11201 #define BXT_DSC_ENABLE (1 << 3)
11202 #define BXT_RGB_FLIP (1 << 2)
11203 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
11204 #define GLK_MIPIIO_ENABLE (1 << 0)
11206 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
11207 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
11208 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
11209 #define DATA_MEM_ADDRESS_SHIFT 5
11210 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
11211 #define DATA_VALID (1 << 0)
11213 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
11214 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
11215 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
11216 #define DATA_LENGTH_SHIFT 0
11217 #define DATA_LENGTH_MASK (0xfffff << 0)
11219 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
11220 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
11221 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
11222 #define COMMAND_MEM_ADDRESS_SHIFT 5
11223 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
11224 #define AUTO_PWG_ENABLE (1 << 2)
11225 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
11226 #define COMMAND_VALID (1 << 0)
11228 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
11229 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
11230 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
11231 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
11232 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
11234 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
11235 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
11236 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
11238 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
11239 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
11240 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
11241 #define READ_DATA_VALID(n) (1 << (n))
11243 /* MOCS (Memory Object Control State) registers */
11244 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
11246 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
11247 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
11248 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
11249 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
11250 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
11251 /* Media decoder 2 MOCS registers */
11252 #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
11254 #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
11255 #define PMFLUSHDONE_LNICRSDROP (1 << 20)
11256 #define PMFLUSH_GAPL3UNBLOCK (1 << 21)
11257 #define PMFLUSHDONE_LNEBLK (1 << 22)
11259 #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
11262 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
11263 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
11264 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
11265 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
11266 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
11268 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
11269 #define MMCD_PCLA (1 << 31)
11270 #define MMCD_HOTSPOT_EN (1 << 27)
11272 #define _ICL_PHY_MISC_A 0x64C00
11273 #define _ICL_PHY_MISC_B 0x64C04
11274 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
11276 #define ICL_PHY_MISC_MUX_DDID (1 << 28)
11277 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
11279 /* Icelake Display Stream Compression Registers */
11280 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
11281 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
11282 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
11283 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
11284 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
11285 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
11286 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11287 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
11288 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
11289 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11290 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
11291 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
11292 #define DSC_VBR_ENABLE (1 << 19)
11293 #define DSC_422_ENABLE (1 << 18)
11294 #define DSC_COLOR_SPACE_CONVERSION (1 << 17)
11295 #define DSC_BLOCK_PREDICTION (1 << 16)
11296 #define DSC_LINE_BUF_DEPTH_SHIFT 12
11297 #define DSC_BPC_SHIFT 8
11298 #define DSC_VER_MIN_SHIFT 4
11299 #define DSC_VER_MAJ (0x1 << 0)
11301 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
11302 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
11303 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
11304 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
11305 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
11306 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
11307 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11308 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
11309 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
11310 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11311 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
11312 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
11313 #define DSC_BPP(bpp) ((bpp) << 0)
11315 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
11316 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
11317 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
11318 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
11319 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
11320 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
11321 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11322 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
11323 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
11324 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11325 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
11326 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
11327 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
11328 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
11330 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
11331 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
11332 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
11333 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
11334 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
11335 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
11336 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11337 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
11338 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
11339 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11340 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
11341 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
11342 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
11343 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
11345 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
11346 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
11347 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
11348 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
11349 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
11350 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
11351 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11352 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
11353 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
11354 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11355 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
11356 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
11357 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
11358 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
11360 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
11361 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
11362 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
11363 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
11364 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
11365 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
11366 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11367 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
11368 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
11369 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11370 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
11371 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
11372 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
11373 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
11375 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
11376 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
11377 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
11378 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
11379 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
11380 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
11381 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11382 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
11383 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
11384 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11385 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
11386 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
11387 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
11388 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
11389 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
11390 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
11392 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
11393 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
11394 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
11395 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
11396 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
11397 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
11398 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11399 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
11400 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
11401 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11402 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
11403 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
11404 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
11405 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
11407 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
11408 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
11409 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
11410 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
11411 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
11412 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
11413 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11414 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
11415 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
11416 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11417 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
11418 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
11419 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
11420 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
11422 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
11423 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
11424 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
11425 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
11426 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
11427 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
11428 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11429 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
11430 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
11431 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11432 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
11433 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
11434 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
11435 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
11437 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
11438 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
11439 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
11440 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
11441 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
11442 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
11443 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11444 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
11445 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
11446 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11447 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
11448 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
11449 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
11450 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
11451 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
11452 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
11454 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
11455 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
11456 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
11457 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
11458 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
11459 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
11460 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11461 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
11462 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
11463 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11464 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
11465 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
11467 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
11468 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
11469 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
11470 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
11471 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
11472 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
11473 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11474 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
11475 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
11476 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11477 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
11478 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
11480 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
11481 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
11482 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
11483 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
11484 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
11485 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
11486 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11487 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
11488 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
11489 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11490 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
11491 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
11493 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
11494 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
11495 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
11496 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
11497 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
11498 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
11499 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11500 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
11501 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
11502 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11503 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
11504 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
11506 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
11507 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
11508 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
11509 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
11510 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
11511 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
11512 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11513 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
11514 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
11515 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11516 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
11517 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
11519 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
11520 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
11521 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
11522 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
11523 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
11524 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
11525 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11526 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
11527 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
11528 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11529 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
11530 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
11531 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
11532 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
11533 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
11535 /* Icelake Rate Control Buffer Threshold Registers */
11536 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
11537 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
11538 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
11539 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
11540 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
11541 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
11542 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
11543 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
11544 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
11545 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
11546 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
11547 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
11548 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11549 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
11550 _ICL_DSC0_RC_BUF_THRESH_0_PC)
11551 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11552 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
11553 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
11554 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11555 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
11556 _ICL_DSC1_RC_BUF_THRESH_0_PC)
11557 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11558 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
11559 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
11561 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
11562 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
11563 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
11564 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
11565 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
11566 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
11567 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
11568 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
11569 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
11570 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
11571 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
11572 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
11573 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11574 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
11575 _ICL_DSC0_RC_BUF_THRESH_1_PC)
11576 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11577 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
11578 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
11579 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11580 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
11581 _ICL_DSC1_RC_BUF_THRESH_1_PC)
11582 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11583 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
11584 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
11586 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
11587 #define MODULAR_FIA_MASK (1 << 4)
11588 #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
11589 #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
11590 #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
11591 #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
11592 #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
11594 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
11595 #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
11597 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
11598 #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
11600 #endif /* _I915_REG_H_ */