2 * Copyright © 2008-2015 Intel Corporation
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25 #include <linux/dma-fence-array.h>
26 #include <linux/irq_work.h>
27 #include <linux/prefetch.h>
28 #include <linux/sched.h>
29 #include <linux/sched/clock.h>
30 #include <linux/sched/signal.h>
32 #include "i915_active.h"
34 #include "i915_globals.h"
35 #include "i915_reset.h"
39 struct list_head link;
41 struct i915_sw_fence *fence;
44 static struct i915_global_request {
45 struct i915_global base;
46 struct kmem_cache *slab_requests;
47 struct kmem_cache *slab_dependencies;
48 struct kmem_cache *slab_execute_cbs;
51 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
56 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
59 * The timeline struct (as part of the ppgtt underneath a context)
60 * may be freed when the request is no longer in use by the GPU.
61 * We could extend the life of a context to beyond that of all
62 * fences, possibly keeping the hw resource around indefinitely,
63 * or we just give them a false name. Since
64 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
65 * lie seems justifiable.
67 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
70 return to_request(fence)->gem_context->name ?: "[i915]";
73 static bool i915_fence_signaled(struct dma_fence *fence)
75 return i915_request_completed(to_request(fence));
78 static bool i915_fence_enable_signaling(struct dma_fence *fence)
80 return i915_request_enable_breadcrumb(to_request(fence));
83 static signed long i915_fence_wait(struct dma_fence *fence,
87 return i915_request_wait(to_request(fence),
88 interruptible | I915_WAIT_PRIORITY,
92 static void i915_fence_release(struct dma_fence *fence)
94 struct i915_request *rq = to_request(fence);
97 * The request is put onto a RCU freelist (i.e. the address
98 * is immediately reused), mark the fences as being freed now.
99 * Otherwise the debugobjects for the fences are only marked as
100 * freed when the slab cache itself is freed, and so we would get
101 * caught trying to reuse dead objects.
103 i915_sw_fence_fini(&rq->submit);
104 i915_sw_fence_fini(&rq->semaphore);
106 kmem_cache_free(global.slab_requests, rq);
109 const struct dma_fence_ops i915_fence_ops = {
110 .get_driver_name = i915_fence_get_driver_name,
111 .get_timeline_name = i915_fence_get_timeline_name,
112 .enable_signaling = i915_fence_enable_signaling,
113 .signaled = i915_fence_signaled,
114 .wait = i915_fence_wait,
115 .release = i915_fence_release,
119 i915_request_remove_from_client(struct i915_request *request)
121 struct drm_i915_file_private *file_priv;
123 file_priv = request->file_priv;
127 spin_lock(&file_priv->mm.lock);
128 if (request->file_priv) {
129 list_del(&request->client_link);
130 request->file_priv = NULL;
132 spin_unlock(&file_priv->mm.lock);
135 static void reserve_gt(struct drm_i915_private *i915)
137 if (!i915->gt.active_requests++)
138 i915_gem_unpark(i915);
141 static void unreserve_gt(struct drm_i915_private *i915)
143 GEM_BUG_ON(!i915->gt.active_requests);
144 if (!--i915->gt.active_requests)
148 static void advance_ring(struct i915_request *request)
150 struct intel_ring *ring = request->ring;
154 * We know the GPU must have read the request to have
155 * sent us the seqno + interrupt, so use the position
156 * of tail of the request to update the last known position
159 * Note this requires that we are always called in request
162 GEM_BUG_ON(!list_is_first(&request->ring_link, &ring->request_list));
163 if (list_is_last(&request->ring_link, &ring->request_list)) {
165 * We may race here with execlists resubmitting this request
166 * as we retire it. The resubmission will move the ring->tail
167 * forwards (to request->wa_tail). We either read the
168 * current value that was written to hw, or the value that
169 * is just about to be. Either works, if we miss the last two
170 * noops - they are safe to be replayed on a reset.
172 tail = READ_ONCE(request->tail);
173 list_del(&ring->active_link);
175 tail = request->postfix;
177 list_del_init(&request->ring_link);
182 static void free_capture_list(struct i915_request *request)
184 struct i915_capture_list *capture;
186 capture = request->capture_list;
188 struct i915_capture_list *next = capture->next;
195 static void __retire_engine_request(struct intel_engine_cs *engine,
196 struct i915_request *rq)
198 GEM_TRACE("%s(%s) fence %llx:%lld, current %d\n",
199 __func__, engine->name,
200 rq->fence.context, rq->fence.seqno,
203 GEM_BUG_ON(!i915_request_completed(rq));
207 spin_lock(&engine->timeline.lock);
208 GEM_BUG_ON(!list_is_first(&rq->link, &engine->timeline.requests));
209 list_del_init(&rq->link);
210 spin_unlock(&engine->timeline.lock);
212 spin_lock(&rq->lock);
213 i915_request_mark_complete(rq);
214 if (!i915_request_signaled(rq))
215 dma_fence_signal_locked(&rq->fence);
216 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
217 i915_request_cancel_breadcrumb(rq);
219 GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters));
220 atomic_dec(&rq->i915->gt_pm.rps.num_waiters);
222 spin_unlock(&rq->lock);
227 * The backing object for the context is done after switching to the
228 * *next* context. Therefore we cannot retire the previous context until
229 * the next context has already started running. However, since we
230 * cannot take the required locks at i915_request_submit() we
231 * defer the unpinning of the active context to now, retirement of
232 * the subsequent request.
234 if (engine->last_retired_context)
235 intel_context_unpin(engine->last_retired_context);
236 engine->last_retired_context = rq->hw_context;
239 static void __retire_engine_upto(struct intel_engine_cs *engine,
240 struct i915_request *rq)
242 struct i915_request *tmp;
244 if (list_empty(&rq->link))
248 tmp = list_first_entry(&engine->timeline.requests,
251 GEM_BUG_ON(tmp->engine != engine);
252 __retire_engine_request(engine, tmp);
256 static void i915_request_retire(struct i915_request *request)
258 struct i915_active_request *active, *next;
260 GEM_TRACE("%s fence %llx:%lld, current %d\n",
261 request->engine->name,
262 request->fence.context, request->fence.seqno,
263 hwsp_seqno(request));
265 lockdep_assert_held(&request->i915->drm.struct_mutex);
266 GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
267 GEM_BUG_ON(!i915_request_completed(request));
269 trace_i915_request_retire(request);
271 advance_ring(request);
272 free_capture_list(request);
275 * Walk through the active list, calling retire on each. This allows
276 * objects to track their GPU activity and mark themselves as idle
277 * when their *last* active request is completed (updating state
278 * tracking lists for eviction, active references for GEM, etc).
280 * As the ->retire() may free the node, we decouple it first and
281 * pass along the auxiliary information (to avoid dereferencing
282 * the node after the callback).
284 list_for_each_entry_safe(active, next, &request->active_list, link) {
286 * In microbenchmarks or focusing upon time inside the kernel,
287 * we may spend an inordinate amount of time simply handling
288 * the retirement of requests and processing their callbacks.
289 * Of which, this loop itself is particularly hot due to the
290 * cache misses when jumping around the list of
291 * i915_active_request. So we try to keep this loop as
292 * streamlined as possible and also prefetch the next
293 * i915_active_request to try and hide the likely cache miss.
297 INIT_LIST_HEAD(&active->link);
298 RCU_INIT_POINTER(active->request, NULL);
300 active->retire(active, request);
303 i915_request_remove_from_client(request);
305 intel_context_unpin(request->hw_context);
307 __retire_engine_upto(request->engine, request);
309 unreserve_gt(request->i915);
311 i915_sched_node_fini(&request->sched);
312 i915_request_put(request);
315 void i915_request_retire_upto(struct i915_request *rq)
317 struct intel_ring *ring = rq->ring;
318 struct i915_request *tmp;
320 GEM_TRACE("%s fence %llx:%lld, current %d\n",
322 rq->fence.context, rq->fence.seqno,
325 lockdep_assert_held(&rq->i915->drm.struct_mutex);
326 GEM_BUG_ON(!i915_request_completed(rq));
328 if (list_empty(&rq->ring_link))
332 tmp = list_first_entry(&ring->request_list,
333 typeof(*tmp), ring_link);
335 i915_request_retire(tmp);
339 static void irq_execute_cb(struct irq_work *wrk)
341 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
343 i915_sw_fence_complete(cb->fence);
344 kmem_cache_free(global.slab_execute_cbs, cb);
347 static void __notify_execute_cb(struct i915_request *rq)
349 struct execute_cb *cb;
351 lockdep_assert_held(&rq->lock);
353 if (list_empty(&rq->execute_cb))
356 list_for_each_entry(cb, &rq->execute_cb, link)
357 irq_work_queue(&cb->work);
360 * XXX Rollback on __i915_request_unsubmit()
362 * In the future, perhaps when we have an active time-slicing scheduler,
363 * it will be interesting to unsubmit parallel execution and remove
364 * busywaits from the GPU until their master is restarted. This is
365 * quite hairy, we have to carefully rollback the fence and do a
366 * preempt-to-idle cycle on the target engine, all the while the
367 * master execute_cb may refire.
369 INIT_LIST_HEAD(&rq->execute_cb);
373 i915_request_await_execution(struct i915_request *rq,
374 struct i915_request *signal,
377 struct execute_cb *cb;
379 if (i915_request_is_active(signal))
382 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
386 cb->fence = &rq->submit;
387 i915_sw_fence_await(cb->fence);
388 init_irq_work(&cb->work, irq_execute_cb);
390 spin_lock_irq(&signal->lock);
391 if (i915_request_is_active(signal)) {
392 i915_sw_fence_complete(cb->fence);
393 kmem_cache_free(global.slab_execute_cbs, cb);
395 list_add_tail(&cb->link, &signal->execute_cb);
397 spin_unlock_irq(&signal->lock);
402 static void move_to_timeline(struct i915_request *request,
403 struct i915_timeline *timeline)
405 GEM_BUG_ON(request->timeline == &request->engine->timeline);
406 lockdep_assert_held(&request->engine->timeline.lock);
408 spin_lock(&request->timeline->lock);
409 list_move_tail(&request->link, &timeline->requests);
410 spin_unlock(&request->timeline->lock);
413 void __i915_request_submit(struct i915_request *request)
415 struct intel_engine_cs *engine = request->engine;
417 GEM_TRACE("%s fence %llx:%lld -> current %d\n",
419 request->fence.context, request->fence.seqno,
420 hwsp_seqno(request));
422 GEM_BUG_ON(!irqs_disabled());
423 lockdep_assert_held(&engine->timeline.lock);
425 if (i915_gem_context_is_banned(request->gem_context))
426 i915_request_skip(request, -EIO);
429 * Are we using semaphores when the gpu is already saturated?
431 * Using semaphores incurs a cost in having the GPU poll a
432 * memory location, busywaiting for it to change. The continual
433 * memory reads can have a noticeable impact on the rest of the
434 * system with the extra bus traffic, stalling the cpu as it too
435 * tries to access memory across the bus (perf stat -e bus-cycles).
437 * If we installed a semaphore on this request and we only submit
438 * the request after the signaler completed, that indicates the
439 * system is overloaded and using semaphores at this time only
440 * increases the amount of work we are doing. If so, we disable
441 * further use of semaphores until we are idle again, whence we
442 * optimistically try again.
444 if (request->sched.semaphores &&
445 i915_sw_fence_signaled(&request->semaphore))
446 request->hw_context->saturated |= request->sched.semaphores;
448 /* We may be recursing from the signal callback of another i915 fence */
449 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
451 GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
452 set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
454 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
455 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) &&
456 !i915_request_enable_breadcrumb(request))
457 intel_engine_queue_breadcrumbs(engine);
459 __notify_execute_cb(request);
461 spin_unlock(&request->lock);
463 engine->emit_fini_breadcrumb(request,
464 request->ring->vaddr + request->postfix);
466 /* Transfer from per-context onto the global per-engine timeline */
467 move_to_timeline(request, &engine->timeline);
469 trace_i915_request_execute(request);
472 void i915_request_submit(struct i915_request *request)
474 struct intel_engine_cs *engine = request->engine;
477 /* Will be called from irq-context when using foreign fences. */
478 spin_lock_irqsave(&engine->timeline.lock, flags);
480 __i915_request_submit(request);
482 spin_unlock_irqrestore(&engine->timeline.lock, flags);
485 void __i915_request_unsubmit(struct i915_request *request)
487 struct intel_engine_cs *engine = request->engine;
489 GEM_TRACE("%s fence %llx:%lld, current %d\n",
491 request->fence.context, request->fence.seqno,
492 hwsp_seqno(request));
494 GEM_BUG_ON(!irqs_disabled());
495 lockdep_assert_held(&engine->timeline.lock);
498 * Only unwind in reverse order, required so that the per-context list
499 * is kept in seqno/ring order.
502 /* We may be recursing from the signal callback of another i915 fence */
503 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
505 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
506 i915_request_cancel_breadcrumb(request);
508 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
509 clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
511 spin_unlock(&request->lock);
513 /* Transfer back from the global per-engine timeline to per-context */
514 move_to_timeline(request, request->timeline);
517 * We don't need to wake_up any waiters on request->execute, they
518 * will get woken by any other event or us re-adding this request
519 * to the engine timeline (__i915_request_submit()). The waiters
520 * should be quite adapt at finding that the request now has a new
521 * global_seqno to the one they went to sleep on.
525 void i915_request_unsubmit(struct i915_request *request)
527 struct intel_engine_cs *engine = request->engine;
530 /* Will be called from irq-context when using foreign fences. */
531 spin_lock_irqsave(&engine->timeline.lock, flags);
533 __i915_request_unsubmit(request);
535 spin_unlock_irqrestore(&engine->timeline.lock, flags);
538 static int __i915_sw_fence_call
539 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
541 struct i915_request *request =
542 container_of(fence, typeof(*request), submit);
546 trace_i915_request_submit(request);
548 * We need to serialize use of the submit_request() callback
549 * with its hotplugging performed during an emergency
550 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
551 * critical section in order to force i915_gem_set_wedged() to
552 * wait until the submit_request() is completed before
556 request->engine->submit_request(request);
561 i915_request_put(request);
568 static int __i915_sw_fence_call
569 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
571 struct i915_request *request =
572 container_of(fence, typeof(*request), semaphore);
577 * We only check a small portion of our dependencies
578 * and so cannot guarantee that there remains no
579 * semaphore chain across all. Instead of opting
580 * for the full NOSEMAPHORE boost, we go for the
581 * smaller (but still preempting) boost of
582 * NEWCLIENT. This will be enough to boost over
583 * a busywaiting request (as that cannot be
584 * NEWCLIENT) without accidentally boosting
585 * a busywait over real work elsewhere.
587 i915_schedule_bump_priority(request, I915_PRIORITY_NEWCLIENT);
591 i915_request_put(request);
598 static void ring_retire_requests(struct intel_ring *ring)
600 struct i915_request *rq, *rn;
602 list_for_each_entry_safe(rq, rn, &ring->request_list, ring_link) {
603 if (!i915_request_completed(rq))
606 i915_request_retire(rq);
610 static noinline struct i915_request *
611 i915_request_alloc_slow(struct intel_context *ce)
613 struct intel_ring *ring = ce->ring;
614 struct i915_request *rq;
616 if (list_empty(&ring->request_list))
619 /* Ratelimit ourselves to prevent oom from malicious clients */
620 rq = list_last_entry(&ring->request_list, typeof(*rq), ring_link);
621 cond_synchronize_rcu(rq->rcustate);
623 /* Retire our old requests in the hope that we free some */
624 ring_retire_requests(ring);
627 return kmem_cache_alloc(global.slab_requests, GFP_KERNEL);
631 * i915_request_alloc - allocate a request structure
633 * @engine: engine that we wish to issue the request on.
634 * @ctx: context that the request will be associated with.
636 * Returns a pointer to the allocated request if successful,
637 * or an error code if not.
639 struct i915_request *
640 i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
642 struct drm_i915_private *i915 = engine->i915;
643 struct intel_context *ce;
644 struct i915_timeline *tl;
645 struct i915_request *rq;
649 lockdep_assert_held(&i915->drm.struct_mutex);
652 * Preempt contexts are reserved for exclusive use to inject a
653 * preemption context switch. They are never to be used for any trivial
656 GEM_BUG_ON(ctx == i915->preempt_context);
659 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
660 * EIO if the GPU is already wedged.
662 ret = i915_terminally_wedged(i915);
667 * Pinning the contexts may generate requests in order to acquire
668 * GGTT space, so do this first before we reserve a seqno for
671 ce = intel_context_pin(ctx, engine);
676 mutex_lock(&ce->ring->timeline->mutex);
678 /* Move our oldest request to the slab-cache (if not in use!) */
679 rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link);
680 if (!list_is_last(&rq->ring_link, &ce->ring->request_list) &&
681 i915_request_completed(rq))
682 i915_request_retire(rq);
685 * Beware: Dragons be flying overhead.
687 * We use RCU to look up requests in flight. The lookups may
688 * race with the request being allocated from the slab freelist.
689 * That is the request we are writing to here, may be in the process
690 * of being read by __i915_active_request_get_rcu(). As such,
691 * we have to be very careful when overwriting the contents. During
692 * the RCU lookup, we change chase the request->engine pointer,
693 * read the request->global_seqno and increment the reference count.
695 * The reference count is incremented atomically. If it is zero,
696 * the lookup knows the request is unallocated and complete. Otherwise,
697 * it is either still in use, or has been reallocated and reset
698 * with dma_fence_init(). This increment is safe for release as we
699 * check that the request we have a reference to and matches the active
702 * Before we increment the refcount, we chase the request->engine
703 * pointer. We must not call kmem_cache_zalloc() or else we set
704 * that pointer to NULL and cause a crash during the lookup. If
705 * we see the request is completed (based on the value of the
706 * old engine and seqno), the lookup is complete and reports NULL.
707 * If we decide the request is not completed (new engine or seqno),
708 * then we grab a reference and double check that it is still the
709 * active request - which it won't be and restart the lookup.
711 * Do not use kmem_cache_zalloc() here!
713 rq = kmem_cache_alloc(global.slab_requests,
714 GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
716 rq = i915_request_alloc_slow(ce);
723 INIT_LIST_HEAD(&rq->active_list);
724 INIT_LIST_HEAD(&rq->execute_cb);
726 tl = ce->ring->timeline;
727 ret = i915_timeline_get_seqno(tl, rq, &seqno);
733 rq->gem_context = ctx;
737 GEM_BUG_ON(rq->timeline == &engine->timeline);
738 rq->hwsp_seqno = tl->hwsp_seqno;
739 rq->hwsp_cacheline = tl->hwsp_cacheline;
740 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
742 spin_lock_init(&rq->lock);
743 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
744 tl->fence_context, seqno);
746 /* We bump the ref for the fence chain */
747 i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify);
748 i915_sw_fence_init(&i915_request_get(rq)->semaphore, semaphore_notify);
750 i915_sched_node_init(&rq->sched);
752 /* No zalloc, must clear what we need by hand */
753 rq->file_priv = NULL;
755 rq->capture_list = NULL;
756 rq->waitboost = false;
759 * Reserve space in the ring buffer for all the commands required to
760 * eventually emit this request. This is to guarantee that the
761 * i915_request_add() call can't fail. Note that the reserve may need
762 * to be redone if the request is not actually submitted straight
763 * away, e.g. because a GPU scheduler has deferred it.
765 * Note that due to how we add reserved_space to intel_ring_begin()
766 * we need to double our request to ensure that if we need to wrap
767 * around inside i915_request_add() there is sufficient space at
768 * the beginning of the ring as well.
770 rq->reserved_space = 2 * engine->emit_fini_breadcrumb_dw * sizeof(u32);
773 * Record the position of the start of the request so that
774 * should we detect the updated seqno part-way through the
775 * GPU processing the request, we never over-estimate the
776 * position of the head.
778 rq->head = rq->ring->emit;
780 ret = engine->request_alloc(rq);
784 /* Keep a second pin for the dual retirement along engine and ring */
785 __intel_context_pin(ce);
787 rq->infix = rq->ring->emit; /* end of header; start of user payload */
789 /* Check that we didn't interrupt ourselves with a new request */
790 lockdep_assert_held(&rq->timeline->mutex);
791 GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno);
792 rq->cookie = lockdep_pin_lock(&rq->timeline->mutex);
797 ce->ring->emit = rq->head;
799 /* Make sure we didn't add ourselves to external state before freeing */
800 GEM_BUG_ON(!list_empty(&rq->active_list));
801 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
802 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
805 kmem_cache_free(global.slab_requests, rq);
807 mutex_unlock(&ce->ring->timeline->mutex);
809 intel_context_unpin(ce);
814 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
816 if (list_is_first(&signal->ring_link, &signal->ring->request_list))
819 signal = list_prev_entry(signal, ring_link);
820 if (i915_timeline_sync_is_later(rq->timeline, &signal->fence))
823 return i915_sw_fence_await_dma_fence(&rq->submit,
828 static intel_engine_mask_t
829 already_busywaiting(struct i915_request *rq)
832 * Polling a semaphore causes bus traffic, delaying other users of
833 * both the GPU and CPU. We want to limit the impact on others,
834 * while taking advantage of early submission to reduce GPU
835 * latency. Therefore we restrict ourselves to not using more
836 * than one semaphore from each source, and not using a semaphore
837 * if we have detected the engine is saturated (i.e. would not be
838 * submitted early and cause bus traffic reading an already passed
841 * See the are-we-too-late? check in __i915_request_submit().
843 return rq->sched.semaphores | rq->hw_context->saturated;
847 emit_semaphore_wait(struct i915_request *to,
848 struct i915_request *from,
855 GEM_BUG_ON(!from->timeline->has_initial_breadcrumb);
856 GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
858 /* Just emit the first semaphore we see as request space is limited. */
859 if (already_busywaiting(to) & from->engine->mask)
860 return i915_sw_fence_await_dma_fence(&to->submit,
864 err = i915_request_await_start(to, from);
868 err = i915_sw_fence_await_dma_fence(&to->semaphore,
874 /* We need to pin the signaler's HWSP until we are finished reading. */
875 err = i915_timeline_read_hwsp(from, to, &hwsp_offset);
879 /* Only submit our spinner after the signaler is running! */
880 err = i915_request_await_execution(to, from, gfp);
884 cs = intel_ring_begin(to, 4);
889 * Using greater-than-or-equal here means we have to worry
890 * about seqno wraparound. To side step that issue, we swap
891 * the timeline HWSP upon wrapping, so that everyone listening
892 * for the old (pre-wrap) values do not see the much smaller
893 * (post-wrap) values than they were expecting (and so wait
896 *cs++ = MI_SEMAPHORE_WAIT |
897 MI_SEMAPHORE_GLOBAL_GTT |
899 MI_SEMAPHORE_SAD_GTE_SDD;
900 *cs++ = from->fence.seqno;
904 intel_ring_advance(to, cs);
905 to->sched.semaphores |= from->engine->mask;
906 to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
911 i915_request_await_request(struct i915_request *to, struct i915_request *from)
915 GEM_BUG_ON(to == from);
916 GEM_BUG_ON(to->timeline == from->timeline);
918 if (i915_request_completed(from))
921 if (to->engine->schedule) {
922 ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
927 if (to->engine == from->engine) {
928 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
931 } else if (intel_engine_has_semaphores(to->engine) &&
932 to->gem_context->sched.priority >= I915_PRIORITY_NORMAL) {
933 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
935 ret = i915_sw_fence_await_dma_fence(&to->submit,
940 return ret < 0 ? ret : 0;
944 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
946 struct dma_fence **child = &fence;
947 unsigned int nchild = 1;
951 * Note that if the fence-array was created in signal-on-any mode,
952 * we should *not* decompose it into its individual fences. However,
953 * we don't currently store which mode the fence-array is operating
954 * in. Fortunately, the only user of signal-on-any is private to
955 * amdgpu and we should not see any incoming fence-array from
956 * sync-file being in signal-on-any mode.
958 if (dma_fence_is_array(fence)) {
959 struct dma_fence_array *array = to_dma_fence_array(fence);
961 child = array->fences;
962 nchild = array->num_fences;
968 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
972 * Requests on the same timeline are explicitly ordered, along
973 * with their dependencies, by i915_request_add() which ensures
974 * that requests are submitted in-order through each ring.
976 if (fence->context == rq->fence.context)
979 /* Squash repeated waits to the same timelines */
980 if (fence->context != rq->i915->mm.unordered_timeline &&
981 i915_timeline_sync_is_later(rq->timeline, fence))
984 if (dma_fence_is_i915(fence))
985 ret = i915_request_await_request(rq, to_request(fence));
987 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
993 /* Record the latest fence used against each timeline */
994 if (fence->context != rq->i915->mm.unordered_timeline)
995 i915_timeline_sync_set(rq->timeline, fence);
1002 * i915_request_await_object - set this request to (async) wait upon a bo
1003 * @to: request we are wishing to use
1004 * @obj: object which may be in use on another ring.
1005 * @write: whether the wait is on behalf of a writer
1007 * This code is meant to abstract object synchronization with the GPU.
1008 * Conceptually we serialise writes between engines inside the GPU.
1009 * We only allow one engine to write into a buffer at any time, but
1010 * multiple readers. To ensure each has a coherent view of memory, we must:
1012 * - If there is an outstanding write request to the object, the new
1013 * request must wait for it to complete (either CPU or in hw, requests
1014 * on the same ring will be naturally ordered).
1016 * - If we are a write request (pending_write_domain is set), the new
1017 * request must wait for outstanding read requests to complete.
1019 * Returns 0 if successful, else propagates up the lower layer error.
1022 i915_request_await_object(struct i915_request *to,
1023 struct drm_i915_gem_object *obj,
1026 struct dma_fence *excl;
1030 struct dma_fence **shared;
1031 unsigned int count, i;
1033 ret = reservation_object_get_fences_rcu(obj->resv,
1034 &excl, &count, &shared);
1038 for (i = 0; i < count; i++) {
1039 ret = i915_request_await_dma_fence(to, shared[i]);
1043 dma_fence_put(shared[i]);
1046 for (; i < count; i++)
1047 dma_fence_put(shared[i]);
1050 excl = reservation_object_get_excl_rcu(obj->resv);
1055 ret = i915_request_await_dma_fence(to, excl);
1057 dma_fence_put(excl);
1063 void i915_request_skip(struct i915_request *rq, int error)
1065 void *vaddr = rq->ring->vaddr;
1068 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
1069 dma_fence_set_error(&rq->fence, error);
1072 * As this request likely depends on state from the lost
1073 * context, clear out all the user operations leaving the
1074 * breadcrumb at the end (so we get the fence notifications).
1077 if (rq->postfix < head) {
1078 memset(vaddr + head, 0, rq->ring->size - head);
1081 memset(vaddr + head, 0, rq->postfix - head);
1084 static struct i915_request *
1085 __i915_request_add_to_timeline(struct i915_request *rq)
1087 struct i915_timeline *timeline = rq->timeline;
1088 struct i915_request *prev;
1091 * Dependency tracking and request ordering along the timeline
1092 * is special cased so that we can eliminate redundant ordering
1093 * operations while building the request (we know that the timeline
1094 * itself is ordered, and here we guarantee it).
1096 * As we know we will need to emit tracking along the timeline,
1097 * we embed the hooks into our request struct -- at the cost of
1098 * having to have specialised no-allocation interfaces (which will
1099 * be beneficial elsewhere).
1101 * A second benefit to open-coding i915_request_await_request is
1102 * that we can apply a slight variant of the rules specialised
1103 * for timelines that jump between engines (such as virtual engines).
1104 * If we consider the case of virtual engine, we must emit a dma-fence
1105 * to prevent scheduling of the second request until the first is
1106 * complete (to maximise our greedy late load balancing) and this
1107 * precludes optimising to use semaphores serialisation of a single
1108 * timeline across engines.
1110 prev = i915_active_request_raw(&timeline->last_request,
1111 &rq->i915->drm.struct_mutex);
1112 if (prev && !i915_request_completed(prev)) {
1113 if (is_power_of_2(prev->engine->mask | rq->engine->mask))
1114 i915_sw_fence_await_sw_fence(&rq->submit,
1118 __i915_sw_fence_await_dma_fence(&rq->submit,
1121 if (rq->engine->schedule)
1122 __i915_sched_node_add_dependency(&rq->sched,
1128 spin_lock_irq(&timeline->lock);
1129 list_add_tail(&rq->link, &timeline->requests);
1130 spin_unlock_irq(&timeline->lock);
1132 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1133 __i915_active_request_set(&timeline->last_request, rq);
1139 * NB: This function is not allowed to fail. Doing so would mean the the
1140 * request is not being tracked for completion but the work itself is
1141 * going to happen on the hardware. This would be a Bad Thing(tm).
1143 void i915_request_add(struct i915_request *request)
1145 struct intel_engine_cs *engine = request->engine;
1146 struct i915_timeline *timeline = request->timeline;
1147 struct intel_ring *ring = request->ring;
1148 struct i915_request *prev;
1151 GEM_TRACE("%s fence %llx:%lld\n",
1152 engine->name, request->fence.context, request->fence.seqno);
1154 lockdep_assert_held(&request->timeline->mutex);
1155 lockdep_unpin_lock(&request->timeline->mutex, request->cookie);
1157 trace_i915_request_add(request);
1160 * Make sure that no request gazumped us - if it was allocated after
1161 * our i915_request_alloc() and called __i915_request_add() before
1162 * us, the timeline will hold its seqno which is later than ours.
1164 GEM_BUG_ON(timeline->seqno != request->fence.seqno);
1167 * To ensure that this call will not fail, space for its emissions
1168 * should already have been reserved in the ring buffer. Let the ring
1169 * know that it is time to use that space up.
1171 GEM_BUG_ON(request->reserved_space > request->ring->space);
1172 request->reserved_space = 0;
1175 * Record the position of the start of the breadcrumb so that
1176 * should we detect the updated seqno part-way through the
1177 * GPU processing the request, we never over-estimate the
1178 * position of the ring's HEAD.
1180 cs = intel_ring_begin(request, engine->emit_fini_breadcrumb_dw);
1181 GEM_BUG_ON(IS_ERR(cs));
1182 request->postfix = intel_ring_offset(request, cs);
1184 prev = __i915_request_add_to_timeline(request);
1186 list_add_tail(&request->ring_link, &ring->request_list);
1187 if (list_is_first(&request->ring_link, &ring->request_list))
1188 list_add(&ring->active_link, &request->i915->gt.active_rings);
1189 request->i915->gt.active_engines |= request->engine->mask;
1190 request->emitted_jiffies = jiffies;
1193 * Let the backend know a new request has arrived that may need
1194 * to adjust the existing execution schedule due to a high priority
1195 * request - i.e. we may want to preempt the current request in order
1196 * to run a high priority dependency chain *before* we can execute this
1199 * This is called before the request is ready to run so that we can
1200 * decide whether to preempt the entire chain so that it is ready to
1201 * run at the earliest possible convenience.
1204 i915_sw_fence_commit(&request->semaphore);
1205 rcu_read_lock(); /* RCU serialisation for set-wedged protection */
1206 if (engine->schedule) {
1207 struct i915_sched_attr attr = request->gem_context->sched;
1210 * Boost actual workloads past semaphores!
1212 * With semaphores we spin on one engine waiting for another,
1213 * simply to reduce the latency of starting our work when
1214 * the signaler completes. However, if there is any other
1215 * work that we could be doing on this engine instead, that
1216 * is better utilisation and will reduce the overall duration
1217 * of the current work. To avoid PI boosting a semaphore
1218 * far in the distance past over useful work, we keep a history
1219 * of any semaphore use along our dependency chain.
1221 if (!(request->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN))
1222 attr.priority |= I915_PRIORITY_NOSEMAPHORE;
1225 * Boost priorities to new clients (new request flows).
1227 * Allow interactive/synchronous clients to jump ahead of
1228 * the bulk clients. (FQ_CODEL)
1230 if (list_empty(&request->sched.signalers_list))
1231 attr.priority |= I915_PRIORITY_NEWCLIENT;
1233 engine->schedule(request, &attr);
1236 i915_sw_fence_commit(&request->submit);
1237 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
1240 * In typical scenarios, we do not expect the previous request on
1241 * the timeline to be still tracked by timeline->last_request if it
1242 * has been completed. If the completed request is still here, that
1243 * implies that request retirement is a long way behind submission,
1244 * suggesting that we haven't been retiring frequently enough from
1245 * the combination of retire-before-alloc, waiters and the background
1246 * retirement worker. So if the last request on this timeline was
1247 * already completed, do a catch up pass, flushing the retirement queue
1248 * up to this client. Since we have now moved the heaviest operations
1249 * during retirement onto secondary workers, such as freeing objects
1250 * or contexts, retiring a bunch of requests is mostly list management
1251 * (and cache misses), and so we should not be overly penalizing this
1252 * client by performing excess work, though we may still performing
1253 * work on behalf of others -- but instead we should benefit from
1254 * improved resource management. (Well, that's the theory at least.)
1256 if (prev && i915_request_completed(prev))
1257 i915_request_retire_upto(prev);
1259 mutex_unlock(&request->timeline->mutex);
1262 static unsigned long local_clock_us(unsigned int *cpu)
1267 * Cheaply and approximately convert from nanoseconds to microseconds.
1268 * The result and subsequent calculations are also defined in the same
1269 * approximate microseconds units. The principal source of timing
1270 * error here is from the simple truncation.
1272 * Note that local_clock() is only defined wrt to the current CPU;
1273 * the comparisons are no longer valid if we switch CPUs. Instead of
1274 * blocking preemption for the entire busywait, we can detect the CPU
1275 * switch and use that as indicator of system load and a reason to
1276 * stop busywaiting, see busywait_stop().
1279 t = local_clock() >> 10;
1285 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1287 unsigned int this_cpu;
1289 if (time_after(local_clock_us(&this_cpu), timeout))
1292 return this_cpu != cpu;
1295 static bool __i915_spin_request(const struct i915_request * const rq,
1296 int state, unsigned long timeout_us)
1301 * Only wait for the request if we know it is likely to complete.
1303 * We don't track the timestamps around requests, nor the average
1304 * request length, so we do not have a good indicator that this
1305 * request will complete within the timeout. What we do know is the
1306 * order in which requests are executed by the context and so we can
1307 * tell if the request has been started. If the request is not even
1308 * running yet, it is a fair assumption that it will not complete
1309 * within our relatively short timeout.
1311 if (!i915_request_is_running(rq))
1315 * When waiting for high frequency requests, e.g. during synchronous
1316 * rendering split between the CPU and GPU, the finite amount of time
1317 * required to set up the irq and wait upon it limits the response
1318 * rate. By busywaiting on the request completion for a short while we
1319 * can service the high frequency waits as quick as possible. However,
1320 * if it is a slow request, we want to sleep as quickly as possible.
1321 * The tradeoff between waiting and sleeping is roughly the time it
1322 * takes to sleep on a request, on the order of a microsecond.
1325 timeout_us += local_clock_us(&cpu);
1327 if (i915_request_completed(rq))
1330 if (signal_pending_state(state, current))
1333 if (busywait_stop(timeout_us, cpu))
1337 } while (!need_resched());
1342 struct request_wait {
1343 struct dma_fence_cb cb;
1344 struct task_struct *tsk;
1347 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1349 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1351 wake_up_process(wait->tsk);
1355 * i915_request_wait - wait until execution of request has finished
1356 * @rq: the request to wait upon
1357 * @flags: how to wait
1358 * @timeout: how long to wait in jiffies
1360 * i915_request_wait() waits for the request to be completed, for a
1361 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1364 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
1365 * in via the flags, and vice versa if the struct_mutex is not held, the caller
1366 * must not specify that the wait is locked.
1368 * Returns the remaining time (in jiffies) if the request completed, which may
1369 * be zero or -ETIME if the request is unfinished after the timeout expires.
1370 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1371 * pending before the request completes.
1373 long i915_request_wait(struct i915_request *rq,
1377 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1378 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1379 struct request_wait wait;
1382 GEM_BUG_ON(timeout < 0);
1384 if (i915_request_completed(rq))
1390 trace_i915_request_wait_begin(rq, flags);
1392 /* Optimistic short spin before touching IRQs */
1393 if (__i915_spin_request(rq, state, 5))
1397 * This client is about to stall waiting for the GPU. In many cases
1398 * this is undesirable and limits the throughput of the system, as
1399 * many clients cannot continue processing user input/output whilst
1400 * blocked. RPS autotuning may take tens of milliseconds to respond
1401 * to the GPU load and thus incurs additional latency for the client.
1402 * We can circumvent that by promoting the GPU frequency to maximum
1403 * before we sleep. This makes the GPU throttle up much more quickly
1404 * (good for benchmarks and user experience, e.g. window animations),
1405 * but at a cost of spending more power processing the workload
1406 * (bad for battery).
1408 if (flags & I915_WAIT_PRIORITY) {
1409 if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
1411 local_bh_disable(); /* suspend tasklets for reprioritisation */
1412 i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
1413 local_bh_enable(); /* kick tasklets en masse */
1417 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1421 set_current_state(state);
1423 if (i915_request_completed(rq))
1426 if (signal_pending_state(state, current)) {
1427 timeout = -ERESTARTSYS;
1436 timeout = io_schedule_timeout(timeout);
1438 __set_current_state(TASK_RUNNING);
1440 dma_fence_remove_callback(&rq->fence, &wait.cb);
1443 trace_i915_request_wait_end(rq);
1447 void i915_retire_requests(struct drm_i915_private *i915)
1449 struct intel_ring *ring, *tmp;
1451 lockdep_assert_held(&i915->drm.struct_mutex);
1453 if (!i915->gt.active_requests)
1456 list_for_each_entry_safe(ring, tmp,
1457 &i915->gt.active_rings, active_link) {
1458 intel_ring_get(ring); /* last rq holds reference! */
1459 ring_retire_requests(ring);
1460 intel_ring_put(ring);
1464 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1465 #include "selftests/mock_request.c"
1466 #include "selftests/i915_request.c"
1469 static void i915_global_request_shrink(void)
1471 kmem_cache_shrink(global.slab_dependencies);
1472 kmem_cache_shrink(global.slab_execute_cbs);
1473 kmem_cache_shrink(global.slab_requests);
1476 static void i915_global_request_exit(void)
1478 kmem_cache_destroy(global.slab_dependencies);
1479 kmem_cache_destroy(global.slab_execute_cbs);
1480 kmem_cache_destroy(global.slab_requests);
1483 static struct i915_global_request global = { {
1484 .shrink = i915_global_request_shrink,
1485 .exit = i915_global_request_exit,
1488 int __init i915_global_request_init(void)
1490 global.slab_requests = KMEM_CACHE(i915_request,
1491 SLAB_HWCACHE_ALIGN |
1492 SLAB_RECLAIM_ACCOUNT |
1493 SLAB_TYPESAFE_BY_RCU);
1494 if (!global.slab_requests)
1497 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1498 SLAB_HWCACHE_ALIGN |
1499 SLAB_RECLAIM_ACCOUNT |
1500 SLAB_TYPESAFE_BY_RCU);
1501 if (!global.slab_execute_cbs)
1504 global.slab_dependencies = KMEM_CACHE(i915_dependency,
1505 SLAB_HWCACHE_ALIGN |
1506 SLAB_RECLAIM_ACCOUNT);
1507 if (!global.slab_dependencies)
1508 goto err_execute_cbs;
1510 i915_global_register(&global.base);
1514 kmem_cache_destroy(global.slab_execute_cbs);
1516 kmem_cache_destroy(global.slab_requests);