2 * Copyright © 2006-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
29 * The display engine uses several different clocks to do its work. There
30 * are two main clocks involved that aren't directly related to the actual
31 * pixel clock or any symbol/bit clock of the actual output port. These
32 * are the core display clock (CDCLK) and RAWCLK.
34 * CDCLK clocks most of the display pipe logic, and thus its frequency
35 * must be high enough to support the rate at which pixels are flowing
36 * through the pipes. Downscaling must also be accounted as that increases
37 * the effective pixel rate.
39 * On several platforms the CDCLK frequency can be changed dynamically
40 * to minimize power consumption for a given display configuration.
41 * Typically changes to the CDCLK frequency require all the display pipes
42 * to be shut down while the frequency is being changed.
44 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
45 * DMC will not change the active CDCLK frequency however, so that part
46 * will still be performed by the driver directly.
48 * RAWCLK is a fixed frequency clock, often used by various auxiliary
49 * blocks such as AUX CH or backlight PWM. Hence the only thing we
50 * really need to know about RAWCLK is its frequency so that various
51 * dividers can be programmed correctly.
54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
55 struct intel_cdclk_state *cdclk_state)
57 cdclk_state->cdclk = 133333;
60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
61 struct intel_cdclk_state *cdclk_state)
63 cdclk_state->cdclk = 200000;
66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
67 struct intel_cdclk_state *cdclk_state)
69 cdclk_state->cdclk = 266667;
72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
73 struct intel_cdclk_state *cdclk_state)
75 cdclk_state->cdclk = 333333;
78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
79 struct intel_cdclk_state *cdclk_state)
81 cdclk_state->cdclk = 400000;
84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
85 struct intel_cdclk_state *cdclk_state)
87 cdclk_state->cdclk = 450000;
90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
91 struct intel_cdclk_state *cdclk_state)
93 struct pci_dev *pdev = dev_priv->drm.pdev;
97 * 852GM/852GMV only supports 133 MHz and the HPLLCC
98 * encoding is different :(
99 * FIXME is this the right way to detect 852GM/852GMV?
101 if (pdev->revision == 0x1) {
102 cdclk_state->cdclk = 133333;
106 pci_bus_read_config_word(pdev->bus,
107 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
109 /* Assume that the hardware is in the high speed state. This
110 * should be the default.
112 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
113 case GC_CLOCK_133_200:
114 case GC_CLOCK_133_200_2:
115 case GC_CLOCK_100_200:
116 cdclk_state->cdclk = 200000;
118 case GC_CLOCK_166_250:
119 cdclk_state->cdclk = 250000;
121 case GC_CLOCK_100_133:
122 cdclk_state->cdclk = 133333;
124 case GC_CLOCK_133_266:
125 case GC_CLOCK_133_266_2:
126 case GC_CLOCK_166_266:
127 cdclk_state->cdclk = 266667;
132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
133 struct intel_cdclk_state *cdclk_state)
135 struct pci_dev *pdev = dev_priv->drm.pdev;
138 pci_read_config_word(pdev, GCFGC, &gcfgc);
140 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
141 cdclk_state->cdclk = 133333;
145 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
146 case GC_DISPLAY_CLOCK_333_320_MHZ:
147 cdclk_state->cdclk = 333333;
150 case GC_DISPLAY_CLOCK_190_200_MHZ:
151 cdclk_state->cdclk = 190000;
156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
157 struct intel_cdclk_state *cdclk_state)
159 struct pci_dev *pdev = dev_priv->drm.pdev;
162 pci_read_config_word(pdev, GCFGC, &gcfgc);
164 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
165 cdclk_state->cdclk = 133333;
169 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
170 case GC_DISPLAY_CLOCK_333_320_MHZ:
171 cdclk_state->cdclk = 320000;
174 case GC_DISPLAY_CLOCK_190_200_MHZ:
175 cdclk_state->cdclk = 200000;
180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
182 static const unsigned int blb_vco[8] = {
189 static const unsigned int pnv_vco[8] = {
196 static const unsigned int cl_vco[8] = {
205 static const unsigned int elk_vco[8] = {
211 static const unsigned int ctg_vco[8] = {
219 const unsigned int *vco_table;
223 /* FIXME other chipsets? */
224 if (IS_GM45(dev_priv))
226 else if (IS_G45(dev_priv))
228 else if (IS_I965GM(dev_priv))
230 else if (IS_PINEVIEW(dev_priv))
232 else if (IS_G33(dev_priv))
237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
239 vco = vco_table[tmp & 0x7];
241 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
243 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
249 struct intel_cdclk_state *cdclk_state)
251 struct pci_dev *pdev = dev_priv->drm.pdev;
252 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
253 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
254 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
255 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
256 const uint8_t *div_table;
257 unsigned int cdclk_sel;
260 cdclk_state->vco = intel_hpll_vco(dev_priv);
262 pci_read_config_word(pdev, GCFGC, &tmp);
264 cdclk_sel = (tmp >> 4) & 0x7;
266 if (cdclk_sel >= ARRAY_SIZE(div_3200))
269 switch (cdclk_state->vco) {
271 div_table = div_3200;
274 div_table = div_4000;
277 div_table = div_4800;
280 div_table = div_5333;
286 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
287 div_table[cdclk_sel]);
291 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
292 cdclk_state->vco, tmp);
293 cdclk_state->cdclk = 190476;
296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
297 struct intel_cdclk_state *cdclk_state)
299 struct pci_dev *pdev = dev_priv->drm.pdev;
302 pci_read_config_word(pdev, GCFGC, &gcfgc);
304 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
305 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
306 cdclk_state->cdclk = 266667;
308 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
309 cdclk_state->cdclk = 333333;
311 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
312 cdclk_state->cdclk = 444444;
314 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
315 cdclk_state->cdclk = 200000;
318 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
319 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
320 cdclk_state->cdclk = 133333;
322 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
323 cdclk_state->cdclk = 166667;
328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
329 struct intel_cdclk_state *cdclk_state)
331 struct pci_dev *pdev = dev_priv->drm.pdev;
332 static const uint8_t div_3200[] = { 16, 10, 8 };
333 static const uint8_t div_4000[] = { 20, 12, 10 };
334 static const uint8_t div_5333[] = { 24, 16, 14 };
335 const uint8_t *div_table;
336 unsigned int cdclk_sel;
339 cdclk_state->vco = intel_hpll_vco(dev_priv);
341 pci_read_config_word(pdev, GCFGC, &tmp);
343 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
345 if (cdclk_sel >= ARRAY_SIZE(div_3200))
348 switch (cdclk_state->vco) {
350 div_table = div_3200;
353 div_table = div_4000;
356 div_table = div_5333;
362 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
363 div_table[cdclk_sel]);
367 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
368 cdclk_state->vco, tmp);
369 cdclk_state->cdclk = 200000;
372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
373 struct intel_cdclk_state *cdclk_state)
375 struct pci_dev *pdev = dev_priv->drm.pdev;
376 unsigned int cdclk_sel;
379 cdclk_state->vco = intel_hpll_vco(dev_priv);
381 pci_read_config_word(pdev, GCFGC, &tmp);
383 cdclk_sel = (tmp >> 12) & 0x1;
385 switch (cdclk_state->vco) {
389 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
392 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
395 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
396 cdclk_state->vco, tmp);
397 cdclk_state->cdclk = 222222;
402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
403 struct intel_cdclk_state *cdclk_state)
405 uint32_t lcpll = I915_READ(LCPLL_CTL);
406 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
408 if (lcpll & LCPLL_CD_SOURCE_FCLK)
409 cdclk_state->cdclk = 800000;
410 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
411 cdclk_state->cdclk = 450000;
412 else if (freq == LCPLL_CLK_FREQ_450)
413 cdclk_state->cdclk = 450000;
414 else if (IS_HSW_ULT(dev_priv))
415 cdclk_state->cdclk = 337500;
417 cdclk_state->cdclk = 540000;
420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv,
423 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
425 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
428 * We seem to get an unstable or solid color picture at 200MHz.
429 * Not sure what's wrong. For now use 200MHz only when all pipes
432 if (!IS_CHERRYVIEW(dev_priv) &&
433 max_pixclk > freq_320*limit/100)
435 else if (max_pixclk > 266667*limit/100)
437 else if (max_pixclk > 0)
443 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
444 struct intel_cdclk_state *cdclk_state)
446 cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
447 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
448 CCK_DISPLAY_CLOCK_CONTROL,
452 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
454 unsigned int credits, default_credits;
456 if (IS_CHERRYVIEW(dev_priv))
457 default_credits = PFI_CREDIT(12);
459 default_credits = PFI_CREDIT(8);
461 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
462 /* CHV suggested value is 31 or 63 */
463 if (IS_CHERRYVIEW(dev_priv))
464 credits = PFI_CREDIT_63;
466 credits = PFI_CREDIT(15);
468 credits = default_credits;
472 * WA - write default credits before re-programming
473 * FIXME: should we also set the resend bit here?
475 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
478 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
479 credits | PFI_CREDIT_RESEND);
482 * FIXME is this guaranteed to clear
483 * immediately or should we poll for it?
485 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
488 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
489 const struct intel_cdclk_state *cdclk_state)
491 int cdclk = cdclk_state->cdclk;
494 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
496 else if (cdclk == 266667)
501 mutex_lock(&dev_priv->rps.hw_lock);
502 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
503 val &= ~DSPFREQGUAR_MASK;
504 val |= (cmd << DSPFREQGUAR_SHIFT);
505 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
506 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
507 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
509 DRM_ERROR("timed out waiting for CDclk change\n");
511 mutex_unlock(&dev_priv->rps.hw_lock);
513 mutex_lock(&dev_priv->sb_lock);
515 if (cdclk == 400000) {
518 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
521 /* adjust cdclk divider */
522 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
523 val &= ~CCK_FREQUENCY_VALUES;
525 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
527 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
528 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
530 DRM_ERROR("timed out waiting for CDclk change\n");
533 /* adjust self-refresh exit latency value */
534 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
538 * For high bandwidth configs, we set a higher latency in the bunit
539 * so that the core display fetch happens in time to avoid underruns.
542 val |= 4500 / 250; /* 4.5 usec */
544 val |= 3000 / 250; /* 3.0 usec */
545 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
547 mutex_unlock(&dev_priv->sb_lock);
549 intel_update_cdclk(dev_priv);
551 vlv_program_pfi_credits(dev_priv);
554 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
555 const struct intel_cdclk_state *cdclk_state)
557 int cdclk = cdclk_state->cdclk;
572 * Specs are full of misinformation, but testing on actual
573 * hardware has shown that we just need to write the desired
574 * CCK divider into the Punit register.
576 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
578 mutex_lock(&dev_priv->rps.hw_lock);
579 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
580 val &= ~DSPFREQGUAR_MASK_CHV;
581 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
582 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
583 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
584 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
586 DRM_ERROR("timed out waiting for CDclk change\n");
588 mutex_unlock(&dev_priv->rps.hw_lock);
590 intel_update_cdclk(dev_priv);
592 vlv_program_pfi_credits(dev_priv);
595 static int bdw_calc_cdclk(int max_pixclk)
597 if (max_pixclk > 540000)
599 else if (max_pixclk > 450000)
601 else if (max_pixclk > 337500)
607 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
608 struct intel_cdclk_state *cdclk_state)
610 uint32_t lcpll = I915_READ(LCPLL_CTL);
611 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
613 if (lcpll & LCPLL_CD_SOURCE_FCLK)
614 cdclk_state->cdclk = 800000;
615 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
616 cdclk_state->cdclk = 450000;
617 else if (freq == LCPLL_CLK_FREQ_450)
618 cdclk_state->cdclk = 450000;
619 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
620 cdclk_state->cdclk = 540000;
621 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
622 cdclk_state->cdclk = 337500;
624 cdclk_state->cdclk = 675000;
627 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
628 const struct intel_cdclk_state *cdclk_state)
630 int cdclk = cdclk_state->cdclk;
634 if (WARN((I915_READ(LCPLL_CTL) &
635 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
636 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
637 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
638 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
639 "trying to change cdclk frequency with cdclk not enabled\n"))
642 mutex_lock(&dev_priv->rps.hw_lock);
643 ret = sandybridge_pcode_write(dev_priv,
644 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
645 mutex_unlock(&dev_priv->rps.hw_lock);
647 DRM_ERROR("failed to inform pcode about cdclk change\n");
651 val = I915_READ(LCPLL_CTL);
652 val |= LCPLL_CD_SOURCE_FCLK;
653 I915_WRITE(LCPLL_CTL, val);
655 if (wait_for_us(I915_READ(LCPLL_CTL) &
656 LCPLL_CD_SOURCE_FCLK_DONE, 1))
657 DRM_ERROR("Switching to FCLK failed\n");
659 val = I915_READ(LCPLL_CTL);
660 val &= ~LCPLL_CLK_FREQ_MASK;
664 val |= LCPLL_CLK_FREQ_450;
668 val |= LCPLL_CLK_FREQ_54O_BDW;
672 val |= LCPLL_CLK_FREQ_337_5_BDW;
676 val |= LCPLL_CLK_FREQ_675_BDW;
680 WARN(1, "invalid cdclk frequency\n");
684 I915_WRITE(LCPLL_CTL, val);
686 val = I915_READ(LCPLL_CTL);
687 val &= ~LCPLL_CD_SOURCE_FCLK;
688 I915_WRITE(LCPLL_CTL, val);
690 if (wait_for_us((I915_READ(LCPLL_CTL) &
691 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
692 DRM_ERROR("Switching back to LCPLL failed\n");
694 mutex_lock(&dev_priv->rps.hw_lock);
695 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
696 mutex_unlock(&dev_priv->rps.hw_lock);
698 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
700 intel_update_cdclk(dev_priv);
702 WARN(cdclk != dev_priv->cdclk.hw.cdclk,
703 "cdclk requested %d kHz but got %d kHz\n",
704 cdclk, dev_priv->cdclk.hw.cdclk);
707 static int skl_calc_cdclk(int max_pixclk, int vco)
709 if (vco == 8640000) {
710 if (max_pixclk > 540000)
712 else if (max_pixclk > 432000)
714 else if (max_pixclk > 308571)
719 if (max_pixclk > 540000)
721 else if (max_pixclk > 450000)
723 else if (max_pixclk > 337500)
730 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
731 struct intel_cdclk_state *cdclk_state)
735 cdclk_state->ref = 24000;
736 cdclk_state->vco = 0;
738 val = I915_READ(LCPLL1_CTL);
739 if ((val & LCPLL_PLL_ENABLE) == 0)
742 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
745 val = I915_READ(DPLL_CTRL1);
747 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
748 DPLL_CTRL1_SSC(SKL_DPLL0) |
749 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
750 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
753 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
754 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
755 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
756 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
757 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
758 cdclk_state->vco = 8100000;
760 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
761 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
762 cdclk_state->vco = 8640000;
765 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
770 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
771 struct intel_cdclk_state *cdclk_state)
775 skl_dpll0_update(dev_priv, cdclk_state);
777 cdclk_state->cdclk = cdclk_state->ref;
779 if (cdclk_state->vco == 0)
782 cdctl = I915_READ(CDCLK_CTL);
784 if (cdclk_state->vco == 8640000) {
785 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
786 case CDCLK_FREQ_450_432:
787 cdclk_state->cdclk = 432000;
789 case CDCLK_FREQ_337_308:
790 cdclk_state->cdclk = 308571;
793 cdclk_state->cdclk = 540000;
795 case CDCLK_FREQ_675_617:
796 cdclk_state->cdclk = 617143;
799 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
803 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
804 case CDCLK_FREQ_450_432:
805 cdclk_state->cdclk = 450000;
807 case CDCLK_FREQ_337_308:
808 cdclk_state->cdclk = 337500;
811 cdclk_state->cdclk = 540000;
813 case CDCLK_FREQ_675_617:
814 cdclk_state->cdclk = 675000;
817 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
823 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
824 static int skl_cdclk_decimal(int cdclk)
826 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
829 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
832 bool changed = dev_priv->skl_preferred_vco_freq != vco;
834 dev_priv->skl_preferred_vco_freq = vco;
837 intel_update_max_cdclk(dev_priv);
840 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
842 int min_cdclk = skl_calc_cdclk(0, vco);
845 WARN_ON(vco != 8100000 && vco != 8640000);
847 /* select the minimum CDCLK before enabling DPLL 0 */
848 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
849 I915_WRITE(CDCLK_CTL, val);
850 POSTING_READ(CDCLK_CTL);
853 * We always enable DPLL0 with the lowest link rate possible, but still
854 * taking into account the VCO required to operate the eDP panel at the
855 * desired frequency. The usual DP link rates operate with a VCO of
856 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
857 * The modeset code is responsible for the selection of the exact link
858 * rate later on, with the constraint of choosing a frequency that
861 val = I915_READ(DPLL_CTRL1);
863 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
864 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
865 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
867 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
870 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
873 I915_WRITE(DPLL_CTRL1, val);
874 POSTING_READ(DPLL_CTRL1);
876 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
878 if (intel_wait_for_register(dev_priv,
879 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
881 DRM_ERROR("DPLL0 not locked\n");
883 dev_priv->cdclk.hw.vco = vco;
885 /* We'll want to keep using the current vco from now on. */
886 skl_set_preferred_cdclk_vco(dev_priv, vco);
889 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
891 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
892 if (intel_wait_for_register(dev_priv,
893 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
895 DRM_ERROR("Couldn't disable DPLL0\n");
897 dev_priv->cdclk.hw.vco = 0;
900 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
901 const struct intel_cdclk_state *cdclk_state)
903 int cdclk = cdclk_state->cdclk;
904 int vco = cdclk_state->vco;
905 u32 freq_select, pcu_ack;
908 WARN_ON((cdclk == 24000) != (vco == 0));
910 mutex_lock(&dev_priv->rps.hw_lock);
911 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
912 SKL_CDCLK_PREPARE_FOR_CHANGE,
913 SKL_CDCLK_READY_FOR_CHANGE,
914 SKL_CDCLK_READY_FOR_CHANGE, 3);
915 mutex_unlock(&dev_priv->rps.hw_lock);
917 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
926 freq_select = CDCLK_FREQ_450_432;
930 freq_select = CDCLK_FREQ_540;
936 freq_select = CDCLK_FREQ_337_308;
941 freq_select = CDCLK_FREQ_675_617;
946 if (dev_priv->cdclk.hw.vco != 0 &&
947 dev_priv->cdclk.hw.vco != vco)
948 skl_dpll0_disable(dev_priv);
950 if (dev_priv->cdclk.hw.vco != vco)
951 skl_dpll0_enable(dev_priv, vco);
953 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
954 POSTING_READ(CDCLK_CTL);
956 /* inform PCU of the change */
957 mutex_lock(&dev_priv->rps.hw_lock);
958 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
959 mutex_unlock(&dev_priv->rps.hw_lock);
961 intel_update_cdclk(dev_priv);
964 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
966 uint32_t cdctl, expected;
969 * check if the pre-os initialized the display
970 * There is SWF18 scratchpad register defined which is set by the
971 * pre-os which can be used by the OS drivers to check the status
973 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
976 intel_update_cdclk(dev_priv);
977 /* Is PLL enabled and locked ? */
978 if (dev_priv->cdclk.hw.vco == 0 ||
979 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
982 /* DPLL okay; verify the cdclock
984 * Noticed in some instances that the freq selection is correct but
985 * decimal part is programmed wrong from BIOS where pre-os does not
986 * enable display. Verify the same as well.
988 cdctl = I915_READ(CDCLK_CTL);
989 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
990 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
991 if (cdctl == expected)
992 /* All well; nothing to sanitize */
996 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
998 /* force cdclk programming */
999 dev_priv->cdclk.hw.cdclk = 0;
1000 /* force full PLL disable + enable */
1001 dev_priv->cdclk.hw.vco = -1;
1005 * skl_init_cdclk - Initialize CDCLK on SKL
1006 * @dev_priv: i915 device
1008 * Initialize CDCLK for SKL and derivatives. This is generally
1009 * done only during the display core initialization sequence,
1010 * after which the DMC will take care of turning CDCLK off/on
1013 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1015 struct intel_cdclk_state cdclk_state;
1017 skl_sanitize_cdclk(dev_priv);
1019 if (dev_priv->cdclk.hw.cdclk != 0 &&
1020 dev_priv->cdclk.hw.vco != 0) {
1022 * Use the current vco as our initial
1023 * guess as to what the preferred vco is.
1025 if (dev_priv->skl_preferred_vco_freq == 0)
1026 skl_set_preferred_cdclk_vco(dev_priv,
1027 dev_priv->cdclk.hw.vco);
1031 cdclk_state = dev_priv->cdclk.hw;
1033 cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1034 if (cdclk_state.vco == 0)
1035 cdclk_state.vco = 8100000;
1036 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1038 skl_set_cdclk(dev_priv, &cdclk_state);
1042 * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1043 * @dev_priv: i915 device
1045 * Uninitialize CDCLK for SKL and derivatives. This is done only
1046 * during the display core uninitialization sequence.
1048 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1050 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1052 cdclk_state.cdclk = cdclk_state.ref;
1053 cdclk_state.vco = 0;
1055 skl_set_cdclk(dev_priv, &cdclk_state);
1058 static int bxt_calc_cdclk(int max_pixclk)
1060 if (max_pixclk > 576000)
1062 else if (max_pixclk > 384000)
1064 else if (max_pixclk > 288000)
1066 else if (max_pixclk > 144000)
1072 static int glk_calc_cdclk(int max_pixclk)
1075 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1076 * as a temporary workaround. Use a higher cdclk instead. (Note that
1077 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1080 if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
1082 else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
1088 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1092 if (cdclk == dev_priv->cdclk.hw.ref)
1097 MISSING_CASE(cdclk);
1109 return dev_priv->cdclk.hw.ref * ratio;
1112 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1116 if (cdclk == dev_priv->cdclk.hw.ref)
1121 MISSING_CASE(cdclk);
1129 return dev_priv->cdclk.hw.ref * ratio;
1132 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1133 struct intel_cdclk_state *cdclk_state)
1137 cdclk_state->ref = 19200;
1138 cdclk_state->vco = 0;
1140 val = I915_READ(BXT_DE_PLL_ENABLE);
1141 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1144 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1147 val = I915_READ(BXT_DE_PLL_CTL);
1148 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1151 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1152 struct intel_cdclk_state *cdclk_state)
1157 bxt_de_pll_update(dev_priv, cdclk_state);
1159 cdclk_state->cdclk = cdclk_state->ref;
1161 if (cdclk_state->vco == 0)
1164 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1167 case BXT_CDCLK_CD2X_DIV_SEL_1:
1170 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1171 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1174 case BXT_CDCLK_CD2X_DIV_SEL_2:
1177 case BXT_CDCLK_CD2X_DIV_SEL_4:
1181 MISSING_CASE(divider);
1185 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1188 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1190 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1193 if (intel_wait_for_register(dev_priv,
1194 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1196 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1198 dev_priv->cdclk.hw.vco = 0;
1201 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1203 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1206 val = I915_READ(BXT_DE_PLL_CTL);
1207 val &= ~BXT_DE_PLL_RATIO_MASK;
1208 val |= BXT_DE_PLL_RATIO(ratio);
1209 I915_WRITE(BXT_DE_PLL_CTL, val);
1211 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1214 if (intel_wait_for_register(dev_priv,
1219 DRM_ERROR("timeout waiting for DE PLL lock\n");
1221 dev_priv->cdclk.hw.vco = vco;
1224 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1225 const struct intel_cdclk_state *cdclk_state)
1227 int cdclk = cdclk_state->cdclk;
1228 int vco = cdclk_state->vco;
1232 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1233 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1235 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1238 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1241 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1242 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1245 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1248 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1251 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1255 /* Inform power controller of upcoming frequency change */
1256 mutex_lock(&dev_priv->rps.hw_lock);
1257 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1259 mutex_unlock(&dev_priv->rps.hw_lock);
1262 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1267 if (dev_priv->cdclk.hw.vco != 0 &&
1268 dev_priv->cdclk.hw.vco != vco)
1269 bxt_de_pll_disable(dev_priv);
1271 if (dev_priv->cdclk.hw.vco != vco)
1272 bxt_de_pll_enable(dev_priv, vco);
1274 val = divider | skl_cdclk_decimal(cdclk);
1276 * FIXME if only the cd2x divider needs changing, it could be done
1277 * without shutting off the pipe (if only one pipe is active).
1279 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1281 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1284 if (cdclk >= 500000)
1285 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1286 I915_WRITE(CDCLK_CTL, val);
1288 mutex_lock(&dev_priv->rps.hw_lock);
1289 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1290 DIV_ROUND_UP(cdclk, 25000));
1291 mutex_unlock(&dev_priv->rps.hw_lock);
1294 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1299 intel_update_cdclk(dev_priv);
1302 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1304 u32 cdctl, expected;
1306 intel_update_cdclk(dev_priv);
1308 if (dev_priv->cdclk.hw.vco == 0 ||
1309 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1312 /* DPLL okay; verify the cdclock
1314 * Some BIOS versions leave an incorrect decimal frequency value and
1315 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1316 * so sanitize this register.
1318 cdctl = I915_READ(CDCLK_CTL);
1320 * Let's ignore the pipe field, since BIOS could have configured the
1321 * dividers both synching to an active pipe, or asynchronously
1324 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1326 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1327 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1329 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1332 if (dev_priv->cdclk.hw.cdclk >= 500000)
1333 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1335 if (cdctl == expected)
1336 /* All well; nothing to sanitize */
1340 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1342 /* force cdclk programming */
1343 dev_priv->cdclk.hw.cdclk = 0;
1345 /* force full PLL disable + enable */
1346 dev_priv->cdclk.hw.vco = -1;
1350 * bxt_init_cdclk - Initialize CDCLK on BXT
1351 * @dev_priv: i915 device
1353 * Initialize CDCLK for BXT and derivatives. This is generally
1354 * done only during the display core initialization sequence,
1355 * after which the DMC will take care of turning CDCLK off/on
1358 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1360 struct intel_cdclk_state cdclk_state;
1362 bxt_sanitize_cdclk(dev_priv);
1364 if (dev_priv->cdclk.hw.cdclk != 0 &&
1365 dev_priv->cdclk.hw.vco != 0)
1368 cdclk_state = dev_priv->cdclk.hw;
1372 * - The initial CDCLK needs to be read from VBT.
1373 * Need to make this change after VBT has changes for BXT.
1375 if (IS_GEMINILAKE(dev_priv)) {
1376 cdclk_state.cdclk = glk_calc_cdclk(0);
1377 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1379 cdclk_state.cdclk = bxt_calc_cdclk(0);
1380 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1383 bxt_set_cdclk(dev_priv, &cdclk_state);
1387 * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1388 * @dev_priv: i915 device
1390 * Uninitialize CDCLK for BXT and derivatives. This is done only
1391 * during the display core uninitialization sequence.
1393 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1395 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1397 cdclk_state.cdclk = cdclk_state.ref;
1398 cdclk_state.vco = 0;
1400 bxt_set_cdclk(dev_priv, &cdclk_state);
1403 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1404 struct intel_cdclk_state *cdclk_state)
1408 if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1409 cdclk_state->ref = 24000;
1411 cdclk_state->ref = 19200;
1413 cdclk_state->vco = 0;
1415 val = I915_READ(BXT_DE_PLL_ENABLE);
1416 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1419 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1422 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1425 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1426 struct intel_cdclk_state *cdclk_state)
1431 cnl_cdclk_pll_update(dev_priv, cdclk_state);
1433 cdclk_state->cdclk = cdclk_state->ref;
1435 if (cdclk_state->vco == 0)
1438 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1441 case BXT_CDCLK_CD2X_DIV_SEL_1:
1444 case BXT_CDCLK_CD2X_DIV_SEL_2:
1448 MISSING_CASE(divider);
1452 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1455 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1459 val = I915_READ(BXT_DE_PLL_ENABLE);
1460 val &= ~BXT_DE_PLL_PLL_ENABLE;
1461 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1464 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1465 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1467 dev_priv->cdclk.hw.vco = 0;
1470 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1472 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1475 val = CNL_CDCLK_PLL_RATIO(ratio);
1476 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1478 val |= BXT_DE_PLL_PLL_ENABLE;
1479 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1482 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1483 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1485 dev_priv->cdclk.hw.vco = vco;
1488 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1489 const struct intel_cdclk_state *cdclk_state)
1491 int cdclk = cdclk_state->cdclk;
1492 int vco = cdclk_state->vco;
1493 u32 val, divider, pcu_ack;
1496 mutex_lock(&dev_priv->rps.hw_lock);
1497 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1498 SKL_CDCLK_PREPARE_FOR_CHANGE,
1499 SKL_CDCLK_READY_FOR_CHANGE,
1500 SKL_CDCLK_READY_FOR_CHANGE, 3);
1501 mutex_unlock(&dev_priv->rps.hw_lock);
1503 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1508 /* cdclk = vco / 2 / div{1,2} */
1509 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1511 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1514 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1517 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1520 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1537 if (dev_priv->cdclk.hw.vco != 0 &&
1538 dev_priv->cdclk.hw.vco != vco)
1539 cnl_cdclk_pll_disable(dev_priv);
1541 if (dev_priv->cdclk.hw.vco != vco)
1542 cnl_cdclk_pll_enable(dev_priv, vco);
1544 val = divider | skl_cdclk_decimal(cdclk);
1546 * FIXME if only the cd2x divider needs changing, it could be done
1547 * without shutting off the pipe (if only one pipe is active).
1549 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1550 I915_WRITE(CDCLK_CTL, val);
1552 /* inform PCU of the change */
1553 mutex_lock(&dev_priv->rps.hw_lock);
1554 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1555 mutex_unlock(&dev_priv->rps.hw_lock);
1557 intel_update_cdclk(dev_priv);
1560 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1564 if (cdclk == dev_priv->cdclk.hw.ref)
1569 MISSING_CASE(cdclk);
1572 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1575 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1579 return dev_priv->cdclk.hw.ref * ratio;
1582 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1584 u32 cdctl, expected;
1586 intel_update_cdclk(dev_priv);
1588 if (dev_priv->cdclk.hw.vco == 0 ||
1589 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1592 /* DPLL okay; verify the cdclock
1594 * Some BIOS versions leave an incorrect decimal frequency value and
1595 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1596 * so sanitize this register.
1598 cdctl = I915_READ(CDCLK_CTL);
1600 * Let's ignore the pipe field, since BIOS could have configured the
1601 * dividers both synching to an active pipe, or asynchronously
1604 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1606 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1607 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1609 if (cdctl == expected)
1610 /* All well; nothing to sanitize */
1614 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1616 /* force cdclk programming */
1617 dev_priv->cdclk.hw.cdclk = 0;
1619 /* force full PLL disable + enable */
1620 dev_priv->cdclk.hw.vco = -1;
1624 * cnl_init_cdclk - Initialize CDCLK on CNL
1625 * @dev_priv: i915 device
1627 * Initialize CDCLK for CNL. This is generally
1628 * done only during the display core initialization sequence,
1629 * after which the DMC will take care of turning CDCLK off/on
1632 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1634 struct intel_cdclk_state cdclk_state;
1636 cnl_sanitize_cdclk(dev_priv);
1638 if (dev_priv->cdclk.hw.cdclk != 0 &&
1639 dev_priv->cdclk.hw.vco != 0)
1642 cdclk_state = dev_priv->cdclk.hw;
1644 cdclk_state.cdclk = 168000;
1645 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1647 cnl_set_cdclk(dev_priv, &cdclk_state);
1651 * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1652 * @dev_priv: i915 device
1654 * Uninitialize CDCLK for CNL. This is done only
1655 * during the display core uninitialization sequence.
1657 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1659 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1661 cdclk_state.cdclk = cdclk_state.ref;
1662 cdclk_state.vco = 0;
1664 cnl_set_cdclk(dev_priv, &cdclk_state);
1668 * intel_cdclk_state_compare - Determine if two CDCLK states differ
1669 * @a: first CDCLK state
1670 * @b: second CDCLK state
1673 * True if the CDCLK states are identical, false if they differ.
1675 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1676 const struct intel_cdclk_state *b)
1678 return memcmp(a, b, sizeof(*a)) == 0;
1682 * intel_set_cdclk - Push the CDCLK state to the hardware
1683 * @dev_priv: i915 device
1684 * @cdclk_state: new CDCLK state
1686 * Program the hardware based on the passed in CDCLK state,
1689 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1690 const struct intel_cdclk_state *cdclk_state)
1692 if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
1695 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1698 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1699 cdclk_state->cdclk, cdclk_state->vco,
1702 dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1705 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
1708 struct drm_i915_private *dev_priv =
1709 to_i915(crtc_state->base.crtc->dev);
1711 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1712 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1713 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
1715 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1716 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1717 * there may be audio corruption or screen corruption." This cdclk
1718 * restriction for GLK is 316.8 MHz and since GLK can output two
1719 * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.
1721 if (intel_crtc_has_dp_encoder(crtc_state) &&
1722 crtc_state->has_audio &&
1723 crtc_state->port_clock >= 540000 &&
1724 crtc_state->lane_count == 4) {
1725 if (IS_GEMINILAKE(dev_priv))
1726 pixel_rate = max(2 * 316800, pixel_rate);
1728 pixel_rate = max(432000, pixel_rate);
1731 /* According to BSpec, "The CD clock frequency must be at least twice
1732 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1733 * The check for GLK has to be adjusted as the platform can output
1734 * two pixels per clock.
1736 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
1737 if (IS_GEMINILAKE(dev_priv))
1738 pixel_rate = max(2 * 2 * 96000, pixel_rate);
1740 pixel_rate = max(2 * 96000, pixel_rate);
1746 /* compute the max rate for new configuration */
1747 static int intel_max_pixel_rate(struct drm_atomic_state *state)
1749 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1750 struct drm_i915_private *dev_priv = to_i915(state->dev);
1751 struct drm_crtc *crtc;
1752 struct drm_crtc_state *cstate;
1753 struct intel_crtc_state *crtc_state;
1754 unsigned int max_pixel_rate = 0, i;
1757 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
1758 sizeof(intel_state->min_pixclk));
1760 for_each_new_crtc_in_state(state, crtc, cstate, i) {
1763 crtc_state = to_intel_crtc_state(cstate);
1764 if (!crtc_state->base.enable) {
1765 intel_state->min_pixclk[i] = 0;
1769 pixel_rate = crtc_state->pixel_rate;
1771 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
1773 bdw_adjust_min_pipe_pixel_rate(crtc_state,
1776 intel_state->min_pixclk[i] = pixel_rate;
1779 for_each_pipe(dev_priv, pipe)
1780 max_pixel_rate = max(intel_state->min_pixclk[pipe],
1783 return max_pixel_rate;
1786 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1788 struct drm_i915_private *dev_priv = to_i915(state->dev);
1789 int max_pixclk = intel_max_pixel_rate(state);
1790 struct intel_atomic_state *intel_state =
1791 to_intel_atomic_state(state);
1794 cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
1796 if (cdclk > dev_priv->max_cdclk_freq) {
1797 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1798 cdclk, dev_priv->max_cdclk_freq);
1802 intel_state->cdclk.logical.cdclk = cdclk;
1804 if (!intel_state->active_crtcs) {
1805 cdclk = vlv_calc_cdclk(dev_priv, 0);
1807 intel_state->cdclk.actual.cdclk = cdclk;
1809 intel_state->cdclk.actual =
1810 intel_state->cdclk.logical;
1816 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1818 struct drm_i915_private *dev_priv = to_i915(state->dev);
1819 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1820 int max_pixclk = intel_max_pixel_rate(state);
1824 * FIXME should also account for plane ratio
1825 * once 64bpp pixel formats are supported.
1827 cdclk = bdw_calc_cdclk(max_pixclk);
1829 if (cdclk > dev_priv->max_cdclk_freq) {
1830 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1831 cdclk, dev_priv->max_cdclk_freq);
1835 intel_state->cdclk.logical.cdclk = cdclk;
1837 if (!intel_state->active_crtcs) {
1838 cdclk = bdw_calc_cdclk(0);
1840 intel_state->cdclk.actual.cdclk = cdclk;
1842 intel_state->cdclk.actual =
1843 intel_state->cdclk.logical;
1849 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1851 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1852 struct drm_i915_private *dev_priv = to_i915(state->dev);
1853 const int max_pixclk = intel_max_pixel_rate(state);
1856 vco = intel_state->cdclk.logical.vco;
1858 vco = dev_priv->skl_preferred_vco_freq;
1861 * FIXME should also account for plane ratio
1862 * once 64bpp pixel formats are supported.
1864 cdclk = skl_calc_cdclk(max_pixclk, vco);
1866 if (cdclk > dev_priv->max_cdclk_freq) {
1867 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1868 cdclk, dev_priv->max_cdclk_freq);
1872 intel_state->cdclk.logical.vco = vco;
1873 intel_state->cdclk.logical.cdclk = cdclk;
1875 if (!intel_state->active_crtcs) {
1876 cdclk = skl_calc_cdclk(0, vco);
1878 intel_state->cdclk.actual.vco = vco;
1879 intel_state->cdclk.actual.cdclk = cdclk;
1881 intel_state->cdclk.actual =
1882 intel_state->cdclk.logical;
1888 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1890 struct drm_i915_private *dev_priv = to_i915(state->dev);
1891 int max_pixclk = intel_max_pixel_rate(state);
1892 struct intel_atomic_state *intel_state =
1893 to_intel_atomic_state(state);
1896 if (IS_GEMINILAKE(dev_priv)) {
1897 cdclk = glk_calc_cdclk(max_pixclk);
1898 vco = glk_de_pll_vco(dev_priv, cdclk);
1900 cdclk = bxt_calc_cdclk(max_pixclk);
1901 vco = bxt_de_pll_vco(dev_priv, cdclk);
1904 if (cdclk > dev_priv->max_cdclk_freq) {
1905 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1906 cdclk, dev_priv->max_cdclk_freq);
1910 intel_state->cdclk.logical.vco = vco;
1911 intel_state->cdclk.logical.cdclk = cdclk;
1913 if (!intel_state->active_crtcs) {
1914 if (IS_GEMINILAKE(dev_priv)) {
1915 cdclk = glk_calc_cdclk(0);
1916 vco = glk_de_pll_vco(dev_priv, cdclk);
1918 cdclk = bxt_calc_cdclk(0);
1919 vco = bxt_de_pll_vco(dev_priv, cdclk);
1922 intel_state->cdclk.actual.vco = vco;
1923 intel_state->cdclk.actual.cdclk = cdclk;
1925 intel_state->cdclk.actual =
1926 intel_state->cdclk.logical;
1932 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
1934 int max_cdclk_freq = dev_priv->max_cdclk_freq;
1936 if (IS_GEMINILAKE(dev_priv))
1938 * FIXME: Limiting to 99% as a temporary workaround. See
1939 * glk_calc_cdclk() for details.
1941 return 2 * max_cdclk_freq * 99 / 100;
1942 else if (INTEL_INFO(dev_priv)->gen >= 9 ||
1943 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1944 return max_cdclk_freq;
1945 else if (IS_CHERRYVIEW(dev_priv))
1946 return max_cdclk_freq*95/100;
1947 else if (INTEL_INFO(dev_priv)->gen < 4)
1948 return 2*max_cdclk_freq*90/100;
1950 return max_cdclk_freq*90/100;
1954 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
1955 * @dev_priv: i915 device
1957 * Determine the maximum CDCLK frequency the platform supports, and also
1958 * derive the maximum dot clock frequency the maximum CDCLK frequency
1961 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
1963 if (IS_GEN9_BC(dev_priv)) {
1964 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
1967 vco = dev_priv->skl_preferred_vco_freq;
1968 WARN_ON(vco != 8100000 && vco != 8640000);
1971 * Use the lower (vco 8640) cdclk values as a
1972 * first guess. skl_calc_cdclk() will correct it
1973 * if the preferred vco is 8100 instead.
1975 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
1977 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
1979 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
1984 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
1985 } else if (IS_GEMINILAKE(dev_priv)) {
1986 dev_priv->max_cdclk_freq = 316800;
1987 } else if (IS_BROXTON(dev_priv)) {
1988 dev_priv->max_cdclk_freq = 624000;
1989 } else if (IS_BROADWELL(dev_priv)) {
1991 * FIXME with extra cooling we can allow
1992 * 540 MHz for ULX and 675 Mhz for ULT.
1993 * How can we know if extra cooling is
1994 * available? PCI ID, VTB, something else?
1996 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1997 dev_priv->max_cdclk_freq = 450000;
1998 else if (IS_BDW_ULX(dev_priv))
1999 dev_priv->max_cdclk_freq = 450000;
2000 else if (IS_BDW_ULT(dev_priv))
2001 dev_priv->max_cdclk_freq = 540000;
2003 dev_priv->max_cdclk_freq = 675000;
2004 } else if (IS_CHERRYVIEW(dev_priv)) {
2005 dev_priv->max_cdclk_freq = 320000;
2006 } else if (IS_VALLEYVIEW(dev_priv)) {
2007 dev_priv->max_cdclk_freq = 400000;
2009 /* otherwise assume cdclk is fixed */
2010 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2013 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2015 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2016 dev_priv->max_cdclk_freq);
2018 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2019 dev_priv->max_dotclk_freq);
2023 * intel_update_cdclk - Determine the current CDCLK frequency
2024 * @dev_priv: i915 device
2026 * Determine the current CDCLK frequency.
2028 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2030 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2032 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2033 dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
2034 dev_priv->cdclk.hw.ref);
2037 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2038 * Programmng [sic] note: bit[9:2] should be programmed to the number
2039 * of cdclk that generates 4MHz reference clock freq which is used to
2040 * generate GMBus clock. This will vary with the cdclk freq.
2042 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2043 I915_WRITE(GMBUSFREQ_VLV,
2044 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2047 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2050 int divider, fraction;
2052 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2062 rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2064 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2067 I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2068 return divider + fraction;
2071 static int pch_rawclk(struct drm_i915_private *dev_priv)
2073 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2076 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2078 /* RAWCLK_FREQ_VLV register updated from power well code */
2079 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2080 CCK_DISPLAY_REF_CLOCK_CONTROL);
2083 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2087 /* hrawclock is 1/4 the FSB frequency */
2088 clkcfg = I915_READ(CLKCFG);
2089 switch (clkcfg & CLKCFG_FSB_MASK) {
2090 case CLKCFG_FSB_400:
2092 case CLKCFG_FSB_533:
2094 case CLKCFG_FSB_667:
2096 case CLKCFG_FSB_800:
2098 case CLKCFG_FSB_1067:
2099 case CLKCFG_FSB_1067_ALT:
2101 case CLKCFG_FSB_1333:
2102 case CLKCFG_FSB_1333_ALT:
2110 * intel_update_rawclk - Determine the current RAWCLK frequency
2111 * @dev_priv: i915 device
2113 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2114 * frequency clock so this needs to done only once.
2116 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2119 if (HAS_PCH_CNP(dev_priv))
2120 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2121 else if (HAS_PCH_SPLIT(dev_priv))
2122 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2123 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2124 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2125 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2126 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2128 /* no rawclk on other platforms, or no need to know it */
2131 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2135 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2136 * @dev_priv: i915 device
2138 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2140 if (IS_CHERRYVIEW(dev_priv)) {
2141 dev_priv->display.set_cdclk = chv_set_cdclk;
2142 dev_priv->display.modeset_calc_cdclk =
2143 vlv_modeset_calc_cdclk;
2144 } else if (IS_VALLEYVIEW(dev_priv)) {
2145 dev_priv->display.set_cdclk = vlv_set_cdclk;
2146 dev_priv->display.modeset_calc_cdclk =
2147 vlv_modeset_calc_cdclk;
2148 } else if (IS_BROADWELL(dev_priv)) {
2149 dev_priv->display.set_cdclk = bdw_set_cdclk;
2150 dev_priv->display.modeset_calc_cdclk =
2151 bdw_modeset_calc_cdclk;
2152 } else if (IS_GEN9_LP(dev_priv)) {
2153 dev_priv->display.set_cdclk = bxt_set_cdclk;
2154 dev_priv->display.modeset_calc_cdclk =
2155 bxt_modeset_calc_cdclk;
2156 } else if (IS_GEN9_BC(dev_priv)) {
2157 dev_priv->display.set_cdclk = skl_set_cdclk;
2158 dev_priv->display.modeset_calc_cdclk =
2159 skl_modeset_calc_cdclk;
2162 if (IS_CANNONLAKE(dev_priv))
2163 dev_priv->display.get_cdclk = cnl_get_cdclk;
2164 else if (IS_GEN9_BC(dev_priv))
2165 dev_priv->display.get_cdclk = skl_get_cdclk;
2166 else if (IS_GEN9_LP(dev_priv))
2167 dev_priv->display.get_cdclk = bxt_get_cdclk;
2168 else if (IS_BROADWELL(dev_priv))
2169 dev_priv->display.get_cdclk = bdw_get_cdclk;
2170 else if (IS_HASWELL(dev_priv))
2171 dev_priv->display.get_cdclk = hsw_get_cdclk;
2172 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2173 dev_priv->display.get_cdclk = vlv_get_cdclk;
2174 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2175 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2176 else if (IS_GEN5(dev_priv))
2177 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2178 else if (IS_GM45(dev_priv))
2179 dev_priv->display.get_cdclk = gm45_get_cdclk;
2180 else if (IS_G45(dev_priv))
2181 dev_priv->display.get_cdclk = g33_get_cdclk;
2182 else if (IS_I965GM(dev_priv))
2183 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2184 else if (IS_I965G(dev_priv))
2185 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2186 else if (IS_PINEVIEW(dev_priv))
2187 dev_priv->display.get_cdclk = pnv_get_cdclk;
2188 else if (IS_G33(dev_priv))
2189 dev_priv->display.get_cdclk = g33_get_cdclk;
2190 else if (IS_I945GM(dev_priv))
2191 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2192 else if (IS_I945G(dev_priv))
2193 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2194 else if (IS_I915GM(dev_priv))
2195 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2196 else if (IS_I915G(dev_priv))
2197 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2198 else if (IS_I865G(dev_priv))
2199 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2200 else if (IS_I85X(dev_priv))
2201 dev_priv->display.get_cdclk = i85x_get_cdclk;
2202 else if (IS_I845G(dev_priv))
2203 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2205 WARN(!IS_I830(dev_priv),
2206 "Unknown platform. Assuming 133 MHz CDCLK\n");
2207 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;