drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G4X(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 320                 cdclk_state->cdclk = 133333;
 321                 break;
 322         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 323                 cdclk_state->cdclk = 166667;
 324                 break;
 325         }
 326 }
 327
 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 329                              struct intel_cdclk_state *cdclk_state)
 330 {
 331         struct pci_dev *pdev = dev_priv->drm.pdev;
 332         static const uint8_t div_3200[] = { 16, 10,  8 };
 333         static const uint8_t div_4000[] = { 20, 12, 10 };
 334         static const uint8_t div_5333[] = { 24, 16, 14 };
 335         const uint8_t *div_table;
 336         unsigned int cdclk_sel;
 337         uint16_t tmp = 0;
 338
 339         cdclk_state->vco = intel_hpll_vco(dev_priv);
 340
 341         pci_read_config_word(pdev, GCFGC, &tmp);
 342
 343         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 344
 345         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 346                 goto fail;
 347
 348         switch (cdclk_state->vco) {
 349         case 3200000:
 350                 div_table = div_3200;
 351                 break;
 352         case 4000000:
 353                 div_table = div_4000;
 354                 break;
 355         case 5333333:
 356                 div_table = div_5333;
 357                 break;
 358         default:
 359                 goto fail;
 360         }
 361
 362         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 363                                                div_table[cdclk_sel]);
 364         return;
 365
 366 fail:
 367         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 368                   cdclk_state->vco, tmp);
 369         cdclk_state->cdclk = 200000;
 370 }
 371
 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 373                            struct intel_cdclk_state *cdclk_state)
 374 {
 375         struct pci_dev *pdev = dev_priv->drm.pdev;
 376         unsigned int cdclk_sel;
 377         uint16_t tmp = 0;
 378
 379         cdclk_state->vco = intel_hpll_vco(dev_priv);
 380
 381         pci_read_config_word(pdev, GCFGC, &tmp);
 382
 383         cdclk_sel = (tmp >> 12) & 0x1;
 384
 385         switch (cdclk_state->vco) {
 386         case 2666667:
 387         case 4000000:
 388         case 5333333:
 389                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 390                 break;
 391         case 3200000:
 392                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 393                 break;
 394         default:
 395                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 396                           cdclk_state->vco, tmp);
 397                 cdclk_state->cdclk = 222222;
 398                 break;
 399         }
 400 }
 401
 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 403                           struct intel_cdclk_state *cdclk_state)
 404 {
 405         uint32_t lcpll = I915_READ(LCPLL_CTL);
 406         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 407
 408         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 409                 cdclk_state->cdclk = 800000;
 410         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 411                 cdclk_state->cdclk = 450000;
 412         else if (freq == LCPLL_CLK_FREQ_450)
 413                 cdclk_state->cdclk = 450000;
 414         else if (IS_HSW_ULT(dev_priv))
 415                 cdclk_state->cdclk = 337500;
 416         else
 417                 cdclk_state->cdclk = 540000;
 418 }
 419
 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv,
 421                           int max_pixclk)
 422 {
 423         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 424                 333333 : 320000;
 425         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
 426
 427         /*
 428          * We seem to get an unstable or solid color picture at 200MHz.
 429          * Not sure what's wrong. For now use 200MHz only when all pipes
 430          * are off.
 431          */
 432         if (!IS_CHERRYVIEW(dev_priv) &&
 433             max_pixclk > freq_320*limit/100)
 434                 return 400000;
 435         else if (max_pixclk > 266667*limit/100)
 436                 return freq_320;
 437         else if (max_pixclk > 0)
 438                 return 266667;
 439         else
 440                 return 200000;
 441 }
 442
 443 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 444                           struct intel_cdclk_state *cdclk_state)
 445 {
 446         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 447         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 448                                                CCK_DISPLAY_CLOCK_CONTROL,
 449                                                cdclk_state->vco);
 450 }
 451
 452 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 453 {
 454         unsigned int credits, default_credits;
 455
 456         if (IS_CHERRYVIEW(dev_priv))
 457                 default_credits = PFI_CREDIT(12);
 458         else
 459                 default_credits = PFI_CREDIT(8);
 460
 461         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 462                 /* CHV suggested value is 31 or 63 */
 463                 if (IS_CHERRYVIEW(dev_priv))
 464                         credits = PFI_CREDIT_63;
 465                 else
 466                         credits = PFI_CREDIT(15);
 467         } else {
 468                 credits = default_credits;
 469         }
 470
 471         /*
 472          * WA - write default credits before re-programming
 473          * FIXME: should we also set the resend bit here?
 474          */
 475         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 476                    default_credits);
 477
 478         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 479                    credits | PFI_CREDIT_RESEND);
 480
 481         /*
 482          * FIXME is this guaranteed to clear
 483          * immediately or should we poll for it?
 484          */
 485         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 486 }
 487
 488 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 489 {
 490         u32 val, cmd;
 491
 492         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 493                 cmd = 2;
 494         else if (cdclk == 266667)
 495                 cmd = 1;
 496         else
 497                 cmd = 0;
 498
 499         mutex_lock(&dev_priv->rps.hw_lock);
 500         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 501         val &= ~DSPFREQGUAR_MASK;
 502         val |= (cmd << DSPFREQGUAR_SHIFT);
 503         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 504         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 505                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 506                      50)) {
 507                 DRM_ERROR("timed out waiting for CDclk change\n");
 508         }
 509         mutex_unlock(&dev_priv->rps.hw_lock);
 510
 511         mutex_lock(&dev_priv->sb_lock);
 512
 513         if (cdclk == 400000) {
 514                 u32 divider;
 515
 516                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 517                                             cdclk) - 1;
 518
 519                 /* adjust cdclk divider */
 520                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 521                 val &= ~CCK_FREQUENCY_VALUES;
 522                 val |= divider;
 523                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 524
 525                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 526                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 527                              50))
 528                         DRM_ERROR("timed out waiting for CDclk change\n");
 529         }
 530
 531         /* adjust self-refresh exit latency value */
 532         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 533         val &= ~0x7f;
 534
 535         /*
 536          * For high bandwidth configs, we set a higher latency in the bunit
 537          * so that the core display fetch happens in time to avoid underruns.
 538          */
 539         if (cdclk == 400000)
 540                 val |= 4500 / 250; /* 4.5 usec */
 541         else
 542                 val |= 3000 / 250; /* 3.0 usec */
 543         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 544
 545         mutex_unlock(&dev_priv->sb_lock);
 546
 547         intel_update_cdclk(dev_priv);
 548 }
 549
 550 static void chv_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 551 {
 552         u32 val, cmd;
 553
 554         switch (cdclk) {
 555         case 333333:
 556         case 320000:
 557         case 266667:
 558         case 200000:
 559                 break;
 560         default:
 561                 MISSING_CASE(cdclk);
 562                 return;
 563         }
 564
 565         /*
 566          * Specs are full of misinformation, but testing on actual
 567          * hardware has shown that we just need to write the desired
 568          * CCK divider into the Punit register.
 569          */
 570         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 571
 572         mutex_lock(&dev_priv->rps.hw_lock);
 573         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 574         val &= ~DSPFREQGUAR_MASK_CHV;
 575         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 576         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 577         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 578                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 579                      50)) {
 580                 DRM_ERROR("timed out waiting for CDclk change\n");
 581         }
 582         mutex_unlock(&dev_priv->rps.hw_lock);
 583
 584         intel_update_cdclk(dev_priv);
 585 }
 586
 587 static int bdw_calc_cdclk(int max_pixclk)
 588 {
 589         if (max_pixclk > 540000)
 590                 return 675000;
 591         else if (max_pixclk > 450000)
 592                 return 540000;
 593         else if (max_pixclk > 337500)
 594                 return 450000;
 595         else
 596                 return 337500;
 597 }
 598
 599 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 600                           struct intel_cdclk_state *cdclk_state)
 601 {
 602         uint32_t lcpll = I915_READ(LCPLL_CTL);
 603         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 604
 605         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 606                 cdclk_state->cdclk = 800000;
 607         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 608                 cdclk_state->cdclk = 450000;
 609         else if (freq == LCPLL_CLK_FREQ_450)
 610                 cdclk_state->cdclk = 450000;
 611         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 612                 cdclk_state->cdclk = 540000;
 613         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 614                 cdclk_state->cdclk = 337500;
 615         else
 616                 cdclk_state->cdclk = 675000;
 617 }
 618
 619 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 620 {
 621         uint32_t val, data;
 622         int ret;
 623
 624         if (WARN((I915_READ(LCPLL_CTL) &
 625                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 626                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 627                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 628                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 629                  "trying to change cdclk frequency with cdclk not enabled\n"))
 630                 return;
 631
 632         mutex_lock(&dev_priv->rps.hw_lock);
 633         ret = sandybridge_pcode_write(dev_priv,
 634                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 635         mutex_unlock(&dev_priv->rps.hw_lock);
 636         if (ret) {
 637                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 638                 return;
 639         }
 640
 641         val = I915_READ(LCPLL_CTL);
 642         val |= LCPLL_CD_SOURCE_FCLK;
 643         I915_WRITE(LCPLL_CTL, val);
 644
 645         if (wait_for_us(I915_READ(LCPLL_CTL) &
 646                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
 647                 DRM_ERROR("Switching to FCLK failed\n");
 648
 649         val = I915_READ(LCPLL_CTL);
 650         val &= ~LCPLL_CLK_FREQ_MASK;
 651
 652         switch (cdclk) {
 653         case 450000:
 654                 val |= LCPLL_CLK_FREQ_450;
 655                 data = 0;
 656                 break;
 657         case 540000:
 658                 val |= LCPLL_CLK_FREQ_54O_BDW;
 659                 data = 1;
 660                 break;
 661         case 337500:
 662                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 663                 data = 2;
 664                 break;
 665         case 675000:
 666                 val |= LCPLL_CLK_FREQ_675_BDW;
 667                 data = 3;
 668                 break;
 669         default:
 670                 WARN(1, "invalid cdclk frequency\n");
 671                 return;
 672         }
 673
 674         I915_WRITE(LCPLL_CTL, val);
 675
 676         val = I915_READ(LCPLL_CTL);
 677         val &= ~LCPLL_CD_SOURCE_FCLK;
 678         I915_WRITE(LCPLL_CTL, val);
 679
 680         if (wait_for_us((I915_READ(LCPLL_CTL) &
 681                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 682                 DRM_ERROR("Switching back to LCPLL failed\n");
 683
 684         mutex_lock(&dev_priv->rps.hw_lock);
 685         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
 686         mutex_unlock(&dev_priv->rps.hw_lock);
 687
 688         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 689
 690         intel_update_cdclk(dev_priv);
 691
 692         WARN(cdclk != dev_priv->cdclk.hw.cdclk,
 693              "cdclk requested %d kHz but got %d kHz\n",
 694              cdclk, dev_priv->cdclk.hw.cdclk);
 695 }
 696
 697 static int skl_calc_cdclk(int max_pixclk, int vco)
 698 {
 699         if (vco == 8640000) {
 700                 if (max_pixclk > 540000)
 701                         return 617143;
 702                 else if (max_pixclk > 432000)
 703                         return 540000;
 704                 else if (max_pixclk > 308571)
 705                         return 432000;
 706                 else
 707                         return 308571;
 708         } else {
 709                 if (max_pixclk > 540000)
 710                         return 675000;
 711                 else if (max_pixclk > 450000)
 712                         return 540000;
 713                 else if (max_pixclk > 337500)
 714                         return 450000;
 715                 else
 716                         return 337500;
 717         }
 718 }
 719
 720 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 721                              struct intel_cdclk_state *cdclk_state)
 722 {
 723         u32 val;
 724
 725         cdclk_state->ref = 24000;
 726         cdclk_state->vco = 0;
 727
 728         val = I915_READ(LCPLL1_CTL);
 729         if ((val & LCPLL_PLL_ENABLE) == 0)
 730                 return;
 731
 732         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 733                 return;
 734
 735         val = I915_READ(DPLL_CTRL1);
 736
 737         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 738                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 739                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 740                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 741                 return;
 742
 743         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 744         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 745         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 746         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 747         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 748                 cdclk_state->vco = 8100000;
 749                 break;
 750         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 751         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 752                 cdclk_state->vco = 8640000;
 753                 break;
 754         default:
 755                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 756                 break;
 757         }
 758 }
 759
 760 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 761                           struct intel_cdclk_state *cdclk_state)
 762 {
 763         u32 cdctl;
 764
 765         skl_dpll0_update(dev_priv, cdclk_state);
 766
 767         cdclk_state->cdclk = cdclk_state->ref;
 768
 769         if (cdclk_state->vco == 0)
 770                 return;
 771
 772         cdctl = I915_READ(CDCLK_CTL);
 773
 774         if (cdclk_state->vco == 8640000) {
 775                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 776                 case CDCLK_FREQ_450_432:
 777                         cdclk_state->cdclk = 432000;
 778                         break;
 779                 case CDCLK_FREQ_337_308:
 780                         cdclk_state->cdclk = 308571;
 781                         break;
 782                 case CDCLK_FREQ_540:
 783                         cdclk_state->cdclk = 540000;
 784                         break;
 785                 case CDCLK_FREQ_675_617:
 786                         cdclk_state->cdclk = 617143;
 787                         break;
 788                 default:
 789                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 790                         break;
 791                 }
 792         } else {
 793                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 794                 case CDCLK_FREQ_450_432:
 795                         cdclk_state->cdclk = 450000;
 796                         break;
 797                 case CDCLK_FREQ_337_308:
 798                         cdclk_state->cdclk = 337500;
 799                         break;
 800                 case CDCLK_FREQ_540:
 801                         cdclk_state->cdclk = 540000;
 802                         break;
 803                 case CDCLK_FREQ_675_617:
 804                         cdclk_state->cdclk = 675000;
 805                         break;
 806                 default:
 807                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 808                         break;
 809                 }
 810         }
 811 }
 812
 813 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 814 static int skl_cdclk_decimal(int cdclk)
 815 {
 816         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 817 }
 818
 819 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 820                                         int vco)
 821 {
 822         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 823
 824         dev_priv->skl_preferred_vco_freq = vco;
 825
 826         if (changed)
 827                 intel_update_max_cdclk(dev_priv);
 828 }
 829
 830 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 831 {
 832         int min_cdclk = skl_calc_cdclk(0, vco);
 833         u32 val;
 834
 835         WARN_ON(vco != 8100000 && vco != 8640000);
 836
 837         /* select the minimum CDCLK before enabling DPLL 0 */
 838         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
 839         I915_WRITE(CDCLK_CTL, val);
 840         POSTING_READ(CDCLK_CTL);
 841
 842         /*
 843          * We always enable DPLL0 with the lowest link rate possible, but still
 844          * taking into account the VCO required to operate the eDP panel at the
 845          * desired frequency. The usual DP link rates operate with a VCO of
 846          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 847          * The modeset code is responsible for the selection of the exact link
 848          * rate later on, with the constraint of choosing a frequency that
 849          * works with vco.
 850          */
 851         val = I915_READ(DPLL_CTRL1);
 852
 853         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 854                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 855         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 856         if (vco == 8640000)
 857                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 858                                             SKL_DPLL0);
 859         else
 860                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 861                                             SKL_DPLL0);
 862
 863         I915_WRITE(DPLL_CTRL1, val);
 864         POSTING_READ(DPLL_CTRL1);
 865
 866         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 867
 868         if (intel_wait_for_register(dev_priv,
 869                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 870                                     5))
 871                 DRM_ERROR("DPLL0 not locked\n");
 872
 873         dev_priv->cdclk.hw.vco = vco;
 874
 875         /* We'll want to keep using the current vco from now on. */
 876         skl_set_preferred_cdclk_vco(dev_priv, vco);
 877 }
 878
 879 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 880 {
 881         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 882         if (intel_wait_for_register(dev_priv,
 883                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 884                                    1))
 885                 DRM_ERROR("Couldn't disable DPLL0\n");
 886
 887         dev_priv->cdclk.hw.vco = 0;
 888 }
 889
 890 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 891                           int cdclk, int vco)
 892 {
 893         u32 freq_select, pcu_ack;
 894         int ret;
 895
 896         WARN_ON((cdclk == 24000) != (vco == 0));
 897
 898         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n",
 899                          cdclk, vco);
 900
 901         mutex_lock(&dev_priv->rps.hw_lock);
 902         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 903                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
 904                                 SKL_CDCLK_READY_FOR_CHANGE,
 905                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
 906         mutex_unlock(&dev_priv->rps.hw_lock);
 907         if (ret) {
 908                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
 909                           ret);
 910                 return;
 911         }
 912
 913         /* set CDCLK_CTL */
 914         switch (cdclk) {
 915         case 450000:
 916         case 432000:
 917                 freq_select = CDCLK_FREQ_450_432;
 918                 pcu_ack = 1;
 919                 break;
 920         case 540000:
 921                 freq_select = CDCLK_FREQ_540;
 922                 pcu_ack = 2;
 923                 break;
 924         case 308571:
 925         case 337500:
 926         default:
 927                 freq_select = CDCLK_FREQ_337_308;
 928                 pcu_ack = 0;
 929                 break;
 930         case 617143:
 931         case 675000:
 932                 freq_select = CDCLK_FREQ_675_617;
 933                 pcu_ack = 3;
 934                 break;
 935         }
 936
 937         if (dev_priv->cdclk.hw.vco != 0 &&
 938             dev_priv->cdclk.hw.vco != vco)
 939                 skl_dpll0_disable(dev_priv);
 940
 941         if (dev_priv->cdclk.hw.vco != vco)
 942                 skl_dpll0_enable(dev_priv, vco);
 943
 944         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
 945         POSTING_READ(CDCLK_CTL);
 946
 947         /* inform PCU of the change */
 948         mutex_lock(&dev_priv->rps.hw_lock);
 949         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
 950         mutex_unlock(&dev_priv->rps.hw_lock);
 951
 952         intel_update_cdclk(dev_priv);
 953 }
 954
 955 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 956 {
 957         uint32_t cdctl, expected;
 958
 959         /*
 960          * check if the pre-os initialized the display
 961          * There is SWF18 scratchpad register defined which is set by the
 962          * pre-os which can be used by the OS drivers to check the status
 963          */
 964         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
 965                 goto sanitize;
 966
 967         intel_update_cdclk(dev_priv);
 968         /* Is PLL enabled and locked ? */
 969         if (dev_priv->cdclk.hw.vco == 0 ||
 970             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
 971                 goto sanitize;
 972
 973         /* DPLL okay; verify the cdclock
 974          *
 975          * Noticed in some instances that the freq selection is correct but
 976          * decimal part is programmed wrong from BIOS where pre-os does not
 977          * enable display. Verify the same as well.
 978          */
 979         cdctl = I915_READ(CDCLK_CTL);
 980         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
 981                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
 982         if (cdctl == expected)
 983                 /* All well; nothing to sanitize */
 984                 return;
 985
 986 sanitize:
 987         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
 988
 989         /* force cdclk programming */
 990         dev_priv->cdclk.hw.cdclk = 0;
 991         /* force full PLL disable + enable */
 992         dev_priv->cdclk.hw.vco = -1;
 993 }
 994
 995 /**
 996  * skl_init_cdclk - Initialize CDCLK on SKL
 997  * @dev_priv: i915 device
 998  *
 999  * Initialize CDCLK for SKL and derivatives. This is generally
1000  * done only during the display core initialization sequence,
1001  * after which the DMC will take care of turning CDCLK off/on
1002  * as needed.
1003  */
1004 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1005 {
1006         int cdclk, vco;
1007
1008         skl_sanitize_cdclk(dev_priv);
1009
1010         if (dev_priv->cdclk.hw.cdclk != 0 &&
1011             dev_priv->cdclk.hw.vco != 0) {
1012                 /*
1013                  * Use the current vco as our initial
1014                  * guess as to what the preferred vco is.
1015                  */
1016                 if (dev_priv->skl_preferred_vco_freq == 0)
1017                         skl_set_preferred_cdclk_vco(dev_priv,
1018                                                     dev_priv->cdclk.hw.vco);
1019                 return;
1020         }
1021
1022         vco = dev_priv->skl_preferred_vco_freq;
1023         if (vco == 0)
1024                 vco = 8100000;
1025         cdclk = skl_calc_cdclk(0, vco);
1026
1027         skl_set_cdclk(dev_priv, cdclk, vco);
1028 }
1029
1030 /**
1031  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1032  * @dev_priv: i915 device
1033  *
1034  * Uninitialize CDCLK for SKL and derivatives. This is done only
1035  * during the display core uninitialization sequence.
1036  */
1037 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1038 {
1039         skl_set_cdclk(dev_priv, dev_priv->cdclk.hw.ref, 0);
1040 }
1041
1042 static int bxt_calc_cdclk(int max_pixclk)
1043 {
1044         if (max_pixclk > 576000)
1045                 return 624000;
1046         else if (max_pixclk > 384000)
1047                 return 576000;
1048         else if (max_pixclk > 288000)
1049                 return 384000;
1050         else if (max_pixclk > 144000)
1051                 return 288000;
1052         else
1053                 return 144000;
1054 }
1055
1056 static int glk_calc_cdclk(int max_pixclk)
1057 {
1058         if (max_pixclk > 2 * 158400)
1059                 return 316800;
1060         else if (max_pixclk > 2 * 79200)
1061                 return 158400;
1062         else
1063                 return 79200;
1064 }
1065
1066 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1067 {
1068         int ratio;
1069
1070         if (cdclk == dev_priv->cdclk.hw.ref)
1071                 return 0;
1072
1073         switch (cdclk) {
1074         default:
1075                 MISSING_CASE(cdclk);
1076         case 144000:
1077         case 288000:
1078         case 384000:
1079         case 576000:
1080                 ratio = 60;
1081                 break;
1082         case 624000:
1083                 ratio = 65;
1084                 break;
1085         }
1086
1087         return dev_priv->cdclk.hw.ref * ratio;
1088 }
1089
1090 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1091 {
1092         int ratio;
1093
1094         if (cdclk == dev_priv->cdclk.hw.ref)
1095                 return 0;
1096
1097         switch (cdclk) {
1098         default:
1099                 MISSING_CASE(cdclk);
1100         case  79200:
1101         case 158400:
1102         case 316800:
1103                 ratio = 33;
1104                 break;
1105         }
1106
1107         return dev_priv->cdclk.hw.ref * ratio;
1108 }
1109
1110 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1111                               struct intel_cdclk_state *cdclk_state)
1112 {
1113         u32 val;
1114
1115         cdclk_state->ref = 19200;
1116         cdclk_state->vco = 0;
1117
1118         val = I915_READ(BXT_DE_PLL_ENABLE);
1119         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1120                 return;
1121
1122         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1123                 return;
1124
1125         val = I915_READ(BXT_DE_PLL_CTL);
1126         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1127 }
1128
1129 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1130                           struct intel_cdclk_state *cdclk_state)
1131 {
1132         u32 divider;
1133         int div;
1134
1135         bxt_de_pll_update(dev_priv, cdclk_state);
1136
1137         cdclk_state->cdclk = cdclk_state->ref;
1138
1139         if (cdclk_state->vco == 0)
1140                 return;
1141
1142         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1143
1144         switch (divider) {
1145         case BXT_CDCLK_CD2X_DIV_SEL_1:
1146                 div = 2;
1147                 break;
1148         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1149                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1150                 div = 3;
1151                 break;
1152         case BXT_CDCLK_CD2X_DIV_SEL_2:
1153                 div = 4;
1154                 break;
1155         case BXT_CDCLK_CD2X_DIV_SEL_4:
1156                 div = 8;
1157                 break;
1158         default:
1159                 MISSING_CASE(divider);
1160                 return;
1161         }
1162
1163         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1164 }
1165
1166 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1167 {
1168         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1169
1170         /* Timeout 200us */
1171         if (intel_wait_for_register(dev_priv,
1172                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1173                                     1))
1174                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1175
1176         dev_priv->cdclk.hw.vco = 0;
1177 }
1178
1179 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1180 {
1181         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1182         u32 val;
1183
1184         val = I915_READ(BXT_DE_PLL_CTL);
1185         val &= ~BXT_DE_PLL_RATIO_MASK;
1186         val |= BXT_DE_PLL_RATIO(ratio);
1187         I915_WRITE(BXT_DE_PLL_CTL, val);
1188
1189         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1190
1191         /* Timeout 200us */
1192         if (intel_wait_for_register(dev_priv,
1193                                     BXT_DE_PLL_ENABLE,
1194                                     BXT_DE_PLL_LOCK,
1195                                     BXT_DE_PLL_LOCK,
1196                                     1))
1197                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1198
1199         dev_priv->cdclk.hw.vco = vco;
1200 }
1201
1202 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1203                           int cdclk, int vco)
1204 {
1205         u32 val, divider;
1206         int ret;
1207
1208         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n",
1209                          cdclk, vco);
1210
1211         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1212         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1213         case 8:
1214                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1215                 break;
1216         case 4:
1217                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1218                 break;
1219         case 3:
1220                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1221                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1222                 break;
1223         case 2:
1224                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1225                 break;
1226         default:
1227                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1228                 WARN_ON(vco != 0);
1229
1230                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1231                 break;
1232         }
1233
1234         /* Inform power controller of upcoming frequency change */
1235         mutex_lock(&dev_priv->rps.hw_lock);
1236         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1237                                       0x80000000);
1238         mutex_unlock(&dev_priv->rps.hw_lock);
1239
1240         if (ret) {
1241                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1242                           ret, cdclk);
1243                 return;
1244         }
1245
1246         if (dev_priv->cdclk.hw.vco != 0 &&
1247             dev_priv->cdclk.hw.vco != vco)
1248                 bxt_de_pll_disable(dev_priv);
1249
1250         if (dev_priv->cdclk.hw.vco != vco)
1251                 bxt_de_pll_enable(dev_priv, vco);
1252
1253         val = divider | skl_cdclk_decimal(cdclk);
1254         /*
1255          * FIXME if only the cd2x divider needs changing, it could be done
1256          * without shutting off the pipe (if only one pipe is active).
1257          */
1258         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1259         /*
1260          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1261          * enable otherwise.
1262          */
1263         if (cdclk >= 500000)
1264                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1265         I915_WRITE(CDCLK_CTL, val);
1266
1267         mutex_lock(&dev_priv->rps.hw_lock);
1268         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1269                                       DIV_ROUND_UP(cdclk, 25000));
1270         mutex_unlock(&dev_priv->rps.hw_lock);
1271
1272         if (ret) {
1273                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1274                           ret, cdclk);
1275                 return;
1276         }
1277
1278         intel_update_cdclk(dev_priv);
1279 }
1280
1281 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1282 {
1283         u32 cdctl, expected;
1284
1285         intel_update_cdclk(dev_priv);
1286
1287         if (dev_priv->cdclk.hw.vco == 0 ||
1288             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1289                 goto sanitize;
1290
1291         /* DPLL okay; verify the cdclock
1292          *
1293          * Some BIOS versions leave an incorrect decimal frequency value and
1294          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1295          * so sanitize this register.
1296          */
1297         cdctl = I915_READ(CDCLK_CTL);
1298         /*
1299          * Let's ignore the pipe field, since BIOS could have configured the
1300          * dividers both synching to an active pipe, or asynchronously
1301          * (PIPE_NONE).
1302          */
1303         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1304
1305         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1306                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1307         /*
1308          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1309          * enable otherwise.
1310          */
1311         if (dev_priv->cdclk.hw.cdclk >= 500000)
1312                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1313
1314         if (cdctl == expected)
1315                 /* All well; nothing to sanitize */
1316                 return;
1317
1318 sanitize:
1319         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1320
1321         /* force cdclk programming */
1322         dev_priv->cdclk.hw.cdclk = 0;
1323
1324         /* force full PLL disable + enable */
1325         dev_priv->cdclk.hw.vco = -1;
1326 }
1327
1328 /**
1329  * bxt_init_cdclk - Initialize CDCLK on BXT
1330  * @dev_priv: i915 device
1331  *
1332  * Initialize CDCLK for BXT and derivatives. This is generally
1333  * done only during the display core initialization sequence,
1334  * after which the DMC will take care of turning CDCLK off/on
1335  * as needed.
1336  */
1337 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1338 {
1339         int cdclk, vco;
1340
1341         bxt_sanitize_cdclk(dev_priv);
1342
1343         if (dev_priv->cdclk.hw.cdclk != 0 &&
1344             dev_priv->cdclk.hw.vco != 0)
1345                 return;
1346
1347         /*
1348          * FIXME:
1349          * - The initial CDCLK needs to be read from VBT.
1350          *   Need to make this change after VBT has changes for BXT.
1351          */
1352         if (IS_GEMINILAKE(dev_priv)) {
1353                 cdclk = glk_calc_cdclk(0);
1354                 vco = glk_de_pll_vco(dev_priv, cdclk);
1355         } else {
1356                 cdclk = bxt_calc_cdclk(0);
1357                 vco = bxt_de_pll_vco(dev_priv, cdclk);
1358         }
1359
1360         bxt_set_cdclk(dev_priv, cdclk, vco);
1361 }
1362
1363 /**
1364  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1365  * @dev_priv: i915 device
1366  *
1367  * Uninitialize CDCLK for BXT and derivatives. This is done only
1368  * during the display core uninitialization sequence.
1369  */
1370 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1371 {
1372         bxt_set_cdclk(dev_priv, dev_priv->cdclk.hw.ref, 0);
1373 }
1374
1375 /**
1376  * intel_cdclk_state_compare - Determine if two CDCLK states differ
1377  * @a: first CDCLK state
1378  * @b: second CDCLK state
1379  *
1380  * Returns:
1381  * True if the CDCLK states are identical, false if they differ.
1382  */
1383 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1384                                const struct intel_cdclk_state *b)
1385 {
1386         return memcmp(a, b, sizeof(*a)) == 0;
1387 }
1388
1389 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
1390                                           int pixel_rate)
1391 {
1392         struct drm_i915_private *dev_priv =
1393                 to_i915(crtc_state->base.crtc->dev);
1394
1395         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1396         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1397                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
1398
1399         /* BSpec says "Do not use DisplayPort with CDCLK less than
1400          * 432 MHz, audio enabled, port width x4, and link rate
1401          * HBR2 (5.4 GHz), or else there may be audio corruption or
1402          * screen corruption."
1403          */
1404         if (intel_crtc_has_dp_encoder(crtc_state) &&
1405             crtc_state->has_audio &&
1406             crtc_state->port_clock >= 540000 &&
1407             crtc_state->lane_count == 4)
1408                 pixel_rate = max(432000, pixel_rate);
1409
1410         return pixel_rate;
1411 }
1412
1413 /* compute the max rate for new configuration */
1414 static int intel_max_pixel_rate(struct drm_atomic_state *state)
1415 {
1416         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1417         struct drm_i915_private *dev_priv = to_i915(state->dev);
1418         struct drm_crtc *crtc;
1419         struct drm_crtc_state *cstate;
1420         struct intel_crtc_state *crtc_state;
1421         unsigned int max_pixel_rate = 0, i;
1422         enum pipe pipe;
1423
1424         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
1425                sizeof(intel_state->min_pixclk));
1426
1427         for_each_crtc_in_state(state, crtc, cstate, i) {
1428                 int pixel_rate;
1429
1430                 crtc_state = to_intel_crtc_state(cstate);
1431                 if (!crtc_state->base.enable) {
1432                         intel_state->min_pixclk[i] = 0;
1433                         continue;
1434                 }
1435
1436                 pixel_rate = crtc_state->pixel_rate;
1437
1438                 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
1439                         pixel_rate =
1440                                 bdw_adjust_min_pipe_pixel_rate(crtc_state,
1441                                                                pixel_rate);
1442
1443                 intel_state->min_pixclk[i] = pixel_rate;
1444         }
1445
1446         for_each_pipe(dev_priv, pipe)
1447                 max_pixel_rate = max(intel_state->min_pixclk[pipe],
1448                                      max_pixel_rate);
1449
1450         return max_pixel_rate;
1451 }
1452
1453 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1454 {
1455         struct drm_i915_private *dev_priv = to_i915(state->dev);
1456         int max_pixclk = intel_max_pixel_rate(state);
1457         struct intel_atomic_state *intel_state =
1458                 to_intel_atomic_state(state);
1459         int cdclk;
1460
1461         cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
1462
1463         if (cdclk > dev_priv->max_cdclk_freq) {
1464                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1465                               cdclk, dev_priv->max_cdclk_freq);
1466                 return -EINVAL;
1467         }
1468
1469         intel_state->cdclk.logical.cdclk = cdclk;
1470
1471         if (!intel_state->active_crtcs) {
1472                 cdclk = vlv_calc_cdclk(dev_priv, 0);
1473
1474                 intel_state->cdclk.actual.cdclk = cdclk;
1475         } else {
1476                 intel_state->cdclk.actual =
1477                         intel_state->cdclk.logical;
1478         }
1479
1480         return 0;
1481 }
1482
1483 static void vlv_modeset_commit_cdclk(struct drm_atomic_state *old_state)
1484 {
1485         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
1486         unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
1487
1488         /*
1489          * FIXME: We can end up here with all power domains off, yet
1490          * with a CDCLK frequency other than the minimum. To account
1491          * for this take the PIPE-A power domain, which covers the HW
1492          * blocks needed for the following programming. This can be
1493          * removed once it's guaranteed that we get here either with
1494          * the minimum CDCLK set, or the required power domains
1495          * enabled.
1496          */
1497         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
1498
1499         if (IS_CHERRYVIEW(dev_priv))
1500                 chv_set_cdclk(dev_priv, req_cdclk);
1501         else
1502                 vlv_set_cdclk(dev_priv, req_cdclk);
1503
1504         vlv_program_pfi_credits(dev_priv);
1505
1506         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
1507 }
1508
1509 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(state->dev);
1512         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1513         int max_pixclk = intel_max_pixel_rate(state);
1514         int cdclk;
1515
1516         /*
1517          * FIXME should also account for plane ratio
1518          * once 64bpp pixel formats are supported.
1519          */
1520         cdclk = bdw_calc_cdclk(max_pixclk);
1521
1522         if (cdclk > dev_priv->max_cdclk_freq) {
1523                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1524                               cdclk, dev_priv->max_cdclk_freq);
1525                 return -EINVAL;
1526         }
1527
1528         intel_state->cdclk.logical.cdclk = cdclk;
1529
1530         if (!intel_state->active_crtcs) {
1531                 cdclk = bdw_calc_cdclk(0);
1532
1533                 intel_state->cdclk.actual.cdclk = cdclk;
1534         } else {
1535                 intel_state->cdclk.actual =
1536                         intel_state->cdclk.logical;
1537         }
1538
1539         return 0;
1540 }
1541
1542 static void bdw_modeset_commit_cdclk(struct drm_atomic_state *old_state)
1543 {
1544         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
1545         unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
1546
1547         bdw_set_cdclk(dev_priv, req_cdclk);
1548 }
1549
1550 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1551 {
1552         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1553         struct drm_i915_private *dev_priv = to_i915(state->dev);
1554         const int max_pixclk = intel_max_pixel_rate(state);
1555         int cdclk, vco;
1556
1557         vco = intel_state->cdclk.logical.vco;
1558         if (!vco)
1559                 vco = dev_priv->skl_preferred_vco_freq;
1560
1561         /*
1562          * FIXME should also account for plane ratio
1563          * once 64bpp pixel formats are supported.
1564          */
1565         cdclk = skl_calc_cdclk(max_pixclk, vco);
1566
1567         if (cdclk > dev_priv->max_cdclk_freq) {
1568                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1569                               cdclk, dev_priv->max_cdclk_freq);
1570                 return -EINVAL;
1571         }
1572
1573         intel_state->cdclk.logical.vco = vco;
1574         intel_state->cdclk.logical.cdclk = cdclk;
1575
1576         if (!intel_state->active_crtcs) {
1577                 cdclk = skl_calc_cdclk(0, vco);
1578
1579                 intel_state->cdclk.actual.vco = vco;
1580                 intel_state->cdclk.actual.cdclk = cdclk;
1581         } else {
1582                 intel_state->cdclk.actual =
1583                         intel_state->cdclk.logical;
1584         }
1585
1586         return 0;
1587 }
1588
1589 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
1590 {
1591         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
1592         unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
1593         unsigned int req_vco = dev_priv->cdclk.actual.vco;
1594
1595         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
1596 }
1597
1598 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1599 {
1600         struct drm_i915_private *dev_priv = to_i915(state->dev);
1601         int max_pixclk = intel_max_pixel_rate(state);
1602         struct intel_atomic_state *intel_state =
1603                 to_intel_atomic_state(state);
1604         int cdclk, vco;
1605
1606         if (IS_GEMINILAKE(dev_priv)) {
1607                 cdclk = glk_calc_cdclk(max_pixclk);
1608                 vco = glk_de_pll_vco(dev_priv, cdclk);
1609         } else {
1610                 cdclk = bxt_calc_cdclk(max_pixclk);
1611                 vco = bxt_de_pll_vco(dev_priv, cdclk);
1612         }
1613
1614         if (cdclk > dev_priv->max_cdclk_freq) {
1615                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1616                               cdclk, dev_priv->max_cdclk_freq);
1617                 return -EINVAL;
1618         }
1619
1620         intel_state->cdclk.logical.vco = vco;
1621         intel_state->cdclk.logical.cdclk = cdclk;
1622
1623         if (!intel_state->active_crtcs) {
1624                 if (IS_GEMINILAKE(dev_priv)) {
1625                         cdclk = glk_calc_cdclk(0);
1626                         vco = glk_de_pll_vco(dev_priv, cdclk);
1627                 } else {
1628                         cdclk = bxt_calc_cdclk(0);
1629                         vco = bxt_de_pll_vco(dev_priv, cdclk);
1630                 }
1631
1632                 intel_state->cdclk.actual.vco = vco;
1633                 intel_state->cdclk.actual.cdclk = cdclk;
1634         } else {
1635                 intel_state->cdclk.actual =
1636                         intel_state->cdclk.logical;
1637         }
1638
1639         return 0;
1640 }
1641
1642 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
1643 {
1644         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
1645         unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
1646         unsigned int req_vco = dev_priv->cdclk.actual.vco;
1647
1648         bxt_set_cdclk(dev_priv, req_cdclk, req_vco);
1649 }
1650
1651 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
1652 {
1653         int max_cdclk_freq = dev_priv->max_cdclk_freq;
1654
1655         if (IS_GEMINILAKE(dev_priv))
1656                 return 2 * max_cdclk_freq;
1657         else if (INTEL_INFO(dev_priv)->gen >= 9 ||
1658                  IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1659                 return max_cdclk_freq;
1660         else if (IS_CHERRYVIEW(dev_priv))
1661                 return max_cdclk_freq*95/100;
1662         else if (INTEL_INFO(dev_priv)->gen < 4)
1663                 return 2*max_cdclk_freq*90/100;
1664         else
1665                 return max_cdclk_freq*90/100;
1666 }
1667
1668 /**
1669  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
1670  * @dev_priv: i915 device
1671  *
1672  * Determine the maximum CDCLK frequency the platform supports, and also
1673  * derive the maximum dot clock frequency the maximum CDCLK frequency
1674  * allows.
1675  */
1676 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
1677 {
1678         if (IS_GEN9_BC(dev_priv)) {
1679                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
1680                 int max_cdclk, vco;
1681
1682                 vco = dev_priv->skl_preferred_vco_freq;
1683                 WARN_ON(vco != 8100000 && vco != 8640000);
1684
1685                 /*
1686                  * Use the lower (vco 8640) cdclk values as a
1687                  * first guess. skl_calc_cdclk() will correct it
1688                  * if the preferred vco is 8100 instead.
1689                  */
1690                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
1691                         max_cdclk = 617143;
1692                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
1693                         max_cdclk = 540000;
1694                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
1695                         max_cdclk = 432000;
1696                 else
1697                         max_cdclk = 308571;
1698
1699                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
1700         } else if (IS_GEMINILAKE(dev_priv)) {
1701                 dev_priv->max_cdclk_freq = 316800;
1702         } else if (IS_BROXTON(dev_priv)) {
1703                 dev_priv->max_cdclk_freq = 624000;
1704         } else if (IS_BROADWELL(dev_priv))  {
1705                 /*
1706                  * FIXME with extra cooling we can allow
1707                  * 540 MHz for ULX and 675 Mhz for ULT.
1708                  * How can we know if extra cooling is
1709                  * available? PCI ID, VTB, something else?
1710                  */
1711                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1712                         dev_priv->max_cdclk_freq = 450000;
1713                 else if (IS_BDW_ULX(dev_priv))
1714                         dev_priv->max_cdclk_freq = 450000;
1715                 else if (IS_BDW_ULT(dev_priv))
1716                         dev_priv->max_cdclk_freq = 540000;
1717                 else
1718                         dev_priv->max_cdclk_freq = 675000;
1719         } else if (IS_CHERRYVIEW(dev_priv)) {
1720                 dev_priv->max_cdclk_freq = 320000;
1721         } else if (IS_VALLEYVIEW(dev_priv)) {
1722                 dev_priv->max_cdclk_freq = 400000;
1723         } else {
1724                 /* otherwise assume cdclk is fixed */
1725                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
1726         }
1727
1728         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
1729
1730         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
1731                          dev_priv->max_cdclk_freq);
1732
1733         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
1734                          dev_priv->max_dotclk_freq);
1735 }
1736
1737 /**
1738  * intel_update_cdclk - Determine the current CDCLK frequency
1739  * @dev_priv: i915 device
1740  *
1741  * Determine the current CDCLK frequency.
1742  */
1743 void intel_update_cdclk(struct drm_i915_private *dev_priv)
1744 {
1745         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
1746
1747         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
1748                          dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
1749                          dev_priv->cdclk.hw.ref);
1750
1751         /*
1752          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
1753          * Programmng [sic] note: bit[9:2] should be programmed to the number
1754          * of cdclk that generates 4MHz reference clock freq which is used to
1755          * generate GMBus clock. This will vary with the cdclk freq.
1756          */
1757         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1758                 I915_WRITE(GMBUSFREQ_VLV,
1759                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
1760 }
1761
1762 static int pch_rawclk(struct drm_i915_private *dev_priv)
1763 {
1764         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
1765 }
1766
1767 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
1768 {
1769         /* RAWCLK_FREQ_VLV register updated from power well code */
1770         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
1771                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
1772 }
1773
1774 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
1775 {
1776         uint32_t clkcfg;
1777
1778         /* hrawclock is 1/4 the FSB frequency */
1779         clkcfg = I915_READ(CLKCFG);
1780         switch (clkcfg & CLKCFG_FSB_MASK) {
1781         case CLKCFG_FSB_400:
1782                 return 100000;
1783         case CLKCFG_FSB_533:
1784                 return 133333;
1785         case CLKCFG_FSB_667:
1786                 return 166667;
1787         case CLKCFG_FSB_800:
1788                 return 200000;
1789         case CLKCFG_FSB_1067:
1790                 return 266667;
1791         case CLKCFG_FSB_1333:
1792                 return 333333;
1793         /* these two are just a guess; one of them might be right */
1794         case CLKCFG_FSB_1600:
1795         case CLKCFG_FSB_1600_ALT:
1796                 return 400000;
1797         default:
1798                 return 133333;
1799         }
1800 }
1801
1802 /**
1803  * intel_update_rawclk - Determine the current RAWCLK frequency
1804  * @dev_priv: i915 device
1805  *
1806  * Determine the current RAWCLK frequency. RAWCLK is a fixed
1807  * frequency clock so this needs to done only once.
1808  */
1809 void intel_update_rawclk(struct drm_i915_private *dev_priv)
1810 {
1811         if (HAS_PCH_SPLIT(dev_priv))
1812                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
1813         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1814                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
1815         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
1816                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
1817         else
1818                 /* no rawclk on other platforms, or no need to know it */
1819                 return;
1820
1821         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
1822 }
1823
1824 /**
1825  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
1826  * @dev_priv: i915 device
1827  */
1828 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
1829 {
1830         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1831                 dev_priv->display.modeset_commit_cdclk =
1832                         vlv_modeset_commit_cdclk;
1833                 dev_priv->display.modeset_calc_cdclk =
1834                         vlv_modeset_calc_cdclk;
1835         } else if (IS_BROADWELL(dev_priv)) {
1836                 dev_priv->display.modeset_commit_cdclk =
1837                         bdw_modeset_commit_cdclk;
1838                 dev_priv->display.modeset_calc_cdclk =
1839                         bdw_modeset_calc_cdclk;
1840         } else if (IS_GEN9_LP(dev_priv)) {
1841                 dev_priv->display.modeset_commit_cdclk =
1842                         bxt_modeset_commit_cdclk;
1843                 dev_priv->display.modeset_calc_cdclk =
1844                         bxt_modeset_calc_cdclk;
1845         } else if (IS_GEN9_BC(dev_priv)) {
1846                 dev_priv->display.modeset_commit_cdclk =
1847                         skl_modeset_commit_cdclk;
1848                 dev_priv->display.modeset_calc_cdclk =
1849                         skl_modeset_calc_cdclk;
1850         }
1851
1852         if (IS_GEN9_BC(dev_priv))
1853                 dev_priv->display.get_cdclk = skl_get_cdclk;
1854         else if (IS_GEN9_LP(dev_priv))
1855                 dev_priv->display.get_cdclk = bxt_get_cdclk;
1856         else if (IS_BROADWELL(dev_priv))
1857                 dev_priv->display.get_cdclk = bdw_get_cdclk;
1858         else if (IS_HASWELL(dev_priv))
1859                 dev_priv->display.get_cdclk = hsw_get_cdclk;
1860         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1861                 dev_priv->display.get_cdclk = vlv_get_cdclk;
1862         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
1863                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
1864         else if (IS_GEN5(dev_priv))
1865                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
1866         else if (IS_GM45(dev_priv))
1867                 dev_priv->display.get_cdclk = gm45_get_cdclk;
1868         else if (IS_G4X(dev_priv))
1869                 dev_priv->display.get_cdclk = g33_get_cdclk;
1870         else if (IS_I965GM(dev_priv))
1871                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
1872         else if (IS_I965G(dev_priv))
1873                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
1874         else if (IS_PINEVIEW(dev_priv))
1875                 dev_priv->display.get_cdclk = pnv_get_cdclk;
1876         else if (IS_G33(dev_priv))
1877                 dev_priv->display.get_cdclk = g33_get_cdclk;
1878         else if (IS_I945GM(dev_priv))
1879                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
1880         else if (IS_I945G(dev_priv))
1881                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
1882         else if (IS_I915GM(dev_priv))
1883                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
1884         else if (IS_I915G(dev_priv))
1885                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
1886         else if (IS_I865G(dev_priv))
1887                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
1888         else if (IS_I85X(dev_priv))
1889                 dev_priv->display.get_cdclk = i85x_get_cdclk;
1890         else if (IS_I845G(dev_priv))
1891                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
1892         else { /* 830 */
1893                 WARN(!IS_I830(dev_priv),
1894                      "Unknown platform. Assuming 133 MHz CDCLK\n");
1895                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
1896         }
1897 }