drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_cdclk.h"
  25 #include "intel_drv.h"
  26
  27 /**
  28  * DOC: CDCLK / RAWCLK
  29  *
  30  * The display engine uses several different clocks to do its work. There
  31  * are two main clocks involved that aren't directly related to the actual
  32  * pixel clock or any symbol/bit clock of the actual output port. These
  33  * are the core display clock (CDCLK) and RAWCLK.
  34  *
  35  * CDCLK clocks most of the display pipe logic, and thus its frequency
  36  * must be high enough to support the rate at which pixels are flowing
  37  * through the pipes. Downscaling must also be accounted as that increases
  38  * the effective pixel rate.
  39  *
  40  * On several platforms the CDCLK frequency can be changed dynamically
  41  * to minimize power consumption for a given display configuration.
  42  * Typically changes to the CDCLK frequency require all the display pipes
  43  * to be shut down while the frequency is being changed.
  44  *
  45  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  46  * DMC will not change the active CDCLK frequency however, so that part
  47  * will still be performed by the driver directly.
  48  *
  49  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  50  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  51  * really need to know about RAWCLK is its frequency so that various
  52  * dividers can be programmed correctly.
  53  */
  54
  55 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  56                                    struct intel_cdclk_state *cdclk_state)
  57 {
  58         cdclk_state->cdclk = 133333;
  59 }
  60
  61 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  62                                    struct intel_cdclk_state *cdclk_state)
  63 {
  64         cdclk_state->cdclk = 200000;
  65 }
  66
  67 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  68                                    struct intel_cdclk_state *cdclk_state)
  69 {
  70         cdclk_state->cdclk = 266667;
  71 }
  72
  73 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  74                                    struct intel_cdclk_state *cdclk_state)
  75 {
  76         cdclk_state->cdclk = 333333;
  77 }
  78
  79 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  80                                    struct intel_cdclk_state *cdclk_state)
  81 {
  82         cdclk_state->cdclk = 400000;
  83 }
  84
  85 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  86                                    struct intel_cdclk_state *cdclk_state)
  87 {
  88         cdclk_state->cdclk = 450000;
  89 }
  90
  91 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  92                            struct intel_cdclk_state *cdclk_state)
  93 {
  94         struct pci_dev *pdev = dev_priv->drm.pdev;
  95         u16 hpllcc = 0;
  96
  97         /*
  98          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  99          * encoding is different :(
 100          * FIXME is this the right way to detect 852GM/852GMV?
 101          */
 102         if (pdev->revision == 0x1) {
 103                 cdclk_state->cdclk = 133333;
 104                 return;
 105         }
 106
 107         pci_bus_read_config_word(pdev->bus,
 108                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 109
 110         /* Assume that the hardware is in the high speed state.  This
 111          * should be the default.
 112          */
 113         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 114         case GC_CLOCK_133_200:
 115         case GC_CLOCK_133_200_2:
 116         case GC_CLOCK_100_200:
 117                 cdclk_state->cdclk = 200000;
 118                 break;
 119         case GC_CLOCK_166_250:
 120                 cdclk_state->cdclk = 250000;
 121                 break;
 122         case GC_CLOCK_100_133:
 123                 cdclk_state->cdclk = 133333;
 124                 break;
 125         case GC_CLOCK_133_266:
 126         case GC_CLOCK_133_266_2:
 127         case GC_CLOCK_166_266:
 128                 cdclk_state->cdclk = 266667;
 129                 break;
 130         }
 131 }
 132
 133 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 134                              struct intel_cdclk_state *cdclk_state)
 135 {
 136         struct pci_dev *pdev = dev_priv->drm.pdev;
 137         u16 gcfgc = 0;
 138
 139         pci_read_config_word(pdev, GCFGC, &gcfgc);
 140
 141         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 142                 cdclk_state->cdclk = 133333;
 143                 return;
 144         }
 145
 146         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 147         case GC_DISPLAY_CLOCK_333_320_MHZ:
 148                 cdclk_state->cdclk = 333333;
 149                 break;
 150         default:
 151         case GC_DISPLAY_CLOCK_190_200_MHZ:
 152                 cdclk_state->cdclk = 190000;
 153                 break;
 154         }
 155 }
 156
 157 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 158                              struct intel_cdclk_state *cdclk_state)
 159 {
 160         struct pci_dev *pdev = dev_priv->drm.pdev;
 161         u16 gcfgc = 0;
 162
 163         pci_read_config_word(pdev, GCFGC, &gcfgc);
 164
 165         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 166                 cdclk_state->cdclk = 133333;
 167                 return;
 168         }
 169
 170         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 171         case GC_DISPLAY_CLOCK_333_320_MHZ:
 172                 cdclk_state->cdclk = 320000;
 173                 break;
 174         default:
 175         case GC_DISPLAY_CLOCK_190_200_MHZ:
 176                 cdclk_state->cdclk = 200000;
 177                 break;
 178         }
 179 }
 180
 181 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 182 {
 183         static const unsigned int blb_vco[8] = {
 184                 [0] = 3200000,
 185                 [1] = 4000000,
 186                 [2] = 5333333,
 187                 [3] = 4800000,
 188                 [4] = 6400000,
 189         };
 190         static const unsigned int pnv_vco[8] = {
 191                 [0] = 3200000,
 192                 [1] = 4000000,
 193                 [2] = 5333333,
 194                 [3] = 4800000,
 195                 [4] = 2666667,
 196         };
 197         static const unsigned int cl_vco[8] = {
 198                 [0] = 3200000,
 199                 [1] = 4000000,
 200                 [2] = 5333333,
 201                 [3] = 6400000,
 202                 [4] = 3333333,
 203                 [5] = 3566667,
 204                 [6] = 4266667,
 205         };
 206         static const unsigned int elk_vco[8] = {
 207                 [0] = 3200000,
 208                 [1] = 4000000,
 209                 [2] = 5333333,
 210                 [3] = 4800000,
 211         };
 212         static const unsigned int ctg_vco[8] = {
 213                 [0] = 3200000,
 214                 [1] = 4000000,
 215                 [2] = 5333333,
 216                 [3] = 6400000,
 217                 [4] = 2666667,
 218                 [5] = 4266667,
 219         };
 220         const unsigned int *vco_table;
 221         unsigned int vco;
 222         u8 tmp = 0;
 223
 224         /* FIXME other chipsets? */
 225         if (IS_GM45(dev_priv))
 226                 vco_table = ctg_vco;
 227         else if (IS_G45(dev_priv))
 228                 vco_table = elk_vco;
 229         else if (IS_I965GM(dev_priv))
 230                 vco_table = cl_vco;
 231         else if (IS_PINEVIEW(dev_priv))
 232                 vco_table = pnv_vco;
 233         else if (IS_G33(dev_priv))
 234                 vco_table = blb_vco;
 235         else
 236                 return 0;
 237
 238         tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ?
 239                         HPLLVCO_MOBILE : HPLLVCO);
 240
 241         vco = vco_table[tmp & 0x7];
 242         if (vco == 0)
 243                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 244         else
 245                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 246
 247         return vco;
 248 }
 249
 250 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 251                           struct intel_cdclk_state *cdclk_state)
 252 {
 253         struct pci_dev *pdev = dev_priv->drm.pdev;
 254         static const u8 div_3200[] = { 12, 10,  8,  7, 5, 16 };
 255         static const u8 div_4000[] = { 14, 12, 10,  8, 6, 20 };
 256         static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
 257         static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
 258         const u8 *div_table;
 259         unsigned int cdclk_sel;
 260         u16 tmp = 0;
 261
 262         cdclk_state->vco = intel_hpll_vco(dev_priv);
 263
 264         pci_read_config_word(pdev, GCFGC, &tmp);
 265
 266         cdclk_sel = (tmp >> 4) & 0x7;
 267
 268         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 269                 goto fail;
 270
 271         switch (cdclk_state->vco) {
 272         case 3200000:
 273                 div_table = div_3200;
 274                 break;
 275         case 4000000:
 276                 div_table = div_4000;
 277                 break;
 278         case 4800000:
 279                 div_table = div_4800;
 280                 break;
 281         case 5333333:
 282                 div_table = div_5333;
 283                 break;
 284         default:
 285                 goto fail;
 286         }
 287
 288         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 289                                                div_table[cdclk_sel]);
 290         return;
 291
 292 fail:
 293         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 294                   cdclk_state->vco, tmp);
 295         cdclk_state->cdclk = 190476;
 296 }
 297
 298 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 299                           struct intel_cdclk_state *cdclk_state)
 300 {
 301         struct pci_dev *pdev = dev_priv->drm.pdev;
 302         u16 gcfgc = 0;
 303
 304         pci_read_config_word(pdev, GCFGC, &gcfgc);
 305
 306         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 307         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 308                 cdclk_state->cdclk = 266667;
 309                 break;
 310         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 311                 cdclk_state->cdclk = 333333;
 312                 break;
 313         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 314                 cdclk_state->cdclk = 444444;
 315                 break;
 316         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 317                 cdclk_state->cdclk = 200000;
 318                 break;
 319         default:
 320                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 321                 /* fall through */
 322         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 323                 cdclk_state->cdclk = 133333;
 324                 break;
 325         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 326                 cdclk_state->cdclk = 166667;
 327                 break;
 328         }
 329 }
 330
 331 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 332                              struct intel_cdclk_state *cdclk_state)
 333 {
 334         struct pci_dev *pdev = dev_priv->drm.pdev;
 335         static const u8 div_3200[] = { 16, 10,  8 };
 336         static const u8 div_4000[] = { 20, 12, 10 };
 337         static const u8 div_5333[] = { 24, 16, 14 };
 338         const u8 *div_table;
 339         unsigned int cdclk_sel;
 340         u16 tmp = 0;
 341
 342         cdclk_state->vco = intel_hpll_vco(dev_priv);
 343
 344         pci_read_config_word(pdev, GCFGC, &tmp);
 345
 346         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 347
 348         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 349                 goto fail;
 350
 351         switch (cdclk_state->vco) {
 352         case 3200000:
 353                 div_table = div_3200;
 354                 break;
 355         case 4000000:
 356                 div_table = div_4000;
 357                 break;
 358         case 5333333:
 359                 div_table = div_5333;
 360                 break;
 361         default:
 362                 goto fail;
 363         }
 364
 365         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 366                                                div_table[cdclk_sel]);
 367         return;
 368
 369 fail:
 370         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 371                   cdclk_state->vco, tmp);
 372         cdclk_state->cdclk = 200000;
 373 }
 374
 375 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 376                            struct intel_cdclk_state *cdclk_state)
 377 {
 378         struct pci_dev *pdev = dev_priv->drm.pdev;
 379         unsigned int cdclk_sel;
 380         u16 tmp = 0;
 381
 382         cdclk_state->vco = intel_hpll_vco(dev_priv);
 383
 384         pci_read_config_word(pdev, GCFGC, &tmp);
 385
 386         cdclk_sel = (tmp >> 12) & 0x1;
 387
 388         switch (cdclk_state->vco) {
 389         case 2666667:
 390         case 4000000:
 391         case 5333333:
 392                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 393                 break;
 394         case 3200000:
 395                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 396                 break;
 397         default:
 398                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 399                           cdclk_state->vco, tmp);
 400                 cdclk_state->cdclk = 222222;
 401                 break;
 402         }
 403 }
 404
 405 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 406                           struct intel_cdclk_state *cdclk_state)
 407 {
 408         u32 lcpll = I915_READ(LCPLL_CTL);
 409         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 410
 411         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 412                 cdclk_state->cdclk = 800000;
 413         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 414                 cdclk_state->cdclk = 450000;
 415         else if (freq == LCPLL_CLK_FREQ_450)
 416                 cdclk_state->cdclk = 450000;
 417         else if (IS_HSW_ULT(dev_priv))
 418                 cdclk_state->cdclk = 337500;
 419         else
 420                 cdclk_state->cdclk = 540000;
 421 }
 422
 423 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 424 {
 425         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 426                 333333 : 320000;
 427
 428         /*
 429          * We seem to get an unstable or solid color picture at 200MHz.
 430          * Not sure what's wrong. For now use 200MHz only when all pipes
 431          * are off.
 432          */
 433         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 434                 return 400000;
 435         else if (min_cdclk > 266667)
 436                 return freq_320;
 437         else if (min_cdclk > 0)
 438                 return 266667;
 439         else
 440                 return 200000;
 441 }
 442
 443 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 444 {
 445         if (IS_VALLEYVIEW(dev_priv)) {
 446                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 447                         return 2;
 448                 else if (cdclk >= 266667)
 449                         return 1;
 450                 else
 451                         return 0;
 452         } else {
 453                 /*
 454                  * Specs are full of misinformation, but testing on actual
 455                  * hardware has shown that we just need to write the desired
 456                  * CCK divider into the Punit register.
 457                  */
 458                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 459         }
 460 }
 461
 462 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 463                           struct intel_cdclk_state *cdclk_state)
 464 {
 465         u32 val;
 466
 467         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 468         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 469                                                CCK_DISPLAY_CLOCK_CONTROL,
 470                                                cdclk_state->vco);
 471
 472         mutex_lock(&dev_priv->pcu_lock);
 473         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 474         mutex_unlock(&dev_priv->pcu_lock);
 475
 476         if (IS_VALLEYVIEW(dev_priv))
 477                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
 478                         DSPFREQGUAR_SHIFT;
 479         else
 480                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 481                         DSPFREQGUAR_SHIFT_CHV;
 482 }
 483
 484 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 485 {
 486         unsigned int credits, default_credits;
 487
 488         if (IS_CHERRYVIEW(dev_priv))
 489                 default_credits = PFI_CREDIT(12);
 490         else
 491                 default_credits = PFI_CREDIT(8);
 492
 493         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 494                 /* CHV suggested value is 31 or 63 */
 495                 if (IS_CHERRYVIEW(dev_priv))
 496                         credits = PFI_CREDIT_63;
 497                 else
 498                         credits = PFI_CREDIT(15);
 499         } else {
 500                 credits = default_credits;
 501         }
 502
 503         /*
 504          * WA - write default credits before re-programming
 505          * FIXME: should we also set the resend bit here?
 506          */
 507         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 508                    default_credits);
 509
 510         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 511                    credits | PFI_CREDIT_RESEND);
 512
 513         /*
 514          * FIXME is this guaranteed to clear
 515          * immediately or should we poll for it?
 516          */
 517         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 518 }
 519
 520 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 521                           const struct intel_cdclk_state *cdclk_state,
 522                           enum pipe pipe)
 523 {
 524         int cdclk = cdclk_state->cdclk;
 525         u32 val, cmd = cdclk_state->voltage_level;
 526         intel_wakeref_t wakeref;
 527
 528         switch (cdclk) {
 529         case 400000:
 530         case 333333:
 531         case 320000:
 532         case 266667:
 533         case 200000:
 534                 break;
 535         default:
 536                 MISSING_CASE(cdclk);
 537                 return;
 538         }
 539
 540         /* There are cases where we can end up here with power domains
 541          * off and a CDCLK frequency other than the minimum, like when
 542          * issuing a modeset without actually changing any display after
 543          * a system suspend.  So grab the PIPE-A domain, which covers
 544          * the HW blocks needed for the following programming.
 545          */
 546         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 547
 548         mutex_lock(&dev_priv->pcu_lock);
 549         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 550         val &= ~DSPFREQGUAR_MASK;
 551         val |= (cmd << DSPFREQGUAR_SHIFT);
 552         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 553         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 554                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 555                      50)) {
 556                 DRM_ERROR("timed out waiting for CDclk change\n");
 557         }
 558         mutex_unlock(&dev_priv->pcu_lock);
 559
 560         mutex_lock(&dev_priv->sb_lock);
 561
 562         if (cdclk == 400000) {
 563                 u32 divider;
 564
 565                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 566                                             cdclk) - 1;
 567
 568                 /* adjust cdclk divider */
 569                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 570                 val &= ~CCK_FREQUENCY_VALUES;
 571                 val |= divider;
 572                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 573
 574                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 575                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 576                              50))
 577                         DRM_ERROR("timed out waiting for CDclk change\n");
 578         }
 579
 580         /* adjust self-refresh exit latency value */
 581         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 582         val &= ~0x7f;
 583
 584         /*
 585          * For high bandwidth configs, we set a higher latency in the bunit
 586          * so that the core display fetch happens in time to avoid underruns.
 587          */
 588         if (cdclk == 400000)
 589                 val |= 4500 / 250; /* 4.5 usec */
 590         else
 591                 val |= 3000 / 250; /* 3.0 usec */
 592         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 593
 594         mutex_unlock(&dev_priv->sb_lock);
 595
 596         intel_update_cdclk(dev_priv);
 597
 598         vlv_program_pfi_credits(dev_priv);
 599
 600         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
 601 }
 602
 603 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 604                           const struct intel_cdclk_state *cdclk_state,
 605                           enum pipe pipe)
 606 {
 607         int cdclk = cdclk_state->cdclk;
 608         u32 val, cmd = cdclk_state->voltage_level;
 609         intel_wakeref_t wakeref;
 610
 611         switch (cdclk) {
 612         case 333333:
 613         case 320000:
 614         case 266667:
 615         case 200000:
 616                 break;
 617         default:
 618                 MISSING_CASE(cdclk);
 619                 return;
 620         }
 621
 622         /* There are cases where we can end up here with power domains
 623          * off and a CDCLK frequency other than the minimum, like when
 624          * issuing a modeset without actually changing any display after
 625          * a system suspend.  So grab the PIPE-A domain, which covers
 626          * the HW blocks needed for the following programming.
 627          */
 628         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 629
 630         mutex_lock(&dev_priv->pcu_lock);
 631         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 632         val &= ~DSPFREQGUAR_MASK_CHV;
 633         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 634         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 635         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 636                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 637                      50)) {
 638                 DRM_ERROR("timed out waiting for CDclk change\n");
 639         }
 640         mutex_unlock(&dev_priv->pcu_lock);
 641
 642         intel_update_cdclk(dev_priv);
 643
 644         vlv_program_pfi_credits(dev_priv);
 645
 646         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
 647 }
 648
 649 static int bdw_calc_cdclk(int min_cdclk)
 650 {
 651         if (min_cdclk > 540000)
 652                 return 675000;
 653         else if (min_cdclk > 450000)
 654                 return 540000;
 655         else if (min_cdclk > 337500)
 656                 return 450000;
 657         else
 658                 return 337500;
 659 }
 660
 661 static u8 bdw_calc_voltage_level(int cdclk)
 662 {
 663         switch (cdclk) {
 664         default:
 665         case 337500:
 666                 return 2;
 667         case 450000:
 668                 return 0;
 669         case 540000:
 670                 return 1;
 671         case 675000:
 672                 return 3;
 673         }
 674 }
 675
 676 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 677                           struct intel_cdclk_state *cdclk_state)
 678 {
 679         u32 lcpll = I915_READ(LCPLL_CTL);
 680         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 681
 682         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 683                 cdclk_state->cdclk = 800000;
 684         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 685                 cdclk_state->cdclk = 450000;
 686         else if (freq == LCPLL_CLK_FREQ_450)
 687                 cdclk_state->cdclk = 450000;
 688         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 689                 cdclk_state->cdclk = 540000;
 690         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 691                 cdclk_state->cdclk = 337500;
 692         else
 693                 cdclk_state->cdclk = 675000;
 694
 695         /*
 696          * Can't read this out :( Let's assume it's
 697          * at least what the CDCLK frequency requires.
 698          */
 699         cdclk_state->voltage_level =
 700                 bdw_calc_voltage_level(cdclk_state->cdclk);
 701 }
 702
 703 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 704                           const struct intel_cdclk_state *cdclk_state,
 705                           enum pipe pipe)
 706 {
 707         int cdclk = cdclk_state->cdclk;
 708         u32 val;
 709         int ret;
 710
 711         if (WARN((I915_READ(LCPLL_CTL) &
 712                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 713                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 714                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 715                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 716                  "trying to change cdclk frequency with cdclk not enabled\n"))
 717                 return;
 718
 719         mutex_lock(&dev_priv->pcu_lock);
 720         ret = sandybridge_pcode_write(dev_priv,
 721                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 722         mutex_unlock(&dev_priv->pcu_lock);
 723         if (ret) {
 724                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 725                 return;
 726         }
 727
 728         val = I915_READ(LCPLL_CTL);
 729         val |= LCPLL_CD_SOURCE_FCLK;
 730         I915_WRITE(LCPLL_CTL, val);
 731
 732         /*
 733          * According to the spec, it should be enough to poll for this 1 us.
 734          * However, extensive testing shows that this can take longer.
 735          */
 736         if (wait_for_us(I915_READ(LCPLL_CTL) &
 737                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 738                 DRM_ERROR("Switching to FCLK failed\n");
 739
 740         val = I915_READ(LCPLL_CTL);
 741         val &= ~LCPLL_CLK_FREQ_MASK;
 742
 743         switch (cdclk) {
 744         default:
 745                 MISSING_CASE(cdclk);
 746                 /* fall through */
 747         case 337500:
 748                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 749                 break;
 750         case 450000:
 751                 val |= LCPLL_CLK_FREQ_450;
 752                 break;
 753         case 540000:
 754                 val |= LCPLL_CLK_FREQ_54O_BDW;
 755                 break;
 756         case 675000:
 757                 val |= LCPLL_CLK_FREQ_675_BDW;
 758                 break;
 759         }
 760
 761         I915_WRITE(LCPLL_CTL, val);
 762
 763         val = I915_READ(LCPLL_CTL);
 764         val &= ~LCPLL_CD_SOURCE_FCLK;
 765         I915_WRITE(LCPLL_CTL, val);
 766
 767         if (wait_for_us((I915_READ(LCPLL_CTL) &
 768                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 769                 DRM_ERROR("Switching back to LCPLL failed\n");
 770
 771         mutex_lock(&dev_priv->pcu_lock);
 772         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
 773                                 cdclk_state->voltage_level);
 774         mutex_unlock(&dev_priv->pcu_lock);
 775
 776         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 777
 778         intel_update_cdclk(dev_priv);
 779 }
 780
 781 static int skl_calc_cdclk(int min_cdclk, int vco)
 782 {
 783         if (vco == 8640000) {
 784                 if (min_cdclk > 540000)
 785                         return 617143;
 786                 else if (min_cdclk > 432000)
 787                         return 540000;
 788                 else if (min_cdclk > 308571)
 789                         return 432000;
 790                 else
 791                         return 308571;
 792         } else {
 793                 if (min_cdclk > 540000)
 794                         return 675000;
 795                 else if (min_cdclk > 450000)
 796                         return 540000;
 797                 else if (min_cdclk > 337500)
 798                         return 450000;
 799                 else
 800                         return 337500;
 801         }
 802 }
 803
 804 static u8 skl_calc_voltage_level(int cdclk)
 805 {
 806         switch (cdclk) {
 807         default:
 808         case 308571:
 809         case 337500:
 810                 return 0;
 811         case 450000:
 812         case 432000:
 813                 return 1;
 814         case 540000:
 815                 return 2;
 816         case 617143:
 817         case 675000:
 818                 return 3;
 819         }
 820 }
 821
 822 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 823                              struct intel_cdclk_state *cdclk_state)
 824 {
 825         u32 val;
 826
 827         cdclk_state->ref = 24000;
 828         cdclk_state->vco = 0;
 829
 830         val = I915_READ(LCPLL1_CTL);
 831         if ((val & LCPLL_PLL_ENABLE) == 0)
 832                 return;
 833
 834         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 835                 return;
 836
 837         val = I915_READ(DPLL_CTRL1);
 838
 839         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 840                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 841                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 842                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 843                 return;
 844
 845         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 846         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 847         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 848         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 849         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 850                 cdclk_state->vco = 8100000;
 851                 break;
 852         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 853         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 854                 cdclk_state->vco = 8640000;
 855                 break;
 856         default:
 857                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 858                 break;
 859         }
 860 }
 861
 862 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 863                           struct intel_cdclk_state *cdclk_state)
 864 {
 865         u32 cdctl;
 866
 867         skl_dpll0_update(dev_priv, cdclk_state);
 868
 869         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
 870
 871         if (cdclk_state->vco == 0)
 872                 goto out;
 873
 874         cdctl = I915_READ(CDCLK_CTL);
 875
 876         if (cdclk_state->vco == 8640000) {
 877                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 878                 case CDCLK_FREQ_450_432:
 879                         cdclk_state->cdclk = 432000;
 880                         break;
 881                 case CDCLK_FREQ_337_308:
 882                         cdclk_state->cdclk = 308571;
 883                         break;
 884                 case CDCLK_FREQ_540:
 885                         cdclk_state->cdclk = 540000;
 886                         break;
 887                 case CDCLK_FREQ_675_617:
 888                         cdclk_state->cdclk = 617143;
 889                         break;
 890                 default:
 891                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 892                         break;
 893                 }
 894         } else {
 895                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 896                 case CDCLK_FREQ_450_432:
 897                         cdclk_state->cdclk = 450000;
 898                         break;
 899                 case CDCLK_FREQ_337_308:
 900                         cdclk_state->cdclk = 337500;
 901                         break;
 902                 case CDCLK_FREQ_540:
 903                         cdclk_state->cdclk = 540000;
 904                         break;
 905                 case CDCLK_FREQ_675_617:
 906                         cdclk_state->cdclk = 675000;
 907                         break;
 908                 default:
 909                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 910                         break;
 911                 }
 912         }
 913
 914  out:
 915         /*
 916          * Can't read this out :( Let's assume it's
 917          * at least what the CDCLK frequency requires.
 918          */
 919         cdclk_state->voltage_level =
 920                 skl_calc_voltage_level(cdclk_state->cdclk);
 921 }
 922
 923 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 924 static int skl_cdclk_decimal(int cdclk)
 925 {
 926         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 927 }
 928
 929 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 930                                         int vco)
 931 {
 932         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 933
 934         dev_priv->skl_preferred_vco_freq = vco;
 935
 936         if (changed)
 937                 intel_update_max_cdclk(dev_priv);
 938 }
 939
 940 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 941 {
 942         u32 val;
 943
 944         WARN_ON(vco != 8100000 && vco != 8640000);
 945
 946         /*
 947          * We always enable DPLL0 with the lowest link rate possible, but still
 948          * taking into account the VCO required to operate the eDP panel at the
 949          * desired frequency. The usual DP link rates operate with a VCO of
 950          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 951          * The modeset code is responsible for the selection of the exact link
 952          * rate later on, with the constraint of choosing a frequency that
 953          * works with vco.
 954          */
 955         val = I915_READ(DPLL_CTRL1);
 956
 957         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 958                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 959         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 960         if (vco == 8640000)
 961                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 962                                             SKL_DPLL0);
 963         else
 964                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 965                                             SKL_DPLL0);
 966
 967         I915_WRITE(DPLL_CTRL1, val);
 968         POSTING_READ(DPLL_CTRL1);
 969
 970         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 971
 972         if (intel_wait_for_register(&dev_priv->uncore,
 973                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 974                                     5))
 975                 DRM_ERROR("DPLL0 not locked\n");
 976
 977         dev_priv->cdclk.hw.vco = vco;
 978
 979         /* We'll want to keep using the current vco from now on. */
 980         skl_set_preferred_cdclk_vco(dev_priv, vco);
 981 }
 982
 983 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 984 {
 985         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 986         if (intel_wait_for_register(&dev_priv->uncore,
 987                                     LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 988                                     1))
 989                 DRM_ERROR("Couldn't disable DPLL0\n");
 990
 991         dev_priv->cdclk.hw.vco = 0;
 992 }
 993
 994 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 995                           const struct intel_cdclk_state *cdclk_state,
 996                           enum pipe pipe)
 997 {
 998         int cdclk = cdclk_state->cdclk;
 999         int vco = cdclk_state->vco;
1000         u32 freq_select, cdclk_ctl;
1001         int ret;
1002
1003         /*
1004          * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1005          * unsupported on SKL. In theory this should never happen since only
1006          * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1007          * supported on SKL either, see the above WA. WARN whenever trying to
1008          * use the corresponding VCO freq as that always leads to using the
1009          * minimum 308MHz CDCLK.
1010          */
1011         WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
1012
1013         mutex_lock(&dev_priv->pcu_lock);
1014         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1015                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1016                                 SKL_CDCLK_READY_FOR_CHANGE,
1017                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1018         mutex_unlock(&dev_priv->pcu_lock);
1019         if (ret) {
1020                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1021                           ret);
1022                 return;
1023         }
1024
1025         /* Choose frequency for this cdclk */
1026         switch (cdclk) {
1027         default:
1028                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1029                 WARN_ON(vco != 0);
1030                 /* fall through */
1031         case 308571:
1032         case 337500:
1033                 freq_select = CDCLK_FREQ_337_308;
1034                 break;
1035         case 450000:
1036         case 432000:
1037                 freq_select = CDCLK_FREQ_450_432;
1038                 break;
1039         case 540000:
1040                 freq_select = CDCLK_FREQ_540;
1041                 break;
1042         case 617143:
1043         case 675000:
1044                 freq_select = CDCLK_FREQ_675_617;
1045                 break;
1046         }
1047
1048         if (dev_priv->cdclk.hw.vco != 0 &&
1049             dev_priv->cdclk.hw.vco != vco)
1050                 skl_dpll0_disable(dev_priv);
1051
1052         cdclk_ctl = I915_READ(CDCLK_CTL);
1053
1054         if (dev_priv->cdclk.hw.vco != vco) {
1055                 /* Wa Display #1183: skl,kbl,cfl */
1056                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1057                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1058                 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1059         }
1060
1061         /* Wa Display #1183: skl,kbl,cfl */
1062         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1063         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1064         POSTING_READ(CDCLK_CTL);
1065
1066         if (dev_priv->cdclk.hw.vco != vco)
1067                 skl_dpll0_enable(dev_priv, vco);
1068
1069         /* Wa Display #1183: skl,kbl,cfl */
1070         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1071         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1072
1073         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1074         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1075
1076         /* Wa Display #1183: skl,kbl,cfl */
1077         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1078         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1079         POSTING_READ(CDCLK_CTL);
1080
1081         /* inform PCU of the change */
1082         mutex_lock(&dev_priv->pcu_lock);
1083         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1084                                 cdclk_state->voltage_level);
1085         mutex_unlock(&dev_priv->pcu_lock);
1086
1087         intel_update_cdclk(dev_priv);
1088 }
1089
1090 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1091 {
1092         u32 cdctl, expected;
1093
1094         /*
1095          * check if the pre-os initialized the display
1096          * There is SWF18 scratchpad register defined which is set by the
1097          * pre-os which can be used by the OS drivers to check the status
1098          */
1099         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1100                 goto sanitize;
1101
1102         intel_update_cdclk(dev_priv);
1103         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1104
1105         /* Is PLL enabled and locked ? */
1106         if (dev_priv->cdclk.hw.vco == 0 ||
1107             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1108                 goto sanitize;
1109
1110         /* DPLL okay; verify the cdclock
1111          *
1112          * Noticed in some instances that the freq selection is correct but
1113          * decimal part is programmed wrong from BIOS where pre-os does not
1114          * enable display. Verify the same as well.
1115          */
1116         cdctl = I915_READ(CDCLK_CTL);
1117         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1118                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1119         if (cdctl == expected)
1120                 /* All well; nothing to sanitize */
1121                 return;
1122
1123 sanitize:
1124         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1125
1126         /* force cdclk programming */
1127         dev_priv->cdclk.hw.cdclk = 0;
1128         /* force full PLL disable + enable */
1129         dev_priv->cdclk.hw.vco = -1;
1130 }
1131
1132 static void skl_init_cdclk(struct drm_i915_private *dev_priv)
1133 {
1134         struct intel_cdclk_state cdclk_state;
1135
1136         skl_sanitize_cdclk(dev_priv);
1137
1138         if (dev_priv->cdclk.hw.cdclk != 0 &&
1139             dev_priv->cdclk.hw.vco != 0) {
1140                 /*
1141                  * Use the current vco as our initial
1142                  * guess as to what the preferred vco is.
1143                  */
1144                 if (dev_priv->skl_preferred_vco_freq == 0)
1145                         skl_set_preferred_cdclk_vco(dev_priv,
1146                                                     dev_priv->cdclk.hw.vco);
1147                 return;
1148         }
1149
1150         cdclk_state = dev_priv->cdclk.hw;
1151
1152         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1153         if (cdclk_state.vco == 0)
1154                 cdclk_state.vco = 8100000;
1155         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1156         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1157
1158         skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1159 }
1160
1161 static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1162 {
1163         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1164
1165         cdclk_state.cdclk = cdclk_state.bypass;
1166         cdclk_state.vco = 0;
1167         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1168
1169         skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1170 }
1171
1172 static int bxt_calc_cdclk(int min_cdclk)
1173 {
1174         if (min_cdclk > 576000)
1175                 return 624000;
1176         else if (min_cdclk > 384000)
1177                 return 576000;
1178         else if (min_cdclk > 288000)
1179                 return 384000;
1180         else if (min_cdclk > 144000)
1181                 return 288000;
1182         else
1183                 return 144000;
1184 }
1185
1186 static int glk_calc_cdclk(int min_cdclk)
1187 {
1188         if (min_cdclk > 158400)
1189                 return 316800;
1190         else if (min_cdclk > 79200)
1191                 return 158400;
1192         else
1193                 return 79200;
1194 }
1195
1196 static u8 bxt_calc_voltage_level(int cdclk)
1197 {
1198         return DIV_ROUND_UP(cdclk, 25000);
1199 }
1200
1201 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1202 {
1203         int ratio;
1204
1205         if (cdclk == dev_priv->cdclk.hw.bypass)
1206                 return 0;
1207
1208         switch (cdclk) {
1209         default:
1210                 MISSING_CASE(cdclk);
1211                 /* fall through */
1212         case 144000:
1213         case 288000:
1214         case 384000:
1215         case 576000:
1216                 ratio = 60;
1217                 break;
1218         case 624000:
1219                 ratio = 65;
1220                 break;
1221         }
1222
1223         return dev_priv->cdclk.hw.ref * ratio;
1224 }
1225
1226 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1227 {
1228         int ratio;
1229
1230         if (cdclk == dev_priv->cdclk.hw.bypass)
1231                 return 0;
1232
1233         switch (cdclk) {
1234         default:
1235                 MISSING_CASE(cdclk);
1236                 /* fall through */
1237         case  79200:
1238         case 158400:
1239         case 316800:
1240                 ratio = 33;
1241                 break;
1242         }
1243
1244         return dev_priv->cdclk.hw.ref * ratio;
1245 }
1246
1247 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1248                               struct intel_cdclk_state *cdclk_state)
1249 {
1250         u32 val;
1251
1252         cdclk_state->ref = 19200;
1253         cdclk_state->vco = 0;
1254
1255         val = I915_READ(BXT_DE_PLL_ENABLE);
1256         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1257                 return;
1258
1259         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1260                 return;
1261
1262         val = I915_READ(BXT_DE_PLL_CTL);
1263         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1264 }
1265
1266 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1267                           struct intel_cdclk_state *cdclk_state)
1268 {
1269         u32 divider;
1270         int div;
1271
1272         bxt_de_pll_update(dev_priv, cdclk_state);
1273
1274         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1275
1276         if (cdclk_state->vco == 0)
1277                 goto out;
1278
1279         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1280
1281         switch (divider) {
1282         case BXT_CDCLK_CD2X_DIV_SEL_1:
1283                 div = 2;
1284                 break;
1285         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1286                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1287                 div = 3;
1288                 break;
1289         case BXT_CDCLK_CD2X_DIV_SEL_2:
1290                 div = 4;
1291                 break;
1292         case BXT_CDCLK_CD2X_DIV_SEL_4:
1293                 div = 8;
1294                 break;
1295         default:
1296                 MISSING_CASE(divider);
1297                 return;
1298         }
1299
1300         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1301
1302  out:
1303         /*
1304          * Can't read this out :( Let's assume it's
1305          * at least what the CDCLK frequency requires.
1306          */
1307         cdclk_state->voltage_level =
1308                 bxt_calc_voltage_level(cdclk_state->cdclk);
1309 }
1310
1311 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1312 {
1313         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1314
1315         /* Timeout 200us */
1316         if (intel_wait_for_register(&dev_priv->uncore,
1317                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1318                                     1))
1319                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1320
1321         dev_priv->cdclk.hw.vco = 0;
1322 }
1323
1324 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1325 {
1326         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1327         u32 val;
1328
1329         val = I915_READ(BXT_DE_PLL_CTL);
1330         val &= ~BXT_DE_PLL_RATIO_MASK;
1331         val |= BXT_DE_PLL_RATIO(ratio);
1332         I915_WRITE(BXT_DE_PLL_CTL, val);
1333
1334         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1335
1336         /* Timeout 200us */
1337         if (intel_wait_for_register(&dev_priv->uncore,
1338                                     BXT_DE_PLL_ENABLE,
1339                                     BXT_DE_PLL_LOCK,
1340                                     BXT_DE_PLL_LOCK,
1341                                     1))
1342                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1343
1344         dev_priv->cdclk.hw.vco = vco;
1345 }
1346
1347 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1348                           const struct intel_cdclk_state *cdclk_state,
1349                           enum pipe pipe)
1350 {
1351         int cdclk = cdclk_state->cdclk;
1352         int vco = cdclk_state->vco;
1353         u32 val, divider;
1354         int ret;
1355
1356         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1357         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1358         default:
1359                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1360                 WARN_ON(vco != 0);
1361                 /* fall through */
1362         case 2:
1363                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1364                 break;
1365         case 3:
1366                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1367                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1368                 break;
1369         case 4:
1370                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1371                 break;
1372         case 8:
1373                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1374                 break;
1375         }
1376
1377         /*
1378          * Inform power controller of upcoming frequency change. BSpec
1379          * requires us to wait up to 150usec, but that leads to timeouts;
1380          * the 2ms used here is based on experiment.
1381          */
1382         mutex_lock(&dev_priv->pcu_lock);
1383         ret = sandybridge_pcode_write_timeout(dev_priv,
1384                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1385                                               0x80000000, 150, 2);
1386         mutex_unlock(&dev_priv->pcu_lock);
1387
1388         if (ret) {
1389                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1390                           ret, cdclk);
1391                 return;
1392         }
1393
1394         if (dev_priv->cdclk.hw.vco != 0 &&
1395             dev_priv->cdclk.hw.vco != vco)
1396                 bxt_de_pll_disable(dev_priv);
1397
1398         if (dev_priv->cdclk.hw.vco != vco)
1399                 bxt_de_pll_enable(dev_priv, vco);
1400
1401         val = divider | skl_cdclk_decimal(cdclk);
1402         if (pipe == INVALID_PIPE)
1403                 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1404         else
1405                 val |= BXT_CDCLK_CD2X_PIPE(pipe);
1406         /*
1407          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1408          * enable otherwise.
1409          */
1410         if (cdclk >= 500000)
1411                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1412         I915_WRITE(CDCLK_CTL, val);
1413
1414         if (pipe != INVALID_PIPE)
1415                 intel_wait_for_vblank(dev_priv, pipe);
1416
1417         mutex_lock(&dev_priv->pcu_lock);
1418         /*
1419          * The timeout isn't specified, the 2ms used here is based on
1420          * experiment.
1421          * FIXME: Waiting for the request completion could be delayed until
1422          * the next PCODE request based on BSpec.
1423          */
1424         ret = sandybridge_pcode_write_timeout(dev_priv,
1425                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1426                                               cdclk_state->voltage_level, 150, 2);
1427         mutex_unlock(&dev_priv->pcu_lock);
1428
1429         if (ret) {
1430                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1431                           ret, cdclk);
1432                 return;
1433         }
1434
1435         intel_update_cdclk(dev_priv);
1436 }
1437
1438 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1439 {
1440         u32 cdctl, expected;
1441
1442         intel_update_cdclk(dev_priv);
1443         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1444
1445         if (dev_priv->cdclk.hw.vco == 0 ||
1446             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1447                 goto sanitize;
1448
1449         /* DPLL okay; verify the cdclock
1450          *
1451          * Some BIOS versions leave an incorrect decimal frequency value and
1452          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1453          * so sanitize this register.
1454          */
1455         cdctl = I915_READ(CDCLK_CTL);
1456         /*
1457          * Let's ignore the pipe field, since BIOS could have configured the
1458          * dividers both synching to an active pipe, or asynchronously
1459          * (PIPE_NONE).
1460          */
1461         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1462
1463         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1464                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1465         /*
1466          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1467          * enable otherwise.
1468          */
1469         if (dev_priv->cdclk.hw.cdclk >= 500000)
1470                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1471
1472         if (cdctl == expected)
1473                 /* All well; nothing to sanitize */
1474                 return;
1475
1476 sanitize:
1477         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1478
1479         /* force cdclk programming */
1480         dev_priv->cdclk.hw.cdclk = 0;
1481
1482         /* force full PLL disable + enable */
1483         dev_priv->cdclk.hw.vco = -1;
1484 }
1485
1486 static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1487 {
1488         struct intel_cdclk_state cdclk_state;
1489
1490         bxt_sanitize_cdclk(dev_priv);
1491
1492         if (dev_priv->cdclk.hw.cdclk != 0 &&
1493             dev_priv->cdclk.hw.vco != 0)
1494                 return;
1495
1496         cdclk_state = dev_priv->cdclk.hw;
1497
1498         /*
1499          * FIXME:
1500          * - The initial CDCLK needs to be read from VBT.
1501          *   Need to make this change after VBT has changes for BXT.
1502          */
1503         if (IS_GEMINILAKE(dev_priv)) {
1504                 cdclk_state.cdclk = glk_calc_cdclk(0);
1505                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1506         } else {
1507                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1508                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1509         }
1510         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1511
1512         bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1513 }
1514
1515 static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1516 {
1517         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1518
1519         cdclk_state.cdclk = cdclk_state.bypass;
1520         cdclk_state.vco = 0;
1521         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1522
1523         bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1524 }
1525
1526 static int cnl_calc_cdclk(int min_cdclk)
1527 {
1528         if (min_cdclk > 336000)
1529                 return 528000;
1530         else if (min_cdclk > 168000)
1531                 return 336000;
1532         else
1533                 return 168000;
1534 }
1535
1536 static u8 cnl_calc_voltage_level(int cdclk)
1537 {
1538         switch (cdclk) {
1539         default:
1540         case 168000:
1541                 return 0;
1542         case 336000:
1543                 return 1;
1544         case 528000:
1545                 return 2;
1546         }
1547 }
1548
1549 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1550                                  struct intel_cdclk_state *cdclk_state)
1551 {
1552         u32 val;
1553
1554         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1555                 cdclk_state->ref = 24000;
1556         else
1557                 cdclk_state->ref = 19200;
1558
1559         cdclk_state->vco = 0;
1560
1561         val = I915_READ(BXT_DE_PLL_ENABLE);
1562         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1563                 return;
1564
1565         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1566                 return;
1567
1568         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1569 }
1570
1571 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1572                          struct intel_cdclk_state *cdclk_state)
1573 {
1574         u32 divider;
1575         int div;
1576
1577         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1578
1579         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1580
1581         if (cdclk_state->vco == 0)
1582                 goto out;
1583
1584         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1585
1586         switch (divider) {
1587         case BXT_CDCLK_CD2X_DIV_SEL_1:
1588                 div = 2;
1589                 break;
1590         case BXT_CDCLK_CD2X_DIV_SEL_2:
1591                 div = 4;
1592                 break;
1593         default:
1594                 MISSING_CASE(divider);
1595                 return;
1596         }
1597
1598         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1599
1600  out:
1601         /*
1602          * Can't read this out :( Let's assume it's
1603          * at least what the CDCLK frequency requires.
1604          */
1605         cdclk_state->voltage_level =
1606                 cnl_calc_voltage_level(cdclk_state->cdclk);
1607 }
1608
1609 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1610 {
1611         u32 val;
1612
1613         val = I915_READ(BXT_DE_PLL_ENABLE);
1614         val &= ~BXT_DE_PLL_PLL_ENABLE;
1615         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1616
1617         /* Timeout 200us */
1618         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1619                 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
1620
1621         dev_priv->cdclk.hw.vco = 0;
1622 }
1623
1624 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1625 {
1626         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1627         u32 val;
1628
1629         val = CNL_CDCLK_PLL_RATIO(ratio);
1630         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1631
1632         val |= BXT_DE_PLL_PLL_ENABLE;
1633         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1634
1635         /* Timeout 200us */
1636         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1637                 DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
1638
1639         dev_priv->cdclk.hw.vco = vco;
1640 }
1641
1642 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1643                           const struct intel_cdclk_state *cdclk_state,
1644                           enum pipe pipe)
1645 {
1646         int cdclk = cdclk_state->cdclk;
1647         int vco = cdclk_state->vco;
1648         u32 val, divider;
1649         int ret;
1650
1651         mutex_lock(&dev_priv->pcu_lock);
1652         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1653                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1654                                 SKL_CDCLK_READY_FOR_CHANGE,
1655                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1656         mutex_unlock(&dev_priv->pcu_lock);
1657         if (ret) {
1658                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1659                           ret);
1660                 return;
1661         }
1662
1663         /* cdclk = vco / 2 / div{1,2} */
1664         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1665         default:
1666                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1667                 WARN_ON(vco != 0);
1668                 /* fall through */
1669         case 2:
1670                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1671                 break;
1672         case 4:
1673                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1674                 break;
1675         }
1676
1677         if (dev_priv->cdclk.hw.vco != 0 &&
1678             dev_priv->cdclk.hw.vco != vco)
1679                 cnl_cdclk_pll_disable(dev_priv);
1680
1681         if (dev_priv->cdclk.hw.vco != vco)
1682                 cnl_cdclk_pll_enable(dev_priv, vco);
1683
1684         val = divider | skl_cdclk_decimal(cdclk);
1685         if (pipe == INVALID_PIPE)
1686                 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1687         else
1688                 val |= BXT_CDCLK_CD2X_PIPE(pipe);
1689         I915_WRITE(CDCLK_CTL, val);
1690
1691         if (pipe != INVALID_PIPE)
1692                 intel_wait_for_vblank(dev_priv, pipe);
1693
1694         /* inform PCU of the change */
1695         mutex_lock(&dev_priv->pcu_lock);
1696         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1697                                 cdclk_state->voltage_level);
1698         mutex_unlock(&dev_priv->pcu_lock);
1699
1700         intel_update_cdclk(dev_priv);
1701
1702         /*
1703          * Can't read out the voltage level :(
1704          * Let's just assume everything is as expected.
1705          */
1706         dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1707 }
1708
1709 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1710 {
1711         int ratio;
1712
1713         if (cdclk == dev_priv->cdclk.hw.bypass)
1714                 return 0;
1715
1716         switch (cdclk) {
1717         default:
1718                 MISSING_CASE(cdclk);
1719                 /* fall through */
1720         case 168000:
1721         case 336000:
1722                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1723                 break;
1724         case 528000:
1725                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1726                 break;
1727         }
1728
1729         return dev_priv->cdclk.hw.ref * ratio;
1730 }
1731
1732 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1733 {
1734         u32 cdctl, expected;
1735
1736         intel_update_cdclk(dev_priv);
1737         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1738
1739         if (dev_priv->cdclk.hw.vco == 0 ||
1740             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1741                 goto sanitize;
1742
1743         /* DPLL okay; verify the cdclock
1744          *
1745          * Some BIOS versions leave an incorrect decimal frequency value and
1746          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1747          * so sanitize this register.
1748          */
1749         cdctl = I915_READ(CDCLK_CTL);
1750         /*
1751          * Let's ignore the pipe field, since BIOS could have configured the
1752          * dividers both synching to an active pipe, or asynchronously
1753          * (PIPE_NONE).
1754          */
1755         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1756
1757         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1758                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1759
1760         if (cdctl == expected)
1761                 /* All well; nothing to sanitize */
1762                 return;
1763
1764 sanitize:
1765         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1766
1767         /* force cdclk programming */
1768         dev_priv->cdclk.hw.cdclk = 0;
1769
1770         /* force full PLL disable + enable */
1771         dev_priv->cdclk.hw.vco = -1;
1772 }
1773
1774 static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1775 {
1776         int ranges_24[] = { 312000, 552000, 648000 };
1777         int ranges_19_38[] = { 307200, 556800, 652800 };
1778         int *ranges;
1779
1780         switch (ref) {
1781         default:
1782                 MISSING_CASE(ref);
1783                 /* fall through */
1784         case 24000:
1785                 ranges = ranges_24;
1786                 break;
1787         case 19200:
1788         case 38400:
1789                 ranges = ranges_19_38;
1790                 break;
1791         }
1792
1793         if (min_cdclk > ranges[1])
1794                 return ranges[2];
1795         else if (min_cdclk > ranges[0])
1796                 return ranges[1];
1797         else
1798                 return ranges[0];
1799 }
1800
1801 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1802 {
1803         int ratio;
1804
1805         if (cdclk == dev_priv->cdclk.hw.bypass)
1806                 return 0;
1807
1808         switch (cdclk) {
1809         default:
1810                 MISSING_CASE(cdclk);
1811                 /* fall through */
1812         case 307200:
1813         case 556800:
1814         case 652800:
1815                 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1816                         dev_priv->cdclk.hw.ref != 38400);
1817                 break;
1818         case 312000:
1819         case 552000:
1820         case 648000:
1821                 WARN_ON(dev_priv->cdclk.hw.ref != 24000);
1822         }
1823
1824         ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
1825
1826         return dev_priv->cdclk.hw.ref * ratio;
1827 }
1828
1829 static void icl_set_cdclk(struct drm_i915_private *dev_priv,
1830                           const struct intel_cdclk_state *cdclk_state,
1831                           enum pipe pipe)
1832 {
1833         unsigned int cdclk = cdclk_state->cdclk;
1834         unsigned int vco = cdclk_state->vco;
1835         int ret;
1836
1837         mutex_lock(&dev_priv->pcu_lock);
1838         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1839                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1840                                 SKL_CDCLK_READY_FOR_CHANGE,
1841                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1842         mutex_unlock(&dev_priv->pcu_lock);
1843         if (ret) {
1844                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1845                           ret);
1846                 return;
1847         }
1848
1849         if (dev_priv->cdclk.hw.vco != 0 &&
1850             dev_priv->cdclk.hw.vco != vco)
1851                 cnl_cdclk_pll_disable(dev_priv);
1852
1853         if (dev_priv->cdclk.hw.vco != vco)
1854                 cnl_cdclk_pll_enable(dev_priv, vco);
1855
1856         /*
1857          * On ICL CD2X_DIV can only be 1, so we'll never end up changing the
1858          * divider here synchronized to a pipe while CDCLK is on, nor will we
1859          * need the corresponding vblank wait.
1860          */
1861         I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
1862                               skl_cdclk_decimal(cdclk));
1863
1864         mutex_lock(&dev_priv->pcu_lock);
1865         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1866                                 cdclk_state->voltage_level);
1867         mutex_unlock(&dev_priv->pcu_lock);
1868
1869         intel_update_cdclk(dev_priv);
1870
1871         /*
1872          * Can't read out the voltage level :(
1873          * Let's just assume everything is as expected.
1874          */
1875         dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1876 }
1877
1878 static u8 icl_calc_voltage_level(int cdclk)
1879 {
1880         switch (cdclk) {
1881         case 50000:
1882         case 307200:
1883         case 312000:
1884                 return 0;
1885         case 556800:
1886         case 552000:
1887                 return 1;
1888         default:
1889                 MISSING_CASE(cdclk);
1890                 /* fall through */
1891         case 652800:
1892         case 648000:
1893                 return 2;
1894         }
1895 }
1896
1897 static void icl_get_cdclk(struct drm_i915_private *dev_priv,
1898                           struct intel_cdclk_state *cdclk_state)
1899 {
1900         u32 val;
1901
1902         cdclk_state->bypass = 50000;
1903
1904         val = I915_READ(SKL_DSSM);
1905         switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
1906         default:
1907                 MISSING_CASE(val);
1908                 /* fall through */
1909         case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1910                 cdclk_state->ref = 24000;
1911                 break;
1912         case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1913                 cdclk_state->ref = 19200;
1914                 break;
1915         case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1916                 cdclk_state->ref = 38400;
1917                 break;
1918         }
1919
1920         val = I915_READ(BXT_DE_PLL_ENABLE);
1921         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1922             (val & BXT_DE_PLL_LOCK) == 0) {
1923                 /*
1924                  * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1925                  * setting it to zero is a way to signal that.
1926                  */
1927                 cdclk_state->vco = 0;
1928                 cdclk_state->cdclk = cdclk_state->bypass;
1929                 goto out;
1930         }
1931
1932         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1933
1934         val = I915_READ(CDCLK_CTL);
1935         WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
1936
1937         cdclk_state->cdclk = cdclk_state->vco / 2;
1938
1939 out:
1940         /*
1941          * Can't read this out :( Let's assume it's
1942          * at least what the CDCLK frequency requires.
1943          */
1944         cdclk_state->voltage_level =
1945                 icl_calc_voltage_level(cdclk_state->cdclk);
1946 }
1947
1948 static void icl_init_cdclk(struct drm_i915_private *dev_priv)
1949 {
1950         struct intel_cdclk_state sanitized_state;
1951         u32 val;
1952
1953         /* This sets dev_priv->cdclk.hw. */
1954         intel_update_cdclk(dev_priv);
1955         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1956
1957         /* This means CDCLK disabled. */
1958         if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1959                 goto sanitize;
1960
1961         val = I915_READ(CDCLK_CTL);
1962
1963         if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
1964                 goto sanitize;
1965
1966         if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
1967             skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
1968                 goto sanitize;
1969
1970         return;
1971
1972 sanitize:
1973         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1974
1975         sanitized_state.ref = dev_priv->cdclk.hw.ref;
1976         sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
1977         sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
1978                                                      sanitized_state.cdclk);
1979         sanitized_state.voltage_level =
1980                                 icl_calc_voltage_level(sanitized_state.cdclk);
1981
1982         icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
1983 }
1984
1985 static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
1986 {
1987         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1988
1989         cdclk_state.cdclk = cdclk_state.bypass;
1990         cdclk_state.vco = 0;
1991         cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
1992
1993         icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1994 }
1995
1996 static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1997 {
1998         struct intel_cdclk_state cdclk_state;
1999
2000         cnl_sanitize_cdclk(dev_priv);
2001
2002         if (dev_priv->cdclk.hw.cdclk != 0 &&
2003             dev_priv->cdclk.hw.vco != 0)
2004                 return;
2005
2006         cdclk_state = dev_priv->cdclk.hw;
2007
2008         cdclk_state.cdclk = cnl_calc_cdclk(0);
2009         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
2010         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
2011
2012         cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
2013 }
2014
2015 static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
2016 {
2017         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2018
2019         cdclk_state.cdclk = cdclk_state.bypass;
2020         cdclk_state.vco = 0;
2021         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
2022
2023         cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
2024 }
2025
2026 /**
2027  * intel_cdclk_init - Initialize CDCLK
2028  * @i915: i915 device
2029  *
2030  * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
2031  * sanitizing the state of the hardware if needed. This is generally done only
2032  * during the display core initialization sequence, after which the DMC will
2033  * take care of turning CDCLK off/on as needed.
2034  */
2035 void intel_cdclk_init(struct drm_i915_private *i915)
2036 {
2037         if (INTEL_GEN(i915) >= 11)
2038                 icl_init_cdclk(i915);
2039         else if (IS_CANNONLAKE(i915))
2040                 cnl_init_cdclk(i915);
2041         else if (IS_GEN9_BC(i915))
2042                 skl_init_cdclk(i915);
2043         else if (IS_GEN9_LP(i915))
2044                 bxt_init_cdclk(i915);
2045 }
2046
2047 /**
2048  * intel_cdclk_uninit - Uninitialize CDCLK
2049  * @i915: i915 device
2050  *
2051  * Uninitialize CDCLK. This is done only during the display core
2052  * uninitialization sequence.
2053  */
2054 void intel_cdclk_uninit(struct drm_i915_private *i915)
2055 {
2056         if (INTEL_GEN(i915) >= 11)
2057                 icl_uninit_cdclk(i915);
2058         else if (IS_CANNONLAKE(i915))
2059                 cnl_uninit_cdclk(i915);
2060         else if (IS_GEN9_BC(i915))
2061                 skl_uninit_cdclk(i915);
2062         else if (IS_GEN9_LP(i915))
2063                 bxt_uninit_cdclk(i915);
2064 }
2065
2066 /**
2067  * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
2068  * @a: first CDCLK state
2069  * @b: second CDCLK state
2070  *
2071  * Returns:
2072  * True if the CDCLK states require pipes to be off during reprogramming, false if not.
2073  */
2074 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
2075                                const struct intel_cdclk_state *b)
2076 {
2077         return a->cdclk != b->cdclk ||
2078                 a->vco != b->vco ||
2079                 a->ref != b->ref;
2080 }
2081
2082 /**
2083  * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update
2084  * @dev_priv: Not a CDCLK state, it's the drm_i915_private!
2085  * @a: first CDCLK state
2086  * @b: second CDCLK state
2087  *
2088  * Returns:
2089  * True if the CDCLK states require just a cd2x divider update, false if not.
2090  */
2091 bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
2092                                    const struct intel_cdclk_state *a,
2093                                    const struct intel_cdclk_state *b)
2094 {
2095         /* Older hw doesn't have the capability */
2096         if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
2097                 return false;
2098
2099         return a->cdclk != b->cdclk &&
2100                 a->vco == b->vco &&
2101                 a->ref == b->ref;
2102 }
2103
2104 /**
2105  * intel_cdclk_changed - Determine if two CDCLK states are different
2106  * @a: first CDCLK state
2107  * @b: second CDCLK state
2108  *
2109  * Returns:
2110  * True if the CDCLK states don't match, false if they do.
2111  */
2112 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
2113                          const struct intel_cdclk_state *b)
2114 {
2115         return intel_cdclk_needs_modeset(a, b) ||
2116                 a->voltage_level != b->voltage_level;
2117 }
2118
2119 /**
2120  * intel_cdclk_swap_state - make atomic CDCLK configuration effective
2121  * @state: atomic state
2122  *
2123  * This is the CDCLK version of drm_atomic_helper_swap_state() since the
2124  * helper does not handle driver-specific global state.
2125  *
2126  * Similarly to the atomic helpers this function does a complete swap,
2127  * i.e. it also puts the old state into @state. This is used by the commit
2128  * code to determine how CDCLK has changed (for instance did it increase or
2129  * decrease).
2130  */
2131 void intel_cdclk_swap_state(struct intel_atomic_state *state)
2132 {
2133         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2134
2135         swap(state->cdclk.logical, dev_priv->cdclk.logical);
2136         swap(state->cdclk.actual, dev_priv->cdclk.actual);
2137 }
2138
2139 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
2140                             const char *context)
2141 {
2142         DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2143                          context, cdclk_state->cdclk, cdclk_state->vco,
2144                          cdclk_state->ref, cdclk_state->bypass,
2145                          cdclk_state->voltage_level);
2146 }
2147
2148 /**
2149  * intel_set_cdclk - Push the CDCLK state to the hardware
2150  * @dev_priv: i915 device
2151  * @cdclk_state: new CDCLK state
2152  * @pipe: pipe with which to synchronize the update
2153  *
2154  * Program the hardware based on the passed in CDCLK state,
2155  * if necessary.
2156  */
2157 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
2158                             const struct intel_cdclk_state *cdclk_state,
2159                             enum pipe pipe)
2160 {
2161         if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
2162                 return;
2163
2164         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
2165                 return;
2166
2167         intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
2168
2169         dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe);
2170
2171         if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
2172                  "cdclk state doesn't match!\n")) {
2173                 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
2174                 intel_dump_cdclk_state(cdclk_state, "[sw state]");
2175         }
2176 }
2177
2178 /**
2179  * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2180  * @dev_priv: i915 device
2181  * @old_state: old CDCLK state
2182  * @new_state: new CDCLK state
2183  * @pipe: pipe with which to synchronize the update
2184  *
2185  * Program the hardware before updating the HW plane state based on the passed
2186  * in CDCLK state, if necessary.
2187  */
2188 void
2189 intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
2190                                  const struct intel_cdclk_state *old_state,
2191                                  const struct intel_cdclk_state *new_state,
2192                                  enum pipe pipe)
2193 {
2194         if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk)
2195                 intel_set_cdclk(dev_priv, new_state, pipe);
2196 }
2197
2198 /**
2199  * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2200  * @dev_priv: i915 device
2201  * @old_state: old CDCLK state
2202  * @new_state: new CDCLK state
2203  * @pipe: pipe with which to synchronize the update
2204  *
2205  * Program the hardware after updating the HW plane state based on the passed
2206  * in CDCLK state, if necessary.
2207  */
2208 void
2209 intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
2210                                   const struct intel_cdclk_state *old_state,
2211                                   const struct intel_cdclk_state *new_state,
2212                                   enum pipe pipe)
2213 {
2214         if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk)
2215                 intel_set_cdclk(dev_priv, new_state, pipe);
2216 }
2217
2218 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2219                                      int pixel_rate)
2220 {
2221         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2222                 return DIV_ROUND_UP(pixel_rate, 2);
2223         else if (IS_GEN(dev_priv, 9) ||
2224                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2225                 return pixel_rate;
2226         else if (IS_CHERRYVIEW(dev_priv))
2227                 return DIV_ROUND_UP(pixel_rate * 100, 95);
2228         else
2229                 return DIV_ROUND_UP(pixel_rate * 100, 90);
2230 }
2231
2232 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2233 {
2234         struct drm_i915_private *dev_priv =
2235                 to_i915(crtc_state->base.crtc->dev);
2236         int min_cdclk;
2237
2238         if (!crtc_state->base.enable)
2239                 return 0;
2240
2241         min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
2242
2243         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2244         if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2245                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2246
2247         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2248          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2249          * there may be audio corruption or screen corruption." This cdclk
2250          * restriction for GLK is 316.8 MHz.
2251          */
2252         if (intel_crtc_has_dp_encoder(crtc_state) &&
2253             crtc_state->has_audio &&
2254             crtc_state->port_clock >= 540000 &&
2255             crtc_state->lane_count == 4) {
2256                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2257                         /* Display WA #1145: glk,cnl */
2258                         min_cdclk = max(316800, min_cdclk);
2259                 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
2260                         /* Display WA #1144: skl,bxt */
2261                         min_cdclk = max(432000, min_cdclk);
2262                 }
2263         }
2264
2265         /*
2266          * According to BSpec, "The CD clock frequency must be at least twice
2267          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2268          */
2269         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
2270                 min_cdclk = max(2 * 96000, min_cdclk);
2271
2272         /*
2273          * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2274          * than 320000KHz.
2275          */
2276         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2277             IS_VALLEYVIEW(dev_priv))
2278                 min_cdclk = max(320000, min_cdclk);
2279
2280         if (min_cdclk > dev_priv->max_cdclk_freq) {
2281                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2282                               min_cdclk, dev_priv->max_cdclk_freq);
2283                 return -EINVAL;
2284         }
2285
2286         return min_cdclk;
2287 }
2288
2289 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
2290 {
2291         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2292         struct drm_i915_private *dev_priv = to_i915(state->dev);
2293         struct intel_crtc *crtc;
2294         struct intel_crtc_state *crtc_state;
2295         int min_cdclk, i;
2296         enum pipe pipe;
2297
2298         memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
2299                sizeof(intel_state->min_cdclk));
2300
2301         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2302                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2303                 if (min_cdclk < 0)
2304                         return min_cdclk;
2305
2306                 intel_state->min_cdclk[i] = min_cdclk;
2307         }
2308
2309         min_cdclk = intel_state->cdclk.force_min_cdclk;
2310         for_each_pipe(dev_priv, pipe)
2311                 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
2312
2313         return min_cdclk;
2314 }
2315
2316 /*
2317  * Note that this functions assumes that 0 is
2318  * the lowest voltage value, and higher values
2319  * correspond to increasingly higher voltages.
2320  *
2321  * Should that relationship no longer hold on
2322  * future platforms this code will need to be
2323  * adjusted.
2324  */
2325 static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2326 {
2327         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2328         struct intel_crtc *crtc;
2329         struct intel_crtc_state *crtc_state;
2330         u8 min_voltage_level;
2331         int i;
2332         enum pipe pipe;
2333
2334         memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2335                sizeof(state->min_voltage_level));
2336
2337         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2338                 if (crtc_state->base.enable)
2339                         state->min_voltage_level[i] =
2340                                 crtc_state->min_voltage_level;
2341                 else
2342                         state->min_voltage_level[i] = 0;
2343         }
2344
2345         min_voltage_level = 0;
2346         for_each_pipe(dev_priv, pipe)
2347                 min_voltage_level = max(state->min_voltage_level[pipe],
2348                                         min_voltage_level);
2349
2350         return min_voltage_level;
2351 }
2352
2353 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
2354 {
2355         struct drm_i915_private *dev_priv = to_i915(state->dev);
2356         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2357         int min_cdclk, cdclk;
2358
2359         min_cdclk = intel_compute_min_cdclk(state);
2360         if (min_cdclk < 0)
2361                 return min_cdclk;
2362
2363         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2364
2365         intel_state->cdclk.logical.cdclk = cdclk;
2366         intel_state->cdclk.logical.voltage_level =
2367                 vlv_calc_voltage_level(dev_priv, cdclk);
2368
2369         if (!intel_state->active_crtcs) {
2370                 cdclk = vlv_calc_cdclk(dev_priv,
2371                                        intel_state->cdclk.force_min_cdclk);
2372
2373                 intel_state->cdclk.actual.cdclk = cdclk;
2374                 intel_state->cdclk.actual.voltage_level =
2375                         vlv_calc_voltage_level(dev_priv, cdclk);
2376         } else {
2377                 intel_state->cdclk.actual =
2378                         intel_state->cdclk.logical;
2379         }
2380
2381         return 0;
2382 }
2383
2384 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
2385 {
2386         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2387         int min_cdclk, cdclk;
2388
2389         min_cdclk = intel_compute_min_cdclk(state);
2390         if (min_cdclk < 0)
2391                 return min_cdclk;
2392
2393         /*
2394          * FIXME should also account for plane ratio
2395          * once 64bpp pixel formats are supported.
2396          */
2397         cdclk = bdw_calc_cdclk(min_cdclk);
2398
2399         intel_state->cdclk.logical.cdclk = cdclk;
2400         intel_state->cdclk.logical.voltage_level =
2401                 bdw_calc_voltage_level(cdclk);
2402
2403         if (!intel_state->active_crtcs) {
2404                 cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2405
2406                 intel_state->cdclk.actual.cdclk = cdclk;
2407                 intel_state->cdclk.actual.voltage_level =
2408                         bdw_calc_voltage_level(cdclk);
2409         } else {
2410                 intel_state->cdclk.actual =
2411                         intel_state->cdclk.logical;
2412         }
2413
2414         return 0;
2415 }
2416
2417 static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
2418 {
2419         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
2420         struct intel_crtc *crtc;
2421         struct intel_crtc_state *crtc_state;
2422         int vco, i;
2423
2424         vco = intel_state->cdclk.logical.vco;
2425         if (!vco)
2426                 vco = dev_priv->skl_preferred_vco_freq;
2427
2428         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2429                 if (!crtc_state->base.enable)
2430                         continue;
2431
2432                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2433                         continue;
2434
2435                 /*
2436                  * DPLL0 VCO may need to be adjusted to get the correct
2437                  * clock for eDP. This will affect cdclk as well.
2438                  */
2439                 switch (crtc_state->port_clock / 2) {
2440                 case 108000:
2441                 case 216000:
2442                         vco = 8640000;
2443                         break;
2444                 default:
2445                         vco = 8100000;
2446                         break;
2447                 }
2448         }
2449
2450         return vco;
2451 }
2452
2453 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2454 {
2455         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2456         int min_cdclk, cdclk, vco;
2457
2458         min_cdclk = intel_compute_min_cdclk(state);
2459         if (min_cdclk < 0)
2460                 return min_cdclk;
2461
2462         vco = skl_dpll0_vco(intel_state);
2463
2464         /*
2465          * FIXME should also account for plane ratio
2466          * once 64bpp pixel formats are supported.
2467          */
2468         cdclk = skl_calc_cdclk(min_cdclk, vco);
2469
2470         intel_state->cdclk.logical.vco = vco;
2471         intel_state->cdclk.logical.cdclk = cdclk;
2472         intel_state->cdclk.logical.voltage_level =
2473                 skl_calc_voltage_level(cdclk);
2474
2475         if (!intel_state->active_crtcs) {
2476                 cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
2477
2478                 intel_state->cdclk.actual.vco = vco;
2479                 intel_state->cdclk.actual.cdclk = cdclk;
2480                 intel_state->cdclk.actual.voltage_level =
2481                         skl_calc_voltage_level(cdclk);
2482         } else {
2483                 intel_state->cdclk.actual =
2484                         intel_state->cdclk.logical;
2485         }
2486
2487         return 0;
2488 }
2489
2490 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
2491 {
2492         struct drm_i915_private *dev_priv = to_i915(state->dev);
2493         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2494         int min_cdclk, cdclk, vco;
2495
2496         min_cdclk = intel_compute_min_cdclk(state);
2497         if (min_cdclk < 0)
2498                 return min_cdclk;
2499
2500         if (IS_GEMINILAKE(dev_priv)) {
2501                 cdclk = glk_calc_cdclk(min_cdclk);
2502                 vco = glk_de_pll_vco(dev_priv, cdclk);
2503         } else {
2504                 cdclk = bxt_calc_cdclk(min_cdclk);
2505                 vco = bxt_de_pll_vco(dev_priv, cdclk);
2506         }
2507
2508         intel_state->cdclk.logical.vco = vco;
2509         intel_state->cdclk.logical.cdclk = cdclk;
2510         intel_state->cdclk.logical.voltage_level =
2511                 bxt_calc_voltage_level(cdclk);
2512
2513         if (!intel_state->active_crtcs) {
2514                 if (IS_GEMINILAKE(dev_priv)) {
2515                         cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2516                         vco = glk_de_pll_vco(dev_priv, cdclk);
2517                 } else {
2518                         cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2519                         vco = bxt_de_pll_vco(dev_priv, cdclk);
2520                 }
2521
2522                 intel_state->cdclk.actual.vco = vco;
2523                 intel_state->cdclk.actual.cdclk = cdclk;
2524                 intel_state->cdclk.actual.voltage_level =
2525                         bxt_calc_voltage_level(cdclk);
2526         } else {
2527                 intel_state->cdclk.actual =
2528                         intel_state->cdclk.logical;
2529         }
2530
2531         return 0;
2532 }
2533
2534 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2535 {
2536         struct drm_i915_private *dev_priv = to_i915(state->dev);
2537         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2538         int min_cdclk, cdclk, vco;
2539
2540         min_cdclk = intel_compute_min_cdclk(state);
2541         if (min_cdclk < 0)
2542                 return min_cdclk;
2543
2544         cdclk = cnl_calc_cdclk(min_cdclk);
2545         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2546
2547         intel_state->cdclk.logical.vco = vco;
2548         intel_state->cdclk.logical.cdclk = cdclk;
2549         intel_state->cdclk.logical.voltage_level =
2550                 max(cnl_calc_voltage_level(cdclk),
2551                     cnl_compute_min_voltage_level(intel_state));
2552
2553         if (!intel_state->active_crtcs) {
2554                 cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2555                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2556
2557                 intel_state->cdclk.actual.vco = vco;
2558                 intel_state->cdclk.actual.cdclk = cdclk;
2559                 intel_state->cdclk.actual.voltage_level =
2560                         cnl_calc_voltage_level(cdclk);
2561         } else {
2562                 intel_state->cdclk.actual =
2563                         intel_state->cdclk.logical;
2564         }
2565
2566         return 0;
2567 }
2568
2569 static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
2570 {
2571         struct drm_i915_private *dev_priv = to_i915(state->dev);
2572         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2573         unsigned int ref = intel_state->cdclk.logical.ref;
2574         int min_cdclk, cdclk, vco;
2575
2576         min_cdclk = intel_compute_min_cdclk(state);
2577         if (min_cdclk < 0)
2578                 return min_cdclk;
2579
2580         cdclk = icl_calc_cdclk(min_cdclk, ref);
2581         vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2582
2583         intel_state->cdclk.logical.vco = vco;
2584         intel_state->cdclk.logical.cdclk = cdclk;
2585         intel_state->cdclk.logical.voltage_level =
2586                 max(icl_calc_voltage_level(cdclk),
2587                     cnl_compute_min_voltage_level(intel_state));
2588
2589         if (!intel_state->active_crtcs) {
2590                 cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
2591                 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2592
2593                 intel_state->cdclk.actual.vco = vco;
2594                 intel_state->cdclk.actual.cdclk = cdclk;
2595                 intel_state->cdclk.actual.voltage_level =
2596                         icl_calc_voltage_level(cdclk);
2597         } else {
2598                 intel_state->cdclk.actual = intel_state->cdclk.logical;
2599         }
2600
2601         return 0;
2602 }
2603
2604 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2605 {
2606         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2607
2608         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2609                 return 2 * max_cdclk_freq;
2610         else if (IS_GEN(dev_priv, 9) ||
2611                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2612                 return max_cdclk_freq;
2613         else if (IS_CHERRYVIEW(dev_priv))
2614                 return max_cdclk_freq*95/100;
2615         else if (INTEL_GEN(dev_priv) < 4)
2616                 return 2*max_cdclk_freq*90/100;
2617         else
2618                 return max_cdclk_freq*90/100;
2619 }
2620
2621 /**
2622  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2623  * @dev_priv: i915 device
2624  *
2625  * Determine the maximum CDCLK frequency the platform supports, and also
2626  * derive the maximum dot clock frequency the maximum CDCLK frequency
2627  * allows.
2628  */
2629 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2630 {
2631         if (INTEL_GEN(dev_priv) >= 11) {
2632                 if (dev_priv->cdclk.hw.ref == 24000)
2633                         dev_priv->max_cdclk_freq = 648000;
2634                 else
2635                         dev_priv->max_cdclk_freq = 652800;
2636         } else if (IS_CANNONLAKE(dev_priv)) {
2637                 dev_priv->max_cdclk_freq = 528000;
2638         } else if (IS_GEN9_BC(dev_priv)) {
2639                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2640                 int max_cdclk, vco;
2641
2642                 vco = dev_priv->skl_preferred_vco_freq;
2643                 WARN_ON(vco != 8100000 && vco != 8640000);
2644
2645                 /*
2646                  * Use the lower (vco 8640) cdclk values as a
2647                  * first guess. skl_calc_cdclk() will correct it
2648                  * if the preferred vco is 8100 instead.
2649                  */
2650                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2651                         max_cdclk = 617143;
2652                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2653                         max_cdclk = 540000;
2654                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2655                         max_cdclk = 432000;
2656                 else
2657                         max_cdclk = 308571;
2658
2659                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2660         } else if (IS_GEMINILAKE(dev_priv)) {
2661                 dev_priv->max_cdclk_freq = 316800;
2662         } else if (IS_BROXTON(dev_priv)) {
2663                 dev_priv->max_cdclk_freq = 624000;
2664         } else if (IS_BROADWELL(dev_priv))  {
2665                 /*
2666                  * FIXME with extra cooling we can allow
2667                  * 540 MHz for ULX and 675 Mhz for ULT.
2668                  * How can we know if extra cooling is
2669                  * available? PCI ID, VTB, something else?
2670                  */
2671                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2672                         dev_priv->max_cdclk_freq = 450000;
2673                 else if (IS_BDW_ULX(dev_priv))
2674                         dev_priv->max_cdclk_freq = 450000;
2675                 else if (IS_BDW_ULT(dev_priv))
2676                         dev_priv->max_cdclk_freq = 540000;
2677                 else
2678                         dev_priv->max_cdclk_freq = 675000;
2679         } else if (IS_CHERRYVIEW(dev_priv)) {
2680                 dev_priv->max_cdclk_freq = 320000;
2681         } else if (IS_VALLEYVIEW(dev_priv)) {
2682                 dev_priv->max_cdclk_freq = 400000;
2683         } else {
2684                 /* otherwise assume cdclk is fixed */
2685                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2686         }
2687
2688         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2689
2690         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2691                          dev_priv->max_cdclk_freq);
2692
2693         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2694                          dev_priv->max_dotclk_freq);
2695 }
2696
2697 /**
2698  * intel_update_cdclk - Determine the current CDCLK frequency
2699  * @dev_priv: i915 device
2700  *
2701  * Determine the current CDCLK frequency.
2702  */
2703 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2704 {
2705         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2706
2707         /*
2708          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2709          * Programmng [sic] note: bit[9:2] should be programmed to the number
2710          * of cdclk that generates 4MHz reference clock freq which is used to
2711          * generate GMBus clock. This will vary with the cdclk freq.
2712          */
2713         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2714                 I915_WRITE(GMBUSFREQ_VLV,
2715                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2716 }
2717
2718 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2719 {
2720         u32 rawclk;
2721         int divider, fraction;
2722
2723         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2724                 /* 24 MHz */
2725                 divider = 24000;
2726                 fraction = 0;
2727         } else {
2728                 /* 19.2 MHz */
2729                 divider = 19000;
2730                 fraction = 200;
2731         }
2732
2733         rawclk = CNP_RAWCLK_DIV(divider / 1000);
2734         if (fraction) {
2735                 int numerator = 1;
2736
2737                 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2738                                                            fraction) - 1);
2739                 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2740                         rawclk |= ICP_RAWCLK_NUM(numerator);
2741         }
2742
2743         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2744         return divider + fraction;
2745 }
2746
2747 static int pch_rawclk(struct drm_i915_private *dev_priv)
2748 {
2749         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2750 }
2751
2752 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2753 {
2754         /* RAWCLK_FREQ_VLV register updated from power well code */
2755         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2756                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2757 }
2758
2759 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2760 {
2761         u32 clkcfg;
2762
2763         /* hrawclock is 1/4 the FSB frequency */
2764         clkcfg = I915_READ(CLKCFG);
2765         switch (clkcfg & CLKCFG_FSB_MASK) {
2766         case CLKCFG_FSB_400:
2767                 return 100000;
2768         case CLKCFG_FSB_533:
2769                 return 133333;
2770         case CLKCFG_FSB_667:
2771                 return 166667;
2772         case CLKCFG_FSB_800:
2773                 return 200000;
2774         case CLKCFG_FSB_1067:
2775         case CLKCFG_FSB_1067_ALT:
2776                 return 266667;
2777         case CLKCFG_FSB_1333:
2778         case CLKCFG_FSB_1333_ALT:
2779                 return 333333;
2780         default:
2781                 return 133333;
2782         }
2783 }
2784
2785 /**
2786  * intel_update_rawclk - Determine the current RAWCLK frequency
2787  * @dev_priv: i915 device
2788  *
2789  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2790  * frequency clock so this needs to done only once.
2791  */
2792 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2793 {
2794         if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
2795                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2796         else if (HAS_PCH_SPLIT(dev_priv))
2797                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2798         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2799                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2800         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2801                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2802         else
2803                 /* no rawclk on other platforms, or no need to know it */
2804                 return;
2805
2806         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2807 }
2808
2809 /**
2810  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2811  * @dev_priv: i915 device
2812  */
2813 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2814 {
2815         if (INTEL_GEN(dev_priv) >= 11) {
2816                 dev_priv->display.set_cdclk = icl_set_cdclk;
2817                 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
2818         } else if (IS_CANNONLAKE(dev_priv)) {
2819                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2820                 dev_priv->display.modeset_calc_cdclk =
2821                         cnl_modeset_calc_cdclk;
2822         } else if (IS_GEN9_LP(dev_priv)) {
2823                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2824                 dev_priv->display.modeset_calc_cdclk =
2825                         bxt_modeset_calc_cdclk;
2826         } else if (IS_GEN9_BC(dev_priv)) {
2827                 dev_priv->display.set_cdclk = skl_set_cdclk;
2828                 dev_priv->display.modeset_calc_cdclk =
2829                         skl_modeset_calc_cdclk;
2830         } else if (IS_BROADWELL(dev_priv)) {
2831                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2832                 dev_priv->display.modeset_calc_cdclk =
2833                         bdw_modeset_calc_cdclk;
2834         } else if (IS_CHERRYVIEW(dev_priv)) {
2835                 dev_priv->display.set_cdclk = chv_set_cdclk;
2836                 dev_priv->display.modeset_calc_cdclk =
2837                         vlv_modeset_calc_cdclk;
2838         } else if (IS_VALLEYVIEW(dev_priv)) {
2839                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2840                 dev_priv->display.modeset_calc_cdclk =
2841                         vlv_modeset_calc_cdclk;
2842         }
2843
2844         if (INTEL_GEN(dev_priv) >= 11)
2845                 dev_priv->display.get_cdclk = icl_get_cdclk;
2846         else if (IS_CANNONLAKE(dev_priv))
2847                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2848         else if (IS_GEN9_LP(dev_priv))
2849                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2850         else if (IS_GEN9_BC(dev_priv))
2851                 dev_priv->display.get_cdclk = skl_get_cdclk;
2852         else if (IS_BROADWELL(dev_priv))
2853                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2854         else if (IS_HASWELL(dev_priv))
2855                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2856         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2857                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2858         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
2859                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2860         else if (IS_GEN(dev_priv, 5))
2861                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2862         else if (IS_GM45(dev_priv))
2863                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2864         else if (IS_G45(dev_priv))
2865                 dev_priv->display.get_cdclk = g33_get_cdclk;
2866         else if (IS_I965GM(dev_priv))
2867                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2868         else if (IS_I965G(dev_priv))
2869                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2870         else if (IS_PINEVIEW(dev_priv))
2871                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2872         else if (IS_G33(dev_priv))
2873                 dev_priv->display.get_cdclk = g33_get_cdclk;
2874         else if (IS_I945GM(dev_priv))
2875                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2876         else if (IS_I945G(dev_priv))
2877                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2878         else if (IS_I915GM(dev_priv))
2879                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2880         else if (IS_I915G(dev_priv))
2881                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2882         else if (IS_I865G(dev_priv))
2883                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2884         else if (IS_I85X(dev_priv))
2885                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2886         else if (IS_I845G(dev_priv))
2887                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2888         else { /* 830 */
2889                 WARN(!IS_I830(dev_priv),
2890                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2891                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2892         }
2893 }