drivers/gpu/drm/i915/intel_color.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_drv.h"
  26
  27 #define CTM_COEFF_SIGN  (1ULL << 63)
  28
  29 #define CTM_COEFF_1_0   (1ULL << 32)
  30 #define CTM_COEFF_2_0   (CTM_COEFF_1_0 << 1)
  31 #define CTM_COEFF_4_0   (CTM_COEFF_2_0 << 1)
  32 #define CTM_COEFF_8_0   (CTM_COEFF_4_0 << 1)
  33 #define CTM_COEFF_0_5   (CTM_COEFF_1_0 >> 1)
  34 #define CTM_COEFF_0_25  (CTM_COEFF_0_5 >> 1)
  35 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
  36
  37 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
  38
  39 #define CTM_COEFF_NEGATIVE(coeff)       (((coeff) & CTM_COEFF_SIGN) != 0)
  40 #define CTM_COEFF_ABS(coeff)            ((coeff) & (CTM_COEFF_SIGN - 1))
  41
  42 #define LEGACY_LUT_LENGTH               256
  43 /*
  44  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  45  * format). This macro takes the coefficient we want transformed and the
  46  * number of fractional bits.
  47  *
  48  * We only have a 9 bits precision window which slides depending on the value
  49  * of the CTM coefficient and we write the value from bit 3. We also round the
  50  * value.
  51  */
  52 #define ILK_CSC_COEFF_FP(coeff, fbits)  \
  53         (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
  54
  55 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
  56 #define ILK_CSC_COEFF_1_0 0x7800
  57
  58 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
  59
  60 static const u16 ilk_csc_off_zero[3] = {};
  61
  62 static const u16 ilk_csc_coeff_identity[9] = {
  63         ILK_CSC_COEFF_1_0, 0, 0,
  64         0, ILK_CSC_COEFF_1_0, 0,
  65         0, 0, ILK_CSC_COEFF_1_0,
  66 };
  67
  68 static const u16 ilk_csc_postoff_limited_range[3] = {
  69         ILK_CSC_POSTOFF_LIMITED_RANGE,
  70         ILK_CSC_POSTOFF_LIMITED_RANGE,
  71         ILK_CSC_POSTOFF_LIMITED_RANGE,
  72 };
  73
  74 static const u16 ilk_csc_coeff_limited_range[9] = {
  75         ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
  76         0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
  77         0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
  78 };
  79
  80 /*
  81  * These values are direct register values specified in the Bspec,
  82  * for RGB->YUV conversion matrix (colorspace BT709)
  83  */
  84 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
  85         0x1e08, 0x9cc0, 0xb528,
  86         0x2ba8, 0x09d8, 0x37e8,
  87         0xbce8, 0x9ad8, 0x1e08,
  88 };
  89
  90 /* Post offset values for RGB->YCBCR conversion */
  91 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
  92         0x0800, 0x0100, 0x0800,
  93 };
  94
  95 static bool lut_is_legacy(const struct drm_property_blob *lut)
  96 {
  97         return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
  98 }
  99
 100 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
 101 {
 102         return !crtc_state->base.degamma_lut &&
 103                 !crtc_state->base.ctm &&
 104                 crtc_state->base.gamma_lut &&
 105                 lut_is_legacy(crtc_state->base.gamma_lut);
 106 }
 107
 108 /*
 109  * When using limited range, multiply the matrix given by userspace by
 110  * the matrix that we would use for the limited range.
 111  */
 112 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
 113 {
 114         int i;
 115
 116         for (i = 0; i < 9; i++) {
 117                 u64 user_coeff = input[i];
 118                 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
 119                 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
 120                                           CTM_COEFF_4_0 - 1) >> 2;
 121
 122                 /*
 123                  * By scaling every co-efficient with limited range (16-235)
 124                  * vs full range (0-255) the final o/p will be scaled down to
 125                  * fit in the limited range supported by the panel.
 126                  */
 127                 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
 128                 result[i] |= user_coeff & CTM_COEFF_SIGN;
 129         }
 130
 131         return result;
 132 }
 133
 134 static void ilk_update_pipe_csc(struct intel_crtc *crtc,
 135                                 const u16 preoff[3],
 136                                 const u16 coeff[9],
 137                                 const u16 postoff[3])
 138 {
 139         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 140         enum pipe pipe = crtc->pipe;
 141
 142         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
 143         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
 144         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
 145
 146         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
 147         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
 148
 149         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
 150         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
 151
 152         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
 153         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
 154
 155         if (INTEL_GEN(dev_priv) >= 7) {
 156                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0]);
 157                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff[1]);
 158                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff[2]);
 159         }
 160 }
 161
 162 static void icl_update_output_csc(struct intel_crtc *crtc,
 163                                   const u16 preoff[3],
 164                                   const u16 coeff[9],
 165                                   const u16 postoff[3])
 166 {
 167         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 168         enum pipe pipe = crtc->pipe;
 169
 170         I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
 171         I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
 172         I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
 173
 174         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
 175         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
 176
 177         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
 178         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
 179
 180         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
 181         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
 182
 183         I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
 184         I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
 185         I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
 186 }
 187
 188 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 189 {
 190         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 191
 192         /*
 193          * FIXME if there's a gamma LUT after the CSC, we should
 194          * do the range compression using the gamma LUT instead.
 195          */
 196         return crtc_state->limited_color_range &&
 197                 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
 198                  IS_GEN_RANGE(dev_priv, 9, 10));
 199 }
 200
 201 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
 202                                 u16 coeffs[9])
 203 {
 204         const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 205         const u64 *input;
 206         u64 temp[9];
 207         int i;
 208
 209         if (ilk_csc_limited_range(crtc_state))
 210                 input = ctm_mult_by_limited(temp, ctm->matrix);
 211         else
 212                 input = ctm->matrix;
 213
 214         /*
 215          * Convert fixed point S31.32 input to format supported by the
 216          * hardware.
 217          */
 218         for (i = 0; i < 9; i++) {
 219                 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
 220
 221                 /*
 222                  * Clamp input value to min/max supported by
 223                  * hardware.
 224                  */
 225                 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
 226
 227                 coeffs[i] = 0;
 228
 229                 /* sign bit */
 230                 if (CTM_COEFF_NEGATIVE(input[i]))
 231                         coeffs[i] |= 1 << 15;
 232
 233                 if (abs_coeff < CTM_COEFF_0_125)
 234                         coeffs[i] |= (3 << 12) |
 235                                 ILK_CSC_COEFF_FP(abs_coeff, 12);
 236                 else if (abs_coeff < CTM_COEFF_0_25)
 237                         coeffs[i] |= (2 << 12) |
 238                                 ILK_CSC_COEFF_FP(abs_coeff, 11);
 239                 else if (abs_coeff < CTM_COEFF_0_5)
 240                         coeffs[i] |= (1 << 12) |
 241                                 ILK_CSC_COEFF_FP(abs_coeff, 10);
 242                 else if (abs_coeff < CTM_COEFF_1_0)
 243                         coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
 244                 else if (abs_coeff < CTM_COEFF_2_0)
 245                         coeffs[i] |= (7 << 12) |
 246                                 ILK_CSC_COEFF_FP(abs_coeff, 8);
 247                 else
 248                         coeffs[i] |= (6 << 12) |
 249                                 ILK_CSC_COEFF_FP(abs_coeff, 7);
 250         }
 251 }
 252
 253 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 254 {
 255         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 256         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 257         bool limited_color_range = ilk_csc_limited_range(crtc_state);
 258
 259         if (crtc_state->base.ctm) {
 260                 u16 coeff[9];
 261
 262                 ilk_csc_convert_ctm(crtc_state, coeff);
 263                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
 264                                     limited_color_range ?
 265                                     ilk_csc_postoff_limited_range :
 266                                     ilk_csc_off_zero);
 267         } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 268                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 269                                     ilk_csc_coeff_rgb_to_ycbcr,
 270                                     ilk_csc_postoff_rgb_to_ycbcr);
 271         } else if (limited_color_range) {
 272                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 273                                     ilk_csc_coeff_limited_range,
 274                                     ilk_csc_postoff_limited_range);
 275         } else if (crtc_state->csc_enable) {
 276                 /*
 277                  * On GLK+ both pipe CSC and degamma LUT are controlled
 278                  * by csc_enable. Hence for the cases where the degama
 279                  * LUT is needed but CSC is not we need to load an
 280                  * identity matrix.
 281                  */
 282                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_GEMINILAKE(dev_priv));
 283
 284                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 285                                     ilk_csc_coeff_identity,
 286                                     ilk_csc_off_zero);
 287         }
 288
 289         I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 290 }
 291
 292 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 293 {
 294         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 295         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 296
 297         if (crtc_state->base.ctm) {
 298                 u16 coeff[9];
 299
 300                 ilk_csc_convert_ctm(crtc_state, coeff);
 301                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 302                                     coeff, ilk_csc_off_zero);
 303         }
 304
 305         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 306                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 307                                       ilk_csc_coeff_rgb_to_ycbcr,
 308                                       ilk_csc_postoff_rgb_to_ycbcr);
 309         } else if (crtc_state->limited_color_range) {
 310                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 311                                       ilk_csc_coeff_limited_range,
 312                                       ilk_csc_postoff_limited_range);
 313         }
 314
 315         I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 316 }
 317
 318 /*
 319  * Set up the pipe CSC unit on CherryView.
 320  */
 321 static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 322 {
 323         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 324         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 325         enum pipe pipe = crtc->pipe;
 326
 327         if (crtc_state->base.ctm) {
 328                 const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 329                 u16 coeffs[9] = {};
 330                 int i;
 331
 332                 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 333                         u64 abs_coeff =
 334                                 ((1ULL << 63) - 1) & ctm->matrix[i];
 335
 336                         /* Round coefficient. */
 337                         abs_coeff += 1 << (32 - 13);
 338                         /* Clamp to hardware limits. */
 339                         abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
 340
 341                         /* Write coefficients in S3.12 format. */
 342                         if (ctm->matrix[i] & (1ULL << 63))
 343                                 coeffs[i] = 1 << 15;
 344                         coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
 345                         coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 346                 }
 347
 348                 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
 349                            coeffs[1] << 16 | coeffs[0]);
 350                 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
 351                            coeffs[3] << 16 | coeffs[2]);
 352                 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
 353                            coeffs[5] << 16 | coeffs[4]);
 354                 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
 355                            coeffs[7] << 16 | coeffs[6]);
 356                 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 357         }
 358
 359         I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
 360 }
 361
 362 static u32 ilk_lut_10(const struct drm_color_lut *color)
 363 {
 364         return drm_color_lut_extract(color->red, 10) << 20 |
 365                 drm_color_lut_extract(color->green, 10) << 10 |
 366                 drm_color_lut_extract(color->blue, 10);
 367 }
 368
 369 /* Loads the legacy palette/gamma unit for the CRTC. */
 370 static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
 371                                     const struct drm_property_blob *blob)
 372 {
 373         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 374         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 375         enum pipe pipe = crtc->pipe;
 376         int i;
 377
 378         if (HAS_GMCH(dev_priv)) {
 379                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 380                         assert_dsi_pll_enabled(dev_priv);
 381                 else
 382                         assert_pll_enabled(dev_priv, pipe);
 383         }
 384
 385         if (blob) {
 386                 const struct drm_color_lut *lut = blob->data;
 387
 388                 for (i = 0; i < 256; i++) {
 389                         u32 word =
 390                                 (drm_color_lut_extract(lut[i].red, 8) << 16) |
 391                                 (drm_color_lut_extract(lut[i].green, 8) << 8) |
 392                                 drm_color_lut_extract(lut[i].blue, 8);
 393
 394                         if (HAS_GMCH(dev_priv))
 395                                 I915_WRITE(PALETTE(pipe, i), word);
 396                         else
 397                                 I915_WRITE(LGC_PALETTE(pipe, i), word);
 398                 }
 399         }
 400 }
 401
 402 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 403 {
 404         i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
 405 }
 406
 407 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 408 {
 409         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 410         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 411         enum pipe pipe = crtc->pipe;
 412         u32 val;
 413
 414         val = I915_READ(PIPECONF(pipe));
 415         val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
 416         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 417         I915_WRITE(PIPECONF(pipe), val);
 418 }
 419
 420 static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
 421 {
 422         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 423         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 424         enum pipe pipe = crtc->pipe;
 425         u32 val;
 426
 427         val = I915_READ(PIPECONF(pipe));
 428         val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
 429         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 430         I915_WRITE(PIPECONF(pipe), val);
 431
 432         ilk_load_csc_matrix(crtc_state);
 433 }
 434
 435 static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 436 {
 437         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 438         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 439
 440         I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
 441
 442         ilk_load_csc_matrix(crtc_state);
 443 }
 444
 445 static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 446 {
 447         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 448         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 449         enum pipe pipe = crtc->pipe;
 450         u32 val = 0;
 451
 452         /*
 453          * We don't (yet) allow userspace to control the pipe background color,
 454          * so force it to black, but apply pipe gamma and CSC appropriately
 455          * so that its handling will match how we program our planes.
 456          */
 457         if (crtc_state->gamma_enable)
 458                 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
 459         if (crtc_state->csc_enable)
 460                 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
 461         I915_WRITE(SKL_BOTTOM_COLOR(pipe), val);
 462
 463         I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
 464
 465         if (INTEL_GEN(dev_priv) >= 11)
 466                 icl_load_csc_matrix(crtc_state);
 467         else
 468                 ilk_load_csc_matrix(crtc_state);
 469 }
 470
 471 static void ilk_load_lut_10(struct intel_crtc *crtc,
 472                             const struct drm_property_blob *blob)
 473 {
 474         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 475         const struct drm_color_lut *lut = blob->data;
 476         int i, lut_size = drm_color_lut_size(blob);
 477         enum pipe pipe = crtc->pipe;
 478
 479         for (i = 0; i < lut_size; i++)
 480                 I915_WRITE(PREC_PALETTE(pipe, i), ilk_lut_10(&lut[i]));
 481 }
 482
 483 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 484 {
 485         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 486         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 487
 488         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 489                 i9xx_load_luts(crtc_state);
 490         else
 491                 ilk_load_lut_10(crtc, gamma_lut);
 492 }
 493
 494 /*
 495  * IVB/HSW Bspec / PAL_PREC_INDEX:
 496  * "Restriction : Index auto increment mode is not
 497  *  supported and must not be enabled."
 498  */
 499 static void ivb_load_lut_10(struct intel_crtc *crtc,
 500                             const struct drm_property_blob *blob,
 501                             u32 prec_index, bool duplicate)
 502 {
 503         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 504         const struct drm_color_lut *lut = blob->data;
 505         int i, lut_size = drm_color_lut_size(blob);
 506         enum pipe pipe = crtc->pipe;
 507
 508         /*
 509          * We advertise the split gamma sizes. When not using split
 510          * gamma we just duplicate each entry.
 511          *
 512          * TODO: expose the full LUT to userspace
 513          */
 514         if (duplicate) {
 515                 for (i = 0; i < lut_size; i++) {
 516                         I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
 517                         I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
 518                         I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
 519                         I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
 520                 }
 521         } else {
 522                 for (i = 0; i < lut_size; i++) {
 523                         I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
 524                         I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
 525                 }
 526         }
 527
 528         /*
 529          * Reset the index, otherwise it prevents the legacy palette to be
 530          * written properly.
 531          */
 532         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 533 }
 534
 535 /* On BDW+ the index auto increment mode actually works */
 536 static void bdw_load_lut_10(struct intel_crtc *crtc,
 537                             const struct drm_property_blob *blob,
 538                             u32 prec_index, bool duplicate)
 539 {
 540         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 541         const struct drm_color_lut *lut = blob->data;
 542         int i, lut_size = drm_color_lut_size(blob);
 543         enum pipe pipe = crtc->pipe;
 544
 545         I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
 546                    PAL_PREC_AUTO_INCREMENT);
 547
 548         /*
 549          * We advertise the split gamma sizes. When not using split
 550          * gamma we just duplicate each entry.
 551          *
 552          * TODO: expose the full LUT to userspace
 553          */
 554         if (duplicate) {
 555                 for (i = 0; i < lut_size; i++) {
 556                         I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
 557                         I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
 558                 }
 559         } else {
 560                 for (i = 0; i < lut_size; i++)
 561                         I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
 562         }
 563
 564         /*
 565          * Reset the index, otherwise it prevents the legacy palette to be
 566          * written properly.
 567          */
 568         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 569 }
 570
 571 static void ivb_load_lut_10_max(struct intel_crtc *crtc)
 572 {
 573         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 574         enum pipe pipe = crtc->pipe;
 575
 576         /* Program the max register to clamp values > 1.0. */
 577         I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
 578         I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
 579         I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
 580
 581         /*
 582          * Program the gc max 2 register to clamp values > 1.0.
 583          * ToDo: Extend the ABI to be able to program values
 584          * from 3.0 to 7.0
 585          */
 586         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 587                 I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
 588                 I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
 589                 I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
 590         }
 591 }
 592
 593 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 594 {
 595         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 596         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 597         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 598
 599         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 600                 i9xx_load_luts(crtc_state);
 601         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 602                 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 603                                 PAL_PREC_INDEX_VALUE(0), false);
 604                 ivb_load_lut_10_max(crtc);
 605                 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 606                                 PAL_PREC_INDEX_VALUE(512),  false);
 607         } else {
 608                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 609
 610                 ivb_load_lut_10(crtc, blob,
 611                                 PAL_PREC_INDEX_VALUE(0), true);
 612                 ivb_load_lut_10_max(crtc);
 613         }
 614 }
 615
 616 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 617 {
 618         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 619         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 620         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 621
 622         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 623                 i9xx_load_luts(crtc_state);
 624         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 625                 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 626                                 PAL_PREC_INDEX_VALUE(0), false);
 627                 ivb_load_lut_10_max(crtc);
 628                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 629                                 PAL_PREC_INDEX_VALUE(512),  false);
 630         } else {
 631                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 632
 633                 bdw_load_lut_10(crtc, blob,
 634                                 PAL_PREC_INDEX_VALUE(0), true);
 635                 ivb_load_lut_10_max(crtc);
 636         }
 637 }
 638
 639 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 640 {
 641         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 642         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 643         enum pipe pipe = crtc->pipe;
 644         const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 645         const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
 646         u32 i;
 647
 648         /*
 649          * When setting the auto-increment bit, the hardware seems to
 650          * ignore the index bits, so we need to reset it to index 0
 651          * separately.
 652          */
 653         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 654         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 655
 656         for (i = 0; i < lut_size; i++) {
 657                 /*
 658                  * First 33 entries represent range from 0 to 1.0
 659                  * 34th and 35th entry will represent extended range
 660                  * inputs 3.0 and 7.0 respectively, currently clamped
 661                  * at 1.0. Since the precision is 16bit, the user
 662                  * value can be directly filled to register.
 663                  * The pipe degamma table in GLK+ onwards doesn't
 664                  * support different values per channel, so this just
 665                  * programs green value which will be equal to Red and
 666                  * Blue into the lut registers.
 667                  * ToDo: Extend to max 7.0. Enable 32 bit input value
 668                  * as compared to just 16 to achieve this.
 669                  */
 670                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
 671         }
 672
 673         /* Clamp values > 1.0. */
 674         while (i++ < 35)
 675                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 676 }
 677
 678 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
 679 {
 680         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 681         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 682         enum pipe pipe = crtc->pipe;
 683         const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 684         u32 i;
 685
 686         /*
 687          * When setting the auto-increment bit, the hardware seems to
 688          * ignore the index bits, so we need to reset it to index 0
 689          * separately.
 690          */
 691         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 692         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 693
 694         for (i = 0; i < lut_size; i++) {
 695                 u32 v = (i << 16) / (lut_size - 1);
 696
 697                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
 698         }
 699
 700         /* Clamp values > 1.0. */
 701         while (i++ < 35)
 702                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 703 }
 704
 705 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 706 {
 707         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 708         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 709
 710         /*
 711          * On GLK+ both pipe CSC and degamma LUT are controlled
 712          * by csc_enable. Hence for the cases where the CSC is
 713          * needed but degamma LUT is not we need to load a
 714          * linear degamma LUT. In fact we'll just always load
 715          * the degama LUT so that we don't have to reload
 716          * it every time the pipe CSC is being enabled.
 717          */
 718         if (crtc_state->base.degamma_lut)
 719                 glk_load_degamma_lut(crtc_state);
 720         else
 721                 glk_load_degamma_lut_linear(crtc_state);
 722
 723         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 724                 i9xx_load_luts(crtc_state);
 725         } else {
 726                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0), false);
 727                 ivb_load_lut_10_max(crtc);
 728         }
 729 }
 730
 731 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 732 {
 733         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 734         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 735
 736         if (crtc_state->base.degamma_lut)
 737                 glk_load_degamma_lut(crtc_state);
 738
 739         if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
 740             GAMMA_MODE_MODE_8BIT) {
 741                 i9xx_load_luts(crtc_state);
 742         } else {
 743                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0), false);
 744                 ivb_load_lut_10_max(crtc);
 745         }
 746 }
 747
 748 static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
 749 {
 750         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 751         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 752         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 753         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 754         enum pipe pipe = crtc->pipe;
 755
 756         cherryview_load_csc_matrix(crtc_state);
 757
 758         if (crtc_state_is_legacy_gamma(crtc_state)) {
 759                 i9xx_load_luts(crtc_state);
 760                 return;
 761         }
 762
 763         if (degamma_lut) {
 764                 const struct drm_color_lut *lut = degamma_lut->data;
 765                 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 766
 767                 for (i = 0; i < lut_size; i++) {
 768                         u32 word0, word1;
 769
 770                         /* Write LUT in U0.14 format. */
 771                         word0 =
 772                         (drm_color_lut_extract(lut[i].green, 14) << 16) |
 773                         drm_color_lut_extract(lut[i].blue, 14);
 774                         word1 = drm_color_lut_extract(lut[i].red, 14);
 775
 776                         I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
 777                         I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
 778                 }
 779         }
 780
 781         if (gamma_lut) {
 782                 const struct drm_color_lut *lut = gamma_lut->data;
 783                 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 784
 785                 for (i = 0; i < lut_size; i++) {
 786                         u32 word0, word1;
 787
 788                         /* Write LUT in U0.10 format. */
 789                         word0 =
 790                         (drm_color_lut_extract(lut[i].green, 10) << 16) |
 791                         drm_color_lut_extract(lut[i].blue, 10);
 792                         word1 = drm_color_lut_extract(lut[i].red, 10);
 793
 794                         I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
 795                         I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);
 796                 }
 797         }
 798 }
 799
 800 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 801 {
 802         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 803
 804         dev_priv->display.load_luts(crtc_state);
 805 }
 806
 807 void intel_color_commit(const struct intel_crtc_state *crtc_state)
 808 {
 809         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 810
 811         dev_priv->display.color_commit(crtc_state);
 812 }
 813
 814 int intel_color_check(struct intel_crtc_state *crtc_state)
 815 {
 816         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 817
 818         return dev_priv->display.color_check(crtc_state);
 819 }
 820
 821 static bool need_plane_update(struct intel_plane *plane,
 822                               const struct intel_crtc_state *crtc_state)
 823 {
 824         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 825
 826         /*
 827          * On pre-SKL the pipe gamma enable and pipe csc enable for
 828          * the pipe bottom color are configured via the primary plane.
 829          * We have to reconfigure that even if the plane is inactive.
 830          */
 831         return crtc_state->active_planes & BIT(plane->id) ||
 832                 (INTEL_GEN(dev_priv) < 9 &&
 833                  plane->id == PLANE_PRIMARY);
 834 }
 835
 836 static int
 837 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
 838 {
 839         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 840         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 841         struct intel_atomic_state *state =
 842                 to_intel_atomic_state(new_crtc_state->base.state);
 843         const struct intel_crtc_state *old_crtc_state =
 844                 intel_atomic_get_old_crtc_state(state, crtc);
 845         struct intel_plane *plane;
 846
 847         if (!new_crtc_state->base.active ||
 848             drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
 849                 return 0;
 850
 851         if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
 852             new_crtc_state->csc_enable == old_crtc_state->csc_enable)
 853                 return 0;
 854
 855         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
 856                 struct intel_plane_state *plane_state;
 857
 858                 if (!need_plane_update(plane, new_crtc_state))
 859                         continue;
 860
 861                 plane_state = intel_atomic_get_plane_state(state, plane);
 862                 if (IS_ERR(plane_state))
 863                         return PTR_ERR(plane_state);
 864
 865                 new_crtc_state->update_planes |= BIT(plane->id);
 866         }
 867
 868         return 0;
 869 }
 870
 871 static int check_lut_size(const struct drm_property_blob *lut, int expected)
 872 {
 873         int len;
 874
 875         if (!lut)
 876                 return 0;
 877
 878         len = drm_color_lut_size(lut);
 879         if (len != expected) {
 880                 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
 881                               len, expected);
 882                 return -EINVAL;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int check_luts(const struct intel_crtc_state *crtc_state)
 889 {
 890         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 891         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 892         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 893         int gamma_length, degamma_length;
 894         u32 gamma_tests, degamma_tests;
 895
 896         /* Always allow legacy gamma LUT with no further checking. */
 897         if (crtc_state_is_legacy_gamma(crtc_state))
 898                 return 0;
 899
 900         /* C8 relies on its palette being stored in the legacy LUT */
 901         if (crtc_state->c8_planes)
 902                 return -EINVAL;
 903
 904         degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 905         gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 906         degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
 907         gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
 908
 909         if (check_lut_size(degamma_lut, degamma_length) ||
 910             check_lut_size(gamma_lut, gamma_length))
 911                 return -EINVAL;
 912
 913         if (drm_color_lut_check(degamma_lut, degamma_tests) ||
 914             drm_color_lut_check(gamma_lut, gamma_tests))
 915                 return -EINVAL;
 916
 917         return 0;
 918 }
 919
 920 static int i9xx_color_check(struct intel_crtc_state *crtc_state)
 921 {
 922         int ret;
 923
 924         ret = check_luts(crtc_state);
 925         if (ret)
 926                 return ret;
 927
 928         crtc_state->gamma_enable =
 929                 crtc_state->base.gamma_lut &&
 930                 !crtc_state->c8_planes;
 931
 932         crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 933
 934         ret = intel_color_add_affected_planes(crtc_state);
 935         if (ret)
 936                 return ret;
 937
 938         return 0;
 939 }
 940
 941 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
 942 {
 943         u32 cgm_mode = 0;
 944
 945         if (crtc_state_is_legacy_gamma(crtc_state))
 946                 return 0;
 947
 948         if (crtc_state->base.degamma_lut)
 949                 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
 950         if (crtc_state->base.ctm)
 951                 cgm_mode |= CGM_PIPE_MODE_CSC;
 952         if (crtc_state->base.gamma_lut)
 953                 cgm_mode |= CGM_PIPE_MODE_GAMMA;
 954
 955         return cgm_mode;
 956 }
 957
 958 /*
 959  * CHV color pipeline:
 960  * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma ->
 961  * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
 962  *
 963  * We always bypass the WGC csc and use the CGM csc
 964  * instead since it has degamma and better precision.
 965  */
 966 static int chv_color_check(struct intel_crtc_state *crtc_state)
 967 {
 968         int ret;
 969
 970         ret = check_luts(crtc_state);
 971         if (ret)
 972                 return ret;
 973
 974         /*
 975          * Pipe gamma will be used only for the legacy LUT.
 976          * Otherwise we bypass it and use the CGM gamma instead.
 977          */
 978         crtc_state->gamma_enable =
 979                 crtc_state_is_legacy_gamma(crtc_state) &&
 980                 !crtc_state->c8_planes;
 981
 982         crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 983
 984         crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
 985
 986         ret = intel_color_add_affected_planes(crtc_state);
 987         if (ret)
 988                 return ret;
 989
 990         return 0;
 991 }
 992
 993 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
 994 {
 995         if (!crtc_state->gamma_enable ||
 996             crtc_state_is_legacy_gamma(crtc_state))
 997                 return GAMMA_MODE_MODE_8BIT;
 998         else
 999                 return GAMMA_MODE_MODE_10BIT;
1000 }
1001
1002 static int ilk_color_check(struct intel_crtc_state *crtc_state)
1003 {
1004         int ret;
1005
1006         ret = check_luts(crtc_state);
1007         if (ret)
1008                 return ret;
1009
1010         crtc_state->gamma_enable =
1011                 crtc_state->base.gamma_lut &&
1012                 !crtc_state->c8_planes;
1013
1014         /*
1015          * We don't expose the ctm on ilk/snb currently,
1016          * nor do we enable YCbCr output. Also RGB limited
1017          * range output is handled by the hw automagically.
1018          */
1019         crtc_state->csc_enable = false;
1020
1021         crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
1022
1023         crtc_state->csc_mode = 0;
1024
1025         ret = intel_color_add_affected_planes(crtc_state);
1026         if (ret)
1027                 return ret;
1028
1029         return 0;
1030 }
1031
1032 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
1033 {
1034         if (!crtc_state->gamma_enable ||
1035             crtc_state_is_legacy_gamma(crtc_state))
1036                 return GAMMA_MODE_MODE_8BIT;
1037         else if (crtc_state->base.gamma_lut &&
1038                  crtc_state->base.degamma_lut)
1039                 return GAMMA_MODE_MODE_SPLIT;
1040         else
1041                 return GAMMA_MODE_MODE_10BIT;
1042 }
1043
1044 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
1045 {
1046         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1047
1048         /*
1049          * CSC comes after the LUT in degamma, RGB->YCbCr,
1050          * and RGB full->limited range mode.
1051          */
1052         if (crtc_state->base.degamma_lut ||
1053             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1054             limited_color_range)
1055                 return 0;
1056
1057         return CSC_POSITION_BEFORE_GAMMA;
1058 }
1059
1060 static int ivb_color_check(struct intel_crtc_state *crtc_state)
1061 {
1062         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1063         int ret;
1064
1065         ret = check_luts(crtc_state);
1066         if (ret)
1067                 return ret;
1068
1069         crtc_state->gamma_enable =
1070                 (crtc_state->base.gamma_lut ||
1071                  crtc_state->base.degamma_lut) &&
1072                 !crtc_state->c8_planes;
1073
1074         crtc_state->csc_enable =
1075                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1076                 crtc_state->base.ctm || limited_color_range;
1077
1078         crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
1079
1080         crtc_state->csc_mode = ivb_csc_mode(crtc_state);
1081
1082         ret = intel_color_add_affected_planes(crtc_state);
1083         if (ret)
1084                 return ret;
1085
1086         return 0;
1087 }
1088
1089 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
1090 {
1091         if (!crtc_state->gamma_enable ||
1092             crtc_state_is_legacy_gamma(crtc_state))
1093                 return GAMMA_MODE_MODE_8BIT;
1094         else
1095                 return GAMMA_MODE_MODE_10BIT;
1096 }
1097
1098 static int glk_color_check(struct intel_crtc_state *crtc_state)
1099 {
1100         int ret;
1101
1102         ret = check_luts(crtc_state);
1103         if (ret)
1104                 return ret;
1105
1106         crtc_state->gamma_enable =
1107                 crtc_state->base.gamma_lut &&
1108                 !crtc_state->c8_planes;
1109
1110         /* On GLK+ degamma LUT is controlled by csc_enable */
1111         crtc_state->csc_enable =
1112                 crtc_state->base.degamma_lut ||
1113                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1114                 crtc_state->base.ctm || crtc_state->limited_color_range;
1115
1116         crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
1117
1118         crtc_state->csc_mode = 0;
1119
1120         ret = intel_color_add_affected_planes(crtc_state);
1121         if (ret)
1122                 return ret;
1123
1124         return 0;
1125 }
1126
1127 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
1128 {
1129         u32 gamma_mode = 0;
1130
1131         if (crtc_state->base.degamma_lut)
1132                 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
1133
1134         if (crtc_state->base.gamma_lut &&
1135             !crtc_state->c8_planes)
1136                 gamma_mode |= POST_CSC_GAMMA_ENABLE;
1137
1138         if (!crtc_state->base.gamma_lut ||
1139             crtc_state_is_legacy_gamma(crtc_state))
1140                 gamma_mode |= GAMMA_MODE_MODE_8BIT;
1141         else
1142                 gamma_mode |= GAMMA_MODE_MODE_10BIT;
1143
1144         return gamma_mode;
1145 }
1146
1147 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
1148 {
1149         u32 csc_mode = 0;
1150
1151         if (crtc_state->base.ctm)
1152                 csc_mode |= ICL_CSC_ENABLE;
1153
1154         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1155             crtc_state->limited_color_range)
1156                 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
1157
1158         return csc_mode;
1159 }
1160
1161 static int icl_color_check(struct intel_crtc_state *crtc_state)
1162 {
1163         int ret;
1164
1165         ret = check_luts(crtc_state);
1166         if (ret)
1167                 return ret;
1168
1169         crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
1170
1171         crtc_state->csc_mode = icl_csc_mode(crtc_state);
1172
1173         return 0;
1174 }
1175
1176 void intel_color_init(struct intel_crtc *crtc)
1177 {
1178         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1179         bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
1180
1181         drm_mode_crtc_set_gamma_size(&crtc->base, 256);
1182
1183         if (HAS_GMCH(dev_priv)) {
1184                 if (IS_CHERRYVIEW(dev_priv)) {
1185                         dev_priv->display.color_check = chv_color_check;
1186                         dev_priv->display.color_commit = i9xx_color_commit;
1187                         dev_priv->display.load_luts = cherryview_load_luts;
1188                 } else {
1189                         dev_priv->display.color_check = i9xx_color_check;
1190                         dev_priv->display.color_commit = i9xx_color_commit;
1191                         dev_priv->display.load_luts = i9xx_load_luts;
1192                 }
1193         } else {
1194                 if (INTEL_GEN(dev_priv) >= 11)
1195                         dev_priv->display.color_check = icl_color_check;
1196                 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1197                         dev_priv->display.color_check = glk_color_check;
1198                 else if (INTEL_GEN(dev_priv) >= 7)
1199                         dev_priv->display.color_check = ivb_color_check;
1200                 else
1201                         dev_priv->display.color_check = ilk_color_check;
1202
1203                 if (INTEL_GEN(dev_priv) >= 9)
1204                         dev_priv->display.color_commit = skl_color_commit;
1205                 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1206                         dev_priv->display.color_commit = hsw_color_commit;
1207                 else
1208                         dev_priv->display.color_commit = ilk_color_commit;
1209
1210                 if (INTEL_GEN(dev_priv) >= 11)
1211                         dev_priv->display.load_luts = icl_load_luts;
1212                 else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
1213                         dev_priv->display.load_luts = glk_load_luts;
1214                 else if (INTEL_GEN(dev_priv) >= 8)
1215                         dev_priv->display.load_luts = bdw_load_luts;
1216                 else if (INTEL_GEN(dev_priv) >= 7)
1217                         dev_priv->display.load_luts = ivb_load_luts;
1218                 else
1219                         dev_priv->display.load_luts = ilk_load_luts;
1220         }
1221
1222         drm_crtc_enable_color_mgmt(&crtc->base,
1223                                    INTEL_INFO(dev_priv)->color.degamma_lut_size,
1224                                    has_ctm,
1225                                    INTEL_INFO(dev_priv)->color.gamma_lut_size);
1226 }