drivers/gpu/drm/i915/intel_color.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_drv.h"
  26
  27 #define CTM_COEFF_SIGN  (1ULL << 63)
  28
  29 #define CTM_COEFF_1_0   (1ULL << 32)
  30 #define CTM_COEFF_2_0   (CTM_COEFF_1_0 << 1)
  31 #define CTM_COEFF_4_0   (CTM_COEFF_2_0 << 1)
  32 #define CTM_COEFF_8_0   (CTM_COEFF_4_0 << 1)
  33 #define CTM_COEFF_0_5   (CTM_COEFF_1_0 >> 1)
  34 #define CTM_COEFF_0_25  (CTM_COEFF_0_5 >> 1)
  35 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
  36
  37 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
  38
  39 #define CTM_COEFF_NEGATIVE(coeff)       (((coeff) & CTM_COEFF_SIGN) != 0)
  40 #define CTM_COEFF_ABS(coeff)            ((coeff) & (CTM_COEFF_SIGN - 1))
  41
  42 #define LEGACY_LUT_LENGTH               256
  43
  44 /* Post offset values for RGB->YCBCR conversion */
  45 #define POSTOFF_RGB_TO_YUV_HI 0x800
  46 #define POSTOFF_RGB_TO_YUV_ME 0x100
  47 #define POSTOFF_RGB_TO_YUV_LO 0x800
  48
  49 /*
  50  * These values are direct register values specified in the Bspec,
  51  * for RGB->YUV conversion matrix (colorspace BT709)
  52  */
  53 #define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8
  54 #define CSC_RGB_TO_YUV_BU 0x37e80000
  55 #define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0
  56 #define CSC_RGB_TO_YUV_BY 0xb5280000
  57 #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
  58 #define CSC_RGB_TO_YUV_BV 0x1e080000
  59
  60 /*
  61  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  62  * format). This macro takes the coefficient we want transformed and the
  63  * number of fractional bits.
  64  *
  65  * We only have a 9 bits precision window which slides depending on the value
  66  * of the CTM coefficient and we write the value from bit 3. We also round the
  67  * value.
  68  */
  69 #define ILK_CSC_COEFF_FP(coeff, fbits)  \
  70         (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
  71
  72 #define ILK_CSC_COEFF_LIMITED_RANGE     \
  73         ILK_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
  74 #define ILK_CSC_COEFF_1_0               \
  75         ((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
  76
  77 static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state)
  78 {
  79         return !state->degamma_lut &&
  80                 !state->ctm &&
  81                 state->gamma_lut &&
  82                 drm_color_lut_size(state->gamma_lut) == LEGACY_LUT_LENGTH;
  83 }
  84
  85 /*
  86  * When using limited range, multiply the matrix given by userspace by
  87  * the matrix that we would use for the limited range.
  88  */
  89 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
  90 {
  91         int i;
  92
  93         for (i = 0; i < 9; i++) {
  94                 u64 user_coeff = input[i];
  95                 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
  96                 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
  97                                           CTM_COEFF_4_0 - 1) >> 2;
  98
  99                 /*
 100                  * By scaling every co-efficient with limited range (16-235)
 101                  * vs full range (0-255) the final o/p will be scaled down to
 102                  * fit in the limited range supported by the panel.
 103                  */
 104                 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
 105                 result[i] |= user_coeff & CTM_COEFF_SIGN;
 106         }
 107
 108         return result;
 109 }
 110
 111 static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
 112 {
 113         int pipe = intel_crtc->pipe;
 114         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 115
 116         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
 117         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
 118         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 119
 120         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
 121         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
 122
 123         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
 124         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
 125
 126         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
 127         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
 128
 129         I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
 130         I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
 131         I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
 132         I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 133 }
 134
 135 static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
 136 {
 137         struct drm_crtc *crtc = crtc_state->crtc;
 138         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 140         int i, pipe = intel_crtc->pipe;
 141         uint16_t coeffs[9] = { 0, };
 142         struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
 143         bool limited_color_range = false;
 144
 145         /*
 146          * FIXME if there's a gamma LUT after the CSC, we should
 147          * do the range compression using the gamma LUT instead.
 148          */
 149         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
 150                 limited_color_range = intel_crtc_state->limited_color_range;
 151
 152         if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 153             intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
 154                 ilk_load_ycbcr_conversion_matrix(intel_crtc);
 155                 return;
 156         } else if (crtc_state->ctm) {
 157                 struct drm_color_ctm *ctm = crtc_state->ctm->data;
 158                 const u64 *input;
 159                 u64 temp[9];
 160
 161                 if (limited_color_range)
 162                         input = ctm_mult_by_limited(temp, ctm->matrix);
 163                 else
 164                         input = ctm->matrix;
 165
 166                 /*
 167                  * Convert fixed point S31.32 input to format supported by the
 168                  * hardware.
 169                  */
 170                 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 171                         uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i];
 172
 173                         /*
 174                          * Clamp input value to min/max supported by
 175                          * hardware.
 176                          */
 177                         abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
 178
 179                         /* sign bit */
 180                         if (CTM_COEFF_NEGATIVE(input[i]))
 181                                 coeffs[i] |= 1 << 15;
 182
 183                         if (abs_coeff < CTM_COEFF_0_125)
 184                                 coeffs[i] |= (3 << 12) |
 185                                         ILK_CSC_COEFF_FP(abs_coeff, 12);
 186                         else if (abs_coeff < CTM_COEFF_0_25)
 187                                 coeffs[i] |= (2 << 12) |
 188                                         ILK_CSC_COEFF_FP(abs_coeff, 11);
 189                         else if (abs_coeff < CTM_COEFF_0_5)
 190                                 coeffs[i] |= (1 << 12) |
 191                                         ILK_CSC_COEFF_FP(abs_coeff, 10);
 192                         else if (abs_coeff < CTM_COEFF_1_0)
 193                                 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
 194                         else if (abs_coeff < CTM_COEFF_2_0)
 195                                 coeffs[i] |= (7 << 12) |
 196                                         ILK_CSC_COEFF_FP(abs_coeff, 8);
 197                         else
 198                                 coeffs[i] |= (6 << 12) |
 199                                         ILK_CSC_COEFF_FP(abs_coeff, 7);
 200                 }
 201         } else {
 202                 /*
 203                  * Load an identity matrix if no coefficients are provided.
 204                  *
 205                  * TODO: Check what kind of values actually come out of the
 206                  * pipe with these coeff/postoff values and adjust to get the
 207                  * best accuracy. Perhaps we even need to take the bpc value
 208                  * into consideration.
 209                  */
 210                 for (i = 0; i < 3; i++) {
 211                         if (limited_color_range)
 212                                 coeffs[i * 3 + i] =
 213                                         ILK_CSC_COEFF_LIMITED_RANGE;
 214                         else
 215                                 coeffs[i * 3 + i] = ILK_CSC_COEFF_1_0;
 216                 }
 217         }
 218
 219         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
 220         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
 221
 222         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
 223         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
 224
 225         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
 226         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
 227
 228         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
 229         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
 230         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 231
 232         if (INTEL_GEN(dev_priv) > 6) {
 233                 uint16_t postoff = 0;
 234
 235                 if (limited_color_range)
 236                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
 237
 238                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
 239                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
 240                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 241
 242                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 243         } else {
 244                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
 245
 246                 if (limited_color_range)
 247                         mode |= CSC_BLACK_SCREEN_OFFSET;
 248
 249                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
 250         }
 251 }
 252
 253 /*
 254  * Set up the pipe CSC unit on CherryView.
 255  */
 256 static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
 257 {
 258         struct drm_crtc *crtc = state->crtc;
 259         struct drm_device *dev = crtc->dev;
 260         struct drm_i915_private *dev_priv = to_i915(dev);
 261         int pipe = to_intel_crtc(crtc)->pipe;
 262         uint32_t mode;
 263
 264         if (state->ctm) {
 265                 struct drm_color_ctm *ctm = state->ctm->data;
 266                 uint16_t coeffs[9] = { 0, };
 267                 int i;
 268
 269                 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 270                         uint64_t abs_coeff =
 271                                 ((1ULL << 63) - 1) & ctm->matrix[i];
 272
 273                         /* Round coefficient. */
 274                         abs_coeff += 1 << (32 - 13);
 275                         /* Clamp to hardware limits. */
 276                         abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
 277
 278                         /* Write coefficients in S3.12 format. */
 279                         if (ctm->matrix[i] & (1ULL << 63))
 280                                 coeffs[i] = 1 << 15;
 281                         coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
 282                         coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 283                 }
 284
 285                 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
 286                            coeffs[1] << 16 | coeffs[0]);
 287                 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
 288                            coeffs[3] << 16 | coeffs[2]);
 289                 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
 290                            coeffs[5] << 16 | coeffs[4]);
 291                 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
 292                            coeffs[7] << 16 | coeffs[6]);
 293                 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 294         }
 295
 296         mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
 297         if (!crtc_state_is_legacy_gamma(state)) {
 298                 mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
 299                         (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
 300         }
 301         I915_WRITE(CGM_PIPE_MODE(pipe), mode);
 302 }
 303
 304 void intel_color_set_csc(struct drm_crtc_state *crtc_state)
 305 {
 306         struct drm_device *dev = crtc_state->crtc->dev;
 307         struct drm_i915_private *dev_priv = to_i915(dev);
 308
 309         if (dev_priv->display.load_csc_matrix)
 310                 dev_priv->display.load_csc_matrix(crtc_state);
 311 }
 312
 313 /* Loads the legacy palette/gamma unit for the CRTC. */
 314 static void i9xx_load_luts_internal(struct drm_crtc *crtc,
 315                                     struct drm_property_blob *blob,
 316                                     struct intel_crtc_state *crtc_state)
 317 {
 318         struct drm_device *dev = crtc->dev;
 319         struct drm_i915_private *dev_priv = to_i915(dev);
 320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 321         enum pipe pipe = intel_crtc->pipe;
 322         int i;
 323
 324         if (HAS_GMCH_DISPLAY(dev_priv)) {
 325                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 326                         assert_dsi_pll_enabled(dev_priv);
 327                 else
 328                         assert_pll_enabled(dev_priv, pipe);
 329         }
 330
 331         if (blob) {
 332                 struct drm_color_lut *lut = blob->data;
 333                 for (i = 0; i < 256; i++) {
 334                         uint32_t word =
 335                                 (drm_color_lut_extract(lut[i].red, 8) << 16) |
 336                                 (drm_color_lut_extract(lut[i].green, 8) << 8) |
 337                                 drm_color_lut_extract(lut[i].blue, 8);
 338
 339                         if (HAS_GMCH_DISPLAY(dev_priv))
 340                                 I915_WRITE(PALETTE(pipe, i), word);
 341                         else
 342                                 I915_WRITE(LGC_PALETTE(pipe, i), word);
 343                 }
 344         } else {
 345                 for (i = 0; i < 256; i++) {
 346                         uint32_t word = (i << 16) | (i << 8) | i;
 347
 348                         if (HAS_GMCH_DISPLAY(dev_priv))
 349                                 I915_WRITE(PALETTE(pipe, i), word);
 350                         else
 351                                 I915_WRITE(LGC_PALETTE(pipe, i), word);
 352                 }
 353         }
 354 }
 355
 356 static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
 357 {
 358         i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
 359                                 to_intel_crtc_state(crtc_state));
 360 }
 361
 362 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
 363 static void haswell_load_luts(struct drm_crtc_state *crtc_state)
 364 {
 365         struct drm_crtc *crtc = crtc_state->crtc;
 366         struct drm_device *dev = crtc->dev;
 367         struct drm_i915_private *dev_priv = to_i915(dev);
 368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 369         struct intel_crtc_state *intel_crtc_state =
 370                 to_intel_crtc_state(crtc_state);
 371         bool reenable_ips = false;
 372
 373         /*
 374          * Workaround : Do not read or write the pipe palette/gamma data while
 375          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 376          */
 377         if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
 378             (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
 379                 hsw_disable_ips(intel_crtc_state);
 380                 reenable_ips = true;
 381         }
 382
 383         intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 384         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
 385
 386         i9xx_load_luts(crtc_state);
 387
 388         if (reenable_ips)
 389                 hsw_enable_ips(intel_crtc_state);
 390 }
 391
 392 static void bdw_load_degamma_lut(struct drm_crtc_state *state)
 393 {
 394         struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 395         enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
 396         uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 397
 398         I915_WRITE(PREC_PAL_INDEX(pipe),
 399                    PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
 400
 401         if (state->degamma_lut) {
 402                 struct drm_color_lut *lut = state->degamma_lut->data;
 403
 404                 for (i = 0; i < lut_size; i++) {
 405                         uint32_t word =
 406                         drm_color_lut_extract(lut[i].red, 10) << 20 |
 407                         drm_color_lut_extract(lut[i].green, 10) << 10 |
 408                         drm_color_lut_extract(lut[i].blue, 10);
 409
 410                         I915_WRITE(PREC_PAL_DATA(pipe), word);
 411                 }
 412         } else {
 413                 for (i = 0; i < lut_size; i++) {
 414                         uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
 415
 416                         I915_WRITE(PREC_PAL_DATA(pipe),
 417                                    (v << 20) | (v << 10) | v);
 418                 }
 419         }
 420 }
 421
 422 static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
 423 {
 424         struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 425         enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
 426         uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 427
 428         WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
 429
 430         I915_WRITE(PREC_PAL_INDEX(pipe),
 431                    (offset ? PAL_PREC_SPLIT_MODE : 0) |
 432                    PAL_PREC_AUTO_INCREMENT |
 433                    offset);
 434
 435         if (state->gamma_lut) {
 436                 struct drm_color_lut *lut = state->gamma_lut->data;
 437
 438                 for (i = 0; i < lut_size; i++) {
 439                         uint32_t word =
 440                         (drm_color_lut_extract(lut[i].red, 10) << 20) |
 441                         (drm_color_lut_extract(lut[i].green, 10) << 10) |
 442                         drm_color_lut_extract(lut[i].blue, 10);
 443
 444                         I915_WRITE(PREC_PAL_DATA(pipe), word);
 445                 }
 446
 447                 /* Program the max register to clamp values > 1.0. */
 448                 i = lut_size - 1;
 449                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
 450                            drm_color_lut_extract(lut[i].red, 16));
 451                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
 452                            drm_color_lut_extract(lut[i].green, 16));
 453                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
 454                            drm_color_lut_extract(lut[i].blue, 16));
 455         } else {
 456                 for (i = 0; i < lut_size; i++) {
 457                         uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
 458
 459                         I915_WRITE(PREC_PAL_DATA(pipe),
 460                                    (v << 20) | (v << 10) | v);
 461                 }
 462
 463                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
 464                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
 465                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
 466         }
 467 }
 468
 469 /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
 470 static void broadwell_load_luts(struct drm_crtc_state *state)
 471 {
 472         struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 473         struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
 474         enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
 475
 476         if (crtc_state_is_legacy_gamma(state)) {
 477                 haswell_load_luts(state);
 478                 return;
 479         }
 480
 481         bdw_load_degamma_lut(state);
 482         bdw_load_gamma_lut(state,
 483                            INTEL_INFO(dev_priv)->color.degamma_lut_size);
 484
 485         intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
 486         I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
 487         POSTING_READ(GAMMA_MODE(pipe));
 488
 489         /*
 490          * Reset the index, otherwise it prevents the legacy palette to be
 491          * written properly.
 492          */
 493         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 494 }
 495
 496 static void glk_load_degamma_lut(struct drm_crtc_state *state)
 497 {
 498         struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 499         enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
 500         const uint32_t lut_size = 33;
 501         uint32_t i;
 502
 503         /*
 504          * When setting the auto-increment bit, the hardware seems to
 505          * ignore the index bits, so we need to reset it to index 0
 506          * separately.
 507          */
 508         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 509         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 510
 511         /*
 512          *  FIXME: The pipe degamma table in geminilake doesn't support
 513          *  different values per channel, so this just loads a linear table.
 514          */
 515         for (i = 0; i < lut_size; i++) {
 516                 uint32_t v = (i * (1 << 16)) / (lut_size - 1);
 517
 518                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
 519         }
 520
 521         /* Clamp values > 1.0. */
 522         while (i++ < 35)
 523                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
 524 }
 525
 526 static void glk_load_luts(struct drm_crtc_state *state)
 527 {
 528         struct drm_crtc *crtc = state->crtc;
 529         struct drm_device *dev = crtc->dev;
 530         struct drm_i915_private *dev_priv = to_i915(dev);
 531         struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
 532         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 533
 534         glk_load_degamma_lut(state);
 535
 536         if (crtc_state_is_legacy_gamma(state)) {
 537                 haswell_load_luts(state);
 538                 return;
 539         }
 540
 541         bdw_load_gamma_lut(state, 0);
 542
 543         intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
 544         I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
 545         POSTING_READ(GAMMA_MODE(pipe));
 546 }
 547
 548 /* Loads the palette/gamma unit for the CRTC on CherryView. */
 549 static void cherryview_load_luts(struct drm_crtc_state *state)
 550 {
 551         struct drm_crtc *crtc = state->crtc;
 552         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 553         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 554         struct drm_color_lut *lut;
 555         uint32_t i, lut_size;
 556         uint32_t word0, word1;
 557
 558         if (crtc_state_is_legacy_gamma(state)) {
 559                 /* Turn off degamma/gamma on CGM block. */
 560                 I915_WRITE(CGM_PIPE_MODE(pipe),
 561                            (state->ctm ? CGM_PIPE_MODE_CSC : 0));
 562                 i9xx_load_luts_internal(crtc, state->gamma_lut,
 563                                         to_intel_crtc_state(state));
 564                 return;
 565         }
 566
 567         if (state->degamma_lut) {
 568                 lut = state->degamma_lut->data;
 569                 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 570                 for (i = 0; i < lut_size; i++) {
 571                         /* Write LUT in U0.14 format. */
 572                         word0 =
 573                         (drm_color_lut_extract(lut[i].green, 14) << 16) |
 574                         drm_color_lut_extract(lut[i].blue, 14);
 575                         word1 = drm_color_lut_extract(lut[i].red, 14);
 576
 577                         I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
 578                         I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
 579                 }
 580         }
 581
 582         if (state->gamma_lut) {
 583                 lut = state->gamma_lut->data;
 584                 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 585                 for (i = 0; i < lut_size; i++) {
 586                         /* Write LUT in U0.10 format. */
 587                         word0 =
 588                         (drm_color_lut_extract(lut[i].green, 10) << 16) |
 589                         drm_color_lut_extract(lut[i].blue, 10);
 590                         word1 = drm_color_lut_extract(lut[i].red, 10);
 591
 592                         I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
 593                         I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);
 594                 }
 595         }
 596
 597         I915_WRITE(CGM_PIPE_MODE(pipe),
 598                    (state->ctm ? CGM_PIPE_MODE_CSC : 0) |
 599                    (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
 600                    (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
 601
 602         /*
 603          * Also program a linear LUT in the legacy block (behind the
 604          * CGM block).
 605          */
 606         i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
 607 }
 608
 609 void intel_color_load_luts(struct drm_crtc_state *crtc_state)
 610 {
 611         struct drm_device *dev = crtc_state->crtc->dev;
 612         struct drm_i915_private *dev_priv = to_i915(dev);
 613
 614         dev_priv->display.load_luts(crtc_state);
 615 }
 616
 617 int intel_color_check(struct drm_crtc *crtc,
 618                       struct drm_crtc_state *crtc_state)
 619 {
 620         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 621         size_t gamma_length, degamma_length;
 622
 623         degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 624         gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 625
 626         /*
 627          * We allow both degamma & gamma luts at the right size or
 628          * NULL.
 629          */
 630         if ((!crtc_state->degamma_lut ||
 631              drm_color_lut_size(crtc_state->degamma_lut) == degamma_length) &&
 632             (!crtc_state->gamma_lut ||
 633              drm_color_lut_size(crtc_state->gamma_lut) == gamma_length))
 634                 return 0;
 635
 636         /*
 637          * We also allow no degamma lut/ctm and a gamma lut at the legacy
 638          * size (256 entries).
 639          */
 640         if (crtc_state_is_legacy_gamma(crtc_state))
 641                 return 0;
 642
 643         return -EINVAL;
 644 }
 645
 646 void intel_color_init(struct drm_crtc *crtc)
 647 {
 648         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 649
 650         drm_mode_crtc_set_gamma_size(crtc, 256);
 651
 652         if (IS_CHERRYVIEW(dev_priv)) {
 653                 dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
 654                 dev_priv->display.load_luts = cherryview_load_luts;
 655         } else if (IS_HASWELL(dev_priv)) {
 656                 dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 657                 dev_priv->display.load_luts = haswell_load_luts;
 658         } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
 659                    IS_BROXTON(dev_priv)) {
 660                 dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 661                 dev_priv->display.load_luts = broadwell_load_luts;
 662         } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 663                 dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 664                 dev_priv->display.load_luts = glk_load_luts;
 665         } else {
 666                 dev_priv->display.load_luts = i9xx_load_luts;
 667         }
 668
 669         /* Enable color management support when we have degamma & gamma LUTs. */
 670         if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
 671             INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
 672                 drm_crtc_enable_color_mgmt(crtc,
 673                                            INTEL_INFO(dev_priv)->color.degamma_lut_size,
 674                                            true,
 675                                            INTEL_INFO(dev_priv)->color.gamma_lut_size);
 676 }