2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 #include "intel_drv.h"
27 #define CTM_COEFF_SIGN (1ULL << 63)
29 #define CTM_COEFF_1_0 (1ULL << 32)
30 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
31 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
32 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
33 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
34 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
35 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
37 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
39 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
40 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
42 #define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256)
44 /* Post offset values for RGB->YCBCR conversion */
45 #define POSTOFF_RGB_TO_YUV_HI 0x800
46 #define POSTOFF_RGB_TO_YUV_ME 0x100
47 #define POSTOFF_RGB_TO_YUV_LO 0x800
50 * These values are direct register values specified in the Bspec,
51 * for RGB->YUV conversion matrix (colorspace BT709)
53 #define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8
54 #define CSC_RGB_TO_YUV_BU 0x37e80000
55 #define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0
56 #define CSC_RGB_TO_YUV_BY 0xb5280000
57 #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
58 #define CSC_RGB_TO_YUV_BV 0x1e080000
61 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
62 * format). This macro takes the coefficient we want transformed and the
63 * number of fractional bits.
65 * We only have a 9 bits precision window which slides depending on the value
66 * of the CTM coefficient and we write the value from bit 3. We also round the
69 #define I9XX_CSC_COEFF_FP(coeff, fbits) \
70 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
72 #define I9XX_CSC_COEFF_LIMITED_RANGE \
73 I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
74 #define I9XX_CSC_COEFF_1_0 \
75 ((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
77 static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state)
79 return !state->degamma_lut &&
82 state->gamma_lut->length == LEGACY_LUT_LENGTH;
86 * When using limited range, multiply the matrix given by userspace by
87 * the matrix that we would use for the limited range. We do the
88 * multiplication in U2.30 format.
90 static void ctm_mult_by_limited(uint64_t *result, int64_t *input)
94 for (i = 0; i < 9; i++)
97 for (i = 0; i < 3; i++) {
98 int64_t user_coeff = input[i * 3 + i];
99 uint64_t limited_coeff = CTM_COEFF_LIMITED_RANGE >> 2;
100 uint64_t abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff),
102 CTM_COEFF_4_0 - 1) >> 2;
104 result[i * 3 + i] = (limited_coeff * abs_coeff) >> 27;
105 if (CTM_COEFF_NEGATIVE(user_coeff))
106 result[i * 3 + i] |= CTM_COEFF_SIGN;
110 static void i9xx_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
112 int pipe = intel_crtc->pipe;
113 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
115 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
116 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
117 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
119 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
120 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
122 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
123 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
125 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
126 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
128 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
129 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
130 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
131 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
134 /* Set up the pipe CSC unit. */
135 static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
137 struct drm_crtc *crtc = crtc_state->crtc;
138 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
140 int i, pipe = intel_crtc->pipe;
141 uint16_t coeffs[9] = { 0, };
142 struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
144 if (intel_crtc_state->ycbcr420) {
145 i9xx_load_ycbcr_conversion_matrix(intel_crtc);
147 } else if (crtc_state->ctm) {
148 struct drm_color_ctm *ctm = crtc_state->ctm->data;
149 uint64_t input[9] = { 0, };
151 if (intel_crtc_state->limited_color_range) {
152 ctm_mult_by_limited(input, ctm->matrix);
154 for (i = 0; i < ARRAY_SIZE(input); i++)
155 input[i] = ctm->matrix[i];
159 * Convert fixed point S31.32 input to format supported by the
162 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
163 uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i];
166 * Clamp input value to min/max supported by
169 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
172 if (CTM_COEFF_NEGATIVE(input[i]))
173 coeffs[i] |= 1 << 15;
175 if (abs_coeff < CTM_COEFF_0_125)
176 coeffs[i] |= (3 << 12) |
177 I9XX_CSC_COEFF_FP(abs_coeff, 12);
178 else if (abs_coeff < CTM_COEFF_0_25)
179 coeffs[i] |= (2 << 12) |
180 I9XX_CSC_COEFF_FP(abs_coeff, 11);
181 else if (abs_coeff < CTM_COEFF_0_5)
182 coeffs[i] |= (1 << 12) |
183 I9XX_CSC_COEFF_FP(abs_coeff, 10);
184 else if (abs_coeff < CTM_COEFF_1_0)
185 coeffs[i] |= I9XX_CSC_COEFF_FP(abs_coeff, 9);
186 else if (abs_coeff < CTM_COEFF_2_0)
187 coeffs[i] |= (7 << 12) |
188 I9XX_CSC_COEFF_FP(abs_coeff, 8);
190 coeffs[i] |= (6 << 12) |
191 I9XX_CSC_COEFF_FP(abs_coeff, 7);
195 * Load an identity matrix if no coefficients are provided.
197 * TODO: Check what kind of values actually come out of the
198 * pipe with these coeff/postoff values and adjust to get the
199 * best accuracy. Perhaps we even need to take the bpc value
200 * into consideration.
202 for (i = 0; i < 3; i++) {
203 if (intel_crtc_state->limited_color_range)
205 I9XX_CSC_COEFF_LIMITED_RANGE;
207 coeffs[i * 3 + i] = I9XX_CSC_COEFF_1_0;
211 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
212 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
214 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
215 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
217 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
218 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
220 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
221 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
222 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
224 if (INTEL_GEN(dev_priv) > 6) {
225 uint16_t postoff = 0;
227 if (intel_crtc_state->limited_color_range)
228 postoff = (16 * (1 << 12) / 255) & 0x1fff;
230 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
231 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
232 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
234 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
236 uint32_t mode = CSC_MODE_YUV_TO_RGB;
238 if (intel_crtc_state->limited_color_range)
239 mode |= CSC_BLACK_SCREEN_OFFSET;
241 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
246 * Set up the pipe CSC unit on CherryView.
248 static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
250 struct drm_crtc *crtc = state->crtc;
251 struct drm_device *dev = crtc->dev;
252 struct drm_i915_private *dev_priv = to_i915(dev);
253 int pipe = to_intel_crtc(crtc)->pipe;
257 struct drm_color_ctm *ctm = state->ctm->data;
258 uint16_t coeffs[9] = { 0, };
261 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
263 ((1ULL << 63) - 1) & ctm->matrix[i];
265 /* Round coefficient. */
266 abs_coeff += 1 << (32 - 13);
267 /* Clamp to hardware limits. */
268 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
270 /* Write coefficients in S3.12 format. */
271 if (ctm->matrix[i] & (1ULL << 63))
273 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
274 coeffs[i] |= (abs_coeff >> 20) & 0xfff;
277 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
278 coeffs[1] << 16 | coeffs[0]);
279 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
280 coeffs[3] << 16 | coeffs[2]);
281 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
282 coeffs[5] << 16 | coeffs[4]);
283 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
284 coeffs[7] << 16 | coeffs[6]);
285 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
288 mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
289 if (!crtc_state_is_legacy_gamma(state)) {
290 mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
291 (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
293 I915_WRITE(CGM_PIPE_MODE(pipe), mode);
296 void intel_color_set_csc(struct drm_crtc_state *crtc_state)
298 struct drm_device *dev = crtc_state->crtc->dev;
299 struct drm_i915_private *dev_priv = to_i915(dev);
301 if (dev_priv->display.load_csc_matrix)
302 dev_priv->display.load_csc_matrix(crtc_state);
305 /* Loads the legacy palette/gamma unit for the CRTC. */
306 static void i9xx_load_luts_internal(struct drm_crtc *crtc,
307 struct drm_property_blob *blob,
308 struct intel_crtc_state *crtc_state)
310 struct drm_device *dev = crtc->dev;
311 struct drm_i915_private *dev_priv = to_i915(dev);
312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
313 enum pipe pipe = intel_crtc->pipe;
316 if (HAS_GMCH_DISPLAY(dev_priv)) {
317 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
318 assert_dsi_pll_enabled(dev_priv);
320 assert_pll_enabled(dev_priv, pipe);
324 struct drm_color_lut *lut = blob->data;
325 for (i = 0; i < 256; i++) {
327 (drm_color_lut_extract(lut[i].red, 8) << 16) |
328 (drm_color_lut_extract(lut[i].green, 8) << 8) |
329 drm_color_lut_extract(lut[i].blue, 8);
331 if (HAS_GMCH_DISPLAY(dev_priv))
332 I915_WRITE(PALETTE(pipe, i), word);
334 I915_WRITE(LGC_PALETTE(pipe, i), word);
337 for (i = 0; i < 256; i++) {
338 uint32_t word = (i << 16) | (i << 8) | i;
340 if (HAS_GMCH_DISPLAY(dev_priv))
341 I915_WRITE(PALETTE(pipe, i), word);
343 I915_WRITE(LGC_PALETTE(pipe, i), word);
348 static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
350 i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
351 to_intel_crtc_state(crtc_state));
354 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
355 static void haswell_load_luts(struct drm_crtc_state *crtc_state)
357 struct drm_crtc *crtc = crtc_state->crtc;
358 struct drm_device *dev = crtc->dev;
359 struct drm_i915_private *dev_priv = to_i915(dev);
360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
361 struct intel_crtc_state *intel_crtc_state =
362 to_intel_crtc_state(crtc_state);
363 bool reenable_ips = false;
366 * Workaround : Do not read or write the pipe palette/gamma data while
367 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
369 if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
370 (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
371 hsw_disable_ips(intel_crtc_state);
375 intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
376 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
378 i9xx_load_luts(crtc_state);
381 hsw_enable_ips(intel_crtc_state);
384 static void bdw_load_degamma_lut(struct drm_crtc_state *state)
386 struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
387 enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
388 uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
390 I915_WRITE(PREC_PAL_INDEX(pipe),
391 PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
393 if (state->degamma_lut) {
394 struct drm_color_lut *lut = state->degamma_lut->data;
396 for (i = 0; i < lut_size; i++) {
398 drm_color_lut_extract(lut[i].red, 10) << 20 |
399 drm_color_lut_extract(lut[i].green, 10) << 10 |
400 drm_color_lut_extract(lut[i].blue, 10);
402 I915_WRITE(PREC_PAL_DATA(pipe), word);
405 for (i = 0; i < lut_size; i++) {
406 uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
408 I915_WRITE(PREC_PAL_DATA(pipe),
409 (v << 20) | (v << 10) | v);
414 static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
416 struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
417 enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
418 uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
420 WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
422 I915_WRITE(PREC_PAL_INDEX(pipe),
423 (offset ? PAL_PREC_SPLIT_MODE : 0) |
424 PAL_PREC_AUTO_INCREMENT |
427 if (state->gamma_lut) {
428 struct drm_color_lut *lut = state->gamma_lut->data;
430 for (i = 0; i < lut_size; i++) {
432 (drm_color_lut_extract(lut[i].red, 10) << 20) |
433 (drm_color_lut_extract(lut[i].green, 10) << 10) |
434 drm_color_lut_extract(lut[i].blue, 10);
436 I915_WRITE(PREC_PAL_DATA(pipe), word);
439 /* Program the max register to clamp values > 1.0. */
441 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
442 drm_color_lut_extract(lut[i].red, 16));
443 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
444 drm_color_lut_extract(lut[i].green, 16));
445 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
446 drm_color_lut_extract(lut[i].blue, 16));
448 for (i = 0; i < lut_size; i++) {
449 uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
451 I915_WRITE(PREC_PAL_DATA(pipe),
452 (v << 20) | (v << 10) | v);
455 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
456 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
457 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
461 /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
462 static void broadwell_load_luts(struct drm_crtc_state *state)
464 struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
465 struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
466 enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
468 if (crtc_state_is_legacy_gamma(state)) {
469 haswell_load_luts(state);
473 bdw_load_degamma_lut(state);
474 bdw_load_gamma_lut(state,
475 INTEL_INFO(dev_priv)->color.degamma_lut_size);
477 intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
478 I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
479 POSTING_READ(GAMMA_MODE(pipe));
482 * Reset the index, otherwise it prevents the legacy palette to be
485 I915_WRITE(PREC_PAL_INDEX(pipe), 0);
488 static void glk_load_degamma_lut(struct drm_crtc_state *state)
490 struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
491 enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
492 const uint32_t lut_size = 33;
496 * When setting the auto-increment bit, the hardware seems to
497 * ignore the index bits, so we need to reset it to index 0
500 I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
501 I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
504 * FIXME: The pipe degamma table in geminilake doesn't support
505 * different values per channel, so this just loads a linear table.
507 for (i = 0; i < lut_size; i++) {
508 uint32_t v = (i * (1 << 16)) / (lut_size - 1);
510 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
513 /* Clamp values > 1.0. */
515 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
518 static void glk_load_luts(struct drm_crtc_state *state)
520 struct drm_crtc *crtc = state->crtc;
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = to_i915(dev);
523 struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
524 enum pipe pipe = to_intel_crtc(crtc)->pipe;
526 glk_load_degamma_lut(state);
528 if (crtc_state_is_legacy_gamma(state)) {
529 haswell_load_luts(state);
533 bdw_load_gamma_lut(state, 0);
535 intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
536 I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
537 POSTING_READ(GAMMA_MODE(pipe));
540 /* Loads the palette/gamma unit for the CRTC on CherryView. */
541 static void cherryview_load_luts(struct drm_crtc_state *state)
543 struct drm_crtc *crtc = state->crtc;
544 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
545 enum pipe pipe = to_intel_crtc(crtc)->pipe;
546 struct drm_color_lut *lut;
547 uint32_t i, lut_size;
548 uint32_t word0, word1;
550 if (crtc_state_is_legacy_gamma(state)) {
551 /* Turn off degamma/gamma on CGM block. */
552 I915_WRITE(CGM_PIPE_MODE(pipe),
553 (state->ctm ? CGM_PIPE_MODE_CSC : 0));
554 i9xx_load_luts_internal(crtc, state->gamma_lut,
555 to_intel_crtc_state(state));
559 if (state->degamma_lut) {
560 lut = state->degamma_lut->data;
561 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
562 for (i = 0; i < lut_size; i++) {
563 /* Write LUT in U0.14 format. */
565 (drm_color_lut_extract(lut[i].green, 14) << 16) |
566 drm_color_lut_extract(lut[i].blue, 14);
567 word1 = drm_color_lut_extract(lut[i].red, 14);
569 I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
570 I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
574 if (state->gamma_lut) {
575 lut = state->gamma_lut->data;
576 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
577 for (i = 0; i < lut_size; i++) {
578 /* Write LUT in U0.10 format. */
580 (drm_color_lut_extract(lut[i].green, 10) << 16) |
581 drm_color_lut_extract(lut[i].blue, 10);
582 word1 = drm_color_lut_extract(lut[i].red, 10);
584 I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
585 I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);
589 I915_WRITE(CGM_PIPE_MODE(pipe),
590 (state->ctm ? CGM_PIPE_MODE_CSC : 0) |
591 (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
592 (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
595 * Also program a linear LUT in the legacy block (behind the
598 i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
601 void intel_color_load_luts(struct drm_crtc_state *crtc_state)
603 struct drm_device *dev = crtc_state->crtc->dev;
604 struct drm_i915_private *dev_priv = to_i915(dev);
606 dev_priv->display.load_luts(crtc_state);
609 int intel_color_check(struct drm_crtc *crtc,
610 struct drm_crtc_state *crtc_state)
612 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
613 size_t gamma_length, degamma_length;
615 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
616 sizeof(struct drm_color_lut);
617 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
618 sizeof(struct drm_color_lut);
621 * We allow both degamma & gamma luts at the right size or
624 if ((!crtc_state->degamma_lut ||
625 crtc_state->degamma_lut->length == degamma_length) &&
626 (!crtc_state->gamma_lut ||
627 crtc_state->gamma_lut->length == gamma_length))
631 * We also allow no degamma lut/ctm and a gamma lut at the legacy
632 * size (256 entries).
634 if (crtc_state_is_legacy_gamma(crtc_state))
640 void intel_color_init(struct drm_crtc *crtc)
642 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
644 drm_mode_crtc_set_gamma_size(crtc, 256);
646 if (IS_CHERRYVIEW(dev_priv)) {
647 dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
648 dev_priv->display.load_luts = cherryview_load_luts;
649 } else if (IS_HASWELL(dev_priv)) {
650 dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
651 dev_priv->display.load_luts = haswell_load_luts;
652 } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
653 IS_BROXTON(dev_priv)) {
654 dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
655 dev_priv->display.load_luts = broadwell_load_luts;
656 } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
657 dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
658 dev_priv->display.load_luts = glk_load_luts;
660 dev_priv->display.load_luts = i9xx_load_luts;
663 /* Enable color management support when we have degamma & gamma LUTs. */
664 if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
665 INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
666 drm_crtc_enable_color_mgmt(crtc,
667 INTEL_INFO(dev_priv)->color.degamma_lut_size,
669 INTEL_INFO(dev_priv)->color.gamma_lut_size);