drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67                                    enum pipe *pipe)
  68 {
  69         struct drm_device *dev = encoder->base.dev;
  70         struct drm_i915_private *dev_priv = to_i915(dev);
  71         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72         enum intel_display_power_domain power_domain;
  73         u32 tmp;
  74         bool ret;
  75
  76         power_domain = intel_display_port_power_domain(encoder);
  77         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  78                 return false;
  79
  80         ret = false;
  81
  82         tmp = I915_READ(crt->adpa_reg);
  83
  84         if (!(tmp & ADPA_DAC_ENABLE))
  85                 goto out;
  86
  87         if (HAS_PCH_CPT(dev_priv))
  88                 *pipe = PORT_TO_PIPE_CPT(tmp);
  89         else
  90                 *pipe = PORT_TO_PIPE(tmp);
  91
  92         ret = true;
  93 out:
  94         intel_display_power_put(dev_priv, power_domain);
  95
  96         return ret;
  97 }
  98
  99 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 100 {
 101         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 102         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 103         u32 tmp, flags = 0;
 104
 105         tmp = I915_READ(crt->adpa_reg);
 106
 107         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 108                 flags |= DRM_MODE_FLAG_PHSYNC;
 109         else
 110                 flags |= DRM_MODE_FLAG_NHSYNC;
 111
 112         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 113                 flags |= DRM_MODE_FLAG_PVSYNC;
 114         else
 115                 flags |= DRM_MODE_FLAG_NVSYNC;
 116
 117         return flags;
 118 }
 119
 120 static void intel_crt_get_config(struct intel_encoder *encoder,
 121                                  struct intel_crtc_state *pipe_config)
 122 {
 123         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 124
 125         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 126 }
 127
 128 static void hsw_crt_get_config(struct intel_encoder *encoder,
 129                                struct intel_crtc_state *pipe_config)
 130 {
 131         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 132
 133         intel_ddi_get_config(encoder, pipe_config);
 134
 135         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 136                                               DRM_MODE_FLAG_NHSYNC |
 137                                               DRM_MODE_FLAG_PVSYNC |
 138                                               DRM_MODE_FLAG_NVSYNC);
 139         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 140
 141         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 142 }
 143
 144 /* Note: The caller is required to filter out dpms modes not supported by the
 145  * platform. */
 146 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 147                                struct intel_crtc_state *crtc_state,
 148                                int mode)
 149 {
 150         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 151         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 152         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 153         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 154         u32 adpa;
 155
 156         if (INTEL_GEN(dev_priv) >= 5)
 157                 adpa = ADPA_HOTPLUG_BITS;
 158         else
 159                 adpa = 0;
 160
 161         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 162                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 163         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 164                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 165
 166         /* For CPT allow 3 pipe config, for others just use A or B */
 167         if (HAS_PCH_LPT(dev_priv))
 168                 ; /* Those bits don't exist here */
 169         else if (HAS_PCH_CPT(dev_priv))
 170                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 171         else if (crtc->pipe == 0)
 172                 adpa |= ADPA_PIPE_A_SELECT;
 173         else
 174                 adpa |= ADPA_PIPE_B_SELECT;
 175
 176         if (!HAS_PCH_SPLIT(dev_priv))
 177                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 178
 179         switch (mode) {
 180         case DRM_MODE_DPMS_ON:
 181                 adpa |= ADPA_DAC_ENABLE;
 182                 break;
 183         case DRM_MODE_DPMS_STANDBY:
 184                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 185                 break;
 186         case DRM_MODE_DPMS_SUSPEND:
 187                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 188                 break;
 189         case DRM_MODE_DPMS_OFF:
 190                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 191                 break;
 192         }
 193
 194         I915_WRITE(crt->adpa_reg, adpa);
 195 }
 196
 197 static void intel_disable_crt(struct intel_encoder *encoder,
 198                               struct intel_crtc_state *old_crtc_state,
 199                               struct drm_connector_state *old_conn_state)
 200 {
 201         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 202 }
 203
 204 static void pch_disable_crt(struct intel_encoder *encoder,
 205                             struct intel_crtc_state *old_crtc_state,
 206                             struct drm_connector_state *old_conn_state)
 207 {
 208 }
 209
 210 static void pch_post_disable_crt(struct intel_encoder *encoder,
 211                                  struct intel_crtc_state *old_crtc_state,
 212                                  struct drm_connector_state *old_conn_state)
 213 {
 214         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 215 }
 216
 217 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 218                                  struct intel_crtc_state *old_crtc_state,
 219                                  struct drm_connector_state *old_conn_state)
 220 {
 221         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 222
 223         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 224
 225         lpt_disable_pch_transcoder(dev_priv);
 226         lpt_disable_iclkip(dev_priv);
 227
 228         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 229 }
 230
 231 static void intel_enable_crt(struct intel_encoder *encoder,
 232                              struct intel_crtc_state *pipe_config,
 233                              struct drm_connector_state *conn_state)
 234 {
 235         intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);
 236 }
 237
 238 static enum drm_mode_status
 239 intel_crt_mode_valid(struct drm_connector *connector,
 240                      struct drm_display_mode *mode)
 241 {
 242         struct drm_device *dev = connector->dev;
 243         struct drm_i915_private *dev_priv = to_i915(dev);
 244         int max_dotclk = dev_priv->max_dotclk_freq;
 245         int max_clock;
 246
 247         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 248                 return MODE_NO_DBLESCAN;
 249
 250         if (mode->clock < 25000)
 251                 return MODE_CLOCK_LOW;
 252
 253         if (HAS_PCH_LPT(dev_priv))
 254                 max_clock = 180000;
 255         else if (IS_VALLEYVIEW(dev_priv))
 256                 /*
 257                  * 270 MHz due to current DPLL limits,
 258                  * DAC limit supposedly 355 MHz.
 259                  */
 260                 max_clock = 270000;
 261         else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
 262                 max_clock = 400000;
 263         else
 264                 max_clock = 350000;
 265         if (mode->clock > max_clock)
 266                 return MODE_CLOCK_HIGH;
 267
 268         if (mode->clock > max_dotclk)
 269                 return MODE_CLOCK_HIGH;
 270
 271         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 272         if (HAS_PCH_LPT(dev_priv) &&
 273             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 274                 return MODE_CLOCK_HIGH;
 275
 276         return MODE_OK;
 277 }
 278
 279 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 280                                      struct intel_crtc_state *pipe_config,
 281                                      struct drm_connector_state *conn_state)
 282 {
 283         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 284
 285         if (HAS_PCH_SPLIT(dev_priv))
 286                 pipe_config->has_pch_encoder = true;
 287
 288         /* LPT FDI RX only supports 8bpc. */
 289         if (HAS_PCH_LPT(dev_priv)) {
 290                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 291                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 292                         return false;
 293                 }
 294
 295                 pipe_config->pipe_bpp = 24;
 296         }
 297
 298         /* FDI must always be 2.7 GHz */
 299         if (HAS_DDI(dev_priv))
 300                 pipe_config->port_clock = 135000 * 2;
 301
 302         return true;
 303 }
 304
 305 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 306 {
 307         struct drm_device *dev = connector->dev;
 308         struct intel_crt *crt = intel_attached_crt(connector);
 309         struct drm_i915_private *dev_priv = to_i915(dev);
 310         u32 adpa;
 311         bool ret;
 312
 313         /* The first time through, trigger an explicit detection cycle */
 314         if (crt->force_hotplug_required) {
 315                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 316                 u32 save_adpa;
 317
 318                 crt->force_hotplug_required = 0;
 319
 320                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 321                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 322
 323                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 324                 if (turn_off_dac)
 325                         adpa &= ~ADPA_DAC_ENABLE;
 326
 327                 I915_WRITE(crt->adpa_reg, adpa);
 328
 329                 if (intel_wait_for_register(dev_priv,
 330                                             crt->adpa_reg,
 331                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 332                                             1000))
 333                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 334
 335                 if (turn_off_dac) {
 336                         I915_WRITE(crt->adpa_reg, save_adpa);
 337                         POSTING_READ(crt->adpa_reg);
 338                 }
 339         }
 340
 341         /* Check the status to see if both blue and green are on now */
 342         adpa = I915_READ(crt->adpa_reg);
 343         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 344                 ret = true;
 345         else
 346                 ret = false;
 347         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 348
 349         return ret;
 350 }
 351
 352 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 353 {
 354         struct drm_device *dev = connector->dev;
 355         struct intel_crt *crt = intel_attached_crt(connector);
 356         struct drm_i915_private *dev_priv = to_i915(dev);
 357         bool reenable_hpd;
 358         u32 adpa;
 359         bool ret;
 360         u32 save_adpa;
 361
 362         /*
 363          * Doing a force trigger causes a hpd interrupt to get sent, which can
 364          * get us stuck in a loop if we're polling:
 365          *  - We enable power wells and reset the ADPA
 366          *  - output_poll_exec does force probe on VGA, triggering a hpd
 367          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 368          *  - output_poll_exec shuts off the ADPA, unlocks
 369          *    dev->mode_config.mutex
 370          *  - HPD handler runs, resets ADPA and brings us back to the start
 371          *
 372          * Just disable HPD interrupts here to prevent this
 373          */
 374         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 375
 376         save_adpa = adpa = I915_READ(crt->adpa_reg);
 377         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 378
 379         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 380
 381         I915_WRITE(crt->adpa_reg, adpa);
 382
 383         if (intel_wait_for_register(dev_priv,
 384                                     crt->adpa_reg,
 385                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 386                                     1000)) {
 387                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 388                 I915_WRITE(crt->adpa_reg, save_adpa);
 389         }
 390
 391         /* Check the status to see if both blue and green are on now */
 392         adpa = I915_READ(crt->adpa_reg);
 393         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 394                 ret = true;
 395         else
 396                 ret = false;
 397
 398         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 399
 400         if (reenable_hpd)
 401                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 402
 403         return ret;
 404 }
 405
 406 /**
 407  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 408  *
 409  * Not for i915G/i915GM
 410  *
 411  * \return true if CRT is connected.
 412  * \return false if CRT is disconnected.
 413  */
 414 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 415 {
 416         struct drm_device *dev = connector->dev;
 417         struct drm_i915_private *dev_priv = to_i915(dev);
 418         u32 stat;
 419         bool ret = false;
 420         int i, tries = 0;
 421
 422         if (HAS_PCH_SPLIT(dev_priv))
 423                 return intel_ironlake_crt_detect_hotplug(connector);
 424
 425         if (IS_VALLEYVIEW(dev_priv))
 426                 return valleyview_crt_detect_hotplug(connector);
 427
 428         /*
 429          * On 4 series desktop, CRT detect sequence need to be done twice
 430          * to get a reliable result.
 431          */
 432
 433         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv))
 434                 tries = 2;
 435         else
 436                 tries = 1;
 437
 438         for (i = 0; i < tries ; i++) {
 439                 /* turn on the FORCE_DETECT */
 440                 i915_hotplug_interrupt_update(dev_priv,
 441                                               CRT_HOTPLUG_FORCE_DETECT,
 442                                               CRT_HOTPLUG_FORCE_DETECT);
 443                 /* wait for FORCE_DETECT to go off */
 444                 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
 445                                             CRT_HOTPLUG_FORCE_DETECT, 0,
 446                                             1000))
 447                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 448         }
 449
 450         stat = I915_READ(PORT_HOTPLUG_STAT);
 451         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 452                 ret = true;
 453
 454         /* clear the interrupt we just generated, if any */
 455         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 456
 457         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 458
 459         return ret;
 460 }
 461
 462 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 463                                 struct i2c_adapter *i2c)
 464 {
 465         struct edid *edid;
 466
 467         edid = drm_get_edid(connector, i2c);
 468
 469         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 470                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 471                 intel_gmbus_force_bit(i2c, true);
 472                 edid = drm_get_edid(connector, i2c);
 473                 intel_gmbus_force_bit(i2c, false);
 474         }
 475
 476         return edid;
 477 }
 478
 479 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 480 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 481                                 struct i2c_adapter *adapter)
 482 {
 483         struct edid *edid;
 484         int ret;
 485
 486         edid = intel_crt_get_edid(connector, adapter);
 487         if (!edid)
 488                 return 0;
 489
 490         ret = intel_connector_update_modes(connector, edid);
 491         kfree(edid);
 492
 493         return ret;
 494 }
 495
 496 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 497 {
 498         struct intel_crt *crt = intel_attached_crt(connector);
 499         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 500         struct edid *edid;
 501         struct i2c_adapter *i2c;
 502
 503         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 504
 505         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 506         edid = intel_crt_get_edid(connector, i2c);
 507
 508         if (edid) {
 509                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 510
 511                 /*
 512                  * This may be a DVI-I connector with a shared DDC
 513                  * link between analog and digital outputs, so we
 514                  * have to check the EDID input spec of the attached device.
 515                  */
 516                 if (!is_digital) {
 517                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 518                         return true;
 519                 }
 520
 521                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 522         } else {
 523                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 524         }
 525
 526         kfree(edid);
 527
 528         return false;
 529 }
 530
 531 static enum drm_connector_status
 532 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
 533 {
 534         struct drm_device *dev = crt->base.base.dev;
 535         struct drm_i915_private *dev_priv = to_i915(dev);
 536         uint32_t save_bclrpat;
 537         uint32_t save_vtotal;
 538         uint32_t vtotal, vactive;
 539         uint32_t vsample;
 540         uint32_t vblank, vblank_start, vblank_end;
 541         uint32_t dsl;
 542         i915_reg_t bclrpat_reg, vtotal_reg,
 543                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 544         uint8_t st00;
 545         enum drm_connector_status status;
 546
 547         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 548
 549         bclrpat_reg = BCLRPAT(pipe);
 550         vtotal_reg = VTOTAL(pipe);
 551         vblank_reg = VBLANK(pipe);
 552         vsync_reg = VSYNC(pipe);
 553         pipeconf_reg = PIPECONF(pipe);
 554         pipe_dsl_reg = PIPEDSL(pipe);
 555
 556         save_bclrpat = I915_READ(bclrpat_reg);
 557         save_vtotal = I915_READ(vtotal_reg);
 558         vblank = I915_READ(vblank_reg);
 559
 560         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 561         vactive = (save_vtotal & 0x7ff) + 1;
 562
 563         vblank_start = (vblank & 0xfff) + 1;
 564         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 565
 566         /* Set the border color to purple. */
 567         I915_WRITE(bclrpat_reg, 0x500050);
 568
 569         if (!IS_GEN2(dev_priv)) {
 570                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 571                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 572                 POSTING_READ(pipeconf_reg);
 573                 /* Wait for next Vblank to substitue
 574                  * border color for Color info */
 575                 intel_wait_for_vblank(dev_priv, pipe);
 576                 st00 = I915_READ8(_VGA_MSR_WRITE);
 577                 status = ((st00 & (1 << 4)) != 0) ?
 578                         connector_status_connected :
 579                         connector_status_disconnected;
 580
 581                 I915_WRITE(pipeconf_reg, pipeconf);
 582         } else {
 583                 bool restore_vblank = false;
 584                 int count, detect;
 585
 586                 /*
 587                 * If there isn't any border, add some.
 588                 * Yes, this will flicker
 589                 */
 590                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 591                         uint32_t vsync = I915_READ(vsync_reg);
 592                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 593
 594                         vblank_start = vsync_start;
 595                         I915_WRITE(vblank_reg,
 596                                    (vblank_start - 1) |
 597                                    ((vblank_end - 1) << 16));
 598                         restore_vblank = true;
 599                 }
 600                 /* sample in the vertical border, selecting the larger one */
 601                 if (vblank_start - vactive >= vtotal - vblank_end)
 602                         vsample = (vblank_start + vactive) >> 1;
 603                 else
 604                         vsample = (vtotal + vblank_end) >> 1;
 605
 606                 /*
 607                  * Wait for the border to be displayed
 608                  */
 609                 while (I915_READ(pipe_dsl_reg) >= vactive)
 610                         ;
 611                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 612                         ;
 613                 /*
 614                  * Watch ST00 for an entire scanline
 615                  */
 616                 detect = 0;
 617                 count = 0;
 618                 do {
 619                         count++;
 620                         /* Read the ST00 VGA status register */
 621                         st00 = I915_READ8(_VGA_MSR_WRITE);
 622                         if (st00 & (1 << 4))
 623                                 detect++;
 624                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 625
 626                 /* restore vblank if necessary */
 627                 if (restore_vblank)
 628                         I915_WRITE(vblank_reg, vblank);
 629                 /*
 630                  * If more than 3/4 of the scanline detected a monitor,
 631                  * then it is assumed to be present. This works even on i830,
 632                  * where there isn't any way to force the border color across
 633                  * the screen
 634                  */
 635                 status = detect * 4 > count * 3 ?
 636                          connector_status_connected :
 637                          connector_status_disconnected;
 638         }
 639
 640         /* Restore previous settings */
 641         I915_WRITE(bclrpat_reg, save_bclrpat);
 642
 643         return status;
 644 }
 645
 646 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 647 {
 648         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 649         return 1;
 650 }
 651
 652 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 653         {
 654                 .callback = intel_spurious_crt_detect_dmi_callback,
 655                 .ident = "ACER ZGB",
 656                 .matches = {
 657                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 658                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 659                 },
 660         },
 661         {
 662                 .callback = intel_spurious_crt_detect_dmi_callback,
 663                 .ident = "Intel DZ77BH-55K",
 664                 .matches = {
 665                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 666                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 667                 },
 668         },
 669         { }
 670 };
 671
 672 static enum drm_connector_status
 673 intel_crt_detect(struct drm_connector *connector, bool force)
 674 {
 675         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 676         struct intel_crt *crt = intel_attached_crt(connector);
 677         struct intel_encoder *intel_encoder = &crt->base;
 678         enum intel_display_power_domain power_domain;
 679         enum drm_connector_status status;
 680         struct intel_load_detect_pipe tmp;
 681         struct drm_modeset_acquire_ctx ctx;
 682
 683         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 684                       connector->base.id, connector->name,
 685                       force);
 686
 687         /* Skip machines without VGA that falsely report hotplug events */
 688         if (dmi_check_system(intel_spurious_crt_detect))
 689                 return connector_status_disconnected;
 690
 691         power_domain = intel_display_port_power_domain(intel_encoder);
 692         intel_display_power_get(dev_priv, power_domain);
 693
 694         if (I915_HAS_HOTPLUG(dev_priv)) {
 695                 /* We can not rely on the HPD pin always being correctly wired
 696                  * up, for example many KVM do not pass it through, and so
 697                  * only trust an assertion that the monitor is connected.
 698                  */
 699                 if (intel_crt_detect_hotplug(connector)) {
 700                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 701                         status = connector_status_connected;
 702                         goto out;
 703                 } else
 704                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 705         }
 706
 707         if (intel_crt_detect_ddc(connector)) {
 708                 status = connector_status_connected;
 709                 goto out;
 710         }
 711
 712         /* Load detection is broken on HPD capable machines. Whoever wants a
 713          * broken monitor (without edid) to work behind a broken kvm (that fails
 714          * to have the right resistors for HP detection) needs to fix this up.
 715          * For now just bail out. */
 716         if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) {
 717                 status = connector_status_disconnected;
 718                 goto out;
 719         }
 720
 721         if (!force) {
 722                 status = connector->status;
 723                 goto out;
 724         }
 725
 726         drm_modeset_acquire_init(&ctx, 0);
 727
 728         /* for pre-945g platforms use load detect */
 729         if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
 730                 if (intel_crt_detect_ddc(connector))
 731                         status = connector_status_connected;
 732                 else if (INTEL_GEN(dev_priv) < 4)
 733                         status = intel_crt_load_detect(crt,
 734                                 to_intel_crtc(connector->state->crtc)->pipe);
 735                 else if (i915.load_detect_test)
 736                         status = connector_status_disconnected;
 737                 else
 738                         status = connector_status_unknown;
 739                 intel_release_load_detect_pipe(connector, &tmp, &ctx);
 740         } else
 741                 status = connector_status_unknown;
 742
 743         drm_modeset_drop_locks(&ctx);
 744         drm_modeset_acquire_fini(&ctx);
 745
 746 out:
 747         intel_display_power_put(dev_priv, power_domain);
 748         return status;
 749 }
 750
 751 static void intel_crt_destroy(struct drm_connector *connector)
 752 {
 753         drm_connector_cleanup(connector);
 754         kfree(connector);
 755 }
 756
 757 static int intel_crt_get_modes(struct drm_connector *connector)
 758 {
 759         struct drm_device *dev = connector->dev;
 760         struct drm_i915_private *dev_priv = to_i915(dev);
 761         struct intel_crt *crt = intel_attached_crt(connector);
 762         struct intel_encoder *intel_encoder = &crt->base;
 763         enum intel_display_power_domain power_domain;
 764         int ret;
 765         struct i2c_adapter *i2c;
 766
 767         power_domain = intel_display_port_power_domain(intel_encoder);
 768         intel_display_power_get(dev_priv, power_domain);
 769
 770         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 771         ret = intel_crt_ddc_get_modes(connector, i2c);
 772         if (ret || !IS_G4X(dev_priv))
 773                 goto out;
 774
 775         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 776         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 777         ret = intel_crt_ddc_get_modes(connector, i2c);
 778
 779 out:
 780         intel_display_power_put(dev_priv, power_domain);
 781
 782         return ret;
 783 }
 784
 785 static int intel_crt_set_property(struct drm_connector *connector,
 786                                   struct drm_property *property,
 787                                   uint64_t value)
 788 {
 789         return 0;
 790 }
 791
 792 void intel_crt_reset(struct drm_encoder *encoder)
 793 {
 794         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 795         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 796
 797         if (INTEL_GEN(dev_priv) >= 5) {
 798                 u32 adpa;
 799
 800                 adpa = I915_READ(crt->adpa_reg);
 801                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 802                 adpa |= ADPA_HOTPLUG_BITS;
 803                 I915_WRITE(crt->adpa_reg, adpa);
 804                 POSTING_READ(crt->adpa_reg);
 805
 806                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 807                 crt->force_hotplug_required = 1;
 808         }
 809
 810 }
 811
 812 /*
 813  * Routines for controlling stuff on the analog port
 814  */
 815
 816 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 817         .dpms = drm_atomic_helper_connector_dpms,
 818         .detect = intel_crt_detect,
 819         .fill_modes = drm_helper_probe_single_connector_modes,
 820         .late_register = intel_connector_register,
 821         .early_unregister = intel_connector_unregister,
 822         .destroy = intel_crt_destroy,
 823         .set_property = intel_crt_set_property,
 824         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 825         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 826         .atomic_get_property = intel_connector_atomic_get_property,
 827 };
 828
 829 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 830         .mode_valid = intel_crt_mode_valid,
 831         .get_modes = intel_crt_get_modes,
 832 };
 833
 834 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 835         .reset = intel_crt_reset,
 836         .destroy = intel_encoder_destroy,
 837 };
 838
 839 void intel_crt_init(struct drm_device *dev)
 840 {
 841         struct drm_connector *connector;
 842         struct intel_crt *crt;
 843         struct intel_connector *intel_connector;
 844         struct drm_i915_private *dev_priv = to_i915(dev);
 845         i915_reg_t adpa_reg;
 846         u32 adpa;
 847
 848         if (HAS_PCH_SPLIT(dev_priv))
 849                 adpa_reg = PCH_ADPA;
 850         else if (IS_VALLEYVIEW(dev_priv))
 851                 adpa_reg = VLV_ADPA;
 852         else
 853                 adpa_reg = ADPA;
 854
 855         adpa = I915_READ(adpa_reg);
 856         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 857                 /*
 858                  * On some machines (some IVB at least) CRT can be
 859                  * fused off, but there's no known fuse bit to
 860                  * indicate that. On these machine the ADPA register
 861                  * works normally, except the DAC enable bit won't
 862                  * take. So the only way to tell is attempt to enable
 863                  * it and see what happens.
 864                  */
 865                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 866                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 867                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 868                         return;
 869                 I915_WRITE(adpa_reg, adpa);
 870         }
 871
 872         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 873         if (!crt)
 874                 return;
 875
 876         intel_connector = intel_connector_alloc();
 877         if (!intel_connector) {
 878                 kfree(crt);
 879                 return;
 880         }
 881
 882         connector = &intel_connector->base;
 883         crt->connector = intel_connector;
 884         drm_connector_init(dev, &intel_connector->base,
 885                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 886
 887         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
 888                          DRM_MODE_ENCODER_DAC, "CRT");
 889
 890         intel_connector_attach_encoder(intel_connector, &crt->base);
 891
 892         crt->base.type = INTEL_OUTPUT_ANALOG;
 893         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 894         if (IS_I830(dev_priv))
 895                 crt->base.crtc_mask = (1 << 0);
 896         else
 897                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 898
 899         if (IS_GEN2(dev_priv))
 900                 connector->interlace_allowed = 0;
 901         else
 902                 connector->interlace_allowed = 1;
 903         connector->doublescan_allowed = 0;
 904
 905         crt->adpa_reg = adpa_reg;
 906
 907         crt->base.compute_config = intel_crt_compute_config;
 908         if (HAS_PCH_SPLIT(dev_priv)) {
 909                 crt->base.disable = pch_disable_crt;
 910                 crt->base.post_disable = pch_post_disable_crt;
 911         } else {
 912                 crt->base.disable = intel_disable_crt;
 913         }
 914         crt->base.enable = intel_enable_crt;
 915         if (I915_HAS_HOTPLUG(dev_priv) &&
 916             !dmi_check_system(intel_spurious_crt_detect))
 917                 crt->base.hpd_pin = HPD_CRT;
 918         if (HAS_DDI(dev_priv)) {
 919                 crt->base.port = PORT_E;
 920                 crt->base.get_config = hsw_crt_get_config;
 921                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 922                 crt->base.post_disable = hsw_post_disable_crt;
 923         } else {
 924                 crt->base.port = PORT_NONE;
 925                 crt->base.get_config = intel_crt_get_config;
 926                 crt->base.get_hw_state = intel_crt_get_hw_state;
 927         }
 928         intel_connector->get_hw_state = intel_connector_get_hw_state;
 929
 930         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 931
 932         if (!I915_HAS_HOTPLUG(dev_priv))
 933                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 934
 935         /*
 936          * Configure the automatic hotplug detection stuff
 937          */
 938         crt->force_hotplug_required = 0;
 939
 940         /*
 941          * TODO: find a proper way to discover whether we need to set the the
 942          * polarity and link reversal bits or not, instead of relying on the
 943          * BIOS.
 944          */
 945         if (HAS_PCH_LPT(dev_priv)) {
 946                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 947                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
 948
 949                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
 950         }
 951
 952         intel_crt_reset(&crt->base.base);
 953 }