drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_edid.h>
  34 #include <drm/drm_probe_helper.h>
  35 #include <drm/i915_drm.h>
  36
  37 #include "i915_drv.h"
  38 #include "intel_connector.h"
  39 #include "intel_crt.h"
  40 #include "intel_ddi.h"
  41 #include "intel_drv.h"
  42
  43 /* Here's the desired hotplug mode */
  44 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  45                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  46                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  47                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  48                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  49                            ADPA_CRT_HOTPLUG_ENABLE)
  50
  51 struct intel_crt {
  52         struct intel_encoder base;
  53         /* DPMS state is stored in the connector, which we need in the
  54          * encoder's enable/disable callbacks */
  55         struct intel_connector *connector;
  56         bool force_hotplug_required;
  57         i915_reg_t adpa_reg;
  58 };
  59
  60 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  61 {
  62         return container_of(encoder, struct intel_crt, base);
  63 }
  64
  65 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  66 {
  67         return intel_encoder_to_crt(intel_attached_encoder(connector));
  68 }
  69
  70 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
  71                             i915_reg_t adpa_reg, enum pipe *pipe)
  72 {
  73         u32 val;
  74
  75         val = I915_READ(adpa_reg);
  76
  77         /* asserts want to know the pipe even if the port is disabled */
  78         if (HAS_PCH_CPT(dev_priv))
  79                 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
  80         else
  81                 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
  82
  83         return val & ADPA_DAC_ENABLE;
  84 }
  85
  86 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  87                                    enum pipe *pipe)
  88 {
  89         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  90         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  91         intel_wakeref_t wakeref;
  92         bool ret;
  93
  94         wakeref = intel_display_power_get_if_enabled(dev_priv,
  95                                                      encoder->power_domain);
  96         if (!wakeref)
  97                 return false;
  98
  99         ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
 100
 101         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 102
 103         return ret;
 104 }
 105
 106 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 107 {
 108         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 109         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 110         u32 tmp, flags = 0;
 111
 112         tmp = I915_READ(crt->adpa_reg);
 113
 114         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 115                 flags |= DRM_MODE_FLAG_PHSYNC;
 116         else
 117                 flags |= DRM_MODE_FLAG_NHSYNC;
 118
 119         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 120                 flags |= DRM_MODE_FLAG_PVSYNC;
 121         else
 122                 flags |= DRM_MODE_FLAG_NVSYNC;
 123
 124         return flags;
 125 }
 126
 127 static void intel_crt_get_config(struct intel_encoder *encoder,
 128                                  struct intel_crtc_state *pipe_config)
 129 {
 130         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 131
 132         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 133
 134         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 135 }
 136
 137 static void hsw_crt_get_config(struct intel_encoder *encoder,
 138                                struct intel_crtc_state *pipe_config)
 139 {
 140         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 141
 142         intel_ddi_get_config(encoder, pipe_config);
 143
 144         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 145                                               DRM_MODE_FLAG_NHSYNC |
 146                                               DRM_MODE_FLAG_PVSYNC |
 147                                               DRM_MODE_FLAG_NVSYNC);
 148         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 149
 150         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 151 }
 152
 153 /* Note: The caller is required to filter out dpms modes not supported by the
 154  * platform. */
 155 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 156                                const struct intel_crtc_state *crtc_state,
 157                                int mode)
 158 {
 159         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 160         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 161         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 162         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 163         u32 adpa;
 164
 165         if (INTEL_GEN(dev_priv) >= 5)
 166                 adpa = ADPA_HOTPLUG_BITS;
 167         else
 168                 adpa = 0;
 169
 170         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 171                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 172         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 173                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 174
 175         /* For CPT allow 3 pipe config, for others just use A or B */
 176         if (HAS_PCH_LPT(dev_priv))
 177                 ; /* Those bits don't exist here */
 178         else if (HAS_PCH_CPT(dev_priv))
 179                 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
 180         else
 181                 adpa |= ADPA_PIPE_SEL(crtc->pipe);
 182
 183         if (!HAS_PCH_SPLIT(dev_priv))
 184                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 185
 186         switch (mode) {
 187         case DRM_MODE_DPMS_ON:
 188                 adpa |= ADPA_DAC_ENABLE;
 189                 break;
 190         case DRM_MODE_DPMS_STANDBY:
 191                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 192                 break;
 193         case DRM_MODE_DPMS_SUSPEND:
 194                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 195                 break;
 196         case DRM_MODE_DPMS_OFF:
 197                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 198                 break;
 199         }
 200
 201         I915_WRITE(crt->adpa_reg, adpa);
 202 }
 203
 204 static void intel_disable_crt(struct intel_encoder *encoder,
 205                               const struct intel_crtc_state *old_crtc_state,
 206                               const struct drm_connector_state *old_conn_state)
 207 {
 208         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 209 }
 210
 211 static void pch_disable_crt(struct intel_encoder *encoder,
 212                             const struct intel_crtc_state *old_crtc_state,
 213                             const struct drm_connector_state *old_conn_state)
 214 {
 215 }
 216
 217 static void pch_post_disable_crt(struct intel_encoder *encoder,
 218                                  const struct intel_crtc_state *old_crtc_state,
 219                                  const struct drm_connector_state *old_conn_state)
 220 {
 221         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 222 }
 223
 224 static void hsw_disable_crt(struct intel_encoder *encoder,
 225                             const struct intel_crtc_state *old_crtc_state,
 226                             const struct drm_connector_state *old_conn_state)
 227 {
 228         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 229
 230         WARN_ON(!old_crtc_state->has_pch_encoder);
 231
 232         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 233 }
 234
 235 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 236                                  const struct intel_crtc_state *old_crtc_state,
 237                                  const struct drm_connector_state *old_conn_state)
 238 {
 239         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 240
 241         intel_ddi_disable_pipe_clock(old_crtc_state);
 242
 243         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 244
 245         lpt_disable_pch_transcoder(dev_priv);
 246         lpt_disable_iclkip(dev_priv);
 247
 248         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 249
 250         WARN_ON(!old_crtc_state->has_pch_encoder);
 251
 252         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 253 }
 254
 255 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 256                                    const struct intel_crtc_state *crtc_state,
 257                                    const struct drm_connector_state *conn_state)
 258 {
 259         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 260
 261         WARN_ON(!crtc_state->has_pch_encoder);
 262
 263         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 264 }
 265
 266 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 267                                const struct intel_crtc_state *crtc_state,
 268                                const struct drm_connector_state *conn_state)
 269 {
 270         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 271         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 272         enum pipe pipe = crtc->pipe;
 273
 274         WARN_ON(!crtc_state->has_pch_encoder);
 275
 276         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 277
 278         dev_priv->display.fdi_link_train(crtc, crtc_state);
 279
 280         intel_ddi_enable_pipe_clock(crtc_state);
 281 }
 282
 283 static void hsw_enable_crt(struct intel_encoder *encoder,
 284                            const struct intel_crtc_state *crtc_state,
 285                            const struct drm_connector_state *conn_state)
 286 {
 287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 288         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 289         enum pipe pipe = crtc->pipe;
 290
 291         WARN_ON(!crtc_state->has_pch_encoder);
 292
 293         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 294
 295         intel_wait_for_vblank(dev_priv, pipe);
 296         intel_wait_for_vblank(dev_priv, pipe);
 297         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 298         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 299 }
 300
 301 static void intel_enable_crt(struct intel_encoder *encoder,
 302                              const struct intel_crtc_state *crtc_state,
 303                              const struct drm_connector_state *conn_state)
 304 {
 305         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 306 }
 307
 308 static enum drm_mode_status
 309 intel_crt_mode_valid(struct drm_connector *connector,
 310                      struct drm_display_mode *mode)
 311 {
 312         struct drm_device *dev = connector->dev;
 313         struct drm_i915_private *dev_priv = to_i915(dev);
 314         int max_dotclk = dev_priv->max_dotclk_freq;
 315         int max_clock;
 316
 317         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 318                 return MODE_NO_DBLESCAN;
 319
 320         if (mode->clock < 25000)
 321                 return MODE_CLOCK_LOW;
 322
 323         if (HAS_PCH_LPT(dev_priv))
 324                 max_clock = 180000;
 325         else if (IS_VALLEYVIEW(dev_priv))
 326                 /*
 327                  * 270 MHz due to current DPLL limits,
 328                  * DAC limit supposedly 355 MHz.
 329                  */
 330                 max_clock = 270000;
 331         else if (IS_GEN_RANGE(dev_priv, 3, 4))
 332                 max_clock = 400000;
 333         else
 334                 max_clock = 350000;
 335         if (mode->clock > max_clock)
 336                 return MODE_CLOCK_HIGH;
 337
 338         if (mode->clock > max_dotclk)
 339                 return MODE_CLOCK_HIGH;
 340
 341         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 342         if (HAS_PCH_LPT(dev_priv) &&
 343             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 344                 return MODE_CLOCK_HIGH;
 345
 346         /* HSW/BDW FDI limited to 4k */
 347         if (mode->hdisplay > 4096)
 348                 return MODE_H_ILLEGAL;
 349
 350         return MODE_OK;
 351 }
 352
 353 static int intel_crt_compute_config(struct intel_encoder *encoder,
 354                                     struct intel_crtc_state *pipe_config,
 355                                     struct drm_connector_state *conn_state)
 356 {
 357         struct drm_display_mode *adjusted_mode =
 358                 &pipe_config->base.adjusted_mode;
 359
 360         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 361                 return -EINVAL;
 362
 363         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 364
 365         return 0;
 366 }
 367
 368 static int pch_crt_compute_config(struct intel_encoder *encoder,
 369                                   struct intel_crtc_state *pipe_config,
 370                                   struct drm_connector_state *conn_state)
 371 {
 372         struct drm_display_mode *adjusted_mode =
 373                 &pipe_config->base.adjusted_mode;
 374
 375         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 376                 return -EINVAL;
 377
 378         pipe_config->has_pch_encoder = true;
 379         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 380
 381         return 0;
 382 }
 383
 384 static int hsw_crt_compute_config(struct intel_encoder *encoder,
 385                                   struct intel_crtc_state *pipe_config,
 386                                   struct drm_connector_state *conn_state)
 387 {
 388         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 389         struct drm_display_mode *adjusted_mode =
 390                 &pipe_config->base.adjusted_mode;
 391
 392         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 393                 return -EINVAL;
 394
 395         /* HSW/BDW FDI limited to 4k */
 396         if (adjusted_mode->crtc_hdisplay > 4096 ||
 397             adjusted_mode->crtc_hblank_start > 4096)
 398                 return -EINVAL;
 399
 400         pipe_config->has_pch_encoder = true;
 401         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 402
 403         /* LPT FDI RX only supports 8bpc. */
 404         if (HAS_PCH_LPT(dev_priv)) {
 405                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 406                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 407                         return -EINVAL;
 408                 }
 409
 410                 pipe_config->pipe_bpp = 24;
 411         }
 412
 413         /* FDI must always be 2.7 GHz */
 414         pipe_config->port_clock = 135000 * 2;
 415
 416         return 0;
 417 }
 418
 419 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 420 {
 421         struct drm_device *dev = connector->dev;
 422         struct intel_crt *crt = intel_attached_crt(connector);
 423         struct drm_i915_private *dev_priv = to_i915(dev);
 424         u32 adpa;
 425         bool ret;
 426
 427         /* The first time through, trigger an explicit detection cycle */
 428         if (crt->force_hotplug_required) {
 429                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 430                 u32 save_adpa;
 431
 432                 crt->force_hotplug_required = 0;
 433
 434                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 435                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 436
 437                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 438                 if (turn_off_dac)
 439                         adpa &= ~ADPA_DAC_ENABLE;
 440
 441                 I915_WRITE(crt->adpa_reg, adpa);
 442
 443                 if (intel_wait_for_register(&dev_priv->uncore,
 444                                             crt->adpa_reg,
 445                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 446                                             1000))
 447                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 448
 449                 if (turn_off_dac) {
 450                         I915_WRITE(crt->adpa_reg, save_adpa);
 451                         POSTING_READ(crt->adpa_reg);
 452                 }
 453         }
 454
 455         /* Check the status to see if both blue and green are on now */
 456         adpa = I915_READ(crt->adpa_reg);
 457         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 458                 ret = true;
 459         else
 460                 ret = false;
 461         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 462
 463         return ret;
 464 }
 465
 466 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 467 {
 468         struct drm_device *dev = connector->dev;
 469         struct intel_crt *crt = intel_attached_crt(connector);
 470         struct drm_i915_private *dev_priv = to_i915(dev);
 471         bool reenable_hpd;
 472         u32 adpa;
 473         bool ret;
 474         u32 save_adpa;
 475
 476         /*
 477          * Doing a force trigger causes a hpd interrupt to get sent, which can
 478          * get us stuck in a loop if we're polling:
 479          *  - We enable power wells and reset the ADPA
 480          *  - output_poll_exec does force probe on VGA, triggering a hpd
 481          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 482          *  - output_poll_exec shuts off the ADPA, unlocks
 483          *    dev->mode_config.mutex
 484          *  - HPD handler runs, resets ADPA and brings us back to the start
 485          *
 486          * Just disable HPD interrupts here to prevent this
 487          */
 488         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 489
 490         save_adpa = adpa = I915_READ(crt->adpa_reg);
 491         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 492
 493         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 494
 495         I915_WRITE(crt->adpa_reg, adpa);
 496
 497         if (intel_wait_for_register(&dev_priv->uncore,
 498                                     crt->adpa_reg,
 499                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 500                                     1000)) {
 501                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 502                 I915_WRITE(crt->adpa_reg, save_adpa);
 503         }
 504
 505         /* Check the status to see if both blue and green are on now */
 506         adpa = I915_READ(crt->adpa_reg);
 507         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 508                 ret = true;
 509         else
 510                 ret = false;
 511
 512         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 513
 514         if (reenable_hpd)
 515                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 516
 517         return ret;
 518 }
 519
 520 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 521 {
 522         struct drm_device *dev = connector->dev;
 523         struct drm_i915_private *dev_priv = to_i915(dev);
 524         u32 stat;
 525         bool ret = false;
 526         int i, tries = 0;
 527
 528         if (HAS_PCH_SPLIT(dev_priv))
 529                 return intel_ironlake_crt_detect_hotplug(connector);
 530
 531         if (IS_VALLEYVIEW(dev_priv))
 532                 return valleyview_crt_detect_hotplug(connector);
 533
 534         /*
 535          * On 4 series desktop, CRT detect sequence need to be done twice
 536          * to get a reliable result.
 537          */
 538
 539         if (IS_G45(dev_priv))
 540                 tries = 2;
 541         else
 542                 tries = 1;
 543
 544         for (i = 0; i < tries ; i++) {
 545                 /* turn on the FORCE_DETECT */
 546                 i915_hotplug_interrupt_update(dev_priv,
 547                                               CRT_HOTPLUG_FORCE_DETECT,
 548                                               CRT_HOTPLUG_FORCE_DETECT);
 549                 /* wait for FORCE_DETECT to go off */
 550                 if (intel_wait_for_register(&dev_priv->uncore, PORT_HOTPLUG_EN,
 551                                             CRT_HOTPLUG_FORCE_DETECT, 0,
 552                                             1000))
 553                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 554         }
 555
 556         stat = I915_READ(PORT_HOTPLUG_STAT);
 557         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 558                 ret = true;
 559
 560         /* clear the interrupt we just generated, if any */
 561         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 562
 563         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 564
 565         return ret;
 566 }
 567
 568 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 569                                 struct i2c_adapter *i2c)
 570 {
 571         struct edid *edid;
 572
 573         edid = drm_get_edid(connector, i2c);
 574
 575         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 576                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 577                 intel_gmbus_force_bit(i2c, true);
 578                 edid = drm_get_edid(connector, i2c);
 579                 intel_gmbus_force_bit(i2c, false);
 580         }
 581
 582         return edid;
 583 }
 584
 585 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 586 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 587                                 struct i2c_adapter *adapter)
 588 {
 589         struct edid *edid;
 590         int ret;
 591
 592         edid = intel_crt_get_edid(connector, adapter);
 593         if (!edid)
 594                 return 0;
 595
 596         ret = intel_connector_update_modes(connector, edid);
 597         kfree(edid);
 598
 599         return ret;
 600 }
 601
 602 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 603 {
 604         struct intel_crt *crt = intel_attached_crt(connector);
 605         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 606         struct edid *edid;
 607         struct i2c_adapter *i2c;
 608         bool ret = false;
 609
 610         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 611
 612         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 613         edid = intel_crt_get_edid(connector, i2c);
 614
 615         if (edid) {
 616                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 617
 618                 /*
 619                  * This may be a DVI-I connector with a shared DDC
 620                  * link between analog and digital outputs, so we
 621                  * have to check the EDID input spec of the attached device.
 622                  */
 623                 if (!is_digital) {
 624                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 625                         ret = true;
 626                 } else {
 627                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 628                 }
 629         } else {
 630                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 631         }
 632
 633         kfree(edid);
 634
 635         return ret;
 636 }
 637
 638 static enum drm_connector_status
 639 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
 640 {
 641         struct drm_device *dev = crt->base.base.dev;
 642         struct drm_i915_private *dev_priv = to_i915(dev);
 643         u32 save_bclrpat;
 644         u32 save_vtotal;
 645         u32 vtotal, vactive;
 646         u32 vsample;
 647         u32 vblank, vblank_start, vblank_end;
 648         u32 dsl;
 649         i915_reg_t bclrpat_reg, vtotal_reg,
 650                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 651         u8 st00;
 652         enum drm_connector_status status;
 653
 654         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 655
 656         bclrpat_reg = BCLRPAT(pipe);
 657         vtotal_reg = VTOTAL(pipe);
 658         vblank_reg = VBLANK(pipe);
 659         vsync_reg = VSYNC(pipe);
 660         pipeconf_reg = PIPECONF(pipe);
 661         pipe_dsl_reg = PIPEDSL(pipe);
 662
 663         save_bclrpat = I915_READ(bclrpat_reg);
 664         save_vtotal = I915_READ(vtotal_reg);
 665         vblank = I915_READ(vblank_reg);
 666
 667         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 668         vactive = (save_vtotal & 0x7ff) + 1;
 669
 670         vblank_start = (vblank & 0xfff) + 1;
 671         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 672
 673         /* Set the border color to purple. */
 674         I915_WRITE(bclrpat_reg, 0x500050);
 675
 676         if (!IS_GEN(dev_priv, 2)) {
 677                 u32 pipeconf = I915_READ(pipeconf_reg);
 678                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 679                 POSTING_READ(pipeconf_reg);
 680                 /* Wait for next Vblank to substitue
 681                  * border color for Color info */
 682                 intel_wait_for_vblank(dev_priv, pipe);
 683                 st00 = I915_READ8(_VGA_MSR_WRITE);
 684                 status = ((st00 & (1 << 4)) != 0) ?
 685                         connector_status_connected :
 686                         connector_status_disconnected;
 687
 688                 I915_WRITE(pipeconf_reg, pipeconf);
 689         } else {
 690                 bool restore_vblank = false;
 691                 int count, detect;
 692
 693                 /*
 694                 * If there isn't any border, add some.
 695                 * Yes, this will flicker
 696                 */
 697                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 698                         u32 vsync = I915_READ(vsync_reg);
 699                         u32 vsync_start = (vsync & 0xffff) + 1;
 700
 701                         vblank_start = vsync_start;
 702                         I915_WRITE(vblank_reg,
 703                                    (vblank_start - 1) |
 704                                    ((vblank_end - 1) << 16));
 705                         restore_vblank = true;
 706                 }
 707                 /* sample in the vertical border, selecting the larger one */
 708                 if (vblank_start - vactive >= vtotal - vblank_end)
 709                         vsample = (vblank_start + vactive) >> 1;
 710                 else
 711                         vsample = (vtotal + vblank_end) >> 1;
 712
 713                 /*
 714                  * Wait for the border to be displayed
 715                  */
 716                 while (I915_READ(pipe_dsl_reg) >= vactive)
 717                         ;
 718                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 719                         ;
 720                 /*
 721                  * Watch ST00 for an entire scanline
 722                  */
 723                 detect = 0;
 724                 count = 0;
 725                 do {
 726                         count++;
 727                         /* Read the ST00 VGA status register */
 728                         st00 = I915_READ8(_VGA_MSR_WRITE);
 729                         if (st00 & (1 << 4))
 730                                 detect++;
 731                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 732
 733                 /* restore vblank if necessary */
 734                 if (restore_vblank)
 735                         I915_WRITE(vblank_reg, vblank);
 736                 /*
 737                  * If more than 3/4 of the scanline detected a monitor,
 738                  * then it is assumed to be present. This works even on i830,
 739                  * where there isn't any way to force the border color across
 740                  * the screen
 741                  */
 742                 status = detect * 4 > count * 3 ?
 743                          connector_status_connected :
 744                          connector_status_disconnected;
 745         }
 746
 747         /* Restore previous settings */
 748         I915_WRITE(bclrpat_reg, save_bclrpat);
 749
 750         return status;
 751 }
 752
 753 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 754 {
 755         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 756         return 1;
 757 }
 758
 759 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 760         {
 761                 .callback = intel_spurious_crt_detect_dmi_callback,
 762                 .ident = "ACER ZGB",
 763                 .matches = {
 764                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 765                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 766                 },
 767         },
 768         {
 769                 .callback = intel_spurious_crt_detect_dmi_callback,
 770                 .ident = "Intel DZ77BH-55K",
 771                 .matches = {
 772                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 773                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 774                 },
 775         },
 776         { }
 777 };
 778
 779 static int
 780 intel_crt_detect(struct drm_connector *connector,
 781                  struct drm_modeset_acquire_ctx *ctx,
 782                  bool force)
 783 {
 784         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 785         struct intel_crt *crt = intel_attached_crt(connector);
 786         struct intel_encoder *intel_encoder = &crt->base;
 787         intel_wakeref_t wakeref;
 788         int status, ret;
 789         struct intel_load_detect_pipe tmp;
 790
 791         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 792                       connector->base.id, connector->name,
 793                       force);
 794
 795         if (i915_modparams.load_detect_test) {
 796                 wakeref = intel_display_power_get(dev_priv,
 797                                                   intel_encoder->power_domain);
 798                 goto load_detect;
 799         }
 800
 801         /* Skip machines without VGA that falsely report hotplug events */
 802         if (dmi_check_system(intel_spurious_crt_detect))
 803                 return connector_status_disconnected;
 804
 805         wakeref = intel_display_power_get(dev_priv,
 806                                           intel_encoder->power_domain);
 807
 808         if (I915_HAS_HOTPLUG(dev_priv)) {
 809                 /* We can not rely on the HPD pin always being correctly wired
 810                  * up, for example many KVM do not pass it through, and so
 811                  * only trust an assertion that the monitor is connected.
 812                  */
 813                 if (intel_crt_detect_hotplug(connector)) {
 814                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 815                         status = connector_status_connected;
 816                         goto out;
 817                 } else
 818                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 819         }
 820
 821         if (intel_crt_detect_ddc(connector)) {
 822                 status = connector_status_connected;
 823                 goto out;
 824         }
 825
 826         /* Load detection is broken on HPD capable machines. Whoever wants a
 827          * broken monitor (without edid) to work behind a broken kvm (that fails
 828          * to have the right resistors for HP detection) needs to fix this up.
 829          * For now just bail out. */
 830         if (I915_HAS_HOTPLUG(dev_priv)) {
 831                 status = connector_status_disconnected;
 832                 goto out;
 833         }
 834
 835 load_detect:
 836         if (!force) {
 837                 status = connector->status;
 838                 goto out;
 839         }
 840
 841         /* for pre-945g platforms use load detect */
 842         ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
 843         if (ret > 0) {
 844                 if (intel_crt_detect_ddc(connector))
 845                         status = connector_status_connected;
 846                 else if (INTEL_GEN(dev_priv) < 4)
 847                         status = intel_crt_load_detect(crt,
 848                                 to_intel_crtc(connector->state->crtc)->pipe);
 849                 else if (i915_modparams.load_detect_test)
 850                         status = connector_status_disconnected;
 851                 else
 852                         status = connector_status_unknown;
 853                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 854         } else if (ret == 0) {
 855                 status = connector_status_unknown;
 856         } else {
 857                 status = ret;
 858         }
 859
 860 out:
 861         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 862         return status;
 863 }
 864
 865 static int intel_crt_get_modes(struct drm_connector *connector)
 866 {
 867         struct drm_device *dev = connector->dev;
 868         struct drm_i915_private *dev_priv = to_i915(dev);
 869         struct intel_crt *crt = intel_attached_crt(connector);
 870         struct intel_encoder *intel_encoder = &crt->base;
 871         intel_wakeref_t wakeref;
 872         struct i2c_adapter *i2c;
 873         int ret;
 874
 875         wakeref = intel_display_power_get(dev_priv,
 876                                           intel_encoder->power_domain);
 877
 878         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 879         ret = intel_crt_ddc_get_modes(connector, i2c);
 880         if (ret || !IS_G4X(dev_priv))
 881                 goto out;
 882
 883         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 884         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 885         ret = intel_crt_ddc_get_modes(connector, i2c);
 886
 887 out:
 888         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 889
 890         return ret;
 891 }
 892
 893 void intel_crt_reset(struct drm_encoder *encoder)
 894 {
 895         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 896         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 897
 898         if (INTEL_GEN(dev_priv) >= 5) {
 899                 u32 adpa;
 900
 901                 adpa = I915_READ(crt->adpa_reg);
 902                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 903                 adpa |= ADPA_HOTPLUG_BITS;
 904                 I915_WRITE(crt->adpa_reg, adpa);
 905                 POSTING_READ(crt->adpa_reg);
 906
 907                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 908                 crt->force_hotplug_required = 1;
 909         }
 910
 911 }
 912
 913 /*
 914  * Routines for controlling stuff on the analog port
 915  */
 916
 917 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 918         .fill_modes = drm_helper_probe_single_connector_modes,
 919         .late_register = intel_connector_register,
 920         .early_unregister = intel_connector_unregister,
 921         .destroy = intel_connector_destroy,
 922         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 923         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 924 };
 925
 926 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 927         .detect_ctx = intel_crt_detect,
 928         .mode_valid = intel_crt_mode_valid,
 929         .get_modes = intel_crt_get_modes,
 930 };
 931
 932 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 933         .reset = intel_crt_reset,
 934         .destroy = intel_encoder_destroy,
 935 };
 936
 937 void intel_crt_init(struct drm_i915_private *dev_priv)
 938 {
 939         struct drm_connector *connector;
 940         struct intel_crt *crt;
 941         struct intel_connector *intel_connector;
 942         i915_reg_t adpa_reg;
 943         u32 adpa;
 944
 945         if (HAS_PCH_SPLIT(dev_priv))
 946                 adpa_reg = PCH_ADPA;
 947         else if (IS_VALLEYVIEW(dev_priv))
 948                 adpa_reg = VLV_ADPA;
 949         else
 950                 adpa_reg = ADPA;
 951
 952         adpa = I915_READ(adpa_reg);
 953         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 954                 /*
 955                  * On some machines (some IVB at least) CRT can be
 956                  * fused off, but there's no known fuse bit to
 957                  * indicate that. On these machine the ADPA register
 958                  * works normally, except the DAC enable bit won't
 959                  * take. So the only way to tell is attempt to enable
 960                  * it and see what happens.
 961                  */
 962                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 963                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 964                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 965                         return;
 966                 I915_WRITE(adpa_reg, adpa);
 967         }
 968
 969         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 970         if (!crt)
 971                 return;
 972
 973         intel_connector = intel_connector_alloc();
 974         if (!intel_connector) {
 975                 kfree(crt);
 976                 return;
 977         }
 978
 979         connector = &intel_connector->base;
 980         crt->connector = intel_connector;
 981         drm_connector_init(&dev_priv->drm, &intel_connector->base,
 982                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 983
 984         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
 985                          DRM_MODE_ENCODER_DAC, "CRT");
 986
 987         intel_connector_attach_encoder(intel_connector, &crt->base);
 988
 989         crt->base.type = INTEL_OUTPUT_ANALOG;
 990         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 991         if (IS_I830(dev_priv))
 992                 crt->base.crtc_mask = (1 << 0);
 993         else
 994                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 995
 996         if (IS_GEN(dev_priv, 2))
 997                 connector->interlace_allowed = 0;
 998         else
 999                 connector->interlace_allowed = 1;
1000         connector->doublescan_allowed = 0;
1001
1002         crt->adpa_reg = adpa_reg;
1003
1004         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1005
1006         if (I915_HAS_HOTPLUG(dev_priv) &&
1007             !dmi_check_system(intel_spurious_crt_detect)) {
1008                 crt->base.hpd_pin = HPD_CRT;
1009                 crt->base.hotplug = intel_encoder_hotplug;
1010         }
1011
1012         if (HAS_DDI(dev_priv)) {
1013                 crt->base.port = PORT_E;
1014                 crt->base.get_config = hsw_crt_get_config;
1015                 crt->base.get_hw_state = intel_ddi_get_hw_state;
1016                 crt->base.compute_config = hsw_crt_compute_config;
1017                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1018                 crt->base.pre_enable = hsw_pre_enable_crt;
1019                 crt->base.enable = hsw_enable_crt;
1020                 crt->base.disable = hsw_disable_crt;
1021                 crt->base.post_disable = hsw_post_disable_crt;
1022         } else {
1023                 if (HAS_PCH_SPLIT(dev_priv)) {
1024                         crt->base.compute_config = pch_crt_compute_config;
1025                         crt->base.disable = pch_disable_crt;
1026                         crt->base.post_disable = pch_post_disable_crt;
1027                 } else {
1028                         crt->base.compute_config = intel_crt_compute_config;
1029                         crt->base.disable = intel_disable_crt;
1030                 }
1031                 crt->base.port = PORT_NONE;
1032                 crt->base.get_config = intel_crt_get_config;
1033                 crt->base.get_hw_state = intel_crt_get_hw_state;
1034                 crt->base.enable = intel_enable_crt;
1035         }
1036         intel_connector->get_hw_state = intel_connector_get_hw_state;
1037
1038         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1039
1040         if (!I915_HAS_HOTPLUG(dev_priv))
1041                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1042
1043         /*
1044          * Configure the automatic hotplug detection stuff
1045          */
1046         crt->force_hotplug_required = 0;
1047
1048         /*
1049          * TODO: find a proper way to discover whether we need to set the the
1050          * polarity and link reversal bits or not, instead of relying on the
1051          * BIOS.
1052          */
1053         if (HAS_PCH_LPT(dev_priv)) {
1054                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1055                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1056
1057                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1058         }
1059
1060         intel_crt_reset(&crt->base.base);
1061 }