drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31
  32 struct ddi_buf_trans {
  33         u32 trans1;     /* balance leg enable, de-emph level */
  34         u32 trans2;     /* vref sel, vswing */
  35         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  36 };
  37
  38 static const u8 index_to_dp_signal_levels[] = {
  39         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  40         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  41         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  42         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  43         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  44         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  45         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  46         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  47         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  48         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  49 };
  50
  51 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  52  * them for both DP and FDI transports, allowing those ports to
  53  * automatically adapt to HDMI connections as well
  54  */
  55 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  56         { 0x00FFFFFF, 0x0006000E, 0x0 },
  57         { 0x00D75FFF, 0x0005000A, 0x0 },
  58         { 0x00C30FFF, 0x00040006, 0x0 },
  59         { 0x80AAAFFF, 0x000B0000, 0x0 },
  60         { 0x00FFFFFF, 0x0005000A, 0x0 },
  61         { 0x00D75FFF, 0x000C0004, 0x0 },
  62         { 0x80C30FFF, 0x000B0000, 0x0 },
  63         { 0x00FFFFFF, 0x00040006, 0x0 },
  64         { 0x80D75FFF, 0x000B0000, 0x0 },
  65 };
  66
  67 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  68         { 0x00FFFFFF, 0x0007000E, 0x0 },
  69         { 0x00D75FFF, 0x000F000A, 0x0 },
  70         { 0x00C30FFF, 0x00060006, 0x0 },
  71         { 0x00AAAFFF, 0x001E0000, 0x0 },
  72         { 0x00FFFFFF, 0x000F000A, 0x0 },
  73         { 0x00D75FFF, 0x00160004, 0x0 },
  74         { 0x00C30FFF, 0x001E0000, 0x0 },
  75         { 0x00FFFFFF, 0x00060006, 0x0 },
  76         { 0x00D75FFF, 0x001E0000, 0x0 },
  77 };
  78
  79 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  80                                         /* Idx  NT mV d T mV d  db      */
  81         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  82         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  83         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  84         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  85         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  86         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  87         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  88         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  89         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  90         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  91         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  92         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  93 };
  94
  95 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  96         { 0x00FFFFFF, 0x00000012, 0x0 },
  97         { 0x00EBAFFF, 0x00020011, 0x0 },
  98         { 0x00C71FFF, 0x0006000F, 0x0 },
  99         { 0x00AAAFFF, 0x000E000A, 0x0 },
 100         { 0x00FFFFFF, 0x00020011, 0x0 },
 101         { 0x00DB6FFF, 0x0005000F, 0x0 },
 102         { 0x00BEEFFF, 0x000A000C, 0x0 },
 103         { 0x00FFFFFF, 0x0005000F, 0x0 },
 104         { 0x00DB6FFF, 0x000A000C, 0x0 },
 105 };
 106
 107 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 108         { 0x00FFFFFF, 0x0007000E, 0x0 },
 109         { 0x00D75FFF, 0x000E000A, 0x0 },
 110         { 0x00BEFFFF, 0x00140006, 0x0 },
 111         { 0x80B2CFFF, 0x001B0002, 0x0 },
 112         { 0x00FFFFFF, 0x000E000A, 0x0 },
 113         { 0x00DB6FFF, 0x00160005, 0x0 },
 114         { 0x80C71FFF, 0x001A0002, 0x0 },
 115         { 0x00F7DFFF, 0x00180004, 0x0 },
 116         { 0x80D75FFF, 0x001B0002, 0x0 },
 117 };
 118
 119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 120         { 0x00FFFFFF, 0x0001000E, 0x0 },
 121         { 0x00D75FFF, 0x0004000A, 0x0 },
 122         { 0x00C30FFF, 0x00070006, 0x0 },
 123         { 0x00AAAFFF, 0x000C0000, 0x0 },
 124         { 0x00FFFFFF, 0x0004000A, 0x0 },
 125         { 0x00D75FFF, 0x00090004, 0x0 },
 126         { 0x00C30FFF, 0x000C0000, 0x0 },
 127         { 0x00FFFFFF, 0x00070006, 0x0 },
 128         { 0x00D75FFF, 0x000C0000, 0x0 },
 129 };
 130
 131 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 132                                         /* Idx  NT mV d T mV df db      */
 133         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 134         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 135         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 136         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 137         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 138         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 139         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 140         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 141         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 142         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 143 };
 144
 145 /* Skylake H and S */
 146 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 147         { 0x00002016, 0x000000A0, 0x0 },
 148         { 0x00005012, 0x0000009B, 0x0 },
 149         { 0x00007011, 0x00000088, 0x0 },
 150         { 0x80009010, 0x000000C0, 0x1 },
 151         { 0x00002016, 0x0000009B, 0x0 },
 152         { 0x00005012, 0x00000088, 0x0 },
 153         { 0x80007011, 0x000000C0, 0x1 },
 154         { 0x00002016, 0x000000DF, 0x0 },
 155         { 0x80005012, 0x000000C0, 0x1 },
 156 };
 157
 158 /* Skylake U */
 159 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 160         { 0x0000201B, 0x000000A2, 0x0 },
 161         { 0x00005012, 0x00000088, 0x0 },
 162         { 0x80007011, 0x000000CD, 0x1 },
 163         { 0x80009010, 0x000000C0, 0x1 },
 164         { 0x0000201B, 0x0000009D, 0x0 },
 165         { 0x80005012, 0x000000C0, 0x1 },
 166         { 0x80007011, 0x000000C0, 0x1 },
 167         { 0x00002016, 0x00000088, 0x0 },
 168         { 0x80005012, 0x000000C0, 0x1 },
 169 };
 170
 171 /* Skylake Y */
 172 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 173         { 0x00000018, 0x000000A2, 0x0 },
 174         { 0x00005012, 0x00000088, 0x0 },
 175         { 0x80007011, 0x000000CD, 0x3 },
 176         { 0x80009010, 0x000000C0, 0x3 },
 177         { 0x00000018, 0x0000009D, 0x0 },
 178         { 0x80005012, 0x000000C0, 0x3 },
 179         { 0x80007011, 0x000000C0, 0x3 },
 180         { 0x00000018, 0x00000088, 0x0 },
 181         { 0x80005012, 0x000000C0, 0x3 },
 182 };
 183
 184 /* Kabylake H and S */
 185 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 186         { 0x00002016, 0x000000A0, 0x0 },
 187         { 0x00005012, 0x0000009B, 0x0 },
 188         { 0x00007011, 0x00000088, 0x0 },
 189         { 0x80009010, 0x000000C0, 0x1 },
 190         { 0x00002016, 0x0000009B, 0x0 },
 191         { 0x00005012, 0x00000088, 0x0 },
 192         { 0x80007011, 0x000000C0, 0x1 },
 193         { 0x00002016, 0x00000097, 0x0 },
 194         { 0x80005012, 0x000000C0, 0x1 },
 195 };
 196
 197 /* Kabylake U */
 198 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 199         { 0x0000201B, 0x000000A1, 0x0 },
 200         { 0x00005012, 0x00000088, 0x0 },
 201         { 0x80007011, 0x000000CD, 0x3 },
 202         { 0x80009010, 0x000000C0, 0x3 },
 203         { 0x0000201B, 0x0000009D, 0x0 },
 204         { 0x80005012, 0x000000C0, 0x3 },
 205         { 0x80007011, 0x000000C0, 0x3 },
 206         { 0x00002016, 0x0000004F, 0x0 },
 207         { 0x80005012, 0x000000C0, 0x3 },
 208 };
 209
 210 /* Kabylake Y */
 211 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 212         { 0x00001017, 0x000000A1, 0x0 },
 213         { 0x00005012, 0x00000088, 0x0 },
 214         { 0x80007011, 0x000000CD, 0x3 },
 215         { 0x8000800F, 0x000000C0, 0x3 },
 216         { 0x00001017, 0x0000009D, 0x0 },
 217         { 0x80005012, 0x000000C0, 0x3 },
 218         { 0x80007011, 0x000000C0, 0x3 },
 219         { 0x00001017, 0x0000004C, 0x0 },
 220         { 0x80005012, 0x000000C0, 0x3 },
 221 };
 222
 223 /*
 224  * Skylake/Kabylake H and S
 225  * eDP 1.4 low vswing translation parameters
 226  */
 227 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 228         { 0x00000018, 0x000000A8, 0x0 },
 229         { 0x00004013, 0x000000A9, 0x0 },
 230         { 0x00007011, 0x000000A2, 0x0 },
 231         { 0x00009010, 0x0000009C, 0x0 },
 232         { 0x00000018, 0x000000A9, 0x0 },
 233         { 0x00006013, 0x000000A2, 0x0 },
 234         { 0x00007011, 0x000000A6, 0x0 },
 235         { 0x00000018, 0x000000AB, 0x0 },
 236         { 0x00007013, 0x0000009F, 0x0 },
 237         { 0x00000018, 0x000000DF, 0x0 },
 238 };
 239
 240 /*
 241  * Skylake/Kabylake U
 242  * eDP 1.4 low vswing translation parameters
 243  */
 244 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 245         { 0x00000018, 0x000000A8, 0x0 },
 246         { 0x00004013, 0x000000A9, 0x0 },
 247         { 0x00007011, 0x000000A2, 0x0 },
 248         { 0x00009010, 0x0000009C, 0x0 },
 249         { 0x00000018, 0x000000A9, 0x0 },
 250         { 0x00006013, 0x000000A2, 0x0 },
 251         { 0x00007011, 0x000000A6, 0x0 },
 252         { 0x00002016, 0x000000AB, 0x0 },
 253         { 0x00005013, 0x0000009F, 0x0 },
 254         { 0x00000018, 0x000000DF, 0x0 },
 255 };
 256
 257 /*
 258  * Skylake/Kabylake Y
 259  * eDP 1.4 low vswing translation parameters
 260  */
 261 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 262         { 0x00000018, 0x000000A8, 0x0 },
 263         { 0x00004013, 0x000000AB, 0x0 },
 264         { 0x00007011, 0x000000A4, 0x0 },
 265         { 0x00009010, 0x000000DF, 0x0 },
 266         { 0x00000018, 0x000000AA, 0x0 },
 267         { 0x00006013, 0x000000A4, 0x0 },
 268         { 0x00007011, 0x0000009D, 0x0 },
 269         { 0x00000018, 0x000000A0, 0x0 },
 270         { 0x00006012, 0x000000DF, 0x0 },
 271         { 0x00000018, 0x0000008A, 0x0 },
 272 };
 273
 274 /* Skylake/Kabylake U, H and S */
 275 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 276         { 0x00000018, 0x000000AC, 0x0 },
 277         { 0x00005012, 0x0000009D, 0x0 },
 278         { 0x00007011, 0x00000088, 0x0 },
 279         { 0x00000018, 0x000000A1, 0x0 },
 280         { 0x00000018, 0x00000098, 0x0 },
 281         { 0x00004013, 0x00000088, 0x0 },
 282         { 0x80006012, 0x000000CD, 0x1 },
 283         { 0x00000018, 0x000000DF, 0x0 },
 284         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 285         { 0x80003015, 0x000000C0, 0x1 },
 286         { 0x80000018, 0x000000C0, 0x1 },
 287 };
 288
 289 /* Skylake/Kabylake Y */
 290 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 291         { 0x00000018, 0x000000A1, 0x0 },
 292         { 0x00005012, 0x000000DF, 0x0 },
 293         { 0x80007011, 0x000000CB, 0x3 },
 294         { 0x00000018, 0x000000A4, 0x0 },
 295         { 0x00000018, 0x0000009D, 0x0 },
 296         { 0x00004013, 0x00000080, 0x0 },
 297         { 0x80006013, 0x000000C0, 0x3 },
 298         { 0x00000018, 0x0000008A, 0x0 },
 299         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 300         { 0x80003015, 0x000000C0, 0x3 },
 301         { 0x80000018, 0x000000C0, 0x3 },
 302 };
 303
 304 struct bxt_ddi_buf_trans {
 305         u8 margin;      /* swing value */
 306         u8 scale;       /* scale value */
 307         u8 enable;      /* scale enable */
 308         u8 deemphasis;
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, },     /* 0:   200             0   */
 328         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 330         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 331         { 32, 0, 0, 128, },     /* 4:   250             0   */
 332         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 334         { 43, 0, 0, 128, },     /* 7:   300             0   */
 335         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, },     /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u8 dw2_swing_sel;
 358         u8 dw7_n_scalar;
 359         u8 dw4_cursor_coeff;
 360         u8 dw4_post_cursor_2;
 361         u8 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 struct icl_combo_phy_ddi_buf_trans {
 497         u32 dw2_swing_select;
 498         u32 dw2_swing_scalar;
 499         u32 dw4_scaling;
 500 };
 501
 502 /* Voltage Swing Programming for VccIO 0.85V for DP */
 503 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
 504                                 /* Voltage mV  db    */
 505         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 506         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 507         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 508         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 509         { 0xB, 0x70, 0x0018 },  /* 600         0.0   */
 510         { 0xB, 0x70, 0x3015 },  /* 600         3.5   */
 511         { 0xB, 0x70, 0x6012 },  /* 600         6.0   */
 512         { 0x5, 0x00, 0x0018 },  /* 800         0.0   */
 513         { 0x5, 0x00, 0x3015 },  /* 800         3.5   */
 514         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 515 };
 516
 517 /* FIXME - After table is updated in Bspec */
 518 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 519 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
 520                                 /* Voltage mV  db    */
 521         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 522         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 523         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 524         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 525         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 526         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 527         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 528         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 529         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 530         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 531 };
 532
 533 /* Voltage Swing Programming for VccIO 0.95V for DP */
 534 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
 535                                 /* Voltage mV  db    */
 536         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 537         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 538         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 539         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 540         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 541         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 542         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 543         { 0x5, 0x76, 0x0018 },  /* 800         0.0   */
 544         { 0x5, 0x76, 0x3015 },  /* 800         3.5   */
 545         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 546 };
 547
 548 /* FIXME - After table is updated in Bspec */
 549 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 550 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
 551                                 /* Voltage mV  db    */
 552         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 553         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 554         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 555         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 556         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 557         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 558         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 559         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 560         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 561         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 562 };
 563
 564 /* Voltage Swing Programming for VccIO 1.05V for DP */
 565 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
 566                                 /* Voltage mV  db    */
 567         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 568         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 569         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 570         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 571         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 572         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 573         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 574         { 0x5, 0x71, 0x0018 },  /* 800         0.0   */
 575         { 0x5, 0x71, 0x3015 },  /* 800         3.5   */
 576         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 577 };
 578
 579 /* FIXME - After table is updated in Bspec */
 580 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 581 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
 582                                 /* Voltage mV  db    */
 583         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 584         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 585         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 586         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 587         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 588         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 589         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 590         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 591         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 592         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 593 };
 594
 595 struct icl_mg_phy_ddi_buf_trans {
 596         u32 cri_txdeemph_override_5_0;
 597         u32 cri_txdeemph_override_11_6;
 598         u32 cri_txdeemph_override_17_12;
 599 };
 600
 601 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 602                                 /* Voltage swing  pre-emphasis */
 603         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 604         { 0x0, 0x23, 0x08 },    /* 0              1   */
 605         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 606         { 0x0, 0x00, 0x00 },    /* 0              3   */
 607         { 0x0, 0x23, 0x00 },    /* 1              0   */
 608         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 609         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 610         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 611         { 0x0, 0x33, 0x0C },    /* 2              1   */
 612         { 0x0, 0x00, 0x00 },    /* 3              0   */
 613 };
 614
 615 static const struct ddi_buf_trans *
 616 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 617 {
 618         if (dev_priv->vbt.edp.low_vswing) {
 619                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 620                 return bdw_ddi_translations_edp;
 621         } else {
 622                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 623                 return bdw_ddi_translations_dp;
 624         }
 625 }
 626
 627 static const struct ddi_buf_trans *
 628 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 629 {
 630         if (IS_SKL_ULX(dev_priv)) {
 631                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 632                 return skl_y_ddi_translations_dp;
 633         } else if (IS_SKL_ULT(dev_priv)) {
 634                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 635                 return skl_u_ddi_translations_dp;
 636         } else {
 637                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 638                 return skl_ddi_translations_dp;
 639         }
 640 }
 641
 642 static const struct ddi_buf_trans *
 643 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 644 {
 645         if (IS_KBL_ULX(dev_priv)) {
 646                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 647                 return kbl_y_ddi_translations_dp;
 648         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 649                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 650                 return kbl_u_ddi_translations_dp;
 651         } else {
 652                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 653                 return kbl_ddi_translations_dp;
 654         }
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 659 {
 660         if (dev_priv->vbt.edp.low_vswing) {
 661                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 662                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 663                         return skl_y_ddi_translations_edp;
 664                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 665                            IS_CFL_ULT(dev_priv)) {
 666                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 667                         return skl_u_ddi_translations_edp;
 668                 } else {
 669                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 670                         return skl_ddi_translations_edp;
 671                 }
 672         }
 673
 674         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 675                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 676         else
 677                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 678 }
 679
 680 static const struct ddi_buf_trans *
 681 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 682 {
 683         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 684                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 685                 return skl_y_ddi_translations_hdmi;
 686         } else {
 687                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 688                 return skl_ddi_translations_hdmi;
 689         }
 690 }
 691
 692 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 693 {
 694         /* Only DDIA and DDIE can select the 10th register with DP */
 695         if (port == PORT_A || port == PORT_E)
 696                 return min(n_entries, 10);
 697         else
 698                 return min(n_entries, 9);
 699 }
 700
 701 static const struct ddi_buf_trans *
 702 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 703                            enum port port, int *n_entries)
 704 {
 705         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 706                 const struct ddi_buf_trans *ddi_translations =
 707                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 708                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 709                 return ddi_translations;
 710         } else if (IS_SKYLAKE(dev_priv)) {
 711                 const struct ddi_buf_trans *ddi_translations =
 712                         skl_get_buf_trans_dp(dev_priv, n_entries);
 713                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 714                 return ddi_translations;
 715         } else if (IS_BROADWELL(dev_priv)) {
 716                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 717                 return  bdw_ddi_translations_dp;
 718         } else if (IS_HASWELL(dev_priv)) {
 719                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 720                 return hsw_ddi_translations_dp;
 721         }
 722
 723         *n_entries = 0;
 724         return NULL;
 725 }
 726
 727 static const struct ddi_buf_trans *
 728 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 729                             enum port port, int *n_entries)
 730 {
 731         if (IS_GEN9_BC(dev_priv)) {
 732                 const struct ddi_buf_trans *ddi_translations =
 733                         skl_get_buf_trans_edp(dev_priv, n_entries);
 734                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 735                 return ddi_translations;
 736         } else if (IS_BROADWELL(dev_priv)) {
 737                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 738         } else if (IS_HASWELL(dev_priv)) {
 739                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 740                 return hsw_ddi_translations_dp;
 741         }
 742
 743         *n_entries = 0;
 744         return NULL;
 745 }
 746
 747 static const struct ddi_buf_trans *
 748 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 749                             int *n_entries)
 750 {
 751         if (IS_BROADWELL(dev_priv)) {
 752                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 753                 return bdw_ddi_translations_fdi;
 754         } else if (IS_HASWELL(dev_priv)) {
 755                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 756                 return hsw_ddi_translations_fdi;
 757         }
 758
 759         *n_entries = 0;
 760         return NULL;
 761 }
 762
 763 static const struct ddi_buf_trans *
 764 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 765                              int *n_entries)
 766 {
 767         if (IS_GEN9_BC(dev_priv)) {
 768                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 769         } else if (IS_BROADWELL(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 771                 return bdw_ddi_translations_hdmi;
 772         } else if (IS_HASWELL(dev_priv)) {
 773                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 774                 return hsw_ddi_translations_hdmi;
 775         }
 776
 777         *n_entries = 0;
 778         return NULL;
 779 }
 780
 781 static const struct bxt_ddi_buf_trans *
 782 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 783 {
 784         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 785         return bxt_ddi_translations_dp;
 786 }
 787
 788 static const struct bxt_ddi_buf_trans *
 789 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 790 {
 791         if (dev_priv->vbt.edp.low_vswing) {
 792                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 793                 return bxt_ddi_translations_edp;
 794         }
 795
 796         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 797 }
 798
 799 static const struct bxt_ddi_buf_trans *
 800 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 801 {
 802         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 803         return bxt_ddi_translations_hdmi;
 804 }
 805
 806 static const struct cnl_ddi_buf_trans *
 807 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 808 {
 809         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 810
 811         if (voltage == VOLTAGE_INFO_0_85V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 813                 return cnl_ddi_translations_hdmi_0_85V;
 814         } else if (voltage == VOLTAGE_INFO_0_95V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 816                 return cnl_ddi_translations_hdmi_0_95V;
 817         } else if (voltage == VOLTAGE_INFO_1_05V) {
 818                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 819                 return cnl_ddi_translations_hdmi_1_05V;
 820         } else {
 821                 *n_entries = 1; /* shut up gcc */
 822                 MISSING_CASE(voltage);
 823         }
 824         return NULL;
 825 }
 826
 827 static const struct cnl_ddi_buf_trans *
 828 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 829 {
 830         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 831
 832         if (voltage == VOLTAGE_INFO_0_85V) {
 833                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 834                 return cnl_ddi_translations_dp_0_85V;
 835         } else if (voltage == VOLTAGE_INFO_0_95V) {
 836                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 837                 return cnl_ddi_translations_dp_0_95V;
 838         } else if (voltage == VOLTAGE_INFO_1_05V) {
 839                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 840                 return cnl_ddi_translations_dp_1_05V;
 841         } else {
 842                 *n_entries = 1; /* shut up gcc */
 843                 MISSING_CASE(voltage);
 844         }
 845         return NULL;
 846 }
 847
 848 static const struct cnl_ddi_buf_trans *
 849 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 850 {
 851         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 852
 853         if (dev_priv->vbt.edp.low_vswing) {
 854                 if (voltage == VOLTAGE_INFO_0_85V) {
 855                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 856                         return cnl_ddi_translations_edp_0_85V;
 857                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 858                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 859                         return cnl_ddi_translations_edp_0_95V;
 860                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 861                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 862                         return cnl_ddi_translations_edp_1_05V;
 863                 } else {
 864                         *n_entries = 1; /* shut up gcc */
 865                         MISSING_CASE(voltage);
 866                 }
 867                 return NULL;
 868         } else {
 869                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 870         }
 871 }
 872
 873 static const struct icl_combo_phy_ddi_buf_trans *
 874 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 875                         int type, int *n_entries)
 876 {
 877         u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
 878
 879         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 880                 switch (voltage) {
 881                 case VOLTAGE_INFO_0_85V:
 882                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
 883                         return icl_combo_phy_ddi_translations_edp_0_85V;
 884                 case VOLTAGE_INFO_0_95V:
 885                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
 886                         return icl_combo_phy_ddi_translations_edp_0_95V;
 887                 case VOLTAGE_INFO_1_05V:
 888                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
 889                         return icl_combo_phy_ddi_translations_edp_1_05V;
 890                 default:
 891                         MISSING_CASE(voltage);
 892                         return NULL;
 893                 }
 894         } else {
 895                 switch (voltage) {
 896                 case VOLTAGE_INFO_0_85V:
 897                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
 898                         return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
 899                 case VOLTAGE_INFO_0_95V:
 900                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
 901                         return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
 902                 case VOLTAGE_INFO_1_05V:
 903                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
 904                         return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
 905                 default:
 906                         MISSING_CASE(voltage);
 907                         return NULL;
 908                 }
 909         }
 910 }
 911
 912 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 913 {
 914         int n_entries, level, default_entry;
 915
 916         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 917
 918         if (IS_ICELAKE(dev_priv)) {
 919                 if (port == PORT_A || port == PORT_B)
 920                         icl_get_combo_buf_trans(dev_priv, port,
 921                                                 INTEL_OUTPUT_HDMI, &n_entries);
 922                 else
 923                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 924                 default_entry = n_entries - 1;
 925         } else if (IS_CANNONLAKE(dev_priv)) {
 926                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 927                 default_entry = n_entries - 1;
 928         } else if (IS_GEN9_LP(dev_priv)) {
 929                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 930                 default_entry = n_entries - 1;
 931         } else if (IS_GEN9_BC(dev_priv)) {
 932                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 933                 default_entry = 8;
 934         } else if (IS_BROADWELL(dev_priv)) {
 935                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 936                 default_entry = 7;
 937         } else if (IS_HASWELL(dev_priv)) {
 938                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 939                 default_entry = 6;
 940         } else {
 941                 WARN(1, "ddi translation table missing\n");
 942                 return 0;
 943         }
 944
 945         /* Choose a good default if VBT is badly populated */
 946         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 947                 level = default_entry;
 948
 949         if (WARN_ON_ONCE(n_entries == 0))
 950                 return 0;
 951         if (WARN_ON_ONCE(level >= n_entries))
 952                 level = n_entries - 1;
 953
 954         return level;
 955 }
 956
 957 /*
 958  * Starting with Haswell, DDI port buffers must be programmed with correct
 959  * values in advance. This function programs the correct values for
 960  * DP/eDP/FDI use cases.
 961  */
 962 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 963                                          const struct intel_crtc_state *crtc_state)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 966         u32 iboost_bit = 0;
 967         int i, n_entries;
 968         enum port port = encoder->port;
 969         const struct ddi_buf_trans *ddi_translations;
 970
 971         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 972                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 973                                                                &n_entries);
 974         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 975                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 976                                                                &n_entries);
 977         else
 978                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 979                                                               &n_entries);
 980
 981         /* If we're boosting the current, set bit 31 of trans1 */
 982         if (IS_GEN9_BC(dev_priv) &&
 983             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 984                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 985
 986         for (i = 0; i < n_entries; i++) {
 987                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 988                            ddi_translations[i].trans1 | iboost_bit);
 989                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 990                            ddi_translations[i].trans2);
 991         }
 992 }
 993
 994 /*
 995  * Starting with Haswell, DDI port buffers must be programmed with correct
 996  * values in advance. This function programs the correct values for
 997  * HDMI/DVI use cases.
 998  */
 999 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1000                                            int level)
1001 {
1002         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003         u32 iboost_bit = 0;
1004         int n_entries;
1005         enum port port = encoder->port;
1006         const struct ddi_buf_trans *ddi_translations;
1007
1008         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1009
1010         if (WARN_ON_ONCE(!ddi_translations))
1011                 return;
1012         if (WARN_ON_ONCE(level >= n_entries))
1013                 level = n_entries - 1;
1014
1015         /* If we're boosting the current, set bit 31 of trans1 */
1016         if (IS_GEN9_BC(dev_priv) &&
1017             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1019
1020         /* Entry 9 is for HDMI: */
1021         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1022                    ddi_translations[level].trans1 | iboost_bit);
1023         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1024                    ddi_translations[level].trans2);
1025 }
1026
1027 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028                                     enum port port)
1029 {
1030         i915_reg_t reg = DDI_BUF_CTL(port);
1031         int i;
1032
1033         for (i = 0; i < 16; i++) {
1034                 udelay(1);
1035                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036                         return;
1037         }
1038         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039 }
1040
1041 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1042 {
1043         switch (pll->info->id) {
1044         case DPLL_ID_WRPLL1:
1045                 return PORT_CLK_SEL_WRPLL1;
1046         case DPLL_ID_WRPLL2:
1047                 return PORT_CLK_SEL_WRPLL2;
1048         case DPLL_ID_SPLL:
1049                 return PORT_CLK_SEL_SPLL;
1050         case DPLL_ID_LCPLL_810:
1051                 return PORT_CLK_SEL_LCPLL_810;
1052         case DPLL_ID_LCPLL_1350:
1053                 return PORT_CLK_SEL_LCPLL_1350;
1054         case DPLL_ID_LCPLL_2700:
1055                 return PORT_CLK_SEL_LCPLL_2700;
1056         default:
1057                 MISSING_CASE(pll->info->id);
1058                 return PORT_CLK_SEL_NONE;
1059         }
1060 }
1061
1062 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1063                                        const struct intel_shared_dpll *pll)
1064 {
1065         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1066         int clock = crtc->config->port_clock;
1067         const enum intel_dpll_id id = pll->info->id;
1068
1069         switch (id) {
1070         default:
1071                 MISSING_CASE(id);
1072                 /* fall through */
1073         case DPLL_ID_ICL_DPLL0:
1074         case DPLL_ID_ICL_DPLL1:
1075                 return DDI_CLK_SEL_NONE;
1076         case DPLL_ID_ICL_TBTPLL:
1077                 switch (clock) {
1078                 case 162000:
1079                         return DDI_CLK_SEL_TBT_162;
1080                 case 270000:
1081                         return DDI_CLK_SEL_TBT_270;
1082                 case 540000:
1083                         return DDI_CLK_SEL_TBT_540;
1084                 case 810000:
1085                         return DDI_CLK_SEL_TBT_810;
1086                 default:
1087                         MISSING_CASE(clock);
1088                         break;
1089                 }
1090         case DPLL_ID_ICL_MGPLL1:
1091         case DPLL_ID_ICL_MGPLL2:
1092         case DPLL_ID_ICL_MGPLL3:
1093         case DPLL_ID_ICL_MGPLL4:
1094                 return DDI_CLK_SEL_MG;
1095         }
1096 }
1097
1098 /* Starting with Haswell, different DDI ports can work in FDI mode for
1099  * connection to the PCH-located connectors. For this, it is necessary to train
1100  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1101  *
1102  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1103  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1104  * DDI A (which is used for eDP)
1105  */
1106
1107 void hsw_fdi_link_train(struct intel_crtc *crtc,
1108                         const struct intel_crtc_state *crtc_state)
1109 {
1110         struct drm_device *dev = crtc->base.dev;
1111         struct drm_i915_private *dev_priv = to_i915(dev);
1112         struct intel_encoder *encoder;
1113         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1114
1115         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1116                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1117                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1118         }
1119
1120         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1121          * mode set "sequence for CRT port" document:
1122          * - TP1 to TP2 time with the default value
1123          * - FDI delay to 90h
1124          *
1125          * WaFDIAutoLinkSetTimingOverrride:hsw
1126          */
1127         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1128                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1129                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1130
1131         /* Enable the PCH Receiver FDI PLL */
1132         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1133                      FDI_RX_PLL_ENABLE |
1134                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1135         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1136         POSTING_READ(FDI_RX_CTL(PIPE_A));
1137         udelay(220);
1138
1139         /* Switch from Rawclk to PCDclk */
1140         rx_ctl_val |= FDI_PCDCLK;
1141         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1142
1143         /* Configure Port Clock Select */
1144         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1145         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1146         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1147
1148         /* Start the training iterating through available voltages and emphasis,
1149          * testing each value twice. */
1150         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1151                 /* Configure DP_TP_CTL with auto-training */
1152                 I915_WRITE(DP_TP_CTL(PORT_E),
1153                                         DP_TP_CTL_FDI_AUTOTRAIN |
1154                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1155                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1156                                         DP_TP_CTL_ENABLE);
1157
1158                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1159                  * DDI E does not support port reversal, the functionality is
1160                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1161                  * port reversal bit */
1162                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1163                            DDI_BUF_CTL_ENABLE |
1164                            ((crtc_state->fdi_lanes - 1) << 1) |
1165                            DDI_BUF_TRANS_SELECT(i / 2));
1166                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1167
1168                 udelay(600);
1169
1170                 /* Program PCH FDI Receiver TU */
1171                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1172
1173                 /* Enable PCH FDI Receiver with auto-training */
1174                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1175                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1176                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1177
1178                 /* Wait for FDI receiver lane calibration */
1179                 udelay(30);
1180
1181                 /* Unset FDI_RX_MISC pwrdn lanes */
1182                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1183                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1186
1187                 /* Wait for FDI auto training time */
1188                 udelay(5);
1189
1190                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1191                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1192                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1193                         break;
1194                 }
1195
1196                 /*
1197                  * Leave things enabled even if we failed to train FDI.
1198                  * Results in less fireworks from the state checker.
1199                  */
1200                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1201                         DRM_ERROR("FDI link training failed!\n");
1202                         break;
1203                 }
1204
1205                 rx_ctl_val &= ~FDI_RX_ENABLE;
1206                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1207                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1208
1209                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1210                 temp &= ~DDI_BUF_CTL_ENABLE;
1211                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1212                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1213
1214                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1215                 temp = I915_READ(DP_TP_CTL(PORT_E));
1216                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1217                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1218                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1219                 POSTING_READ(DP_TP_CTL(PORT_E));
1220
1221                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1222
1223                 /* Reset FDI_RX_MISC pwrdn lanes */
1224                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1225                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1226                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1227                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1228                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1229         }
1230
1231         /* Enable normal pixel sending for FDI */
1232         I915_WRITE(DP_TP_CTL(PORT_E),
1233                    DP_TP_CTL_FDI_AUTOTRAIN |
1234                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1235                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1236                    DP_TP_CTL_ENABLE);
1237 }
1238
1239 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1240 {
1241         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1242         struct intel_digital_port *intel_dig_port =
1243                 enc_to_dig_port(&encoder->base);
1244
1245         intel_dp->DP = intel_dig_port->saved_port_bits |
1246                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1247         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1248 }
1249
1250 static struct intel_encoder *
1251 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1252 {
1253         struct drm_device *dev = crtc->base.dev;
1254         struct intel_encoder *encoder, *ret = NULL;
1255         int num_encoders = 0;
1256
1257         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1258                 ret = encoder;
1259                 num_encoders++;
1260         }
1261
1262         if (num_encoders != 1)
1263                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1264                      pipe_name(crtc->pipe));
1265
1266         BUG_ON(ret == NULL);
1267         return ret;
1268 }
1269
1270 #define LC_FREQ 2700
1271
1272 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1273                                    i915_reg_t reg)
1274 {
1275         int refclk = LC_FREQ;
1276         int n, p, r;
1277         u32 wrpll;
1278
1279         wrpll = I915_READ(reg);
1280         switch (wrpll & WRPLL_PLL_REF_MASK) {
1281         case WRPLL_PLL_SSC:
1282         case WRPLL_PLL_NON_SSC:
1283                 /*
1284                  * We could calculate spread here, but our checking
1285                  * code only cares about 5% accuracy, and spread is a max of
1286                  * 0.5% downspread.
1287                  */
1288                 refclk = 135;
1289                 break;
1290         case WRPLL_PLL_LCPLL:
1291                 refclk = LC_FREQ;
1292                 break;
1293         default:
1294                 WARN(1, "bad wrpll refclk\n");
1295                 return 0;
1296         }
1297
1298         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1299         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1300         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1301
1302         /* Convert to KHz, p & r have a fixed point portion */
1303         return (refclk * n * 100) / (p * r);
1304 }
1305
1306 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1307                                enum intel_dpll_id pll_id)
1308 {
1309         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1310         uint32_t cfgcr1_val, cfgcr2_val;
1311         uint32_t p0, p1, p2, dco_freq;
1312
1313         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1314         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1315
1316         cfgcr1_val = I915_READ(cfgcr1_reg);
1317         cfgcr2_val = I915_READ(cfgcr2_reg);
1318
1319         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1320         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1321
1322         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1323                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1324         else
1325                 p1 = 1;
1326
1327
1328         switch (p0) {
1329         case DPLL_CFGCR2_PDIV_1:
1330                 p0 = 1;
1331                 break;
1332         case DPLL_CFGCR2_PDIV_2:
1333                 p0 = 2;
1334                 break;
1335         case DPLL_CFGCR2_PDIV_3:
1336                 p0 = 3;
1337                 break;
1338         case DPLL_CFGCR2_PDIV_7:
1339                 p0 = 7;
1340                 break;
1341         }
1342
1343         switch (p2) {
1344         case DPLL_CFGCR2_KDIV_5:
1345                 p2 = 5;
1346                 break;
1347         case DPLL_CFGCR2_KDIV_2:
1348                 p2 = 2;
1349                 break;
1350         case DPLL_CFGCR2_KDIV_3:
1351                 p2 = 3;
1352                 break;
1353         case DPLL_CFGCR2_KDIV_1:
1354                 p2 = 1;
1355                 break;
1356         }
1357
1358         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1359
1360         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1361                 1000) / 0x8000;
1362
1363         return dco_freq / (p0 * p1 * p2 * 5);
1364 }
1365
1366 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1367                                enum intel_dpll_id pll_id)
1368 {
1369         uint32_t cfgcr0, cfgcr1;
1370         uint32_t p0, p1, p2, dco_freq, ref_clock;
1371
1372         if (INTEL_GEN(dev_priv) >= 11) {
1373                 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1374                 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1375         } else {
1376                 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1377                 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1378         }
1379
1380         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1382
1383         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1386         else
1387                 p1 = 1;
1388
1389
1390         switch (p0) {
1391         case DPLL_CFGCR1_PDIV_2:
1392                 p0 = 2;
1393                 break;
1394         case DPLL_CFGCR1_PDIV_3:
1395                 p0 = 3;
1396                 break;
1397         case DPLL_CFGCR1_PDIV_5:
1398                 p0 = 5;
1399                 break;
1400         case DPLL_CFGCR1_PDIV_7:
1401                 p0 = 7;
1402                 break;
1403         }
1404
1405         switch (p2) {
1406         case DPLL_CFGCR1_KDIV_1:
1407                 p2 = 1;
1408                 break;
1409         case DPLL_CFGCR1_KDIV_2:
1410                 p2 = 2;
1411                 break;
1412         case DPLL_CFGCR1_KDIV_4:
1413                 p2 = 4;
1414                 break;
1415         }
1416
1417         ref_clock = dev_priv->cdclk.hw.ref;
1418
1419         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1420
1421         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1422                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1423
1424         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1425                 return 0;
1426
1427         return dco_freq / (p0 * p1 * p2 * 5);
1428 }
1429
1430 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1431 {
1432         int dotclock;
1433
1434         if (pipe_config->has_pch_encoder)
1435                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1436                                                     &pipe_config->fdi_m_n);
1437         else if (intel_crtc_has_dp_encoder(pipe_config))
1438                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1439                                                     &pipe_config->dp_m_n);
1440         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1441                 dotclock = pipe_config->port_clock * 2 / 3;
1442         else
1443                 dotclock = pipe_config->port_clock;
1444
1445         if (pipe_config->ycbcr420)
1446                 dotclock *= 2;
1447
1448         if (pipe_config->pixel_multiplier)
1449                 dotclock /= pipe_config->pixel_multiplier;
1450
1451         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1452 }
1453
1454 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1455                               struct intel_crtc_state *pipe_config)
1456 {
1457         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1458         enum port port = encoder->port;
1459         int link_clock = 0;
1460         uint32_t pll_id;
1461
1462         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1463         if (port == PORT_A || port == PORT_B) {
1464                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1465                         link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1466                 else
1467                         link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1468                                                                 pll_id);
1469         } else {
1470                 /* FIXME - Add for MG PLL */
1471                 WARN(1, "MG PLL clock_get code not implemented yet\n");
1472         }
1473
1474         pipe_config->port_clock = link_clock;
1475         ddi_dotclock_get(pipe_config);
1476 }
1477
1478 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1479                               struct intel_crtc_state *pipe_config)
1480 {
1481         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1482         int link_clock = 0;
1483         uint32_t cfgcr0;
1484         enum intel_dpll_id pll_id;
1485
1486         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1487
1488         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1489
1490         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1491                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1492         } else {
1493                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1494
1495                 switch (link_clock) {
1496                 case DPLL_CFGCR0_LINK_RATE_810:
1497                         link_clock = 81000;
1498                         break;
1499                 case DPLL_CFGCR0_LINK_RATE_1080:
1500                         link_clock = 108000;
1501                         break;
1502                 case DPLL_CFGCR0_LINK_RATE_1350:
1503                         link_clock = 135000;
1504                         break;
1505                 case DPLL_CFGCR0_LINK_RATE_1620:
1506                         link_clock = 162000;
1507                         break;
1508                 case DPLL_CFGCR0_LINK_RATE_2160:
1509                         link_clock = 216000;
1510                         break;
1511                 case DPLL_CFGCR0_LINK_RATE_2700:
1512                         link_clock = 270000;
1513                         break;
1514                 case DPLL_CFGCR0_LINK_RATE_3240:
1515                         link_clock = 324000;
1516                         break;
1517                 case DPLL_CFGCR0_LINK_RATE_4050:
1518                         link_clock = 405000;
1519                         break;
1520                 default:
1521                         WARN(1, "Unsupported link rate\n");
1522                         break;
1523                 }
1524                 link_clock *= 2;
1525         }
1526
1527         pipe_config->port_clock = link_clock;
1528
1529         ddi_dotclock_get(pipe_config);
1530 }
1531
1532 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1533                                 struct intel_crtc_state *pipe_config)
1534 {
1535         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1536         int link_clock = 0;
1537         uint32_t dpll_ctl1;
1538         enum intel_dpll_id pll_id;
1539
1540         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1541
1542         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1543
1544         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1545                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1546         } else {
1547                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1548                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1549
1550                 switch (link_clock) {
1551                 case DPLL_CTRL1_LINK_RATE_810:
1552                         link_clock = 81000;
1553                         break;
1554                 case DPLL_CTRL1_LINK_RATE_1080:
1555                         link_clock = 108000;
1556                         break;
1557                 case DPLL_CTRL1_LINK_RATE_1350:
1558                         link_clock = 135000;
1559                         break;
1560                 case DPLL_CTRL1_LINK_RATE_1620:
1561                         link_clock = 162000;
1562                         break;
1563                 case DPLL_CTRL1_LINK_RATE_2160:
1564                         link_clock = 216000;
1565                         break;
1566                 case DPLL_CTRL1_LINK_RATE_2700:
1567                         link_clock = 270000;
1568                         break;
1569                 default:
1570                         WARN(1, "Unsupported link rate\n");
1571                         break;
1572                 }
1573                 link_clock *= 2;
1574         }
1575
1576         pipe_config->port_clock = link_clock;
1577
1578         ddi_dotclock_get(pipe_config);
1579 }
1580
1581 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1582                               struct intel_crtc_state *pipe_config)
1583 {
1584         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1585         int link_clock = 0;
1586         u32 val, pll;
1587
1588         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1589         switch (val & PORT_CLK_SEL_MASK) {
1590         case PORT_CLK_SEL_LCPLL_810:
1591                 link_clock = 81000;
1592                 break;
1593         case PORT_CLK_SEL_LCPLL_1350:
1594                 link_clock = 135000;
1595                 break;
1596         case PORT_CLK_SEL_LCPLL_2700:
1597                 link_clock = 270000;
1598                 break;
1599         case PORT_CLK_SEL_WRPLL1:
1600                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1601                 break;
1602         case PORT_CLK_SEL_WRPLL2:
1603                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1604                 break;
1605         case PORT_CLK_SEL_SPLL:
1606                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1607                 if (pll == SPLL_PLL_FREQ_810MHz)
1608                         link_clock = 81000;
1609                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1610                         link_clock = 135000;
1611                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1612                         link_clock = 270000;
1613                 else {
1614                         WARN(1, "bad spll freq\n");
1615                         return;
1616                 }
1617                 break;
1618         default:
1619                 WARN(1, "bad port clock sel\n");
1620                 return;
1621         }
1622
1623         pipe_config->port_clock = link_clock * 2;
1624
1625         ddi_dotclock_get(pipe_config);
1626 }
1627
1628 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1629 {
1630         struct intel_dpll_hw_state *state;
1631         struct dpll clock;
1632
1633         /* For DDI ports we always use a shared PLL. */
1634         if (WARN_ON(!crtc_state->shared_dpll))
1635                 return 0;
1636
1637         state = &crtc_state->dpll_hw_state;
1638
1639         clock.m1 = 2;
1640         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1641         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1642                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1643         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1644         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1645         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1646
1647         return chv_calc_dpll_params(100000, &clock);
1648 }
1649
1650 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1651                               struct intel_crtc_state *pipe_config)
1652 {
1653         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1654
1655         ddi_dotclock_get(pipe_config);
1656 }
1657
1658 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1659                                 struct intel_crtc_state *pipe_config)
1660 {
1661         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1662
1663         if (INTEL_GEN(dev_priv) <= 8)
1664                 hsw_ddi_clock_get(encoder, pipe_config);
1665         else if (IS_GEN9_BC(dev_priv))
1666                 skl_ddi_clock_get(encoder, pipe_config);
1667         else if (IS_GEN9_LP(dev_priv))
1668                 bxt_ddi_clock_get(encoder, pipe_config);
1669         else if (IS_CANNONLAKE(dev_priv))
1670                 cnl_ddi_clock_get(encoder, pipe_config);
1671         else if (IS_ICELAKE(dev_priv))
1672                 icl_ddi_clock_get(encoder, pipe_config);
1673 }
1674
1675 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1676 {
1677         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1678         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1679         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1680         u32 temp;
1681
1682         if (!intel_crtc_has_dp_encoder(crtc_state))
1683                 return;
1684
1685         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1686
1687         temp = TRANS_MSA_SYNC_CLK;
1688         switch (crtc_state->pipe_bpp) {
1689         case 18:
1690                 temp |= TRANS_MSA_6_BPC;
1691                 break;
1692         case 24:
1693                 temp |= TRANS_MSA_8_BPC;
1694                 break;
1695         case 30:
1696                 temp |= TRANS_MSA_10_BPC;
1697                 break;
1698         case 36:
1699                 temp |= TRANS_MSA_12_BPC;
1700                 break;
1701         default:
1702                 MISSING_CASE(crtc_state->pipe_bpp);
1703                 break;
1704         }
1705
1706         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1707 }
1708
1709 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1710                                     bool state)
1711 {
1712         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1713         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1714         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1715         uint32_t temp;
1716
1717         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1718         if (state == true)
1719                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1720         else
1721                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1722         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1723 }
1724
1725 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1726 {
1727         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1728         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1729         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1730         enum pipe pipe = crtc->pipe;
1731         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1732         enum port port = encoder->port;
1733         uint32_t temp;
1734
1735         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1736         temp = TRANS_DDI_FUNC_ENABLE;
1737         temp |= TRANS_DDI_SELECT_PORT(port);
1738
1739         switch (crtc_state->pipe_bpp) {
1740         case 18:
1741                 temp |= TRANS_DDI_BPC_6;
1742                 break;
1743         case 24:
1744                 temp |= TRANS_DDI_BPC_8;
1745                 break;
1746         case 30:
1747                 temp |= TRANS_DDI_BPC_10;
1748                 break;
1749         case 36:
1750                 temp |= TRANS_DDI_BPC_12;
1751                 break;
1752         default:
1753                 BUG();
1754         }
1755
1756         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1757                 temp |= TRANS_DDI_PVSYNC;
1758         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1759                 temp |= TRANS_DDI_PHSYNC;
1760
1761         if (cpu_transcoder == TRANSCODER_EDP) {
1762                 switch (pipe) {
1763                 case PIPE_A:
1764                         /* On Haswell, can only use the always-on power well for
1765                          * eDP when not using the panel fitter, and when not
1766                          * using motion blur mitigation (which we don't
1767                          * support). */
1768                         if (IS_HASWELL(dev_priv) &&
1769                             (crtc_state->pch_pfit.enabled ||
1770                              crtc_state->pch_pfit.force_thru))
1771                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1772                         else
1773                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1774                         break;
1775                 case PIPE_B:
1776                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1777                         break;
1778                 case PIPE_C:
1779                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1780                         break;
1781                 default:
1782                         BUG();
1783                         break;
1784                 }
1785         }
1786
1787         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1788                 if (crtc_state->has_hdmi_sink)
1789                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1790                 else
1791                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1792
1793                 if (crtc_state->hdmi_scrambling)
1794                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1795                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1796                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1797         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1798                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1799                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1800         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1801                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1802                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1803         } else {
1804                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1805                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1806         }
1807
1808         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1809 }
1810
1811 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1812 {
1813         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1814         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1815         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1816         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1817         uint32_t val = I915_READ(reg);
1818
1819         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1820         val |= TRANS_DDI_PORT_NONE;
1821         I915_WRITE(reg, val);
1822
1823         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1824             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1825                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1826                 /* Quirk time at 100ms for reliable operation */
1827                 msleep(100);
1828         }
1829 }
1830
1831 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1832                                      bool enable)
1833 {
1834         struct drm_device *dev = intel_encoder->base.dev;
1835         struct drm_i915_private *dev_priv = to_i915(dev);
1836         enum pipe pipe = 0;
1837         int ret = 0;
1838         uint32_t tmp;
1839
1840         if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1841                                                 intel_encoder->power_domain)))
1842                 return -ENXIO;
1843
1844         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1845                 ret = -EIO;
1846                 goto out;
1847         }
1848
1849         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1850         if (enable)
1851                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1852         else
1853                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1854         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1855 out:
1856         intel_display_power_put(dev_priv, intel_encoder->power_domain);
1857         return ret;
1858 }
1859
1860 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1861 {
1862         struct drm_device *dev = intel_connector->base.dev;
1863         struct drm_i915_private *dev_priv = to_i915(dev);
1864         struct intel_encoder *encoder = intel_connector->encoder;
1865         int type = intel_connector->base.connector_type;
1866         enum port port = encoder->port;
1867         enum pipe pipe = 0;
1868         enum transcoder cpu_transcoder;
1869         uint32_t tmp;
1870         bool ret;
1871
1872         if (!intel_display_power_get_if_enabled(dev_priv,
1873                                                 encoder->power_domain))
1874                 return false;
1875
1876         if (!encoder->get_hw_state(encoder, &pipe)) {
1877                 ret = false;
1878                 goto out;
1879         }
1880
1881         if (port == PORT_A)
1882                 cpu_transcoder = TRANSCODER_EDP;
1883         else
1884                 cpu_transcoder = (enum transcoder) pipe;
1885
1886         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1887
1888         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1889         case TRANS_DDI_MODE_SELECT_HDMI:
1890         case TRANS_DDI_MODE_SELECT_DVI:
1891                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1892                 break;
1893
1894         case TRANS_DDI_MODE_SELECT_DP_SST:
1895                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1896                       type == DRM_MODE_CONNECTOR_DisplayPort;
1897                 break;
1898
1899         case TRANS_DDI_MODE_SELECT_DP_MST:
1900                 /* if the transcoder is in MST state then
1901                  * connector isn't connected */
1902                 ret = false;
1903                 break;
1904
1905         case TRANS_DDI_MODE_SELECT_FDI:
1906                 ret = type == DRM_MODE_CONNECTOR_VGA;
1907                 break;
1908
1909         default:
1910                 ret = false;
1911                 break;
1912         }
1913
1914 out:
1915         intel_display_power_put(dev_priv, encoder->power_domain);
1916
1917         return ret;
1918 }
1919
1920 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1921                             enum pipe *pipe)
1922 {
1923         struct drm_device *dev = encoder->base.dev;
1924         struct drm_i915_private *dev_priv = to_i915(dev);
1925         enum port port = encoder->port;
1926         enum pipe p;
1927         u32 tmp;
1928         bool ret;
1929
1930         if (!intel_display_power_get_if_enabled(dev_priv,
1931                                                 encoder->power_domain))
1932                 return false;
1933
1934         ret = false;
1935
1936         tmp = I915_READ(DDI_BUF_CTL(port));
1937
1938         if (!(tmp & DDI_BUF_CTL_ENABLE))
1939                 goto out;
1940
1941         if (port == PORT_A) {
1942                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1943
1944                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1945                 case TRANS_DDI_EDP_INPUT_A_ON:
1946                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1947                         *pipe = PIPE_A;
1948                         break;
1949                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1950                         *pipe = PIPE_B;
1951                         break;
1952                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1953                         *pipe = PIPE_C;
1954                         break;
1955                 }
1956
1957                 ret = true;
1958
1959                 goto out;
1960         }
1961
1962         for_each_pipe(dev_priv, p) {
1963                 enum transcoder cpu_transcoder = (enum transcoder) p;
1964
1965                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1966
1967                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1968                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1969                             TRANS_DDI_MODE_SELECT_DP_MST)
1970                                 goto out;
1971
1972                         *pipe = p;
1973                         ret = true;
1974
1975                         goto out;
1976                 }
1977         }
1978
1979         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1980
1981 out:
1982         if (ret && IS_GEN9_LP(dev_priv)) {
1983                 tmp = I915_READ(BXT_PHY_CTL(port));
1984                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1985                             BXT_PHY_LANE_POWERDOWN_ACK |
1986                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1987                         DRM_ERROR("Port %c enabled but PHY powered down? "
1988                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1989         }
1990
1991         intel_display_power_put(dev_priv, encoder->power_domain);
1992
1993         return ret;
1994 }
1995
1996 static inline enum intel_display_power_domain
1997 intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
1998 {
1999         /* CNL HW requires corresponding AUX IOs to be powered up for PSR with
2000          * DC states enabled at the same time, while for driver initiated AUX
2001          * transfers we need the same AUX IOs to be powered but with DC states
2002          * disabled. Accordingly use the AUX power domain here which leaves DC
2003          * states enabled.
2004          * However, for non-A AUX ports the corresponding non-EDP transcoders
2005          * would have already enabled power well 2 and DC_OFF. This means we can
2006          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2007          * specific AUX_IO reference without powering up any extra wells.
2008          * Note that PSR is enabled only on Port A even though this function
2009          * returns the correct domain for other ports too.
2010          */
2011         return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2012                                               intel_dp->aux_power_domain;
2013 }
2014
2015 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2016                                        struct intel_crtc_state *crtc_state)
2017 {
2018         struct intel_digital_port *dig_port;
2019         u64 domains;
2020
2021         /*
2022          * TODO: Add support for MST encoders. Atm, the following should never
2023          * happen since fake-MST encoders don't set their get_power_domains()
2024          * hook.
2025          */
2026         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2027                 return 0;
2028
2029         dig_port = enc_to_dig_port(&encoder->base);
2030         domains = BIT_ULL(dig_port->ddi_io_power_domain);
2031
2032         /* AUX power is only needed for (e)DP mode, not for HDMI. */
2033         if (intel_crtc_has_dp_encoder(crtc_state)) {
2034                 struct intel_dp *intel_dp = &dig_port->dp;
2035
2036                 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(intel_dp));
2037         }
2038
2039         return domains;
2040 }
2041
2042 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2043 {
2044         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2045         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2046         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2047         enum port port = encoder->port;
2048         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2049
2050         if (cpu_transcoder != TRANSCODER_EDP)
2051                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2052                            TRANS_CLK_SEL_PORT(port));
2053 }
2054
2055 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2056 {
2057         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2058         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2059
2060         if (cpu_transcoder != TRANSCODER_EDP)
2061                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2062                            TRANS_CLK_SEL_DISABLED);
2063 }
2064
2065 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2066                                 enum port port, uint8_t iboost)
2067 {
2068         u32 tmp;
2069
2070         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2071         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2072         if (iboost)
2073                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2074         else
2075                 tmp |= BALANCE_LEG_DISABLE(port);
2076         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2077 }
2078
2079 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2080                                int level, enum intel_output_type type)
2081 {
2082         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2083         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2084         enum port port = encoder->port;
2085         uint8_t iboost;
2086
2087         if (type == INTEL_OUTPUT_HDMI)
2088                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2089         else
2090                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2091
2092         if (iboost == 0) {
2093                 const struct ddi_buf_trans *ddi_translations;
2094                 int n_entries;
2095
2096                 if (type == INTEL_OUTPUT_HDMI)
2097                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2098                 else if (type == INTEL_OUTPUT_EDP)
2099                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2100                 else
2101                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2102
2103                 if (WARN_ON_ONCE(!ddi_translations))
2104                         return;
2105                 if (WARN_ON_ONCE(level >= n_entries))
2106                         level = n_entries - 1;
2107
2108                 iboost = ddi_translations[level].i_boost;
2109         }
2110
2111         /* Make sure that the requested I_boost is valid */
2112         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2113                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2114                 return;
2115         }
2116
2117         _skl_ddi_set_iboost(dev_priv, port, iboost);
2118
2119         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2120                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2121 }
2122
2123 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2124                                     int level, enum intel_output_type type)
2125 {
2126         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2127         const struct bxt_ddi_buf_trans *ddi_translations;
2128         enum port port = encoder->port;
2129         int n_entries;
2130
2131         if (type == INTEL_OUTPUT_HDMI)
2132                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2133         else if (type == INTEL_OUTPUT_EDP)
2134                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2135         else
2136                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2137
2138         if (WARN_ON_ONCE(!ddi_translations))
2139                 return;
2140         if (WARN_ON_ONCE(level >= n_entries))
2141                 level = n_entries - 1;
2142
2143         bxt_ddi_phy_set_signal_level(dev_priv, port,
2144                                      ddi_translations[level].margin,
2145                                      ddi_translations[level].scale,
2146                                      ddi_translations[level].enable,
2147                                      ddi_translations[level].deemphasis);
2148 }
2149
2150 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2151 {
2152         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2153         enum port port = encoder->port;
2154         int n_entries;
2155
2156         if (IS_ICELAKE(dev_priv)) {
2157                 if (port == PORT_A || port == PORT_B)
2158                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2159                                                 &n_entries);
2160                 else
2161                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2162         } else if (IS_CANNONLAKE(dev_priv)) {
2163                 if (encoder->type == INTEL_OUTPUT_EDP)
2164                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2165                 else
2166                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2167         } else if (IS_GEN9_LP(dev_priv)) {
2168                 if (encoder->type == INTEL_OUTPUT_EDP)
2169                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2170                 else
2171                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2172         } else {
2173                 if (encoder->type == INTEL_OUTPUT_EDP)
2174                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2175                 else
2176                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2177         }
2178
2179         if (WARN_ON(n_entries < 1))
2180                 n_entries = 1;
2181         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2182                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2183
2184         return index_to_dp_signal_levels[n_entries - 1] &
2185                 DP_TRAIN_VOLTAGE_SWING_MASK;
2186 }
2187
2188 /*
2189  * We assume that the full set of pre-emphasis values can be
2190  * used on all DDI platforms. Should that change we need to
2191  * rethink this code.
2192  */
2193 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2194 {
2195         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2196         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2197                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2198         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2199                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2200         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2201                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2202         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2203         default:
2204                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2205         }
2206 }
2207
2208 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2209                                    int level, enum intel_output_type type)
2210 {
2211         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2212         const struct cnl_ddi_buf_trans *ddi_translations;
2213         enum port port = encoder->port;
2214         int n_entries, ln;
2215         u32 val;
2216
2217         if (type == INTEL_OUTPUT_HDMI)
2218                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2219         else if (type == INTEL_OUTPUT_EDP)
2220                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2221         else
2222                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2223
2224         if (WARN_ON_ONCE(!ddi_translations))
2225                 return;
2226         if (WARN_ON_ONCE(level >= n_entries))
2227                 level = n_entries - 1;
2228
2229         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2230         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2231         val &= ~SCALING_MODE_SEL_MASK;
2232         val |= SCALING_MODE_SEL(2);
2233         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2234
2235         /* Program PORT_TX_DW2 */
2236         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2237         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2238                  RCOMP_SCALAR_MASK);
2239         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2240         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2241         /* Rcomp scalar is fixed as 0x98 for every table entry */
2242         val |= RCOMP_SCALAR(0x98);
2243         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2244
2245         /* Program PORT_TX_DW4 */
2246         /* We cannot write to GRP. It would overrite individual loadgen */
2247         for (ln = 0; ln < 4; ln++) {
2248                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2249                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2250                          CURSOR_COEFF_MASK);
2251                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2252                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2253                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2254                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2255         }
2256
2257         /* Program PORT_TX_DW5 */
2258         /* All DW5 values are fixed for every table entry */
2259         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2260         val &= ~RTERM_SELECT_MASK;
2261         val |= RTERM_SELECT(6);
2262         val |= TAP3_DISABLE;
2263         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2264
2265         /* Program PORT_TX_DW7 */
2266         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2267         val &= ~N_SCALAR_MASK;
2268         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2269         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2270 }
2271
2272 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2273                                     int level, enum intel_output_type type)
2274 {
2275         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2276         enum port port = encoder->port;
2277         int width, rate, ln;
2278         u32 val;
2279
2280         if (type == INTEL_OUTPUT_HDMI) {
2281                 width = 4;
2282                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2283         } else {
2284                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2285
2286                 width = intel_dp->lane_count;
2287                 rate = intel_dp->link_rate;
2288         }
2289
2290         /*
2291          * 1. If port type is eDP or DP,
2292          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2293          * else clear to 0b.
2294          */
2295         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2296         if (type != INTEL_OUTPUT_HDMI)
2297                 val |= COMMON_KEEPER_EN;
2298         else
2299                 val &= ~COMMON_KEEPER_EN;
2300         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2301
2302         /* 2. Program loadgen select */
2303         /*
2304          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2305          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2306          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2307          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2308          */
2309         for (ln = 0; ln <= 3; ln++) {
2310                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2311                 val &= ~LOADGEN_SELECT;
2312
2313                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2314                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2315                         val |= LOADGEN_SELECT;
2316                 }
2317                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2318         }
2319
2320         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2321         val = I915_READ(CNL_PORT_CL1CM_DW5);
2322         val |= SUS_CLOCK_CONFIG;
2323         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2324
2325         /* 4. Clear training enable to change swing values */
2326         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2327         val &= ~TX_TRAINING_EN;
2328         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2329
2330         /* 5. Program swing and de-emphasis */
2331         cnl_ddi_vswing_program(encoder, level, type);
2332
2333         /* 6. Set training enable to trigger update */
2334         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2335         val |= TX_TRAINING_EN;
2336         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2337 }
2338
2339 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2340                                          u32 level, enum port port, int type)
2341 {
2342         const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2343         u32 n_entries, val;
2344         int ln;
2345
2346         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2347                                                    &n_entries);
2348         if (!ddi_translations)
2349                 return;
2350
2351         if (level >= n_entries) {
2352                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2353                 level = n_entries - 1;
2354         }
2355
2356         /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2357         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2358         val &= ~RTERM_SELECT_MASK;
2359         val |= RTERM_SELECT(0x6);
2360         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2361
2362         /* Program PORT_TX_DW5 */
2363         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2364         /* Set DisableTap2 and DisableTap3 if MIPI DSI
2365          * Clear DisableTap2 and DisableTap3 for all other Ports
2366          */
2367         if (type == INTEL_OUTPUT_DSI) {
2368                 val |= TAP2_DISABLE;
2369                 val |= TAP3_DISABLE;
2370         } else {
2371                 val &= ~TAP2_DISABLE;
2372                 val &= ~TAP3_DISABLE;
2373         }
2374         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2375
2376         /* Program PORT_TX_DW2 */
2377         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2378         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2379                  RCOMP_SCALAR_MASK);
2380         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2381         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2382         /* Program Rcomp scalar for every table entry */
2383         val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2384         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2385
2386         /* Program PORT_TX_DW4 */
2387         /* We cannot write to GRP. It would overwrite individual loadgen. */
2388         for (ln = 0; ln <= 3; ln++) {
2389                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2390                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2391                          CURSOR_COEFF_MASK);
2392                 val |= ddi_translations[level].dw4_scaling;
2393                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2394         }
2395 }
2396
2397 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2398                                               u32 level,
2399                                               enum intel_output_type type)
2400 {
2401         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2402         enum port port = encoder->port;
2403         int width = 0;
2404         int rate = 0;
2405         u32 val;
2406         int ln = 0;
2407
2408         if (type == INTEL_OUTPUT_HDMI) {
2409                 width = 4;
2410                 /* Rate is always < than 6GHz for HDMI */
2411         } else {
2412                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2413
2414                 width = intel_dp->lane_count;
2415                 rate = intel_dp->link_rate;
2416         }
2417
2418         /*
2419          * 1. If port type is eDP or DP,
2420          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2421          * else clear to 0b.
2422          */
2423         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2424         if (type == INTEL_OUTPUT_HDMI)
2425                 val &= ~COMMON_KEEPER_EN;
2426         else
2427                 val |= COMMON_KEEPER_EN;
2428         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2429
2430         /* 2. Program loadgen select */
2431         /*
2432          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2433          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2434          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2435          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2436          */
2437         for (ln = 0; ln <= 3; ln++) {
2438                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2439                 val &= ~LOADGEN_SELECT;
2440
2441                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2442                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2443                         val |= LOADGEN_SELECT;
2444                 }
2445                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2446         }
2447
2448         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2449         val = I915_READ(ICL_PORT_CL_DW5(port));
2450         val |= SUS_CLOCK_CONFIG;
2451         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2452
2453         /* 4. Clear training enable to change swing values */
2454         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2455         val &= ~TX_TRAINING_EN;
2456         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2457
2458         /* 5. Program swing and de-emphasis */
2459         icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2460
2461         /* 6. Set training enable to trigger update */
2462         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2463         val |= TX_TRAINING_EN;
2464         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2465 }
2466
2467 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2468                                            int link_clock,
2469                                            u32 level)
2470 {
2471         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2472         enum port port = encoder->port;
2473         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2474         u32 n_entries, val;
2475         int ln;
2476
2477         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2478         ddi_translations = icl_mg_phy_ddi_translations;
2479         /* The table does not have values for level 3 and level 9. */
2480         if (level >= n_entries || level == 3 || level == 9) {
2481                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2482                               level, n_entries - 2);
2483                 level = n_entries - 2;
2484         }
2485
2486         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2487         for (ln = 0; ln < 2; ln++) {
2488                 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2489                 val &= ~CRI_USE_FS32;
2490                 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2491
2492                 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2493                 val &= ~CRI_USE_FS32;
2494                 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2495         }
2496
2497         /* Program MG_TX_SWINGCTRL with values from vswing table */
2498         for (ln = 0; ln < 2; ln++) {
2499                 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2500                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2501                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2502                         ddi_translations[level].cri_txdeemph_override_17_12);
2503                 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2504
2505                 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2506                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2507                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2508                         ddi_translations[level].cri_txdeemph_override_17_12);
2509                 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2510         }
2511
2512         /* Program MG_TX_DRVCTRL with values from vswing table */
2513         for (ln = 0; ln < 2; ln++) {
2514                 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2515                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2516                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2517                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2518                         ddi_translations[level].cri_txdeemph_override_5_0) |
2519                         CRI_TXDEEMPH_OVERRIDE_11_6(
2520                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2521                         CRI_TXDEEMPH_OVERRIDE_EN;
2522                 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2523
2524                 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2525                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2526                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2527                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2528                         ddi_translations[level].cri_txdeemph_override_5_0) |
2529                         CRI_TXDEEMPH_OVERRIDE_11_6(
2530                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2531                         CRI_TXDEEMPH_OVERRIDE_EN;
2532                 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2533
2534                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2535         }
2536
2537         /*
2538          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2539          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2540          * values from table for which TX1 and TX2 enabled.
2541          */
2542         for (ln = 0; ln < 2; ln++) {
2543                 val = I915_READ(MG_CLKHUB(port, ln));
2544                 if (link_clock < 300000)
2545                         val |= CFG_LOW_RATE_LKREN_EN;
2546                 else
2547                         val &= ~CFG_LOW_RATE_LKREN_EN;
2548                 I915_WRITE(MG_CLKHUB(port, ln), val);
2549         }
2550
2551         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2552         for (ln = 0; ln < 2; ln++) {
2553                 val = I915_READ(MG_TX1_DCC(port, ln));
2554                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2555                 if (link_clock <= 500000) {
2556                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2557                 } else {
2558                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2559                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2560                 }
2561                 I915_WRITE(MG_TX1_DCC(port, ln), val);
2562
2563                 val = I915_READ(MG_TX2_DCC(port, ln));
2564                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2565                 if (link_clock <= 500000) {
2566                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2567                 } else {
2568                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2569                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2570                 }
2571                 I915_WRITE(MG_TX2_DCC(port, ln), val);
2572         }
2573
2574         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2575         for (ln = 0; ln < 2; ln++) {
2576                 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2577                 val |= CRI_CALCINIT;
2578                 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2579
2580                 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2581                 val |= CRI_CALCINIT;
2582                 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2583         }
2584 }
2585
2586 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2587                                     int link_clock,
2588                                     u32 level,
2589                                     enum intel_output_type type)
2590 {
2591         enum port port = encoder->port;
2592
2593         if (port == PORT_A || port == PORT_B)
2594                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2595         else
2596                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2597 }
2598
2599 static uint32_t translate_signal_level(int signal_levels)
2600 {
2601         int i;
2602
2603         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2604                 if (index_to_dp_signal_levels[i] == signal_levels)
2605                         return i;
2606         }
2607
2608         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2609              signal_levels);
2610
2611         return 0;
2612 }
2613
2614 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2615 {
2616         uint8_t train_set = intel_dp->train_set[0];
2617         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2618                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2619
2620         return translate_signal_level(signal_levels);
2621 }
2622
2623 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2624 {
2625         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2626         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2627         struct intel_encoder *encoder = &dport->base;
2628         int level = intel_ddi_dp_level(intel_dp);
2629
2630         if (IS_ICELAKE(dev_priv))
2631                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2632                                         level, encoder->type);
2633         else if (IS_CANNONLAKE(dev_priv))
2634                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2635         else
2636                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2637
2638         return 0;
2639 }
2640
2641 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2642 {
2643         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2644         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2645         struct intel_encoder *encoder = &dport->base;
2646         int level = intel_ddi_dp_level(intel_dp);
2647
2648         if (IS_GEN9_BC(dev_priv))
2649                 skl_ddi_set_iboost(encoder, level, encoder->type);
2650
2651         return DDI_BUF_TRANS_SELECT(level);
2652 }
2653
2654 void icl_map_plls_to_ports(struct drm_crtc *crtc,
2655                            struct intel_crtc_state *crtc_state,
2656                            struct drm_atomic_state *old_state)
2657 {
2658         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2659         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2660         struct drm_connector_state *conn_state;
2661         struct drm_connector *conn;
2662         int i;
2663
2664         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2665                 struct intel_encoder *encoder =
2666                         to_intel_encoder(conn_state->best_encoder);
2667                 enum port port;
2668                 uint32_t val;
2669
2670                 if (conn_state->crtc != crtc)
2671                         continue;
2672
2673                 port = encoder->port;
2674                 mutex_lock(&dev_priv->dpll_lock);
2675
2676                 val = I915_READ(DPCLKA_CFGCR0_ICL);
2677                 WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
2678
2679                 if (port == PORT_A || port == PORT_B) {
2680                         val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2681                         val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2682                         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2683                         POSTING_READ(DPCLKA_CFGCR0_ICL);
2684                 }
2685
2686                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2687                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2688
2689                 mutex_unlock(&dev_priv->dpll_lock);
2690         }
2691 }
2692
2693 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2694                              struct intel_crtc_state *crtc_state,
2695                              struct drm_atomic_state *old_state)
2696 {
2697         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2698         struct drm_connector_state *old_conn_state;
2699         struct drm_connector *conn;
2700         int i;
2701
2702         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2703                 struct intel_encoder *encoder =
2704                         to_intel_encoder(old_conn_state->best_encoder);
2705                 enum port port;
2706
2707                 if (old_conn_state->crtc != crtc)
2708                         continue;
2709
2710                 port = encoder->port;
2711                 mutex_lock(&dev_priv->dpll_lock);
2712                 I915_WRITE(DPCLKA_CFGCR0_ICL,
2713                            I915_READ(DPCLKA_CFGCR0_ICL) |
2714                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2715                 mutex_unlock(&dev_priv->dpll_lock);
2716         }
2717 }
2718
2719 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2720                                  const struct intel_shared_dpll *pll)
2721 {
2722         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2723         enum port port = encoder->port;
2724         uint32_t val;
2725
2726         if (WARN_ON(!pll))
2727                 return;
2728
2729         mutex_lock(&dev_priv->dpll_lock);
2730
2731         if (IS_ICELAKE(dev_priv)) {
2732                 if (port >= PORT_C)
2733                         I915_WRITE(DDI_CLK_SEL(port),
2734                                    icl_pll_to_ddi_pll_sel(encoder, pll));
2735         } else if (IS_CANNONLAKE(dev_priv)) {
2736                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2737                 val = I915_READ(DPCLKA_CFGCR0);
2738                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2739                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2740                 I915_WRITE(DPCLKA_CFGCR0, val);
2741
2742                 /*
2743                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2744                  * This step and the step before must be done with separate
2745                  * register writes.
2746                  */
2747                 val = I915_READ(DPCLKA_CFGCR0);
2748                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2749                 I915_WRITE(DPCLKA_CFGCR0, val);
2750         } else if (IS_GEN9_BC(dev_priv)) {
2751                 /* DDI -> PLL mapping  */
2752                 val = I915_READ(DPLL_CTRL2);
2753
2754                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2755                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2756                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2757                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2758
2759                 I915_WRITE(DPLL_CTRL2, val);
2760
2761         } else if (INTEL_GEN(dev_priv) < 9) {
2762                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2763         }
2764
2765         mutex_unlock(&dev_priv->dpll_lock);
2766 }
2767
2768 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2769 {
2770         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2771         enum port port = encoder->port;
2772
2773         if (IS_ICELAKE(dev_priv)) {
2774                 if (port >= PORT_C)
2775                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2776         } else if (IS_CANNONLAKE(dev_priv)) {
2777                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2778                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2779         } else if (IS_GEN9_BC(dev_priv)) {
2780                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2781                            DPLL_CTRL2_DDI_CLK_OFF(port));
2782         } else if (INTEL_GEN(dev_priv) < 9) {
2783                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2784         }
2785 }
2786
2787 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2788                                     const struct intel_crtc_state *crtc_state,
2789                                     const struct drm_connector_state *conn_state)
2790 {
2791         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2792         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2793         enum port port = encoder->port;
2794         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2795         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2796         int level = intel_ddi_dp_level(intel_dp);
2797
2798         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2799
2800         intel_display_power_get(dev_priv,
2801                                 intel_ddi_main_link_aux_domain(intel_dp));
2802
2803         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2804                                  crtc_state->lane_count, is_mst);
2805
2806         intel_edp_panel_on(intel_dp);
2807
2808         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2809
2810         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2811
2812         if (IS_ICELAKE(dev_priv))
2813                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2814                                         level, encoder->type);
2815         else if (IS_CANNONLAKE(dev_priv))
2816                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2817         else if (IS_GEN9_LP(dev_priv))
2818                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2819         else
2820                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2821
2822         intel_ddi_init_dp_buf_reg(encoder);
2823         if (!is_mst)
2824                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2825         intel_dp_start_link_train(intel_dp);
2826         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2827                 intel_dp_stop_link_train(intel_dp);
2828
2829         intel_ddi_enable_pipe_clock(crtc_state);
2830 }
2831
2832 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2833                                       const struct intel_crtc_state *crtc_state,
2834                                       const struct drm_connector_state *conn_state)
2835 {
2836         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2837         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2838         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2839         enum port port = encoder->port;
2840         int level = intel_ddi_hdmi_level(dev_priv, port);
2841         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2842
2843         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2844         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2845
2846         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2847
2848         if (IS_ICELAKE(dev_priv))
2849                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2850                                         level, INTEL_OUTPUT_HDMI);
2851         else if (IS_CANNONLAKE(dev_priv))
2852                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2853         else if (IS_GEN9_LP(dev_priv))
2854                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2855         else
2856                 intel_prepare_hdmi_ddi_buffers(encoder, level);
2857
2858         if (IS_GEN9_BC(dev_priv))
2859                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2860
2861         intel_ddi_enable_pipe_clock(crtc_state);
2862
2863         intel_dig_port->set_infoframes(&encoder->base,
2864                                        crtc_state->has_infoframe,
2865                                        crtc_state, conn_state);
2866 }
2867
2868 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2869                                  const struct intel_crtc_state *crtc_state,
2870                                  const struct drm_connector_state *conn_state)
2871 {
2872         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2873         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2874         enum pipe pipe = crtc->pipe;
2875
2876         /*
2877          * When called from DP MST code:
2878          * - conn_state will be NULL
2879          * - encoder will be the main encoder (ie. mst->primary)
2880          * - the main connector associated with this port
2881          *   won't be active or linked to a crtc
2882          * - crtc_state will be the state of the first stream to
2883          *   be activated on this port, and it may not be the same
2884          *   stream that will be deactivated last, but each stream
2885          *   should have a state that is identical when it comes to
2886          *   the DP link parameteres
2887          */
2888
2889         WARN_ON(crtc_state->has_pch_encoder);
2890
2891         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2892
2893         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2894                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2895         else
2896                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
2897 }
2898
2899 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2900 {
2901         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2902         enum port port = encoder->port;
2903         bool wait = false;
2904         u32 val;
2905
2906         val = I915_READ(DDI_BUF_CTL(port));
2907         if (val & DDI_BUF_CTL_ENABLE) {
2908                 val &= ~DDI_BUF_CTL_ENABLE;
2909                 I915_WRITE(DDI_BUF_CTL(port), val);
2910                 wait = true;
2911         }
2912
2913         val = I915_READ(DP_TP_CTL(port));
2914         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2915         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2916         I915_WRITE(DP_TP_CTL(port), val);
2917
2918         if (wait)
2919                 intel_wait_ddi_buf_idle(dev_priv, port);
2920 }
2921
2922 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2923                                       const struct intel_crtc_state *old_crtc_state,
2924                                       const struct drm_connector_state *old_conn_state)
2925 {
2926         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2927         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2928         struct intel_dp *intel_dp = &dig_port->dp;
2929         bool is_mst = intel_crtc_has_type(old_crtc_state,
2930                                           INTEL_OUTPUT_DP_MST);
2931
2932         intel_ddi_disable_pipe_clock(old_crtc_state);
2933
2934         /*
2935          * Power down sink before disabling the port, otherwise we end
2936          * up getting interrupts from the sink on detecting link loss.
2937          */
2938         if (!is_mst)
2939                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2940
2941         intel_disable_ddi_buf(encoder);
2942
2943         intel_edp_panel_vdd_on(intel_dp);
2944         intel_edp_panel_off(intel_dp);
2945
2946         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2947
2948         intel_ddi_clk_disable(encoder);
2949
2950         intel_display_power_put(dev_priv,
2951                                 intel_ddi_main_link_aux_domain(intel_dp));
2952 }
2953
2954 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2955                                         const struct intel_crtc_state *old_crtc_state,
2956                                         const struct drm_connector_state *old_conn_state)
2957 {
2958         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2959         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2960         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2961
2962         dig_port->set_infoframes(&encoder->base, false,
2963                                  old_crtc_state, old_conn_state);
2964
2965         intel_ddi_disable_pipe_clock(old_crtc_state);
2966
2967         intel_disable_ddi_buf(encoder);
2968
2969         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2970
2971         intel_ddi_clk_disable(encoder);
2972
2973         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2974 }
2975
2976 static void intel_ddi_post_disable(struct intel_encoder *encoder,
2977                                    const struct intel_crtc_state *old_crtc_state,
2978                                    const struct drm_connector_state *old_conn_state)
2979 {
2980         /*
2981          * When called from DP MST code:
2982          * - old_conn_state will be NULL
2983          * - encoder will be the main encoder (ie. mst->primary)
2984          * - the main connector associated with this port
2985          *   won't be active or linked to a crtc
2986          * - old_crtc_state will be the state of the last stream to
2987          *   be deactivated on this port, and it may not be the same
2988          *   stream that was activated last, but each stream
2989          *   should have a state that is identical when it comes to
2990          *   the DP link parameteres
2991          */
2992
2993         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2994                 intel_ddi_post_disable_hdmi(encoder,
2995                                             old_crtc_state, old_conn_state);
2996         else
2997                 intel_ddi_post_disable_dp(encoder,
2998                                           old_crtc_state, old_conn_state);
2999 }
3000
3001 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3002                                 const struct intel_crtc_state *old_crtc_state,
3003                                 const struct drm_connector_state *old_conn_state)
3004 {
3005         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3006         uint32_t val;
3007
3008         /*
3009          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3010          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3011          * step 13 is the correct place for it. Step 18 is where it was
3012          * originally before the BUN.
3013          */
3014         val = I915_READ(FDI_RX_CTL(PIPE_A));
3015         val &= ~FDI_RX_ENABLE;
3016         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3017
3018         intel_disable_ddi_buf(encoder);
3019         intel_ddi_clk_disable(encoder);
3020
3021         val = I915_READ(FDI_RX_MISC(PIPE_A));
3022         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3023         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3024         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3025
3026         val = I915_READ(FDI_RX_CTL(PIPE_A));
3027         val &= ~FDI_PCDCLK;
3028         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3029
3030         val = I915_READ(FDI_RX_CTL(PIPE_A));
3031         val &= ~FDI_RX_PLL_ENABLE;
3032         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3033 }
3034
3035 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3036                                 const struct intel_crtc_state *crtc_state,
3037                                 const struct drm_connector_state *conn_state)
3038 {
3039         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3040         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3041         enum port port = encoder->port;
3042
3043         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3044                 intel_dp_stop_link_train(intel_dp);
3045
3046         intel_edp_backlight_on(crtc_state, conn_state);
3047         intel_psr_enable(intel_dp, crtc_state);
3048         intel_edp_drrs_enable(intel_dp, crtc_state);
3049
3050         if (crtc_state->has_audio)
3051                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3052 }
3053
3054 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3055                                   const struct intel_crtc_state *crtc_state,
3056                                   const struct drm_connector_state *conn_state)
3057 {
3058         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3059         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3060         struct drm_connector *connector = conn_state->connector;
3061         enum port port = encoder->port;
3062
3063         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3064                                                crtc_state->hdmi_high_tmds_clock_ratio,
3065                                                crtc_state->hdmi_scrambling))
3066                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3067                           connector->base.id, connector->name);
3068
3069         /* Display WA #1143: skl,kbl,cfl */
3070         if (IS_GEN9_BC(dev_priv)) {
3071                 /*
3072                  * For some reason these chicken bits have been
3073                  * stuffed into a transcoder register, event though
3074                  * the bits affect a specific DDI port rather than
3075                  * a specific transcoder.
3076                  */
3077                 static const enum transcoder port_to_transcoder[] = {
3078                         [PORT_A] = TRANSCODER_EDP,
3079                         [PORT_B] = TRANSCODER_A,
3080                         [PORT_C] = TRANSCODER_B,
3081                         [PORT_D] = TRANSCODER_C,
3082                         [PORT_E] = TRANSCODER_A,
3083                 };
3084                 enum transcoder transcoder = port_to_transcoder[port];
3085                 u32 val;
3086
3087                 val = I915_READ(CHICKEN_TRANS(transcoder));
3088
3089                 if (port == PORT_E)
3090                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3091                                 DDIE_TRAINING_OVERRIDE_VALUE;
3092                 else
3093                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3094                                 DDI_TRAINING_OVERRIDE_VALUE;
3095
3096                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3097                 POSTING_READ(CHICKEN_TRANS(transcoder));
3098
3099                 udelay(1);
3100
3101                 if (port == PORT_E)
3102                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3103                                  DDIE_TRAINING_OVERRIDE_VALUE);
3104                 else
3105                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3106                                  DDI_TRAINING_OVERRIDE_VALUE);
3107
3108                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3109         }
3110
3111         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3112          * are ignored so nothing special needs to be done besides
3113          * enabling the port.
3114          */
3115         I915_WRITE(DDI_BUF_CTL(port),
3116                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3117
3118         if (crtc_state->has_audio)
3119                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3120 }
3121
3122 static void intel_enable_ddi(struct intel_encoder *encoder,
3123                              const struct intel_crtc_state *crtc_state,
3124                              const struct drm_connector_state *conn_state)
3125 {
3126         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3127                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3128         else
3129                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3130
3131         /* Enable hdcp if it's desired */
3132         if (conn_state->content_protection ==
3133             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3134                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3135 }
3136
3137 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3138                                  const struct intel_crtc_state *old_crtc_state,
3139                                  const struct drm_connector_state *old_conn_state)
3140 {
3141         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3142
3143         intel_dp->link_trained = false;
3144
3145         if (old_crtc_state->has_audio)
3146                 intel_audio_codec_disable(encoder,
3147                                           old_crtc_state, old_conn_state);
3148
3149         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3150         intel_psr_disable(intel_dp, old_crtc_state);
3151         intel_edp_backlight_off(old_conn_state);
3152 }
3153
3154 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3155                                    const struct intel_crtc_state *old_crtc_state,
3156                                    const struct drm_connector_state *old_conn_state)
3157 {
3158         struct drm_connector *connector = old_conn_state->connector;
3159
3160         if (old_crtc_state->has_audio)
3161                 intel_audio_codec_disable(encoder,
3162                                           old_crtc_state, old_conn_state);
3163
3164         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3165                                                false, false))
3166                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3167                               connector->base.id, connector->name);
3168 }
3169
3170 static void intel_disable_ddi(struct intel_encoder *encoder,
3171                               const struct intel_crtc_state *old_crtc_state,
3172                               const struct drm_connector_state *old_conn_state)
3173 {
3174         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3175
3176         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3177                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3178         else
3179                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3180 }
3181
3182 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
3183                                    const struct intel_crtc_state *pipe_config,
3184                                    const struct drm_connector_state *conn_state)
3185 {
3186         uint8_t mask = pipe_config->lane_lat_optim_mask;
3187
3188         bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
3189 }
3190
3191 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3192 {
3193         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3194         struct drm_i915_private *dev_priv =
3195                 to_i915(intel_dig_port->base.base.dev);
3196         enum port port = intel_dig_port->base.port;
3197         uint32_t val;
3198         bool wait = false;
3199
3200         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3201                 val = I915_READ(DDI_BUF_CTL(port));
3202                 if (val & DDI_BUF_CTL_ENABLE) {
3203                         val &= ~DDI_BUF_CTL_ENABLE;
3204                         I915_WRITE(DDI_BUF_CTL(port), val);
3205                         wait = true;
3206                 }
3207
3208                 val = I915_READ(DP_TP_CTL(port));
3209                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3210                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3211                 I915_WRITE(DP_TP_CTL(port), val);
3212                 POSTING_READ(DP_TP_CTL(port));
3213
3214                 if (wait)
3215                         intel_wait_ddi_buf_idle(dev_priv, port);
3216         }
3217
3218         val = DP_TP_CTL_ENABLE |
3219               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3220         if (intel_dp->link_mst)
3221                 val |= DP_TP_CTL_MODE_MST;
3222         else {
3223                 val |= DP_TP_CTL_MODE_SST;
3224                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3225                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3226         }
3227         I915_WRITE(DP_TP_CTL(port), val);
3228         POSTING_READ(DP_TP_CTL(port));
3229
3230         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3231         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3232         POSTING_READ(DDI_BUF_CTL(port));
3233
3234         udelay(600);
3235 }
3236
3237 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3238                                        enum transcoder cpu_transcoder)
3239 {
3240         if (cpu_transcoder == TRANSCODER_EDP)
3241                 return false;
3242
3243         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3244                 return false;
3245
3246         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3247                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3248 }
3249
3250 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3251                                          struct intel_crtc_state *crtc_state)
3252 {
3253         if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3254                 crtc_state->min_voltage_level = 2;
3255         else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3256                 crtc_state->min_voltage_level = 1;
3257 }
3258
3259 void intel_ddi_get_config(struct intel_encoder *encoder,
3260                           struct intel_crtc_state *pipe_config)
3261 {
3262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3263         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3264         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3265         struct intel_digital_port *intel_dig_port;
3266         u32 temp, flags = 0;
3267
3268         /* XXX: DSI transcoder paranoia */
3269         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3270                 return;
3271
3272         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3273         if (temp & TRANS_DDI_PHSYNC)
3274                 flags |= DRM_MODE_FLAG_PHSYNC;
3275         else
3276                 flags |= DRM_MODE_FLAG_NHSYNC;
3277         if (temp & TRANS_DDI_PVSYNC)
3278                 flags |= DRM_MODE_FLAG_PVSYNC;
3279         else
3280                 flags |= DRM_MODE_FLAG_NVSYNC;
3281
3282         pipe_config->base.adjusted_mode.flags |= flags;
3283
3284         switch (temp & TRANS_DDI_BPC_MASK) {
3285         case TRANS_DDI_BPC_6:
3286                 pipe_config->pipe_bpp = 18;
3287                 break;
3288         case TRANS_DDI_BPC_8:
3289                 pipe_config->pipe_bpp = 24;
3290                 break;
3291         case TRANS_DDI_BPC_10:
3292                 pipe_config->pipe_bpp = 30;
3293                 break;
3294         case TRANS_DDI_BPC_12:
3295                 pipe_config->pipe_bpp = 36;
3296                 break;
3297         default:
3298                 break;
3299         }
3300
3301         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3302         case TRANS_DDI_MODE_SELECT_HDMI:
3303                 pipe_config->has_hdmi_sink = true;
3304                 intel_dig_port = enc_to_dig_port(&encoder->base);
3305
3306                 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
3307                         pipe_config->has_infoframe = true;
3308
3309                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3310                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
3311                         pipe_config->hdmi_scrambling = true;
3312                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3313                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3314                 /* fall through */
3315         case TRANS_DDI_MODE_SELECT_DVI:
3316                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3317                 pipe_config->lane_count = 4;
3318                 break;
3319         case TRANS_DDI_MODE_SELECT_FDI:
3320                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3321                 break;
3322         case TRANS_DDI_MODE_SELECT_DP_SST:
3323                 if (encoder->type == INTEL_OUTPUT_EDP)
3324                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3325                 else
3326                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3327                 pipe_config->lane_count =
3328                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3329                 intel_dp_get_m_n(intel_crtc, pipe_config);
3330                 break;
3331         case TRANS_DDI_MODE_SELECT_DP_MST:
3332                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3333                 pipe_config->lane_count =
3334                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3335                 intel_dp_get_m_n(intel_crtc, pipe_config);
3336                 break;
3337         default:
3338                 break;
3339         }
3340
3341         pipe_config->has_audio =
3342                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3343
3344         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3345             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3346                 /*
3347                  * This is a big fat ugly hack.
3348                  *
3349                  * Some machines in UEFI boot mode provide us a VBT that has 18
3350                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3351                  * unknown we fail to light up. Yet the same BIOS boots up with
3352                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3353                  * max, not what it tells us to use.
3354                  *
3355                  * Note: This will still be broken if the eDP panel is not lit
3356                  * up by the BIOS, and thus we can't get the mode at module
3357                  * load.
3358                  */
3359                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3360                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3361                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3362         }
3363
3364         intel_ddi_clock_get(encoder, pipe_config);
3365
3366         if (IS_GEN9_LP(dev_priv))
3367                 pipe_config->lane_lat_optim_mask =
3368                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3369
3370         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3371 }
3372
3373 static enum intel_output_type
3374 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3375                               struct intel_crtc_state *crtc_state,
3376                               struct drm_connector_state *conn_state)
3377 {
3378         switch (conn_state->connector->connector_type) {
3379         case DRM_MODE_CONNECTOR_HDMIA:
3380                 return INTEL_OUTPUT_HDMI;
3381         case DRM_MODE_CONNECTOR_eDP:
3382                 return INTEL_OUTPUT_EDP;
3383         case DRM_MODE_CONNECTOR_DisplayPort:
3384                 return INTEL_OUTPUT_DP;
3385         default:
3386                 MISSING_CASE(conn_state->connector->connector_type);
3387                 return INTEL_OUTPUT_UNUSED;
3388         }
3389 }
3390
3391 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3392                                      struct intel_crtc_state *pipe_config,
3393                                      struct drm_connector_state *conn_state)
3394 {
3395         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3396         enum port port = encoder->port;
3397         int ret;
3398
3399         if (port == PORT_A)
3400                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3401
3402         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3403                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3404         else
3405                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3406
3407         if (IS_GEN9_LP(dev_priv) && ret)
3408                 pipe_config->lane_lat_optim_mask =
3409                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3410
3411         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3412
3413         return ret;
3414
3415 }
3416
3417 static const struct drm_encoder_funcs intel_ddi_funcs = {
3418         .reset = intel_dp_encoder_reset,
3419         .destroy = intel_dp_encoder_destroy,
3420 };
3421
3422 static struct intel_connector *
3423 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3424 {
3425         struct intel_connector *connector;
3426         enum port port = intel_dig_port->base.port;
3427
3428         connector = intel_connector_alloc();
3429         if (!connector)
3430                 return NULL;
3431
3432         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3433         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3434                 kfree(connector);
3435                 return NULL;
3436         }
3437
3438         return connector;
3439 }
3440
3441 static int modeset_pipe(struct drm_crtc *crtc,
3442                         struct drm_modeset_acquire_ctx *ctx)
3443 {
3444         struct drm_atomic_state *state;
3445         struct drm_crtc_state *crtc_state;
3446         int ret;
3447
3448         state = drm_atomic_state_alloc(crtc->dev);
3449         if (!state)
3450                 return -ENOMEM;
3451
3452         state->acquire_ctx = ctx;
3453
3454         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3455         if (IS_ERR(crtc_state)) {
3456                 ret = PTR_ERR(crtc_state);
3457                 goto out;
3458         }
3459
3460         crtc_state->mode_changed = true;
3461
3462         ret = drm_atomic_add_affected_connectors(state, crtc);
3463         if (ret)
3464                 goto out;
3465
3466         ret = drm_atomic_add_affected_planes(state, crtc);
3467         if (ret)
3468                 goto out;
3469
3470         ret = drm_atomic_commit(state);
3471         if (ret)
3472                 goto out;
3473
3474         return 0;
3475
3476  out:
3477         drm_atomic_state_put(state);
3478
3479         return ret;
3480 }
3481
3482 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3483                                  struct drm_modeset_acquire_ctx *ctx)
3484 {
3485         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3486         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3487         struct intel_connector *connector = hdmi->attached_connector;
3488         struct i2c_adapter *adapter =
3489                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3490         struct drm_connector_state *conn_state;
3491         struct intel_crtc_state *crtc_state;
3492         struct intel_crtc *crtc;
3493         u8 config;
3494         int ret;
3495
3496         if (!connector || connector->base.status != connector_status_connected)
3497                 return 0;
3498
3499         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3500                                ctx);
3501         if (ret)
3502                 return ret;
3503
3504         conn_state = connector->base.state;
3505
3506         crtc = to_intel_crtc(conn_state->crtc);
3507         if (!crtc)
3508                 return 0;
3509
3510         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3511         if (ret)
3512                 return ret;
3513
3514         crtc_state = to_intel_crtc_state(crtc->base.state);
3515
3516         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3517
3518         if (!crtc_state->base.active)
3519                 return 0;
3520
3521         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3522             !crtc_state->hdmi_scrambling)
3523                 return 0;
3524
3525         if (conn_state->commit &&
3526             !try_wait_for_completion(&conn_state->commit->hw_done))
3527                 return 0;
3528
3529         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3530         if (ret < 0) {
3531                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3532                 return 0;
3533         }
3534
3535         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3536             crtc_state->hdmi_high_tmds_clock_ratio &&
3537             !!(config & SCDC_SCRAMBLING_ENABLE) ==
3538             crtc_state->hdmi_scrambling)
3539                 return 0;
3540
3541         /*
3542          * HDMI 2.0 says that one should not send scrambled data
3543          * prior to configuring the sink scrambling, and that
3544          * TMDS clock/data transmission should be suspended when
3545          * changing the TMDS clock rate in the sink. So let's
3546          * just do a full modeset here, even though some sinks
3547          * would be perfectly happy if were to just reconfigure
3548          * the SCDC settings on the fly.
3549          */
3550         return modeset_pipe(&crtc->base, ctx);
3551 }
3552
3553 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3554                               struct intel_connector *connector)
3555 {
3556         struct drm_modeset_acquire_ctx ctx;
3557         bool changed;
3558         int ret;
3559
3560         changed = intel_encoder_hotplug(encoder, connector);
3561
3562         drm_modeset_acquire_init(&ctx, 0);
3563
3564         for (;;) {
3565                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3566                         ret = intel_hdmi_reset_link(encoder, &ctx);
3567                 else
3568                         ret = intel_dp_retrain_link(encoder, &ctx);
3569
3570                 if (ret == -EDEADLK) {
3571                         drm_modeset_backoff(&ctx);
3572                         continue;
3573                 }
3574
3575                 break;
3576         }
3577
3578         drm_modeset_drop_locks(&ctx);
3579         drm_modeset_acquire_fini(&ctx);
3580         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3581
3582         return changed;
3583 }
3584
3585 static struct intel_connector *
3586 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3587 {
3588         struct intel_connector *connector;
3589         enum port port = intel_dig_port->base.port;
3590
3591         connector = intel_connector_alloc();
3592         if (!connector)
3593                 return NULL;
3594
3595         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3596         intel_hdmi_init_connector(intel_dig_port, connector);
3597
3598         return connector;
3599 }
3600
3601 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
3602 {
3603         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
3604
3605         if (dport->base.port != PORT_A)
3606                 return false;
3607
3608         if (dport->saved_port_bits & DDI_A_4_LANES)
3609                 return false;
3610
3611         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
3612          *                     supported configuration
3613          */
3614         if (IS_GEN9_LP(dev_priv))
3615                 return true;
3616
3617         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
3618          *             one who does also have a full A/E split called
3619          *             DDI_F what makes DDI_E useless. However for this
3620          *             case let's trust VBT info.
3621          */
3622         if (IS_CANNONLAKE(dev_priv) &&
3623             !intel_bios_is_port_present(dev_priv, PORT_E))
3624                 return true;
3625
3626         return false;
3627 }
3628
3629 static int
3630 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
3631 {
3632         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
3633         enum port port = intel_dport->base.port;
3634         int max_lanes = 4;
3635
3636         if (INTEL_GEN(dev_priv) >= 11)
3637                 return max_lanes;
3638
3639         if (port == PORT_A || port == PORT_E) {
3640                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3641                         max_lanes = port == PORT_A ? 4 : 0;
3642                 else
3643                         /* Both A and E share 2 lanes */
3644                         max_lanes = 2;
3645         }
3646
3647         /*
3648          * Some BIOS might fail to set this bit on port A if eDP
3649          * wasn't lit up at boot.  Force this bit set when needed
3650          * so we use the proper lane count for our calculations.
3651          */
3652         if (intel_ddi_a_force_4_lanes(intel_dport)) {
3653                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3654                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3655                 max_lanes = 4;
3656         }
3657
3658         return max_lanes;
3659 }
3660
3661 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
3662 {
3663         struct intel_digital_port *intel_dig_port;
3664         struct intel_encoder *intel_encoder;
3665         struct drm_encoder *encoder;
3666         bool init_hdmi, init_dp, init_lspcon = false;
3667
3668
3669         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3670                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3671         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3672
3673         if (intel_bios_is_lspcon_present(dev_priv, port)) {
3674                 /*
3675                  * Lspcon device needs to be driven with DP connector
3676                  * with special detection sequence. So make sure DP
3677                  * is initialized before lspcon.
3678                  */
3679                 init_dp = true;
3680                 init_lspcon = true;
3681                 init_hdmi = false;
3682                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3683         }
3684
3685         if (!init_dp && !init_hdmi) {
3686                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3687                               port_name(port));
3688                 return;
3689         }
3690
3691         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3692         if (!intel_dig_port)
3693                 return;
3694
3695         intel_encoder = &intel_dig_port->base;
3696         encoder = &intel_encoder->base;
3697
3698         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
3699                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
3700
3701         intel_encoder->hotplug = intel_ddi_hotplug;
3702         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
3703         intel_encoder->compute_config = intel_ddi_compute_config;
3704         intel_encoder->enable = intel_enable_ddi;
3705         if (IS_GEN9_LP(dev_priv))
3706                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
3707         intel_encoder->pre_enable = intel_ddi_pre_enable;
3708         intel_encoder->disable = intel_disable_ddi;
3709         intel_encoder->post_disable = intel_ddi_post_disable;
3710         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3711         intel_encoder->get_config = intel_ddi_get_config;
3712         intel_encoder->suspend = intel_dp_encoder_suspend;
3713         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3714         intel_encoder->type = INTEL_OUTPUT_DDI;
3715         intel_encoder->power_domain = intel_port_to_power_domain(port);
3716         intel_encoder->port = port;
3717         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3718         intel_encoder->cloneable = 0;
3719
3720         if (INTEL_GEN(dev_priv) >= 11)
3721                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3722                         DDI_BUF_PORT_REVERSAL;
3723         else
3724                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3725                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3726         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3727         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
3728
3729         switch (port) {
3730         case PORT_A:
3731                 intel_dig_port->ddi_io_power_domain =
3732                         POWER_DOMAIN_PORT_DDI_A_IO;
3733                 break;
3734         case PORT_B:
3735                 intel_dig_port->ddi_io_power_domain =
3736                         POWER_DOMAIN_PORT_DDI_B_IO;
3737                 break;
3738         case PORT_C:
3739                 intel_dig_port->ddi_io_power_domain =
3740                         POWER_DOMAIN_PORT_DDI_C_IO;
3741                 break;
3742         case PORT_D:
3743                 intel_dig_port->ddi_io_power_domain =
3744                         POWER_DOMAIN_PORT_DDI_D_IO;
3745                 break;
3746         case PORT_E:
3747                 intel_dig_port->ddi_io_power_domain =
3748                         POWER_DOMAIN_PORT_DDI_E_IO;
3749                 break;
3750         case PORT_F:
3751                 intel_dig_port->ddi_io_power_domain =
3752                         POWER_DOMAIN_PORT_DDI_F_IO;
3753                 break;
3754         default:
3755                 MISSING_CASE(port);
3756         }
3757
3758         intel_infoframe_init(intel_dig_port);
3759
3760         if (init_dp) {
3761                 if (!intel_ddi_init_dp_connector(intel_dig_port))
3762                         goto err;
3763
3764                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3765         }
3766
3767         /* In theory we don't need the encoder->type check, but leave it just in
3768          * case we have some really bad VBTs... */
3769         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3770                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3771                         goto err;
3772         }
3773
3774         if (init_lspcon) {
3775                 if (lspcon_init(intel_dig_port))
3776                         /* TODO: handle hdmi info frame part */
3777                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3778                                 port_name(port));
3779                 else
3780                         /*
3781                          * LSPCON init faied, but DP init was success, so
3782                          * lets try to drive as DP++ port.
3783                          */
3784                         DRM_ERROR("LSPCON init failed on port %c\n",
3785                                 port_name(port));
3786         }
3787
3788         return;
3789
3790 err:
3791         drm_encoder_cleanup(encoder);
3792         kfree(intel_dig_port);
3793 }