drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "intel_dsi.h"
  32
  33 struct ddi_buf_trans {
  34         u32 trans1;     /* balance leg enable, de-emph level */
  35         u32 trans2;     /* vref sel, vswing */
  36         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  37 };
  38
  39 static const u8 index_to_dp_signal_levels[] = {
  40         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  41         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  42         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  43         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  44         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  45         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  46         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  47         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  48         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  49         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  50 };
  51
  52 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  53  * them for both DP and FDI transports, allowing those ports to
  54  * automatically adapt to HDMI connections as well
  55  */
  56 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  57         { 0x00FFFFFF, 0x0006000E, 0x0 },
  58         { 0x00D75FFF, 0x0005000A, 0x0 },
  59         { 0x00C30FFF, 0x00040006, 0x0 },
  60         { 0x80AAAFFF, 0x000B0000, 0x0 },
  61         { 0x00FFFFFF, 0x0005000A, 0x0 },
  62         { 0x00D75FFF, 0x000C0004, 0x0 },
  63         { 0x80C30FFF, 0x000B0000, 0x0 },
  64         { 0x00FFFFFF, 0x00040006, 0x0 },
  65         { 0x80D75FFF, 0x000B0000, 0x0 },
  66 };
  67
  68 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  69         { 0x00FFFFFF, 0x0007000E, 0x0 },
  70         { 0x00D75FFF, 0x000F000A, 0x0 },
  71         { 0x00C30FFF, 0x00060006, 0x0 },
  72         { 0x00AAAFFF, 0x001E0000, 0x0 },
  73         { 0x00FFFFFF, 0x000F000A, 0x0 },
  74         { 0x00D75FFF, 0x00160004, 0x0 },
  75         { 0x00C30FFF, 0x001E0000, 0x0 },
  76         { 0x00FFFFFF, 0x00060006, 0x0 },
  77         { 0x00D75FFF, 0x001E0000, 0x0 },
  78 };
  79
  80 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  81                                         /* Idx  NT mV d T mV d  db      */
  82         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  83         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  84         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  85         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  86         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  87         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  88         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  89         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  90         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  91         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  92         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  93         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  94 };
  95
  96 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  97         { 0x00FFFFFF, 0x00000012, 0x0 },
  98         { 0x00EBAFFF, 0x00020011, 0x0 },
  99         { 0x00C71FFF, 0x0006000F, 0x0 },
 100         { 0x00AAAFFF, 0x000E000A, 0x0 },
 101         { 0x00FFFFFF, 0x00020011, 0x0 },
 102         { 0x00DB6FFF, 0x0005000F, 0x0 },
 103         { 0x00BEEFFF, 0x000A000C, 0x0 },
 104         { 0x00FFFFFF, 0x0005000F, 0x0 },
 105         { 0x00DB6FFF, 0x000A000C, 0x0 },
 106 };
 107
 108 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 109         { 0x00FFFFFF, 0x0007000E, 0x0 },
 110         { 0x00D75FFF, 0x000E000A, 0x0 },
 111         { 0x00BEFFFF, 0x00140006, 0x0 },
 112         { 0x80B2CFFF, 0x001B0002, 0x0 },
 113         { 0x00FFFFFF, 0x000E000A, 0x0 },
 114         { 0x00DB6FFF, 0x00160005, 0x0 },
 115         { 0x80C71FFF, 0x001A0002, 0x0 },
 116         { 0x00F7DFFF, 0x00180004, 0x0 },
 117         { 0x80D75FFF, 0x001B0002, 0x0 },
 118 };
 119
 120 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 121         { 0x00FFFFFF, 0x0001000E, 0x0 },
 122         { 0x00D75FFF, 0x0004000A, 0x0 },
 123         { 0x00C30FFF, 0x00070006, 0x0 },
 124         { 0x00AAAFFF, 0x000C0000, 0x0 },
 125         { 0x00FFFFFF, 0x0004000A, 0x0 },
 126         { 0x00D75FFF, 0x00090004, 0x0 },
 127         { 0x00C30FFF, 0x000C0000, 0x0 },
 128         { 0x00FFFFFF, 0x00070006, 0x0 },
 129         { 0x00D75FFF, 0x000C0000, 0x0 },
 130 };
 131
 132 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 133                                         /* Idx  NT mV d T mV df db      */
 134         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 135         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 136         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 137         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 138         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 139         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 140         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 141         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 142         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 143         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 144 };
 145
 146 /* Skylake H and S */
 147 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 148         { 0x00002016, 0x000000A0, 0x0 },
 149         { 0x00005012, 0x0000009B, 0x0 },
 150         { 0x00007011, 0x00000088, 0x0 },
 151         { 0x80009010, 0x000000C0, 0x1 },
 152         { 0x00002016, 0x0000009B, 0x0 },
 153         { 0x00005012, 0x00000088, 0x0 },
 154         { 0x80007011, 0x000000C0, 0x1 },
 155         { 0x00002016, 0x000000DF, 0x0 },
 156         { 0x80005012, 0x000000C0, 0x1 },
 157 };
 158
 159 /* Skylake U */
 160 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 161         { 0x0000201B, 0x000000A2, 0x0 },
 162         { 0x00005012, 0x00000088, 0x0 },
 163         { 0x80007011, 0x000000CD, 0x1 },
 164         { 0x80009010, 0x000000C0, 0x1 },
 165         { 0x0000201B, 0x0000009D, 0x0 },
 166         { 0x80005012, 0x000000C0, 0x1 },
 167         { 0x80007011, 0x000000C0, 0x1 },
 168         { 0x00002016, 0x00000088, 0x0 },
 169         { 0x80005012, 0x000000C0, 0x1 },
 170 };
 171
 172 /* Skylake Y */
 173 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 174         { 0x00000018, 0x000000A2, 0x0 },
 175         { 0x00005012, 0x00000088, 0x0 },
 176         { 0x80007011, 0x000000CD, 0x3 },
 177         { 0x80009010, 0x000000C0, 0x3 },
 178         { 0x00000018, 0x0000009D, 0x0 },
 179         { 0x80005012, 0x000000C0, 0x3 },
 180         { 0x80007011, 0x000000C0, 0x3 },
 181         { 0x00000018, 0x00000088, 0x0 },
 182         { 0x80005012, 0x000000C0, 0x3 },
 183 };
 184
 185 /* Kabylake H and S */
 186 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 187         { 0x00002016, 0x000000A0, 0x0 },
 188         { 0x00005012, 0x0000009B, 0x0 },
 189         { 0x00007011, 0x00000088, 0x0 },
 190         { 0x80009010, 0x000000C0, 0x1 },
 191         { 0x00002016, 0x0000009B, 0x0 },
 192         { 0x00005012, 0x00000088, 0x0 },
 193         { 0x80007011, 0x000000C0, 0x1 },
 194         { 0x00002016, 0x00000097, 0x0 },
 195         { 0x80005012, 0x000000C0, 0x1 },
 196 };
 197
 198 /* Kabylake U */
 199 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 200         { 0x0000201B, 0x000000A1, 0x0 },
 201         { 0x00005012, 0x00000088, 0x0 },
 202         { 0x80007011, 0x000000CD, 0x3 },
 203         { 0x80009010, 0x000000C0, 0x3 },
 204         { 0x0000201B, 0x0000009D, 0x0 },
 205         { 0x80005012, 0x000000C0, 0x3 },
 206         { 0x80007011, 0x000000C0, 0x3 },
 207         { 0x00002016, 0x0000004F, 0x0 },
 208         { 0x80005012, 0x000000C0, 0x3 },
 209 };
 210
 211 /* Kabylake Y */
 212 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 213         { 0x00001017, 0x000000A1, 0x0 },
 214         { 0x00005012, 0x00000088, 0x0 },
 215         { 0x80007011, 0x000000CD, 0x3 },
 216         { 0x8000800F, 0x000000C0, 0x3 },
 217         { 0x00001017, 0x0000009D, 0x0 },
 218         { 0x80005012, 0x000000C0, 0x3 },
 219         { 0x80007011, 0x000000C0, 0x3 },
 220         { 0x00001017, 0x0000004C, 0x0 },
 221         { 0x80005012, 0x000000C0, 0x3 },
 222 };
 223
 224 /*
 225  * Skylake/Kabylake H and S
 226  * eDP 1.4 low vswing translation parameters
 227  */
 228 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 229         { 0x00000018, 0x000000A8, 0x0 },
 230         { 0x00004013, 0x000000A9, 0x0 },
 231         { 0x00007011, 0x000000A2, 0x0 },
 232         { 0x00009010, 0x0000009C, 0x0 },
 233         { 0x00000018, 0x000000A9, 0x0 },
 234         { 0x00006013, 0x000000A2, 0x0 },
 235         { 0x00007011, 0x000000A6, 0x0 },
 236         { 0x00000018, 0x000000AB, 0x0 },
 237         { 0x00007013, 0x0000009F, 0x0 },
 238         { 0x00000018, 0x000000DF, 0x0 },
 239 };
 240
 241 /*
 242  * Skylake/Kabylake U
 243  * eDP 1.4 low vswing translation parameters
 244  */
 245 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 246         { 0x00000018, 0x000000A8, 0x0 },
 247         { 0x00004013, 0x000000A9, 0x0 },
 248         { 0x00007011, 0x000000A2, 0x0 },
 249         { 0x00009010, 0x0000009C, 0x0 },
 250         { 0x00000018, 0x000000A9, 0x0 },
 251         { 0x00006013, 0x000000A2, 0x0 },
 252         { 0x00007011, 0x000000A6, 0x0 },
 253         { 0x00002016, 0x000000AB, 0x0 },
 254         { 0x00005013, 0x0000009F, 0x0 },
 255         { 0x00000018, 0x000000DF, 0x0 },
 256 };
 257
 258 /*
 259  * Skylake/Kabylake Y
 260  * eDP 1.4 low vswing translation parameters
 261  */
 262 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 263         { 0x00000018, 0x000000A8, 0x0 },
 264         { 0x00004013, 0x000000AB, 0x0 },
 265         { 0x00007011, 0x000000A4, 0x0 },
 266         { 0x00009010, 0x000000DF, 0x0 },
 267         { 0x00000018, 0x000000AA, 0x0 },
 268         { 0x00006013, 0x000000A4, 0x0 },
 269         { 0x00007011, 0x0000009D, 0x0 },
 270         { 0x00000018, 0x000000A0, 0x0 },
 271         { 0x00006012, 0x000000DF, 0x0 },
 272         { 0x00000018, 0x0000008A, 0x0 },
 273 };
 274
 275 /* Skylake/Kabylake U, H and S */
 276 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 277         { 0x00000018, 0x000000AC, 0x0 },
 278         { 0x00005012, 0x0000009D, 0x0 },
 279         { 0x00007011, 0x00000088, 0x0 },
 280         { 0x00000018, 0x000000A1, 0x0 },
 281         { 0x00000018, 0x00000098, 0x0 },
 282         { 0x00004013, 0x00000088, 0x0 },
 283         { 0x80006012, 0x000000CD, 0x1 },
 284         { 0x00000018, 0x000000DF, 0x0 },
 285         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 286         { 0x80003015, 0x000000C0, 0x1 },
 287         { 0x80000018, 0x000000C0, 0x1 },
 288 };
 289
 290 /* Skylake/Kabylake Y */
 291 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 292         { 0x00000018, 0x000000A1, 0x0 },
 293         { 0x00005012, 0x000000DF, 0x0 },
 294         { 0x80007011, 0x000000CB, 0x3 },
 295         { 0x00000018, 0x000000A4, 0x0 },
 296         { 0x00000018, 0x0000009D, 0x0 },
 297         { 0x00004013, 0x00000080, 0x0 },
 298         { 0x80006013, 0x000000C0, 0x3 },
 299         { 0x00000018, 0x0000008A, 0x0 },
 300         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 301         { 0x80003015, 0x000000C0, 0x3 },
 302         { 0x80000018, 0x000000C0, 0x3 },
 303 };
 304
 305 struct bxt_ddi_buf_trans {
 306         u8 margin;      /* swing value */
 307         u8 scale;       /* scale value */
 308         u8 enable;      /* scale enable */
 309         u8 deemphasis;
 310 };
 311
 312 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 313                                         /* Idx  NT mV diff      db  */
 314         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 315         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 316         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 317         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 318         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 319         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 320         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 321         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 322         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 323         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 324 };
 325
 326 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 327                                         /* Idx  NT mV diff      db  */
 328         { 26, 0, 0, 128, },     /* 0:   200             0   */
 329         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 330         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 331         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 332         { 32, 0, 0, 128, },     /* 4:   250             0   */
 333         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 334         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 335         { 43, 0, 0, 128, },     /* 7:   300             0   */
 336         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 337         { 48, 0, 0, 128, },     /* 9:   300             0   */
 338 };
 339
 340 /* BSpec has 2 recommended values - entries 0 and 8.
 341  * Using the entry with higher vswing.
 342  */
 343 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 344                                         /* Idx  NT mV diff      db  */
 345         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 346         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 347         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 348         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 349         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 350         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 351         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 352         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 353         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 354         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 355 };
 356
 357 struct cnl_ddi_buf_trans {
 358         u8 dw2_swing_sel;
 359         u8 dw7_n_scalar;
 360         u8 dw4_cursor_coeff;
 361         u8 dw4_post_cursor_2;
 362         u8 dw4_post_cursor_1;
 363 };
 364
 365 /* Voltage Swing Programming for VccIO 0.85V for DP */
 366 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 367                                                 /* NT mV Trans mV db    */
 368         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 369         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 370         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 371         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 372         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 373         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 374         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 375         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 376         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 377         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 378 };
 379
 380 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 381 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 382                                                 /* NT mV Trans mV db    */
 383         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 384         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 385         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 386         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 387         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 388         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 389         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 390 };
 391
 392 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 393 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 394                                                 /* NT mV Trans mV db    */
 395         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 396         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 397         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 398         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 399         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 400         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 401         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 402         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 403         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 404 };
 405
 406 /* Voltage Swing Programming for VccIO 0.95V for DP */
 407 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 408                                                 /* NT mV Trans mV db    */
 409         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 410         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 411         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 412         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 413         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 414         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 415         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 416         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 417         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 418         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 419 };
 420
 421 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 422 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 423                                                 /* NT mV Trans mV db    */
 424         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 425         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 426         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 427         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 428         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 429         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 430         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 431         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 432         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 433         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 434         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 435 };
 436
 437 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 438 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 439                                                 /* NT mV Trans mV db    */
 440         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 441         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 442         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 443         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 444         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 445         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 446         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 447         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 448         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 449         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 450 };
 451
 452 /* Voltage Swing Programming for VccIO 1.05V for DP */
 453 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 454                                                 /* NT mV Trans mV db    */
 455         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 456         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 457         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 458         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 459         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 460         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 461         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 462         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 463         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 464         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 465 };
 466
 467 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 468 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 469                                                 /* NT mV Trans mV db    */
 470         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 471         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 472         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 473         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 474         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 475         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 476         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 477         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 478         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 479         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 480         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 481 };
 482
 483 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 484 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 485                                                 /* NT mV Trans mV db    */
 486         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 487         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 488         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 489         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 490         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 491         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 492         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 493         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 494         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 495 };
 496
 497 /* icl_combo_phy_ddi_translations */
 498 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 499                                                 /* NT mV Trans mV db    */
 500         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 501         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 502         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 503         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 504         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 505         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 506         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 507         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 508         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 509         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 510 };
 511
 512 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 513                                                 /* NT mV Trans mV db    */
 514         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 515         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 516         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 517         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 518         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 519         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 520         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 521         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 522         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 523         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 524 };
 525
 526 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 527                                                 /* NT mV Trans mV db    */
 528         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 529         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 530         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 531         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 532         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 533         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 534         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 535         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 536         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 537         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 538 };
 539
 540 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 541                                                 /* NT mV Trans mV db    */
 542         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 543         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 544         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 545         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 546         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 547         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 548         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 549 };
 550
 551 struct icl_mg_phy_ddi_buf_trans {
 552         u32 cri_txdeemph_override_5_0;
 553         u32 cri_txdeemph_override_11_6;
 554         u32 cri_txdeemph_override_17_12;
 555 };
 556
 557 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 558                                 /* Voltage swing  pre-emphasis */
 559         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 560         { 0x0, 0x23, 0x08 },    /* 0              1   */
 561         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 562         { 0x0, 0x00, 0x00 },    /* 0              3   */
 563         { 0x0, 0x23, 0x00 },    /* 1              0   */
 564         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 565         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 566         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 567         { 0x0, 0x33, 0x0C },    /* 2              1   */
 568         { 0x0, 0x00, 0x00 },    /* 3              0   */
 569 };
 570
 571 static const struct ddi_buf_trans *
 572 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 573 {
 574         if (dev_priv->vbt.edp.low_vswing) {
 575                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 576                 return bdw_ddi_translations_edp;
 577         } else {
 578                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 579                 return bdw_ddi_translations_dp;
 580         }
 581 }
 582
 583 static const struct ddi_buf_trans *
 584 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 585 {
 586         if (IS_SKL_ULX(dev_priv)) {
 587                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 588                 return skl_y_ddi_translations_dp;
 589         } else if (IS_SKL_ULT(dev_priv)) {
 590                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 591                 return skl_u_ddi_translations_dp;
 592         } else {
 593                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 594                 return skl_ddi_translations_dp;
 595         }
 596 }
 597
 598 static const struct ddi_buf_trans *
 599 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 600 {
 601         if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 602                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 603                 return kbl_y_ddi_translations_dp;
 604         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 605                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 606                 return kbl_u_ddi_translations_dp;
 607         } else {
 608                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 609                 return kbl_ddi_translations_dp;
 610         }
 611 }
 612
 613 static const struct ddi_buf_trans *
 614 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 615 {
 616         if (dev_priv->vbt.edp.low_vswing) {
 617                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 618                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 619                         return skl_y_ddi_translations_edp;
 620                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 621                            IS_CFL_ULT(dev_priv)) {
 622                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 623                         return skl_u_ddi_translations_edp;
 624                 } else {
 625                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 626                         return skl_ddi_translations_edp;
 627                 }
 628         }
 629
 630         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 631                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 632         else
 633                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 634 }
 635
 636 static const struct ddi_buf_trans *
 637 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 638 {
 639         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 640                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 641                 return skl_y_ddi_translations_hdmi;
 642         } else {
 643                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 644                 return skl_ddi_translations_hdmi;
 645         }
 646 }
 647
 648 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 649 {
 650         /* Only DDIA and DDIE can select the 10th register with DP */
 651         if (port == PORT_A || port == PORT_E)
 652                 return min(n_entries, 10);
 653         else
 654                 return min(n_entries, 9);
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 659                            enum port port, int *n_entries)
 660 {
 661         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 662                 const struct ddi_buf_trans *ddi_translations =
 663                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 664                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 665                 return ddi_translations;
 666         } else if (IS_SKYLAKE(dev_priv)) {
 667                 const struct ddi_buf_trans *ddi_translations =
 668                         skl_get_buf_trans_dp(dev_priv, n_entries);
 669                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 670                 return ddi_translations;
 671         } else if (IS_BROADWELL(dev_priv)) {
 672                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 673                 return  bdw_ddi_translations_dp;
 674         } else if (IS_HASWELL(dev_priv)) {
 675                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 676                 return hsw_ddi_translations_dp;
 677         }
 678
 679         *n_entries = 0;
 680         return NULL;
 681 }
 682
 683 static const struct ddi_buf_trans *
 684 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 685                             enum port port, int *n_entries)
 686 {
 687         if (IS_GEN9_BC(dev_priv)) {
 688                 const struct ddi_buf_trans *ddi_translations =
 689                         skl_get_buf_trans_edp(dev_priv, n_entries);
 690                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 691                 return ddi_translations;
 692         } else if (IS_BROADWELL(dev_priv)) {
 693                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 694         } else if (IS_HASWELL(dev_priv)) {
 695                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 696                 return hsw_ddi_translations_dp;
 697         }
 698
 699         *n_entries = 0;
 700         return NULL;
 701 }
 702
 703 static const struct ddi_buf_trans *
 704 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 705                             int *n_entries)
 706 {
 707         if (IS_BROADWELL(dev_priv)) {
 708                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 709                 return bdw_ddi_translations_fdi;
 710         } else if (IS_HASWELL(dev_priv)) {
 711                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 712                 return hsw_ddi_translations_fdi;
 713         }
 714
 715         *n_entries = 0;
 716         return NULL;
 717 }
 718
 719 static const struct ddi_buf_trans *
 720 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 721                              int *n_entries)
 722 {
 723         if (IS_GEN9_BC(dev_priv)) {
 724                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 725         } else if (IS_BROADWELL(dev_priv)) {
 726                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 727                 return bdw_ddi_translations_hdmi;
 728         } else if (IS_HASWELL(dev_priv)) {
 729                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 730                 return hsw_ddi_translations_hdmi;
 731         }
 732
 733         *n_entries = 0;
 734         return NULL;
 735 }
 736
 737 static const struct bxt_ddi_buf_trans *
 738 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 739 {
 740         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 741         return bxt_ddi_translations_dp;
 742 }
 743
 744 static const struct bxt_ddi_buf_trans *
 745 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 746 {
 747         if (dev_priv->vbt.edp.low_vswing) {
 748                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 749                 return bxt_ddi_translations_edp;
 750         }
 751
 752         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 753 }
 754
 755 static const struct bxt_ddi_buf_trans *
 756 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 757 {
 758         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 759         return bxt_ddi_translations_hdmi;
 760 }
 761
 762 static const struct cnl_ddi_buf_trans *
 763 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 764 {
 765         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 766
 767         if (voltage == VOLTAGE_INFO_0_85V) {
 768                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 769                 return cnl_ddi_translations_hdmi_0_85V;
 770         } else if (voltage == VOLTAGE_INFO_0_95V) {
 771                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 772                 return cnl_ddi_translations_hdmi_0_95V;
 773         } else if (voltage == VOLTAGE_INFO_1_05V) {
 774                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 775                 return cnl_ddi_translations_hdmi_1_05V;
 776         } else {
 777                 *n_entries = 1; /* shut up gcc */
 778                 MISSING_CASE(voltage);
 779         }
 780         return NULL;
 781 }
 782
 783 static const struct cnl_ddi_buf_trans *
 784 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 785 {
 786         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 787
 788         if (voltage == VOLTAGE_INFO_0_85V) {
 789                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 790                 return cnl_ddi_translations_dp_0_85V;
 791         } else if (voltage == VOLTAGE_INFO_0_95V) {
 792                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 793                 return cnl_ddi_translations_dp_0_95V;
 794         } else if (voltage == VOLTAGE_INFO_1_05V) {
 795                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 796                 return cnl_ddi_translations_dp_1_05V;
 797         } else {
 798                 *n_entries = 1; /* shut up gcc */
 799                 MISSING_CASE(voltage);
 800         }
 801         return NULL;
 802 }
 803
 804 static const struct cnl_ddi_buf_trans *
 805 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 806 {
 807         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 808
 809         if (dev_priv->vbt.edp.low_vswing) {
 810                 if (voltage == VOLTAGE_INFO_0_85V) {
 811                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 812                         return cnl_ddi_translations_edp_0_85V;
 813                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 814                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 815                         return cnl_ddi_translations_edp_0_95V;
 816                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 817                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 818                         return cnl_ddi_translations_edp_1_05V;
 819                 } else {
 820                         *n_entries = 1; /* shut up gcc */
 821                         MISSING_CASE(voltage);
 822                 }
 823                 return NULL;
 824         } else {
 825                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 826         }
 827 }
 828
 829 static const struct cnl_ddi_buf_trans *
 830 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 831                         int type, int rate, int *n_entries)
 832 {
 833         if (type == INTEL_OUTPUT_HDMI) {
 834                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 835                 return icl_combo_phy_ddi_translations_hdmi;
 836         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 837                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 838                 return icl_combo_phy_ddi_translations_edp_hbr3;
 839         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 840                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 841                 return icl_combo_phy_ddi_translations_edp_hbr2;
 842         }
 843
 844         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 845         return icl_combo_phy_ddi_translations_dp_hbr2;
 846 }
 847
 848 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 849 {
 850         int n_entries, level, default_entry;
 851
 852         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 853
 854         if (INTEL_GEN(dev_priv) >= 11) {
 855                 if (intel_port_is_combophy(dev_priv, port))
 856                         icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
 857                                                 0, &n_entries);
 858                 else
 859                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 860                 default_entry = n_entries - 1;
 861         } else if (IS_CANNONLAKE(dev_priv)) {
 862                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 863                 default_entry = n_entries - 1;
 864         } else if (IS_GEN9_LP(dev_priv)) {
 865                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 866                 default_entry = n_entries - 1;
 867         } else if (IS_GEN9_BC(dev_priv)) {
 868                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 869                 default_entry = 8;
 870         } else if (IS_BROADWELL(dev_priv)) {
 871                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 872                 default_entry = 7;
 873         } else if (IS_HASWELL(dev_priv)) {
 874                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 875                 default_entry = 6;
 876         } else {
 877                 WARN(1, "ddi translation table missing\n");
 878                 return 0;
 879         }
 880
 881         /* Choose a good default if VBT is badly populated */
 882         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 883                 level = default_entry;
 884
 885         if (WARN_ON_ONCE(n_entries == 0))
 886                 return 0;
 887         if (WARN_ON_ONCE(level >= n_entries))
 888                 level = n_entries - 1;
 889
 890         return level;
 891 }
 892
 893 /*
 894  * Starting with Haswell, DDI port buffers must be programmed with correct
 895  * values in advance. This function programs the correct values for
 896  * DP/eDP/FDI use cases.
 897  */
 898 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 899                                          const struct intel_crtc_state *crtc_state)
 900 {
 901         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 902         u32 iboost_bit = 0;
 903         int i, n_entries;
 904         enum port port = encoder->port;
 905         const struct ddi_buf_trans *ddi_translations;
 906
 907         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 908                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 909                                                                &n_entries);
 910         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 911                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 912                                                                &n_entries);
 913         else
 914                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 915                                                               &n_entries);
 916
 917         /* If we're boosting the current, set bit 31 of trans1 */
 918         if (IS_GEN9_BC(dev_priv) &&
 919             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 920                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 921
 922         for (i = 0; i < n_entries; i++) {
 923                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 924                            ddi_translations[i].trans1 | iboost_bit);
 925                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 926                            ddi_translations[i].trans2);
 927         }
 928 }
 929
 930 /*
 931  * Starting with Haswell, DDI port buffers must be programmed with correct
 932  * values in advance. This function programs the correct values for
 933  * HDMI/DVI use cases.
 934  */
 935 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 936                                            int level)
 937 {
 938         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 939         u32 iboost_bit = 0;
 940         int n_entries;
 941         enum port port = encoder->port;
 942         const struct ddi_buf_trans *ddi_translations;
 943
 944         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 945
 946         if (WARN_ON_ONCE(!ddi_translations))
 947                 return;
 948         if (WARN_ON_ONCE(level >= n_entries))
 949                 level = n_entries - 1;
 950
 951         /* If we're boosting the current, set bit 31 of trans1 */
 952         if (IS_GEN9_BC(dev_priv) &&
 953             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 954                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 955
 956         /* Entry 9 is for HDMI: */
 957         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 958                    ddi_translations[level].trans1 | iboost_bit);
 959         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 960                    ddi_translations[level].trans2);
 961 }
 962
 963 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 964                                     enum port port)
 965 {
 966         i915_reg_t reg = DDI_BUF_CTL(port);
 967         int i;
 968
 969         for (i = 0; i < 16; i++) {
 970                 udelay(1);
 971                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 972                         return;
 973         }
 974         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 975 }
 976
 977 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 978 {
 979         switch (pll->info->id) {
 980         case DPLL_ID_WRPLL1:
 981                 return PORT_CLK_SEL_WRPLL1;
 982         case DPLL_ID_WRPLL2:
 983                 return PORT_CLK_SEL_WRPLL2;
 984         case DPLL_ID_SPLL:
 985                 return PORT_CLK_SEL_SPLL;
 986         case DPLL_ID_LCPLL_810:
 987                 return PORT_CLK_SEL_LCPLL_810;
 988         case DPLL_ID_LCPLL_1350:
 989                 return PORT_CLK_SEL_LCPLL_1350;
 990         case DPLL_ID_LCPLL_2700:
 991                 return PORT_CLK_SEL_LCPLL_2700;
 992         default:
 993                 MISSING_CASE(pll->info->id);
 994                 return PORT_CLK_SEL_NONE;
 995         }
 996 }
 997
 998 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 999                                   const struct intel_crtc_state *crtc_state)
1000 {
1001         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1002         int clock = crtc_state->port_clock;
1003         const enum intel_dpll_id id = pll->info->id;
1004
1005         switch (id) {
1006         default:
1007                 /*
1008                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1009                  * here, so do warn if this get passed in
1010                  */
1011                 MISSING_CASE(id);
1012                 return DDI_CLK_SEL_NONE;
1013         case DPLL_ID_ICL_TBTPLL:
1014                 switch (clock) {
1015                 case 162000:
1016                         return DDI_CLK_SEL_TBT_162;
1017                 case 270000:
1018                         return DDI_CLK_SEL_TBT_270;
1019                 case 540000:
1020                         return DDI_CLK_SEL_TBT_540;
1021                 case 810000:
1022                         return DDI_CLK_SEL_TBT_810;
1023                 default:
1024                         MISSING_CASE(clock);
1025                         return DDI_CLK_SEL_NONE;
1026                 }
1027         case DPLL_ID_ICL_MGPLL1:
1028         case DPLL_ID_ICL_MGPLL2:
1029         case DPLL_ID_ICL_MGPLL3:
1030         case DPLL_ID_ICL_MGPLL4:
1031                 return DDI_CLK_SEL_MG;
1032         }
1033 }
1034
1035 /* Starting with Haswell, different DDI ports can work in FDI mode for
1036  * connection to the PCH-located connectors. For this, it is necessary to train
1037  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1038  *
1039  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1040  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1041  * DDI A (which is used for eDP)
1042  */
1043
1044 void hsw_fdi_link_train(struct intel_crtc *crtc,
1045                         const struct intel_crtc_state *crtc_state)
1046 {
1047         struct drm_device *dev = crtc->base.dev;
1048         struct drm_i915_private *dev_priv = to_i915(dev);
1049         struct intel_encoder *encoder;
1050         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1051
1052         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1053                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1054                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1055         }
1056
1057         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1058          * mode set "sequence for CRT port" document:
1059          * - TP1 to TP2 time with the default value
1060          * - FDI delay to 90h
1061          *
1062          * WaFDIAutoLinkSetTimingOverrride:hsw
1063          */
1064         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1065                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1066                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1067
1068         /* Enable the PCH Receiver FDI PLL */
1069         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1070                      FDI_RX_PLL_ENABLE |
1071                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1072         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1073         POSTING_READ(FDI_RX_CTL(PIPE_A));
1074         udelay(220);
1075
1076         /* Switch from Rawclk to PCDclk */
1077         rx_ctl_val |= FDI_PCDCLK;
1078         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1079
1080         /* Configure Port Clock Select */
1081         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1082         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1083         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1084
1085         /* Start the training iterating through available voltages and emphasis,
1086          * testing each value twice. */
1087         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1088                 /* Configure DP_TP_CTL with auto-training */
1089                 I915_WRITE(DP_TP_CTL(PORT_E),
1090                                         DP_TP_CTL_FDI_AUTOTRAIN |
1091                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1092                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1093                                         DP_TP_CTL_ENABLE);
1094
1095                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1096                  * DDI E does not support port reversal, the functionality is
1097                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1098                  * port reversal bit */
1099                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1100                            DDI_BUF_CTL_ENABLE |
1101                            ((crtc_state->fdi_lanes - 1) << 1) |
1102                            DDI_BUF_TRANS_SELECT(i / 2));
1103                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1104
1105                 udelay(600);
1106
1107                 /* Program PCH FDI Receiver TU */
1108                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1109
1110                 /* Enable PCH FDI Receiver with auto-training */
1111                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1112                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1113                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1114
1115                 /* Wait for FDI receiver lane calibration */
1116                 udelay(30);
1117
1118                 /* Unset FDI_RX_MISC pwrdn lanes */
1119                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1120                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1121                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1122                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1123
1124                 /* Wait for FDI auto training time */
1125                 udelay(5);
1126
1127                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1128                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1129                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1130                         break;
1131                 }
1132
1133                 /*
1134                  * Leave things enabled even if we failed to train FDI.
1135                  * Results in less fireworks from the state checker.
1136                  */
1137                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1138                         DRM_ERROR("FDI link training failed!\n");
1139                         break;
1140                 }
1141
1142                 rx_ctl_val &= ~FDI_RX_ENABLE;
1143                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1144                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1145
1146                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1147                 temp &= ~DDI_BUF_CTL_ENABLE;
1148                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1149                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1150
1151                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1152                 temp = I915_READ(DP_TP_CTL(PORT_E));
1153                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1154                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1155                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1156                 POSTING_READ(DP_TP_CTL(PORT_E));
1157
1158                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1159
1160                 /* Reset FDI_RX_MISC pwrdn lanes */
1161                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1162                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1163                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1164                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1165                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1166         }
1167
1168         /* Enable normal pixel sending for FDI */
1169         I915_WRITE(DP_TP_CTL(PORT_E),
1170                    DP_TP_CTL_FDI_AUTOTRAIN |
1171                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1172                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1173                    DP_TP_CTL_ENABLE);
1174 }
1175
1176 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1177 {
1178         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1179         struct intel_digital_port *intel_dig_port =
1180                 enc_to_dig_port(&encoder->base);
1181
1182         intel_dp->DP = intel_dig_port->saved_port_bits |
1183                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1184         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1185 }
1186
1187 static struct intel_encoder *
1188 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1189 {
1190         struct drm_device *dev = crtc->base.dev;
1191         struct intel_encoder *encoder, *ret = NULL;
1192         int num_encoders = 0;
1193
1194         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1195                 ret = encoder;
1196                 num_encoders++;
1197         }
1198
1199         if (num_encoders != 1)
1200                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1201                      pipe_name(crtc->pipe));
1202
1203         BUG_ON(ret == NULL);
1204         return ret;
1205 }
1206
1207 #define LC_FREQ 2700
1208
1209 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1210                                    i915_reg_t reg)
1211 {
1212         int refclk = LC_FREQ;
1213         int n, p, r;
1214         u32 wrpll;
1215
1216         wrpll = I915_READ(reg);
1217         switch (wrpll & WRPLL_PLL_REF_MASK) {
1218         case WRPLL_PLL_SSC:
1219         case WRPLL_PLL_NON_SSC:
1220                 /*
1221                  * We could calculate spread here, but our checking
1222                  * code only cares about 5% accuracy, and spread is a max of
1223                  * 0.5% downspread.
1224                  */
1225                 refclk = 135;
1226                 break;
1227         case WRPLL_PLL_LCPLL:
1228                 refclk = LC_FREQ;
1229                 break;
1230         default:
1231                 WARN(1, "bad wrpll refclk\n");
1232                 return 0;
1233         }
1234
1235         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1236         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1237         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1238
1239         /* Convert to KHz, p & r have a fixed point portion */
1240         return (refclk * n * 100) / (p * r);
1241 }
1242
1243 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1244 {
1245         u32 p0, p1, p2, dco_freq;
1246
1247         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1248         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1249
1250         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1251                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1252         else
1253                 p1 = 1;
1254
1255
1256         switch (p0) {
1257         case DPLL_CFGCR2_PDIV_1:
1258                 p0 = 1;
1259                 break;
1260         case DPLL_CFGCR2_PDIV_2:
1261                 p0 = 2;
1262                 break;
1263         case DPLL_CFGCR2_PDIV_3:
1264                 p0 = 3;
1265                 break;
1266         case DPLL_CFGCR2_PDIV_7:
1267                 p0 = 7;
1268                 break;
1269         }
1270
1271         switch (p2) {
1272         case DPLL_CFGCR2_KDIV_5:
1273                 p2 = 5;
1274                 break;
1275         case DPLL_CFGCR2_KDIV_2:
1276                 p2 = 2;
1277                 break;
1278         case DPLL_CFGCR2_KDIV_3:
1279                 p2 = 3;
1280                 break;
1281         case DPLL_CFGCR2_KDIV_1:
1282                 p2 = 1;
1283                 break;
1284         }
1285
1286         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1287                 * 24 * 1000;
1288
1289         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1290                      * 24 * 1000) / 0x8000;
1291
1292         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1293                 return 0;
1294
1295         return dco_freq / (p0 * p1 * p2 * 5);
1296 }
1297
1298 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1299                         enum intel_dpll_id pll_id)
1300 {
1301         u32 cfgcr0, cfgcr1;
1302         u32 p0, p1, p2, dco_freq, ref_clock;
1303
1304         if (INTEL_GEN(dev_priv) >= 11) {
1305                 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1306                 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1307         } else {
1308                 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1309                 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1310         }
1311
1312         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1313         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1314
1315         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1316                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1317                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1318         else
1319                 p1 = 1;
1320
1321
1322         switch (p0) {
1323         case DPLL_CFGCR1_PDIV_2:
1324                 p0 = 2;
1325                 break;
1326         case DPLL_CFGCR1_PDIV_3:
1327                 p0 = 3;
1328                 break;
1329         case DPLL_CFGCR1_PDIV_5:
1330                 p0 = 5;
1331                 break;
1332         case DPLL_CFGCR1_PDIV_7:
1333                 p0 = 7;
1334                 break;
1335         }
1336
1337         switch (p2) {
1338         case DPLL_CFGCR1_KDIV_1:
1339                 p2 = 1;
1340                 break;
1341         case DPLL_CFGCR1_KDIV_2:
1342                 p2 = 2;
1343                 break;
1344         case DPLL_CFGCR1_KDIV_3:
1345                 p2 = 3;
1346                 break;
1347         }
1348
1349         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1350
1351         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1352
1353         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1354                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1355
1356         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1357                 return 0;
1358
1359         return dco_freq / (p0 * p1 * p2 * 5);
1360 }
1361
1362 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1363                                  enum port port)
1364 {
1365         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1366
1367         switch (val) {
1368         case DDI_CLK_SEL_NONE:
1369                 return 0;
1370         case DDI_CLK_SEL_TBT_162:
1371                 return 162000;
1372         case DDI_CLK_SEL_TBT_270:
1373                 return 270000;
1374         case DDI_CLK_SEL_TBT_540:
1375                 return 540000;
1376         case DDI_CLK_SEL_TBT_810:
1377                 return 810000;
1378         default:
1379                 MISSING_CASE(val);
1380                 return 0;
1381         }
1382 }
1383
1384 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1385                                 enum port port)
1386 {
1387         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
1388         u32 mg_pll_div0, mg_clktop_hsclkctl;
1389         u32 m1, m2_int, m2_frac, div1, div2, refclk;
1390         u64 tmp;
1391
1392         refclk = dev_priv->cdclk.hw.ref;
1393
1394         mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
1395         mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
1396
1397         m1 = I915_READ(MG_PLL_DIV1(tc_port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1398         m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1399         m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1400                   (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1401                   MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1402
1403         switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1404         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1405                 div1 = 2;
1406                 break;
1407         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1408                 div1 = 3;
1409                 break;
1410         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1411                 div1 = 5;
1412                 break;
1413         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1414                 div1 = 7;
1415                 break;
1416         default:
1417                 MISSING_CASE(mg_clktop_hsclkctl);
1418                 return 0;
1419         }
1420
1421         div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1422                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1423         /* div2 value of 0 is same as 1 means no div */
1424         if (div2 == 0)
1425                 div2 = 1;
1426
1427         /*
1428          * Adjust the original formula to delay the division by 2^22 in order to
1429          * minimize possible rounding errors.
1430          */
1431         tmp = (u64)m1 * m2_int * refclk +
1432               (((u64)m1 * m2_frac * refclk) >> 22);
1433         tmp = div_u64(tmp, 5 * div1 * div2);
1434
1435         return tmp;
1436 }
1437
1438 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1439 {
1440         int dotclock;
1441
1442         if (pipe_config->has_pch_encoder)
1443                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1444                                                     &pipe_config->fdi_m_n);
1445         else if (intel_crtc_has_dp_encoder(pipe_config))
1446                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1447                                                     &pipe_config->dp_m_n);
1448         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1449                 dotclock = pipe_config->port_clock * 2 / 3;
1450         else
1451                 dotclock = pipe_config->port_clock;
1452
1453         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1454                 dotclock *= 2;
1455
1456         if (pipe_config->pixel_multiplier)
1457                 dotclock /= pipe_config->pixel_multiplier;
1458
1459         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1460 }
1461
1462 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1463                               struct intel_crtc_state *pipe_config)
1464 {
1465         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1466         enum port port = encoder->port;
1467         int link_clock = 0;
1468         u32 pll_id;
1469
1470         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1471         if (intel_port_is_combophy(dev_priv, port)) {
1472                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1473         } else {
1474                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1475                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1476                 else
1477                         link_clock = icl_calc_mg_pll_link(dev_priv, port);
1478         }
1479
1480         pipe_config->port_clock = link_clock;
1481         ddi_dotclock_get(pipe_config);
1482 }
1483
1484 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1485                               struct intel_crtc_state *pipe_config)
1486 {
1487         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1488         int link_clock = 0;
1489         u32 cfgcr0;
1490         enum intel_dpll_id pll_id;
1491
1492         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1493
1494         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1495
1496         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1497                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1498         } else {
1499                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1500
1501                 switch (link_clock) {
1502                 case DPLL_CFGCR0_LINK_RATE_810:
1503                         link_clock = 81000;
1504                         break;
1505                 case DPLL_CFGCR0_LINK_RATE_1080:
1506                         link_clock = 108000;
1507                         break;
1508                 case DPLL_CFGCR0_LINK_RATE_1350:
1509                         link_clock = 135000;
1510                         break;
1511                 case DPLL_CFGCR0_LINK_RATE_1620:
1512                         link_clock = 162000;
1513                         break;
1514                 case DPLL_CFGCR0_LINK_RATE_2160:
1515                         link_clock = 216000;
1516                         break;
1517                 case DPLL_CFGCR0_LINK_RATE_2700:
1518                         link_clock = 270000;
1519                         break;
1520                 case DPLL_CFGCR0_LINK_RATE_3240:
1521                         link_clock = 324000;
1522                         break;
1523                 case DPLL_CFGCR0_LINK_RATE_4050:
1524                         link_clock = 405000;
1525                         break;
1526                 default:
1527                         WARN(1, "Unsupported link rate\n");
1528                         break;
1529                 }
1530                 link_clock *= 2;
1531         }
1532
1533         pipe_config->port_clock = link_clock;
1534
1535         ddi_dotclock_get(pipe_config);
1536 }
1537
1538 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1539                               struct intel_crtc_state *pipe_config)
1540 {
1541         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1542         int link_clock;
1543
1544         /*
1545          * ctrl1 register is already shifted for each pll, just use 0 to get
1546          * the internal shift for each field
1547          */
1548         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1549                 link_clock = skl_calc_wrpll_link(pll_state);
1550         } else {
1551                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1552                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1553
1554                 switch (link_clock) {
1555                 case DPLL_CTRL1_LINK_RATE_810:
1556                         link_clock = 81000;
1557                         break;
1558                 case DPLL_CTRL1_LINK_RATE_1080:
1559                         link_clock = 108000;
1560                         break;
1561                 case DPLL_CTRL1_LINK_RATE_1350:
1562                         link_clock = 135000;
1563                         break;
1564                 case DPLL_CTRL1_LINK_RATE_1620:
1565                         link_clock = 162000;
1566                         break;
1567                 case DPLL_CTRL1_LINK_RATE_2160:
1568                         link_clock = 216000;
1569                         break;
1570                 case DPLL_CTRL1_LINK_RATE_2700:
1571                         link_clock = 270000;
1572                         break;
1573                 default:
1574                         WARN(1, "Unsupported link rate\n");
1575                         break;
1576                 }
1577                 link_clock *= 2;
1578         }
1579
1580         pipe_config->port_clock = link_clock;
1581
1582         ddi_dotclock_get(pipe_config);
1583 }
1584
1585 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1586                               struct intel_crtc_state *pipe_config)
1587 {
1588         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1589         int link_clock = 0;
1590         u32 val, pll;
1591
1592         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1593         switch (val & PORT_CLK_SEL_MASK) {
1594         case PORT_CLK_SEL_LCPLL_810:
1595                 link_clock = 81000;
1596                 break;
1597         case PORT_CLK_SEL_LCPLL_1350:
1598                 link_clock = 135000;
1599                 break;
1600         case PORT_CLK_SEL_LCPLL_2700:
1601                 link_clock = 270000;
1602                 break;
1603         case PORT_CLK_SEL_WRPLL1:
1604                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1605                 break;
1606         case PORT_CLK_SEL_WRPLL2:
1607                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1608                 break;
1609         case PORT_CLK_SEL_SPLL:
1610                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1611                 if (pll == SPLL_PLL_FREQ_810MHz)
1612                         link_clock = 81000;
1613                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1614                         link_clock = 135000;
1615                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1616                         link_clock = 270000;
1617                 else {
1618                         WARN(1, "bad spll freq\n");
1619                         return;
1620                 }
1621                 break;
1622         default:
1623                 WARN(1, "bad port clock sel\n");
1624                 return;
1625         }
1626
1627         pipe_config->port_clock = link_clock * 2;
1628
1629         ddi_dotclock_get(pipe_config);
1630 }
1631
1632 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1633 {
1634         struct dpll clock;
1635
1636         clock.m1 = 2;
1637         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1638         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1639                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1640         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1641         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1642         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1643
1644         return chv_calc_dpll_params(100000, &clock);
1645 }
1646
1647 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1648                               struct intel_crtc_state *pipe_config)
1649 {
1650         pipe_config->port_clock =
1651                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1652
1653         ddi_dotclock_get(pipe_config);
1654 }
1655
1656 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1657                                 struct intel_crtc_state *pipe_config)
1658 {
1659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1660
1661         if (INTEL_GEN(dev_priv) >= 11)
1662                 icl_ddi_clock_get(encoder, pipe_config);
1663         else if (IS_CANNONLAKE(dev_priv))
1664                 cnl_ddi_clock_get(encoder, pipe_config);
1665         else if (IS_GEN9_LP(dev_priv))
1666                 bxt_ddi_clock_get(encoder, pipe_config);
1667         else if (IS_GEN9_BC(dev_priv))
1668                 skl_ddi_clock_get(encoder, pipe_config);
1669         else if (INTEL_GEN(dev_priv) <= 8)
1670                 hsw_ddi_clock_get(encoder, pipe_config);
1671 }
1672
1673 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1674 {
1675         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1676         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1677         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1678         u32 temp;
1679
1680         if (!intel_crtc_has_dp_encoder(crtc_state))
1681                 return;
1682
1683         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1684
1685         temp = TRANS_MSA_SYNC_CLK;
1686
1687         if (crtc_state->limited_color_range)
1688                 temp |= TRANS_MSA_CEA_RANGE;
1689
1690         switch (crtc_state->pipe_bpp) {
1691         case 18:
1692                 temp |= TRANS_MSA_6_BPC;
1693                 break;
1694         case 24:
1695                 temp |= TRANS_MSA_8_BPC;
1696                 break;
1697         case 30:
1698                 temp |= TRANS_MSA_10_BPC;
1699                 break;
1700         case 36:
1701                 temp |= TRANS_MSA_12_BPC;
1702                 break;
1703         default:
1704                 MISSING_CASE(crtc_state->pipe_bpp);
1705                 break;
1706         }
1707
1708         /*
1709          * As per DP 1.2 spec section 2.3.4.3 while sending
1710          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1711          * colorspace information. The output colorspace encoding is BT601.
1712          */
1713         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1714                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1715         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1716 }
1717
1718 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1719                                     bool state)
1720 {
1721         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1722         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1723         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1724         u32 temp;
1725
1726         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1727         if (state == true)
1728                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1729         else
1730                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1731         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1732 }
1733
1734 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1735 {
1736         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1737         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1738         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1739         enum pipe pipe = crtc->pipe;
1740         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1741         enum port port = encoder->port;
1742         u32 temp;
1743
1744         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1745         temp = TRANS_DDI_FUNC_ENABLE;
1746         temp |= TRANS_DDI_SELECT_PORT(port);
1747
1748         switch (crtc_state->pipe_bpp) {
1749         case 18:
1750                 temp |= TRANS_DDI_BPC_6;
1751                 break;
1752         case 24:
1753                 temp |= TRANS_DDI_BPC_8;
1754                 break;
1755         case 30:
1756                 temp |= TRANS_DDI_BPC_10;
1757                 break;
1758         case 36:
1759                 temp |= TRANS_DDI_BPC_12;
1760                 break;
1761         default:
1762                 BUG();
1763         }
1764
1765         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1766                 temp |= TRANS_DDI_PVSYNC;
1767         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1768                 temp |= TRANS_DDI_PHSYNC;
1769
1770         if (cpu_transcoder == TRANSCODER_EDP) {
1771                 switch (pipe) {
1772                 case PIPE_A:
1773                         /* On Haswell, can only use the always-on power well for
1774                          * eDP when not using the panel fitter, and when not
1775                          * using motion blur mitigation (which we don't
1776                          * support). */
1777                         if (IS_HASWELL(dev_priv) &&
1778                             (crtc_state->pch_pfit.enabled ||
1779                              crtc_state->pch_pfit.force_thru))
1780                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1781                         else
1782                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1783                         break;
1784                 case PIPE_B:
1785                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1786                         break;
1787                 case PIPE_C:
1788                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1789                         break;
1790                 default:
1791                         BUG();
1792                         break;
1793                 }
1794         }
1795
1796         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1797                 if (crtc_state->has_hdmi_sink)
1798                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1799                 else
1800                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1801
1802                 if (crtc_state->hdmi_scrambling)
1803                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1804                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1805                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1806         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1807                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1808                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1809         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1810                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1811                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1812         } else {
1813                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1814                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1815         }
1816
1817         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1818 }
1819
1820 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1821 {
1822         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1823         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1824         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1825         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1826         u32 val = I915_READ(reg);
1827
1828         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1829         val |= TRANS_DDI_PORT_NONE;
1830         I915_WRITE(reg, val);
1831
1832         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1833             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1834                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1835                 /* Quirk time at 100ms for reliable operation */
1836                 msleep(100);
1837         }
1838 }
1839
1840 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1841                                      bool enable)
1842 {
1843         struct drm_device *dev = intel_encoder->base.dev;
1844         struct drm_i915_private *dev_priv = to_i915(dev);
1845         intel_wakeref_t wakeref;
1846         enum pipe pipe = 0;
1847         int ret = 0;
1848         u32 tmp;
1849
1850         wakeref = intel_display_power_get_if_enabled(dev_priv,
1851                                                      intel_encoder->power_domain);
1852         if (WARN_ON(!wakeref))
1853                 return -ENXIO;
1854
1855         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1856                 ret = -EIO;
1857                 goto out;
1858         }
1859
1860         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1861         if (enable)
1862                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1863         else
1864                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1865         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1866 out:
1867         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1868         return ret;
1869 }
1870
1871 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1872 {
1873         struct drm_device *dev = intel_connector->base.dev;
1874         struct drm_i915_private *dev_priv = to_i915(dev);
1875         struct intel_encoder *encoder = intel_connector->encoder;
1876         int type = intel_connector->base.connector_type;
1877         enum port port = encoder->port;
1878         enum transcoder cpu_transcoder;
1879         intel_wakeref_t wakeref;
1880         enum pipe pipe = 0;
1881         u32 tmp;
1882         bool ret;
1883
1884         wakeref = intel_display_power_get_if_enabled(dev_priv,
1885                                                      encoder->power_domain);
1886         if (!wakeref)
1887                 return false;
1888
1889         if (!encoder->get_hw_state(encoder, &pipe)) {
1890                 ret = false;
1891                 goto out;
1892         }
1893
1894         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1895                 cpu_transcoder = TRANSCODER_EDP;
1896         else
1897                 cpu_transcoder = (enum transcoder) pipe;
1898
1899         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1900
1901         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1902         case TRANS_DDI_MODE_SELECT_HDMI:
1903         case TRANS_DDI_MODE_SELECT_DVI:
1904                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1905                 break;
1906
1907         case TRANS_DDI_MODE_SELECT_DP_SST:
1908                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1909                       type == DRM_MODE_CONNECTOR_DisplayPort;
1910                 break;
1911
1912         case TRANS_DDI_MODE_SELECT_DP_MST:
1913                 /* if the transcoder is in MST state then
1914                  * connector isn't connected */
1915                 ret = false;
1916                 break;
1917
1918         case TRANS_DDI_MODE_SELECT_FDI:
1919                 ret = type == DRM_MODE_CONNECTOR_VGA;
1920                 break;
1921
1922         default:
1923                 ret = false;
1924                 break;
1925         }
1926
1927 out:
1928         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1929
1930         return ret;
1931 }
1932
1933 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1934                                         u8 *pipe_mask, bool *is_dp_mst)
1935 {
1936         struct drm_device *dev = encoder->base.dev;
1937         struct drm_i915_private *dev_priv = to_i915(dev);
1938         enum port port = encoder->port;
1939         intel_wakeref_t wakeref;
1940         enum pipe p;
1941         u32 tmp;
1942         u8 mst_pipe_mask;
1943
1944         *pipe_mask = 0;
1945         *is_dp_mst = false;
1946
1947         wakeref = intel_display_power_get_if_enabled(dev_priv,
1948                                                      encoder->power_domain);
1949         if (!wakeref)
1950                 return;
1951
1952         tmp = I915_READ(DDI_BUF_CTL(port));
1953         if (!(tmp & DDI_BUF_CTL_ENABLE))
1954                 goto out;
1955
1956         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1957                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1958
1959                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1960                 default:
1961                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1962                         /* fallthrough */
1963                 case TRANS_DDI_EDP_INPUT_A_ON:
1964                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1965                         *pipe_mask = BIT(PIPE_A);
1966                         break;
1967                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1968                         *pipe_mask = BIT(PIPE_B);
1969                         break;
1970                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1971                         *pipe_mask = BIT(PIPE_C);
1972                         break;
1973                 }
1974
1975                 goto out;
1976         }
1977
1978         mst_pipe_mask = 0;
1979         for_each_pipe(dev_priv, p) {
1980                 enum transcoder cpu_transcoder = (enum transcoder)p;
1981
1982                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1983
1984                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
1985                         continue;
1986
1987                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1988                     TRANS_DDI_MODE_SELECT_DP_MST)
1989                         mst_pipe_mask |= BIT(p);
1990
1991                 *pipe_mask |= BIT(p);
1992         }
1993
1994         if (!*pipe_mask)
1995                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
1996                               port_name(port));
1997
1998         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
1999                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2000                               port_name(port), *pipe_mask);
2001                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2002         }
2003
2004         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2005                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2006                               port_name(port), *pipe_mask, mst_pipe_mask);
2007         else
2008                 *is_dp_mst = mst_pipe_mask;
2009
2010 out:
2011         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2012                 tmp = I915_READ(BXT_PHY_CTL(port));
2013                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2014                             BXT_PHY_LANE_POWERDOWN_ACK |
2015                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2016                         DRM_ERROR("Port %c enabled but PHY powered down? "
2017                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2018         }
2019
2020         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2021 }
2022
2023 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2024                             enum pipe *pipe)
2025 {
2026         u8 pipe_mask;
2027         bool is_mst;
2028
2029         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2030
2031         if (is_mst || !pipe_mask)
2032                 return false;
2033
2034         *pipe = ffs(pipe_mask) - 1;
2035
2036         return true;
2037 }
2038
2039 static inline enum intel_display_power_domain
2040 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2041 {
2042         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2043          * DC states enabled at the same time, while for driver initiated AUX
2044          * transfers we need the same AUX IOs to be powered but with DC states
2045          * disabled. Accordingly use the AUX power domain here which leaves DC
2046          * states enabled.
2047          * However, for non-A AUX ports the corresponding non-EDP transcoders
2048          * would have already enabled power well 2 and DC_OFF. This means we can
2049          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2050          * specific AUX_IO reference without powering up any extra wells.
2051          * Note that PSR is enabled only on Port A even though this function
2052          * returns the correct domain for other ports too.
2053          */
2054         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2055                                               intel_aux_power_domain(dig_port);
2056 }
2057
2058 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2059                                        struct intel_crtc_state *crtc_state)
2060 {
2061         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2062         struct intel_digital_port *dig_port;
2063         u64 domains;
2064
2065         /*
2066          * TODO: Add support for MST encoders. Atm, the following should never
2067          * happen since fake-MST encoders don't set their get_power_domains()
2068          * hook.
2069          */
2070         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2071                 return 0;
2072
2073         dig_port = enc_to_dig_port(&encoder->base);
2074         domains = BIT_ULL(dig_port->ddi_io_power_domain);
2075
2076         /*
2077          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2078          * ports.
2079          */
2080         if (intel_crtc_has_dp_encoder(crtc_state) ||
2081             intel_port_is_tc(dev_priv, encoder->port))
2082                 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
2083
2084         /*
2085          * VDSC power is needed when DSC is enabled
2086          */
2087         if (crtc_state->dsc_params.compression_enable)
2088                 domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
2089
2090         return domains;
2091 }
2092
2093 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2094 {
2095         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2096         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2097         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2098         enum port port = encoder->port;
2099         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2100
2101         if (cpu_transcoder != TRANSCODER_EDP)
2102                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2103                            TRANS_CLK_SEL_PORT(port));
2104 }
2105
2106 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2107 {
2108         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2109         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2110
2111         if (cpu_transcoder != TRANSCODER_EDP)
2112                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2113                            TRANS_CLK_SEL_DISABLED);
2114 }
2115
2116 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2117                                 enum port port, u8 iboost)
2118 {
2119         u32 tmp;
2120
2121         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2122         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2123         if (iboost)
2124                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2125         else
2126                 tmp |= BALANCE_LEG_DISABLE(port);
2127         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2128 }
2129
2130 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2131                                int level, enum intel_output_type type)
2132 {
2133         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2134         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2135         enum port port = encoder->port;
2136         u8 iboost;
2137
2138         if (type == INTEL_OUTPUT_HDMI)
2139                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2140         else
2141                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2142
2143         if (iboost == 0) {
2144                 const struct ddi_buf_trans *ddi_translations;
2145                 int n_entries;
2146
2147                 if (type == INTEL_OUTPUT_HDMI)
2148                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2149                 else if (type == INTEL_OUTPUT_EDP)
2150                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2151                 else
2152                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2153
2154                 if (WARN_ON_ONCE(!ddi_translations))
2155                         return;
2156                 if (WARN_ON_ONCE(level >= n_entries))
2157                         level = n_entries - 1;
2158
2159                 iboost = ddi_translations[level].i_boost;
2160         }
2161
2162         /* Make sure that the requested I_boost is valid */
2163         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2164                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2165                 return;
2166         }
2167
2168         _skl_ddi_set_iboost(dev_priv, port, iboost);
2169
2170         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2171                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2172 }
2173
2174 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2175                                     int level, enum intel_output_type type)
2176 {
2177         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2178         const struct bxt_ddi_buf_trans *ddi_translations;
2179         enum port port = encoder->port;
2180         int n_entries;
2181
2182         if (type == INTEL_OUTPUT_HDMI)
2183                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2184         else if (type == INTEL_OUTPUT_EDP)
2185                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2186         else
2187                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2188
2189         if (WARN_ON_ONCE(!ddi_translations))
2190                 return;
2191         if (WARN_ON_ONCE(level >= n_entries))
2192                 level = n_entries - 1;
2193
2194         bxt_ddi_phy_set_signal_level(dev_priv, port,
2195                                      ddi_translations[level].margin,
2196                                      ddi_translations[level].scale,
2197                                      ddi_translations[level].enable,
2198                                      ddi_translations[level].deemphasis);
2199 }
2200
2201 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2202 {
2203         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2204         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2205         enum port port = encoder->port;
2206         int n_entries;
2207
2208         if (INTEL_GEN(dev_priv) >= 11) {
2209                 if (intel_port_is_combophy(dev_priv, port))
2210                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2211                                                 intel_dp->link_rate, &n_entries);
2212                 else
2213                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2214         } else if (IS_CANNONLAKE(dev_priv)) {
2215                 if (encoder->type == INTEL_OUTPUT_EDP)
2216                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2217                 else
2218                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2219         } else if (IS_GEN9_LP(dev_priv)) {
2220                 if (encoder->type == INTEL_OUTPUT_EDP)
2221                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2222                 else
2223                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2224         } else {
2225                 if (encoder->type == INTEL_OUTPUT_EDP)
2226                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2227                 else
2228                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2229         }
2230
2231         if (WARN_ON(n_entries < 1))
2232                 n_entries = 1;
2233         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2234                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2235
2236         return index_to_dp_signal_levels[n_entries - 1] &
2237                 DP_TRAIN_VOLTAGE_SWING_MASK;
2238 }
2239
2240 /*
2241  * We assume that the full set of pre-emphasis values can be
2242  * used on all DDI platforms. Should that change we need to
2243  * rethink this code.
2244  */
2245 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2246 {
2247         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2248         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2249                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2250         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2251                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2252         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2253                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2254         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2255         default:
2256                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2257         }
2258 }
2259
2260 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2261                                    int level, enum intel_output_type type)
2262 {
2263         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2264         const struct cnl_ddi_buf_trans *ddi_translations;
2265         enum port port = encoder->port;
2266         int n_entries, ln;
2267         u32 val;
2268
2269         if (type == INTEL_OUTPUT_HDMI)
2270                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2271         else if (type == INTEL_OUTPUT_EDP)
2272                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2273         else
2274                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2275
2276         if (WARN_ON_ONCE(!ddi_translations))
2277                 return;
2278         if (WARN_ON_ONCE(level >= n_entries))
2279                 level = n_entries - 1;
2280
2281         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2282         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2283         val &= ~SCALING_MODE_SEL_MASK;
2284         val |= SCALING_MODE_SEL(2);
2285         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2286
2287         /* Program PORT_TX_DW2 */
2288         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2289         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2290                  RCOMP_SCALAR_MASK);
2291         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2292         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2293         /* Rcomp scalar is fixed as 0x98 for every table entry */
2294         val |= RCOMP_SCALAR(0x98);
2295         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2296
2297         /* Program PORT_TX_DW4 */
2298         /* We cannot write to GRP. It would overrite individual loadgen */
2299         for (ln = 0; ln < 4; ln++) {
2300                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2301                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2302                          CURSOR_COEFF_MASK);
2303                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2304                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2305                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2306                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2307         }
2308
2309         /* Program PORT_TX_DW5 */
2310         /* All DW5 values are fixed for every table entry */
2311         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2312         val &= ~RTERM_SELECT_MASK;
2313         val |= RTERM_SELECT(6);
2314         val |= TAP3_DISABLE;
2315         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2316
2317         /* Program PORT_TX_DW7 */
2318         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2319         val &= ~N_SCALAR_MASK;
2320         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2321         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2322 }
2323
2324 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2325                                     int level, enum intel_output_type type)
2326 {
2327         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2328         enum port port = encoder->port;
2329         int width, rate, ln;
2330         u32 val;
2331
2332         if (type == INTEL_OUTPUT_HDMI) {
2333                 width = 4;
2334                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2335         } else {
2336                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2337
2338                 width = intel_dp->lane_count;
2339                 rate = intel_dp->link_rate;
2340         }
2341
2342         /*
2343          * 1. If port type is eDP or DP,
2344          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2345          * else clear to 0b.
2346          */
2347         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2348         if (type != INTEL_OUTPUT_HDMI)
2349                 val |= COMMON_KEEPER_EN;
2350         else
2351                 val &= ~COMMON_KEEPER_EN;
2352         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2353
2354         /* 2. Program loadgen select */
2355         /*
2356          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2357          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2358          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2359          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2360          */
2361         for (ln = 0; ln <= 3; ln++) {
2362                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2363                 val &= ~LOADGEN_SELECT;
2364
2365                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2366                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2367                         val |= LOADGEN_SELECT;
2368                 }
2369                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2370         }
2371
2372         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2373         val = I915_READ(CNL_PORT_CL1CM_DW5);
2374         val |= SUS_CLOCK_CONFIG;
2375         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2376
2377         /* 4. Clear training enable to change swing values */
2378         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2379         val &= ~TX_TRAINING_EN;
2380         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2381
2382         /* 5. Program swing and de-emphasis */
2383         cnl_ddi_vswing_program(encoder, level, type);
2384
2385         /* 6. Set training enable to trigger update */
2386         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2387         val |= TX_TRAINING_EN;
2388         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2389 }
2390
2391 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2392                                         u32 level, enum port port, int type,
2393                                         int rate)
2394 {
2395         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2396         u32 n_entries, val;
2397         int ln;
2398
2399         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2400                                                    rate, &n_entries);
2401         if (!ddi_translations)
2402                 return;
2403
2404         if (level >= n_entries) {
2405                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2406                 level = n_entries - 1;
2407         }
2408
2409         /* Set PORT_TX_DW5 */
2410         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2411         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2412                   TAP2_DISABLE | TAP3_DISABLE);
2413         val |= SCALING_MODE_SEL(0x2);
2414         val |= RTERM_SELECT(0x6);
2415         val |= TAP3_DISABLE;
2416         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2417
2418         /* Program PORT_TX_DW2 */
2419         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2420         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2421                  RCOMP_SCALAR_MASK);
2422         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2423         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2424         /* Program Rcomp scalar for every table entry */
2425         val |= RCOMP_SCALAR(0x98);
2426         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2427
2428         /* Program PORT_TX_DW4 */
2429         /* We cannot write to GRP. It would overwrite individual loadgen. */
2430         for (ln = 0; ln <= 3; ln++) {
2431                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2432                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2433                          CURSOR_COEFF_MASK);
2434                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2435                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2436                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2437                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2438         }
2439
2440         /* Program PORT_TX_DW7 */
2441         val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2442         val &= ~N_SCALAR_MASK;
2443         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2444         I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2445 }
2446
2447 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2448                                               u32 level,
2449                                               enum intel_output_type type)
2450 {
2451         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2452         enum port port = encoder->port;
2453         int width = 0;
2454         int rate = 0;
2455         u32 val;
2456         int ln = 0;
2457
2458         if (type == INTEL_OUTPUT_HDMI) {
2459                 width = 4;
2460                 /* Rate is always < than 6GHz for HDMI */
2461         } else {
2462                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2463
2464                 width = intel_dp->lane_count;
2465                 rate = intel_dp->link_rate;
2466         }
2467
2468         /*
2469          * 1. If port type is eDP or DP,
2470          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2471          * else clear to 0b.
2472          */
2473         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2474         if (type == INTEL_OUTPUT_HDMI)
2475                 val &= ~COMMON_KEEPER_EN;
2476         else
2477                 val |= COMMON_KEEPER_EN;
2478         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2479
2480         /* 2. Program loadgen select */
2481         /*
2482          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2483          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2484          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2485          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2486          */
2487         for (ln = 0; ln <= 3; ln++) {
2488                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2489                 val &= ~LOADGEN_SELECT;
2490
2491                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2492                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2493                         val |= LOADGEN_SELECT;
2494                 }
2495                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2496         }
2497
2498         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2499         val = I915_READ(ICL_PORT_CL_DW5(port));
2500         val |= SUS_CLOCK_CONFIG;
2501         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2502
2503         /* 4. Clear training enable to change swing values */
2504         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2505         val &= ~TX_TRAINING_EN;
2506         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2507
2508         /* 5. Program swing and de-emphasis */
2509         icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2510
2511         /* 6. Set training enable to trigger update */
2512         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2513         val |= TX_TRAINING_EN;
2514         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2515 }
2516
2517 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2518                                            int link_clock,
2519                                            u32 level)
2520 {
2521         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2522         enum port port = encoder->port;
2523         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2524         u32 n_entries, val;
2525         int ln;
2526
2527         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2528         ddi_translations = icl_mg_phy_ddi_translations;
2529         /* The table does not have values for level 3 and level 9. */
2530         if (level >= n_entries || level == 3 || level == 9) {
2531                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2532                               level, n_entries - 2);
2533                 level = n_entries - 2;
2534         }
2535
2536         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2537         for (ln = 0; ln < 2; ln++) {
2538                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2539                 val &= ~CRI_USE_FS32;
2540                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2541
2542                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2543                 val &= ~CRI_USE_FS32;
2544                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2545         }
2546
2547         /* Program MG_TX_SWINGCTRL with values from vswing table */
2548         for (ln = 0; ln < 2; ln++) {
2549                 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2550                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2551                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2552                         ddi_translations[level].cri_txdeemph_override_17_12);
2553                 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2554
2555                 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2556                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2557                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2558                         ddi_translations[level].cri_txdeemph_override_17_12);
2559                 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2560         }
2561
2562         /* Program MG_TX_DRVCTRL with values from vswing table */
2563         for (ln = 0; ln < 2; ln++) {
2564                 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2565                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2566                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2567                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2568                         ddi_translations[level].cri_txdeemph_override_5_0) |
2569                         CRI_TXDEEMPH_OVERRIDE_11_6(
2570                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2571                         CRI_TXDEEMPH_OVERRIDE_EN;
2572                 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2573
2574                 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2575                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2576                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2577                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2578                         ddi_translations[level].cri_txdeemph_override_5_0) |
2579                         CRI_TXDEEMPH_OVERRIDE_11_6(
2580                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2581                         CRI_TXDEEMPH_OVERRIDE_EN;
2582                 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2583
2584                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2585         }
2586
2587         /*
2588          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2589          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2590          * values from table for which TX1 and TX2 enabled.
2591          */
2592         for (ln = 0; ln < 2; ln++) {
2593                 val = I915_READ(MG_CLKHUB(ln, port));
2594                 if (link_clock < 300000)
2595                         val |= CFG_LOW_RATE_LKREN_EN;
2596                 else
2597                         val &= ~CFG_LOW_RATE_LKREN_EN;
2598                 I915_WRITE(MG_CLKHUB(ln, port), val);
2599         }
2600
2601         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2602         for (ln = 0; ln < 2; ln++) {
2603                 val = I915_READ(MG_TX1_DCC(ln, port));
2604                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2605                 if (link_clock <= 500000) {
2606                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2607                 } else {
2608                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2609                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2610                 }
2611                 I915_WRITE(MG_TX1_DCC(ln, port), val);
2612
2613                 val = I915_READ(MG_TX2_DCC(ln, port));
2614                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2615                 if (link_clock <= 500000) {
2616                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2617                 } else {
2618                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2619                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2620                 }
2621                 I915_WRITE(MG_TX2_DCC(ln, port), val);
2622         }
2623
2624         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2625         for (ln = 0; ln < 2; ln++) {
2626                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2627                 val |= CRI_CALCINIT;
2628                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2629
2630                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2631                 val |= CRI_CALCINIT;
2632                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2633         }
2634 }
2635
2636 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2637                                     int link_clock,
2638                                     u32 level,
2639                                     enum intel_output_type type)
2640 {
2641         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2642         enum port port = encoder->port;
2643
2644         if (intel_port_is_combophy(dev_priv, port))
2645                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2646         else
2647                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2648 }
2649
2650 static u32 translate_signal_level(int signal_levels)
2651 {
2652         int i;
2653
2654         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2655                 if (index_to_dp_signal_levels[i] == signal_levels)
2656                         return i;
2657         }
2658
2659         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2660              signal_levels);
2661
2662         return 0;
2663 }
2664
2665 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2666 {
2667         u8 train_set = intel_dp->train_set[0];
2668         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2669                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2670
2671         return translate_signal_level(signal_levels);
2672 }
2673
2674 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2675 {
2676         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2677         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2678         struct intel_encoder *encoder = &dport->base;
2679         int level = intel_ddi_dp_level(intel_dp);
2680
2681         if (INTEL_GEN(dev_priv) >= 11)
2682                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2683                                         level, encoder->type);
2684         else if (IS_CANNONLAKE(dev_priv))
2685                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2686         else
2687                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2688
2689         return 0;
2690 }
2691
2692 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2693 {
2694         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2695         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2696         struct intel_encoder *encoder = &dport->base;
2697         int level = intel_ddi_dp_level(intel_dp);
2698
2699         if (IS_GEN9_BC(dev_priv))
2700                 skl_ddi_set_iboost(encoder, level, encoder->type);
2701
2702         return DDI_BUF_TRANS_SELECT(level);
2703 }
2704
2705 static inline
2706 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2707                               enum port port)
2708 {
2709         if (intel_port_is_combophy(dev_priv, port)) {
2710                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2711         } else if (intel_port_is_tc(dev_priv, port)) {
2712                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2713
2714                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2715         }
2716
2717         return 0;
2718 }
2719
2720 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2721                                   const struct intel_crtc_state *crtc_state)
2722 {
2723         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2724         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2725         enum port port = encoder->port;
2726         u32 val;
2727
2728         mutex_lock(&dev_priv->dpll_lock);
2729
2730         val = I915_READ(DPCLKA_CFGCR0_ICL);
2731         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2732
2733         if (intel_port_is_combophy(dev_priv, port)) {
2734                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2735                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2736                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2737                 POSTING_READ(DPCLKA_CFGCR0_ICL);
2738         }
2739
2740         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2741         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2742
2743         mutex_unlock(&dev_priv->dpll_lock);
2744 }
2745
2746 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2747 {
2748         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2749         enum port port = encoder->port;
2750         u32 val;
2751
2752         mutex_lock(&dev_priv->dpll_lock);
2753
2754         val = I915_READ(DPCLKA_CFGCR0_ICL);
2755         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2756         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2757
2758         mutex_unlock(&dev_priv->dpll_lock);
2759 }
2760
2761 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2762 {
2763         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2764         u32 val;
2765         enum port port;
2766         u32 port_mask;
2767         bool ddi_clk_needed;
2768
2769         /*
2770          * In case of DP MST, we sanitize the primary encoder only, not the
2771          * virtual ones.
2772          */
2773         if (encoder->type == INTEL_OUTPUT_DP_MST)
2774                 return;
2775
2776         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2777                 u8 pipe_mask;
2778                 bool is_mst;
2779
2780                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2781                 /*
2782                  * In the unlikely case that BIOS enables DP in MST mode, just
2783                  * warn since our MST HW readout is incomplete.
2784                  */
2785                 if (WARN_ON(is_mst))
2786                         return;
2787         }
2788
2789         port_mask = BIT(encoder->port);
2790         ddi_clk_needed = encoder->base.crtc;
2791
2792         if (encoder->type == INTEL_OUTPUT_DSI) {
2793                 struct intel_encoder *other_encoder;
2794
2795                 port_mask = intel_dsi_encoder_ports(encoder);
2796                 /*
2797                  * Sanity check that we haven't incorrectly registered another
2798                  * encoder using any of the ports of this DSI encoder.
2799                  */
2800                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2801                         if (other_encoder == encoder)
2802                                 continue;
2803
2804                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2805                                 return;
2806                 }
2807                 /*
2808                  * DSI ports should have their DDI clock ungated when disabled
2809                  * and gated when enabled.
2810                  */
2811                 ddi_clk_needed = !encoder->base.crtc;
2812         }
2813
2814         val = I915_READ(DPCLKA_CFGCR0_ICL);
2815         for_each_port_masked(port, port_mask) {
2816                 bool ddi_clk_ungated = !(val &
2817                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2818                                                                    port));
2819
2820                 if (ddi_clk_needed == ddi_clk_ungated)
2821                         continue;
2822
2823                 /*
2824                  * Punt on the case now where clock is gated, but it would
2825                  * be needed by the port. Something else is really broken then.
2826                  */
2827                 if (WARN_ON(ddi_clk_needed))
2828                         continue;
2829
2830                 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2831                          port_name(port));
2832                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2833                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2834         }
2835 }
2836
2837 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2838                                  const struct intel_crtc_state *crtc_state)
2839 {
2840         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2841         enum port port = encoder->port;
2842         u32 val;
2843         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2844
2845         if (WARN_ON(!pll))
2846                 return;
2847
2848         mutex_lock(&dev_priv->dpll_lock);
2849
2850         if (INTEL_GEN(dev_priv) >= 11) {
2851                 if (!intel_port_is_combophy(dev_priv, port))
2852                         I915_WRITE(DDI_CLK_SEL(port),
2853                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2854         } else if (IS_CANNONLAKE(dev_priv)) {
2855                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2856                 val = I915_READ(DPCLKA_CFGCR0);
2857                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2858                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2859                 I915_WRITE(DPCLKA_CFGCR0, val);
2860
2861                 /*
2862                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2863                  * This step and the step before must be done with separate
2864                  * register writes.
2865                  */
2866                 val = I915_READ(DPCLKA_CFGCR0);
2867                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2868                 I915_WRITE(DPCLKA_CFGCR0, val);
2869         } else if (IS_GEN9_BC(dev_priv)) {
2870                 /* DDI -> PLL mapping  */
2871                 val = I915_READ(DPLL_CTRL2);
2872
2873                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2874                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2875                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2876                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2877
2878                 I915_WRITE(DPLL_CTRL2, val);
2879
2880         } else if (INTEL_GEN(dev_priv) < 9) {
2881                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2882         }
2883
2884         mutex_unlock(&dev_priv->dpll_lock);
2885 }
2886
2887 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2888 {
2889         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2890         enum port port = encoder->port;
2891
2892         if (INTEL_GEN(dev_priv) >= 11) {
2893                 if (!intel_port_is_combophy(dev_priv, port))
2894                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2895         } else if (IS_CANNONLAKE(dev_priv)) {
2896                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2897                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2898         } else if (IS_GEN9_BC(dev_priv)) {
2899                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2900                            DPLL_CTRL2_DDI_CLK_OFF(port));
2901         } else if (INTEL_GEN(dev_priv) < 9) {
2902                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2903         }
2904 }
2905
2906 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2907 {
2908         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2909         enum port port = dig_port->base.port;
2910         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2911         i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
2912         u32 val;
2913         int i;
2914
2915         if (tc_port == PORT_TC_NONE)
2916                 return;
2917
2918         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2919                 val = I915_READ(mg_regs[i]);
2920                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2921                        MG_DP_MODE_CFG_TRPWR_GATING |
2922                        MG_DP_MODE_CFG_CLNPWR_GATING |
2923                        MG_DP_MODE_CFG_DIGPWR_GATING |
2924                        MG_DP_MODE_CFG_GAONPWR_GATING;
2925                 I915_WRITE(mg_regs[i], val);
2926         }
2927
2928         val = I915_READ(MG_MISC_SUS0(tc_port));
2929         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2930                MG_MISC_SUS0_CFG_TR2PWR_GATING |
2931                MG_MISC_SUS0_CFG_CL2PWR_GATING |
2932                MG_MISC_SUS0_CFG_GAONPWR_GATING |
2933                MG_MISC_SUS0_CFG_TRPWR_GATING |
2934                MG_MISC_SUS0_CFG_CL1PWR_GATING |
2935                MG_MISC_SUS0_CFG_DGPWR_GATING;
2936         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2937 }
2938
2939 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2940 {
2941         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2942         enum port port = dig_port->base.port;
2943         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2944         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2945         u32 val;
2946         int i;
2947
2948         if (tc_port == PORT_TC_NONE)
2949                 return;
2950
2951         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2952                 val = I915_READ(mg_regs[i]);
2953                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2954                          MG_DP_MODE_CFG_TRPWR_GATING |
2955                          MG_DP_MODE_CFG_CLNPWR_GATING |
2956                          MG_DP_MODE_CFG_DIGPWR_GATING |
2957                          MG_DP_MODE_CFG_GAONPWR_GATING);
2958                 I915_WRITE(mg_regs[i], val);
2959         }
2960
2961         val = I915_READ(MG_MISC_SUS0(tc_port));
2962         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2963                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
2964                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
2965                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
2966                  MG_MISC_SUS0_CFG_TRPWR_GATING |
2967                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
2968                  MG_MISC_SUS0_CFG_DGPWR_GATING);
2969         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2970 }
2971
2972 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2973 {
2974         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2975         enum port port = intel_dig_port->base.port;
2976         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2977         u32 ln0, ln1, lane_info;
2978
2979         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2980                 return;
2981
2982         ln0 = I915_READ(MG_DP_MODE(0, port));
2983         ln1 = I915_READ(MG_DP_MODE(1, port));
2984
2985         switch (intel_dig_port->tc_type) {
2986         case TC_PORT_TYPEC:
2987                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2988                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2989
2990                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
2991                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
2992                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
2993
2994                 switch (lane_info) {
2995                 case 0x1:
2996                 case 0x4:
2997                         break;
2998                 case 0x2:
2999                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3000                         break;
3001                 case 0x3:
3002                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3003                                MG_DP_MODE_CFG_DP_X2_MODE;
3004                         break;
3005                 case 0x8:
3006                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3007                         break;
3008                 case 0xC:
3009                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3010                                MG_DP_MODE_CFG_DP_X2_MODE;
3011                         break;
3012                 case 0xF:
3013                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3014                                MG_DP_MODE_CFG_DP_X2_MODE;
3015                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3016                                MG_DP_MODE_CFG_DP_X2_MODE;
3017                         break;
3018                 default:
3019                         MISSING_CASE(lane_info);
3020                 }
3021                 break;
3022
3023         case TC_PORT_LEGACY:
3024                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3025                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3026                 break;
3027
3028         default:
3029                 MISSING_CASE(intel_dig_port->tc_type);
3030                 return;
3031         }
3032
3033         I915_WRITE(MG_DP_MODE(0, port), ln0);
3034         I915_WRITE(MG_DP_MODE(1, port), ln1);
3035 }
3036
3037 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3038                                         const struct intel_crtc_state *crtc_state)
3039 {
3040         if (!crtc_state->fec_enable)
3041                 return;
3042
3043         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3044                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3045 }
3046
3047 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3048                                  const struct intel_crtc_state *crtc_state)
3049 {
3050         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3051         enum port port = encoder->port;
3052         u32 val;
3053
3054         if (!crtc_state->fec_enable)
3055                 return;
3056
3057         val = I915_READ(DP_TP_CTL(port));
3058         val |= DP_TP_CTL_FEC_ENABLE;
3059         I915_WRITE(DP_TP_CTL(port), val);
3060
3061         if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
3062                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3063                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3064                                     1))
3065                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3066 }
3067
3068 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3069                                         const struct intel_crtc_state *crtc_state)
3070 {
3071         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3072         enum port port = encoder->port;
3073         u32 val;
3074
3075         if (!crtc_state->fec_enable)
3076                 return;
3077
3078         val = I915_READ(DP_TP_CTL(port));
3079         val &= ~DP_TP_CTL_FEC_ENABLE;
3080         I915_WRITE(DP_TP_CTL(port), val);
3081         POSTING_READ(DP_TP_CTL(port));
3082 }
3083
3084 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3085                                     const struct intel_crtc_state *crtc_state,
3086                                     const struct drm_connector_state *conn_state)
3087 {
3088         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3089         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3090         enum port port = encoder->port;
3091         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3092         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3093         int level = intel_ddi_dp_level(intel_dp);
3094
3095         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3096
3097         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3098                                  crtc_state->lane_count, is_mst);
3099
3100         intel_edp_panel_on(intel_dp);
3101
3102         intel_ddi_clk_select(encoder, crtc_state);
3103
3104         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3105
3106         icl_program_mg_dp_mode(dig_port);
3107         icl_disable_phy_clock_gating(dig_port);
3108
3109         if (INTEL_GEN(dev_priv) >= 11)
3110                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3111                                         level, encoder->type);
3112         else if (IS_CANNONLAKE(dev_priv))
3113                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3114         else if (IS_GEN9_LP(dev_priv))
3115                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3116         else
3117                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3118
3119         intel_ddi_init_dp_buf_reg(encoder);
3120         if (!is_mst)
3121                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3122         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3123                                               true);
3124         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3125         intel_dp_start_link_train(intel_dp);
3126         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3127                 intel_dp_stop_link_train(intel_dp);
3128
3129         intel_ddi_enable_fec(encoder, crtc_state);
3130
3131         icl_enable_phy_clock_gating(dig_port);
3132
3133         if (!is_mst)
3134                 intel_ddi_enable_pipe_clock(crtc_state);
3135
3136         intel_dsc_enable(encoder, crtc_state);
3137 }
3138
3139 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3140                                       const struct intel_crtc_state *crtc_state,
3141                                       const struct drm_connector_state *conn_state)
3142 {
3143         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3144         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3145         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3146         enum port port = encoder->port;
3147         int level = intel_ddi_hdmi_level(dev_priv, port);
3148         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3149
3150         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3151         intel_ddi_clk_select(encoder, crtc_state);
3152
3153         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3154
3155         icl_program_mg_dp_mode(dig_port);
3156         icl_disable_phy_clock_gating(dig_port);
3157
3158         if (INTEL_GEN(dev_priv) >= 11)
3159                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3160                                         level, INTEL_OUTPUT_HDMI);
3161         else if (IS_CANNONLAKE(dev_priv))
3162                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3163         else if (IS_GEN9_LP(dev_priv))
3164                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3165         else
3166                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3167
3168         icl_enable_phy_clock_gating(dig_port);
3169
3170         if (IS_GEN9_BC(dev_priv))
3171                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3172
3173         intel_ddi_enable_pipe_clock(crtc_state);
3174
3175         intel_dig_port->set_infoframes(encoder,
3176                                        crtc_state->has_infoframe,
3177                                        crtc_state, conn_state);
3178 }
3179
3180 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3181                                  const struct intel_crtc_state *crtc_state,
3182                                  const struct drm_connector_state *conn_state)
3183 {
3184         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3185         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3186         enum pipe pipe = crtc->pipe;
3187
3188         /*
3189          * When called from DP MST code:
3190          * - conn_state will be NULL
3191          * - encoder will be the main encoder (ie. mst->primary)
3192          * - the main connector associated with this port
3193          *   won't be active or linked to a crtc
3194          * - crtc_state will be the state of the first stream to
3195          *   be activated on this port, and it may not be the same
3196          *   stream that will be deactivated last, but each stream
3197          *   should have a state that is identical when it comes to
3198          *   the DP link parameteres
3199          */
3200
3201         WARN_ON(crtc_state->has_pch_encoder);
3202
3203         if (INTEL_GEN(dev_priv) >= 11)
3204                 icl_map_plls_to_ports(encoder, crtc_state);
3205
3206         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3207
3208         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3209                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3210         } else {
3211                 struct intel_lspcon *lspcon =
3212                                 enc_to_intel_lspcon(&encoder->base);
3213
3214                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3215                 if (lspcon->active) {
3216                         struct intel_digital_port *dig_port =
3217                                         enc_to_dig_port(&encoder->base);
3218
3219                         dig_port->set_infoframes(encoder,
3220                                                  crtc_state->has_infoframe,
3221                                                  crtc_state, conn_state);
3222                 }
3223         }
3224 }
3225
3226 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3227                                   const struct intel_crtc_state *crtc_state)
3228 {
3229         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3230         enum port port = encoder->port;
3231         bool wait = false;
3232         u32 val;
3233
3234         val = I915_READ(DDI_BUF_CTL(port));
3235         if (val & DDI_BUF_CTL_ENABLE) {
3236                 val &= ~DDI_BUF_CTL_ENABLE;
3237                 I915_WRITE(DDI_BUF_CTL(port), val);
3238                 wait = true;
3239         }
3240
3241         val = I915_READ(DP_TP_CTL(port));
3242         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3243         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3244         I915_WRITE(DP_TP_CTL(port), val);
3245
3246         /* Disable FEC in DP Sink */
3247         intel_ddi_disable_fec_state(encoder, crtc_state);
3248
3249         if (wait)
3250                 intel_wait_ddi_buf_idle(dev_priv, port);
3251 }
3252
3253 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3254                                       const struct intel_crtc_state *old_crtc_state,
3255                                       const struct drm_connector_state *old_conn_state)
3256 {
3257         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3258         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3259         struct intel_dp *intel_dp = &dig_port->dp;
3260         bool is_mst = intel_crtc_has_type(old_crtc_state,
3261                                           INTEL_OUTPUT_DP_MST);
3262
3263         if (!is_mst) {
3264                 intel_ddi_disable_pipe_clock(old_crtc_state);
3265                 /*
3266                  * Power down sink before disabling the port, otherwise we end
3267                  * up getting interrupts from the sink on detecting link loss.
3268                  */
3269                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3270         }
3271
3272         intel_disable_ddi_buf(encoder, old_crtc_state);
3273
3274         intel_edp_panel_vdd_on(intel_dp);
3275         intel_edp_panel_off(intel_dp);
3276
3277         intel_display_power_put_unchecked(dev_priv,
3278                                           dig_port->ddi_io_power_domain);
3279
3280         intel_ddi_clk_disable(encoder);
3281 }
3282
3283 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3284                                         const struct intel_crtc_state *old_crtc_state,
3285                                         const struct drm_connector_state *old_conn_state)
3286 {
3287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3288         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3289         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3290
3291         dig_port->set_infoframes(encoder, false,
3292                                  old_crtc_state, old_conn_state);
3293
3294         intel_ddi_disable_pipe_clock(old_crtc_state);
3295
3296         intel_disable_ddi_buf(encoder, old_crtc_state);
3297
3298         intel_display_power_put_unchecked(dev_priv,
3299                                           dig_port->ddi_io_power_domain);
3300
3301         intel_ddi_clk_disable(encoder);
3302
3303         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3304 }
3305
3306 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3307                                    const struct intel_crtc_state *old_crtc_state,
3308                                    const struct drm_connector_state *old_conn_state)
3309 {
3310         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3311
3312         /*
3313          * When called from DP MST code:
3314          * - old_conn_state will be NULL
3315          * - encoder will be the main encoder (ie. mst->primary)
3316          * - the main connector associated with this port
3317          *   won't be active or linked to a crtc
3318          * - old_crtc_state will be the state of the last stream to
3319          *   be deactivated on this port, and it may not be the same
3320          *   stream that was activated last, but each stream
3321          *   should have a state that is identical when it comes to
3322          *   the DP link parameteres
3323          */
3324
3325         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3326                 intel_ddi_post_disable_hdmi(encoder,
3327                                             old_crtc_state, old_conn_state);
3328         else
3329                 intel_ddi_post_disable_dp(encoder,
3330                                           old_crtc_state, old_conn_state);
3331
3332         if (INTEL_GEN(dev_priv) >= 11)
3333                 icl_unmap_plls_to_ports(encoder);
3334 }
3335
3336 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3337                                 const struct intel_crtc_state *old_crtc_state,
3338                                 const struct drm_connector_state *old_conn_state)
3339 {
3340         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3341         u32 val;
3342
3343         /*
3344          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3345          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3346          * step 13 is the correct place for it. Step 18 is where it was
3347          * originally before the BUN.
3348          */
3349         val = I915_READ(FDI_RX_CTL(PIPE_A));
3350         val &= ~FDI_RX_ENABLE;
3351         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3352
3353         intel_disable_ddi_buf(encoder, old_crtc_state);
3354         intel_ddi_clk_disable(encoder);
3355
3356         val = I915_READ(FDI_RX_MISC(PIPE_A));
3357         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3358         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3359         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3360
3361         val = I915_READ(FDI_RX_CTL(PIPE_A));
3362         val &= ~FDI_PCDCLK;
3363         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3364
3365         val = I915_READ(FDI_RX_CTL(PIPE_A));
3366         val &= ~FDI_RX_PLL_ENABLE;
3367         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3368 }
3369
3370 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3371                                 const struct intel_crtc_state *crtc_state,
3372                                 const struct drm_connector_state *conn_state)
3373 {
3374         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3375         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3376         enum port port = encoder->port;
3377
3378         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3379                 intel_dp_stop_link_train(intel_dp);
3380
3381         intel_edp_backlight_on(crtc_state, conn_state);
3382         intel_psr_enable(intel_dp, crtc_state);
3383         intel_edp_drrs_enable(intel_dp, crtc_state);
3384
3385         if (crtc_state->has_audio)
3386                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3387 }
3388
3389 static i915_reg_t
3390 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3391                                enum port port)
3392 {
3393         static const i915_reg_t regs[] = {
3394                 [PORT_A] = CHICKEN_TRANS_EDP,
3395                 [PORT_B] = CHICKEN_TRANS_A,
3396                 [PORT_C] = CHICKEN_TRANS_B,
3397                 [PORT_D] = CHICKEN_TRANS_C,
3398                 [PORT_E] = CHICKEN_TRANS_A,
3399         };
3400
3401         WARN_ON(INTEL_GEN(dev_priv) < 9);
3402
3403         if (WARN_ON(port < PORT_A || port > PORT_E))
3404                 port = PORT_A;
3405
3406         return regs[port];
3407 }
3408
3409 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3410                                   const struct intel_crtc_state *crtc_state,
3411                                   const struct drm_connector_state *conn_state)
3412 {
3413         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3414         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3415         struct drm_connector *connector = conn_state->connector;
3416         enum port port = encoder->port;
3417
3418         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3419                                                crtc_state->hdmi_high_tmds_clock_ratio,
3420                                                crtc_state->hdmi_scrambling))
3421                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3422                           connector->base.id, connector->name);
3423
3424         /* Display WA #1143: skl,kbl,cfl */
3425         if (IS_GEN9_BC(dev_priv)) {
3426                 /*
3427                  * For some reason these chicken bits have been
3428                  * stuffed into a transcoder register, event though
3429                  * the bits affect a specific DDI port rather than
3430                  * a specific transcoder.
3431                  */
3432                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3433                 u32 val;
3434
3435                 val = I915_READ(reg);
3436
3437                 if (port == PORT_E)
3438                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3439                                 DDIE_TRAINING_OVERRIDE_VALUE;
3440                 else
3441                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3442                                 DDI_TRAINING_OVERRIDE_VALUE;
3443
3444                 I915_WRITE(reg, val);
3445                 POSTING_READ(reg);
3446
3447                 udelay(1);
3448
3449                 if (port == PORT_E)
3450                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3451                                  DDIE_TRAINING_OVERRIDE_VALUE);
3452                 else
3453                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3454                                  DDI_TRAINING_OVERRIDE_VALUE);
3455
3456                 I915_WRITE(reg, val);
3457         }
3458
3459         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3460          * are ignored so nothing special needs to be done besides
3461          * enabling the port.
3462          */
3463         I915_WRITE(DDI_BUF_CTL(port),
3464                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3465
3466         if (crtc_state->has_audio)
3467                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3468 }
3469
3470 static void intel_enable_ddi(struct intel_encoder *encoder,
3471                              const struct intel_crtc_state *crtc_state,
3472                              const struct drm_connector_state *conn_state)
3473 {
3474         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3475                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3476         else
3477                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3478
3479         /* Enable hdcp if it's desired */
3480         if (conn_state->content_protection ==
3481             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3482                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3483 }
3484
3485 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3486                                  const struct intel_crtc_state *old_crtc_state,
3487                                  const struct drm_connector_state *old_conn_state)
3488 {
3489         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3490
3491         intel_dp->link_trained = false;
3492
3493         if (old_crtc_state->has_audio)
3494                 intel_audio_codec_disable(encoder,
3495                                           old_crtc_state, old_conn_state);
3496
3497         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3498         intel_psr_disable(intel_dp, old_crtc_state);
3499         intel_edp_backlight_off(old_conn_state);
3500         /* Disable the decompression in DP Sink */
3501         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3502                                               false);
3503 }
3504
3505 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3506                                    const struct intel_crtc_state *old_crtc_state,
3507                                    const struct drm_connector_state *old_conn_state)
3508 {
3509         struct drm_connector *connector = old_conn_state->connector;
3510
3511         if (old_crtc_state->has_audio)
3512                 intel_audio_codec_disable(encoder,
3513                                           old_crtc_state, old_conn_state);
3514
3515         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3516                                                false, false))
3517                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3518                               connector->base.id, connector->name);
3519 }
3520
3521 static void intel_disable_ddi(struct intel_encoder *encoder,
3522                               const struct intel_crtc_state *old_crtc_state,
3523                               const struct drm_connector_state *old_conn_state)
3524 {
3525         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3526
3527         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3528                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3529         else
3530                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3531 }
3532
3533 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3534                                      const struct intel_crtc_state *crtc_state,
3535                                      const struct drm_connector_state *conn_state)
3536 {
3537         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3538
3539         intel_psr_update(intel_dp, crtc_state);
3540         intel_edp_drrs_enable(intel_dp, crtc_state);
3541
3542         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3543 }
3544
3545 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3546                                   const struct intel_crtc_state *crtc_state,
3547                                   const struct drm_connector_state *conn_state)
3548 {
3549         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3550                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3551
3552         if (conn_state->content_protection ==
3553             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3554                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3555         else if (conn_state->content_protection ==
3556                  DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3557                 intel_hdcp_disable(to_intel_connector(conn_state->connector));
3558 }
3559
3560 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3561                                          const struct intel_crtc_state *pipe_config,
3562                                          enum port port)
3563 {
3564         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3565         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3566         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3567         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3568         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3569
3570         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3571         switch (pipe_config->lane_count) {
3572         case 1:
3573                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3574                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3575                 break;
3576         case 2:
3577                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3578                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3579                 break;
3580         case 4:
3581                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3582                 break;
3583         default:
3584                 MISSING_CASE(pipe_config->lane_count);
3585         }
3586         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3587 }
3588
3589 static void
3590 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3591                          const struct intel_crtc_state *crtc_state,
3592                          const struct drm_connector_state *conn_state)
3593 {
3594         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3595         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3596         enum port port = encoder->port;
3597
3598         if (intel_crtc_has_dp_encoder(crtc_state) ||
3599             intel_port_is_tc(dev_priv, encoder->port))
3600                 intel_display_power_get(dev_priv,
3601                                         intel_ddi_main_link_aux_domain(dig_port));
3602
3603         if (IS_GEN9_LP(dev_priv))
3604                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3605                                                 crtc_state->lane_lat_optim_mask);
3606
3607         /*
3608          * Program the lane count for static/dynamic connections on Type-C ports.
3609          * Skip this step for TBT.
3610          */
3611         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3612             dig_port->tc_type == TC_PORT_TBT)
3613                 return;
3614
3615         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3616 }
3617
3618 static void
3619 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3620                            const struct intel_crtc_state *crtc_state,
3621                            const struct drm_connector_state *conn_state)
3622 {
3623         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3624         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3625
3626         if (intel_crtc_has_dp_encoder(crtc_state) ||
3627             intel_port_is_tc(dev_priv, encoder->port))
3628                 intel_display_power_put_unchecked(dev_priv,
3629                                                   intel_ddi_main_link_aux_domain(dig_port));
3630 }
3631
3632 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3633 {
3634         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3635         struct drm_i915_private *dev_priv =
3636                 to_i915(intel_dig_port->base.base.dev);
3637         enum port port = intel_dig_port->base.port;
3638         u32 val;
3639         bool wait = false;
3640
3641         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3642                 val = I915_READ(DDI_BUF_CTL(port));
3643                 if (val & DDI_BUF_CTL_ENABLE) {
3644                         val &= ~DDI_BUF_CTL_ENABLE;
3645                         I915_WRITE(DDI_BUF_CTL(port), val);
3646                         wait = true;
3647                 }
3648
3649                 val = I915_READ(DP_TP_CTL(port));
3650                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3651                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3652                 I915_WRITE(DP_TP_CTL(port), val);
3653                 POSTING_READ(DP_TP_CTL(port));
3654
3655                 if (wait)
3656                         intel_wait_ddi_buf_idle(dev_priv, port);
3657         }
3658
3659         val = DP_TP_CTL_ENABLE |
3660               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3661         if (intel_dp->link_mst)
3662                 val |= DP_TP_CTL_MODE_MST;
3663         else {
3664                 val |= DP_TP_CTL_MODE_SST;
3665                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3666                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3667         }
3668         I915_WRITE(DP_TP_CTL(port), val);
3669         POSTING_READ(DP_TP_CTL(port));
3670
3671         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3672         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3673         POSTING_READ(DDI_BUF_CTL(port));
3674
3675         udelay(600);
3676 }
3677
3678 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3679                                        enum transcoder cpu_transcoder)
3680 {
3681         if (cpu_transcoder == TRANSCODER_EDP)
3682                 return false;
3683
3684         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3685                 return false;
3686
3687         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3688                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3689 }
3690
3691 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3692                                          struct intel_crtc_state *crtc_state)
3693 {
3694         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3695                 crtc_state->min_voltage_level = 1;
3696         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3697                 crtc_state->min_voltage_level = 2;
3698 }
3699
3700 void intel_ddi_get_config(struct intel_encoder *encoder,
3701                           struct intel_crtc_state *pipe_config)
3702 {
3703         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3704         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3705         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3706         struct intel_digital_port *intel_dig_port;
3707         u32 temp, flags = 0;
3708
3709         /* XXX: DSI transcoder paranoia */
3710         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3711                 return;
3712
3713         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3714         if (temp & TRANS_DDI_PHSYNC)
3715                 flags |= DRM_MODE_FLAG_PHSYNC;
3716         else
3717                 flags |= DRM_MODE_FLAG_NHSYNC;
3718         if (temp & TRANS_DDI_PVSYNC)
3719                 flags |= DRM_MODE_FLAG_PVSYNC;
3720         else
3721                 flags |= DRM_MODE_FLAG_NVSYNC;
3722
3723         pipe_config->base.adjusted_mode.flags |= flags;
3724
3725         switch (temp & TRANS_DDI_BPC_MASK) {
3726         case TRANS_DDI_BPC_6:
3727                 pipe_config->pipe_bpp = 18;
3728                 break;
3729         case TRANS_DDI_BPC_8:
3730                 pipe_config->pipe_bpp = 24;
3731                 break;
3732         case TRANS_DDI_BPC_10:
3733                 pipe_config->pipe_bpp = 30;
3734                 break;
3735         case TRANS_DDI_BPC_12:
3736                 pipe_config->pipe_bpp = 36;
3737                 break;
3738         default:
3739                 break;
3740         }
3741
3742         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3743         case TRANS_DDI_MODE_SELECT_HDMI:
3744                 pipe_config->has_hdmi_sink = true;
3745                 intel_dig_port = enc_to_dig_port(&encoder->base);
3746
3747                 pipe_config->infoframes.enable |=
3748                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3749
3750                 if (pipe_config->infoframes.enable)
3751                         pipe_config->has_infoframe = true;
3752
3753                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3754                         pipe_config->hdmi_scrambling = true;
3755                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3756                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3757                 /* fall through */
3758         case TRANS_DDI_MODE_SELECT_DVI:
3759                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3760                 pipe_config->lane_count = 4;
3761                 break;
3762         case TRANS_DDI_MODE_SELECT_FDI:
3763                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3764                 break;
3765         case TRANS_DDI_MODE_SELECT_DP_SST:
3766                 if (encoder->type == INTEL_OUTPUT_EDP)
3767                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3768                 else
3769                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3770                 pipe_config->lane_count =
3771                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3772                 intel_dp_get_m_n(intel_crtc, pipe_config);
3773                 break;
3774         case TRANS_DDI_MODE_SELECT_DP_MST:
3775                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3776                 pipe_config->lane_count =
3777                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3778                 intel_dp_get_m_n(intel_crtc, pipe_config);
3779                 break;
3780         default:
3781                 break;
3782         }
3783
3784         pipe_config->has_audio =
3785                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3786
3787         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3788             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3789                 /*
3790                  * This is a big fat ugly hack.
3791                  *
3792                  * Some machines in UEFI boot mode provide us a VBT that has 18
3793                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3794                  * unknown we fail to light up. Yet the same BIOS boots up with
3795                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3796                  * max, not what it tells us to use.
3797                  *
3798                  * Note: This will still be broken if the eDP panel is not lit
3799                  * up by the BIOS, and thus we can't get the mode at module
3800                  * load.
3801                  */
3802                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3803                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3804                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3805         }
3806
3807         intel_ddi_clock_get(encoder, pipe_config);
3808
3809         if (IS_GEN9_LP(dev_priv))
3810                 pipe_config->lane_lat_optim_mask =
3811                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3812
3813         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3814
3815         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3816
3817         intel_read_infoframe(encoder, pipe_config,
3818                              HDMI_INFOFRAME_TYPE_AVI,
3819                              &pipe_config->infoframes.avi);
3820         intel_read_infoframe(encoder, pipe_config,
3821                              HDMI_INFOFRAME_TYPE_SPD,
3822                              &pipe_config->infoframes.spd);
3823         intel_read_infoframe(encoder, pipe_config,
3824                              HDMI_INFOFRAME_TYPE_VENDOR,
3825                              &pipe_config->infoframes.hdmi);
3826 }
3827
3828 static enum intel_output_type
3829 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3830                               struct intel_crtc_state *crtc_state,
3831                               struct drm_connector_state *conn_state)
3832 {
3833         switch (conn_state->connector->connector_type) {
3834         case DRM_MODE_CONNECTOR_HDMIA:
3835                 return INTEL_OUTPUT_HDMI;
3836         case DRM_MODE_CONNECTOR_eDP:
3837                 return INTEL_OUTPUT_EDP;
3838         case DRM_MODE_CONNECTOR_DisplayPort:
3839                 return INTEL_OUTPUT_DP;
3840         default:
3841                 MISSING_CASE(conn_state->connector->connector_type);
3842                 return INTEL_OUTPUT_UNUSED;
3843         }
3844 }
3845
3846 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3847                                     struct intel_crtc_state *pipe_config,
3848                                     struct drm_connector_state *conn_state)
3849 {
3850         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3851         enum port port = encoder->port;
3852         int ret;
3853
3854         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
3855                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3856
3857         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3858                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3859         else
3860                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3861
3862         if (IS_GEN9_LP(dev_priv) && ret)
3863                 pipe_config->lane_lat_optim_mask =
3864                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3865
3866         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3867
3868         return ret;
3869
3870 }
3871
3872 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3873 {
3874         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3875         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3876
3877         intel_dp_encoder_suspend(encoder);
3878
3879         /*
3880          * TODO: disconnect also from USB DP alternate mode once we have a
3881          * way to handle the modeset restore in that mode during resume
3882          * even if the sink has disappeared while being suspended.
3883          */
3884         if (dig_port->tc_legacy_port)
3885                 icl_tc_phy_disconnect(i915, dig_port);
3886 }
3887
3888 static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3889 {
3890         struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3891         struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3892
3893         if (intel_port_is_tc(i915, dig_port->base.port))
3894                 intel_digital_port_connected(&dig_port->base);
3895
3896         intel_dp_encoder_reset(drm_encoder);
3897 }
3898
3899 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3900 {
3901         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3902         struct drm_i915_private *i915 = to_i915(encoder->dev);
3903
3904         intel_dp_encoder_flush_work(encoder);
3905
3906         if (intel_port_is_tc(i915, dig_port->base.port))
3907                 icl_tc_phy_disconnect(i915, dig_port);
3908
3909         drm_encoder_cleanup(encoder);
3910         kfree(dig_port);
3911 }
3912
3913 static const struct drm_encoder_funcs intel_ddi_funcs = {
3914         .reset = intel_ddi_encoder_reset,
3915         .destroy = intel_ddi_encoder_destroy,
3916 };
3917
3918 static struct intel_connector *
3919 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3920 {
3921         struct intel_connector *connector;
3922         enum port port = intel_dig_port->base.port;
3923
3924         connector = intel_connector_alloc();
3925         if (!connector)
3926                 return NULL;
3927
3928         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3929         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3930                 kfree(connector);
3931                 return NULL;
3932         }
3933
3934         return connector;
3935 }
3936
3937 static int modeset_pipe(struct drm_crtc *crtc,
3938                         struct drm_modeset_acquire_ctx *ctx)
3939 {
3940         struct drm_atomic_state *state;
3941         struct drm_crtc_state *crtc_state;
3942         int ret;
3943
3944         state = drm_atomic_state_alloc(crtc->dev);
3945         if (!state)
3946                 return -ENOMEM;
3947
3948         state->acquire_ctx = ctx;
3949
3950         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3951         if (IS_ERR(crtc_state)) {
3952                 ret = PTR_ERR(crtc_state);
3953                 goto out;
3954         }
3955
3956         crtc_state->connectors_changed = true;
3957
3958         ret = drm_atomic_commit(state);
3959 out:
3960         drm_atomic_state_put(state);
3961
3962         return ret;
3963 }
3964
3965 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3966                                  struct drm_modeset_acquire_ctx *ctx)
3967 {
3968         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3969         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3970         struct intel_connector *connector = hdmi->attached_connector;
3971         struct i2c_adapter *adapter =
3972                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3973         struct drm_connector_state *conn_state;
3974         struct intel_crtc_state *crtc_state;
3975         struct intel_crtc *crtc;
3976         u8 config;
3977         int ret;
3978
3979         if (!connector || connector->base.status != connector_status_connected)
3980                 return 0;
3981
3982         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3983                                ctx);
3984         if (ret)
3985                 return ret;
3986
3987         conn_state = connector->base.state;
3988
3989         crtc = to_intel_crtc(conn_state->crtc);
3990         if (!crtc)
3991                 return 0;
3992
3993         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3994         if (ret)
3995                 return ret;
3996
3997         crtc_state = to_intel_crtc_state(crtc->base.state);
3998
3999         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4000
4001         if (!crtc_state->base.active)
4002                 return 0;
4003
4004         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4005             !crtc_state->hdmi_scrambling)
4006                 return 0;
4007
4008         if (conn_state->commit &&
4009             !try_wait_for_completion(&conn_state->commit->hw_done))
4010                 return 0;
4011
4012         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4013         if (ret < 0) {
4014                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4015                 return 0;
4016         }
4017
4018         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4019             crtc_state->hdmi_high_tmds_clock_ratio &&
4020             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4021             crtc_state->hdmi_scrambling)
4022                 return 0;
4023
4024         /*
4025          * HDMI 2.0 says that one should not send scrambled data
4026          * prior to configuring the sink scrambling, and that
4027          * TMDS clock/data transmission should be suspended when
4028          * changing the TMDS clock rate in the sink. So let's
4029          * just do a full modeset here, even though some sinks
4030          * would be perfectly happy if were to just reconfigure
4031          * the SCDC settings on the fly.
4032          */
4033         return modeset_pipe(&crtc->base, ctx);
4034 }
4035
4036 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4037                               struct intel_connector *connector)
4038 {
4039         struct drm_modeset_acquire_ctx ctx;
4040         bool changed;
4041         int ret;
4042
4043         changed = intel_encoder_hotplug(encoder, connector);
4044
4045         drm_modeset_acquire_init(&ctx, 0);
4046
4047         for (;;) {
4048                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4049                         ret = intel_hdmi_reset_link(encoder, &ctx);
4050                 else
4051                         ret = intel_dp_retrain_link(encoder, &ctx);
4052
4053                 if (ret == -EDEADLK) {
4054                         drm_modeset_backoff(&ctx);
4055                         continue;
4056                 }
4057
4058                 break;
4059         }
4060
4061         drm_modeset_drop_locks(&ctx);
4062         drm_modeset_acquire_fini(&ctx);
4063         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4064
4065         return changed;
4066 }
4067
4068 static struct intel_connector *
4069 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4070 {
4071         struct intel_connector *connector;
4072         enum port port = intel_dig_port->base.port;
4073
4074         connector = intel_connector_alloc();
4075         if (!connector)
4076                 return NULL;
4077
4078         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4079         intel_hdmi_init_connector(intel_dig_port, connector);
4080
4081         return connector;
4082 }
4083
4084 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4085 {
4086         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4087
4088         if (dport->base.port != PORT_A)
4089                 return false;
4090
4091         if (dport->saved_port_bits & DDI_A_4_LANES)
4092                 return false;
4093
4094         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4095          *                     supported configuration
4096          */
4097         if (IS_GEN9_LP(dev_priv))
4098                 return true;
4099
4100         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4101          *             one who does also have a full A/E split called
4102          *             DDI_F what makes DDI_E useless. However for this
4103          *             case let's trust VBT info.
4104          */
4105         if (IS_CANNONLAKE(dev_priv) &&
4106             !intel_bios_is_port_present(dev_priv, PORT_E))
4107                 return true;
4108
4109         return false;
4110 }
4111
4112 static int
4113 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4114 {
4115         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4116         enum port port = intel_dport->base.port;
4117         int max_lanes = 4;
4118
4119         if (INTEL_GEN(dev_priv) >= 11)
4120                 return max_lanes;
4121
4122         if (port == PORT_A || port == PORT_E) {
4123                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4124                         max_lanes = port == PORT_A ? 4 : 0;
4125                 else
4126                         /* Both A and E share 2 lanes */
4127                         max_lanes = 2;
4128         }
4129
4130         /*
4131          * Some BIOS might fail to set this bit on port A if eDP
4132          * wasn't lit up at boot.  Force this bit set when needed
4133          * so we use the proper lane count for our calculations.
4134          */
4135         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4136                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4137                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4138                 max_lanes = 4;
4139         }
4140
4141         return max_lanes;
4142 }
4143
4144 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4145 {
4146         struct ddi_vbt_port_info *port_info =
4147                 &dev_priv->vbt.ddi_port_info[port];
4148         struct intel_digital_port *intel_dig_port;
4149         struct intel_encoder *intel_encoder;
4150         struct drm_encoder *encoder;
4151         bool init_hdmi, init_dp, init_lspcon = false;
4152         enum pipe pipe;
4153
4154         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4155         init_dp = port_info->supports_dp;
4156
4157         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4158                 /*
4159                  * Lspcon device needs to be driven with DP connector
4160                  * with special detection sequence. So make sure DP
4161                  * is initialized before lspcon.
4162                  */
4163                 init_dp = true;
4164                 init_lspcon = true;
4165                 init_hdmi = false;
4166                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4167         }
4168
4169         if (!init_dp && !init_hdmi) {
4170                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4171                               port_name(port));
4172                 return;
4173         }
4174
4175         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4176         if (!intel_dig_port)
4177                 return;
4178
4179         intel_encoder = &intel_dig_port->base;
4180         encoder = &intel_encoder->base;
4181
4182         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4183                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4184
4185         intel_encoder->hotplug = intel_ddi_hotplug;
4186         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4187         intel_encoder->compute_config = intel_ddi_compute_config;
4188         intel_encoder->enable = intel_enable_ddi;
4189         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4190         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4191         intel_encoder->pre_enable = intel_ddi_pre_enable;
4192         intel_encoder->disable = intel_disable_ddi;
4193         intel_encoder->post_disable = intel_ddi_post_disable;
4194         intel_encoder->update_pipe = intel_ddi_update_pipe;
4195         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4196         intel_encoder->get_config = intel_ddi_get_config;
4197         intel_encoder->suspend = intel_ddi_encoder_suspend;
4198         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4199         intel_encoder->type = INTEL_OUTPUT_DDI;
4200         intel_encoder->power_domain = intel_port_to_power_domain(port);
4201         intel_encoder->port = port;
4202         intel_encoder->cloneable = 0;
4203         for_each_pipe(dev_priv, pipe)
4204                 intel_encoder->crtc_mask |= BIT(pipe);
4205
4206         if (INTEL_GEN(dev_priv) >= 11)
4207                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4208                         DDI_BUF_PORT_REVERSAL;
4209         else
4210                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4211                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4212         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4213         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4214         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4215
4216         intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4217                                          !port_info->supports_typec_usb &&
4218                                          !port_info->supports_tbt;
4219
4220         switch (port) {
4221         case PORT_A:
4222                 intel_dig_port->ddi_io_power_domain =
4223                         POWER_DOMAIN_PORT_DDI_A_IO;
4224                 break;
4225         case PORT_B:
4226                 intel_dig_port->ddi_io_power_domain =
4227                         POWER_DOMAIN_PORT_DDI_B_IO;
4228                 break;
4229         case PORT_C:
4230                 intel_dig_port->ddi_io_power_domain =
4231                         POWER_DOMAIN_PORT_DDI_C_IO;
4232                 break;
4233         case PORT_D:
4234                 intel_dig_port->ddi_io_power_domain =
4235                         POWER_DOMAIN_PORT_DDI_D_IO;
4236                 break;
4237         case PORT_E:
4238                 intel_dig_port->ddi_io_power_domain =
4239                         POWER_DOMAIN_PORT_DDI_E_IO;
4240                 break;
4241         case PORT_F:
4242                 intel_dig_port->ddi_io_power_domain =
4243                         POWER_DOMAIN_PORT_DDI_F_IO;
4244                 break;
4245         default:
4246                 MISSING_CASE(port);
4247         }
4248
4249         if (init_dp) {
4250                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4251                         goto err;
4252
4253                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4254         }
4255
4256         /* In theory we don't need the encoder->type check, but leave it just in
4257          * case we have some really bad VBTs... */
4258         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4259                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4260                         goto err;
4261         }
4262
4263         if (init_lspcon) {
4264                 if (lspcon_init(intel_dig_port))
4265                         /* TODO: handle hdmi info frame part */
4266                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4267                                 port_name(port));
4268                 else
4269                         /*
4270                          * LSPCON init faied, but DP init was success, so
4271                          * lets try to drive as DP++ port.
4272                          */
4273                         DRM_ERROR("LSPCON init failed on port %c\n",
4274                                 port_name(port));
4275         }
4276
4277         intel_infoframe_init(intel_dig_port);
4278
4279         if (intel_port_is_tc(dev_priv, port))
4280                 intel_digital_port_connected(intel_encoder);
4281
4282         return;
4283
4284 err:
4285         drm_encoder_cleanup(encoder);
4286         kfree(intel_dig_port);
4287 }