drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31
  32 struct ddi_buf_trans {
  33         u32 trans1;     /* balance leg enable, de-emph level */
  34         u32 trans2;     /* vref sel, vswing */
  35         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  36 };
  37
  38 static const u8 index_to_dp_signal_levels[] = {
  39         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  40         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  41         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  42         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  43         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  44         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  45         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  46         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  47         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  48         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  49 };
  50
  51 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  52  * them for both DP and FDI transports, allowing those ports to
  53  * automatically adapt to HDMI connections as well
  54  */
  55 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  56         { 0x00FFFFFF, 0x0006000E, 0x0 },
  57         { 0x00D75FFF, 0x0005000A, 0x0 },
  58         { 0x00C30FFF, 0x00040006, 0x0 },
  59         { 0x80AAAFFF, 0x000B0000, 0x0 },
  60         { 0x00FFFFFF, 0x0005000A, 0x0 },
  61         { 0x00D75FFF, 0x000C0004, 0x0 },
  62         { 0x80C30FFF, 0x000B0000, 0x0 },
  63         { 0x00FFFFFF, 0x00040006, 0x0 },
  64         { 0x80D75FFF, 0x000B0000, 0x0 },
  65 };
  66
  67 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  68         { 0x00FFFFFF, 0x0007000E, 0x0 },
  69         { 0x00D75FFF, 0x000F000A, 0x0 },
  70         { 0x00C30FFF, 0x00060006, 0x0 },
  71         { 0x00AAAFFF, 0x001E0000, 0x0 },
  72         { 0x00FFFFFF, 0x000F000A, 0x0 },
  73         { 0x00D75FFF, 0x00160004, 0x0 },
  74         { 0x00C30FFF, 0x001E0000, 0x0 },
  75         { 0x00FFFFFF, 0x00060006, 0x0 },
  76         { 0x00D75FFF, 0x001E0000, 0x0 },
  77 };
  78
  79 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  80                                         /* Idx  NT mV d T mV d  db      */
  81         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  82         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  83         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  84         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  85         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  86         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  87         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  88         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  89         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  90         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  91         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  92         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  93 };
  94
  95 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  96         { 0x00FFFFFF, 0x00000012, 0x0 },
  97         { 0x00EBAFFF, 0x00020011, 0x0 },
  98         { 0x00C71FFF, 0x0006000F, 0x0 },
  99         { 0x00AAAFFF, 0x000E000A, 0x0 },
 100         { 0x00FFFFFF, 0x00020011, 0x0 },
 101         { 0x00DB6FFF, 0x0005000F, 0x0 },
 102         { 0x00BEEFFF, 0x000A000C, 0x0 },
 103         { 0x00FFFFFF, 0x0005000F, 0x0 },
 104         { 0x00DB6FFF, 0x000A000C, 0x0 },
 105 };
 106
 107 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 108         { 0x00FFFFFF, 0x0007000E, 0x0 },
 109         { 0x00D75FFF, 0x000E000A, 0x0 },
 110         { 0x00BEFFFF, 0x00140006, 0x0 },
 111         { 0x80B2CFFF, 0x001B0002, 0x0 },
 112         { 0x00FFFFFF, 0x000E000A, 0x0 },
 113         { 0x00DB6FFF, 0x00160005, 0x0 },
 114         { 0x80C71FFF, 0x001A0002, 0x0 },
 115         { 0x00F7DFFF, 0x00180004, 0x0 },
 116         { 0x80D75FFF, 0x001B0002, 0x0 },
 117 };
 118
 119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 120         { 0x00FFFFFF, 0x0001000E, 0x0 },
 121         { 0x00D75FFF, 0x0004000A, 0x0 },
 122         { 0x00C30FFF, 0x00070006, 0x0 },
 123         { 0x00AAAFFF, 0x000C0000, 0x0 },
 124         { 0x00FFFFFF, 0x0004000A, 0x0 },
 125         { 0x00D75FFF, 0x00090004, 0x0 },
 126         { 0x00C30FFF, 0x000C0000, 0x0 },
 127         { 0x00FFFFFF, 0x00070006, 0x0 },
 128         { 0x00D75FFF, 0x000C0000, 0x0 },
 129 };
 130
 131 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 132                                         /* Idx  NT mV d T mV df db      */
 133         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 134         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 135         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 136         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 137         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 138         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 139         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 140         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 141         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 142         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 143 };
 144
 145 /* Skylake H and S */
 146 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 147         { 0x00002016, 0x000000A0, 0x0 },
 148         { 0x00005012, 0x0000009B, 0x0 },
 149         { 0x00007011, 0x00000088, 0x0 },
 150         { 0x80009010, 0x000000C0, 0x1 },
 151         { 0x00002016, 0x0000009B, 0x0 },
 152         { 0x00005012, 0x00000088, 0x0 },
 153         { 0x80007011, 0x000000C0, 0x1 },
 154         { 0x00002016, 0x000000DF, 0x0 },
 155         { 0x80005012, 0x000000C0, 0x1 },
 156 };
 157
 158 /* Skylake U */
 159 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 160         { 0x0000201B, 0x000000A2, 0x0 },
 161         { 0x00005012, 0x00000088, 0x0 },
 162         { 0x80007011, 0x000000CD, 0x1 },
 163         { 0x80009010, 0x000000C0, 0x1 },
 164         { 0x0000201B, 0x0000009D, 0x0 },
 165         { 0x80005012, 0x000000C0, 0x1 },
 166         { 0x80007011, 0x000000C0, 0x1 },
 167         { 0x00002016, 0x00000088, 0x0 },
 168         { 0x80005012, 0x000000C0, 0x1 },
 169 };
 170
 171 /* Skylake Y */
 172 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 173         { 0x00000018, 0x000000A2, 0x0 },
 174         { 0x00005012, 0x00000088, 0x0 },
 175         { 0x80007011, 0x000000CD, 0x3 },
 176         { 0x80009010, 0x000000C0, 0x3 },
 177         { 0x00000018, 0x0000009D, 0x0 },
 178         { 0x80005012, 0x000000C0, 0x3 },
 179         { 0x80007011, 0x000000C0, 0x3 },
 180         { 0x00000018, 0x00000088, 0x0 },
 181         { 0x80005012, 0x000000C0, 0x3 },
 182 };
 183
 184 /* Kabylake H and S */
 185 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 186         { 0x00002016, 0x000000A0, 0x0 },
 187         { 0x00005012, 0x0000009B, 0x0 },
 188         { 0x00007011, 0x00000088, 0x0 },
 189         { 0x80009010, 0x000000C0, 0x1 },
 190         { 0x00002016, 0x0000009B, 0x0 },
 191         { 0x00005012, 0x00000088, 0x0 },
 192         { 0x80007011, 0x000000C0, 0x1 },
 193         { 0x00002016, 0x00000097, 0x0 },
 194         { 0x80005012, 0x000000C0, 0x1 },
 195 };
 196
 197 /* Kabylake U */
 198 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 199         { 0x0000201B, 0x000000A1, 0x0 },
 200         { 0x00005012, 0x00000088, 0x0 },
 201         { 0x80007011, 0x000000CD, 0x3 },
 202         { 0x80009010, 0x000000C0, 0x3 },
 203         { 0x0000201B, 0x0000009D, 0x0 },
 204         { 0x80005012, 0x000000C0, 0x3 },
 205         { 0x80007011, 0x000000C0, 0x3 },
 206         { 0x00002016, 0x0000004F, 0x0 },
 207         { 0x80005012, 0x000000C0, 0x3 },
 208 };
 209
 210 /* Kabylake Y */
 211 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 212         { 0x00001017, 0x000000A1, 0x0 },
 213         { 0x00005012, 0x00000088, 0x0 },
 214         { 0x80007011, 0x000000CD, 0x3 },
 215         { 0x8000800F, 0x000000C0, 0x3 },
 216         { 0x00001017, 0x0000009D, 0x0 },
 217         { 0x80005012, 0x000000C0, 0x3 },
 218         { 0x80007011, 0x000000C0, 0x3 },
 219         { 0x00001017, 0x0000004C, 0x0 },
 220         { 0x80005012, 0x000000C0, 0x3 },
 221 };
 222
 223 /*
 224  * Skylake/Kabylake H and S
 225  * eDP 1.4 low vswing translation parameters
 226  */
 227 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 228         { 0x00000018, 0x000000A8, 0x0 },
 229         { 0x00004013, 0x000000A9, 0x0 },
 230         { 0x00007011, 0x000000A2, 0x0 },
 231         { 0x00009010, 0x0000009C, 0x0 },
 232         { 0x00000018, 0x000000A9, 0x0 },
 233         { 0x00006013, 0x000000A2, 0x0 },
 234         { 0x00007011, 0x000000A6, 0x0 },
 235         { 0x00000018, 0x000000AB, 0x0 },
 236         { 0x00007013, 0x0000009F, 0x0 },
 237         { 0x00000018, 0x000000DF, 0x0 },
 238 };
 239
 240 /*
 241  * Skylake/Kabylake U
 242  * eDP 1.4 low vswing translation parameters
 243  */
 244 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 245         { 0x00000018, 0x000000A8, 0x0 },
 246         { 0x00004013, 0x000000A9, 0x0 },
 247         { 0x00007011, 0x000000A2, 0x0 },
 248         { 0x00009010, 0x0000009C, 0x0 },
 249         { 0x00000018, 0x000000A9, 0x0 },
 250         { 0x00006013, 0x000000A2, 0x0 },
 251         { 0x00007011, 0x000000A6, 0x0 },
 252         { 0x00002016, 0x000000AB, 0x0 },
 253         { 0x00005013, 0x0000009F, 0x0 },
 254         { 0x00000018, 0x000000DF, 0x0 },
 255 };
 256
 257 /*
 258  * Skylake/Kabylake Y
 259  * eDP 1.4 low vswing translation parameters
 260  */
 261 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 262         { 0x00000018, 0x000000A8, 0x0 },
 263         { 0x00004013, 0x000000AB, 0x0 },
 264         { 0x00007011, 0x000000A4, 0x0 },
 265         { 0x00009010, 0x000000DF, 0x0 },
 266         { 0x00000018, 0x000000AA, 0x0 },
 267         { 0x00006013, 0x000000A4, 0x0 },
 268         { 0x00007011, 0x0000009D, 0x0 },
 269         { 0x00000018, 0x000000A0, 0x0 },
 270         { 0x00006012, 0x000000DF, 0x0 },
 271         { 0x00000018, 0x0000008A, 0x0 },
 272 };
 273
 274 /* Skylake/Kabylake U, H and S */
 275 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 276         { 0x00000018, 0x000000AC, 0x0 },
 277         { 0x00005012, 0x0000009D, 0x0 },
 278         { 0x00007011, 0x00000088, 0x0 },
 279         { 0x00000018, 0x000000A1, 0x0 },
 280         { 0x00000018, 0x00000098, 0x0 },
 281         { 0x00004013, 0x00000088, 0x0 },
 282         { 0x80006012, 0x000000CD, 0x1 },
 283         { 0x00000018, 0x000000DF, 0x0 },
 284         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 285         { 0x80003015, 0x000000C0, 0x1 },
 286         { 0x80000018, 0x000000C0, 0x1 },
 287 };
 288
 289 /* Skylake/Kabylake Y */
 290 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 291         { 0x00000018, 0x000000A1, 0x0 },
 292         { 0x00005012, 0x000000DF, 0x0 },
 293         { 0x80007011, 0x000000CB, 0x3 },
 294         { 0x00000018, 0x000000A4, 0x0 },
 295         { 0x00000018, 0x0000009D, 0x0 },
 296         { 0x00004013, 0x00000080, 0x0 },
 297         { 0x80006013, 0x000000C0, 0x3 },
 298         { 0x00000018, 0x0000008A, 0x0 },
 299         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 300         { 0x80003015, 0x000000C0, 0x3 },
 301         { 0x80000018, 0x000000C0, 0x3 },
 302 };
 303
 304 struct bxt_ddi_buf_trans {
 305         u8 margin;      /* swing value */
 306         u8 scale;       /* scale value */
 307         u8 enable;      /* scale enable */
 308         u8 deemphasis;
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, },     /* 0:   200             0   */
 328         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 330         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 331         { 32, 0, 0, 128, },     /* 4:   250             0   */
 332         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 334         { 43, 0, 0, 128, },     /* 7:   300             0   */
 335         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, },     /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u8 dw2_swing_sel;
 358         u8 dw7_n_scalar;
 359         u8 dw4_cursor_coeff;
 360         u8 dw4_post_cursor_2;
 361         u8 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 struct icl_combo_phy_ddi_buf_trans {
 497         u32 dw2_swing_select;
 498         u32 dw2_swing_scalar;
 499         u32 dw4_scaling;
 500 };
 501
 502 /* Voltage Swing Programming for VccIO 0.85V for DP */
 503 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
 504                                 /* Voltage mV  db    */
 505         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 506         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 507         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 508         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 509         { 0xB, 0x70, 0x0018 },  /* 600         0.0   */
 510         { 0xB, 0x70, 0x3015 },  /* 600         3.5   */
 511         { 0xB, 0x70, 0x6012 },  /* 600         6.0   */
 512         { 0x5, 0x00, 0x0018 },  /* 800         0.0   */
 513         { 0x5, 0x00, 0x3015 },  /* 800         3.5   */
 514         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 515 };
 516
 517 /* FIXME - After table is updated in Bspec */
 518 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 519 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
 520                                 /* Voltage mV  db    */
 521         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 522         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 523         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 524         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 525         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 526         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 527         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 528         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 529         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 530         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 531 };
 532
 533 /* Voltage Swing Programming for VccIO 0.95V for DP */
 534 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
 535                                 /* Voltage mV  db    */
 536         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 537         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 538         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 539         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 540         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 541         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 542         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 543         { 0x5, 0x76, 0x0018 },  /* 800         0.0   */
 544         { 0x5, 0x76, 0x3015 },  /* 800         3.5   */
 545         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 546 };
 547
 548 /* FIXME - After table is updated in Bspec */
 549 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 550 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
 551                                 /* Voltage mV  db    */
 552         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 553         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 554         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 555         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 556         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 557         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 558         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 559         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 560         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 561         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 562 };
 563
 564 /* Voltage Swing Programming for VccIO 1.05V for DP */
 565 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
 566                                 /* Voltage mV  db    */
 567         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 568         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 569         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 570         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 571         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 572         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 573         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 574         { 0x5, 0x71, 0x0018 },  /* 800         0.0   */
 575         { 0x5, 0x71, 0x3015 },  /* 800         3.5   */
 576         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 577 };
 578
 579 /* FIXME - After table is updated in Bspec */
 580 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 581 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
 582                                 /* Voltage mV  db    */
 583         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 584         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 585         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 586         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 587         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 588         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 589         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 590         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 591         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 592         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 593 };
 594
 595 struct icl_mg_phy_ddi_buf_trans {
 596         u32 cri_txdeemph_override_5_0;
 597         u32 cri_txdeemph_override_11_6;
 598         u32 cri_txdeemph_override_17_12;
 599 };
 600
 601 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 602                                 /* Voltage swing  pre-emphasis */
 603         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 604         { 0x0, 0x23, 0x08 },    /* 0              1   */
 605         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 606         { 0x0, 0x00, 0x00 },    /* 0              3   */
 607         { 0x0, 0x23, 0x00 },    /* 1              0   */
 608         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 609         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 610         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 611         { 0x0, 0x33, 0x0C },    /* 2              1   */
 612         { 0x0, 0x00, 0x00 },    /* 3              0   */
 613 };
 614
 615 static const struct ddi_buf_trans *
 616 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 617 {
 618         if (dev_priv->vbt.edp.low_vswing) {
 619                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 620                 return bdw_ddi_translations_edp;
 621         } else {
 622                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 623                 return bdw_ddi_translations_dp;
 624         }
 625 }
 626
 627 static const struct ddi_buf_trans *
 628 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 629 {
 630         if (IS_SKL_ULX(dev_priv)) {
 631                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 632                 return skl_y_ddi_translations_dp;
 633         } else if (IS_SKL_ULT(dev_priv)) {
 634                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 635                 return skl_u_ddi_translations_dp;
 636         } else {
 637                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 638                 return skl_ddi_translations_dp;
 639         }
 640 }
 641
 642 static const struct ddi_buf_trans *
 643 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 644 {
 645         if (IS_KBL_ULX(dev_priv)) {
 646                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 647                 return kbl_y_ddi_translations_dp;
 648         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 649                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 650                 return kbl_u_ddi_translations_dp;
 651         } else {
 652                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 653                 return kbl_ddi_translations_dp;
 654         }
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 659 {
 660         if (dev_priv->vbt.edp.low_vswing) {
 661                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 662                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 663                         return skl_y_ddi_translations_edp;
 664                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 665                            IS_CFL_ULT(dev_priv)) {
 666                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 667                         return skl_u_ddi_translations_edp;
 668                 } else {
 669                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 670                         return skl_ddi_translations_edp;
 671                 }
 672         }
 673
 674         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 675                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 676         else
 677                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 678 }
 679
 680 static const struct ddi_buf_trans *
 681 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 682 {
 683         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 684                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 685                 return skl_y_ddi_translations_hdmi;
 686         } else {
 687                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 688                 return skl_ddi_translations_hdmi;
 689         }
 690 }
 691
 692 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 693 {
 694         /* Only DDIA and DDIE can select the 10th register with DP */
 695         if (port == PORT_A || port == PORT_E)
 696                 return min(n_entries, 10);
 697         else
 698                 return min(n_entries, 9);
 699 }
 700
 701 static const struct ddi_buf_trans *
 702 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 703                            enum port port, int *n_entries)
 704 {
 705         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 706                 const struct ddi_buf_trans *ddi_translations =
 707                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 708                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 709                 return ddi_translations;
 710         } else if (IS_SKYLAKE(dev_priv)) {
 711                 const struct ddi_buf_trans *ddi_translations =
 712                         skl_get_buf_trans_dp(dev_priv, n_entries);
 713                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 714                 return ddi_translations;
 715         } else if (IS_BROADWELL(dev_priv)) {
 716                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 717                 return  bdw_ddi_translations_dp;
 718         } else if (IS_HASWELL(dev_priv)) {
 719                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 720                 return hsw_ddi_translations_dp;
 721         }
 722
 723         *n_entries = 0;
 724         return NULL;
 725 }
 726
 727 static const struct ddi_buf_trans *
 728 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 729                             enum port port, int *n_entries)
 730 {
 731         if (IS_GEN9_BC(dev_priv)) {
 732                 const struct ddi_buf_trans *ddi_translations =
 733                         skl_get_buf_trans_edp(dev_priv, n_entries);
 734                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 735                 return ddi_translations;
 736         } else if (IS_BROADWELL(dev_priv)) {
 737                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 738         } else if (IS_HASWELL(dev_priv)) {
 739                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 740                 return hsw_ddi_translations_dp;
 741         }
 742
 743         *n_entries = 0;
 744         return NULL;
 745 }
 746
 747 static const struct ddi_buf_trans *
 748 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 749                             int *n_entries)
 750 {
 751         if (IS_BROADWELL(dev_priv)) {
 752                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 753                 return bdw_ddi_translations_fdi;
 754         } else if (IS_HASWELL(dev_priv)) {
 755                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 756                 return hsw_ddi_translations_fdi;
 757         }
 758
 759         *n_entries = 0;
 760         return NULL;
 761 }
 762
 763 static const struct ddi_buf_trans *
 764 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 765                              int *n_entries)
 766 {
 767         if (IS_GEN9_BC(dev_priv)) {
 768                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 769         } else if (IS_BROADWELL(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 771                 return bdw_ddi_translations_hdmi;
 772         } else if (IS_HASWELL(dev_priv)) {
 773                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 774                 return hsw_ddi_translations_hdmi;
 775         }
 776
 777         *n_entries = 0;
 778         return NULL;
 779 }
 780
 781 static const struct bxt_ddi_buf_trans *
 782 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 783 {
 784         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 785         return bxt_ddi_translations_dp;
 786 }
 787
 788 static const struct bxt_ddi_buf_trans *
 789 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 790 {
 791         if (dev_priv->vbt.edp.low_vswing) {
 792                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 793                 return bxt_ddi_translations_edp;
 794         }
 795
 796         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 797 }
 798
 799 static const struct bxt_ddi_buf_trans *
 800 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 801 {
 802         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 803         return bxt_ddi_translations_hdmi;
 804 }
 805
 806 static const struct cnl_ddi_buf_trans *
 807 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 808 {
 809         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 810
 811         if (voltage == VOLTAGE_INFO_0_85V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 813                 return cnl_ddi_translations_hdmi_0_85V;
 814         } else if (voltage == VOLTAGE_INFO_0_95V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 816                 return cnl_ddi_translations_hdmi_0_95V;
 817         } else if (voltage == VOLTAGE_INFO_1_05V) {
 818                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 819                 return cnl_ddi_translations_hdmi_1_05V;
 820         } else {
 821                 *n_entries = 1; /* shut up gcc */
 822                 MISSING_CASE(voltage);
 823         }
 824         return NULL;
 825 }
 826
 827 static const struct cnl_ddi_buf_trans *
 828 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 829 {
 830         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 831
 832         if (voltage == VOLTAGE_INFO_0_85V) {
 833                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 834                 return cnl_ddi_translations_dp_0_85V;
 835         } else if (voltage == VOLTAGE_INFO_0_95V) {
 836                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 837                 return cnl_ddi_translations_dp_0_95V;
 838         } else if (voltage == VOLTAGE_INFO_1_05V) {
 839                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 840                 return cnl_ddi_translations_dp_1_05V;
 841         } else {
 842                 *n_entries = 1; /* shut up gcc */
 843                 MISSING_CASE(voltage);
 844         }
 845         return NULL;
 846 }
 847
 848 static const struct cnl_ddi_buf_trans *
 849 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 850 {
 851         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 852
 853         if (dev_priv->vbt.edp.low_vswing) {
 854                 if (voltage == VOLTAGE_INFO_0_85V) {
 855                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 856                         return cnl_ddi_translations_edp_0_85V;
 857                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 858                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 859                         return cnl_ddi_translations_edp_0_95V;
 860                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 861                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 862                         return cnl_ddi_translations_edp_1_05V;
 863                 } else {
 864                         *n_entries = 1; /* shut up gcc */
 865                         MISSING_CASE(voltage);
 866                 }
 867                 return NULL;
 868         } else {
 869                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 870         }
 871 }
 872
 873 static const struct icl_combo_phy_ddi_buf_trans *
 874 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 875                         int type, int *n_entries)
 876 {
 877         u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
 878
 879         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 880                 switch (voltage) {
 881                 case VOLTAGE_INFO_0_85V:
 882                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
 883                         return icl_combo_phy_ddi_translations_edp_0_85V;
 884                 case VOLTAGE_INFO_0_95V:
 885                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
 886                         return icl_combo_phy_ddi_translations_edp_0_95V;
 887                 case VOLTAGE_INFO_1_05V:
 888                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
 889                         return icl_combo_phy_ddi_translations_edp_1_05V;
 890                 default:
 891                         MISSING_CASE(voltage);
 892                         return NULL;
 893                 }
 894         } else {
 895                 switch (voltage) {
 896                 case VOLTAGE_INFO_0_85V:
 897                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
 898                         return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
 899                 case VOLTAGE_INFO_0_95V:
 900                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
 901                         return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
 902                 case VOLTAGE_INFO_1_05V:
 903                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
 904                         return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
 905                 default:
 906                         MISSING_CASE(voltage);
 907                         return NULL;
 908                 }
 909         }
 910 }
 911
 912 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 913 {
 914         int n_entries, level, default_entry;
 915
 916         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 917
 918         if (IS_ICELAKE(dev_priv)) {
 919                 if (port == PORT_A || port == PORT_B)
 920                         icl_get_combo_buf_trans(dev_priv, port,
 921                                                 INTEL_OUTPUT_HDMI, &n_entries);
 922                 else
 923                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 924                 default_entry = n_entries - 1;
 925         } else if (IS_CANNONLAKE(dev_priv)) {
 926                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 927                 default_entry = n_entries - 1;
 928         } else if (IS_GEN9_LP(dev_priv)) {
 929                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 930                 default_entry = n_entries - 1;
 931         } else if (IS_GEN9_BC(dev_priv)) {
 932                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 933                 default_entry = 8;
 934         } else if (IS_BROADWELL(dev_priv)) {
 935                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 936                 default_entry = 7;
 937         } else if (IS_HASWELL(dev_priv)) {
 938                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 939                 default_entry = 6;
 940         } else {
 941                 WARN(1, "ddi translation table missing\n");
 942                 return 0;
 943         }
 944
 945         /* Choose a good default if VBT is badly populated */
 946         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 947                 level = default_entry;
 948
 949         if (WARN_ON_ONCE(n_entries == 0))
 950                 return 0;
 951         if (WARN_ON_ONCE(level >= n_entries))
 952                 level = n_entries - 1;
 953
 954         return level;
 955 }
 956
 957 /*
 958  * Starting with Haswell, DDI port buffers must be programmed with correct
 959  * values in advance. This function programs the correct values for
 960  * DP/eDP/FDI use cases.
 961  */
 962 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 963                                          const struct intel_crtc_state *crtc_state)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 966         u32 iboost_bit = 0;
 967         int i, n_entries;
 968         enum port port = encoder->port;
 969         const struct ddi_buf_trans *ddi_translations;
 970
 971         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 972                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 973                                                                &n_entries);
 974         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 975                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 976                                                                &n_entries);
 977         else
 978                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 979                                                               &n_entries);
 980
 981         /* If we're boosting the current, set bit 31 of trans1 */
 982         if (IS_GEN9_BC(dev_priv) &&
 983             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 984                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 985
 986         for (i = 0; i < n_entries; i++) {
 987                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 988                            ddi_translations[i].trans1 | iboost_bit);
 989                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 990                            ddi_translations[i].trans2);
 991         }
 992 }
 993
 994 /*
 995  * Starting with Haswell, DDI port buffers must be programmed with correct
 996  * values in advance. This function programs the correct values for
 997  * HDMI/DVI use cases.
 998  */
 999 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1000                                            int level)
1001 {
1002         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003         u32 iboost_bit = 0;
1004         int n_entries;
1005         enum port port = encoder->port;
1006         const struct ddi_buf_trans *ddi_translations;
1007
1008         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1009
1010         if (WARN_ON_ONCE(!ddi_translations))
1011                 return;
1012         if (WARN_ON_ONCE(level >= n_entries))
1013                 level = n_entries - 1;
1014
1015         /* If we're boosting the current, set bit 31 of trans1 */
1016         if (IS_GEN9_BC(dev_priv) &&
1017             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1019
1020         /* Entry 9 is for HDMI: */
1021         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1022                    ddi_translations[level].trans1 | iboost_bit);
1023         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1024                    ddi_translations[level].trans2);
1025 }
1026
1027 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028                                     enum port port)
1029 {
1030         i915_reg_t reg = DDI_BUF_CTL(port);
1031         int i;
1032
1033         for (i = 0; i < 16; i++) {
1034                 udelay(1);
1035                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036                         return;
1037         }
1038         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039 }
1040
1041 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1042 {
1043         switch (pll->info->id) {
1044         case DPLL_ID_WRPLL1:
1045                 return PORT_CLK_SEL_WRPLL1;
1046         case DPLL_ID_WRPLL2:
1047                 return PORT_CLK_SEL_WRPLL2;
1048         case DPLL_ID_SPLL:
1049                 return PORT_CLK_SEL_SPLL;
1050         case DPLL_ID_LCPLL_810:
1051                 return PORT_CLK_SEL_LCPLL_810;
1052         case DPLL_ID_LCPLL_1350:
1053                 return PORT_CLK_SEL_LCPLL_1350;
1054         case DPLL_ID_LCPLL_2700:
1055                 return PORT_CLK_SEL_LCPLL_2700;
1056         default:
1057                 MISSING_CASE(pll->info->id);
1058                 return PORT_CLK_SEL_NONE;
1059         }
1060 }
1061
1062 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1063                                        const struct intel_shared_dpll *pll)
1064 {
1065         const enum intel_dpll_id id = pll->info->id;
1066
1067         switch (id) {
1068         default:
1069                 MISSING_CASE(id);
1070         case DPLL_ID_ICL_DPLL0:
1071         case DPLL_ID_ICL_DPLL1:
1072                 return DDI_CLK_SEL_NONE;
1073         case DPLL_ID_ICL_MGPLL1:
1074         case DPLL_ID_ICL_MGPLL2:
1075         case DPLL_ID_ICL_MGPLL3:
1076         case DPLL_ID_ICL_MGPLL4:
1077                 return DDI_CLK_SEL_MG;
1078         }
1079 }
1080
1081 /* Starting with Haswell, different DDI ports can work in FDI mode for
1082  * connection to the PCH-located connectors. For this, it is necessary to train
1083  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1084  *
1085  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1086  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1087  * DDI A (which is used for eDP)
1088  */
1089
1090 void hsw_fdi_link_train(struct intel_crtc *crtc,
1091                         const struct intel_crtc_state *crtc_state)
1092 {
1093         struct drm_device *dev = crtc->base.dev;
1094         struct drm_i915_private *dev_priv = to_i915(dev);
1095         struct intel_encoder *encoder;
1096         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1097
1098         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1099                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1100                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1101         }
1102
1103         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1104          * mode set "sequence for CRT port" document:
1105          * - TP1 to TP2 time with the default value
1106          * - FDI delay to 90h
1107          *
1108          * WaFDIAutoLinkSetTimingOverrride:hsw
1109          */
1110         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1111                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1112                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1113
1114         /* Enable the PCH Receiver FDI PLL */
1115         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1116                      FDI_RX_PLL_ENABLE |
1117                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1118         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1119         POSTING_READ(FDI_RX_CTL(PIPE_A));
1120         udelay(220);
1121
1122         /* Switch from Rawclk to PCDclk */
1123         rx_ctl_val |= FDI_PCDCLK;
1124         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1125
1126         /* Configure Port Clock Select */
1127         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1128         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1129         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1130
1131         /* Start the training iterating through available voltages and emphasis,
1132          * testing each value twice. */
1133         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1134                 /* Configure DP_TP_CTL with auto-training */
1135                 I915_WRITE(DP_TP_CTL(PORT_E),
1136                                         DP_TP_CTL_FDI_AUTOTRAIN |
1137                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1138                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1139                                         DP_TP_CTL_ENABLE);
1140
1141                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1142                  * DDI E does not support port reversal, the functionality is
1143                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1144                  * port reversal bit */
1145                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1146                            DDI_BUF_CTL_ENABLE |
1147                            ((crtc_state->fdi_lanes - 1) << 1) |
1148                            DDI_BUF_TRANS_SELECT(i / 2));
1149                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1150
1151                 udelay(600);
1152
1153                 /* Program PCH FDI Receiver TU */
1154                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1155
1156                 /* Enable PCH FDI Receiver with auto-training */
1157                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1158                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1159                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1160
1161                 /* Wait for FDI receiver lane calibration */
1162                 udelay(30);
1163
1164                 /* Unset FDI_RX_MISC pwrdn lanes */
1165                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1166                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1167                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1168                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1169
1170                 /* Wait for FDI auto training time */
1171                 udelay(5);
1172
1173                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1174                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1175                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1176                         break;
1177                 }
1178
1179                 /*
1180                  * Leave things enabled even if we failed to train FDI.
1181                  * Results in less fireworks from the state checker.
1182                  */
1183                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1184                         DRM_ERROR("FDI link training failed!\n");
1185                         break;
1186                 }
1187
1188                 rx_ctl_val &= ~FDI_RX_ENABLE;
1189                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1190                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1191
1192                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1193                 temp &= ~DDI_BUF_CTL_ENABLE;
1194                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1195                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1196
1197                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1198                 temp = I915_READ(DP_TP_CTL(PORT_E));
1199                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1200                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1201                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1202                 POSTING_READ(DP_TP_CTL(PORT_E));
1203
1204                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1205
1206                 /* Reset FDI_RX_MISC pwrdn lanes */
1207                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1208                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1209                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1210                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1211                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1212         }
1213
1214         /* Enable normal pixel sending for FDI */
1215         I915_WRITE(DP_TP_CTL(PORT_E),
1216                    DP_TP_CTL_FDI_AUTOTRAIN |
1217                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1218                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1219                    DP_TP_CTL_ENABLE);
1220 }
1221
1222 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1223 {
1224         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1225         struct intel_digital_port *intel_dig_port =
1226                 enc_to_dig_port(&encoder->base);
1227
1228         intel_dp->DP = intel_dig_port->saved_port_bits |
1229                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1230         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1231 }
1232
1233 static struct intel_encoder *
1234 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1235 {
1236         struct drm_device *dev = crtc->base.dev;
1237         struct intel_encoder *encoder, *ret = NULL;
1238         int num_encoders = 0;
1239
1240         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1241                 ret = encoder;
1242                 num_encoders++;
1243         }
1244
1245         if (num_encoders != 1)
1246                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1247                      pipe_name(crtc->pipe));
1248
1249         BUG_ON(ret == NULL);
1250         return ret;
1251 }
1252
1253 #define LC_FREQ 2700
1254
1255 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1256                                    i915_reg_t reg)
1257 {
1258         int refclk = LC_FREQ;
1259         int n, p, r;
1260         u32 wrpll;
1261
1262         wrpll = I915_READ(reg);
1263         switch (wrpll & WRPLL_PLL_REF_MASK) {
1264         case WRPLL_PLL_SSC:
1265         case WRPLL_PLL_NON_SSC:
1266                 /*
1267                  * We could calculate spread here, but our checking
1268                  * code only cares about 5% accuracy, and spread is a max of
1269                  * 0.5% downspread.
1270                  */
1271                 refclk = 135;
1272                 break;
1273         case WRPLL_PLL_LCPLL:
1274                 refclk = LC_FREQ;
1275                 break;
1276         default:
1277                 WARN(1, "bad wrpll refclk\n");
1278                 return 0;
1279         }
1280
1281         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1282         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1283         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1284
1285         /* Convert to KHz, p & r have a fixed point portion */
1286         return (refclk * n * 100) / (p * r);
1287 }
1288
1289 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1290                                enum intel_dpll_id pll_id)
1291 {
1292         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1293         uint32_t cfgcr1_val, cfgcr2_val;
1294         uint32_t p0, p1, p2, dco_freq;
1295
1296         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1297         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1298
1299         cfgcr1_val = I915_READ(cfgcr1_reg);
1300         cfgcr2_val = I915_READ(cfgcr2_reg);
1301
1302         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1303         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1304
1305         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1306                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1307         else
1308                 p1 = 1;
1309
1310
1311         switch (p0) {
1312         case DPLL_CFGCR2_PDIV_1:
1313                 p0 = 1;
1314                 break;
1315         case DPLL_CFGCR2_PDIV_2:
1316                 p0 = 2;
1317                 break;
1318         case DPLL_CFGCR2_PDIV_3:
1319                 p0 = 3;
1320                 break;
1321         case DPLL_CFGCR2_PDIV_7:
1322                 p0 = 7;
1323                 break;
1324         }
1325
1326         switch (p2) {
1327         case DPLL_CFGCR2_KDIV_5:
1328                 p2 = 5;
1329                 break;
1330         case DPLL_CFGCR2_KDIV_2:
1331                 p2 = 2;
1332                 break;
1333         case DPLL_CFGCR2_KDIV_3:
1334                 p2 = 3;
1335                 break;
1336         case DPLL_CFGCR2_KDIV_1:
1337                 p2 = 1;
1338                 break;
1339         }
1340
1341         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1342
1343         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1344                 1000) / 0x8000;
1345
1346         return dco_freq / (p0 * p1 * p2 * 5);
1347 }
1348
1349 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1350                                enum intel_dpll_id pll_id)
1351 {
1352         uint32_t cfgcr0, cfgcr1;
1353         uint32_t p0, p1, p2, dco_freq, ref_clock;
1354
1355         if (INTEL_GEN(dev_priv) >= 11) {
1356                 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1357                 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1358         } else {
1359                 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1360                 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1361         }
1362
1363         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1364         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1365
1366         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1367                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1368                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1369         else
1370                 p1 = 1;
1371
1372
1373         switch (p0) {
1374         case DPLL_CFGCR1_PDIV_2:
1375                 p0 = 2;
1376                 break;
1377         case DPLL_CFGCR1_PDIV_3:
1378                 p0 = 3;
1379                 break;
1380         case DPLL_CFGCR1_PDIV_5:
1381                 p0 = 5;
1382                 break;
1383         case DPLL_CFGCR1_PDIV_7:
1384                 p0 = 7;
1385                 break;
1386         }
1387
1388         switch (p2) {
1389         case DPLL_CFGCR1_KDIV_1:
1390                 p2 = 1;
1391                 break;
1392         case DPLL_CFGCR1_KDIV_2:
1393                 p2 = 2;
1394                 break;
1395         case DPLL_CFGCR1_KDIV_4:
1396                 p2 = 4;
1397                 break;
1398         }
1399
1400         ref_clock = dev_priv->cdclk.hw.ref;
1401
1402         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1403
1404         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1405                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1406
1407         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1408                 return 0;
1409
1410         return dco_freq / (p0 * p1 * p2 * 5);
1411 }
1412
1413 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1414 {
1415         int dotclock;
1416
1417         if (pipe_config->has_pch_encoder)
1418                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1419                                                     &pipe_config->fdi_m_n);
1420         else if (intel_crtc_has_dp_encoder(pipe_config))
1421                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1422                                                     &pipe_config->dp_m_n);
1423         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1424                 dotclock = pipe_config->port_clock * 2 / 3;
1425         else
1426                 dotclock = pipe_config->port_clock;
1427
1428         if (pipe_config->ycbcr420)
1429                 dotclock *= 2;
1430
1431         if (pipe_config->pixel_multiplier)
1432                 dotclock /= pipe_config->pixel_multiplier;
1433
1434         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1435 }
1436
1437 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1438                               struct intel_crtc_state *pipe_config)
1439 {
1440         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1441         enum port port = encoder->port;
1442         int link_clock = 0;
1443         uint32_t pll_id;
1444
1445         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1446         if (port == PORT_A || port == PORT_B) {
1447                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1448                         link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1449                 else
1450                         link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1451                                                                 pll_id);
1452         } else {
1453                 /* FIXME - Add for MG PLL */
1454                 WARN(1, "MG PLL clock_get code not implemented yet\n");
1455         }
1456
1457         pipe_config->port_clock = link_clock;
1458         ddi_dotclock_get(pipe_config);
1459 }
1460
1461 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1462                               struct intel_crtc_state *pipe_config)
1463 {
1464         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1465         int link_clock = 0;
1466         uint32_t cfgcr0;
1467         enum intel_dpll_id pll_id;
1468
1469         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1470
1471         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1472
1473         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1474                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1475         } else {
1476                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1477
1478                 switch (link_clock) {
1479                 case DPLL_CFGCR0_LINK_RATE_810:
1480                         link_clock = 81000;
1481                         break;
1482                 case DPLL_CFGCR0_LINK_RATE_1080:
1483                         link_clock = 108000;
1484                         break;
1485                 case DPLL_CFGCR0_LINK_RATE_1350:
1486                         link_clock = 135000;
1487                         break;
1488                 case DPLL_CFGCR0_LINK_RATE_1620:
1489                         link_clock = 162000;
1490                         break;
1491                 case DPLL_CFGCR0_LINK_RATE_2160:
1492                         link_clock = 216000;
1493                         break;
1494                 case DPLL_CFGCR0_LINK_RATE_2700:
1495                         link_clock = 270000;
1496                         break;
1497                 case DPLL_CFGCR0_LINK_RATE_3240:
1498                         link_clock = 324000;
1499                         break;
1500                 case DPLL_CFGCR0_LINK_RATE_4050:
1501                         link_clock = 405000;
1502                         break;
1503                 default:
1504                         WARN(1, "Unsupported link rate\n");
1505                         break;
1506                 }
1507                 link_clock *= 2;
1508         }
1509
1510         pipe_config->port_clock = link_clock;
1511
1512         ddi_dotclock_get(pipe_config);
1513 }
1514
1515 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1516                                 struct intel_crtc_state *pipe_config)
1517 {
1518         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1519         int link_clock = 0;
1520         uint32_t dpll_ctl1;
1521         enum intel_dpll_id pll_id;
1522
1523         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1524
1525         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1526
1527         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1528                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1529         } else {
1530                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1531                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1532
1533                 switch (link_clock) {
1534                 case DPLL_CTRL1_LINK_RATE_810:
1535                         link_clock = 81000;
1536                         break;
1537                 case DPLL_CTRL1_LINK_RATE_1080:
1538                         link_clock = 108000;
1539                         break;
1540                 case DPLL_CTRL1_LINK_RATE_1350:
1541                         link_clock = 135000;
1542                         break;
1543                 case DPLL_CTRL1_LINK_RATE_1620:
1544                         link_clock = 162000;
1545                         break;
1546                 case DPLL_CTRL1_LINK_RATE_2160:
1547                         link_clock = 216000;
1548                         break;
1549                 case DPLL_CTRL1_LINK_RATE_2700:
1550                         link_clock = 270000;
1551                         break;
1552                 default:
1553                         WARN(1, "Unsupported link rate\n");
1554                         break;
1555                 }
1556                 link_clock *= 2;
1557         }
1558
1559         pipe_config->port_clock = link_clock;
1560
1561         ddi_dotclock_get(pipe_config);
1562 }
1563
1564 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1565                               struct intel_crtc_state *pipe_config)
1566 {
1567         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1568         int link_clock = 0;
1569         u32 val, pll;
1570
1571         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1572         switch (val & PORT_CLK_SEL_MASK) {
1573         case PORT_CLK_SEL_LCPLL_810:
1574                 link_clock = 81000;
1575                 break;
1576         case PORT_CLK_SEL_LCPLL_1350:
1577                 link_clock = 135000;
1578                 break;
1579         case PORT_CLK_SEL_LCPLL_2700:
1580                 link_clock = 270000;
1581                 break;
1582         case PORT_CLK_SEL_WRPLL1:
1583                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1584                 break;
1585         case PORT_CLK_SEL_WRPLL2:
1586                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1587                 break;
1588         case PORT_CLK_SEL_SPLL:
1589                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1590                 if (pll == SPLL_PLL_FREQ_810MHz)
1591                         link_clock = 81000;
1592                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1593                         link_clock = 135000;
1594                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1595                         link_clock = 270000;
1596                 else {
1597                         WARN(1, "bad spll freq\n");
1598                         return;
1599                 }
1600                 break;
1601         default:
1602                 WARN(1, "bad port clock sel\n");
1603                 return;
1604         }
1605
1606         pipe_config->port_clock = link_clock * 2;
1607
1608         ddi_dotclock_get(pipe_config);
1609 }
1610
1611 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1612 {
1613         struct intel_dpll_hw_state *state;
1614         struct dpll clock;
1615
1616         /* For DDI ports we always use a shared PLL. */
1617         if (WARN_ON(!crtc_state->shared_dpll))
1618                 return 0;
1619
1620         state = &crtc_state->dpll_hw_state;
1621
1622         clock.m1 = 2;
1623         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1624         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1625                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1626         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1627         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1628         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1629
1630         return chv_calc_dpll_params(100000, &clock);
1631 }
1632
1633 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1634                               struct intel_crtc_state *pipe_config)
1635 {
1636         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1637
1638         ddi_dotclock_get(pipe_config);
1639 }
1640
1641 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1642                                 struct intel_crtc_state *pipe_config)
1643 {
1644         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1645
1646         if (INTEL_GEN(dev_priv) <= 8)
1647                 hsw_ddi_clock_get(encoder, pipe_config);
1648         else if (IS_GEN9_BC(dev_priv))
1649                 skl_ddi_clock_get(encoder, pipe_config);
1650         else if (IS_GEN9_LP(dev_priv))
1651                 bxt_ddi_clock_get(encoder, pipe_config);
1652         else if (IS_CANNONLAKE(dev_priv))
1653                 cnl_ddi_clock_get(encoder, pipe_config);
1654         else if (IS_ICELAKE(dev_priv))
1655                 icl_ddi_clock_get(encoder, pipe_config);
1656 }
1657
1658 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1659 {
1660         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1661         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1662         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1663         u32 temp;
1664
1665         if (!intel_crtc_has_dp_encoder(crtc_state))
1666                 return;
1667
1668         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1669
1670         temp = TRANS_MSA_SYNC_CLK;
1671         switch (crtc_state->pipe_bpp) {
1672         case 18:
1673                 temp |= TRANS_MSA_6_BPC;
1674                 break;
1675         case 24:
1676                 temp |= TRANS_MSA_8_BPC;
1677                 break;
1678         case 30:
1679                 temp |= TRANS_MSA_10_BPC;
1680                 break;
1681         case 36:
1682                 temp |= TRANS_MSA_12_BPC;
1683                 break;
1684         default:
1685                 MISSING_CASE(crtc_state->pipe_bpp);
1686                 break;
1687         }
1688
1689         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1690 }
1691
1692 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1693                                     bool state)
1694 {
1695         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1696         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1697         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1698         uint32_t temp;
1699
1700         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1701         if (state == true)
1702                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1703         else
1704                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1705         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1706 }
1707
1708 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1709 {
1710         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1711         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1712         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1713         enum pipe pipe = crtc->pipe;
1714         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1715         enum port port = encoder->port;
1716         uint32_t temp;
1717
1718         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1719         temp = TRANS_DDI_FUNC_ENABLE;
1720         temp |= TRANS_DDI_SELECT_PORT(port);
1721
1722         switch (crtc_state->pipe_bpp) {
1723         case 18:
1724                 temp |= TRANS_DDI_BPC_6;
1725                 break;
1726         case 24:
1727                 temp |= TRANS_DDI_BPC_8;
1728                 break;
1729         case 30:
1730                 temp |= TRANS_DDI_BPC_10;
1731                 break;
1732         case 36:
1733                 temp |= TRANS_DDI_BPC_12;
1734                 break;
1735         default:
1736                 BUG();
1737         }
1738
1739         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1740                 temp |= TRANS_DDI_PVSYNC;
1741         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1742                 temp |= TRANS_DDI_PHSYNC;
1743
1744         if (cpu_transcoder == TRANSCODER_EDP) {
1745                 switch (pipe) {
1746                 case PIPE_A:
1747                         /* On Haswell, can only use the always-on power well for
1748                          * eDP when not using the panel fitter, and when not
1749                          * using motion blur mitigation (which we don't
1750                          * support). */
1751                         if (IS_HASWELL(dev_priv) &&
1752                             (crtc_state->pch_pfit.enabled ||
1753                              crtc_state->pch_pfit.force_thru))
1754                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1755                         else
1756                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1757                         break;
1758                 case PIPE_B:
1759                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1760                         break;
1761                 case PIPE_C:
1762                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1763                         break;
1764                 default:
1765                         BUG();
1766                         break;
1767                 }
1768         }
1769
1770         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1771                 if (crtc_state->has_hdmi_sink)
1772                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1773                 else
1774                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1775
1776                 if (crtc_state->hdmi_scrambling)
1777                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1778                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1779                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1780         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1781                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1782                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1783         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1784                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1785                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1786         } else {
1787                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1788                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1789         }
1790
1791         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1792 }
1793
1794 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1795                                        enum transcoder cpu_transcoder)
1796 {
1797         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1798         uint32_t val = I915_READ(reg);
1799
1800         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1801         val |= TRANS_DDI_PORT_NONE;
1802         I915_WRITE(reg, val);
1803 }
1804
1805 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1806                                      bool enable)
1807 {
1808         struct drm_device *dev = intel_encoder->base.dev;
1809         struct drm_i915_private *dev_priv = to_i915(dev);
1810         enum pipe pipe = 0;
1811         int ret = 0;
1812         uint32_t tmp;
1813
1814         if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1815                                                 intel_encoder->power_domain)))
1816                 return -ENXIO;
1817
1818         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1819                 ret = -EIO;
1820                 goto out;
1821         }
1822
1823         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1824         if (enable)
1825                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1826         else
1827                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1828         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1829 out:
1830         intel_display_power_put(dev_priv, intel_encoder->power_domain);
1831         return ret;
1832 }
1833
1834 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1835 {
1836         struct drm_device *dev = intel_connector->base.dev;
1837         struct drm_i915_private *dev_priv = to_i915(dev);
1838         struct intel_encoder *encoder = intel_connector->encoder;
1839         int type = intel_connector->base.connector_type;
1840         enum port port = encoder->port;
1841         enum pipe pipe = 0;
1842         enum transcoder cpu_transcoder;
1843         uint32_t tmp;
1844         bool ret;
1845
1846         if (!intel_display_power_get_if_enabled(dev_priv,
1847                                                 encoder->power_domain))
1848                 return false;
1849
1850         if (!encoder->get_hw_state(encoder, &pipe)) {
1851                 ret = false;
1852                 goto out;
1853         }
1854
1855         if (port == PORT_A)
1856                 cpu_transcoder = TRANSCODER_EDP;
1857         else
1858                 cpu_transcoder = (enum transcoder) pipe;
1859
1860         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1861
1862         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1863         case TRANS_DDI_MODE_SELECT_HDMI:
1864         case TRANS_DDI_MODE_SELECT_DVI:
1865                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1866                 break;
1867
1868         case TRANS_DDI_MODE_SELECT_DP_SST:
1869                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1870                       type == DRM_MODE_CONNECTOR_DisplayPort;
1871                 break;
1872
1873         case TRANS_DDI_MODE_SELECT_DP_MST:
1874                 /* if the transcoder is in MST state then
1875                  * connector isn't connected */
1876                 ret = false;
1877                 break;
1878
1879         case TRANS_DDI_MODE_SELECT_FDI:
1880                 ret = type == DRM_MODE_CONNECTOR_VGA;
1881                 break;
1882
1883         default:
1884                 ret = false;
1885                 break;
1886         }
1887
1888 out:
1889         intel_display_power_put(dev_priv, encoder->power_domain);
1890
1891         return ret;
1892 }
1893
1894 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1895                             enum pipe *pipe)
1896 {
1897         struct drm_device *dev = encoder->base.dev;
1898         struct drm_i915_private *dev_priv = to_i915(dev);
1899         enum port port = encoder->port;
1900         enum pipe p;
1901         u32 tmp;
1902         bool ret;
1903
1904         if (!intel_display_power_get_if_enabled(dev_priv,
1905                                                 encoder->power_domain))
1906                 return false;
1907
1908         ret = false;
1909
1910         tmp = I915_READ(DDI_BUF_CTL(port));
1911
1912         if (!(tmp & DDI_BUF_CTL_ENABLE))
1913                 goto out;
1914
1915         if (port == PORT_A) {
1916                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1917
1918                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1919                 case TRANS_DDI_EDP_INPUT_A_ON:
1920                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1921                         *pipe = PIPE_A;
1922                         break;
1923                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1924                         *pipe = PIPE_B;
1925                         break;
1926                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1927                         *pipe = PIPE_C;
1928                         break;
1929                 }
1930
1931                 ret = true;
1932
1933                 goto out;
1934         }
1935
1936         for_each_pipe(dev_priv, p) {
1937                 enum transcoder cpu_transcoder = (enum transcoder) p;
1938
1939                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1940
1941                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1942                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1943                             TRANS_DDI_MODE_SELECT_DP_MST)
1944                                 goto out;
1945
1946                         *pipe = p;
1947                         ret = true;
1948
1949                         goto out;
1950                 }
1951         }
1952
1953         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1954
1955 out:
1956         if (ret && IS_GEN9_LP(dev_priv)) {
1957                 tmp = I915_READ(BXT_PHY_CTL(port));
1958                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1959                             BXT_PHY_LANE_POWERDOWN_ACK |
1960                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1961                         DRM_ERROR("Port %c enabled but PHY powered down? "
1962                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1963         }
1964
1965         intel_display_power_put(dev_priv, encoder->power_domain);
1966
1967         return ret;
1968 }
1969
1970 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1971 {
1972         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1973         enum pipe pipe;
1974
1975         if (intel_ddi_get_hw_state(encoder, &pipe))
1976                 return BIT_ULL(dig_port->ddi_io_power_domain);
1977
1978         return 0;
1979 }
1980
1981 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1982 {
1983         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1984         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1985         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1986         enum port port = encoder->port;
1987         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1988
1989         if (cpu_transcoder != TRANSCODER_EDP)
1990                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1991                            TRANS_CLK_SEL_PORT(port));
1992 }
1993
1994 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1997         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1998
1999         if (cpu_transcoder != TRANSCODER_EDP)
2000                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2001                            TRANS_CLK_SEL_DISABLED);
2002 }
2003
2004 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2005                                 enum port port, uint8_t iboost)
2006 {
2007         u32 tmp;
2008
2009         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2010         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2011         if (iboost)
2012                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2013         else
2014                 tmp |= BALANCE_LEG_DISABLE(port);
2015         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2016 }
2017
2018 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2019                                int level, enum intel_output_type type)
2020 {
2021         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2022         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2023         enum port port = encoder->port;
2024         uint8_t iboost;
2025
2026         if (type == INTEL_OUTPUT_HDMI)
2027                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2028         else
2029                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2030
2031         if (iboost == 0) {
2032                 const struct ddi_buf_trans *ddi_translations;
2033                 int n_entries;
2034
2035                 if (type == INTEL_OUTPUT_HDMI)
2036                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2037                 else if (type == INTEL_OUTPUT_EDP)
2038                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2039                 else
2040                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2041
2042                 if (WARN_ON_ONCE(!ddi_translations))
2043                         return;
2044                 if (WARN_ON_ONCE(level >= n_entries))
2045                         level = n_entries - 1;
2046
2047                 iboost = ddi_translations[level].i_boost;
2048         }
2049
2050         /* Make sure that the requested I_boost is valid */
2051         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2052                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2053                 return;
2054         }
2055
2056         _skl_ddi_set_iboost(dev_priv, port, iboost);
2057
2058         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2059                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2060 }
2061
2062 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2063                                     int level, enum intel_output_type type)
2064 {
2065         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2066         const struct bxt_ddi_buf_trans *ddi_translations;
2067         enum port port = encoder->port;
2068         int n_entries;
2069
2070         if (type == INTEL_OUTPUT_HDMI)
2071                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2072         else if (type == INTEL_OUTPUT_EDP)
2073                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2074         else
2075                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2076
2077         if (WARN_ON_ONCE(!ddi_translations))
2078                 return;
2079         if (WARN_ON_ONCE(level >= n_entries))
2080                 level = n_entries - 1;
2081
2082         bxt_ddi_phy_set_signal_level(dev_priv, port,
2083                                      ddi_translations[level].margin,
2084                                      ddi_translations[level].scale,
2085                                      ddi_translations[level].enable,
2086                                      ddi_translations[level].deemphasis);
2087 }
2088
2089 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2090 {
2091         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2092         enum port port = encoder->port;
2093         int n_entries;
2094
2095         if (IS_ICELAKE(dev_priv)) {
2096                 if (port == PORT_A || port == PORT_B)
2097                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2098                                                 &n_entries);
2099                 else
2100                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2101         } else if (IS_CANNONLAKE(dev_priv)) {
2102                 if (encoder->type == INTEL_OUTPUT_EDP)
2103                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2104                 else
2105                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2106         } else if (IS_GEN9_LP(dev_priv)) {
2107                 if (encoder->type == INTEL_OUTPUT_EDP)
2108                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2109                 else
2110                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2111         } else {
2112                 if (encoder->type == INTEL_OUTPUT_EDP)
2113                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2114                 else
2115                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2116         }
2117
2118         if (WARN_ON(n_entries < 1))
2119                 n_entries = 1;
2120         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2121                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2122
2123         return index_to_dp_signal_levels[n_entries - 1] &
2124                 DP_TRAIN_VOLTAGE_SWING_MASK;
2125 }
2126
2127 /*
2128  * We assume that the full set of pre-emphasis values can be
2129  * used on all DDI platforms. Should that change we need to
2130  * rethink this code.
2131  */
2132 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2133 {
2134         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2135         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2136                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2137         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2138                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2139         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2140                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2141         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2142         default:
2143                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2144         }
2145 }
2146
2147 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2148                                    int level, enum intel_output_type type)
2149 {
2150         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2151         const struct cnl_ddi_buf_trans *ddi_translations;
2152         enum port port = encoder->port;
2153         int n_entries, ln;
2154         u32 val;
2155
2156         if (type == INTEL_OUTPUT_HDMI)
2157                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2158         else if (type == INTEL_OUTPUT_EDP)
2159                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2160         else
2161                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2162
2163         if (WARN_ON_ONCE(!ddi_translations))
2164                 return;
2165         if (WARN_ON_ONCE(level >= n_entries))
2166                 level = n_entries - 1;
2167
2168         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2169         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2170         val &= ~SCALING_MODE_SEL_MASK;
2171         val |= SCALING_MODE_SEL(2);
2172         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2173
2174         /* Program PORT_TX_DW2 */
2175         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2176         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2177                  RCOMP_SCALAR_MASK);
2178         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2179         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2180         /* Rcomp scalar is fixed as 0x98 for every table entry */
2181         val |= RCOMP_SCALAR(0x98);
2182         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2183
2184         /* Program PORT_TX_DW4 */
2185         /* We cannot write to GRP. It would overrite individual loadgen */
2186         for (ln = 0; ln < 4; ln++) {
2187                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2188                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2189                          CURSOR_COEFF_MASK);
2190                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2191                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2192                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2193                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2194         }
2195
2196         /* Program PORT_TX_DW5 */
2197         /* All DW5 values are fixed for every table entry */
2198         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2199         val &= ~RTERM_SELECT_MASK;
2200         val |= RTERM_SELECT(6);
2201         val |= TAP3_DISABLE;
2202         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2203
2204         /* Program PORT_TX_DW7 */
2205         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2206         val &= ~N_SCALAR_MASK;
2207         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2208         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2209 }
2210
2211 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2212                                     int level, enum intel_output_type type)
2213 {
2214         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2215         enum port port = encoder->port;
2216         int width, rate, ln;
2217         u32 val;
2218
2219         if (type == INTEL_OUTPUT_HDMI) {
2220                 width = 4;
2221                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2222         } else {
2223                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2224
2225                 width = intel_dp->lane_count;
2226                 rate = intel_dp->link_rate;
2227         }
2228
2229         /*
2230          * 1. If port type is eDP or DP,
2231          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2232          * else clear to 0b.
2233          */
2234         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2235         if (type != INTEL_OUTPUT_HDMI)
2236                 val |= COMMON_KEEPER_EN;
2237         else
2238                 val &= ~COMMON_KEEPER_EN;
2239         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2240
2241         /* 2. Program loadgen select */
2242         /*
2243          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2244          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2245          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2246          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2247          */
2248         for (ln = 0; ln <= 3; ln++) {
2249                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2250                 val &= ~LOADGEN_SELECT;
2251
2252                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2253                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2254                         val |= LOADGEN_SELECT;
2255                 }
2256                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2257         }
2258
2259         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2260         val = I915_READ(CNL_PORT_CL1CM_DW5);
2261         val |= SUS_CLOCK_CONFIG;
2262         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2263
2264         /* 4. Clear training enable to change swing values */
2265         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2266         val &= ~TX_TRAINING_EN;
2267         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2268
2269         /* 5. Program swing and de-emphasis */
2270         cnl_ddi_vswing_program(encoder, level, type);
2271
2272         /* 6. Set training enable to trigger update */
2273         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2274         val |= TX_TRAINING_EN;
2275         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2276 }
2277
2278 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2279                                          u32 level, enum port port, int type)
2280 {
2281         const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2282         u32 n_entries, val;
2283         int ln;
2284
2285         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2286                                                    &n_entries);
2287         if (!ddi_translations)
2288                 return;
2289
2290         if (level >= n_entries) {
2291                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2292                 level = n_entries - 1;
2293         }
2294
2295         /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2296         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2297         val &= ~RTERM_SELECT_MASK;
2298         val |= RTERM_SELECT(0x6);
2299         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2300
2301         /* Program PORT_TX_DW5 */
2302         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2303         /* Set DisableTap2 and DisableTap3 if MIPI DSI
2304          * Clear DisableTap2 and DisableTap3 for all other Ports
2305          */
2306         if (type == INTEL_OUTPUT_DSI) {
2307                 val |= TAP2_DISABLE;
2308                 val |= TAP3_DISABLE;
2309         } else {
2310                 val &= ~TAP2_DISABLE;
2311                 val &= ~TAP3_DISABLE;
2312         }
2313         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2314
2315         /* Program PORT_TX_DW2 */
2316         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2317         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2318                  RCOMP_SCALAR_MASK);
2319         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2320         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2321         /* Program Rcomp scalar for every table entry */
2322         val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2323         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2324
2325         /* Program PORT_TX_DW4 */
2326         /* We cannot write to GRP. It would overwrite individual loadgen. */
2327         for (ln = 0; ln <= 3; ln++) {
2328                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2329                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2330                          CURSOR_COEFF_MASK);
2331                 val |= ddi_translations[level].dw4_scaling;
2332                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2333         }
2334 }
2335
2336 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2337                                               u32 level,
2338                                               enum intel_output_type type)
2339 {
2340         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2341         enum port port = encoder->port;
2342         int width = 0;
2343         int rate = 0;
2344         u32 val;
2345         int ln = 0;
2346
2347         if (type == INTEL_OUTPUT_HDMI) {
2348                 width = 4;
2349                 /* Rate is always < than 6GHz for HDMI */
2350         } else {
2351                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2352
2353                 width = intel_dp->lane_count;
2354                 rate = intel_dp->link_rate;
2355         }
2356
2357         /*
2358          * 1. If port type is eDP or DP,
2359          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2360          * else clear to 0b.
2361          */
2362         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2363         if (type == INTEL_OUTPUT_HDMI)
2364                 val &= ~COMMON_KEEPER_EN;
2365         else
2366                 val |= COMMON_KEEPER_EN;
2367         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2368
2369         /* 2. Program loadgen select */
2370         /*
2371          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2372          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2373          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2374          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2375          */
2376         for (ln = 0; ln <= 3; ln++) {
2377                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2378                 val &= ~LOADGEN_SELECT;
2379
2380                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2381                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2382                         val |= LOADGEN_SELECT;
2383                 }
2384                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2385         }
2386
2387         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2388         val = I915_READ(ICL_PORT_CL_DW5(port));
2389         val |= SUS_CLOCK_CONFIG;
2390         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2391
2392         /* 4. Clear training enable to change swing values */
2393         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2394         val &= ~TX_TRAINING_EN;
2395         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2396
2397         /* 5. Program swing and de-emphasis */
2398         icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2399
2400         /* 6. Set training enable to trigger update */
2401         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2402         val |= TX_TRAINING_EN;
2403         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2404 }
2405
2406 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level,
2407                                     enum intel_output_type type)
2408 {
2409         enum port port = encoder->port;
2410
2411         if (port == PORT_A || port == PORT_B)
2412                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2413         else
2414                 /* Not Implemented Yet */
2415                 WARN_ON(1);
2416 }
2417
2418 static uint32_t translate_signal_level(int signal_levels)
2419 {
2420         int i;
2421
2422         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2423                 if (index_to_dp_signal_levels[i] == signal_levels)
2424                         return i;
2425         }
2426
2427         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2428              signal_levels);
2429
2430         return 0;
2431 }
2432
2433 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2434 {
2435         uint8_t train_set = intel_dp->train_set[0];
2436         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2437                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2438
2439         return translate_signal_level(signal_levels);
2440 }
2441
2442 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2443 {
2444         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2445         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2446         struct intel_encoder *encoder = &dport->base;
2447         int level = intel_ddi_dp_level(intel_dp);
2448
2449         if (IS_ICELAKE(dev_priv))
2450                 icl_ddi_vswing_sequence(encoder, level, encoder->type);
2451         else if (IS_CANNONLAKE(dev_priv))
2452                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2453         else
2454                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2455
2456         return 0;
2457 }
2458
2459 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2460 {
2461         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2462         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2463         struct intel_encoder *encoder = &dport->base;
2464         int level = intel_ddi_dp_level(intel_dp);
2465
2466         if (IS_GEN9_BC(dev_priv))
2467                 skl_ddi_set_iboost(encoder, level, encoder->type);
2468
2469         return DDI_BUF_TRANS_SELECT(level);
2470 }
2471
2472 void icl_map_plls_to_ports(struct drm_crtc *crtc,
2473                            struct intel_crtc_state *crtc_state,
2474                            struct drm_atomic_state *old_state)
2475 {
2476         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2477         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2478         struct drm_connector_state *conn_state;
2479         struct drm_connector *conn;
2480         int i;
2481
2482         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2483                 struct intel_encoder *encoder =
2484                         to_intel_encoder(conn_state->best_encoder);
2485                 enum port port;
2486                 uint32_t val;
2487
2488                 if (conn_state->crtc != crtc)
2489                         continue;
2490
2491                 port = encoder->port;
2492                 mutex_lock(&dev_priv->dpll_lock);
2493
2494                 val = I915_READ(DPCLKA_CFGCR0_ICL);
2495                 WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
2496
2497                 if (port == PORT_A || port == PORT_B) {
2498                         val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2499                         val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2500                         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2501                         POSTING_READ(DPCLKA_CFGCR0_ICL);
2502                 }
2503
2504                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2505                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2506
2507                 mutex_unlock(&dev_priv->dpll_lock);
2508         }
2509 }
2510
2511 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2512                              struct intel_crtc_state *crtc_state,
2513                              struct drm_atomic_state *old_state)
2514 {
2515         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2516         struct drm_connector_state *old_conn_state;
2517         struct drm_connector *conn;
2518         int i;
2519
2520         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2521                 struct intel_encoder *encoder =
2522                         to_intel_encoder(old_conn_state->best_encoder);
2523                 enum port port;
2524
2525                 if (old_conn_state->crtc != crtc)
2526                         continue;
2527
2528                 port = encoder->port;
2529                 mutex_lock(&dev_priv->dpll_lock);
2530                 I915_WRITE(DPCLKA_CFGCR0_ICL,
2531                            I915_READ(DPCLKA_CFGCR0_ICL) |
2532                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2533                 mutex_unlock(&dev_priv->dpll_lock);
2534         }
2535 }
2536
2537 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2538                                  const struct intel_shared_dpll *pll)
2539 {
2540         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2541         enum port port = encoder->port;
2542         uint32_t val;
2543
2544         if (WARN_ON(!pll))
2545                 return;
2546
2547         mutex_lock(&dev_priv->dpll_lock);
2548
2549         if (IS_ICELAKE(dev_priv)) {
2550                 if (port >= PORT_C)
2551                         I915_WRITE(DDI_CLK_SEL(port),
2552                                    icl_pll_to_ddi_pll_sel(encoder, pll));
2553         } else if (IS_CANNONLAKE(dev_priv)) {
2554                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2555                 val = I915_READ(DPCLKA_CFGCR0);
2556                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2557                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2558                 I915_WRITE(DPCLKA_CFGCR0, val);
2559
2560                 /*
2561                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2562                  * This step and the step before must be done with separate
2563                  * register writes.
2564                  */
2565                 val = I915_READ(DPCLKA_CFGCR0);
2566                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2567                 I915_WRITE(DPCLKA_CFGCR0, val);
2568         } else if (IS_GEN9_BC(dev_priv)) {
2569                 /* DDI -> PLL mapping  */
2570                 val = I915_READ(DPLL_CTRL2);
2571
2572                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2573                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2574                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2575                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2576
2577                 I915_WRITE(DPLL_CTRL2, val);
2578
2579         } else if (INTEL_GEN(dev_priv) < 9) {
2580                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2581         }
2582
2583         mutex_unlock(&dev_priv->dpll_lock);
2584 }
2585
2586 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2587 {
2588         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2589         enum port port = encoder->port;
2590
2591         if (IS_ICELAKE(dev_priv)) {
2592                 if (port >= PORT_C)
2593                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2594         } else if (IS_CANNONLAKE(dev_priv)) {
2595                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2596                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2597         } else if (IS_GEN9_BC(dev_priv)) {
2598                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2599                            DPLL_CTRL2_DDI_CLK_OFF(port));
2600         } else if (INTEL_GEN(dev_priv) < 9) {
2601                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2602         }
2603 }
2604
2605 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2606                                     const struct intel_crtc_state *crtc_state,
2607                                     const struct drm_connector_state *conn_state)
2608 {
2609         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2610         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2611         enum port port = encoder->port;
2612         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2613         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2614         int level = intel_ddi_dp_level(intel_dp);
2615
2616         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2617
2618         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2619                                  crtc_state->lane_count, is_mst);
2620
2621         intel_edp_panel_on(intel_dp);
2622
2623         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2624
2625         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2626
2627         if (IS_ICELAKE(dev_priv))
2628                 icl_ddi_vswing_sequence(encoder, level, encoder->type);
2629         else if (IS_CANNONLAKE(dev_priv))
2630                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2631         else if (IS_GEN9_LP(dev_priv))
2632                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2633         else
2634                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2635
2636         intel_ddi_init_dp_buf_reg(encoder);
2637         if (!is_mst)
2638                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2639         intel_dp_start_link_train(intel_dp);
2640         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2641                 intel_dp_stop_link_train(intel_dp);
2642 }
2643
2644 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2645                                       const struct intel_crtc_state *crtc_state,
2646                                       const struct drm_connector_state *conn_state)
2647 {
2648         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2649         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2650         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2651         enum port port = encoder->port;
2652         int level = intel_ddi_hdmi_level(dev_priv, port);
2653         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2654
2655         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2656         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2657
2658         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2659
2660         if (IS_ICELAKE(dev_priv))
2661                 icl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2662         else if (IS_CANNONLAKE(dev_priv))
2663                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2664         else if (IS_GEN9_LP(dev_priv))
2665                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2666         else
2667                 intel_prepare_hdmi_ddi_buffers(encoder, level);
2668
2669         if (IS_GEN9_BC(dev_priv))
2670                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2671
2672         intel_dig_port->set_infoframes(&encoder->base,
2673                                        crtc_state->has_infoframe,
2674                                        crtc_state, conn_state);
2675 }
2676
2677 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2678                                  const struct intel_crtc_state *crtc_state,
2679                                  const struct drm_connector_state *conn_state)
2680 {
2681         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2682         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2683         enum pipe pipe = crtc->pipe;
2684
2685         /*
2686          * When called from DP MST code:
2687          * - conn_state will be NULL
2688          * - encoder will be the main encoder (ie. mst->primary)
2689          * - the main connector associated with this port
2690          *   won't be active or linked to a crtc
2691          * - crtc_state will be the state of the first stream to
2692          *   be activated on this port, and it may not be the same
2693          *   stream that will be deactivated last, but each stream
2694          *   should have a state that is identical when it comes to
2695          *   the DP link parameteres
2696          */
2697
2698         WARN_ON(crtc_state->has_pch_encoder);
2699
2700         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2701
2702         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2703                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2704         else
2705                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
2706 }
2707
2708 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2709 {
2710         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2711         enum port port = encoder->port;
2712         bool wait = false;
2713         u32 val;
2714
2715         val = I915_READ(DDI_BUF_CTL(port));
2716         if (val & DDI_BUF_CTL_ENABLE) {
2717                 val &= ~DDI_BUF_CTL_ENABLE;
2718                 I915_WRITE(DDI_BUF_CTL(port), val);
2719                 wait = true;
2720         }
2721
2722         val = I915_READ(DP_TP_CTL(port));
2723         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2724         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2725         I915_WRITE(DP_TP_CTL(port), val);
2726
2727         if (wait)
2728                 intel_wait_ddi_buf_idle(dev_priv, port);
2729 }
2730
2731 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2732                                       const struct intel_crtc_state *old_crtc_state,
2733                                       const struct drm_connector_state *old_conn_state)
2734 {
2735         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2736         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2737         struct intel_dp *intel_dp = &dig_port->dp;
2738         bool is_mst = intel_crtc_has_type(old_crtc_state,
2739                                           INTEL_OUTPUT_DP_MST);
2740
2741         /*
2742          * Power down sink before disabling the port, otherwise we end
2743          * up getting interrupts from the sink on detecting link loss.
2744          */
2745         if (!is_mst)
2746                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2747
2748         intel_disable_ddi_buf(encoder);
2749
2750         intel_edp_panel_vdd_on(intel_dp);
2751         intel_edp_panel_off(intel_dp);
2752
2753         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2754
2755         intel_ddi_clk_disable(encoder);
2756 }
2757
2758 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2759                                         const struct intel_crtc_state *old_crtc_state,
2760                                         const struct drm_connector_state *old_conn_state)
2761 {
2762         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2763         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2764         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2765
2766         intel_disable_ddi_buf(encoder);
2767
2768         dig_port->set_infoframes(&encoder->base, false,
2769                                  old_crtc_state, old_conn_state);
2770
2771         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2772
2773         intel_ddi_clk_disable(encoder);
2774
2775         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2776 }
2777
2778 static void intel_ddi_post_disable(struct intel_encoder *encoder,
2779                                    const struct intel_crtc_state *old_crtc_state,
2780                                    const struct drm_connector_state *old_conn_state)
2781 {
2782         /*
2783          * When called from DP MST code:
2784          * - old_conn_state will be NULL
2785          * - encoder will be the main encoder (ie. mst->primary)
2786          * - the main connector associated with this port
2787          *   won't be active or linked to a crtc
2788          * - old_crtc_state will be the state of the last stream to
2789          *   be deactivated on this port, and it may not be the same
2790          *   stream that was activated last, but each stream
2791          *   should have a state that is identical when it comes to
2792          *   the DP link parameteres
2793          */
2794
2795         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2796                 intel_ddi_post_disable_hdmi(encoder,
2797                                             old_crtc_state, old_conn_state);
2798         else
2799                 intel_ddi_post_disable_dp(encoder,
2800                                           old_crtc_state, old_conn_state);
2801 }
2802
2803 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2804                                 const struct intel_crtc_state *old_crtc_state,
2805                                 const struct drm_connector_state *old_conn_state)
2806 {
2807         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2808         uint32_t val;
2809
2810         /*
2811          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2812          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2813          * step 13 is the correct place for it. Step 18 is where it was
2814          * originally before the BUN.
2815          */
2816         val = I915_READ(FDI_RX_CTL(PIPE_A));
2817         val &= ~FDI_RX_ENABLE;
2818         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2819
2820         intel_disable_ddi_buf(encoder);
2821         intel_ddi_clk_disable(encoder);
2822
2823         val = I915_READ(FDI_RX_MISC(PIPE_A));
2824         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2825         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2826         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2827
2828         val = I915_READ(FDI_RX_CTL(PIPE_A));
2829         val &= ~FDI_PCDCLK;
2830         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2831
2832         val = I915_READ(FDI_RX_CTL(PIPE_A));
2833         val &= ~FDI_RX_PLL_ENABLE;
2834         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2835 }
2836
2837 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2838                                 const struct intel_crtc_state *crtc_state,
2839                                 const struct drm_connector_state *conn_state)
2840 {
2841         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2842         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2843         enum port port = encoder->port;
2844
2845         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2846                 intel_dp_stop_link_train(intel_dp);
2847
2848         intel_edp_backlight_on(crtc_state, conn_state);
2849         intel_psr_enable(intel_dp, crtc_state);
2850         intel_edp_drrs_enable(intel_dp, crtc_state);
2851
2852         if (crtc_state->has_audio)
2853                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2854 }
2855
2856 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2857                                   const struct intel_crtc_state *crtc_state,
2858                                   const struct drm_connector_state *conn_state)
2859 {
2860         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2861         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2862         struct drm_connector *connector = conn_state->connector;
2863         enum port port = encoder->port;
2864
2865         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2866                                                crtc_state->hdmi_high_tmds_clock_ratio,
2867                                                crtc_state->hdmi_scrambling))
2868                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
2869                           connector->base.id, connector->name);
2870
2871         /* Display WA #1143: skl,kbl,cfl */
2872         if (IS_GEN9_BC(dev_priv)) {
2873                 /*
2874                  * For some reason these chicken bits have been
2875                  * stuffed into a transcoder register, event though
2876                  * the bits affect a specific DDI port rather than
2877                  * a specific transcoder.
2878                  */
2879                 static const enum transcoder port_to_transcoder[] = {
2880                         [PORT_A] = TRANSCODER_EDP,
2881                         [PORT_B] = TRANSCODER_A,
2882                         [PORT_C] = TRANSCODER_B,
2883                         [PORT_D] = TRANSCODER_C,
2884                         [PORT_E] = TRANSCODER_A,
2885                 };
2886                 enum transcoder transcoder = port_to_transcoder[port];
2887                 u32 val;
2888
2889                 val = I915_READ(CHICKEN_TRANS(transcoder));
2890
2891                 if (port == PORT_E)
2892                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2893                                 DDIE_TRAINING_OVERRIDE_VALUE;
2894                 else
2895                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
2896                                 DDI_TRAINING_OVERRIDE_VALUE;
2897
2898                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2899                 POSTING_READ(CHICKEN_TRANS(transcoder));
2900
2901                 udelay(1);
2902
2903                 if (port == PORT_E)
2904                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2905                                  DDIE_TRAINING_OVERRIDE_VALUE);
2906                 else
2907                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2908                                  DDI_TRAINING_OVERRIDE_VALUE);
2909
2910                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2911         }
2912
2913         /* In HDMI/DVI mode, the port width, and swing/emphasis values
2914          * are ignored so nothing special needs to be done besides
2915          * enabling the port.
2916          */
2917         I915_WRITE(DDI_BUF_CTL(port),
2918                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
2919
2920         if (crtc_state->has_audio)
2921                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2922 }
2923
2924 static void intel_enable_ddi(struct intel_encoder *encoder,
2925                              const struct intel_crtc_state *crtc_state,
2926                              const struct drm_connector_state *conn_state)
2927 {
2928         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2929                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
2930         else
2931                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
2932
2933         /* Enable hdcp if it's desired */
2934         if (conn_state->content_protection ==
2935             DRM_MODE_CONTENT_PROTECTION_DESIRED)
2936                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
2937 }
2938
2939 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
2940                                  const struct intel_crtc_state *old_crtc_state,
2941                                  const struct drm_connector_state *old_conn_state)
2942 {
2943         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2944
2945         intel_dp->link_trained = false;
2946
2947         if (old_crtc_state->has_audio)
2948                 intel_audio_codec_disable(encoder,
2949                                           old_crtc_state, old_conn_state);
2950
2951         intel_edp_drrs_disable(intel_dp, old_crtc_state);
2952         intel_psr_disable(intel_dp, old_crtc_state);
2953         intel_edp_backlight_off(old_conn_state);
2954 }
2955
2956 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
2957                                    const struct intel_crtc_state *old_crtc_state,
2958                                    const struct drm_connector_state *old_conn_state)
2959 {
2960         struct drm_connector *connector = old_conn_state->connector;
2961
2962         if (old_crtc_state->has_audio)
2963                 intel_audio_codec_disable(encoder,
2964                                           old_crtc_state, old_conn_state);
2965
2966         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2967                                                false, false))
2968                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
2969                               connector->base.id, connector->name);
2970 }
2971
2972 static void intel_disable_ddi(struct intel_encoder *encoder,
2973                               const struct intel_crtc_state *old_crtc_state,
2974                               const struct drm_connector_state *old_conn_state)
2975 {
2976         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
2977
2978         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2979                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
2980         else
2981                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
2982 }
2983
2984 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2985                                    const struct intel_crtc_state *pipe_config,
2986                                    const struct drm_connector_state *conn_state)
2987 {
2988         uint8_t mask = pipe_config->lane_lat_optim_mask;
2989
2990         bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2991 }
2992
2993 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2994 {
2995         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2996         struct drm_i915_private *dev_priv =
2997                 to_i915(intel_dig_port->base.base.dev);
2998         enum port port = intel_dig_port->base.port;
2999         uint32_t val;
3000         bool wait = false;
3001
3002         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3003                 val = I915_READ(DDI_BUF_CTL(port));
3004                 if (val & DDI_BUF_CTL_ENABLE) {
3005                         val &= ~DDI_BUF_CTL_ENABLE;
3006                         I915_WRITE(DDI_BUF_CTL(port), val);
3007                         wait = true;
3008                 }
3009
3010                 val = I915_READ(DP_TP_CTL(port));
3011                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3012                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3013                 I915_WRITE(DP_TP_CTL(port), val);
3014                 POSTING_READ(DP_TP_CTL(port));
3015
3016                 if (wait)
3017                         intel_wait_ddi_buf_idle(dev_priv, port);
3018         }
3019
3020         val = DP_TP_CTL_ENABLE |
3021               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3022         if (intel_dp->link_mst)
3023                 val |= DP_TP_CTL_MODE_MST;
3024         else {
3025                 val |= DP_TP_CTL_MODE_SST;
3026                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3027                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3028         }
3029         I915_WRITE(DP_TP_CTL(port), val);
3030         POSTING_READ(DP_TP_CTL(port));
3031
3032         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3033         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3034         POSTING_READ(DDI_BUF_CTL(port));
3035
3036         udelay(600);
3037 }
3038
3039 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3040                                        enum transcoder cpu_transcoder)
3041 {
3042         if (cpu_transcoder == TRANSCODER_EDP)
3043                 return false;
3044
3045         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3046                 return false;
3047
3048         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3049                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3050 }
3051
3052 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3053                                          struct intel_crtc_state *crtc_state)
3054 {
3055         if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3056                 crtc_state->min_voltage_level = 2;
3057 }
3058
3059 void intel_ddi_get_config(struct intel_encoder *encoder,
3060                           struct intel_crtc_state *pipe_config)
3061 {
3062         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3063         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3064         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3065         struct intel_digital_port *intel_dig_port;
3066         u32 temp, flags = 0;
3067
3068         /* XXX: DSI transcoder paranoia */
3069         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3070                 return;
3071
3072         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3073         if (temp & TRANS_DDI_PHSYNC)
3074                 flags |= DRM_MODE_FLAG_PHSYNC;
3075         else
3076                 flags |= DRM_MODE_FLAG_NHSYNC;
3077         if (temp & TRANS_DDI_PVSYNC)
3078                 flags |= DRM_MODE_FLAG_PVSYNC;
3079         else
3080                 flags |= DRM_MODE_FLAG_NVSYNC;
3081
3082         pipe_config->base.adjusted_mode.flags |= flags;
3083
3084         switch (temp & TRANS_DDI_BPC_MASK) {
3085         case TRANS_DDI_BPC_6:
3086                 pipe_config->pipe_bpp = 18;
3087                 break;
3088         case TRANS_DDI_BPC_8:
3089                 pipe_config->pipe_bpp = 24;
3090                 break;
3091         case TRANS_DDI_BPC_10:
3092                 pipe_config->pipe_bpp = 30;
3093                 break;
3094         case TRANS_DDI_BPC_12:
3095                 pipe_config->pipe_bpp = 36;
3096                 break;
3097         default:
3098                 break;
3099         }
3100
3101         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3102         case TRANS_DDI_MODE_SELECT_HDMI:
3103                 pipe_config->has_hdmi_sink = true;
3104                 intel_dig_port = enc_to_dig_port(&encoder->base);
3105
3106                 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
3107                         pipe_config->has_infoframe = true;
3108
3109                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3110                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
3111                         pipe_config->hdmi_scrambling = true;
3112                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3113                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3114                 /* fall through */
3115         case TRANS_DDI_MODE_SELECT_DVI:
3116                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3117                 pipe_config->lane_count = 4;
3118                 break;
3119         case TRANS_DDI_MODE_SELECT_FDI:
3120                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3121                 break;
3122         case TRANS_DDI_MODE_SELECT_DP_SST:
3123                 if (encoder->type == INTEL_OUTPUT_EDP)
3124                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3125                 else
3126                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3127                 pipe_config->lane_count =
3128                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3129                 intel_dp_get_m_n(intel_crtc, pipe_config);
3130                 break;
3131         case TRANS_DDI_MODE_SELECT_DP_MST:
3132                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3133                 pipe_config->lane_count =
3134                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3135                 intel_dp_get_m_n(intel_crtc, pipe_config);
3136                 break;
3137         default:
3138                 break;
3139         }
3140
3141         pipe_config->has_audio =
3142                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3143
3144         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3145             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3146                 /*
3147                  * This is a big fat ugly hack.
3148                  *
3149                  * Some machines in UEFI boot mode provide us a VBT that has 18
3150                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3151                  * unknown we fail to light up. Yet the same BIOS boots up with
3152                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3153                  * max, not what it tells us to use.
3154                  *
3155                  * Note: This will still be broken if the eDP panel is not lit
3156                  * up by the BIOS, and thus we can't get the mode at module
3157                  * load.
3158                  */
3159                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3160                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3161                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3162         }
3163
3164         intel_ddi_clock_get(encoder, pipe_config);
3165
3166         if (IS_GEN9_LP(dev_priv))
3167                 pipe_config->lane_lat_optim_mask =
3168                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3169
3170         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3171 }
3172
3173 static enum intel_output_type
3174 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3175                               struct intel_crtc_state *crtc_state,
3176                               struct drm_connector_state *conn_state)
3177 {
3178         switch (conn_state->connector->connector_type) {
3179         case DRM_MODE_CONNECTOR_HDMIA:
3180                 return INTEL_OUTPUT_HDMI;
3181         case DRM_MODE_CONNECTOR_eDP:
3182                 return INTEL_OUTPUT_EDP;
3183         case DRM_MODE_CONNECTOR_DisplayPort:
3184                 return INTEL_OUTPUT_DP;
3185         default:
3186                 MISSING_CASE(conn_state->connector->connector_type);
3187                 return INTEL_OUTPUT_UNUSED;
3188         }
3189 }
3190
3191 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3192                                      struct intel_crtc_state *pipe_config,
3193                                      struct drm_connector_state *conn_state)
3194 {
3195         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3196         enum port port = encoder->port;
3197         int ret;
3198
3199         if (port == PORT_A)
3200                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3201
3202         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3203                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3204         else
3205                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3206
3207         if (IS_GEN9_LP(dev_priv) && ret)
3208                 pipe_config->lane_lat_optim_mask =
3209                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3210
3211         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3212
3213         return ret;
3214
3215 }
3216
3217 static const struct drm_encoder_funcs intel_ddi_funcs = {
3218         .reset = intel_dp_encoder_reset,
3219         .destroy = intel_dp_encoder_destroy,
3220 };
3221
3222 static struct intel_connector *
3223 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3224 {
3225         struct intel_connector *connector;
3226         enum port port = intel_dig_port->base.port;
3227
3228         connector = intel_connector_alloc();
3229         if (!connector)
3230                 return NULL;
3231
3232         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3233         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3234                 kfree(connector);
3235                 return NULL;
3236         }
3237
3238         return connector;
3239 }
3240
3241 static int modeset_pipe(struct drm_crtc *crtc,
3242                         struct drm_modeset_acquire_ctx *ctx)
3243 {
3244         struct drm_atomic_state *state;
3245         struct drm_crtc_state *crtc_state;
3246         int ret;
3247
3248         state = drm_atomic_state_alloc(crtc->dev);
3249         if (!state)
3250                 return -ENOMEM;
3251
3252         state->acquire_ctx = ctx;
3253
3254         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3255         if (IS_ERR(crtc_state)) {
3256                 ret = PTR_ERR(crtc_state);
3257                 goto out;
3258         }
3259
3260         crtc_state->mode_changed = true;
3261
3262         ret = drm_atomic_add_affected_connectors(state, crtc);
3263         if (ret)
3264                 goto out;
3265
3266         ret = drm_atomic_add_affected_planes(state, crtc);
3267         if (ret)
3268                 goto out;
3269
3270         ret = drm_atomic_commit(state);
3271         if (ret)
3272                 goto out;
3273
3274         return 0;
3275
3276  out:
3277         drm_atomic_state_put(state);
3278
3279         return ret;
3280 }
3281
3282 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3283                                  struct drm_modeset_acquire_ctx *ctx)
3284 {
3285         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3286         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3287         struct intel_connector *connector = hdmi->attached_connector;
3288         struct i2c_adapter *adapter =
3289                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3290         struct drm_connector_state *conn_state;
3291         struct intel_crtc_state *crtc_state;
3292         struct intel_crtc *crtc;
3293         u8 config;
3294         int ret;
3295
3296         if (!connector || connector->base.status != connector_status_connected)
3297                 return 0;
3298
3299         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3300                                ctx);
3301         if (ret)
3302                 return ret;
3303
3304         conn_state = connector->base.state;
3305
3306         crtc = to_intel_crtc(conn_state->crtc);
3307         if (!crtc)
3308                 return 0;
3309
3310         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3311         if (ret)
3312                 return ret;
3313
3314         crtc_state = to_intel_crtc_state(crtc->base.state);
3315
3316         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3317
3318         if (!crtc_state->base.active)
3319                 return 0;
3320
3321         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3322             !crtc_state->hdmi_scrambling)
3323                 return 0;
3324
3325         if (conn_state->commit &&
3326             !try_wait_for_completion(&conn_state->commit->hw_done))
3327                 return 0;
3328
3329         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3330         if (ret < 0) {
3331                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3332                 return 0;
3333         }
3334
3335         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3336             crtc_state->hdmi_high_tmds_clock_ratio &&
3337             !!(config & SCDC_SCRAMBLING_ENABLE) ==
3338             crtc_state->hdmi_scrambling)
3339                 return 0;
3340
3341         /*
3342          * HDMI 2.0 says that one should not send scrambled data
3343          * prior to configuring the sink scrambling, and that
3344          * TMDS clock/data transmission should be suspended when
3345          * changing the TMDS clock rate in the sink. So let's
3346          * just do a full modeset here, even though some sinks
3347          * would be perfectly happy if were to just reconfigure
3348          * the SCDC settings on the fly.
3349          */
3350         return modeset_pipe(&crtc->base, ctx);
3351 }
3352
3353 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3354                               struct intel_connector *connector)
3355 {
3356         struct drm_modeset_acquire_ctx ctx;
3357         bool changed;
3358         int ret;
3359
3360         changed = intel_encoder_hotplug(encoder, connector);
3361
3362         drm_modeset_acquire_init(&ctx, 0);
3363
3364         for (;;) {
3365                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3366                         ret = intel_hdmi_reset_link(encoder, &ctx);
3367                 else
3368                         ret = intel_dp_retrain_link(encoder, &ctx);
3369
3370                 if (ret == -EDEADLK) {
3371                         drm_modeset_backoff(&ctx);
3372                         continue;
3373                 }
3374
3375                 break;
3376         }
3377
3378         drm_modeset_drop_locks(&ctx);
3379         drm_modeset_acquire_fini(&ctx);
3380         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3381
3382         return changed;
3383 }
3384
3385 static struct intel_connector *
3386 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3387 {
3388         struct intel_connector *connector;
3389         enum port port = intel_dig_port->base.port;
3390
3391         connector = intel_connector_alloc();
3392         if (!connector)
3393                 return NULL;
3394
3395         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3396         intel_hdmi_init_connector(intel_dig_port, connector);
3397
3398         return connector;
3399 }
3400
3401 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
3402 {
3403         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
3404
3405         if (dport->base.port != PORT_A)
3406                 return false;
3407
3408         if (dport->saved_port_bits & DDI_A_4_LANES)
3409                 return false;
3410
3411         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
3412          *                     supported configuration
3413          */
3414         if (IS_GEN9_LP(dev_priv))
3415                 return true;
3416
3417         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
3418          *             one who does also have a full A/E split called
3419          *             DDI_F what makes DDI_E useless. However for this
3420          *             case let's trust VBT info.
3421          */
3422         if (IS_CANNONLAKE(dev_priv) &&
3423             !intel_bios_is_port_present(dev_priv, PORT_E))
3424                 return true;
3425
3426         return false;
3427 }
3428
3429 static int
3430 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
3431 {
3432         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
3433         enum port port = intel_dport->base.port;
3434         int max_lanes = 4;
3435
3436         if (INTEL_GEN(dev_priv) >= 11)
3437                 return max_lanes;
3438
3439         if (port == PORT_A || port == PORT_E) {
3440                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3441                         max_lanes = port == PORT_A ? 4 : 0;
3442                 else
3443                         /* Both A and E share 2 lanes */
3444                         max_lanes = 2;
3445         }
3446
3447         /*
3448          * Some BIOS might fail to set this bit on port A if eDP
3449          * wasn't lit up at boot.  Force this bit set when needed
3450          * so we use the proper lane count for our calculations.
3451          */
3452         if (intel_ddi_a_force_4_lanes(intel_dport)) {
3453                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3454                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3455                 max_lanes = 4;
3456         }
3457
3458         return max_lanes;
3459 }
3460
3461 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
3462 {
3463         struct intel_digital_port *intel_dig_port;
3464         struct intel_encoder *intel_encoder;
3465         struct drm_encoder *encoder;
3466         bool init_hdmi, init_dp, init_lspcon = false;
3467
3468
3469         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3470                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3471         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3472
3473         if (intel_bios_is_lspcon_present(dev_priv, port)) {
3474                 /*
3475                  * Lspcon device needs to be driven with DP connector
3476                  * with special detection sequence. So make sure DP
3477                  * is initialized before lspcon.
3478                  */
3479                 init_dp = true;
3480                 init_lspcon = true;
3481                 init_hdmi = false;
3482                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3483         }
3484
3485         if (!init_dp && !init_hdmi) {
3486                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3487                               port_name(port));
3488                 return;
3489         }
3490
3491         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3492         if (!intel_dig_port)
3493                 return;
3494
3495         intel_encoder = &intel_dig_port->base;
3496         encoder = &intel_encoder->base;
3497
3498         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
3499                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
3500
3501         intel_encoder->hotplug = intel_ddi_hotplug;
3502         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
3503         intel_encoder->compute_config = intel_ddi_compute_config;
3504         intel_encoder->enable = intel_enable_ddi;
3505         if (IS_GEN9_LP(dev_priv))
3506                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
3507         intel_encoder->pre_enable = intel_ddi_pre_enable;
3508         intel_encoder->disable = intel_disable_ddi;
3509         intel_encoder->post_disable = intel_ddi_post_disable;
3510         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3511         intel_encoder->get_config = intel_ddi_get_config;
3512         intel_encoder->suspend = intel_dp_encoder_suspend;
3513         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3514         intel_encoder->type = INTEL_OUTPUT_DDI;
3515         intel_encoder->power_domain = intel_port_to_power_domain(port);
3516         intel_encoder->port = port;
3517         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3518         intel_encoder->cloneable = 0;
3519
3520         if (INTEL_GEN(dev_priv) >= 11)
3521                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3522                         DDI_BUF_PORT_REVERSAL;
3523         else
3524                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3525                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3526         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3527         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
3528
3529         switch (port) {
3530         case PORT_A:
3531                 intel_dig_port->ddi_io_power_domain =
3532                         POWER_DOMAIN_PORT_DDI_A_IO;
3533                 break;
3534         case PORT_B:
3535                 intel_dig_port->ddi_io_power_domain =
3536                         POWER_DOMAIN_PORT_DDI_B_IO;
3537                 break;
3538         case PORT_C:
3539                 intel_dig_port->ddi_io_power_domain =
3540                         POWER_DOMAIN_PORT_DDI_C_IO;
3541                 break;
3542         case PORT_D:
3543                 intel_dig_port->ddi_io_power_domain =
3544                         POWER_DOMAIN_PORT_DDI_D_IO;
3545                 break;
3546         case PORT_E:
3547                 intel_dig_port->ddi_io_power_domain =
3548                         POWER_DOMAIN_PORT_DDI_E_IO;
3549                 break;
3550         case PORT_F:
3551                 intel_dig_port->ddi_io_power_domain =
3552                         POWER_DOMAIN_PORT_DDI_F_IO;
3553                 break;
3554         default:
3555                 MISSING_CASE(port);
3556         }
3557
3558         intel_infoframe_init(intel_dig_port);
3559
3560         if (init_dp) {
3561                 if (!intel_ddi_init_dp_connector(intel_dig_port))
3562                         goto err;
3563
3564                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3565                 dev_priv->hotplug.irq_port[port] = intel_dig_port;
3566         }
3567
3568         /* In theory we don't need the encoder->type check, but leave it just in
3569          * case we have some really bad VBTs... */
3570         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3571                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3572                         goto err;
3573         }
3574
3575         if (init_lspcon) {
3576                 if (lspcon_init(intel_dig_port))
3577                         /* TODO: handle hdmi info frame part */
3578                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3579                                 port_name(port));
3580                 else
3581                         /*
3582                          * LSPCON init faied, but DP init was success, so
3583                          * lets try to drive as DP++ port.
3584                          */
3585                         DRM_ERROR("LSPCON init failed on port %c\n",
3586                                 port_name(port));
3587         }
3588
3589         return;
3590
3591 err:
3592         drm_encoder_cleanup(encoder);
3593         kfree(intel_dig_port);
3594 }