drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_dp.h"
  36 #include "intel_dp_link_training.h"
  37 #include "intel_dpio_phy.h"
  38 #include "intel_drv.h"
  39 #include "intel_dsi.h"
  40 #include "intel_fifo_underrun.h"
  41 #include "intel_gmbus.h"
  42 #include "intel_hdcp.h"
  43 #include "intel_hdmi.h"
  44 #include "intel_hotplug.h"
  45 #include "intel_lspcon.h"
  46 #include "intel_panel.h"
  47 #include "intel_psr.h"
  48 #include "intel_vdsc.h"
  49
  50 struct ddi_buf_trans {
  51         u32 trans1;     /* balance leg enable, de-emph level */
  52         u32 trans2;     /* vref sel, vswing */
  53         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  54 };
  55
  56 static const u8 index_to_dp_signal_levels[] = {
  57         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  58         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  59         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  60         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  61         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  62         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  63         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  64         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  67 };
  68
  69 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  70  * them for both DP and FDI transports, allowing those ports to
  71  * automatically adapt to HDMI connections as well
  72  */
  73 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  74         { 0x00FFFFFF, 0x0006000E, 0x0 },
  75         { 0x00D75FFF, 0x0005000A, 0x0 },
  76         { 0x00C30FFF, 0x00040006, 0x0 },
  77         { 0x80AAAFFF, 0x000B0000, 0x0 },
  78         { 0x00FFFFFF, 0x0005000A, 0x0 },
  79         { 0x00D75FFF, 0x000C0004, 0x0 },
  80         { 0x80C30FFF, 0x000B0000, 0x0 },
  81         { 0x00FFFFFF, 0x00040006, 0x0 },
  82         { 0x80D75FFF, 0x000B0000, 0x0 },
  83 };
  84
  85 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  86         { 0x00FFFFFF, 0x0007000E, 0x0 },
  87         { 0x00D75FFF, 0x000F000A, 0x0 },
  88         { 0x00C30FFF, 0x00060006, 0x0 },
  89         { 0x00AAAFFF, 0x001E0000, 0x0 },
  90         { 0x00FFFFFF, 0x000F000A, 0x0 },
  91         { 0x00D75FFF, 0x00160004, 0x0 },
  92         { 0x00C30FFF, 0x001E0000, 0x0 },
  93         { 0x00FFFFFF, 0x00060006, 0x0 },
  94         { 0x00D75FFF, 0x001E0000, 0x0 },
  95 };
  96
  97 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  98                                         /* Idx  NT mV d T mV d  db      */
  99         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 100         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 101         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 102         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 103         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 104         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 105         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 106         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 107         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 108         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 109         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 110         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 111 };
 112
 113 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 114         { 0x00FFFFFF, 0x00000012, 0x0 },
 115         { 0x00EBAFFF, 0x00020011, 0x0 },
 116         { 0x00C71FFF, 0x0006000F, 0x0 },
 117         { 0x00AAAFFF, 0x000E000A, 0x0 },
 118         { 0x00FFFFFF, 0x00020011, 0x0 },
 119         { 0x00DB6FFF, 0x0005000F, 0x0 },
 120         { 0x00BEEFFF, 0x000A000C, 0x0 },
 121         { 0x00FFFFFF, 0x0005000F, 0x0 },
 122         { 0x00DB6FFF, 0x000A000C, 0x0 },
 123 };
 124
 125 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 126         { 0x00FFFFFF, 0x0007000E, 0x0 },
 127         { 0x00D75FFF, 0x000E000A, 0x0 },
 128         { 0x00BEFFFF, 0x00140006, 0x0 },
 129         { 0x80B2CFFF, 0x001B0002, 0x0 },
 130         { 0x00FFFFFF, 0x000E000A, 0x0 },
 131         { 0x00DB6FFF, 0x00160005, 0x0 },
 132         { 0x80C71FFF, 0x001A0002, 0x0 },
 133         { 0x00F7DFFF, 0x00180004, 0x0 },
 134         { 0x80D75FFF, 0x001B0002, 0x0 },
 135 };
 136
 137 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 138         { 0x00FFFFFF, 0x0001000E, 0x0 },
 139         { 0x00D75FFF, 0x0004000A, 0x0 },
 140         { 0x00C30FFF, 0x00070006, 0x0 },
 141         { 0x00AAAFFF, 0x000C0000, 0x0 },
 142         { 0x00FFFFFF, 0x0004000A, 0x0 },
 143         { 0x00D75FFF, 0x00090004, 0x0 },
 144         { 0x00C30FFF, 0x000C0000, 0x0 },
 145         { 0x00FFFFFF, 0x00070006, 0x0 },
 146         { 0x00D75FFF, 0x000C0000, 0x0 },
 147 };
 148
 149 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 150                                         /* Idx  NT mV d T mV df db      */
 151         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 152         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 153         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 154         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 155         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 156         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 157         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 158         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 159         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 160         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 161 };
 162
 163 /* Skylake H and S */
 164 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 165         { 0x00002016, 0x000000A0, 0x0 },
 166         { 0x00005012, 0x0000009B, 0x0 },
 167         { 0x00007011, 0x00000088, 0x0 },
 168         { 0x80009010, 0x000000C0, 0x1 },
 169         { 0x00002016, 0x0000009B, 0x0 },
 170         { 0x00005012, 0x00000088, 0x0 },
 171         { 0x80007011, 0x000000C0, 0x1 },
 172         { 0x00002016, 0x000000DF, 0x0 },
 173         { 0x80005012, 0x000000C0, 0x1 },
 174 };
 175
 176 /* Skylake U */
 177 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 178         { 0x0000201B, 0x000000A2, 0x0 },
 179         { 0x00005012, 0x00000088, 0x0 },
 180         { 0x80007011, 0x000000CD, 0x1 },
 181         { 0x80009010, 0x000000C0, 0x1 },
 182         { 0x0000201B, 0x0000009D, 0x0 },
 183         { 0x80005012, 0x000000C0, 0x1 },
 184         { 0x80007011, 0x000000C0, 0x1 },
 185         { 0x00002016, 0x00000088, 0x0 },
 186         { 0x80005012, 0x000000C0, 0x1 },
 187 };
 188
 189 /* Skylake Y */
 190 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 191         { 0x00000018, 0x000000A2, 0x0 },
 192         { 0x00005012, 0x00000088, 0x0 },
 193         { 0x80007011, 0x000000CD, 0x3 },
 194         { 0x80009010, 0x000000C0, 0x3 },
 195         { 0x00000018, 0x0000009D, 0x0 },
 196         { 0x80005012, 0x000000C0, 0x3 },
 197         { 0x80007011, 0x000000C0, 0x3 },
 198         { 0x00000018, 0x00000088, 0x0 },
 199         { 0x80005012, 0x000000C0, 0x3 },
 200 };
 201
 202 /* Kabylake H and S */
 203 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 204         { 0x00002016, 0x000000A0, 0x0 },
 205         { 0x00005012, 0x0000009B, 0x0 },
 206         { 0x00007011, 0x00000088, 0x0 },
 207         { 0x80009010, 0x000000C0, 0x1 },
 208         { 0x00002016, 0x0000009B, 0x0 },
 209         { 0x00005012, 0x00000088, 0x0 },
 210         { 0x80007011, 0x000000C0, 0x1 },
 211         { 0x00002016, 0x00000097, 0x0 },
 212         { 0x80005012, 0x000000C0, 0x1 },
 213 };
 214
 215 /* Kabylake U */
 216 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 217         { 0x0000201B, 0x000000A1, 0x0 },
 218         { 0x00005012, 0x00000088, 0x0 },
 219         { 0x80007011, 0x000000CD, 0x3 },
 220         { 0x80009010, 0x000000C0, 0x3 },
 221         { 0x0000201B, 0x0000009D, 0x0 },
 222         { 0x80005012, 0x000000C0, 0x3 },
 223         { 0x80007011, 0x000000C0, 0x3 },
 224         { 0x00002016, 0x0000004F, 0x0 },
 225         { 0x80005012, 0x000000C0, 0x3 },
 226 };
 227
 228 /* Kabylake Y */
 229 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 230         { 0x00001017, 0x000000A1, 0x0 },
 231         { 0x00005012, 0x00000088, 0x0 },
 232         { 0x80007011, 0x000000CD, 0x3 },
 233         { 0x8000800F, 0x000000C0, 0x3 },
 234         { 0x00001017, 0x0000009D, 0x0 },
 235         { 0x80005012, 0x000000C0, 0x3 },
 236         { 0x80007011, 0x000000C0, 0x3 },
 237         { 0x00001017, 0x0000004C, 0x0 },
 238         { 0x80005012, 0x000000C0, 0x3 },
 239 };
 240
 241 /*
 242  * Skylake/Kabylake H and S
 243  * eDP 1.4 low vswing translation parameters
 244  */
 245 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 246         { 0x00000018, 0x000000A8, 0x0 },
 247         { 0x00004013, 0x000000A9, 0x0 },
 248         { 0x00007011, 0x000000A2, 0x0 },
 249         { 0x00009010, 0x0000009C, 0x0 },
 250         { 0x00000018, 0x000000A9, 0x0 },
 251         { 0x00006013, 0x000000A2, 0x0 },
 252         { 0x00007011, 0x000000A6, 0x0 },
 253         { 0x00000018, 0x000000AB, 0x0 },
 254         { 0x00007013, 0x0000009F, 0x0 },
 255         { 0x00000018, 0x000000DF, 0x0 },
 256 };
 257
 258 /*
 259  * Skylake/Kabylake U
 260  * eDP 1.4 low vswing translation parameters
 261  */
 262 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 263         { 0x00000018, 0x000000A8, 0x0 },
 264         { 0x00004013, 0x000000A9, 0x0 },
 265         { 0x00007011, 0x000000A2, 0x0 },
 266         { 0x00009010, 0x0000009C, 0x0 },
 267         { 0x00000018, 0x000000A9, 0x0 },
 268         { 0x00006013, 0x000000A2, 0x0 },
 269         { 0x00007011, 0x000000A6, 0x0 },
 270         { 0x00002016, 0x000000AB, 0x0 },
 271         { 0x00005013, 0x0000009F, 0x0 },
 272         { 0x00000018, 0x000000DF, 0x0 },
 273 };
 274
 275 /*
 276  * Skylake/Kabylake Y
 277  * eDP 1.4 low vswing translation parameters
 278  */
 279 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 280         { 0x00000018, 0x000000A8, 0x0 },
 281         { 0x00004013, 0x000000AB, 0x0 },
 282         { 0x00007011, 0x000000A4, 0x0 },
 283         { 0x00009010, 0x000000DF, 0x0 },
 284         { 0x00000018, 0x000000AA, 0x0 },
 285         { 0x00006013, 0x000000A4, 0x0 },
 286         { 0x00007011, 0x0000009D, 0x0 },
 287         { 0x00000018, 0x000000A0, 0x0 },
 288         { 0x00006012, 0x000000DF, 0x0 },
 289         { 0x00000018, 0x0000008A, 0x0 },
 290 };
 291
 292 /* Skylake/Kabylake U, H and S */
 293 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 294         { 0x00000018, 0x000000AC, 0x0 },
 295         { 0x00005012, 0x0000009D, 0x0 },
 296         { 0x00007011, 0x00000088, 0x0 },
 297         { 0x00000018, 0x000000A1, 0x0 },
 298         { 0x00000018, 0x00000098, 0x0 },
 299         { 0x00004013, 0x00000088, 0x0 },
 300         { 0x80006012, 0x000000CD, 0x1 },
 301         { 0x00000018, 0x000000DF, 0x0 },
 302         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 303         { 0x80003015, 0x000000C0, 0x1 },
 304         { 0x80000018, 0x000000C0, 0x1 },
 305 };
 306
 307 /* Skylake/Kabylake Y */
 308 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 309         { 0x00000018, 0x000000A1, 0x0 },
 310         { 0x00005012, 0x000000DF, 0x0 },
 311         { 0x80007011, 0x000000CB, 0x3 },
 312         { 0x00000018, 0x000000A4, 0x0 },
 313         { 0x00000018, 0x0000009D, 0x0 },
 314         { 0x00004013, 0x00000080, 0x0 },
 315         { 0x80006013, 0x000000C0, 0x3 },
 316         { 0x00000018, 0x0000008A, 0x0 },
 317         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 318         { 0x80003015, 0x000000C0, 0x3 },
 319         { 0x80000018, 0x000000C0, 0x3 },
 320 };
 321
 322 struct bxt_ddi_buf_trans {
 323         u8 margin;      /* swing value */
 324         u8 scale;       /* scale value */
 325         u8 enable;      /* scale enable */
 326         u8 deemphasis;
 327 };
 328
 329 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 330                                         /* Idx  NT mV diff      db  */
 331         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 332         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 333         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 334         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 335         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 336         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 337         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 338         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 339         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 340         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 341 };
 342
 343 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 344                                         /* Idx  NT mV diff      db  */
 345         { 26, 0, 0, 128, },     /* 0:   200             0   */
 346         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 347         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 348         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 349         { 32, 0, 0, 128, },     /* 4:   250             0   */
 350         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 351         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 352         { 43, 0, 0, 128, },     /* 7:   300             0   */
 353         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 354         { 48, 0, 0, 128, },     /* 9:   300             0   */
 355 };
 356
 357 /* BSpec has 2 recommended values - entries 0 and 8.
 358  * Using the entry with higher vswing.
 359  */
 360 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 361                                         /* Idx  NT mV diff      db  */
 362         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 363         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 364         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 365         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 366         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 367         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 368         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 369         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 370         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 371         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 372 };
 373
 374 struct cnl_ddi_buf_trans {
 375         u8 dw2_swing_sel;
 376         u8 dw7_n_scalar;
 377         u8 dw4_cursor_coeff;
 378         u8 dw4_post_cursor_2;
 379         u8 dw4_post_cursor_1;
 380 };
 381
 382 /* Voltage Swing Programming for VccIO 0.85V for DP */
 383 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 384                                                 /* NT mV Trans mV db    */
 385         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 386         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 387         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 388         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 389         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 390         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 391         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 392         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 393         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 394         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 395 };
 396
 397 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 398 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 399                                                 /* NT mV Trans mV db    */
 400         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 401         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 402         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 403         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 404         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 405         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 406         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 407 };
 408
 409 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 410 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 411                                                 /* NT mV Trans mV db    */
 412         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 413         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 414         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 415         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 416         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 417         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 418         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 419         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 420         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 421 };
 422
 423 /* Voltage Swing Programming for VccIO 0.95V for DP */
 424 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 425                                                 /* NT mV Trans mV db    */
 426         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 427         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 428         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 429         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 430         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 431         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 432         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 433         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 434         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 435         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 436 };
 437
 438 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 439 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 440                                                 /* NT mV Trans mV db    */
 441         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 442         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 443         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 444         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 445         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 446         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 447         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 448         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 449         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 450         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 451         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 452 };
 453
 454 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 455 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 456                                                 /* NT mV Trans mV db    */
 457         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 458         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 459         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 460         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 461         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 462         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 463         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 464         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 465         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 466         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 467 };
 468
 469 /* Voltage Swing Programming for VccIO 1.05V for DP */
 470 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 471                                                 /* NT mV Trans mV db    */
 472         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 473         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 474         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 475         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 476         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 477         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 478         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 479         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 480         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 481         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 482 };
 483
 484 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 485 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 486                                                 /* NT mV Trans mV db    */
 487         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 488         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 489         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 490         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 491         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 492         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 493         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 494         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 495         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 496         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 497         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 498 };
 499
 500 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 501 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 502                                                 /* NT mV Trans mV db    */
 503         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 504         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 505         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 506         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 507         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 508         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 509         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 510         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 511         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 512 };
 513
 514 /* icl_combo_phy_ddi_translations */
 515 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 516                                                 /* NT mV Trans mV db    */
 517         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 518         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 519         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 520         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 521         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 522         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 523         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 524         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 525         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 526         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 527 };
 528
 529 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 530                                                 /* NT mV Trans mV db    */
 531         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 532         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 533         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 534         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 535         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 536         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 537         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 538         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 539         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 540         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 541 };
 542
 543 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 544                                                 /* NT mV Trans mV db    */
 545         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 546         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 547         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 548         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 549         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 550         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 551         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 552         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 553         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 554         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 555 };
 556
 557 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 558                                                 /* NT mV Trans mV db    */
 559         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 560         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 561         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 562         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 563         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 564         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 565         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 566 };
 567
 568 struct icl_mg_phy_ddi_buf_trans {
 569         u32 cri_txdeemph_override_5_0;
 570         u32 cri_txdeemph_override_11_6;
 571         u32 cri_txdeemph_override_17_12;
 572 };
 573
 574 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 575                                 /* Voltage swing  pre-emphasis */
 576         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 577         { 0x0, 0x23, 0x08 },    /* 0              1   */
 578         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 579         { 0x0, 0x00, 0x00 },    /* 0              3   */
 580         { 0x0, 0x23, 0x00 },    /* 1              0   */
 581         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 582         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 583         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 584         { 0x0, 0x33, 0x0C },    /* 2              1   */
 585         { 0x0, 0x00, 0x00 },    /* 3              0   */
 586 };
 587
 588 static const struct ddi_buf_trans *
 589 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 590 {
 591         if (dev_priv->vbt.edp.low_vswing) {
 592                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 593                 return bdw_ddi_translations_edp;
 594         } else {
 595                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 596                 return bdw_ddi_translations_dp;
 597         }
 598 }
 599
 600 static const struct ddi_buf_trans *
 601 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 602 {
 603         if (IS_SKL_ULX(dev_priv)) {
 604                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 605                 return skl_y_ddi_translations_dp;
 606         } else if (IS_SKL_ULT(dev_priv)) {
 607                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 608                 return skl_u_ddi_translations_dp;
 609         } else {
 610                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 611                 return skl_ddi_translations_dp;
 612         }
 613 }
 614
 615 static const struct ddi_buf_trans *
 616 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 617 {
 618         if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 619                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 620                 return kbl_y_ddi_translations_dp;
 621         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 622                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 623                 return kbl_u_ddi_translations_dp;
 624         } else {
 625                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 626                 return kbl_ddi_translations_dp;
 627         }
 628 }
 629
 630 static const struct ddi_buf_trans *
 631 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 632 {
 633         if (dev_priv->vbt.edp.low_vswing) {
 634                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 635                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 636                         return skl_y_ddi_translations_edp;
 637                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 638                            IS_CFL_ULT(dev_priv)) {
 639                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 640                         return skl_u_ddi_translations_edp;
 641                 } else {
 642                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 643                         return skl_ddi_translations_edp;
 644                 }
 645         }
 646
 647         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 648                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 649         else
 650                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 651 }
 652
 653 static const struct ddi_buf_trans *
 654 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 655 {
 656         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 657                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 658                 return skl_y_ddi_translations_hdmi;
 659         } else {
 660                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 661                 return skl_ddi_translations_hdmi;
 662         }
 663 }
 664
 665 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 666 {
 667         /* Only DDIA and DDIE can select the 10th register with DP */
 668         if (port == PORT_A || port == PORT_E)
 669                 return min(n_entries, 10);
 670         else
 671                 return min(n_entries, 9);
 672 }
 673
 674 static const struct ddi_buf_trans *
 675 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 676                            enum port port, int *n_entries)
 677 {
 678         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 679                 const struct ddi_buf_trans *ddi_translations =
 680                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 681                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 682                 return ddi_translations;
 683         } else if (IS_SKYLAKE(dev_priv)) {
 684                 const struct ddi_buf_trans *ddi_translations =
 685                         skl_get_buf_trans_dp(dev_priv, n_entries);
 686                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 687                 return ddi_translations;
 688         } else if (IS_BROADWELL(dev_priv)) {
 689                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 690                 return  bdw_ddi_translations_dp;
 691         } else if (IS_HASWELL(dev_priv)) {
 692                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 693                 return hsw_ddi_translations_dp;
 694         }
 695
 696         *n_entries = 0;
 697         return NULL;
 698 }
 699
 700 static const struct ddi_buf_trans *
 701 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 702                             enum port port, int *n_entries)
 703 {
 704         if (IS_GEN9_BC(dev_priv)) {
 705                 const struct ddi_buf_trans *ddi_translations =
 706                         skl_get_buf_trans_edp(dev_priv, n_entries);
 707                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 708                 return ddi_translations;
 709         } else if (IS_BROADWELL(dev_priv)) {
 710                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 711         } else if (IS_HASWELL(dev_priv)) {
 712                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 713                 return hsw_ddi_translations_dp;
 714         }
 715
 716         *n_entries = 0;
 717         return NULL;
 718 }
 719
 720 static const struct ddi_buf_trans *
 721 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 722                             int *n_entries)
 723 {
 724         if (IS_BROADWELL(dev_priv)) {
 725                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 726                 return bdw_ddi_translations_fdi;
 727         } else if (IS_HASWELL(dev_priv)) {
 728                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 729                 return hsw_ddi_translations_fdi;
 730         }
 731
 732         *n_entries = 0;
 733         return NULL;
 734 }
 735
 736 static const struct ddi_buf_trans *
 737 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 738                              int *n_entries)
 739 {
 740         if (IS_GEN9_BC(dev_priv)) {
 741                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 742         } else if (IS_BROADWELL(dev_priv)) {
 743                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 744                 return bdw_ddi_translations_hdmi;
 745         } else if (IS_HASWELL(dev_priv)) {
 746                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 747                 return hsw_ddi_translations_hdmi;
 748         }
 749
 750         *n_entries = 0;
 751         return NULL;
 752 }
 753
 754 static const struct bxt_ddi_buf_trans *
 755 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 756 {
 757         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 758         return bxt_ddi_translations_dp;
 759 }
 760
 761 static const struct bxt_ddi_buf_trans *
 762 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 763 {
 764         if (dev_priv->vbt.edp.low_vswing) {
 765                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 766                 return bxt_ddi_translations_edp;
 767         }
 768
 769         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 770 }
 771
 772 static const struct bxt_ddi_buf_trans *
 773 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 774 {
 775         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 776         return bxt_ddi_translations_hdmi;
 777 }
 778
 779 static const struct cnl_ddi_buf_trans *
 780 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 781 {
 782         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 783
 784         if (voltage == VOLTAGE_INFO_0_85V) {
 785                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 786                 return cnl_ddi_translations_hdmi_0_85V;
 787         } else if (voltage == VOLTAGE_INFO_0_95V) {
 788                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 789                 return cnl_ddi_translations_hdmi_0_95V;
 790         } else if (voltage == VOLTAGE_INFO_1_05V) {
 791                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 792                 return cnl_ddi_translations_hdmi_1_05V;
 793         } else {
 794                 *n_entries = 1; /* shut up gcc */
 795                 MISSING_CASE(voltage);
 796         }
 797         return NULL;
 798 }
 799
 800 static const struct cnl_ddi_buf_trans *
 801 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 802 {
 803         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 804
 805         if (voltage == VOLTAGE_INFO_0_85V) {
 806                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 807                 return cnl_ddi_translations_dp_0_85V;
 808         } else if (voltage == VOLTAGE_INFO_0_95V) {
 809                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 810                 return cnl_ddi_translations_dp_0_95V;
 811         } else if (voltage == VOLTAGE_INFO_1_05V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 813                 return cnl_ddi_translations_dp_1_05V;
 814         } else {
 815                 *n_entries = 1; /* shut up gcc */
 816                 MISSING_CASE(voltage);
 817         }
 818         return NULL;
 819 }
 820
 821 static const struct cnl_ddi_buf_trans *
 822 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 823 {
 824         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 825
 826         if (dev_priv->vbt.edp.low_vswing) {
 827                 if (voltage == VOLTAGE_INFO_0_85V) {
 828                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 829                         return cnl_ddi_translations_edp_0_85V;
 830                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 831                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 832                         return cnl_ddi_translations_edp_0_95V;
 833                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 834                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 835                         return cnl_ddi_translations_edp_1_05V;
 836                 } else {
 837                         *n_entries = 1; /* shut up gcc */
 838                         MISSING_CASE(voltage);
 839                 }
 840                 return NULL;
 841         } else {
 842                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 843         }
 844 }
 845
 846 static const struct cnl_ddi_buf_trans *
 847 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 848                         int type, int rate, int *n_entries)
 849 {
 850         if (type == INTEL_OUTPUT_HDMI) {
 851                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 852                 return icl_combo_phy_ddi_translations_hdmi;
 853         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 854                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 855                 return icl_combo_phy_ddi_translations_edp_hbr3;
 856         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 857                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 858                 return icl_combo_phy_ddi_translations_edp_hbr2;
 859         }
 860
 861         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 862         return icl_combo_phy_ddi_translations_dp_hbr2;
 863 }
 864
 865 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 866 {
 867         int n_entries, level, default_entry;
 868
 869         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 870
 871         if (INTEL_GEN(dev_priv) >= 11) {
 872                 if (intel_port_is_combophy(dev_priv, port))
 873                         icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
 874                                                 0, &n_entries);
 875                 else
 876                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 877                 default_entry = n_entries - 1;
 878         } else if (IS_CANNONLAKE(dev_priv)) {
 879                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 880                 default_entry = n_entries - 1;
 881         } else if (IS_GEN9_LP(dev_priv)) {
 882                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 883                 default_entry = n_entries - 1;
 884         } else if (IS_GEN9_BC(dev_priv)) {
 885                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 886                 default_entry = 8;
 887         } else if (IS_BROADWELL(dev_priv)) {
 888                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 889                 default_entry = 7;
 890         } else if (IS_HASWELL(dev_priv)) {
 891                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 892                 default_entry = 6;
 893         } else {
 894                 WARN(1, "ddi translation table missing\n");
 895                 return 0;
 896         }
 897
 898         /* Choose a good default if VBT is badly populated */
 899         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 900                 level = default_entry;
 901
 902         if (WARN_ON_ONCE(n_entries == 0))
 903                 return 0;
 904         if (WARN_ON_ONCE(level >= n_entries))
 905                 level = n_entries - 1;
 906
 907         return level;
 908 }
 909
 910 /*
 911  * Starting with Haswell, DDI port buffers must be programmed with correct
 912  * values in advance. This function programs the correct values for
 913  * DP/eDP/FDI use cases.
 914  */
 915 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 916                                          const struct intel_crtc_state *crtc_state)
 917 {
 918         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 919         u32 iboost_bit = 0;
 920         int i, n_entries;
 921         enum port port = encoder->port;
 922         const struct ddi_buf_trans *ddi_translations;
 923
 924         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 925                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 926                                                                &n_entries);
 927         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 928                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 929                                                                &n_entries);
 930         else
 931                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 932                                                               &n_entries);
 933
 934         /* If we're boosting the current, set bit 31 of trans1 */
 935         if (IS_GEN9_BC(dev_priv) &&
 936             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 937                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 938
 939         for (i = 0; i < n_entries; i++) {
 940                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 941                            ddi_translations[i].trans1 | iboost_bit);
 942                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 943                            ddi_translations[i].trans2);
 944         }
 945 }
 946
 947 /*
 948  * Starting with Haswell, DDI port buffers must be programmed with correct
 949  * values in advance. This function programs the correct values for
 950  * HDMI/DVI use cases.
 951  */
 952 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 953                                            int level)
 954 {
 955         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 956         u32 iboost_bit = 0;
 957         int n_entries;
 958         enum port port = encoder->port;
 959         const struct ddi_buf_trans *ddi_translations;
 960
 961         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 962
 963         if (WARN_ON_ONCE(!ddi_translations))
 964                 return;
 965         if (WARN_ON_ONCE(level >= n_entries))
 966                 level = n_entries - 1;
 967
 968         /* If we're boosting the current, set bit 31 of trans1 */
 969         if (IS_GEN9_BC(dev_priv) &&
 970             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 971                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 972
 973         /* Entry 9 is for HDMI: */
 974         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 975                    ddi_translations[level].trans1 | iboost_bit);
 976         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 977                    ddi_translations[level].trans2);
 978 }
 979
 980 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 981                                     enum port port)
 982 {
 983         i915_reg_t reg = DDI_BUF_CTL(port);
 984         int i;
 985
 986         for (i = 0; i < 16; i++) {
 987                 udelay(1);
 988                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 989                         return;
 990         }
 991         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 992 }
 993
 994 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 995 {
 996         switch (pll->info->id) {
 997         case DPLL_ID_WRPLL1:
 998                 return PORT_CLK_SEL_WRPLL1;
 999         case DPLL_ID_WRPLL2:
1000                 return PORT_CLK_SEL_WRPLL2;
1001         case DPLL_ID_SPLL:
1002                 return PORT_CLK_SEL_SPLL;
1003         case DPLL_ID_LCPLL_810:
1004                 return PORT_CLK_SEL_LCPLL_810;
1005         case DPLL_ID_LCPLL_1350:
1006                 return PORT_CLK_SEL_LCPLL_1350;
1007         case DPLL_ID_LCPLL_2700:
1008                 return PORT_CLK_SEL_LCPLL_2700;
1009         default:
1010                 MISSING_CASE(pll->info->id);
1011                 return PORT_CLK_SEL_NONE;
1012         }
1013 }
1014
1015 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1016                                   const struct intel_crtc_state *crtc_state)
1017 {
1018         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1019         int clock = crtc_state->port_clock;
1020         const enum intel_dpll_id id = pll->info->id;
1021
1022         switch (id) {
1023         default:
1024                 /*
1025                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1026                  * here, so do warn if this get passed in
1027                  */
1028                 MISSING_CASE(id);
1029                 return DDI_CLK_SEL_NONE;
1030         case DPLL_ID_ICL_TBTPLL:
1031                 switch (clock) {
1032                 case 162000:
1033                         return DDI_CLK_SEL_TBT_162;
1034                 case 270000:
1035                         return DDI_CLK_SEL_TBT_270;
1036                 case 540000:
1037                         return DDI_CLK_SEL_TBT_540;
1038                 case 810000:
1039                         return DDI_CLK_SEL_TBT_810;
1040                 default:
1041                         MISSING_CASE(clock);
1042                         return DDI_CLK_SEL_NONE;
1043                 }
1044         case DPLL_ID_ICL_MGPLL1:
1045         case DPLL_ID_ICL_MGPLL2:
1046         case DPLL_ID_ICL_MGPLL3:
1047         case DPLL_ID_ICL_MGPLL4:
1048                 return DDI_CLK_SEL_MG;
1049         }
1050 }
1051
1052 /* Starting with Haswell, different DDI ports can work in FDI mode for
1053  * connection to the PCH-located connectors. For this, it is necessary to train
1054  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1055  *
1056  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1057  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1058  * DDI A (which is used for eDP)
1059  */
1060
1061 void hsw_fdi_link_train(struct intel_crtc *crtc,
1062                         const struct intel_crtc_state *crtc_state)
1063 {
1064         struct drm_device *dev = crtc->base.dev;
1065         struct drm_i915_private *dev_priv = to_i915(dev);
1066         struct intel_encoder *encoder;
1067         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1068
1069         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1070                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1071                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1072         }
1073
1074         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1075          * mode set "sequence for CRT port" document:
1076          * - TP1 to TP2 time with the default value
1077          * - FDI delay to 90h
1078          *
1079          * WaFDIAutoLinkSetTimingOverrride:hsw
1080          */
1081         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1082                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1083                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1084
1085         /* Enable the PCH Receiver FDI PLL */
1086         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1087                      FDI_RX_PLL_ENABLE |
1088                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1089         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1090         POSTING_READ(FDI_RX_CTL(PIPE_A));
1091         udelay(220);
1092
1093         /* Switch from Rawclk to PCDclk */
1094         rx_ctl_val |= FDI_PCDCLK;
1095         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1096
1097         /* Configure Port Clock Select */
1098         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1099         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1100         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1101
1102         /* Start the training iterating through available voltages and emphasis,
1103          * testing each value twice. */
1104         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1105                 /* Configure DP_TP_CTL with auto-training */
1106                 I915_WRITE(DP_TP_CTL(PORT_E),
1107                                         DP_TP_CTL_FDI_AUTOTRAIN |
1108                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1109                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1110                                         DP_TP_CTL_ENABLE);
1111
1112                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1113                  * DDI E does not support port reversal, the functionality is
1114                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1115                  * port reversal bit */
1116                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1117                            DDI_BUF_CTL_ENABLE |
1118                            ((crtc_state->fdi_lanes - 1) << 1) |
1119                            DDI_BUF_TRANS_SELECT(i / 2));
1120                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1121
1122                 udelay(600);
1123
1124                 /* Program PCH FDI Receiver TU */
1125                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1126
1127                 /* Enable PCH FDI Receiver with auto-training */
1128                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1129                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1130                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1131
1132                 /* Wait for FDI receiver lane calibration */
1133                 udelay(30);
1134
1135                 /* Unset FDI_RX_MISC pwrdn lanes */
1136                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1137                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1138                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1139                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1140
1141                 /* Wait for FDI auto training time */
1142                 udelay(5);
1143
1144                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1145                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1146                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1147                         break;
1148                 }
1149
1150                 /*
1151                  * Leave things enabled even if we failed to train FDI.
1152                  * Results in less fireworks from the state checker.
1153                  */
1154                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1155                         DRM_ERROR("FDI link training failed!\n");
1156                         break;
1157                 }
1158
1159                 rx_ctl_val &= ~FDI_RX_ENABLE;
1160                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1161                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1162
1163                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1164                 temp &= ~DDI_BUF_CTL_ENABLE;
1165                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1166                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1167
1168                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1169                 temp = I915_READ(DP_TP_CTL(PORT_E));
1170                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1171                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1172                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1173                 POSTING_READ(DP_TP_CTL(PORT_E));
1174
1175                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1176
1177                 /* Reset FDI_RX_MISC pwrdn lanes */
1178                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1179                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1180                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1181                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1182                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1183         }
1184
1185         /* Enable normal pixel sending for FDI */
1186         I915_WRITE(DP_TP_CTL(PORT_E),
1187                    DP_TP_CTL_FDI_AUTOTRAIN |
1188                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1189                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1190                    DP_TP_CTL_ENABLE);
1191 }
1192
1193 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1194 {
1195         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1196         struct intel_digital_port *intel_dig_port =
1197                 enc_to_dig_port(&encoder->base);
1198
1199         intel_dp->DP = intel_dig_port->saved_port_bits |
1200                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1201         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1202 }
1203
1204 static struct intel_encoder *
1205 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1206 {
1207         struct drm_device *dev = crtc->base.dev;
1208         struct intel_encoder *encoder, *ret = NULL;
1209         int num_encoders = 0;
1210
1211         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1212                 ret = encoder;
1213                 num_encoders++;
1214         }
1215
1216         if (num_encoders != 1)
1217                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1218                      pipe_name(crtc->pipe));
1219
1220         BUG_ON(ret == NULL);
1221         return ret;
1222 }
1223
1224 #define LC_FREQ 2700
1225
1226 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1227                                    i915_reg_t reg)
1228 {
1229         int refclk = LC_FREQ;
1230         int n, p, r;
1231         u32 wrpll;
1232
1233         wrpll = I915_READ(reg);
1234         switch (wrpll & WRPLL_PLL_REF_MASK) {
1235         case WRPLL_PLL_SSC:
1236         case WRPLL_PLL_NON_SSC:
1237                 /*
1238                  * We could calculate spread here, but our checking
1239                  * code only cares about 5% accuracy, and spread is a max of
1240                  * 0.5% downspread.
1241                  */
1242                 refclk = 135;
1243                 break;
1244         case WRPLL_PLL_LCPLL:
1245                 refclk = LC_FREQ;
1246                 break;
1247         default:
1248                 WARN(1, "bad wrpll refclk\n");
1249                 return 0;
1250         }
1251
1252         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1253         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1254         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1255
1256         /* Convert to KHz, p & r have a fixed point portion */
1257         return (refclk * n * 100) / (p * r);
1258 }
1259
1260 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1261 {
1262         u32 p0, p1, p2, dco_freq;
1263
1264         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1265         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1266
1267         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1268                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1269         else
1270                 p1 = 1;
1271
1272
1273         switch (p0) {
1274         case DPLL_CFGCR2_PDIV_1:
1275                 p0 = 1;
1276                 break;
1277         case DPLL_CFGCR2_PDIV_2:
1278                 p0 = 2;
1279                 break;
1280         case DPLL_CFGCR2_PDIV_3:
1281                 p0 = 3;
1282                 break;
1283         case DPLL_CFGCR2_PDIV_7:
1284                 p0 = 7;
1285                 break;
1286         }
1287
1288         switch (p2) {
1289         case DPLL_CFGCR2_KDIV_5:
1290                 p2 = 5;
1291                 break;
1292         case DPLL_CFGCR2_KDIV_2:
1293                 p2 = 2;
1294                 break;
1295         case DPLL_CFGCR2_KDIV_3:
1296                 p2 = 3;
1297                 break;
1298         case DPLL_CFGCR2_KDIV_1:
1299                 p2 = 1;
1300                 break;
1301         }
1302
1303         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1304                 * 24 * 1000;
1305
1306         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1307                      * 24 * 1000) / 0x8000;
1308
1309         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1310                 return 0;
1311
1312         return dco_freq / (p0 * p1 * p2 * 5);
1313 }
1314
1315 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1316                         struct intel_dpll_hw_state *pll_state)
1317 {
1318         u32 p0, p1, p2, dco_freq, ref_clock;
1319
1320         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1321         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1322
1323         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1324                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1325                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1326         else
1327                 p1 = 1;
1328
1329
1330         switch (p0) {
1331         case DPLL_CFGCR1_PDIV_2:
1332                 p0 = 2;
1333                 break;
1334         case DPLL_CFGCR1_PDIV_3:
1335                 p0 = 3;
1336                 break;
1337         case DPLL_CFGCR1_PDIV_5:
1338                 p0 = 5;
1339                 break;
1340         case DPLL_CFGCR1_PDIV_7:
1341                 p0 = 7;
1342                 break;
1343         }
1344
1345         switch (p2) {
1346         case DPLL_CFGCR1_KDIV_1:
1347                 p2 = 1;
1348                 break;
1349         case DPLL_CFGCR1_KDIV_2:
1350                 p2 = 2;
1351                 break;
1352         case DPLL_CFGCR1_KDIV_3:
1353                 p2 = 3;
1354                 break;
1355         }
1356
1357         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1358
1359         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1360                 * ref_clock;
1361
1362         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1363                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1364
1365         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1366                 return 0;
1367
1368         return dco_freq / (p0 * p1 * p2 * 5);
1369 }
1370
1371 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1372                                  enum port port)
1373 {
1374         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1375
1376         switch (val) {
1377         case DDI_CLK_SEL_NONE:
1378                 return 0;
1379         case DDI_CLK_SEL_TBT_162:
1380                 return 162000;
1381         case DDI_CLK_SEL_TBT_270:
1382                 return 270000;
1383         case DDI_CLK_SEL_TBT_540:
1384                 return 540000;
1385         case DDI_CLK_SEL_TBT_810:
1386                 return 810000;
1387         default:
1388                 MISSING_CASE(val);
1389                 return 0;
1390         }
1391 }
1392
1393 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1394                                 const struct intel_dpll_hw_state *pll_state)
1395 {
1396         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1397         u64 tmp;
1398
1399         ref_clock = dev_priv->cdclk.hw.ref;
1400
1401         m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1402         m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1403         m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1404                 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1405                 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1406
1407         switch (pll_state->mg_clktop2_hsclkctl &
1408                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1409         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1410                 div1 = 2;
1411                 break;
1412         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1413                 div1 = 3;
1414                 break;
1415         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1416                 div1 = 5;
1417                 break;
1418         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1419                 div1 = 7;
1420                 break;
1421         default:
1422                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1423                 return 0;
1424         }
1425
1426         div2 = (pll_state->mg_clktop2_hsclkctl &
1427                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1428                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1429
1430         /* div2 value of 0 is same as 1 means no div */
1431         if (div2 == 0)
1432                 div2 = 1;
1433
1434         /*
1435          * Adjust the original formula to delay the division by 2^22 in order to
1436          * minimize possible rounding errors.
1437          */
1438         tmp = (u64)m1 * m2_int * ref_clock +
1439               (((u64)m1 * m2_frac * ref_clock) >> 22);
1440         tmp = div_u64(tmp, 5 * div1 * div2);
1441
1442         return tmp;
1443 }
1444
1445 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1446 {
1447         int dotclock;
1448
1449         if (pipe_config->has_pch_encoder)
1450                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1451                                                     &pipe_config->fdi_m_n);
1452         else if (intel_crtc_has_dp_encoder(pipe_config))
1453                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1454                                                     &pipe_config->dp_m_n);
1455         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1456                 dotclock = pipe_config->port_clock * 2 / 3;
1457         else
1458                 dotclock = pipe_config->port_clock;
1459
1460         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1461                 dotclock *= 2;
1462
1463         if (pipe_config->pixel_multiplier)
1464                 dotclock /= pipe_config->pixel_multiplier;
1465
1466         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1467 }
1468
1469 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1470                               struct intel_crtc_state *pipe_config)
1471 {
1472         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1473         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1474         enum port port = encoder->port;
1475         int link_clock;
1476
1477         if (intel_port_is_combophy(dev_priv, port)) {
1478                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1479         } else {
1480                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1481                                                 pipe_config->shared_dpll);
1482
1483                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1484                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1485                 else
1486                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1487         }
1488
1489         pipe_config->port_clock = link_clock;
1490
1491         ddi_dotclock_get(pipe_config);
1492 }
1493
1494 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1495                               struct intel_crtc_state *pipe_config)
1496 {
1497         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1498         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1499         int link_clock;
1500
1501         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1502                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1503         } else {
1504                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1505
1506                 switch (link_clock) {
1507                 case DPLL_CFGCR0_LINK_RATE_810:
1508                         link_clock = 81000;
1509                         break;
1510                 case DPLL_CFGCR0_LINK_RATE_1080:
1511                         link_clock = 108000;
1512                         break;
1513                 case DPLL_CFGCR0_LINK_RATE_1350:
1514                         link_clock = 135000;
1515                         break;
1516                 case DPLL_CFGCR0_LINK_RATE_1620:
1517                         link_clock = 162000;
1518                         break;
1519                 case DPLL_CFGCR0_LINK_RATE_2160:
1520                         link_clock = 216000;
1521                         break;
1522                 case DPLL_CFGCR0_LINK_RATE_2700:
1523                         link_clock = 270000;
1524                         break;
1525                 case DPLL_CFGCR0_LINK_RATE_3240:
1526                         link_clock = 324000;
1527                         break;
1528                 case DPLL_CFGCR0_LINK_RATE_4050:
1529                         link_clock = 405000;
1530                         break;
1531                 default:
1532                         WARN(1, "Unsupported link rate\n");
1533                         break;
1534                 }
1535                 link_clock *= 2;
1536         }
1537
1538         pipe_config->port_clock = link_clock;
1539
1540         ddi_dotclock_get(pipe_config);
1541 }
1542
1543 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1544                               struct intel_crtc_state *pipe_config)
1545 {
1546         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1547         int link_clock;
1548
1549         /*
1550          * ctrl1 register is already shifted for each pll, just use 0 to get
1551          * the internal shift for each field
1552          */
1553         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1554                 link_clock = skl_calc_wrpll_link(pll_state);
1555         } else {
1556                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1557                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1558
1559                 switch (link_clock) {
1560                 case DPLL_CTRL1_LINK_RATE_810:
1561                         link_clock = 81000;
1562                         break;
1563                 case DPLL_CTRL1_LINK_RATE_1080:
1564                         link_clock = 108000;
1565                         break;
1566                 case DPLL_CTRL1_LINK_RATE_1350:
1567                         link_clock = 135000;
1568                         break;
1569                 case DPLL_CTRL1_LINK_RATE_1620:
1570                         link_clock = 162000;
1571                         break;
1572                 case DPLL_CTRL1_LINK_RATE_2160:
1573                         link_clock = 216000;
1574                         break;
1575                 case DPLL_CTRL1_LINK_RATE_2700:
1576                         link_clock = 270000;
1577                         break;
1578                 default:
1579                         WARN(1, "Unsupported link rate\n");
1580                         break;
1581                 }
1582                 link_clock *= 2;
1583         }
1584
1585         pipe_config->port_clock = link_clock;
1586
1587         ddi_dotclock_get(pipe_config);
1588 }
1589
1590 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1591                               struct intel_crtc_state *pipe_config)
1592 {
1593         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1594         int link_clock = 0;
1595         u32 val, pll;
1596
1597         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1598         switch (val & PORT_CLK_SEL_MASK) {
1599         case PORT_CLK_SEL_LCPLL_810:
1600                 link_clock = 81000;
1601                 break;
1602         case PORT_CLK_SEL_LCPLL_1350:
1603                 link_clock = 135000;
1604                 break;
1605         case PORT_CLK_SEL_LCPLL_2700:
1606                 link_clock = 270000;
1607                 break;
1608         case PORT_CLK_SEL_WRPLL1:
1609                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1610                 break;
1611         case PORT_CLK_SEL_WRPLL2:
1612                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1613                 break;
1614         case PORT_CLK_SEL_SPLL:
1615                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1616                 if (pll == SPLL_PLL_FREQ_810MHz)
1617                         link_clock = 81000;
1618                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1619                         link_clock = 135000;
1620                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1621                         link_clock = 270000;
1622                 else {
1623                         WARN(1, "bad spll freq\n");
1624                         return;
1625                 }
1626                 break;
1627         default:
1628                 WARN(1, "bad port clock sel\n");
1629                 return;
1630         }
1631
1632         pipe_config->port_clock = link_clock * 2;
1633
1634         ddi_dotclock_get(pipe_config);
1635 }
1636
1637 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1638 {
1639         struct dpll clock;
1640
1641         clock.m1 = 2;
1642         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1643         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1644                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1645         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1646         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1647         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1648
1649         return chv_calc_dpll_params(100000, &clock);
1650 }
1651
1652 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1653                               struct intel_crtc_state *pipe_config)
1654 {
1655         pipe_config->port_clock =
1656                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1657
1658         ddi_dotclock_get(pipe_config);
1659 }
1660
1661 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1662                                 struct intel_crtc_state *pipe_config)
1663 {
1664         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1665
1666         if (INTEL_GEN(dev_priv) >= 11)
1667                 icl_ddi_clock_get(encoder, pipe_config);
1668         else if (IS_CANNONLAKE(dev_priv))
1669                 cnl_ddi_clock_get(encoder, pipe_config);
1670         else if (IS_GEN9_LP(dev_priv))
1671                 bxt_ddi_clock_get(encoder, pipe_config);
1672         else if (IS_GEN9_BC(dev_priv))
1673                 skl_ddi_clock_get(encoder, pipe_config);
1674         else if (INTEL_GEN(dev_priv) <= 8)
1675                 hsw_ddi_clock_get(encoder, pipe_config);
1676 }
1677
1678 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1679 {
1680         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1681         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1682         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1683         u32 temp;
1684
1685         if (!intel_crtc_has_dp_encoder(crtc_state))
1686                 return;
1687
1688         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1689
1690         temp = TRANS_MSA_SYNC_CLK;
1691
1692         if (crtc_state->limited_color_range)
1693                 temp |= TRANS_MSA_CEA_RANGE;
1694
1695         switch (crtc_state->pipe_bpp) {
1696         case 18:
1697                 temp |= TRANS_MSA_6_BPC;
1698                 break;
1699         case 24:
1700                 temp |= TRANS_MSA_8_BPC;
1701                 break;
1702         case 30:
1703                 temp |= TRANS_MSA_10_BPC;
1704                 break;
1705         case 36:
1706                 temp |= TRANS_MSA_12_BPC;
1707                 break;
1708         default:
1709                 MISSING_CASE(crtc_state->pipe_bpp);
1710                 break;
1711         }
1712
1713         /*
1714          * As per DP 1.2 spec section 2.3.4.3 while sending
1715          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1716          * colorspace information. The output colorspace encoding is BT601.
1717          */
1718         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1719                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1720         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1721 }
1722
1723 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1724                                     bool state)
1725 {
1726         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1727         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1728         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1729         u32 temp;
1730
1731         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1732         if (state == true)
1733                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1734         else
1735                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1736         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1737 }
1738
1739 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1740 {
1741         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1742         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1743         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1744         enum pipe pipe = crtc->pipe;
1745         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1746         enum port port = encoder->port;
1747         u32 temp;
1748
1749         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1750         temp = TRANS_DDI_FUNC_ENABLE;
1751         temp |= TRANS_DDI_SELECT_PORT(port);
1752
1753         switch (crtc_state->pipe_bpp) {
1754         case 18:
1755                 temp |= TRANS_DDI_BPC_6;
1756                 break;
1757         case 24:
1758                 temp |= TRANS_DDI_BPC_8;
1759                 break;
1760         case 30:
1761                 temp |= TRANS_DDI_BPC_10;
1762                 break;
1763         case 36:
1764                 temp |= TRANS_DDI_BPC_12;
1765                 break;
1766         default:
1767                 BUG();
1768         }
1769
1770         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1771                 temp |= TRANS_DDI_PVSYNC;
1772         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1773                 temp |= TRANS_DDI_PHSYNC;
1774
1775         if (cpu_transcoder == TRANSCODER_EDP) {
1776                 switch (pipe) {
1777                 case PIPE_A:
1778                         /* On Haswell, can only use the always-on power well for
1779                          * eDP when not using the panel fitter, and when not
1780                          * using motion blur mitigation (which we don't
1781                          * support). */
1782                         if (IS_HASWELL(dev_priv) &&
1783                             (crtc_state->pch_pfit.enabled ||
1784                              crtc_state->pch_pfit.force_thru))
1785                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1786                         else
1787                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1788                         break;
1789                 case PIPE_B:
1790                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1791                         break;
1792                 case PIPE_C:
1793                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1794                         break;
1795                 default:
1796                         BUG();
1797                         break;
1798                 }
1799         }
1800
1801         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1802                 if (crtc_state->has_hdmi_sink)
1803                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1804                 else
1805                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1806
1807                 if (crtc_state->hdmi_scrambling)
1808                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1809                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1810                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1811         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1812                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1813                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1814         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1815                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1816                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1817         } else {
1818                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1819                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1820         }
1821
1822         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1823 }
1824
1825 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1826 {
1827         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1828         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1829         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1830         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1831         u32 val = I915_READ(reg);
1832
1833         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1834         val |= TRANS_DDI_PORT_NONE;
1835         I915_WRITE(reg, val);
1836
1837         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1838             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1839                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1840                 /* Quirk time at 100ms for reliable operation */
1841                 msleep(100);
1842         }
1843 }
1844
1845 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1846                                      bool enable)
1847 {
1848         struct drm_device *dev = intel_encoder->base.dev;
1849         struct drm_i915_private *dev_priv = to_i915(dev);
1850         intel_wakeref_t wakeref;
1851         enum pipe pipe = 0;
1852         int ret = 0;
1853         u32 tmp;
1854
1855         wakeref = intel_display_power_get_if_enabled(dev_priv,
1856                                                      intel_encoder->power_domain);
1857         if (WARN_ON(!wakeref))
1858                 return -ENXIO;
1859
1860         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1861                 ret = -EIO;
1862                 goto out;
1863         }
1864
1865         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1866         if (enable)
1867                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1868         else
1869                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1870         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1871 out:
1872         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1873         return ret;
1874 }
1875
1876 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1877 {
1878         struct drm_device *dev = intel_connector->base.dev;
1879         struct drm_i915_private *dev_priv = to_i915(dev);
1880         struct intel_encoder *encoder = intel_connector->encoder;
1881         int type = intel_connector->base.connector_type;
1882         enum port port = encoder->port;
1883         enum transcoder cpu_transcoder;
1884         intel_wakeref_t wakeref;
1885         enum pipe pipe = 0;
1886         u32 tmp;
1887         bool ret;
1888
1889         wakeref = intel_display_power_get_if_enabled(dev_priv,
1890                                                      encoder->power_domain);
1891         if (!wakeref)
1892                 return false;
1893
1894         if (!encoder->get_hw_state(encoder, &pipe)) {
1895                 ret = false;
1896                 goto out;
1897         }
1898
1899         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1900                 cpu_transcoder = TRANSCODER_EDP;
1901         else
1902                 cpu_transcoder = (enum transcoder) pipe;
1903
1904         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1905
1906         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1907         case TRANS_DDI_MODE_SELECT_HDMI:
1908         case TRANS_DDI_MODE_SELECT_DVI:
1909                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1910                 break;
1911
1912         case TRANS_DDI_MODE_SELECT_DP_SST:
1913                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1914                       type == DRM_MODE_CONNECTOR_DisplayPort;
1915                 break;
1916
1917         case TRANS_DDI_MODE_SELECT_DP_MST:
1918                 /* if the transcoder is in MST state then
1919                  * connector isn't connected */
1920                 ret = false;
1921                 break;
1922
1923         case TRANS_DDI_MODE_SELECT_FDI:
1924                 ret = type == DRM_MODE_CONNECTOR_VGA;
1925                 break;
1926
1927         default:
1928                 ret = false;
1929                 break;
1930         }
1931
1932 out:
1933         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1934
1935         return ret;
1936 }
1937
1938 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1939                                         u8 *pipe_mask, bool *is_dp_mst)
1940 {
1941         struct drm_device *dev = encoder->base.dev;
1942         struct drm_i915_private *dev_priv = to_i915(dev);
1943         enum port port = encoder->port;
1944         intel_wakeref_t wakeref;
1945         enum pipe p;
1946         u32 tmp;
1947         u8 mst_pipe_mask;
1948
1949         *pipe_mask = 0;
1950         *is_dp_mst = false;
1951
1952         wakeref = intel_display_power_get_if_enabled(dev_priv,
1953                                                      encoder->power_domain);
1954         if (!wakeref)
1955                 return;
1956
1957         tmp = I915_READ(DDI_BUF_CTL(port));
1958         if (!(tmp & DDI_BUF_CTL_ENABLE))
1959                 goto out;
1960
1961         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1962                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1963
1964                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1965                 default:
1966                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1967                         /* fallthrough */
1968                 case TRANS_DDI_EDP_INPUT_A_ON:
1969                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1970                         *pipe_mask = BIT(PIPE_A);
1971                         break;
1972                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1973                         *pipe_mask = BIT(PIPE_B);
1974                         break;
1975                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1976                         *pipe_mask = BIT(PIPE_C);
1977                         break;
1978                 }
1979
1980                 goto out;
1981         }
1982
1983         mst_pipe_mask = 0;
1984         for_each_pipe(dev_priv, p) {
1985                 enum transcoder cpu_transcoder = (enum transcoder)p;
1986
1987                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1988
1989                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
1990                         continue;
1991
1992                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1993                     TRANS_DDI_MODE_SELECT_DP_MST)
1994                         mst_pipe_mask |= BIT(p);
1995
1996                 *pipe_mask |= BIT(p);
1997         }
1998
1999         if (!*pipe_mask)
2000                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2001                               port_name(port));
2002
2003         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2004                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2005                               port_name(port), *pipe_mask);
2006                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2007         }
2008
2009         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2010                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2011                               port_name(port), *pipe_mask, mst_pipe_mask);
2012         else
2013                 *is_dp_mst = mst_pipe_mask;
2014
2015 out:
2016         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2017                 tmp = I915_READ(BXT_PHY_CTL(port));
2018                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2019                             BXT_PHY_LANE_POWERDOWN_ACK |
2020                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2021                         DRM_ERROR("Port %c enabled but PHY powered down? "
2022                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2023         }
2024
2025         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2026 }
2027
2028 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2029                             enum pipe *pipe)
2030 {
2031         u8 pipe_mask;
2032         bool is_mst;
2033
2034         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2035
2036         if (is_mst || !pipe_mask)
2037                 return false;
2038
2039         *pipe = ffs(pipe_mask) - 1;
2040
2041         return true;
2042 }
2043
2044 static inline enum intel_display_power_domain
2045 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2046 {
2047         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2048          * DC states enabled at the same time, while for driver initiated AUX
2049          * transfers we need the same AUX IOs to be powered but with DC states
2050          * disabled. Accordingly use the AUX power domain here which leaves DC
2051          * states enabled.
2052          * However, for non-A AUX ports the corresponding non-EDP transcoders
2053          * would have already enabled power well 2 and DC_OFF. This means we can
2054          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2055          * specific AUX_IO reference without powering up any extra wells.
2056          * Note that PSR is enabled only on Port A even though this function
2057          * returns the correct domain for other ports too.
2058          */
2059         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2060                                               intel_aux_power_domain(dig_port);
2061 }
2062
2063 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2064                                         struct intel_crtc_state *crtc_state)
2065 {
2066         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2067         struct intel_digital_port *dig_port;
2068
2069         /*
2070          * TODO: Add support for MST encoders. Atm, the following should never
2071          * happen since fake-MST encoders don't set their get_power_domains()
2072          * hook.
2073          */
2074         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2075                 return;
2076
2077         dig_port = enc_to_dig_port(&encoder->base);
2078         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2079
2080         /*
2081          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2082          * ports.
2083          */
2084         if (intel_crtc_has_dp_encoder(crtc_state) ||
2085             intel_port_is_tc(dev_priv, encoder->port))
2086                 intel_display_power_get(dev_priv,
2087                                         intel_ddi_main_link_aux_domain(dig_port));
2088
2089         /*
2090          * VDSC power is needed when DSC is enabled
2091          */
2092         if (crtc_state->dsc_params.compression_enable)
2093                 intel_display_power_get(dev_priv,
2094                                         intel_dsc_power_domain(crtc_state));
2095 }
2096
2097 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2098 {
2099         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2100         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2101         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2102         enum port port = encoder->port;
2103         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2104
2105         if (cpu_transcoder != TRANSCODER_EDP)
2106                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2107                            TRANS_CLK_SEL_PORT(port));
2108 }
2109
2110 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2111 {
2112         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2113         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2114
2115         if (cpu_transcoder != TRANSCODER_EDP)
2116                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2117                            TRANS_CLK_SEL_DISABLED);
2118 }
2119
2120 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2121                                 enum port port, u8 iboost)
2122 {
2123         u32 tmp;
2124
2125         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2126         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2127         if (iboost)
2128                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2129         else
2130                 tmp |= BALANCE_LEG_DISABLE(port);
2131         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2132 }
2133
2134 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2135                                int level, enum intel_output_type type)
2136 {
2137         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2138         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2139         enum port port = encoder->port;
2140         u8 iboost;
2141
2142         if (type == INTEL_OUTPUT_HDMI)
2143                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2144         else
2145                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2146
2147         if (iboost == 0) {
2148                 const struct ddi_buf_trans *ddi_translations;
2149                 int n_entries;
2150
2151                 if (type == INTEL_OUTPUT_HDMI)
2152                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2153                 else if (type == INTEL_OUTPUT_EDP)
2154                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2155                 else
2156                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2157
2158                 if (WARN_ON_ONCE(!ddi_translations))
2159                         return;
2160                 if (WARN_ON_ONCE(level >= n_entries))
2161                         level = n_entries - 1;
2162
2163                 iboost = ddi_translations[level].i_boost;
2164         }
2165
2166         /* Make sure that the requested I_boost is valid */
2167         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2168                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2169                 return;
2170         }
2171
2172         _skl_ddi_set_iboost(dev_priv, port, iboost);
2173
2174         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2175                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2176 }
2177
2178 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2179                                     int level, enum intel_output_type type)
2180 {
2181         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2182         const struct bxt_ddi_buf_trans *ddi_translations;
2183         enum port port = encoder->port;
2184         int n_entries;
2185
2186         if (type == INTEL_OUTPUT_HDMI)
2187                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2188         else if (type == INTEL_OUTPUT_EDP)
2189                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2190         else
2191                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2192
2193         if (WARN_ON_ONCE(!ddi_translations))
2194                 return;
2195         if (WARN_ON_ONCE(level >= n_entries))
2196                 level = n_entries - 1;
2197
2198         bxt_ddi_phy_set_signal_level(dev_priv, port,
2199                                      ddi_translations[level].margin,
2200                                      ddi_translations[level].scale,
2201                                      ddi_translations[level].enable,
2202                                      ddi_translations[level].deemphasis);
2203 }
2204
2205 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2206 {
2207         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2208         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2209         enum port port = encoder->port;
2210         int n_entries;
2211
2212         if (INTEL_GEN(dev_priv) >= 11) {
2213                 if (intel_port_is_combophy(dev_priv, port))
2214                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2215                                                 intel_dp->link_rate, &n_entries);
2216                 else
2217                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2218         } else if (IS_CANNONLAKE(dev_priv)) {
2219                 if (encoder->type == INTEL_OUTPUT_EDP)
2220                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2221                 else
2222                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2223         } else if (IS_GEN9_LP(dev_priv)) {
2224                 if (encoder->type == INTEL_OUTPUT_EDP)
2225                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2226                 else
2227                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2228         } else {
2229                 if (encoder->type == INTEL_OUTPUT_EDP)
2230                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2231                 else
2232                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2233         }
2234
2235         if (WARN_ON(n_entries < 1))
2236                 n_entries = 1;
2237         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2238                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2239
2240         return index_to_dp_signal_levels[n_entries - 1] &
2241                 DP_TRAIN_VOLTAGE_SWING_MASK;
2242 }
2243
2244 /*
2245  * We assume that the full set of pre-emphasis values can be
2246  * used on all DDI platforms. Should that change we need to
2247  * rethink this code.
2248  */
2249 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2250 {
2251         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2252         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2253                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2254         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2255                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2256         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2257                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2258         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2259         default:
2260                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2261         }
2262 }
2263
2264 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2265                                    int level, enum intel_output_type type)
2266 {
2267         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2268         const struct cnl_ddi_buf_trans *ddi_translations;
2269         enum port port = encoder->port;
2270         int n_entries, ln;
2271         u32 val;
2272
2273         if (type == INTEL_OUTPUT_HDMI)
2274                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2275         else if (type == INTEL_OUTPUT_EDP)
2276                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2277         else
2278                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2279
2280         if (WARN_ON_ONCE(!ddi_translations))
2281                 return;
2282         if (WARN_ON_ONCE(level >= n_entries))
2283                 level = n_entries - 1;
2284
2285         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2286         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2287         val &= ~SCALING_MODE_SEL_MASK;
2288         val |= SCALING_MODE_SEL(2);
2289         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2290
2291         /* Program PORT_TX_DW2 */
2292         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2293         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2294                  RCOMP_SCALAR_MASK);
2295         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2296         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2297         /* Rcomp scalar is fixed as 0x98 for every table entry */
2298         val |= RCOMP_SCALAR(0x98);
2299         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2300
2301         /* Program PORT_TX_DW4 */
2302         /* We cannot write to GRP. It would overrite individual loadgen */
2303         for (ln = 0; ln < 4; ln++) {
2304                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2305                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2306                          CURSOR_COEFF_MASK);
2307                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2308                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2309                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2310                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2311         }
2312
2313         /* Program PORT_TX_DW5 */
2314         /* All DW5 values are fixed for every table entry */
2315         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2316         val &= ~RTERM_SELECT_MASK;
2317         val |= RTERM_SELECT(6);
2318         val |= TAP3_DISABLE;
2319         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2320
2321         /* Program PORT_TX_DW7 */
2322         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2323         val &= ~N_SCALAR_MASK;
2324         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2325         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2326 }
2327
2328 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2329                                     int level, enum intel_output_type type)
2330 {
2331         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2332         enum port port = encoder->port;
2333         int width, rate, ln;
2334         u32 val;
2335
2336         if (type == INTEL_OUTPUT_HDMI) {
2337                 width = 4;
2338                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2339         } else {
2340                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2341
2342                 width = intel_dp->lane_count;
2343                 rate = intel_dp->link_rate;
2344         }
2345
2346         /*
2347          * 1. If port type is eDP or DP,
2348          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2349          * else clear to 0b.
2350          */
2351         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2352         if (type != INTEL_OUTPUT_HDMI)
2353                 val |= COMMON_KEEPER_EN;
2354         else
2355                 val &= ~COMMON_KEEPER_EN;
2356         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2357
2358         /* 2. Program loadgen select */
2359         /*
2360          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2361          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2362          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2363          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2364          */
2365         for (ln = 0; ln <= 3; ln++) {
2366                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2367                 val &= ~LOADGEN_SELECT;
2368
2369                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2370                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2371                         val |= LOADGEN_SELECT;
2372                 }
2373                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2374         }
2375
2376         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2377         val = I915_READ(CNL_PORT_CL1CM_DW5);
2378         val |= SUS_CLOCK_CONFIG;
2379         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2380
2381         /* 4. Clear training enable to change swing values */
2382         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2383         val &= ~TX_TRAINING_EN;
2384         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2385
2386         /* 5. Program swing and de-emphasis */
2387         cnl_ddi_vswing_program(encoder, level, type);
2388
2389         /* 6. Set training enable to trigger update */
2390         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2391         val |= TX_TRAINING_EN;
2392         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2393 }
2394
2395 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2396                                         u32 level, enum port port, int type,
2397                                         int rate)
2398 {
2399         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2400         u32 n_entries, val;
2401         int ln;
2402
2403         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2404                                                    rate, &n_entries);
2405         if (!ddi_translations)
2406                 return;
2407
2408         if (level >= n_entries) {
2409                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2410                 level = n_entries - 1;
2411         }
2412
2413         /* Set PORT_TX_DW5 */
2414         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2415         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2416                   TAP2_DISABLE | TAP3_DISABLE);
2417         val |= SCALING_MODE_SEL(0x2);
2418         val |= RTERM_SELECT(0x6);
2419         val |= TAP3_DISABLE;
2420         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2421
2422         /* Program PORT_TX_DW2 */
2423         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2424         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2425                  RCOMP_SCALAR_MASK);
2426         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2427         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2428         /* Program Rcomp scalar for every table entry */
2429         val |= RCOMP_SCALAR(0x98);
2430         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2431
2432         /* Program PORT_TX_DW4 */
2433         /* We cannot write to GRP. It would overwrite individual loadgen. */
2434         for (ln = 0; ln <= 3; ln++) {
2435                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2436                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2437                          CURSOR_COEFF_MASK);
2438                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2439                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2440                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2441                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2442         }
2443
2444         /* Program PORT_TX_DW7 */
2445         val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2446         val &= ~N_SCALAR_MASK;
2447         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2448         I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2449 }
2450
2451 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2452                                               u32 level,
2453                                               enum intel_output_type type)
2454 {
2455         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2456         enum port port = encoder->port;
2457         int width = 0;
2458         int rate = 0;
2459         u32 val;
2460         int ln = 0;
2461
2462         if (type == INTEL_OUTPUT_HDMI) {
2463                 width = 4;
2464                 /* Rate is always < than 6GHz for HDMI */
2465         } else {
2466                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2467
2468                 width = intel_dp->lane_count;
2469                 rate = intel_dp->link_rate;
2470         }
2471
2472         /*
2473          * 1. If port type is eDP or DP,
2474          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2475          * else clear to 0b.
2476          */
2477         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2478         if (type == INTEL_OUTPUT_HDMI)
2479                 val &= ~COMMON_KEEPER_EN;
2480         else
2481                 val |= COMMON_KEEPER_EN;
2482         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2483
2484         /* 2. Program loadgen select */
2485         /*
2486          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2487          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2488          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2489          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2490          */
2491         for (ln = 0; ln <= 3; ln++) {
2492                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
2493                 val &= ~LOADGEN_SELECT;
2494
2495                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2496                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2497                         val |= LOADGEN_SELECT;
2498                 }
2499                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
2500         }
2501
2502         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2503         val = I915_READ(ICL_PORT_CL_DW5(port));
2504         val |= SUS_CLOCK_CONFIG;
2505         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2506
2507         /* 4. Clear training enable to change swing values */
2508         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2509         val &= ~TX_TRAINING_EN;
2510         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2511
2512         /* 5. Program swing and de-emphasis */
2513         icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2514
2515         /* 6. Set training enable to trigger update */
2516         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2517         val |= TX_TRAINING_EN;
2518         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2519 }
2520
2521 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2522                                            int link_clock,
2523                                            u32 level)
2524 {
2525         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2526         enum port port = encoder->port;
2527         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2528         u32 n_entries, val;
2529         int ln;
2530
2531         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2532         ddi_translations = icl_mg_phy_ddi_translations;
2533         /* The table does not have values for level 3 and level 9. */
2534         if (level >= n_entries || level == 3 || level == 9) {
2535                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2536                               level, n_entries - 2);
2537                 level = n_entries - 2;
2538         }
2539
2540         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2541         for (ln = 0; ln < 2; ln++) {
2542                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2543                 val &= ~CRI_USE_FS32;
2544                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2545
2546                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2547                 val &= ~CRI_USE_FS32;
2548                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2549         }
2550
2551         /* Program MG_TX_SWINGCTRL with values from vswing table */
2552         for (ln = 0; ln < 2; ln++) {
2553                 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2554                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2555                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2556                         ddi_translations[level].cri_txdeemph_override_17_12);
2557                 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2558
2559                 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2560                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2561                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2562                         ddi_translations[level].cri_txdeemph_override_17_12);
2563                 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2564         }
2565
2566         /* Program MG_TX_DRVCTRL with values from vswing table */
2567         for (ln = 0; ln < 2; ln++) {
2568                 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2569                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2570                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2571                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2572                         ddi_translations[level].cri_txdeemph_override_5_0) |
2573                         CRI_TXDEEMPH_OVERRIDE_11_6(
2574                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2575                         CRI_TXDEEMPH_OVERRIDE_EN;
2576                 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2577
2578                 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2579                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2580                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2581                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2582                         ddi_translations[level].cri_txdeemph_override_5_0) |
2583                         CRI_TXDEEMPH_OVERRIDE_11_6(
2584                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2585                         CRI_TXDEEMPH_OVERRIDE_EN;
2586                 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2587
2588                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2589         }
2590
2591         /*
2592          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2593          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2594          * values from table for which TX1 and TX2 enabled.
2595          */
2596         for (ln = 0; ln < 2; ln++) {
2597                 val = I915_READ(MG_CLKHUB(ln, port));
2598                 if (link_clock < 300000)
2599                         val |= CFG_LOW_RATE_LKREN_EN;
2600                 else
2601                         val &= ~CFG_LOW_RATE_LKREN_EN;
2602                 I915_WRITE(MG_CLKHUB(ln, port), val);
2603         }
2604
2605         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2606         for (ln = 0; ln < 2; ln++) {
2607                 val = I915_READ(MG_TX1_DCC(ln, port));
2608                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2609                 if (link_clock <= 500000) {
2610                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2611                 } else {
2612                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2613                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2614                 }
2615                 I915_WRITE(MG_TX1_DCC(ln, port), val);
2616
2617                 val = I915_READ(MG_TX2_DCC(ln, port));
2618                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2619                 if (link_clock <= 500000) {
2620                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2621                 } else {
2622                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2623                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2624                 }
2625                 I915_WRITE(MG_TX2_DCC(ln, port), val);
2626         }
2627
2628         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2629         for (ln = 0; ln < 2; ln++) {
2630                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2631                 val |= CRI_CALCINIT;
2632                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2633
2634                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2635                 val |= CRI_CALCINIT;
2636                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2637         }
2638 }
2639
2640 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2641                                     int link_clock,
2642                                     u32 level,
2643                                     enum intel_output_type type)
2644 {
2645         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2646         enum port port = encoder->port;
2647
2648         if (intel_port_is_combophy(dev_priv, port))
2649                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2650         else
2651                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2652 }
2653
2654 static u32 translate_signal_level(int signal_levels)
2655 {
2656         int i;
2657
2658         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2659                 if (index_to_dp_signal_levels[i] == signal_levels)
2660                         return i;
2661         }
2662
2663         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2664              signal_levels);
2665
2666         return 0;
2667 }
2668
2669 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2670 {
2671         u8 train_set = intel_dp->train_set[0];
2672         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2673                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2674
2675         return translate_signal_level(signal_levels);
2676 }
2677
2678 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2679 {
2680         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2681         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2682         struct intel_encoder *encoder = &dport->base;
2683         int level = intel_ddi_dp_level(intel_dp);
2684
2685         if (INTEL_GEN(dev_priv) >= 11)
2686                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2687                                         level, encoder->type);
2688         else if (IS_CANNONLAKE(dev_priv))
2689                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2690         else
2691                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2692
2693         return 0;
2694 }
2695
2696 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2697 {
2698         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2699         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2700         struct intel_encoder *encoder = &dport->base;
2701         int level = intel_ddi_dp_level(intel_dp);
2702
2703         if (IS_GEN9_BC(dev_priv))
2704                 skl_ddi_set_iboost(encoder, level, encoder->type);
2705
2706         return DDI_BUF_TRANS_SELECT(level);
2707 }
2708
2709 static inline
2710 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2711                               enum port port)
2712 {
2713         if (intel_port_is_combophy(dev_priv, port)) {
2714                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2715         } else if (intel_port_is_tc(dev_priv, port)) {
2716                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2717
2718                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2719         }
2720
2721         return 0;
2722 }
2723
2724 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2725                                   const struct intel_crtc_state *crtc_state)
2726 {
2727         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2728         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2729         enum port port = encoder->port;
2730         u32 val;
2731
2732         mutex_lock(&dev_priv->dpll_lock);
2733
2734         val = I915_READ(DPCLKA_CFGCR0_ICL);
2735         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2736
2737         if (intel_port_is_combophy(dev_priv, port)) {
2738                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2739                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2740                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2741                 POSTING_READ(DPCLKA_CFGCR0_ICL);
2742         }
2743
2744         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2745         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2746
2747         mutex_unlock(&dev_priv->dpll_lock);
2748 }
2749
2750 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2751 {
2752         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2753         enum port port = encoder->port;
2754         u32 val;
2755
2756         mutex_lock(&dev_priv->dpll_lock);
2757
2758         val = I915_READ(DPCLKA_CFGCR0_ICL);
2759         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2760         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2761
2762         mutex_unlock(&dev_priv->dpll_lock);
2763 }
2764
2765 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2766 {
2767         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2768         u32 val;
2769         enum port port;
2770         u32 port_mask;
2771         bool ddi_clk_needed;
2772
2773         /*
2774          * In case of DP MST, we sanitize the primary encoder only, not the
2775          * virtual ones.
2776          */
2777         if (encoder->type == INTEL_OUTPUT_DP_MST)
2778                 return;
2779
2780         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2781                 u8 pipe_mask;
2782                 bool is_mst;
2783
2784                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2785                 /*
2786                  * In the unlikely case that BIOS enables DP in MST mode, just
2787                  * warn since our MST HW readout is incomplete.
2788                  */
2789                 if (WARN_ON(is_mst))
2790                         return;
2791         }
2792
2793         port_mask = BIT(encoder->port);
2794         ddi_clk_needed = encoder->base.crtc;
2795
2796         if (encoder->type == INTEL_OUTPUT_DSI) {
2797                 struct intel_encoder *other_encoder;
2798
2799                 port_mask = intel_dsi_encoder_ports(encoder);
2800                 /*
2801                  * Sanity check that we haven't incorrectly registered another
2802                  * encoder using any of the ports of this DSI encoder.
2803                  */
2804                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2805                         if (other_encoder == encoder)
2806                                 continue;
2807
2808                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2809                                 return;
2810                 }
2811                 /*
2812                  * For DSI we keep the ddi clocks gated
2813                  * except during enable/disable sequence.
2814                  */
2815                 ddi_clk_needed = false;
2816         }
2817
2818         val = I915_READ(DPCLKA_CFGCR0_ICL);
2819         for_each_port_masked(port, port_mask) {
2820                 bool ddi_clk_ungated = !(val &
2821                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2822                                                                    port));
2823
2824                 if (ddi_clk_needed == ddi_clk_ungated)
2825                         continue;
2826
2827                 /*
2828                  * Punt on the case now where clock is gated, but it would
2829                  * be needed by the port. Something else is really broken then.
2830                  */
2831                 if (WARN_ON(ddi_clk_needed))
2832                         continue;
2833
2834                 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2835                          port_name(port));
2836                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2837                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2838         }
2839 }
2840
2841 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2842                                  const struct intel_crtc_state *crtc_state)
2843 {
2844         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2845         enum port port = encoder->port;
2846         u32 val;
2847         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2848
2849         if (WARN_ON(!pll))
2850                 return;
2851
2852         mutex_lock(&dev_priv->dpll_lock);
2853
2854         if (INTEL_GEN(dev_priv) >= 11) {
2855                 if (!intel_port_is_combophy(dev_priv, port))
2856                         I915_WRITE(DDI_CLK_SEL(port),
2857                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2858         } else if (IS_CANNONLAKE(dev_priv)) {
2859                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2860                 val = I915_READ(DPCLKA_CFGCR0);
2861                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2862                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2863                 I915_WRITE(DPCLKA_CFGCR0, val);
2864
2865                 /*
2866                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2867                  * This step and the step before must be done with separate
2868                  * register writes.
2869                  */
2870                 val = I915_READ(DPCLKA_CFGCR0);
2871                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2872                 I915_WRITE(DPCLKA_CFGCR0, val);
2873         } else if (IS_GEN9_BC(dev_priv)) {
2874                 /* DDI -> PLL mapping  */
2875                 val = I915_READ(DPLL_CTRL2);
2876
2877                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2878                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2879                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2880                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2881
2882                 I915_WRITE(DPLL_CTRL2, val);
2883
2884         } else if (INTEL_GEN(dev_priv) < 9) {
2885                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2886         }
2887
2888         mutex_unlock(&dev_priv->dpll_lock);
2889 }
2890
2891 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2892 {
2893         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2894         enum port port = encoder->port;
2895
2896         if (INTEL_GEN(dev_priv) >= 11) {
2897                 if (!intel_port_is_combophy(dev_priv, port))
2898                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2899         } else if (IS_CANNONLAKE(dev_priv)) {
2900                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2901                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2902         } else if (IS_GEN9_BC(dev_priv)) {
2903                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2904                            DPLL_CTRL2_DDI_CLK_OFF(port));
2905         } else if (INTEL_GEN(dev_priv) < 9) {
2906                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2907         }
2908 }
2909
2910 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2911 {
2912         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2913         enum port port = dig_port->base.port;
2914         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2915         u32 val;
2916         int ln;
2917
2918         if (tc_port == PORT_TC_NONE)
2919                 return;
2920
2921         for (ln = 0; ln < 2; ln++) {
2922                 val = I915_READ(MG_DP_MODE(ln, port));
2923                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2924                        MG_DP_MODE_CFG_TRPWR_GATING |
2925                        MG_DP_MODE_CFG_CLNPWR_GATING |
2926                        MG_DP_MODE_CFG_DIGPWR_GATING |
2927                        MG_DP_MODE_CFG_GAONPWR_GATING;
2928                 I915_WRITE(MG_DP_MODE(ln, port), val);
2929         }
2930
2931         val = I915_READ(MG_MISC_SUS0(tc_port));
2932         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2933                MG_MISC_SUS0_CFG_TR2PWR_GATING |
2934                MG_MISC_SUS0_CFG_CL2PWR_GATING |
2935                MG_MISC_SUS0_CFG_GAONPWR_GATING |
2936                MG_MISC_SUS0_CFG_TRPWR_GATING |
2937                MG_MISC_SUS0_CFG_CL1PWR_GATING |
2938                MG_MISC_SUS0_CFG_DGPWR_GATING;
2939         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2940 }
2941
2942 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2943 {
2944         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2945         enum port port = dig_port->base.port;
2946         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2947         u32 val;
2948         int ln;
2949
2950         if (tc_port == PORT_TC_NONE)
2951                 return;
2952
2953         for (ln = 0; ln < 2; ln++) {
2954                 val = I915_READ(MG_DP_MODE(ln, port));
2955                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2956                          MG_DP_MODE_CFG_TRPWR_GATING |
2957                          MG_DP_MODE_CFG_CLNPWR_GATING |
2958                          MG_DP_MODE_CFG_DIGPWR_GATING |
2959                          MG_DP_MODE_CFG_GAONPWR_GATING);
2960                 I915_WRITE(MG_DP_MODE(ln, port), val);
2961         }
2962
2963         val = I915_READ(MG_MISC_SUS0(tc_port));
2964         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2965                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
2966                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
2967                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
2968                  MG_MISC_SUS0_CFG_TRPWR_GATING |
2969                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
2970                  MG_MISC_SUS0_CFG_DGPWR_GATING);
2971         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2972 }
2973
2974 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2975 {
2976         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2977         enum port port = intel_dig_port->base.port;
2978         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2979         u32 ln0, ln1, lane_info;
2980
2981         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2982                 return;
2983
2984         ln0 = I915_READ(MG_DP_MODE(0, port));
2985         ln1 = I915_READ(MG_DP_MODE(1, port));
2986
2987         switch (intel_dig_port->tc_type) {
2988         case TC_PORT_TYPEC:
2989                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2990                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2991
2992                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
2993                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
2994                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
2995
2996                 switch (lane_info) {
2997                 case 0x1:
2998                 case 0x4:
2999                         break;
3000                 case 0x2:
3001                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3002                         break;
3003                 case 0x3:
3004                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3005                                MG_DP_MODE_CFG_DP_X2_MODE;
3006                         break;
3007                 case 0x8:
3008                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3009                         break;
3010                 case 0xC:
3011                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3012                                MG_DP_MODE_CFG_DP_X2_MODE;
3013                         break;
3014                 case 0xF:
3015                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3016                                MG_DP_MODE_CFG_DP_X2_MODE;
3017                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3018                                MG_DP_MODE_CFG_DP_X2_MODE;
3019                         break;
3020                 default:
3021                         MISSING_CASE(lane_info);
3022                 }
3023                 break;
3024
3025         case TC_PORT_LEGACY:
3026                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3027                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3028                 break;
3029
3030         default:
3031                 MISSING_CASE(intel_dig_port->tc_type);
3032                 return;
3033         }
3034
3035         I915_WRITE(MG_DP_MODE(0, port), ln0);
3036         I915_WRITE(MG_DP_MODE(1, port), ln1);
3037 }
3038
3039 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3040                                         const struct intel_crtc_state *crtc_state)
3041 {
3042         if (!crtc_state->fec_enable)
3043                 return;
3044
3045         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3046                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3047 }
3048
3049 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3050                                  const struct intel_crtc_state *crtc_state)
3051 {
3052         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3053         enum port port = encoder->port;
3054         u32 val;
3055
3056         if (!crtc_state->fec_enable)
3057                 return;
3058
3059         val = I915_READ(DP_TP_CTL(port));
3060         val |= DP_TP_CTL_FEC_ENABLE;
3061         I915_WRITE(DP_TP_CTL(port), val);
3062
3063         if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
3064                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3065                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3066                                     1))
3067                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3068 }
3069
3070 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3071                                         const struct intel_crtc_state *crtc_state)
3072 {
3073         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3074         enum port port = encoder->port;
3075         u32 val;
3076
3077         if (!crtc_state->fec_enable)
3078                 return;
3079
3080         val = I915_READ(DP_TP_CTL(port));
3081         val &= ~DP_TP_CTL_FEC_ENABLE;
3082         I915_WRITE(DP_TP_CTL(port), val);
3083         POSTING_READ(DP_TP_CTL(port));
3084 }
3085
3086 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3087                                     const struct intel_crtc_state *crtc_state,
3088                                     const struct drm_connector_state *conn_state)
3089 {
3090         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3091         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3092         enum port port = encoder->port;
3093         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3094         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3095         int level = intel_ddi_dp_level(intel_dp);
3096
3097         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3098
3099         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3100                                  crtc_state->lane_count, is_mst);
3101
3102         intel_edp_panel_on(intel_dp);
3103
3104         intel_ddi_clk_select(encoder, crtc_state);
3105
3106         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3107
3108         icl_program_mg_dp_mode(dig_port);
3109         icl_disable_phy_clock_gating(dig_port);
3110
3111         if (INTEL_GEN(dev_priv) >= 11)
3112                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3113                                         level, encoder->type);
3114         else if (IS_CANNONLAKE(dev_priv))
3115                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3116         else if (IS_GEN9_LP(dev_priv))
3117                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3118         else
3119                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3120
3121         if (intel_port_is_combophy(dev_priv, port)) {
3122                 bool lane_reversal =
3123                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3124
3125                 intel_combo_phy_power_up_lanes(dev_priv, port, false,
3126                                                crtc_state->lane_count,
3127                                                lane_reversal);
3128         }
3129
3130         intel_ddi_init_dp_buf_reg(encoder);
3131         if (!is_mst)
3132                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3133         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3134                                               true);
3135         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3136         intel_dp_start_link_train(intel_dp);
3137         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3138                 intel_dp_stop_link_train(intel_dp);
3139
3140         intel_ddi_enable_fec(encoder, crtc_state);
3141
3142         icl_enable_phy_clock_gating(dig_port);
3143
3144         if (!is_mst)
3145                 intel_ddi_enable_pipe_clock(crtc_state);
3146
3147         intel_dsc_enable(encoder, crtc_state);
3148 }
3149
3150 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3151                                       const struct intel_crtc_state *crtc_state,
3152                                       const struct drm_connector_state *conn_state)
3153 {
3154         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3155         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3156         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3157         enum port port = encoder->port;
3158         int level = intel_ddi_hdmi_level(dev_priv, port);
3159         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3160
3161         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3162         intel_ddi_clk_select(encoder, crtc_state);
3163
3164         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3165
3166         icl_program_mg_dp_mode(dig_port);
3167         icl_disable_phy_clock_gating(dig_port);
3168
3169         if (INTEL_GEN(dev_priv) >= 11)
3170                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3171                                         level, INTEL_OUTPUT_HDMI);
3172         else if (IS_CANNONLAKE(dev_priv))
3173                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3174         else if (IS_GEN9_LP(dev_priv))
3175                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3176         else
3177                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3178
3179         icl_enable_phy_clock_gating(dig_port);
3180
3181         if (IS_GEN9_BC(dev_priv))
3182                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3183
3184         intel_ddi_enable_pipe_clock(crtc_state);
3185
3186         intel_dig_port->set_infoframes(encoder,
3187                                        crtc_state->has_infoframe,
3188                                        crtc_state, conn_state);
3189 }
3190
3191 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3192                                  const struct intel_crtc_state *crtc_state,
3193                                  const struct drm_connector_state *conn_state)
3194 {
3195         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3196         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3197         enum pipe pipe = crtc->pipe;
3198
3199         /*
3200          * When called from DP MST code:
3201          * - conn_state will be NULL
3202          * - encoder will be the main encoder (ie. mst->primary)
3203          * - the main connector associated with this port
3204          *   won't be active or linked to a crtc
3205          * - crtc_state will be the state of the first stream to
3206          *   be activated on this port, and it may not be the same
3207          *   stream that will be deactivated last, but each stream
3208          *   should have a state that is identical when it comes to
3209          *   the DP link parameteres
3210          */
3211
3212         WARN_ON(crtc_state->has_pch_encoder);
3213
3214         if (INTEL_GEN(dev_priv) >= 11)
3215                 icl_map_plls_to_ports(encoder, crtc_state);
3216
3217         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3218
3219         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3220                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3221         } else {
3222                 struct intel_lspcon *lspcon =
3223                                 enc_to_intel_lspcon(&encoder->base);
3224
3225                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3226                 if (lspcon->active) {
3227                         struct intel_digital_port *dig_port =
3228                                         enc_to_dig_port(&encoder->base);
3229
3230                         dig_port->set_infoframes(encoder,
3231                                                  crtc_state->has_infoframe,
3232                                                  crtc_state, conn_state);
3233                 }
3234         }
3235 }
3236
3237 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3238                                   const struct intel_crtc_state *crtc_state)
3239 {
3240         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3241         enum port port = encoder->port;
3242         bool wait = false;
3243         u32 val;
3244
3245         val = I915_READ(DDI_BUF_CTL(port));
3246         if (val & DDI_BUF_CTL_ENABLE) {
3247                 val &= ~DDI_BUF_CTL_ENABLE;
3248                 I915_WRITE(DDI_BUF_CTL(port), val);
3249                 wait = true;
3250         }
3251
3252         val = I915_READ(DP_TP_CTL(port));
3253         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3254         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3255         I915_WRITE(DP_TP_CTL(port), val);
3256
3257         /* Disable FEC in DP Sink */
3258         intel_ddi_disable_fec_state(encoder, crtc_state);
3259
3260         if (wait)
3261                 intel_wait_ddi_buf_idle(dev_priv, port);
3262 }
3263
3264 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3265                                       const struct intel_crtc_state *old_crtc_state,
3266                                       const struct drm_connector_state *old_conn_state)
3267 {
3268         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3269         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3270         struct intel_dp *intel_dp = &dig_port->dp;
3271         bool is_mst = intel_crtc_has_type(old_crtc_state,
3272                                           INTEL_OUTPUT_DP_MST);
3273
3274         if (!is_mst) {
3275                 intel_ddi_disable_pipe_clock(old_crtc_state);
3276                 /*
3277                  * Power down sink before disabling the port, otherwise we end
3278                  * up getting interrupts from the sink on detecting link loss.
3279                  */
3280                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3281         }
3282
3283         intel_disable_ddi_buf(encoder, old_crtc_state);
3284
3285         intel_edp_panel_vdd_on(intel_dp);
3286         intel_edp_panel_off(intel_dp);
3287
3288         intel_display_power_put_unchecked(dev_priv,
3289                                           dig_port->ddi_io_power_domain);
3290
3291         intel_ddi_clk_disable(encoder);
3292 }
3293
3294 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3295                                         const struct intel_crtc_state *old_crtc_state,
3296                                         const struct drm_connector_state *old_conn_state)
3297 {
3298         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3299         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3300         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3301
3302         dig_port->set_infoframes(encoder, false,
3303                                  old_crtc_state, old_conn_state);
3304
3305         intel_ddi_disable_pipe_clock(old_crtc_state);
3306
3307         intel_disable_ddi_buf(encoder, old_crtc_state);
3308
3309         intel_display_power_put_unchecked(dev_priv,
3310                                           dig_port->ddi_io_power_domain);
3311
3312         intel_ddi_clk_disable(encoder);
3313
3314         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3315 }
3316
3317 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3318                                    const struct intel_crtc_state *old_crtc_state,
3319                                    const struct drm_connector_state *old_conn_state)
3320 {
3321         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3322
3323         /*
3324          * When called from DP MST code:
3325          * - old_conn_state will be NULL
3326          * - encoder will be the main encoder (ie. mst->primary)
3327          * - the main connector associated with this port
3328          *   won't be active or linked to a crtc
3329          * - old_crtc_state will be the state of the last stream to
3330          *   be deactivated on this port, and it may not be the same
3331          *   stream that was activated last, but each stream
3332          *   should have a state that is identical when it comes to
3333          *   the DP link parameteres
3334          */
3335
3336         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3337                 intel_ddi_post_disable_hdmi(encoder,
3338                                             old_crtc_state, old_conn_state);
3339         else
3340                 intel_ddi_post_disable_dp(encoder,
3341                                           old_crtc_state, old_conn_state);
3342
3343         if (INTEL_GEN(dev_priv) >= 11)
3344                 icl_unmap_plls_to_ports(encoder);
3345 }
3346
3347 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3348                                 const struct intel_crtc_state *old_crtc_state,
3349                                 const struct drm_connector_state *old_conn_state)
3350 {
3351         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3352         u32 val;
3353
3354         /*
3355          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3356          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3357          * step 13 is the correct place for it. Step 18 is where it was
3358          * originally before the BUN.
3359          */
3360         val = I915_READ(FDI_RX_CTL(PIPE_A));
3361         val &= ~FDI_RX_ENABLE;
3362         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3363
3364         intel_disable_ddi_buf(encoder, old_crtc_state);
3365         intel_ddi_clk_disable(encoder);
3366
3367         val = I915_READ(FDI_RX_MISC(PIPE_A));
3368         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3369         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3370         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3371
3372         val = I915_READ(FDI_RX_CTL(PIPE_A));
3373         val &= ~FDI_PCDCLK;
3374         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3375
3376         val = I915_READ(FDI_RX_CTL(PIPE_A));
3377         val &= ~FDI_RX_PLL_ENABLE;
3378         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3379 }
3380
3381 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3382                                 const struct intel_crtc_state *crtc_state,
3383                                 const struct drm_connector_state *conn_state)
3384 {
3385         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3386         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3387         enum port port = encoder->port;
3388
3389         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3390                 intel_dp_stop_link_train(intel_dp);
3391
3392         intel_edp_backlight_on(crtc_state, conn_state);
3393         intel_psr_enable(intel_dp, crtc_state);
3394         intel_edp_drrs_enable(intel_dp, crtc_state);
3395
3396         if (crtc_state->has_audio)
3397                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3398 }
3399
3400 static i915_reg_t
3401 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3402                                enum port port)
3403 {
3404         static const i915_reg_t regs[] = {
3405                 [PORT_A] = CHICKEN_TRANS_EDP,
3406                 [PORT_B] = CHICKEN_TRANS_A,
3407                 [PORT_C] = CHICKEN_TRANS_B,
3408                 [PORT_D] = CHICKEN_TRANS_C,
3409                 [PORT_E] = CHICKEN_TRANS_A,
3410         };
3411
3412         WARN_ON(INTEL_GEN(dev_priv) < 9);
3413
3414         if (WARN_ON(port < PORT_A || port > PORT_E))
3415                 port = PORT_A;
3416
3417         return regs[port];
3418 }
3419
3420 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3421                                   const struct intel_crtc_state *crtc_state,
3422                                   const struct drm_connector_state *conn_state)
3423 {
3424         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3425         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3426         struct drm_connector *connector = conn_state->connector;
3427         enum port port = encoder->port;
3428
3429         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3430                                                crtc_state->hdmi_high_tmds_clock_ratio,
3431                                                crtc_state->hdmi_scrambling))
3432                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3433                           connector->base.id, connector->name);
3434
3435         /* Display WA #1143: skl,kbl,cfl */
3436         if (IS_GEN9_BC(dev_priv)) {
3437                 /*
3438                  * For some reason these chicken bits have been
3439                  * stuffed into a transcoder register, event though
3440                  * the bits affect a specific DDI port rather than
3441                  * a specific transcoder.
3442                  */
3443                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3444                 u32 val;
3445
3446                 val = I915_READ(reg);
3447
3448                 if (port == PORT_E)
3449                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3450                                 DDIE_TRAINING_OVERRIDE_VALUE;
3451                 else
3452                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3453                                 DDI_TRAINING_OVERRIDE_VALUE;
3454
3455                 I915_WRITE(reg, val);
3456                 POSTING_READ(reg);
3457
3458                 udelay(1);
3459
3460                 if (port == PORT_E)
3461                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3462                                  DDIE_TRAINING_OVERRIDE_VALUE);
3463                 else
3464                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3465                                  DDI_TRAINING_OVERRIDE_VALUE);
3466
3467                 I915_WRITE(reg, val);
3468         }
3469
3470         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3471          * are ignored so nothing special needs to be done besides
3472          * enabling the port.
3473          */
3474         I915_WRITE(DDI_BUF_CTL(port),
3475                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3476
3477         if (crtc_state->has_audio)
3478                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3479 }
3480
3481 static void intel_enable_ddi(struct intel_encoder *encoder,
3482                              const struct intel_crtc_state *crtc_state,
3483                              const struct drm_connector_state *conn_state)
3484 {
3485         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3486                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3487         else
3488                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3489
3490         /* Enable hdcp if it's desired */
3491         if (conn_state->content_protection ==
3492             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3493                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3494 }
3495
3496 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3497                                  const struct intel_crtc_state *old_crtc_state,
3498                                  const struct drm_connector_state *old_conn_state)
3499 {
3500         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3501
3502         intel_dp->link_trained = false;
3503
3504         if (old_crtc_state->has_audio)
3505                 intel_audio_codec_disable(encoder,
3506                                           old_crtc_state, old_conn_state);
3507
3508         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3509         intel_psr_disable(intel_dp, old_crtc_state);
3510         intel_edp_backlight_off(old_conn_state);
3511         /* Disable the decompression in DP Sink */
3512         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3513                                               false);
3514 }
3515
3516 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3517                                    const struct intel_crtc_state *old_crtc_state,
3518                                    const struct drm_connector_state *old_conn_state)
3519 {
3520         struct drm_connector *connector = old_conn_state->connector;
3521
3522         if (old_crtc_state->has_audio)
3523                 intel_audio_codec_disable(encoder,
3524                                           old_crtc_state, old_conn_state);
3525
3526         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3527                                                false, false))
3528                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3529                               connector->base.id, connector->name);
3530 }
3531
3532 static void intel_disable_ddi(struct intel_encoder *encoder,
3533                               const struct intel_crtc_state *old_crtc_state,
3534                               const struct drm_connector_state *old_conn_state)
3535 {
3536         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3537
3538         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3539                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3540         else
3541                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3542 }
3543
3544 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3545                                      const struct intel_crtc_state *crtc_state,
3546                                      const struct drm_connector_state *conn_state)
3547 {
3548         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3549
3550         intel_ddi_set_pipe_settings(crtc_state);
3551
3552         intel_psr_update(intel_dp, crtc_state);
3553         intel_edp_drrs_enable(intel_dp, crtc_state);
3554
3555         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3556 }
3557
3558 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3559                                   const struct intel_crtc_state *crtc_state,
3560                                   const struct drm_connector_state *conn_state)
3561 {
3562         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3563                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3564
3565         if (conn_state->content_protection ==
3566             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3567                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3568         else if (conn_state->content_protection ==
3569                  DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3570                 intel_hdcp_disable(to_intel_connector(conn_state->connector));
3571 }
3572
3573 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3574                                          const struct intel_crtc_state *pipe_config,
3575                                          enum port port)
3576 {
3577         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3578         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3579         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3580         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3581         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3582
3583         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3584         switch (pipe_config->lane_count) {
3585         case 1:
3586                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3587                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3588                 break;
3589         case 2:
3590                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3591                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3592                 break;
3593         case 4:
3594                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3595                 break;
3596         default:
3597                 MISSING_CASE(pipe_config->lane_count);
3598         }
3599         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3600 }
3601
3602 static void
3603 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3604                          const struct intel_crtc_state *crtc_state,
3605                          const struct drm_connector_state *conn_state)
3606 {
3607         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3608         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3609         enum port port = encoder->port;
3610
3611         if (intel_crtc_has_dp_encoder(crtc_state) ||
3612             intel_port_is_tc(dev_priv, encoder->port))
3613                 intel_display_power_get(dev_priv,
3614                                         intel_ddi_main_link_aux_domain(dig_port));
3615
3616         if (IS_GEN9_LP(dev_priv))
3617                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3618                                                 crtc_state->lane_lat_optim_mask);
3619
3620         /*
3621          * Program the lane count for static/dynamic connections on Type-C ports.
3622          * Skip this step for TBT.
3623          */
3624         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3625             dig_port->tc_type == TC_PORT_TBT)
3626                 return;
3627
3628         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3629 }
3630
3631 static void
3632 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3633                            const struct intel_crtc_state *crtc_state,
3634                            const struct drm_connector_state *conn_state)
3635 {
3636         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3637         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3638
3639         if (intel_crtc_has_dp_encoder(crtc_state) ||
3640             intel_port_is_tc(dev_priv, encoder->port))
3641                 intel_display_power_put_unchecked(dev_priv,
3642                                                   intel_ddi_main_link_aux_domain(dig_port));
3643 }
3644
3645 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3646 {
3647         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3648         struct drm_i915_private *dev_priv =
3649                 to_i915(intel_dig_port->base.base.dev);
3650         enum port port = intel_dig_port->base.port;
3651         u32 val;
3652         bool wait = false;
3653
3654         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3655                 val = I915_READ(DDI_BUF_CTL(port));
3656                 if (val & DDI_BUF_CTL_ENABLE) {
3657                         val &= ~DDI_BUF_CTL_ENABLE;
3658                         I915_WRITE(DDI_BUF_CTL(port), val);
3659                         wait = true;
3660                 }
3661
3662                 val = I915_READ(DP_TP_CTL(port));
3663                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3664                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3665                 I915_WRITE(DP_TP_CTL(port), val);
3666                 POSTING_READ(DP_TP_CTL(port));
3667
3668                 if (wait)
3669                         intel_wait_ddi_buf_idle(dev_priv, port);
3670         }
3671
3672         val = DP_TP_CTL_ENABLE |
3673               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3674         if (intel_dp->link_mst)
3675                 val |= DP_TP_CTL_MODE_MST;
3676         else {
3677                 val |= DP_TP_CTL_MODE_SST;
3678                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3679                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3680         }
3681         I915_WRITE(DP_TP_CTL(port), val);
3682         POSTING_READ(DP_TP_CTL(port));
3683
3684         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3685         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3686         POSTING_READ(DDI_BUF_CTL(port));
3687
3688         udelay(600);
3689 }
3690
3691 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3692                                        enum transcoder cpu_transcoder)
3693 {
3694         if (cpu_transcoder == TRANSCODER_EDP)
3695                 return false;
3696
3697         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3698                 return false;
3699
3700         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3701                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3702 }
3703
3704 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3705                                          struct intel_crtc_state *crtc_state)
3706 {
3707         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3708                 crtc_state->min_voltage_level = 1;
3709         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3710                 crtc_state->min_voltage_level = 2;
3711 }
3712
3713 void intel_ddi_get_config(struct intel_encoder *encoder,
3714                           struct intel_crtc_state *pipe_config)
3715 {
3716         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3717         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3718         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3719         struct intel_digital_port *intel_dig_port;
3720         u32 temp, flags = 0;
3721
3722         /* XXX: DSI transcoder paranoia */
3723         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3724                 return;
3725
3726         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3727         if (temp & TRANS_DDI_PHSYNC)
3728                 flags |= DRM_MODE_FLAG_PHSYNC;
3729         else
3730                 flags |= DRM_MODE_FLAG_NHSYNC;
3731         if (temp & TRANS_DDI_PVSYNC)
3732                 flags |= DRM_MODE_FLAG_PVSYNC;
3733         else
3734                 flags |= DRM_MODE_FLAG_NVSYNC;
3735
3736         pipe_config->base.adjusted_mode.flags |= flags;
3737
3738         switch (temp & TRANS_DDI_BPC_MASK) {
3739         case TRANS_DDI_BPC_6:
3740                 pipe_config->pipe_bpp = 18;
3741                 break;
3742         case TRANS_DDI_BPC_8:
3743                 pipe_config->pipe_bpp = 24;
3744                 break;
3745         case TRANS_DDI_BPC_10:
3746                 pipe_config->pipe_bpp = 30;
3747                 break;
3748         case TRANS_DDI_BPC_12:
3749                 pipe_config->pipe_bpp = 36;
3750                 break;
3751         default:
3752                 break;
3753         }
3754
3755         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3756         case TRANS_DDI_MODE_SELECT_HDMI:
3757                 pipe_config->has_hdmi_sink = true;
3758                 intel_dig_port = enc_to_dig_port(&encoder->base);
3759
3760                 pipe_config->infoframes.enable |=
3761                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3762
3763                 if (pipe_config->infoframes.enable)
3764                         pipe_config->has_infoframe = true;
3765
3766                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3767                         pipe_config->hdmi_scrambling = true;
3768                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3769                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3770                 /* fall through */
3771         case TRANS_DDI_MODE_SELECT_DVI:
3772                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3773                 pipe_config->lane_count = 4;
3774                 break;
3775         case TRANS_DDI_MODE_SELECT_FDI:
3776                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3777                 break;
3778         case TRANS_DDI_MODE_SELECT_DP_SST:
3779                 if (encoder->type == INTEL_OUTPUT_EDP)
3780                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3781                 else
3782                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3783                 pipe_config->lane_count =
3784                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3785                 intel_dp_get_m_n(intel_crtc, pipe_config);
3786                 break;
3787         case TRANS_DDI_MODE_SELECT_DP_MST:
3788                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3789                 pipe_config->lane_count =
3790                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3791                 intel_dp_get_m_n(intel_crtc, pipe_config);
3792                 break;
3793         default:
3794                 break;
3795         }
3796
3797         pipe_config->has_audio =
3798                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3799
3800         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3801             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3802                 /*
3803                  * This is a big fat ugly hack.
3804                  *
3805                  * Some machines in UEFI boot mode provide us a VBT that has 18
3806                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3807                  * unknown we fail to light up. Yet the same BIOS boots up with
3808                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3809                  * max, not what it tells us to use.
3810                  *
3811                  * Note: This will still be broken if the eDP panel is not lit
3812                  * up by the BIOS, and thus we can't get the mode at module
3813                  * load.
3814                  */
3815                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3816                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3817                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3818         }
3819
3820         intel_ddi_clock_get(encoder, pipe_config);
3821
3822         if (IS_GEN9_LP(dev_priv))
3823                 pipe_config->lane_lat_optim_mask =
3824                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3825
3826         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3827
3828         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3829
3830         intel_read_infoframe(encoder, pipe_config,
3831                              HDMI_INFOFRAME_TYPE_AVI,
3832                              &pipe_config->infoframes.avi);
3833         intel_read_infoframe(encoder, pipe_config,
3834                              HDMI_INFOFRAME_TYPE_SPD,
3835                              &pipe_config->infoframes.spd);
3836         intel_read_infoframe(encoder, pipe_config,
3837                              HDMI_INFOFRAME_TYPE_VENDOR,
3838                              &pipe_config->infoframes.hdmi);
3839 }
3840
3841 static enum intel_output_type
3842 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3843                               struct intel_crtc_state *crtc_state,
3844                               struct drm_connector_state *conn_state)
3845 {
3846         switch (conn_state->connector->connector_type) {
3847         case DRM_MODE_CONNECTOR_HDMIA:
3848                 return INTEL_OUTPUT_HDMI;
3849         case DRM_MODE_CONNECTOR_eDP:
3850                 return INTEL_OUTPUT_EDP;
3851         case DRM_MODE_CONNECTOR_DisplayPort:
3852                 return INTEL_OUTPUT_DP;
3853         default:
3854                 MISSING_CASE(conn_state->connector->connector_type);
3855                 return INTEL_OUTPUT_UNUSED;
3856         }
3857 }
3858
3859 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3860                                     struct intel_crtc_state *pipe_config,
3861                                     struct drm_connector_state *conn_state)
3862 {
3863         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3864         enum port port = encoder->port;
3865         int ret;
3866
3867         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
3868                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3869
3870         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3871                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3872         else
3873                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3874         if (ret)
3875                 return ret;
3876
3877         if (IS_GEN9_LP(dev_priv))
3878                 pipe_config->lane_lat_optim_mask =
3879                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3880
3881         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3882
3883         return 0;
3884
3885 }
3886
3887 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3888 {
3889         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3890         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3891
3892         intel_dp_encoder_suspend(encoder);
3893
3894         /*
3895          * TODO: disconnect also from USB DP alternate mode once we have a
3896          * way to handle the modeset restore in that mode during resume
3897          * even if the sink has disappeared while being suspended.
3898          */
3899         if (dig_port->tc_legacy_port)
3900                 icl_tc_phy_disconnect(i915, dig_port);
3901 }
3902
3903 static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3904 {
3905         struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3906         struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3907
3908         if (intel_port_is_tc(i915, dig_port->base.port))
3909                 intel_digital_port_connected(&dig_port->base);
3910
3911         intel_dp_encoder_reset(drm_encoder);
3912 }
3913
3914 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3915 {
3916         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3917         struct drm_i915_private *i915 = to_i915(encoder->dev);
3918
3919         intel_dp_encoder_flush_work(encoder);
3920
3921         if (intel_port_is_tc(i915, dig_port->base.port))
3922                 icl_tc_phy_disconnect(i915, dig_port);
3923
3924         drm_encoder_cleanup(encoder);
3925         kfree(dig_port);
3926 }
3927
3928 static const struct drm_encoder_funcs intel_ddi_funcs = {
3929         .reset = intel_ddi_encoder_reset,
3930         .destroy = intel_ddi_encoder_destroy,
3931 };
3932
3933 static struct intel_connector *
3934 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3935 {
3936         struct intel_connector *connector;
3937         enum port port = intel_dig_port->base.port;
3938
3939         connector = intel_connector_alloc();
3940         if (!connector)
3941                 return NULL;
3942
3943         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3944         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3945                 kfree(connector);
3946                 return NULL;
3947         }
3948
3949         return connector;
3950 }
3951
3952 static int modeset_pipe(struct drm_crtc *crtc,
3953                         struct drm_modeset_acquire_ctx *ctx)
3954 {
3955         struct drm_atomic_state *state;
3956         struct drm_crtc_state *crtc_state;
3957         int ret;
3958
3959         state = drm_atomic_state_alloc(crtc->dev);
3960         if (!state)
3961                 return -ENOMEM;
3962
3963         state->acquire_ctx = ctx;
3964
3965         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3966         if (IS_ERR(crtc_state)) {
3967                 ret = PTR_ERR(crtc_state);
3968                 goto out;
3969         }
3970
3971         crtc_state->connectors_changed = true;
3972
3973         ret = drm_atomic_commit(state);
3974 out:
3975         drm_atomic_state_put(state);
3976
3977         return ret;
3978 }
3979
3980 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3981                                  struct drm_modeset_acquire_ctx *ctx)
3982 {
3983         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3984         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3985         struct intel_connector *connector = hdmi->attached_connector;
3986         struct i2c_adapter *adapter =
3987                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3988         struct drm_connector_state *conn_state;
3989         struct intel_crtc_state *crtc_state;
3990         struct intel_crtc *crtc;
3991         u8 config;
3992         int ret;
3993
3994         if (!connector || connector->base.status != connector_status_connected)
3995                 return 0;
3996
3997         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3998                                ctx);
3999         if (ret)
4000                 return ret;
4001
4002         conn_state = connector->base.state;
4003
4004         crtc = to_intel_crtc(conn_state->crtc);
4005         if (!crtc)
4006                 return 0;
4007
4008         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4009         if (ret)
4010                 return ret;
4011
4012         crtc_state = to_intel_crtc_state(crtc->base.state);
4013
4014         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4015
4016         if (!crtc_state->base.active)
4017                 return 0;
4018
4019         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4020             !crtc_state->hdmi_scrambling)
4021                 return 0;
4022
4023         if (conn_state->commit &&
4024             !try_wait_for_completion(&conn_state->commit->hw_done))
4025                 return 0;
4026
4027         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4028         if (ret < 0) {
4029                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4030                 return 0;
4031         }
4032
4033         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4034             crtc_state->hdmi_high_tmds_clock_ratio &&
4035             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4036             crtc_state->hdmi_scrambling)
4037                 return 0;
4038
4039         /*
4040          * HDMI 2.0 says that one should not send scrambled data
4041          * prior to configuring the sink scrambling, and that
4042          * TMDS clock/data transmission should be suspended when
4043          * changing the TMDS clock rate in the sink. So let's
4044          * just do a full modeset here, even though some sinks
4045          * would be perfectly happy if were to just reconfigure
4046          * the SCDC settings on the fly.
4047          */
4048         return modeset_pipe(&crtc->base, ctx);
4049 }
4050
4051 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4052                               struct intel_connector *connector)
4053 {
4054         struct drm_modeset_acquire_ctx ctx;
4055         bool changed;
4056         int ret;
4057
4058         changed = intel_encoder_hotplug(encoder, connector);
4059
4060         drm_modeset_acquire_init(&ctx, 0);
4061
4062         for (;;) {
4063                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4064                         ret = intel_hdmi_reset_link(encoder, &ctx);
4065                 else
4066                         ret = intel_dp_retrain_link(encoder, &ctx);
4067
4068                 if (ret == -EDEADLK) {
4069                         drm_modeset_backoff(&ctx);
4070                         continue;
4071                 }
4072
4073                 break;
4074         }
4075
4076         drm_modeset_drop_locks(&ctx);
4077         drm_modeset_acquire_fini(&ctx);
4078         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4079
4080         return changed;
4081 }
4082
4083 static struct intel_connector *
4084 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4085 {
4086         struct intel_connector *connector;
4087         enum port port = intel_dig_port->base.port;
4088
4089         connector = intel_connector_alloc();
4090         if (!connector)
4091                 return NULL;
4092
4093         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4094         intel_hdmi_init_connector(intel_dig_port, connector);
4095
4096         return connector;
4097 }
4098
4099 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4100 {
4101         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4102
4103         if (dport->base.port != PORT_A)
4104                 return false;
4105
4106         if (dport->saved_port_bits & DDI_A_4_LANES)
4107                 return false;
4108
4109         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4110          *                     supported configuration
4111          */
4112         if (IS_GEN9_LP(dev_priv))
4113                 return true;
4114
4115         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4116          *             one who does also have a full A/E split called
4117          *             DDI_F what makes DDI_E useless. However for this
4118          *             case let's trust VBT info.
4119          */
4120         if (IS_CANNONLAKE(dev_priv) &&
4121             !intel_bios_is_port_present(dev_priv, PORT_E))
4122                 return true;
4123
4124         return false;
4125 }
4126
4127 static int
4128 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4129 {
4130         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4131         enum port port = intel_dport->base.port;
4132         int max_lanes = 4;
4133
4134         if (INTEL_GEN(dev_priv) >= 11)
4135                 return max_lanes;
4136
4137         if (port == PORT_A || port == PORT_E) {
4138                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4139                         max_lanes = port == PORT_A ? 4 : 0;
4140                 else
4141                         /* Both A and E share 2 lanes */
4142                         max_lanes = 2;
4143         }
4144
4145         /*
4146          * Some BIOS might fail to set this bit on port A if eDP
4147          * wasn't lit up at boot.  Force this bit set when needed
4148          * so we use the proper lane count for our calculations.
4149          */
4150         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4151                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4152                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4153                 max_lanes = 4;
4154         }
4155
4156         return max_lanes;
4157 }
4158
4159 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4160 {
4161         struct ddi_vbt_port_info *port_info =
4162                 &dev_priv->vbt.ddi_port_info[port];
4163         struct intel_digital_port *intel_dig_port;
4164         struct intel_encoder *intel_encoder;
4165         struct drm_encoder *encoder;
4166         bool init_hdmi, init_dp, init_lspcon = false;
4167         enum pipe pipe;
4168
4169         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4170         init_dp = port_info->supports_dp;
4171
4172         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4173                 /*
4174                  * Lspcon device needs to be driven with DP connector
4175                  * with special detection sequence. So make sure DP
4176                  * is initialized before lspcon.
4177                  */
4178                 init_dp = true;
4179                 init_lspcon = true;
4180                 init_hdmi = false;
4181                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4182         }
4183
4184         if (!init_dp && !init_hdmi) {
4185                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4186                               port_name(port));
4187                 return;
4188         }
4189
4190         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4191         if (!intel_dig_port)
4192                 return;
4193
4194         intel_encoder = &intel_dig_port->base;
4195         encoder = &intel_encoder->base;
4196
4197         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4198                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4199
4200         intel_encoder->hotplug = intel_ddi_hotplug;
4201         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4202         intel_encoder->compute_config = intel_ddi_compute_config;
4203         intel_encoder->enable = intel_enable_ddi;
4204         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4205         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4206         intel_encoder->pre_enable = intel_ddi_pre_enable;
4207         intel_encoder->disable = intel_disable_ddi;
4208         intel_encoder->post_disable = intel_ddi_post_disable;
4209         intel_encoder->update_pipe = intel_ddi_update_pipe;
4210         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4211         intel_encoder->get_config = intel_ddi_get_config;
4212         intel_encoder->suspend = intel_ddi_encoder_suspend;
4213         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4214         intel_encoder->type = INTEL_OUTPUT_DDI;
4215         intel_encoder->power_domain = intel_port_to_power_domain(port);
4216         intel_encoder->port = port;
4217         intel_encoder->cloneable = 0;
4218         for_each_pipe(dev_priv, pipe)
4219                 intel_encoder->crtc_mask |= BIT(pipe);
4220
4221         if (INTEL_GEN(dev_priv) >= 11)
4222                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4223                         DDI_BUF_PORT_REVERSAL;
4224         else
4225                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4226                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4227         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4228         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4229         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4230
4231         intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4232                                          !port_info->supports_typec_usb &&
4233                                          !port_info->supports_tbt;
4234
4235         switch (port) {
4236         case PORT_A:
4237                 intel_dig_port->ddi_io_power_domain =
4238                         POWER_DOMAIN_PORT_DDI_A_IO;
4239                 break;
4240         case PORT_B:
4241                 intel_dig_port->ddi_io_power_domain =
4242                         POWER_DOMAIN_PORT_DDI_B_IO;
4243                 break;
4244         case PORT_C:
4245                 intel_dig_port->ddi_io_power_domain =
4246                         POWER_DOMAIN_PORT_DDI_C_IO;
4247                 break;
4248         case PORT_D:
4249                 intel_dig_port->ddi_io_power_domain =
4250                         POWER_DOMAIN_PORT_DDI_D_IO;
4251                 break;
4252         case PORT_E:
4253                 intel_dig_port->ddi_io_power_domain =
4254                         POWER_DOMAIN_PORT_DDI_E_IO;
4255                 break;
4256         case PORT_F:
4257                 intel_dig_port->ddi_io_power_domain =
4258                         POWER_DOMAIN_PORT_DDI_F_IO;
4259                 break;
4260         default:
4261                 MISSING_CASE(port);
4262         }
4263
4264         if (init_dp) {
4265                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4266                         goto err;
4267
4268                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4269         }
4270
4271         /* In theory we don't need the encoder->type check, but leave it just in
4272          * case we have some really bad VBTs... */
4273         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4274                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4275                         goto err;
4276         }
4277
4278         if (init_lspcon) {
4279                 if (lspcon_init(intel_dig_port))
4280                         /* TODO: handle hdmi info frame part */
4281                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4282                                 port_name(port));
4283                 else
4284                         /*
4285                          * LSPCON init faied, but DP init was success, so
4286                          * lets try to drive as DP++ port.
4287                          */
4288                         DRM_ERROR("LSPCON init failed on port %c\n",
4289                                 port_name(port));
4290         }
4291
4292         intel_infoframe_init(intel_dig_port);
4293
4294         if (intel_port_is_tc(dev_priv, port))
4295                 intel_digital_port_connected(intel_encoder);
4296
4297         return;
4298
4299 err:
4300         drm_encoder_cleanup(encoder);
4301         kfree(intel_dig_port);
4302 }