drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 static const u8 index_to_dp_signal_levels[] = {
  38         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  39         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  40         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  41         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  42         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  43         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  44         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  45         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  46         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  47         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  48 };
  49
  50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  51  * them for both DP and FDI transports, allowing those ports to
  52  * automatically adapt to HDMI connections as well
  53  */
  54 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  55         { 0x00FFFFFF, 0x0006000E, 0x0 },
  56         { 0x00D75FFF, 0x0005000A, 0x0 },
  57         { 0x00C30FFF, 0x00040006, 0x0 },
  58         { 0x80AAAFFF, 0x000B0000, 0x0 },
  59         { 0x00FFFFFF, 0x0005000A, 0x0 },
  60         { 0x00D75FFF, 0x000C0004, 0x0 },
  61         { 0x80C30FFF, 0x000B0000, 0x0 },
  62         { 0x00FFFFFF, 0x00040006, 0x0 },
  63         { 0x80D75FFF, 0x000B0000, 0x0 },
  64 };
  65
  66 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  67         { 0x00FFFFFF, 0x0007000E, 0x0 },
  68         { 0x00D75FFF, 0x000F000A, 0x0 },
  69         { 0x00C30FFF, 0x00060006, 0x0 },
  70         { 0x00AAAFFF, 0x001E0000, 0x0 },
  71         { 0x00FFFFFF, 0x000F000A, 0x0 },
  72         { 0x00D75FFF, 0x00160004, 0x0 },
  73         { 0x00C30FFF, 0x001E0000, 0x0 },
  74         { 0x00FFFFFF, 0x00060006, 0x0 },
  75         { 0x00D75FFF, 0x001E0000, 0x0 },
  76 };
  77
  78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  79                                         /* Idx  NT mV d T mV d  db      */
  80         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  81         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  82         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  83         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  84         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  85         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  86         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  87         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  88         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  89         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  90         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  91         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  92 };
  93
  94 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  95         { 0x00FFFFFF, 0x00000012, 0x0 },
  96         { 0x00EBAFFF, 0x00020011, 0x0 },
  97         { 0x00C71FFF, 0x0006000F, 0x0 },
  98         { 0x00AAAFFF, 0x000E000A, 0x0 },
  99         { 0x00FFFFFF, 0x00020011, 0x0 },
 100         { 0x00DB6FFF, 0x0005000F, 0x0 },
 101         { 0x00BEEFFF, 0x000A000C, 0x0 },
 102         { 0x00FFFFFF, 0x0005000F, 0x0 },
 103         { 0x00DB6FFF, 0x000A000C, 0x0 },
 104 };
 105
 106 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 107         { 0x00FFFFFF, 0x0007000E, 0x0 },
 108         { 0x00D75FFF, 0x000E000A, 0x0 },
 109         { 0x00BEFFFF, 0x00140006, 0x0 },
 110         { 0x80B2CFFF, 0x001B0002, 0x0 },
 111         { 0x00FFFFFF, 0x000E000A, 0x0 },
 112         { 0x00DB6FFF, 0x00160005, 0x0 },
 113         { 0x80C71FFF, 0x001A0002, 0x0 },
 114         { 0x00F7DFFF, 0x00180004, 0x0 },
 115         { 0x80D75FFF, 0x001B0002, 0x0 },
 116 };
 117
 118 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 119         { 0x00FFFFFF, 0x0001000E, 0x0 },
 120         { 0x00D75FFF, 0x0004000A, 0x0 },
 121         { 0x00C30FFF, 0x00070006, 0x0 },
 122         { 0x00AAAFFF, 0x000C0000, 0x0 },
 123         { 0x00FFFFFF, 0x0004000A, 0x0 },
 124         { 0x00D75FFF, 0x00090004, 0x0 },
 125         { 0x00C30FFF, 0x000C0000, 0x0 },
 126         { 0x00FFFFFF, 0x00070006, 0x0 },
 127         { 0x00D75FFF, 0x000C0000, 0x0 },
 128 };
 129
 130 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 131                                         /* Idx  NT mV d T mV df db      */
 132         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 133         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 134         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 135         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 136         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 137         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 138         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 139         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 140         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 141         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 142 };
 143
 144 /* Skylake H and S */
 145 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 146         { 0x00002016, 0x000000A0, 0x0 },
 147         { 0x00005012, 0x0000009B, 0x0 },
 148         { 0x00007011, 0x00000088, 0x0 },
 149         { 0x80009010, 0x000000C0, 0x1 },
 150         { 0x00002016, 0x0000009B, 0x0 },
 151         { 0x00005012, 0x00000088, 0x0 },
 152         { 0x80007011, 0x000000C0, 0x1 },
 153         { 0x00002016, 0x000000DF, 0x0 },
 154         { 0x80005012, 0x000000C0, 0x1 },
 155 };
 156
 157 /* Skylake U */
 158 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 159         { 0x0000201B, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x80007011, 0x000000CD, 0x1 },
 162         { 0x80009010, 0x000000C0, 0x1 },
 163         { 0x0000201B, 0x0000009D, 0x0 },
 164         { 0x80005012, 0x000000C0, 0x1 },
 165         { 0x80007011, 0x000000C0, 0x1 },
 166         { 0x00002016, 0x00000088, 0x0 },
 167         { 0x80005012, 0x000000C0, 0x1 },
 168 };
 169
 170 /* Skylake Y */
 171 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 172         { 0x00000018, 0x000000A2, 0x0 },
 173         { 0x00005012, 0x00000088, 0x0 },
 174         { 0x80007011, 0x000000CD, 0x3 },
 175         { 0x80009010, 0x000000C0, 0x3 },
 176         { 0x00000018, 0x0000009D, 0x0 },
 177         { 0x80005012, 0x000000C0, 0x3 },
 178         { 0x80007011, 0x000000C0, 0x3 },
 179         { 0x00000018, 0x00000088, 0x0 },
 180         { 0x80005012, 0x000000C0, 0x3 },
 181 };
 182
 183 /* Kabylake H and S */
 184 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 185         { 0x00002016, 0x000000A0, 0x0 },
 186         { 0x00005012, 0x0000009B, 0x0 },
 187         { 0x00007011, 0x00000088, 0x0 },
 188         { 0x80009010, 0x000000C0, 0x1 },
 189         { 0x00002016, 0x0000009B, 0x0 },
 190         { 0x00005012, 0x00000088, 0x0 },
 191         { 0x80007011, 0x000000C0, 0x1 },
 192         { 0x00002016, 0x00000097, 0x0 },
 193         { 0x80005012, 0x000000C0, 0x1 },
 194 };
 195
 196 /* Kabylake U */
 197 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 198         { 0x0000201B, 0x000000A1, 0x0 },
 199         { 0x00005012, 0x00000088, 0x0 },
 200         { 0x80007011, 0x000000CD, 0x3 },
 201         { 0x80009010, 0x000000C0, 0x3 },
 202         { 0x0000201B, 0x0000009D, 0x0 },
 203         { 0x80005012, 0x000000C0, 0x3 },
 204         { 0x80007011, 0x000000C0, 0x3 },
 205         { 0x00002016, 0x0000004F, 0x0 },
 206         { 0x80005012, 0x000000C0, 0x3 },
 207 };
 208
 209 /* Kabylake Y */
 210 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 211         { 0x00001017, 0x000000A1, 0x0 },
 212         { 0x00005012, 0x00000088, 0x0 },
 213         { 0x80007011, 0x000000CD, 0x3 },
 214         { 0x8000800F, 0x000000C0, 0x3 },
 215         { 0x00001017, 0x0000009D, 0x0 },
 216         { 0x80005012, 0x000000C0, 0x3 },
 217         { 0x80007011, 0x000000C0, 0x3 },
 218         { 0x00001017, 0x0000004C, 0x0 },
 219         { 0x80005012, 0x000000C0, 0x3 },
 220 };
 221
 222 /*
 223  * Skylake/Kabylake H and S
 224  * eDP 1.4 low vswing translation parameters
 225  */
 226 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 227         { 0x00000018, 0x000000A8, 0x0 },
 228         { 0x00004013, 0x000000A9, 0x0 },
 229         { 0x00007011, 0x000000A2, 0x0 },
 230         { 0x00009010, 0x0000009C, 0x0 },
 231         { 0x00000018, 0x000000A9, 0x0 },
 232         { 0x00006013, 0x000000A2, 0x0 },
 233         { 0x00007011, 0x000000A6, 0x0 },
 234         { 0x00000018, 0x000000AB, 0x0 },
 235         { 0x00007013, 0x0000009F, 0x0 },
 236         { 0x00000018, 0x000000DF, 0x0 },
 237 };
 238
 239 /*
 240  * Skylake/Kabylake U
 241  * eDP 1.4 low vswing translation parameters
 242  */
 243 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 244         { 0x00000018, 0x000000A8, 0x0 },
 245         { 0x00004013, 0x000000A9, 0x0 },
 246         { 0x00007011, 0x000000A2, 0x0 },
 247         { 0x00009010, 0x0000009C, 0x0 },
 248         { 0x00000018, 0x000000A9, 0x0 },
 249         { 0x00006013, 0x000000A2, 0x0 },
 250         { 0x00007011, 0x000000A6, 0x0 },
 251         { 0x00002016, 0x000000AB, 0x0 },
 252         { 0x00005013, 0x0000009F, 0x0 },
 253         { 0x00000018, 0x000000DF, 0x0 },
 254 };
 255
 256 /*
 257  * Skylake/Kabylake Y
 258  * eDP 1.4 low vswing translation parameters
 259  */
 260 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 261         { 0x00000018, 0x000000A8, 0x0 },
 262         { 0x00004013, 0x000000AB, 0x0 },
 263         { 0x00007011, 0x000000A4, 0x0 },
 264         { 0x00009010, 0x000000DF, 0x0 },
 265         { 0x00000018, 0x000000AA, 0x0 },
 266         { 0x00006013, 0x000000A4, 0x0 },
 267         { 0x00007011, 0x0000009D, 0x0 },
 268         { 0x00000018, 0x000000A0, 0x0 },
 269         { 0x00006012, 0x000000DF, 0x0 },
 270         { 0x00000018, 0x0000008A, 0x0 },
 271 };
 272
 273 /* Skylake/Kabylake U, H and S */
 274 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 275         { 0x00000018, 0x000000AC, 0x0 },
 276         { 0x00005012, 0x0000009D, 0x0 },
 277         { 0x00007011, 0x00000088, 0x0 },
 278         { 0x00000018, 0x000000A1, 0x0 },
 279         { 0x00000018, 0x00000098, 0x0 },
 280         { 0x00004013, 0x00000088, 0x0 },
 281         { 0x80006012, 0x000000CD, 0x1 },
 282         { 0x00000018, 0x000000DF, 0x0 },
 283         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 284         { 0x80003015, 0x000000C0, 0x1 },
 285         { 0x80000018, 0x000000C0, 0x1 },
 286 };
 287
 288 /* Skylake/Kabylake Y */
 289 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 290         { 0x00000018, 0x000000A1, 0x0 },
 291         { 0x00005012, 0x000000DF, 0x0 },
 292         { 0x80007011, 0x000000CB, 0x3 },
 293         { 0x00000018, 0x000000A4, 0x0 },
 294         { 0x00000018, 0x0000009D, 0x0 },
 295         { 0x00004013, 0x00000080, 0x0 },
 296         { 0x80006013, 0x000000C0, 0x3 },
 297         { 0x00000018, 0x0000008A, 0x0 },
 298         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 299         { 0x80003015, 0x000000C0, 0x3 },
 300         { 0x80000018, 0x000000C0, 0x3 },
 301 };
 302
 303 struct bxt_ddi_buf_trans {
 304         u32 margin;     /* swing value */
 305         u32 scale;      /* scale value */
 306         u32 enable;     /* scale enable */
 307         u32 deemphasis;
 308         bool default_index; /* true if the entry represents default value */
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, false },       /* 0:   200             0   */
 328         { 38, 0, 0, 112, false },       /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  false },       /* 2:   200             4   */
 330         { 54, 0, 0, 69,  false },       /* 3:   200             6   */
 331         { 32, 0, 0, 128, false },       /* 4:   250             0   */
 332         { 48, 0, 0, 104, false },       /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  false },       /* 6:   250             4   */
 334         { 43, 0, 0, 128, false },       /* 7:   300             0   */
 335         { 54, 0, 0, 101, false },       /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, false },       /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u32 dw2_swing_sel;
 358         u32 dw7_n_scalar;
 359         u32 dw4_cursor_coeff;
 360         u32 dw4_post_cursor_2;
 361         u32 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
 497 {
 498         switch (encoder->type) {
 499         case INTEL_OUTPUT_DP_MST:
 500                 return enc_to_mst(&encoder->base)->primary->port;
 501         case INTEL_OUTPUT_DP:
 502         case INTEL_OUTPUT_EDP:
 503         case INTEL_OUTPUT_HDMI:
 504         case INTEL_OUTPUT_UNKNOWN:
 505                 return enc_to_dig_port(&encoder->base)->port;
 506         case INTEL_OUTPUT_ANALOG:
 507                 return PORT_E;
 508         default:
 509                 MISSING_CASE(encoder->type);
 510                 return PORT_A;
 511         }
 512 }
 513
 514 static const struct ddi_buf_trans *
 515 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 516 {
 517         if (dev_priv->vbt.edp.low_vswing) {
 518                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 519                 return bdw_ddi_translations_edp;
 520         } else {
 521                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 522                 return bdw_ddi_translations_dp;
 523         }
 524 }
 525
 526 static const struct ddi_buf_trans *
 527 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 528 {
 529         if (IS_SKL_ULX(dev_priv)) {
 530                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 531                 return skl_y_ddi_translations_dp;
 532         } else if (IS_SKL_ULT(dev_priv)) {
 533                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 534                 return skl_u_ddi_translations_dp;
 535         } else {
 536                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 537                 return skl_ddi_translations_dp;
 538         }
 539 }
 540
 541 static const struct ddi_buf_trans *
 542 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 543 {
 544         if (IS_KBL_ULX(dev_priv)) {
 545                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 546                 return kbl_y_ddi_translations_dp;
 547         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 548                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 549                 return kbl_u_ddi_translations_dp;
 550         } else {
 551                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 552                 return kbl_ddi_translations_dp;
 553         }
 554 }
 555
 556 static const struct ddi_buf_trans *
 557 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 558 {
 559         if (dev_priv->vbt.edp.low_vswing) {
 560                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 561                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 562                         return skl_y_ddi_translations_edp;
 563                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 564                            IS_CFL_ULT(dev_priv)) {
 565                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 566                         return skl_u_ddi_translations_edp;
 567                 } else {
 568                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 569                         return skl_ddi_translations_edp;
 570                 }
 571         }
 572
 573         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 574                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 575         else
 576                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 577 }
 578
 579 static const struct ddi_buf_trans *
 580 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 581 {
 582         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 583                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 584                 return skl_y_ddi_translations_hdmi;
 585         } else {
 586                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 587                 return skl_ddi_translations_hdmi;
 588         }
 589 }
 590
 591 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 592 {
 593         int n_hdmi_entries;
 594         int hdmi_level;
 595         int hdmi_default_entry;
 596
 597         hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 598
 599         if (IS_GEN9_LP(dev_priv))
 600                 return hdmi_level;
 601
 602         if (IS_GEN9_BC(dev_priv)) {
 603                 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 604                 hdmi_default_entry = 8;
 605         } else if (IS_BROADWELL(dev_priv)) {
 606                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 607                 hdmi_default_entry = 7;
 608         } else if (IS_HASWELL(dev_priv)) {
 609                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 610                 hdmi_default_entry = 6;
 611         } else {
 612                 WARN(1, "ddi translation table missing\n");
 613                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 614                 hdmi_default_entry = 7;
 615         }
 616
 617         /* Choose a good default if VBT is badly populated */
 618         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 619             hdmi_level >= n_hdmi_entries)
 620                 hdmi_level = hdmi_default_entry;
 621
 622         return hdmi_level;
 623 }
 624
 625 static const struct ddi_buf_trans *
 626 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 627                            int *n_entries)
 628 {
 629         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 630                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 631         } else if (IS_SKYLAKE(dev_priv)) {
 632                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 633         } else if (IS_BROADWELL(dev_priv)) {
 634                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 635                 return  bdw_ddi_translations_dp;
 636         } else if (IS_HASWELL(dev_priv)) {
 637                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 638                 return hsw_ddi_translations_dp;
 639         }
 640
 641         *n_entries = 0;
 642         return NULL;
 643 }
 644
 645 static const struct ddi_buf_trans *
 646 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 647                             int *n_entries)
 648 {
 649         if (IS_GEN9_BC(dev_priv)) {
 650                 return skl_get_buf_trans_edp(dev_priv, n_entries);
 651         } else if (IS_BROADWELL(dev_priv)) {
 652                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 653         } else if (IS_HASWELL(dev_priv)) {
 654                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 655                 return hsw_ddi_translations_dp;
 656         }
 657
 658         *n_entries = 0;
 659         return NULL;
 660 }
 661
 662 static const struct ddi_buf_trans *
 663 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 664                             int *n_entries)
 665 {
 666         if (IS_BROADWELL(dev_priv)) {
 667                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 668                 return hsw_ddi_translations_fdi;
 669         } else if (IS_HASWELL(dev_priv)) {
 670                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 671                 return hsw_ddi_translations_fdi;
 672         }
 673
 674         *n_entries = 0;
 675         return NULL;
 676 }
 677
 678 /*
 679  * Starting with Haswell, DDI port buffers must be programmed with correct
 680  * values in advance. This function programs the correct values for
 681  * DP/eDP/FDI use cases.
 682  */
 683 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
 684 {
 685         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 686         u32 iboost_bit = 0;
 687         int i, n_entries;
 688         enum port port = intel_ddi_get_encoder_port(encoder);
 689         const struct ddi_buf_trans *ddi_translations;
 690
 691         if (IS_GEN9_LP(dev_priv))
 692                 return;
 693
 694         switch (encoder->type) {
 695         case INTEL_OUTPUT_EDP:
 696                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
 697                                                                &n_entries);
 698                 break;
 699         case INTEL_OUTPUT_DP:
 700                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
 701                                                               &n_entries);
 702                 break;
 703         case INTEL_OUTPUT_ANALOG:
 704                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 705                                                                &n_entries);
 706                 break;
 707         default:
 708                 MISSING_CASE(encoder->type);
 709                 return;
 710         }
 711
 712         if (IS_GEN9_BC(dev_priv)) {
 713                 /* If we're boosting the current, set bit 31 of trans1 */
 714                 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 715                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 716
 717                 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
 718                             port != PORT_A && port != PORT_E &&
 719                             n_entries > 9))
 720                         n_entries = 9;
 721         }
 722
 723         for (i = 0; i < n_entries; i++) {
 724                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 725                            ddi_translations[i].trans1 | iboost_bit);
 726                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 727                            ddi_translations[i].trans2);
 728         }
 729 }
 730
 731 /*
 732  * Starting with Haswell, DDI port buffers must be programmed with correct
 733  * values in advance. This function programs the correct values for
 734  * HDMI/DVI use cases.
 735  */
 736 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
 737 {
 738         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 739         u32 iboost_bit = 0;
 740         int n_hdmi_entries, hdmi_level;
 741         enum port port = intel_ddi_get_encoder_port(encoder);
 742         const struct ddi_buf_trans *ddi_translations_hdmi;
 743
 744         if (IS_GEN9_LP(dev_priv))
 745                 return;
 746
 747         hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
 748
 749         if (IS_GEN9_BC(dev_priv)) {
 750                 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 751
 752                 /* If we're boosting the current, set bit 31 of trans1 */
 753                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 754                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 755         } else if (IS_BROADWELL(dev_priv)) {
 756                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 757                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 758         } else if (IS_HASWELL(dev_priv)) {
 759                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 760                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 761         } else {
 762                 WARN(1, "ddi translation table missing\n");
 763                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 764                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 765         }
 766
 767         /* Entry 9 is for HDMI: */
 768         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 769                    ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 770         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 771                    ddi_translations_hdmi[hdmi_level].trans2);
 772 }
 773
 774 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 775                                     enum port port)
 776 {
 777         i915_reg_t reg = DDI_BUF_CTL(port);
 778         int i;
 779
 780         for (i = 0; i < 16; i++) {
 781                 udelay(1);
 782                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 783                         return;
 784         }
 785         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 786 }
 787
 788 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
 789 {
 790         switch (pll->id) {
 791         case DPLL_ID_WRPLL1:
 792                 return PORT_CLK_SEL_WRPLL1;
 793         case DPLL_ID_WRPLL2:
 794                 return PORT_CLK_SEL_WRPLL2;
 795         case DPLL_ID_SPLL:
 796                 return PORT_CLK_SEL_SPLL;
 797         case DPLL_ID_LCPLL_810:
 798                 return PORT_CLK_SEL_LCPLL_810;
 799         case DPLL_ID_LCPLL_1350:
 800                 return PORT_CLK_SEL_LCPLL_1350;
 801         case DPLL_ID_LCPLL_2700:
 802                 return PORT_CLK_SEL_LCPLL_2700;
 803         default:
 804                 MISSING_CASE(pll->id);
 805                 return PORT_CLK_SEL_NONE;
 806         }
 807 }
 808
 809 /* Starting with Haswell, different DDI ports can work in FDI mode for
 810  * connection to the PCH-located connectors. For this, it is necessary to train
 811  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 812  *
 813  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 814  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 815  * DDI A (which is used for eDP)
 816  */
 817
 818 void hsw_fdi_link_train(struct intel_crtc *crtc,
 819                         const struct intel_crtc_state *crtc_state)
 820 {
 821         struct drm_device *dev = crtc->base.dev;
 822         struct drm_i915_private *dev_priv = to_i915(dev);
 823         struct intel_encoder *encoder;
 824         u32 temp, i, rx_ctl_val, ddi_pll_sel;
 825
 826         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 827                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
 828                 intel_prepare_dp_ddi_buffers(encoder);
 829         }
 830
 831         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 832          * mode set "sequence for CRT port" document:
 833          * - TP1 to TP2 time with the default value
 834          * - FDI delay to 90h
 835          *
 836          * WaFDIAutoLinkSetTimingOverrride:hsw
 837          */
 838         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 839                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 840                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 841
 842         /* Enable the PCH Receiver FDI PLL */
 843         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 844                      FDI_RX_PLL_ENABLE |
 845                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
 846         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 847         POSTING_READ(FDI_RX_CTL(PIPE_A));
 848         udelay(220);
 849
 850         /* Switch from Rawclk to PCDclk */
 851         rx_ctl_val |= FDI_PCDCLK;
 852         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 853
 854         /* Configure Port Clock Select */
 855         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
 856         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
 857         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
 858
 859         /* Start the training iterating through available voltages and emphasis,
 860          * testing each value twice. */
 861         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 862                 /* Configure DP_TP_CTL with auto-training */
 863                 I915_WRITE(DP_TP_CTL(PORT_E),
 864                                         DP_TP_CTL_FDI_AUTOTRAIN |
 865                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 866                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 867                                         DP_TP_CTL_ENABLE);
 868
 869                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 870                  * DDI E does not support port reversal, the functionality is
 871                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 872                  * port reversal bit */
 873                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 874                            DDI_BUF_CTL_ENABLE |
 875                            ((crtc_state->fdi_lanes - 1) << 1) |
 876                            DDI_BUF_TRANS_SELECT(i / 2));
 877                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 878
 879                 udelay(600);
 880
 881                 /* Program PCH FDI Receiver TU */
 882                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 883
 884                 /* Enable PCH FDI Receiver with auto-training */
 885                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 886                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 887                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 888
 889                 /* Wait for FDI receiver lane calibration */
 890                 udelay(30);
 891
 892                 /* Unset FDI_RX_MISC pwrdn lanes */
 893                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 894                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 895                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 896                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 897
 898                 /* Wait for FDI auto training time */
 899                 udelay(5);
 900
 901                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 902                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 903                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 904                         break;
 905                 }
 906
 907                 /*
 908                  * Leave things enabled even if we failed to train FDI.
 909                  * Results in less fireworks from the state checker.
 910                  */
 911                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
 912                         DRM_ERROR("FDI link training failed!\n");
 913                         break;
 914                 }
 915
 916                 rx_ctl_val &= ~FDI_RX_ENABLE;
 917                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 918                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 919
 920                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 921                 temp &= ~DDI_BUF_CTL_ENABLE;
 922                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 923                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 924
 925                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 926                 temp = I915_READ(DP_TP_CTL(PORT_E));
 927                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 928                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 929                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 930                 POSTING_READ(DP_TP_CTL(PORT_E));
 931
 932                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 933
 934                 /* Reset FDI_RX_MISC pwrdn lanes */
 935                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 936                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 937                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 938                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 939                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 940         }
 941
 942         /* Enable normal pixel sending for FDI */
 943         I915_WRITE(DP_TP_CTL(PORT_E),
 944                    DP_TP_CTL_FDI_AUTOTRAIN |
 945                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 946                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 947                    DP_TP_CTL_ENABLE);
 948 }
 949
 950 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 951 {
 952         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 953         struct intel_digital_port *intel_dig_port =
 954                 enc_to_dig_port(&encoder->base);
 955
 956         intel_dp->DP = intel_dig_port->saved_port_bits |
 957                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 958         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 959 }
 960
 961 static struct intel_encoder *
 962 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
 963 {
 964         struct drm_device *dev = crtc->base.dev;
 965         struct intel_encoder *encoder, *ret = NULL;
 966         int num_encoders = 0;
 967
 968         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 969                 ret = encoder;
 970                 num_encoders++;
 971         }
 972
 973         if (num_encoders != 1)
 974                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 975                      pipe_name(crtc->pipe));
 976
 977         BUG_ON(ret == NULL);
 978         return ret;
 979 }
 980
 981 /* Finds the only possible encoder associated with the given CRTC. */
 982 struct intel_encoder *
 983 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 984 {
 985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 986         struct intel_encoder *ret = NULL;
 987         struct drm_atomic_state *state;
 988         struct drm_connector *connector;
 989         struct drm_connector_state *connector_state;
 990         int num_encoders = 0;
 991         int i;
 992
 993         state = crtc_state->base.state;
 994
 995         for_each_new_connector_in_state(state, connector, connector_state, i) {
 996                 if (connector_state->crtc != crtc_state->base.crtc)
 997                         continue;
 998
 999                 ret = to_intel_encoder(connector_state->best_encoder);
1000                 num_encoders++;
1001         }
1002
1003         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1004              pipe_name(crtc->pipe));
1005
1006         BUG_ON(ret == NULL);
1007         return ret;
1008 }
1009
1010 #define LC_FREQ 2700
1011
1012 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1013                                    i915_reg_t reg)
1014 {
1015         int refclk = LC_FREQ;
1016         int n, p, r;
1017         u32 wrpll;
1018
1019         wrpll = I915_READ(reg);
1020         switch (wrpll & WRPLL_PLL_REF_MASK) {
1021         case WRPLL_PLL_SSC:
1022         case WRPLL_PLL_NON_SSC:
1023                 /*
1024                  * We could calculate spread here, but our checking
1025                  * code only cares about 5% accuracy, and spread is a max of
1026                  * 0.5% downspread.
1027                  */
1028                 refclk = 135;
1029                 break;
1030         case WRPLL_PLL_LCPLL:
1031                 refclk = LC_FREQ;
1032                 break;
1033         default:
1034                 WARN(1, "bad wrpll refclk\n");
1035                 return 0;
1036         }
1037
1038         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1039         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1040         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1041
1042         /* Convert to KHz, p & r have a fixed point portion */
1043         return (refclk * n * 100) / (p * r);
1044 }
1045
1046 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1047                                uint32_t dpll)
1048 {
1049         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1050         uint32_t cfgcr1_val, cfgcr2_val;
1051         uint32_t p0, p1, p2, dco_freq;
1052
1053         cfgcr1_reg = DPLL_CFGCR1(dpll);
1054         cfgcr2_reg = DPLL_CFGCR2(dpll);
1055
1056         cfgcr1_val = I915_READ(cfgcr1_reg);
1057         cfgcr2_val = I915_READ(cfgcr2_reg);
1058
1059         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1060         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1061
1062         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1063                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1064         else
1065                 p1 = 1;
1066
1067
1068         switch (p0) {
1069         case DPLL_CFGCR2_PDIV_1:
1070                 p0 = 1;
1071                 break;
1072         case DPLL_CFGCR2_PDIV_2:
1073                 p0 = 2;
1074                 break;
1075         case DPLL_CFGCR2_PDIV_3:
1076                 p0 = 3;
1077                 break;
1078         case DPLL_CFGCR2_PDIV_7:
1079                 p0 = 7;
1080                 break;
1081         }
1082
1083         switch (p2) {
1084         case DPLL_CFGCR2_KDIV_5:
1085                 p2 = 5;
1086                 break;
1087         case DPLL_CFGCR2_KDIV_2:
1088                 p2 = 2;
1089                 break;
1090         case DPLL_CFGCR2_KDIV_3:
1091                 p2 = 3;
1092                 break;
1093         case DPLL_CFGCR2_KDIV_1:
1094                 p2 = 1;
1095                 break;
1096         }
1097
1098         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1099
1100         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1101                 1000) / 0x8000;
1102
1103         return dco_freq / (p0 * p1 * p2 * 5);
1104 }
1105
1106 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1107                                uint32_t pll_id)
1108 {
1109         uint32_t cfgcr0, cfgcr1;
1110         uint32_t p0, p1, p2, dco_freq, ref_clock;
1111
1112         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1113         cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1114
1115         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1116         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1117
1118         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1119                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1120                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1121         else
1122                 p1 = 1;
1123
1124
1125         switch (p0) {
1126         case DPLL_CFGCR1_PDIV_2:
1127                 p0 = 2;
1128                 break;
1129         case DPLL_CFGCR1_PDIV_3:
1130                 p0 = 3;
1131                 break;
1132         case DPLL_CFGCR1_PDIV_5:
1133                 p0 = 5;
1134                 break;
1135         case DPLL_CFGCR1_PDIV_7:
1136                 p0 = 7;
1137                 break;
1138         }
1139
1140         switch (p2) {
1141         case DPLL_CFGCR1_KDIV_1:
1142                 p2 = 1;
1143                 break;
1144         case DPLL_CFGCR1_KDIV_2:
1145                 p2 = 2;
1146                 break;
1147         case DPLL_CFGCR1_KDIV_4:
1148                 p2 = 4;
1149                 break;
1150         }
1151
1152         ref_clock = dev_priv->cdclk.hw.ref;
1153
1154         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1155
1156         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1157                       DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
1158
1159         return dco_freq / (p0 * p1 * p2 * 5);
1160 }
1161
1162 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1163 {
1164         int dotclock;
1165
1166         if (pipe_config->has_pch_encoder)
1167                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1168                                                     &pipe_config->fdi_m_n);
1169         else if (intel_crtc_has_dp_encoder(pipe_config))
1170                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1171                                                     &pipe_config->dp_m_n);
1172         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1173                 dotclock = pipe_config->port_clock * 2 / 3;
1174         else
1175                 dotclock = pipe_config->port_clock;
1176
1177         if (pipe_config->pixel_multiplier)
1178                 dotclock /= pipe_config->pixel_multiplier;
1179
1180         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1181 }
1182
1183 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1184                               struct intel_crtc_state *pipe_config)
1185 {
1186         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1187         int link_clock = 0;
1188         uint32_t cfgcr0, pll_id;
1189
1190         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1191
1192         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1193
1194         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1195                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1196         } else {
1197                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1198
1199                 switch (link_clock) {
1200                 case DPLL_CFGCR0_LINK_RATE_810:
1201                         link_clock = 81000;
1202                         break;
1203                 case DPLL_CFGCR0_LINK_RATE_1080:
1204                         link_clock = 108000;
1205                         break;
1206                 case DPLL_CFGCR0_LINK_RATE_1350:
1207                         link_clock = 135000;
1208                         break;
1209                 case DPLL_CFGCR0_LINK_RATE_1620:
1210                         link_clock = 162000;
1211                         break;
1212                 case DPLL_CFGCR0_LINK_RATE_2160:
1213                         link_clock = 216000;
1214                         break;
1215                 case DPLL_CFGCR0_LINK_RATE_2700:
1216                         link_clock = 270000;
1217                         break;
1218                 case DPLL_CFGCR0_LINK_RATE_3240:
1219                         link_clock = 324000;
1220                         break;
1221                 case DPLL_CFGCR0_LINK_RATE_4050:
1222                         link_clock = 405000;
1223                         break;
1224                 default:
1225                         WARN(1, "Unsupported link rate\n");
1226                         break;
1227                 }
1228                 link_clock *= 2;
1229         }
1230
1231         pipe_config->port_clock = link_clock;
1232
1233         ddi_dotclock_get(pipe_config);
1234 }
1235
1236 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1237                                 struct intel_crtc_state *pipe_config)
1238 {
1239         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1240         int link_clock = 0;
1241         uint32_t dpll_ctl1, dpll;
1242
1243         dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1244
1245         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1246
1247         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1248                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1249         } else {
1250                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1251                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1252
1253                 switch (link_clock) {
1254                 case DPLL_CTRL1_LINK_RATE_810:
1255                         link_clock = 81000;
1256                         break;
1257                 case DPLL_CTRL1_LINK_RATE_1080:
1258                         link_clock = 108000;
1259                         break;
1260                 case DPLL_CTRL1_LINK_RATE_1350:
1261                         link_clock = 135000;
1262                         break;
1263                 case DPLL_CTRL1_LINK_RATE_1620:
1264                         link_clock = 162000;
1265                         break;
1266                 case DPLL_CTRL1_LINK_RATE_2160:
1267                         link_clock = 216000;
1268                         break;
1269                 case DPLL_CTRL1_LINK_RATE_2700:
1270                         link_clock = 270000;
1271                         break;
1272                 default:
1273                         WARN(1, "Unsupported link rate\n");
1274                         break;
1275                 }
1276                 link_clock *= 2;
1277         }
1278
1279         pipe_config->port_clock = link_clock;
1280
1281         ddi_dotclock_get(pipe_config);
1282 }
1283
1284 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1285                               struct intel_crtc_state *pipe_config)
1286 {
1287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1288         int link_clock = 0;
1289         u32 val, pll;
1290
1291         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1292         switch (val & PORT_CLK_SEL_MASK) {
1293         case PORT_CLK_SEL_LCPLL_810:
1294                 link_clock = 81000;
1295                 break;
1296         case PORT_CLK_SEL_LCPLL_1350:
1297                 link_clock = 135000;
1298                 break;
1299         case PORT_CLK_SEL_LCPLL_2700:
1300                 link_clock = 270000;
1301                 break;
1302         case PORT_CLK_SEL_WRPLL1:
1303                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1304                 break;
1305         case PORT_CLK_SEL_WRPLL2:
1306                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1307                 break;
1308         case PORT_CLK_SEL_SPLL:
1309                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1310                 if (pll == SPLL_PLL_FREQ_810MHz)
1311                         link_clock = 81000;
1312                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1313                         link_clock = 135000;
1314                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1315                         link_clock = 270000;
1316                 else {
1317                         WARN(1, "bad spll freq\n");
1318                         return;
1319                 }
1320                 break;
1321         default:
1322                 WARN(1, "bad port clock sel\n");
1323                 return;
1324         }
1325
1326         pipe_config->port_clock = link_clock * 2;
1327
1328         ddi_dotclock_get(pipe_config);
1329 }
1330
1331 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1332                                 enum intel_dpll_id dpll)
1333 {
1334         struct intel_shared_dpll *pll;
1335         struct intel_dpll_hw_state *state;
1336         struct dpll clock;
1337
1338         /* For DDI ports we always use a shared PLL. */
1339         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1340                 return 0;
1341
1342         pll = &dev_priv->shared_dplls[dpll];
1343         state = &pll->state.hw_state;
1344
1345         clock.m1 = 2;
1346         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1347         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1348                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1349         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1350         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1351         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1352
1353         return chv_calc_dpll_params(100000, &clock);
1354 }
1355
1356 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1357                                 struct intel_crtc_state *pipe_config)
1358 {
1359         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1360         enum port port = intel_ddi_get_encoder_port(encoder);
1361         uint32_t dpll = port;
1362
1363         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1364
1365         ddi_dotclock_get(pipe_config);
1366 }
1367
1368 void intel_ddi_clock_get(struct intel_encoder *encoder,
1369                          struct intel_crtc_state *pipe_config)
1370 {
1371         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1372
1373         if (INTEL_GEN(dev_priv) <= 8)
1374                 hsw_ddi_clock_get(encoder, pipe_config);
1375         else if (IS_GEN9_BC(dev_priv))
1376                 skl_ddi_clock_get(encoder, pipe_config);
1377         else if (IS_GEN9_LP(dev_priv))
1378                 bxt_ddi_clock_get(encoder, pipe_config);
1379         else if (IS_CANNONLAKE(dev_priv))
1380                 cnl_ddi_clock_get(encoder, pipe_config);
1381 }
1382
1383 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1384 {
1385         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1386         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1387         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1388         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1389         int type = encoder->type;
1390         uint32_t temp;
1391
1392         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1393                 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1394
1395                 temp = TRANS_MSA_SYNC_CLK;
1396                 switch (crtc_state->pipe_bpp) {
1397                 case 18:
1398                         temp |= TRANS_MSA_6_BPC;
1399                         break;
1400                 case 24:
1401                         temp |= TRANS_MSA_8_BPC;
1402                         break;
1403                 case 30:
1404                         temp |= TRANS_MSA_10_BPC;
1405                         break;
1406                 case 36:
1407                         temp |= TRANS_MSA_12_BPC;
1408                         break;
1409                 default:
1410                         BUG();
1411                 }
1412                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1413         }
1414 }
1415
1416 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1417                                     bool state)
1418 {
1419         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1420         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1421         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1422         uint32_t temp;
1423         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1424         if (state == true)
1425                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1426         else
1427                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1428         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1429 }
1430
1431 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1432 {
1433         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1434         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1435         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436         enum pipe pipe = crtc->pipe;
1437         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1438         enum port port = intel_ddi_get_encoder_port(encoder);
1439         int type = encoder->type;
1440         uint32_t temp;
1441
1442         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1443         temp = TRANS_DDI_FUNC_ENABLE;
1444         temp |= TRANS_DDI_SELECT_PORT(port);
1445
1446         switch (crtc_state->pipe_bpp) {
1447         case 18:
1448                 temp |= TRANS_DDI_BPC_6;
1449                 break;
1450         case 24:
1451                 temp |= TRANS_DDI_BPC_8;
1452                 break;
1453         case 30:
1454                 temp |= TRANS_DDI_BPC_10;
1455                 break;
1456         case 36:
1457                 temp |= TRANS_DDI_BPC_12;
1458                 break;
1459         default:
1460                 BUG();
1461         }
1462
1463         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1464                 temp |= TRANS_DDI_PVSYNC;
1465         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1466                 temp |= TRANS_DDI_PHSYNC;
1467
1468         if (cpu_transcoder == TRANSCODER_EDP) {
1469                 switch (pipe) {
1470                 case PIPE_A:
1471                         /* On Haswell, can only use the always-on power well for
1472                          * eDP when not using the panel fitter, and when not
1473                          * using motion blur mitigation (which we don't
1474                          * support). */
1475                         if (IS_HASWELL(dev_priv) &&
1476                             (crtc_state->pch_pfit.enabled ||
1477                              crtc_state->pch_pfit.force_thru))
1478                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1479                         else
1480                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1481                         break;
1482                 case PIPE_B:
1483                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1484                         break;
1485                 case PIPE_C:
1486                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1487                         break;
1488                 default:
1489                         BUG();
1490                         break;
1491                 }
1492         }
1493
1494         if (type == INTEL_OUTPUT_HDMI) {
1495                 if (crtc_state->has_hdmi_sink)
1496                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1497                 else
1498                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1499
1500                 if (crtc_state->hdmi_scrambling)
1501                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1502                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1503                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1504         } else if (type == INTEL_OUTPUT_ANALOG) {
1505                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1506                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1507         } else if (type == INTEL_OUTPUT_DP ||
1508                    type == INTEL_OUTPUT_EDP) {
1509                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1510                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1511         } else if (type == INTEL_OUTPUT_DP_MST) {
1512                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1513                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1514         } else {
1515                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1516                      encoder->type, pipe_name(pipe));
1517         }
1518
1519         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1520 }
1521
1522 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1523                                        enum transcoder cpu_transcoder)
1524 {
1525         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1526         uint32_t val = I915_READ(reg);
1527
1528         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1529         val |= TRANS_DDI_PORT_NONE;
1530         I915_WRITE(reg, val);
1531 }
1532
1533 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1534 {
1535         struct drm_device *dev = intel_connector->base.dev;
1536         struct drm_i915_private *dev_priv = to_i915(dev);
1537         struct intel_encoder *encoder = intel_connector->encoder;
1538         int type = intel_connector->base.connector_type;
1539         enum port port = intel_ddi_get_encoder_port(encoder);
1540         enum pipe pipe = 0;
1541         enum transcoder cpu_transcoder;
1542         uint32_t tmp;
1543         bool ret;
1544
1545         if (!intel_display_power_get_if_enabled(dev_priv,
1546                                                 encoder->power_domain))
1547                 return false;
1548
1549         if (!encoder->get_hw_state(encoder, &pipe)) {
1550                 ret = false;
1551                 goto out;
1552         }
1553
1554         if (port == PORT_A)
1555                 cpu_transcoder = TRANSCODER_EDP;
1556         else
1557                 cpu_transcoder = (enum transcoder) pipe;
1558
1559         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1560
1561         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1562         case TRANS_DDI_MODE_SELECT_HDMI:
1563         case TRANS_DDI_MODE_SELECT_DVI:
1564                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1565                 break;
1566
1567         case TRANS_DDI_MODE_SELECT_DP_SST:
1568                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1569                       type == DRM_MODE_CONNECTOR_DisplayPort;
1570                 break;
1571
1572         case TRANS_DDI_MODE_SELECT_DP_MST:
1573                 /* if the transcoder is in MST state then
1574                  * connector isn't connected */
1575                 ret = false;
1576                 break;
1577
1578         case TRANS_DDI_MODE_SELECT_FDI:
1579                 ret = type == DRM_MODE_CONNECTOR_VGA;
1580                 break;
1581
1582         default:
1583                 ret = false;
1584                 break;
1585         }
1586
1587 out:
1588         intel_display_power_put(dev_priv, encoder->power_domain);
1589
1590         return ret;
1591 }
1592
1593 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1594                             enum pipe *pipe)
1595 {
1596         struct drm_device *dev = encoder->base.dev;
1597         struct drm_i915_private *dev_priv = to_i915(dev);
1598         enum port port = intel_ddi_get_encoder_port(encoder);
1599         u32 tmp;
1600         int i;
1601         bool ret;
1602
1603         if (!intel_display_power_get_if_enabled(dev_priv,
1604                                                 encoder->power_domain))
1605                 return false;
1606
1607         ret = false;
1608
1609         tmp = I915_READ(DDI_BUF_CTL(port));
1610
1611         if (!(tmp & DDI_BUF_CTL_ENABLE))
1612                 goto out;
1613
1614         if (port == PORT_A) {
1615                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1616
1617                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1618                 case TRANS_DDI_EDP_INPUT_A_ON:
1619                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1620                         *pipe = PIPE_A;
1621                         break;
1622                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1623                         *pipe = PIPE_B;
1624                         break;
1625                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1626                         *pipe = PIPE_C;
1627                         break;
1628                 }
1629
1630                 ret = true;
1631
1632                 goto out;
1633         }
1634
1635         for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1636                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1637
1638                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1639                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1640                             TRANS_DDI_MODE_SELECT_DP_MST)
1641                                 goto out;
1642
1643                         *pipe = i;
1644                         ret = true;
1645
1646                         goto out;
1647                 }
1648         }
1649
1650         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1651
1652 out:
1653         if (ret && IS_GEN9_LP(dev_priv)) {
1654                 tmp = I915_READ(BXT_PHY_CTL(port));
1655                 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1656                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1657                         DRM_ERROR("Port %c enabled but PHY powered down? "
1658                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1659         }
1660
1661         intel_display_power_put(dev_priv, encoder->power_domain);
1662
1663         return ret;
1664 }
1665
1666 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1667 {
1668         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1669         enum pipe pipe;
1670
1671         if (intel_ddi_get_hw_state(encoder, &pipe))
1672                 return BIT_ULL(dig_port->ddi_io_power_domain);
1673
1674         return 0;
1675 }
1676
1677 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1678 {
1679         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1680         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1682         enum port port = intel_ddi_get_encoder_port(encoder);
1683         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1684
1685         if (cpu_transcoder != TRANSCODER_EDP)
1686                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1687                            TRANS_CLK_SEL_PORT(port));
1688 }
1689
1690 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1691 {
1692         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1693         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1694
1695         if (cpu_transcoder != TRANSCODER_EDP)
1696                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1697                            TRANS_CLK_SEL_DISABLED);
1698 }
1699
1700 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1701                                 enum port port, uint8_t iboost)
1702 {
1703         u32 tmp;
1704
1705         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1706         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1707         if (iboost)
1708                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1709         else
1710                 tmp |= BALANCE_LEG_DISABLE(port);
1711         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1712 }
1713
1714 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1715 {
1716         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1717         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1718         enum port port = intel_dig_port->port;
1719         int type = encoder->type;
1720         const struct ddi_buf_trans *ddi_translations;
1721         uint8_t iboost;
1722         uint8_t dp_iboost, hdmi_iboost;
1723         int n_entries;
1724
1725         /* VBT may override standard boost values */
1726         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1727         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1728
1729         if (type == INTEL_OUTPUT_DP) {
1730                 if (dp_iboost) {
1731                         iboost = dp_iboost;
1732                 } else {
1733                         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
1734                                 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1735                                                                         &n_entries);
1736                         else
1737                                 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1738                                                                         &n_entries);
1739                         iboost = ddi_translations[level].i_boost;
1740                 }
1741         } else if (type == INTEL_OUTPUT_EDP) {
1742                 if (dp_iboost) {
1743                         iboost = dp_iboost;
1744                 } else {
1745                         ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1746
1747                         if (WARN_ON(port != PORT_A &&
1748                                     port != PORT_E && n_entries > 9))
1749                                 n_entries = 9;
1750
1751                         iboost = ddi_translations[level].i_boost;
1752                 }
1753         } else if (type == INTEL_OUTPUT_HDMI) {
1754                 if (hdmi_iboost) {
1755                         iboost = hdmi_iboost;
1756                 } else {
1757                         ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1758                         iboost = ddi_translations[level].i_boost;
1759                 }
1760         } else {
1761                 return;
1762         }
1763
1764         /* Make sure that the requested I_boost is valid */
1765         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1766                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1767                 return;
1768         }
1769
1770         _skl_ddi_set_iboost(dev_priv, port, iboost);
1771
1772         if (port == PORT_A && intel_dig_port->max_lanes == 4)
1773                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1774 }
1775
1776 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1777                                     u32 level, enum port port, int type)
1778 {
1779         const struct bxt_ddi_buf_trans *ddi_translations;
1780         u32 n_entries, i;
1781
1782         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1783                 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1784                 ddi_translations = bxt_ddi_translations_edp;
1785         } else if (type == INTEL_OUTPUT_DP
1786                         || type == INTEL_OUTPUT_EDP) {
1787                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1788                 ddi_translations = bxt_ddi_translations_dp;
1789         } else if (type == INTEL_OUTPUT_HDMI) {
1790                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1791                 ddi_translations = bxt_ddi_translations_hdmi;
1792         } else {
1793                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1794                                 type);
1795                 return;
1796         }
1797
1798         /* Check if default value has to be used */
1799         if (level >= n_entries ||
1800             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1801                 for (i = 0; i < n_entries; i++) {
1802                         if (ddi_translations[i].default_index) {
1803                                 level = i;
1804                                 break;
1805                         }
1806                 }
1807         }
1808
1809         bxt_ddi_phy_set_signal_level(dev_priv, port,
1810                                      ddi_translations[level].margin,
1811                                      ddi_translations[level].scale,
1812                                      ddi_translations[level].enable,
1813                                      ddi_translations[level].deemphasis);
1814 }
1815
1816 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1817 {
1818         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1819         int n_entries;
1820
1821         if (encoder->type == INTEL_OUTPUT_EDP)
1822                 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1823         else
1824                 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1825
1826         if (WARN_ON(n_entries < 1))
1827                 n_entries = 1;
1828         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1829                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1830
1831         return index_to_dp_signal_levels[n_entries - 1] &
1832                 DP_TRAIN_VOLTAGE_SWING_MASK;
1833 }
1834
1835 static const struct cnl_ddi_buf_trans *
1836 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
1837                        u32 voltage, int *n_entries)
1838 {
1839         if (voltage == VOLTAGE_INFO_0_85V) {
1840                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1841                 return cnl_ddi_translations_hdmi_0_85V;
1842         } else if (voltage == VOLTAGE_INFO_0_95V) {
1843                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1844                 return cnl_ddi_translations_hdmi_0_95V;
1845         } else if (voltage == VOLTAGE_INFO_1_05V) {
1846                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1847                 return cnl_ddi_translations_hdmi_1_05V;
1848         }
1849         return NULL;
1850 }
1851
1852 static const struct cnl_ddi_buf_trans *
1853 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
1854                      u32 voltage, int *n_entries)
1855 {
1856         if (voltage == VOLTAGE_INFO_0_85V) {
1857                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1858                 return cnl_ddi_translations_dp_0_85V;
1859         } else if (voltage == VOLTAGE_INFO_0_95V) {
1860                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1861                 return cnl_ddi_translations_dp_0_95V;
1862         } else if (voltage == VOLTAGE_INFO_1_05V) {
1863                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1864                 return cnl_ddi_translations_dp_1_05V;
1865         }
1866         return NULL;
1867 }
1868
1869 static const struct cnl_ddi_buf_trans *
1870 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
1871                       u32 voltage, int *n_entries)
1872 {
1873         if (dev_priv->vbt.edp.low_vswing) {
1874                 if (voltage == VOLTAGE_INFO_0_85V) {
1875                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1876                         return cnl_ddi_translations_dp_0_85V;
1877                 } else if (voltage == VOLTAGE_INFO_0_95V) {
1878                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1879                         return cnl_ddi_translations_edp_0_95V;
1880                 } else if (voltage == VOLTAGE_INFO_1_05V) {
1881                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1882                         return cnl_ddi_translations_edp_1_05V;
1883                 }
1884                 return NULL;
1885         } else {
1886                 return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
1887         }
1888 }
1889
1890 static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1891                                     u32 level, enum port port, int type)
1892 {
1893         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
1894         u32 n_entries, val, voltage;
1895         int ln;
1896
1897         /*
1898          * Values for each port type are listed in
1899          * voltage swing programming tables.
1900          * Vccio voltage found in PORT_COMP_DW3.
1901          */
1902         voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1903
1904         if (type == INTEL_OUTPUT_HDMI) {
1905                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
1906                                                           voltage, &n_entries);
1907         } else if (type == INTEL_OUTPUT_DP) {
1908                 ddi_translations = cnl_get_buf_trans_dp(dev_priv,
1909                                                         voltage, &n_entries);
1910         } else if (type == INTEL_OUTPUT_EDP) {
1911                 ddi_translations = cnl_get_buf_trans_edp(dev_priv,
1912                                                          voltage, &n_entries);
1913         }
1914
1915         if (ddi_translations == NULL) {
1916                 MISSING_CASE(voltage);
1917                 return;
1918         }
1919
1920         if (level >= n_entries) {
1921                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1922                 level = n_entries - 1;
1923         }
1924
1925         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1926         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1927         val &= ~SCALING_MODE_SEL_MASK;
1928         val |= SCALING_MODE_SEL(2);
1929         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1930
1931         /* Program PORT_TX_DW2 */
1932         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1933         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1934                  RCOMP_SCALAR_MASK);
1935         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1936         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1937         /* Rcomp scalar is fixed as 0x98 for every table entry */
1938         val |= RCOMP_SCALAR(0x98);
1939         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1940
1941         /* Program PORT_TX_DW4 */
1942         /* We cannot write to GRP. It would overrite individual loadgen */
1943         for (ln = 0; ln < 4; ln++) {
1944                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1945                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1946                          CURSOR_COEFF_MASK);
1947                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1948                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1949                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1950                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1951         }
1952
1953         /* Program PORT_TX_DW5 */
1954         /* All DW5 values are fixed for every table entry */
1955         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1956         val &= ~RTERM_SELECT_MASK;
1957         val |= RTERM_SELECT(6);
1958         val |= TAP3_DISABLE;
1959         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1960
1961         /* Program PORT_TX_DW7 */
1962         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1963         val &= ~N_SCALAR_MASK;
1964         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1965         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1966 }
1967
1968 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
1969 {
1970         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1971         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1972         enum port port = intel_ddi_get_encoder_port(encoder);
1973         int type = encoder->type;
1974         int width = 0;
1975         int rate = 0;
1976         u32 val;
1977         int ln = 0;
1978
1979         if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
1980                 width = intel_dp->lane_count;
1981                 rate = intel_dp->link_rate;
1982         } else {
1983                 width = 4;
1984                 /* Rate is always < than 6GHz for HDMI */
1985         }
1986
1987         /*
1988          * 1. If port type is eDP or DP,
1989          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1990          * else clear to 0b.
1991          */
1992         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
1993         if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
1994                 val |= COMMON_KEEPER_EN;
1995         else
1996                 val &= ~COMMON_KEEPER_EN;
1997         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
1998
1999         /* 2. Program loadgen select */
2000         /*
2001          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2002          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2003          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2004          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2005          */
2006         for (ln = 0; ln <= 3; ln++) {
2007                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2008                 val &= ~LOADGEN_SELECT;
2009
2010                 if (((rate < 600000) && (width == 4) && (ln >= 1))  ||
2011                     ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
2012                         val |= LOADGEN_SELECT;
2013                 }
2014                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2015         }
2016
2017         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2018         val = I915_READ(CNL_PORT_CL1CM_DW5);
2019         val |= SUS_CLOCK_CONFIG;
2020         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2021
2022         /* 4. Clear training enable to change swing values */
2023         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2024         val &= ~TX_TRAINING_EN;
2025         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2026
2027         /* 5. Program swing and de-emphasis */
2028         cnl_ddi_vswing_program(dev_priv, level, port, type);
2029
2030         /* 6. Set training enable to trigger update */
2031         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2032         val |= TX_TRAINING_EN;
2033         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2034 }
2035
2036 static uint32_t translate_signal_level(int signal_levels)
2037 {
2038         int i;
2039
2040         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2041                 if (index_to_dp_signal_levels[i] == signal_levels)
2042                         return i;
2043         }
2044
2045         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2046              signal_levels);
2047
2048         return 0;
2049 }
2050
2051 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2052 {
2053         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2054         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2055         struct intel_encoder *encoder = &dport->base;
2056         uint8_t train_set = intel_dp->train_set[0];
2057         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2058                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2059         enum port port = dport->port;
2060         uint32_t level;
2061
2062         level = translate_signal_level(signal_levels);
2063
2064         if (IS_GEN9_BC(dev_priv))
2065                 skl_ddi_set_iboost(encoder, level);
2066         else if (IS_GEN9_LP(dev_priv))
2067                 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2068         else if (IS_CANNONLAKE(dev_priv)) {
2069                 cnl_ddi_vswing_sequence(encoder, level);
2070                 /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
2071                 return 0;
2072         }
2073         return DDI_BUF_TRANS_SELECT(level);
2074 }
2075
2076 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2077                                  struct intel_shared_dpll *pll)
2078 {
2079         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2080         enum port port = intel_ddi_get_encoder_port(encoder);
2081         uint32_t val;
2082
2083         if (WARN_ON(!pll))
2084                 return;
2085
2086         if (IS_CANNONLAKE(dev_priv)) {
2087                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2088                 val = I915_READ(DPCLKA_CFGCR0);
2089                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2090                 I915_WRITE(DPCLKA_CFGCR0, val);
2091
2092                 /*
2093                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2094                  * This step and the step before must be done with separate
2095                  * register writes.
2096                  */
2097                 val = I915_READ(DPCLKA_CFGCR0);
2098                 val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
2099                          DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
2100                 I915_WRITE(DPCLKA_CFGCR0, val);
2101         } else if (IS_GEN9_BC(dev_priv)) {
2102                 /* DDI -> PLL mapping  */
2103                 val = I915_READ(DPLL_CTRL2);
2104
2105                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2106                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2107                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2108                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2109
2110                 I915_WRITE(DPLL_CTRL2, val);
2111
2112         } else if (INTEL_INFO(dev_priv)->gen < 9) {
2113                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2114         }
2115 }
2116
2117 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2118                                     int link_rate, uint32_t lane_count,
2119                                     struct intel_shared_dpll *pll,
2120                                     bool link_mst)
2121 {
2122         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2123         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2124         enum port port = intel_ddi_get_encoder_port(encoder);
2125         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2126
2127         WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2128
2129         intel_dp_set_link_params(intel_dp, link_rate, lane_count,
2130                                  link_mst);
2131         if (encoder->type == INTEL_OUTPUT_EDP)
2132                 intel_edp_panel_on(intel_dp);
2133
2134         intel_ddi_clk_select(encoder, pll);
2135
2136         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2137
2138         intel_prepare_dp_ddi_buffers(encoder);
2139         intel_ddi_init_dp_buf_reg(encoder);
2140         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2141         intel_dp_start_link_train(intel_dp);
2142         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2143                 intel_dp_stop_link_train(intel_dp);
2144 }
2145
2146 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2147                                       bool has_hdmi_sink,
2148                                       const struct intel_crtc_state *crtc_state,
2149                                       const struct drm_connector_state *conn_state,
2150                                       struct intel_shared_dpll *pll)
2151 {
2152         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2153         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2154         struct drm_encoder *drm_encoder = &encoder->base;
2155         enum port port = intel_ddi_get_encoder_port(encoder);
2156         int level = intel_ddi_hdmi_level(dev_priv, port);
2157         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2158
2159         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2160         intel_ddi_clk_select(encoder, pll);
2161
2162         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2163
2164         intel_prepare_hdmi_ddi_buffers(encoder);
2165         if (IS_GEN9_BC(dev_priv))
2166                 skl_ddi_set_iboost(encoder, level);
2167         else if (IS_GEN9_LP(dev_priv))
2168                 bxt_ddi_vswing_sequence(dev_priv, level, port,
2169                                         INTEL_OUTPUT_HDMI);
2170         else if (IS_CANNONLAKE(dev_priv))
2171                 cnl_ddi_vswing_sequence(encoder, level);
2172
2173         intel_hdmi->set_infoframes(drm_encoder,
2174                                    has_hdmi_sink,
2175                                    crtc_state, conn_state);
2176 }
2177
2178 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2179                                  struct intel_crtc_state *pipe_config,
2180                                  struct drm_connector_state *conn_state)
2181 {
2182         int type = encoder->type;
2183
2184         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2185                 intel_ddi_pre_enable_dp(encoder,
2186                                         pipe_config->port_clock,
2187                                         pipe_config->lane_count,
2188                                         pipe_config->shared_dpll,
2189                                         intel_crtc_has_type(pipe_config,
2190                                                             INTEL_OUTPUT_DP_MST));
2191         }
2192         if (type == INTEL_OUTPUT_HDMI) {
2193                 intel_ddi_pre_enable_hdmi(encoder,
2194                                           pipe_config->has_hdmi_sink,
2195                                           pipe_config, conn_state,
2196                                           pipe_config->shared_dpll);
2197         }
2198 }
2199
2200 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2201                                    struct intel_crtc_state *old_crtc_state,
2202                                    struct drm_connector_state *old_conn_state)
2203 {
2204         struct drm_encoder *encoder = &intel_encoder->base;
2205         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2206         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2207         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2208         struct intel_dp *intel_dp = NULL;
2209         int type = intel_encoder->type;
2210         uint32_t val;
2211         bool wait = false;
2212
2213         /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
2214
2215         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2216                 intel_dp = enc_to_intel_dp(encoder);
2217                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2218         }
2219
2220         val = I915_READ(DDI_BUF_CTL(port));
2221         if (val & DDI_BUF_CTL_ENABLE) {
2222                 val &= ~DDI_BUF_CTL_ENABLE;
2223                 I915_WRITE(DDI_BUF_CTL(port), val);
2224                 wait = true;
2225         }
2226
2227         val = I915_READ(DP_TP_CTL(port));
2228         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2229         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2230         I915_WRITE(DP_TP_CTL(port), val);
2231
2232         if (wait)
2233                 intel_wait_ddi_buf_idle(dev_priv, port);
2234
2235         if (intel_dp) {
2236                 intel_edp_panel_vdd_on(intel_dp);
2237                 intel_edp_panel_off(intel_dp);
2238         }
2239
2240         if (dig_port)
2241                 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2242
2243         if (IS_CANNONLAKE(dev_priv))
2244                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2245                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2246         else if (IS_GEN9_BC(dev_priv))
2247                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2248                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
2249         else if (INTEL_GEN(dev_priv) < 9)
2250                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2251
2252         if (type == INTEL_OUTPUT_HDMI) {
2253                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2254
2255                 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2256         }
2257 }
2258
2259 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2260                                 struct intel_crtc_state *old_crtc_state,
2261                                 struct drm_connector_state *old_conn_state)
2262 {
2263         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2264         uint32_t val;
2265
2266         /*
2267          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2268          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2269          * step 13 is the correct place for it. Step 18 is where it was
2270          * originally before the BUN.
2271          */
2272         val = I915_READ(FDI_RX_CTL(PIPE_A));
2273         val &= ~FDI_RX_ENABLE;
2274         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2275
2276         intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
2277
2278         val = I915_READ(FDI_RX_MISC(PIPE_A));
2279         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2280         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2281         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2282
2283         val = I915_READ(FDI_RX_CTL(PIPE_A));
2284         val &= ~FDI_PCDCLK;
2285         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2286
2287         val = I915_READ(FDI_RX_CTL(PIPE_A));
2288         val &= ~FDI_RX_PLL_ENABLE;
2289         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2290 }
2291
2292 static void intel_enable_ddi(struct intel_encoder *intel_encoder,
2293                              struct intel_crtc_state *pipe_config,
2294                              struct drm_connector_state *conn_state)
2295 {
2296         struct drm_encoder *encoder = &intel_encoder->base;
2297         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2298         enum port port = intel_ddi_get_encoder_port(intel_encoder);
2299         int type = intel_encoder->type;
2300
2301         if (type == INTEL_OUTPUT_HDMI) {
2302                 struct intel_digital_port *intel_dig_port =
2303                         enc_to_dig_port(encoder);
2304                 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
2305                 bool scrambling = pipe_config->hdmi_scrambling;
2306
2307                 intel_hdmi_handle_sink_scrambling(intel_encoder,
2308                                                   conn_state->connector,
2309                                                   clock_ratio, scrambling);
2310
2311                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2312                  * are ignored so nothing special needs to be done besides
2313                  * enabling the port.
2314                  */
2315                 I915_WRITE(DDI_BUF_CTL(port),
2316                            intel_dig_port->saved_port_bits |
2317                            DDI_BUF_CTL_ENABLE);
2318         } else if (type == INTEL_OUTPUT_EDP) {
2319                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2320
2321                 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2322                         intel_dp_stop_link_train(intel_dp);
2323
2324                 intel_edp_backlight_on(pipe_config, conn_state);
2325                 intel_psr_enable(intel_dp);
2326                 intel_edp_drrs_enable(intel_dp, pipe_config);
2327         }
2328
2329         if (pipe_config->has_audio)
2330                 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
2331 }
2332
2333 static void intel_disable_ddi(struct intel_encoder *intel_encoder,
2334                               struct intel_crtc_state *old_crtc_state,
2335                               struct drm_connector_state *old_conn_state)
2336 {
2337         struct drm_encoder *encoder = &intel_encoder->base;
2338         int type = intel_encoder->type;
2339
2340         if (old_crtc_state->has_audio)
2341                 intel_audio_codec_disable(intel_encoder);
2342
2343         if (type == INTEL_OUTPUT_HDMI) {
2344                 intel_hdmi_handle_sink_scrambling(intel_encoder,
2345                                                   old_conn_state->connector,
2346                                                   false, false);
2347         }
2348
2349         if (type == INTEL_OUTPUT_EDP) {
2350                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2351
2352                 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2353                 intel_psr_disable(intel_dp);
2354                 intel_edp_backlight_off(old_conn_state);
2355         }
2356 }
2357
2358 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2359                                    struct intel_crtc_state *pipe_config,
2360                                    struct drm_connector_state *conn_state)
2361 {
2362         uint8_t mask = pipe_config->lane_lat_optim_mask;
2363
2364         bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2365 }
2366
2367 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2368 {
2369         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2370         struct drm_i915_private *dev_priv =
2371                 to_i915(intel_dig_port->base.base.dev);
2372         enum port port = intel_dig_port->port;
2373         uint32_t val;
2374         bool wait = false;
2375
2376         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2377                 val = I915_READ(DDI_BUF_CTL(port));
2378                 if (val & DDI_BUF_CTL_ENABLE) {
2379                         val &= ~DDI_BUF_CTL_ENABLE;
2380                         I915_WRITE(DDI_BUF_CTL(port), val);
2381                         wait = true;
2382                 }
2383
2384                 val = I915_READ(DP_TP_CTL(port));
2385                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2386                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2387                 I915_WRITE(DP_TP_CTL(port), val);
2388                 POSTING_READ(DP_TP_CTL(port));
2389
2390                 if (wait)
2391                         intel_wait_ddi_buf_idle(dev_priv, port);
2392         }
2393
2394         val = DP_TP_CTL_ENABLE |
2395               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2396         if (intel_dp->link_mst)
2397                 val |= DP_TP_CTL_MODE_MST;
2398         else {
2399                 val |= DP_TP_CTL_MODE_SST;
2400                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2401                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2402         }
2403         I915_WRITE(DP_TP_CTL(port), val);
2404         POSTING_READ(DP_TP_CTL(port));
2405
2406         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2407         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2408         POSTING_READ(DDI_BUF_CTL(port));
2409
2410         udelay(600);
2411 }
2412
2413 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2414                                  struct intel_crtc *intel_crtc)
2415 {
2416         u32 temp;
2417
2418         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2419                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2420                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2421                         return true;
2422         }
2423         return false;
2424 }
2425
2426 void intel_ddi_get_config(struct intel_encoder *encoder,
2427                           struct intel_crtc_state *pipe_config)
2428 {
2429         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2430         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2431         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2432         struct intel_hdmi *intel_hdmi;
2433         u32 temp, flags = 0;
2434
2435         /* XXX: DSI transcoder paranoia */
2436         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2437                 return;
2438
2439         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2440         if (temp & TRANS_DDI_PHSYNC)
2441                 flags |= DRM_MODE_FLAG_PHSYNC;
2442         else
2443                 flags |= DRM_MODE_FLAG_NHSYNC;
2444         if (temp & TRANS_DDI_PVSYNC)
2445                 flags |= DRM_MODE_FLAG_PVSYNC;
2446         else
2447                 flags |= DRM_MODE_FLAG_NVSYNC;
2448
2449         pipe_config->base.adjusted_mode.flags |= flags;
2450
2451         switch (temp & TRANS_DDI_BPC_MASK) {
2452         case TRANS_DDI_BPC_6:
2453                 pipe_config->pipe_bpp = 18;
2454                 break;
2455         case TRANS_DDI_BPC_8:
2456                 pipe_config->pipe_bpp = 24;
2457                 break;
2458         case TRANS_DDI_BPC_10:
2459                 pipe_config->pipe_bpp = 30;
2460                 break;
2461         case TRANS_DDI_BPC_12:
2462                 pipe_config->pipe_bpp = 36;
2463                 break;
2464         default:
2465                 break;
2466         }
2467
2468         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2469         case TRANS_DDI_MODE_SELECT_HDMI:
2470                 pipe_config->has_hdmi_sink = true;
2471                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2472
2473                 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2474                         pipe_config->has_infoframe = true;
2475
2476                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2477                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
2478                         pipe_config->hdmi_scrambling = true;
2479                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2480                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2481                 /* fall through */
2482         case TRANS_DDI_MODE_SELECT_DVI:
2483                 pipe_config->lane_count = 4;
2484                 break;
2485         case TRANS_DDI_MODE_SELECT_FDI:
2486                 break;
2487         case TRANS_DDI_MODE_SELECT_DP_SST:
2488         case TRANS_DDI_MODE_SELECT_DP_MST:
2489                 pipe_config->lane_count =
2490                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2491                 intel_dp_get_m_n(intel_crtc, pipe_config);
2492                 break;
2493         default:
2494                 break;
2495         }
2496
2497         pipe_config->has_audio =
2498                 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2499
2500         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2501             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2502                 /*
2503                  * This is a big fat ugly hack.
2504                  *
2505                  * Some machines in UEFI boot mode provide us a VBT that has 18
2506                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2507                  * unknown we fail to light up. Yet the same BIOS boots up with
2508                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2509                  * max, not what it tells us to use.
2510                  *
2511                  * Note: This will still be broken if the eDP panel is not lit
2512                  * up by the BIOS, and thus we can't get the mode at module
2513                  * load.
2514                  */
2515                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2516                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2517                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2518         }
2519
2520         intel_ddi_clock_get(encoder, pipe_config);
2521
2522         if (IS_GEN9_LP(dev_priv))
2523                 pipe_config->lane_lat_optim_mask =
2524                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2525 }
2526
2527 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2528                                      struct intel_crtc_state *pipe_config,
2529                                      struct drm_connector_state *conn_state)
2530 {
2531         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2532         int type = encoder->type;
2533         int port = intel_ddi_get_encoder_port(encoder);
2534         int ret;
2535
2536         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2537
2538         if (port == PORT_A)
2539                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2540
2541         if (type == INTEL_OUTPUT_HDMI)
2542                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2543         else
2544                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2545
2546         if (IS_GEN9_LP(dev_priv) && ret)
2547                 pipe_config->lane_lat_optim_mask =
2548                         bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2549                                                              pipe_config->lane_count);
2550
2551         return ret;
2552
2553 }
2554
2555 static const struct drm_encoder_funcs intel_ddi_funcs = {
2556         .reset = intel_dp_encoder_reset,
2557         .destroy = intel_dp_encoder_destroy,
2558 };
2559
2560 static struct intel_connector *
2561 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2562 {
2563         struct intel_connector *connector;
2564         enum port port = intel_dig_port->port;
2565
2566         connector = intel_connector_alloc();
2567         if (!connector)
2568                 return NULL;
2569
2570         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2571         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2572                 kfree(connector);
2573                 return NULL;
2574         }
2575
2576         return connector;
2577 }
2578
2579 static struct intel_connector *
2580 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2581 {
2582         struct intel_connector *connector;
2583         enum port port = intel_dig_port->port;
2584
2585         connector = intel_connector_alloc();
2586         if (!connector)
2587                 return NULL;
2588
2589         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2590         intel_hdmi_init_connector(intel_dig_port, connector);
2591
2592         return connector;
2593 }
2594
2595 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
2596 {
2597         struct intel_digital_port *intel_dig_port;
2598         struct intel_encoder *intel_encoder;
2599         struct drm_encoder *encoder;
2600         bool init_hdmi, init_dp, init_lspcon = false;
2601         int max_lanes;
2602
2603         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2604                 switch (port) {
2605                 case PORT_A:
2606                         max_lanes = 4;
2607                         break;
2608                 case PORT_E:
2609                         max_lanes = 0;
2610                         break;
2611                 default:
2612                         max_lanes = 4;
2613                         break;
2614                 }
2615         } else {
2616                 switch (port) {
2617                 case PORT_A:
2618                         max_lanes = 2;
2619                         break;
2620                 case PORT_E:
2621                         max_lanes = 2;
2622                         break;
2623                 default:
2624                         max_lanes = 4;
2625                         break;
2626                 }
2627         }
2628
2629         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2630                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2631         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2632
2633         if (intel_bios_is_lspcon_present(dev_priv, port)) {
2634                 /*
2635                  * Lspcon device needs to be driven with DP connector
2636                  * with special detection sequence. So make sure DP
2637                  * is initialized before lspcon.
2638                  */
2639                 init_dp = true;
2640                 init_lspcon = true;
2641                 init_hdmi = false;
2642                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2643         }
2644
2645         if (!init_dp && !init_hdmi) {
2646                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2647                               port_name(port));
2648                 return;
2649         }
2650
2651         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2652         if (!intel_dig_port)
2653                 return;
2654
2655         intel_encoder = &intel_dig_port->base;
2656         encoder = &intel_encoder->base;
2657
2658         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2659                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2660
2661         intel_encoder->compute_config = intel_ddi_compute_config;
2662         intel_encoder->enable = intel_enable_ddi;
2663         if (IS_GEN9_LP(dev_priv))
2664                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2665         intel_encoder->pre_enable = intel_ddi_pre_enable;
2666         intel_encoder->disable = intel_disable_ddi;
2667         intel_encoder->post_disable = intel_ddi_post_disable;
2668         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2669         intel_encoder->get_config = intel_ddi_get_config;
2670         intel_encoder->suspend = intel_dp_encoder_suspend;
2671         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
2672
2673         intel_dig_port->port = port;
2674         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2675                                           (DDI_BUF_PORT_REVERSAL |
2676                                            DDI_A_4_LANES);
2677
2678         switch (port) {
2679         case PORT_A:
2680                 intel_dig_port->ddi_io_power_domain =
2681                         POWER_DOMAIN_PORT_DDI_A_IO;
2682                 break;
2683         case PORT_B:
2684                 intel_dig_port->ddi_io_power_domain =
2685                         POWER_DOMAIN_PORT_DDI_B_IO;
2686                 break;
2687         case PORT_C:
2688                 intel_dig_port->ddi_io_power_domain =
2689                         POWER_DOMAIN_PORT_DDI_C_IO;
2690                 break;
2691         case PORT_D:
2692                 intel_dig_port->ddi_io_power_domain =
2693                         POWER_DOMAIN_PORT_DDI_D_IO;
2694                 break;
2695         case PORT_E:
2696                 intel_dig_port->ddi_io_power_domain =
2697                         POWER_DOMAIN_PORT_DDI_E_IO;
2698                 break;
2699         default:
2700                 MISSING_CASE(port);
2701         }
2702
2703         /*
2704          * Bspec says that DDI_A_4_LANES is the only supported configuration
2705          * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
2706          * wasn't lit up at boot.  Force this bit on in our internal
2707          * configuration so that we use the proper lane count for our
2708          * calculations.
2709          */
2710         if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
2711                 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2712                         DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2713                         intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2714                         max_lanes = 4;
2715                 }
2716         }
2717
2718         intel_dig_port->max_lanes = max_lanes;
2719
2720         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2721         intel_encoder->power_domain = intel_port_to_power_domain(port);
2722         intel_encoder->port = port;
2723         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2724         intel_encoder->cloneable = 0;
2725
2726         if (init_dp) {
2727                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2728                         goto err;
2729
2730                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2731                 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2732         }
2733
2734         /* In theory we don't need the encoder->type check, but leave it just in
2735          * case we have some really bad VBTs... */
2736         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2737                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2738                         goto err;
2739         }
2740
2741         if (init_lspcon) {
2742                 if (lspcon_init(intel_dig_port))
2743                         /* TODO: handle hdmi info frame part */
2744                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2745                                 port_name(port));
2746                 else
2747                         /*
2748                          * LSPCON init faied, but DP init was success, so
2749                          * lets try to drive as DP++ port.
2750                          */
2751                         DRM_ERROR("LSPCON init failed on port %c\n",
2752                                 port_name(port));
2753         }
2754
2755         return;
2756
2757 err:
2758         drm_encoder_cleanup(encoder);
2759         kfree(intel_dig_port);
2760 }