drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 /* Primary plane formats for gen <= 3 */
  53 static const uint32_t i8xx_primary_formats[] = {
  54         DRM_FORMAT_C8,
  55         DRM_FORMAT_RGB565,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_XRGB8888,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t i965_primary_formats[] = {
  62         DRM_FORMAT_C8,
  63         DRM_FORMAT_RGB565,
  64         DRM_FORMAT_XRGB8888,
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68 };
  69
  70 static const uint64_t i9xx_format_modifiers[] = {
  71         I915_FORMAT_MOD_X_TILED,
  72         DRM_FORMAT_MOD_LINEAR,
  73         DRM_FORMAT_MOD_INVALID
  74 };
  75
  76 static const uint32_t skl_primary_formats[] = {
  77         DRM_FORMAT_C8,
  78         DRM_FORMAT_RGB565,
  79         DRM_FORMAT_XRGB8888,
  80         DRM_FORMAT_XBGR8888,
  81         DRM_FORMAT_ARGB8888,
  82         DRM_FORMAT_ABGR8888,
  83         DRM_FORMAT_XRGB2101010,
  84         DRM_FORMAT_XBGR2101010,
  85         DRM_FORMAT_YUYV,
  86         DRM_FORMAT_YVYU,
  87         DRM_FORMAT_UYVY,
  88         DRM_FORMAT_VYUY,
  89 };
  90
  91 static const uint64_t skl_format_modifiers_noccs[] = {
  92         I915_FORMAT_MOD_Yf_TILED,
  93         I915_FORMAT_MOD_Y_TILED,
  94         I915_FORMAT_MOD_X_TILED,
  95         DRM_FORMAT_MOD_LINEAR,
  96         DRM_FORMAT_MOD_INVALID
  97 };
  98
  99 static const uint64_t skl_format_modifiers_ccs[] = {
 100         I915_FORMAT_MOD_Yf_TILED_CCS,
 101         I915_FORMAT_MOD_Y_TILED_CCS,
 102         I915_FORMAT_MOD_Yf_TILED,
 103         I915_FORMAT_MOD_Y_TILED,
 104         I915_FORMAT_MOD_X_TILED,
 105         DRM_FORMAT_MOD_LINEAR,
 106         DRM_FORMAT_MOD_INVALID
 107 };
 108
 109 /* Cursor formats */
 110 static const uint32_t intel_cursor_formats[] = {
 111         DRM_FORMAT_ARGB8888,
 112 };
 113
 114 static const uint64_t cursor_format_modifiers[] = {
 115         DRM_FORMAT_MOD_LINEAR,
 116         DRM_FORMAT_MOD_INVALID
 117 };
 118
 119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 120                                 struct intel_crtc_state *pipe_config);
 121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 122                                    struct intel_crtc_state *pipe_config);
 123
 124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 125                                   struct drm_i915_gem_object *obj,
 126                                   struct drm_mode_fb_cmd2 *mode_cmd);
 127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 131                                          struct intel_link_m_n *m_n,
 132                                          struct intel_link_m_n *m2_n2);
 133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 136 static void vlv_prepare_pll(struct intel_crtc *crtc,
 137                             const struct intel_crtc_state *pipe_config);
 138 static void chv_prepare_pll(struct intel_crtc *crtc,
 139                             const struct intel_crtc_state *pipe_config);
 140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 143                                     struct intel_crtc_state *crtc_state);
 144 static void skylake_pfit_enable(struct intel_crtc *crtc);
 145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 148                                          struct drm_modeset_acquire_ctx *ctx);
 149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 150
 151 struct intel_limit {
 152         struct {
 153                 int min, max;
 154         } dot, vco, n, m, m1, m2, p, p1;
 155
 156         struct {
 157                 int dot_limit;
 158                 int p2_slow, p2_fast;
 159         } p2;
 160 };
 161
 162 /* returns HPLL frequency in kHz */
 163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 164 {
 165         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 166
 167         /* Obtain SKU information */
 168         mutex_lock(&dev_priv->sb_lock);
 169         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 170                 CCK_FUSE_HPLL_FREQ_MASK;
 171         mutex_unlock(&dev_priv->sb_lock);
 172
 173         return vco_freq[hpll_freq] * 1000;
 174 }
 175
 176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 177                       const char *name, u32 reg, int ref_freq)
 178 {
 179         u32 val;
 180         int divider;
 181
 182         mutex_lock(&dev_priv->sb_lock);
 183         val = vlv_cck_read(dev_priv, reg);
 184         mutex_unlock(&dev_priv->sb_lock);
 185
 186         divider = val & CCK_FREQUENCY_VALUES;
 187
 188         WARN((val & CCK_FREQUENCY_STATUS) !=
 189              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 190              "%s change in progress\n", name);
 191
 192         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 193 }
 194
 195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 196                            const char *name, u32 reg)
 197 {
 198         if (dev_priv->hpll_freq == 0)
 199                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 200
 201         return vlv_get_cck_clock(dev_priv, name, reg,
 202                                  dev_priv->hpll_freq);
 203 }
 204
 205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 206 {
 207         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 208                 return;
 209
 210         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 211                                                       CCK_CZ_CLOCK_CONTROL);
 212
 213         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 214 }
 215
 216 static inline u32 /* units of 100MHz */
 217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 218                     const struct intel_crtc_state *pipe_config)
 219 {
 220         if (HAS_DDI(dev_priv))
 221                 return pipe_config->port_clock; /* SPLL */
 222         else if (IS_GEN5(dev_priv))
 223                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 224         else
 225                 return 270000;
 226 }
 227
 228 static const struct intel_limit intel_limits_i8xx_dac = {
 229         .dot = { .min = 25000, .max = 350000 },
 230         .vco = { .min = 908000, .max = 1512000 },
 231         .n = { .min = 2, .max = 16 },
 232         .m = { .min = 96, .max = 140 },
 233         .m1 = { .min = 18, .max = 26 },
 234         .m2 = { .min = 6, .max = 16 },
 235         .p = { .min = 4, .max = 128 },
 236         .p1 = { .min = 2, .max = 33 },
 237         .p2 = { .dot_limit = 165000,
 238                 .p2_slow = 4, .p2_fast = 2 },
 239 };
 240
 241 static const struct intel_limit intel_limits_i8xx_dvo = {
 242         .dot = { .min = 25000, .max = 350000 },
 243         .vco = { .min = 908000, .max = 1512000 },
 244         .n = { .min = 2, .max = 16 },
 245         .m = { .min = 96, .max = 140 },
 246         .m1 = { .min = 18, .max = 26 },
 247         .m2 = { .min = 6, .max = 16 },
 248         .p = { .min = 4, .max = 128 },
 249         .p1 = { .min = 2, .max = 33 },
 250         .p2 = { .dot_limit = 165000,
 251                 .p2_slow = 4, .p2_fast = 4 },
 252 };
 253
 254 static const struct intel_limit intel_limits_i8xx_lvds = {
 255         .dot = { .min = 25000, .max = 350000 },
 256         .vco = { .min = 908000, .max = 1512000 },
 257         .n = { .min = 2, .max = 16 },
 258         .m = { .min = 96, .max = 140 },
 259         .m1 = { .min = 18, .max = 26 },
 260         .m2 = { .min = 6, .max = 16 },
 261         .p = { .min = 4, .max = 128 },
 262         .p1 = { .min = 1, .max = 6 },
 263         .p2 = { .dot_limit = 165000,
 264                 .p2_slow = 14, .p2_fast = 7 },
 265 };
 266
 267 static const struct intel_limit intel_limits_i9xx_sdvo = {
 268         .dot = { .min = 20000, .max = 400000 },
 269         .vco = { .min = 1400000, .max = 2800000 },
 270         .n = { .min = 1, .max = 6 },
 271         .m = { .min = 70, .max = 120 },
 272         .m1 = { .min = 8, .max = 18 },
 273         .m2 = { .min = 3, .max = 7 },
 274         .p = { .min = 5, .max = 80 },
 275         .p1 = { .min = 1, .max = 8 },
 276         .p2 = { .dot_limit = 200000,
 277                 .p2_slow = 10, .p2_fast = 5 },
 278 };
 279
 280 static const struct intel_limit intel_limits_i9xx_lvds = {
 281         .dot = { .min = 20000, .max = 400000 },
 282         .vco = { .min = 1400000, .max = 2800000 },
 283         .n = { .min = 1, .max = 6 },
 284         .m = { .min = 70, .max = 120 },
 285         .m1 = { .min = 8, .max = 18 },
 286         .m2 = { .min = 3, .max = 7 },
 287         .p = { .min = 7, .max = 98 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 112000,
 290                 .p2_slow = 14, .p2_fast = 7 },
 291 };
 292
 293
 294 static const struct intel_limit intel_limits_g4x_sdvo = {
 295         .dot = { .min = 25000, .max = 270000 },
 296         .vco = { .min = 1750000, .max = 3500000},
 297         .n = { .min = 1, .max = 4 },
 298         .m = { .min = 104, .max = 138 },
 299         .m1 = { .min = 17, .max = 23 },
 300         .m2 = { .min = 5, .max = 11 },
 301         .p = { .min = 10, .max = 30 },
 302         .p1 = { .min = 1, .max = 3},
 303         .p2 = { .dot_limit = 270000,
 304                 .p2_slow = 10,
 305                 .p2_fast = 10
 306         },
 307 };
 308
 309 static const struct intel_limit intel_limits_g4x_hdmi = {
 310         .dot = { .min = 22000, .max = 400000 },
 311         .vco = { .min = 1750000, .max = 3500000},
 312         .n = { .min = 1, .max = 4 },
 313         .m = { .min = 104, .max = 138 },
 314         .m1 = { .min = 16, .max = 23 },
 315         .m2 = { .min = 5, .max = 11 },
 316         .p = { .min = 5, .max = 80 },
 317         .p1 = { .min = 1, .max = 8},
 318         .p2 = { .dot_limit = 165000,
 319                 .p2_slow = 10, .p2_fast = 5 },
 320 };
 321
 322 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 323         .dot = { .min = 20000, .max = 115000 },
 324         .vco = { .min = 1750000, .max = 3500000 },
 325         .n = { .min = 1, .max = 3 },
 326         .m = { .min = 104, .max = 138 },
 327         .m1 = { .min = 17, .max = 23 },
 328         .m2 = { .min = 5, .max = 11 },
 329         .p = { .min = 28, .max = 112 },
 330         .p1 = { .min = 2, .max = 8 },
 331         .p2 = { .dot_limit = 0,
 332                 .p2_slow = 14, .p2_fast = 14
 333         },
 334 };
 335
 336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 337         .dot = { .min = 80000, .max = 224000 },
 338         .vco = { .min = 1750000, .max = 3500000 },
 339         .n = { .min = 1, .max = 3 },
 340         .m = { .min = 104, .max = 138 },
 341         .m1 = { .min = 17, .max = 23 },
 342         .m2 = { .min = 5, .max = 11 },
 343         .p = { .min = 14, .max = 42 },
 344         .p1 = { .min = 2, .max = 6 },
 345         .p2 = { .dot_limit = 0,
 346                 .p2_slow = 7, .p2_fast = 7
 347         },
 348 };
 349
 350 static const struct intel_limit intel_limits_pineview_sdvo = {
 351         .dot = { .min = 20000, .max = 400000},
 352         .vco = { .min = 1700000, .max = 3500000 },
 353         /* Pineview's Ncounter is a ring counter */
 354         .n = { .min = 3, .max = 6 },
 355         .m = { .min = 2, .max = 256 },
 356         /* Pineview only has one combined m divider, which we treat as m2. */
 357         .m1 = { .min = 0, .max = 0 },
 358         .m2 = { .min = 0, .max = 254 },
 359         .p = { .min = 5, .max = 80 },
 360         .p1 = { .min = 1, .max = 8 },
 361         .p2 = { .dot_limit = 200000,
 362                 .p2_slow = 10, .p2_fast = 5 },
 363 };
 364
 365 static const struct intel_limit intel_limits_pineview_lvds = {
 366         .dot = { .min = 20000, .max = 400000 },
 367         .vco = { .min = 1700000, .max = 3500000 },
 368         .n = { .min = 3, .max = 6 },
 369         .m = { .min = 2, .max = 256 },
 370         .m1 = { .min = 0, .max = 0 },
 371         .m2 = { .min = 0, .max = 254 },
 372         .p = { .min = 7, .max = 112 },
 373         .p1 = { .min = 1, .max = 8 },
 374         .p2 = { .dot_limit = 112000,
 375                 .p2_slow = 14, .p2_fast = 14 },
 376 };
 377
 378 /* Ironlake / Sandybridge
 379  *
 380  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 381  * the range value for them is (actual_value - 2).
 382  */
 383 static const struct intel_limit intel_limits_ironlake_dac = {
 384         .dot = { .min = 25000, .max = 350000 },
 385         .vco = { .min = 1760000, .max = 3510000 },
 386         .n = { .min = 1, .max = 5 },
 387         .m = { .min = 79, .max = 127 },
 388         .m1 = { .min = 12, .max = 22 },
 389         .m2 = { .min = 5, .max = 9 },
 390         .p = { .min = 5, .max = 80 },
 391         .p1 = { .min = 1, .max = 8 },
 392         .p2 = { .dot_limit = 225000,
 393                 .p2_slow = 10, .p2_fast = 5 },
 394 };
 395
 396 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 397         .dot = { .min = 25000, .max = 350000 },
 398         .vco = { .min = 1760000, .max = 3510000 },
 399         .n = { .min = 1, .max = 3 },
 400         .m = { .min = 79, .max = 118 },
 401         .m1 = { .min = 12, .max = 22 },
 402         .m2 = { .min = 5, .max = 9 },
 403         .p = { .min = 28, .max = 112 },
 404         .p1 = { .min = 2, .max = 8 },
 405         .p2 = { .dot_limit = 225000,
 406                 .p2_slow = 14, .p2_fast = 14 },
 407 };
 408
 409 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 410         .dot = { .min = 25000, .max = 350000 },
 411         .vco = { .min = 1760000, .max = 3510000 },
 412         .n = { .min = 1, .max = 3 },
 413         .m = { .min = 79, .max = 127 },
 414         .m1 = { .min = 12, .max = 22 },
 415         .m2 = { .min = 5, .max = 9 },
 416         .p = { .min = 14, .max = 56 },
 417         .p1 = { .min = 2, .max = 8 },
 418         .p2 = { .dot_limit = 225000,
 419                 .p2_slow = 7, .p2_fast = 7 },
 420 };
 421
 422 /* LVDS 100mhz refclk limits. */
 423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 424         .dot = { .min = 25000, .max = 350000 },
 425         .vco = { .min = 1760000, .max = 3510000 },
 426         .n = { .min = 1, .max = 2 },
 427         .m = { .min = 79, .max = 126 },
 428         .m1 = { .min = 12, .max = 22 },
 429         .m2 = { .min = 5, .max = 9 },
 430         .p = { .min = 28, .max = 112 },
 431         .p1 = { .min = 2, .max = 8 },
 432         .p2 = { .dot_limit = 225000,
 433                 .p2_slow = 14, .p2_fast = 14 },
 434 };
 435
 436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 437         .dot = { .min = 25000, .max = 350000 },
 438         .vco = { .min = 1760000, .max = 3510000 },
 439         .n = { .min = 1, .max = 3 },
 440         .m = { .min = 79, .max = 126 },
 441         .m1 = { .min = 12, .max = 22 },
 442         .m2 = { .min = 5, .max = 9 },
 443         .p = { .min = 14, .max = 42 },
 444         .p1 = { .min = 2, .max = 6 },
 445         .p2 = { .dot_limit = 225000,
 446                 .p2_slow = 7, .p2_fast = 7 },
 447 };
 448
 449 static const struct intel_limit intel_limits_vlv = {
 450          /*
 451           * These are the data rate limits (measured in fast clocks)
 452           * since those are the strictest limits we have. The fast
 453           * clock and actual rate limits are more relaxed, so checking
 454           * them would make no difference.
 455           */
 456         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 457         .vco = { .min = 4000000, .max = 6000000 },
 458         .n = { .min = 1, .max = 7 },
 459         .m1 = { .min = 2, .max = 3 },
 460         .m2 = { .min = 11, .max = 156 },
 461         .p1 = { .min = 2, .max = 3 },
 462         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 463 };
 464
 465 static const struct intel_limit intel_limits_chv = {
 466         /*
 467          * These are the data rate limits (measured in fast clocks)
 468          * since those are the strictest limits we have.  The fast
 469          * clock and actual rate limits are more relaxed, so checking
 470          * them would make no difference.
 471          */
 472         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 473         .vco = { .min = 4800000, .max = 6480000 },
 474         .n = { .min = 1, .max = 1 },
 475         .m1 = { .min = 2, .max = 2 },
 476         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 477         .p1 = { .min = 2, .max = 4 },
 478         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 479 };
 480
 481 static const struct intel_limit intel_limits_bxt = {
 482         /* FIXME: find real dot limits */
 483         .dot = { .min = 0, .max = INT_MAX },
 484         .vco = { .min = 4800000, .max = 6700000 },
 485         .n = { .min = 1, .max = 1 },
 486         .m1 = { .min = 2, .max = 2 },
 487         /* FIXME: find real m2 limits */
 488         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 489         .p1 = { .min = 2, .max = 4 },
 490         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 491 };
 492
 493 static bool
 494 needs_modeset(struct drm_crtc_state *state)
 495 {
 496         return drm_atomic_crtc_needs_modeset(state);
 497 }
 498
 499 /*
 500  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 501  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 502  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 503  * The helpers' return value is the rate of the clock that is fed to the
 504  * display engine's pipe which can be the above fast dot clock rate or a
 505  * divided-down version of it.
 506  */
 507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 509 {
 510         clock->m = clock->m2 + 2;
 511         clock->p = clock->p1 * clock->p2;
 512         if (WARN_ON(clock->n == 0 || clock->p == 0))
 513                 return 0;
 514         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 515         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 516
 517         return clock->dot;
 518 }
 519
 520 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 521 {
 522         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 523 }
 524
 525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 526 {
 527         clock->m = i9xx_dpll_compute_m(clock);
 528         clock->p = clock->p1 * clock->p2;
 529         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 530                 return 0;
 531         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot;
 535 }
 536
 537 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 538 {
 539         clock->m = clock->m1 * clock->m2;
 540         clock->p = clock->p1 * clock->p2;
 541         if (WARN_ON(clock->n == 0 || clock->p == 0))
 542                 return 0;
 543         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 544         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 545
 546         return clock->dot / 5;
 547 }
 548
 549 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 550 {
 551         clock->m = clock->m1 * clock->m2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return 0;
 555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 556                         clock->n << 22);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558
 559         return clock->dot / 5;
 560 }
 561
 562 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 563 /**
 564  * Returns whether the given set of divisors are valid for a given refclk with
 565  * the given connectors.
 566  */
 567
 568 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 569                                const struct intel_limit *limit,
 570                                const struct dpll *clock)
 571 {
 572         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 573                 INTELPllInvalid("n out of range\n");
 574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 575                 INTELPllInvalid("p1 out of range\n");
 576         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 577                 INTELPllInvalid("m2 out of range\n");
 578         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 579                 INTELPllInvalid("m1 out of range\n");
 580
 581         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 582             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 583                 if (clock->m1 <= clock->m2)
 584                         INTELPllInvalid("m1 <= m2\n");
 585
 586         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 587             !IS_GEN9_LP(dev_priv)) {
 588                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 589                         INTELPllInvalid("p out of range\n");
 590                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 591                         INTELPllInvalid("m out of range\n");
 592         }
 593
 594         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 595                 INTELPllInvalid("vco out of range\n");
 596         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 597          * connector, etc., rather than just a single range.
 598          */
 599         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 600                 INTELPllInvalid("dot out of range\n");
 601
 602         return true;
 603 }
 604
 605 static int
 606 i9xx_select_p2_div(const struct intel_limit *limit,
 607                    const struct intel_crtc_state *crtc_state,
 608                    int target)
 609 {
 610         struct drm_device *dev = crtc_state->base.crtc->dev;
 611
 612         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 613                 /*
 614                  * For LVDS just rely on its current settings for dual-channel.
 615                  * We haven't figured out how to reliably set up different
 616                  * single/dual channel state, if we even can.
 617                  */
 618                 if (intel_is_dual_link_lvds(dev))
 619                         return limit->p2.p2_fast;
 620                 else
 621                         return limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         return limit->p2.p2_slow;
 625                 else
 626                         return limit->p2.p2_fast;
 627         }
 628 }
 629
 630 /*
 631  * Returns a set of divisors for the desired target clock with the given
 632  * refclk, or FALSE.  The returned values represent the clock equation:
 633  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 634  *
 635  * Target and reference clocks are specified in kHz.
 636  *
 637  * If match_clock is provided, then best_clock P divider must match the P
 638  * divider from @match_clock used for LVDS downclocking.
 639  */
 640 static bool
 641 i9xx_find_best_dpll(const struct intel_limit *limit,
 642                     struct intel_crtc_state *crtc_state,
 643                     int target, int refclk, struct dpll *match_clock,
 644                     struct dpll *best_clock)
 645 {
 646         struct drm_device *dev = crtc_state->base.crtc->dev;
 647         struct dpll clock;
 648         int err = target;
 649
 650         memset(best_clock, 0, sizeof(*best_clock));
 651
 652         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 653
 654         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 655              clock.m1++) {
 656                 for (clock.m2 = limit->m2.min;
 657                      clock.m2 <= limit->m2.max; clock.m2++) {
 658                         if (clock.m2 >= clock.m1)
 659                                 break;
 660                         for (clock.n = limit->n.min;
 661                              clock.n <= limit->n.max; clock.n++) {
 662                                 for (clock.p1 = limit->p1.min;
 663                                         clock.p1 <= limit->p1.max; clock.p1++) {
 664                                         int this_err;
 665
 666                                         i9xx_calc_dpll_params(refclk, &clock);
 667                                         if (!intel_PLL_is_valid(to_i915(dev),
 668                                                                 limit,
 669                                                                 &clock))
 670                                                 continue;
 671                                         if (match_clock &&
 672                                             clock.p != match_clock->p)
 673                                                 continue;
 674
 675                                         this_err = abs(clock.dot - target);
 676                                         if (this_err < err) {
 677                                                 *best_clock = clock;
 678                                                 err = this_err;
 679                                         }
 680                                 }
 681                         }
 682                 }
 683         }
 684
 685         return (err != target);
 686 }
 687
 688 /*
 689  * Returns a set of divisors for the desired target clock with the given
 690  * refclk, or FALSE.  The returned values represent the clock equation:
 691  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 692  *
 693  * Target and reference clocks are specified in kHz.
 694  *
 695  * If match_clock is provided, then best_clock P divider must match the P
 696  * divider from @match_clock used for LVDS downclocking.
 697  */
 698 static bool
 699 pnv_find_best_dpll(const struct intel_limit *limit,
 700                    struct intel_crtc_state *crtc_state,
 701                    int target, int refclk, struct dpll *match_clock,
 702                    struct dpll *best_clock)
 703 {
 704         struct drm_device *dev = crtc_state->base.crtc->dev;
 705         struct dpll clock;
 706         int err = target;
 707
 708         memset(best_clock, 0, sizeof(*best_clock));
 709
 710         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 711
 712         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 713              clock.m1++) {
 714                 for (clock.m2 = limit->m2.min;
 715                      clock.m2 <= limit->m2.max; clock.m2++) {
 716                         for (clock.n = limit->n.min;
 717                              clock.n <= limit->n.max; clock.n++) {
 718                                 for (clock.p1 = limit->p1.min;
 719                                         clock.p1 <= limit->p1.max; clock.p1++) {
 720                                         int this_err;
 721
 722                                         pnv_calc_dpll_params(refclk, &clock);
 723                                         if (!intel_PLL_is_valid(to_i915(dev),
 724                                                                 limit,
 725                                                                 &clock))
 726                                                 continue;
 727                                         if (match_clock &&
 728                                             clock.p != match_clock->p)
 729                                                 continue;
 730
 731                                         this_err = abs(clock.dot - target);
 732                                         if (this_err < err) {
 733                                                 *best_clock = clock;
 734                                                 err = this_err;
 735                                         }
 736                                 }
 737                         }
 738                 }
 739         }
 740
 741         return (err != target);
 742 }
 743
 744 /*
 745  * Returns a set of divisors for the desired target clock with the given
 746  * refclk, or FALSE.  The returned values represent the clock equation:
 747  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 748  *
 749  * Target and reference clocks are specified in kHz.
 750  *
 751  * If match_clock is provided, then best_clock P divider must match the P
 752  * divider from @match_clock used for LVDS downclocking.
 753  */
 754 static bool
 755 g4x_find_best_dpll(const struct intel_limit *limit,
 756                    struct intel_crtc_state *crtc_state,
 757                    int target, int refclk, struct dpll *match_clock,
 758                    struct dpll *best_clock)
 759 {
 760         struct drm_device *dev = crtc_state->base.crtc->dev;
 761         struct dpll clock;
 762         int max_n;
 763         bool found = false;
 764         /* approximately equals target * 0.00585 */
 765         int err_most = (target >> 8) + (target >> 9);
 766
 767         memset(best_clock, 0, sizeof(*best_clock));
 768
 769         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 770
 771         max_n = limit->n.max;
 772         /* based on hardware requirement, prefer smaller n to precision */
 773         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 774                 /* based on hardware requirement, prefere larger m1,m2 */
 775                 for (clock.m1 = limit->m1.max;
 776                      clock.m1 >= limit->m1.min; clock.m1--) {
 777                         for (clock.m2 = limit->m2.max;
 778                              clock.m2 >= limit->m2.min; clock.m2--) {
 779                                 for (clock.p1 = limit->p1.max;
 780                                      clock.p1 >= limit->p1.min; clock.p1--) {
 781                                         int this_err;
 782
 783                                         i9xx_calc_dpll_params(refclk, &clock);
 784                                         if (!intel_PLL_is_valid(to_i915(dev),
 785                                                                 limit,
 786                                                                 &clock))
 787                                                 continue;
 788
 789                                         this_err = abs(clock.dot - target);
 790                                         if (this_err < err_most) {
 791                                                 *best_clock = clock;
 792                                                 err_most = this_err;
 793                                                 max_n = clock.n;
 794                                                 found = true;
 795                                         }
 796                                 }
 797                         }
 798                 }
 799         }
 800         return found;
 801 }
 802
 803 /*
 804  * Check if the calculated PLL configuration is more optimal compared to the
 805  * best configuration and error found so far. Return the calculated error.
 806  */
 807 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 808                                const struct dpll *calculated_clock,
 809                                const struct dpll *best_clock,
 810                                unsigned int best_error_ppm,
 811                                unsigned int *error_ppm)
 812 {
 813         /*
 814          * For CHV ignore the error and consider only the P value.
 815          * Prefer a bigger P value based on HW requirements.
 816          */
 817         if (IS_CHERRYVIEW(to_i915(dev))) {
 818                 *error_ppm = 0;
 819
 820                 return calculated_clock->p > best_clock->p;
 821         }
 822
 823         if (WARN_ON_ONCE(!target_freq))
 824                 return false;
 825
 826         *error_ppm = div_u64(1000000ULL *
 827                                 abs(target_freq - calculated_clock->dot),
 828                              target_freq);
 829         /*
 830          * Prefer a better P value over a better (smaller) error if the error
 831          * is small. Ensure this preference for future configurations too by
 832          * setting the error to 0.
 833          */
 834         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 835                 *error_ppm = 0;
 836
 837                 return true;
 838         }
 839
 840         return *error_ppm + 10 < best_error_ppm;
 841 }
 842
 843 /*
 844  * Returns a set of divisors for the desired target clock with the given
 845  * refclk, or FALSE.  The returned values represent the clock equation:
 846  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 847  */
 848 static bool
 849 vlv_find_best_dpll(const struct intel_limit *limit,
 850                    struct intel_crtc_state *crtc_state,
 851                    int target, int refclk, struct dpll *match_clock,
 852                    struct dpll *best_clock)
 853 {
 854         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 855         struct drm_device *dev = crtc->base.dev;
 856         struct dpll clock;
 857         unsigned int bestppm = 1000000;
 858         /* min update 19.2 MHz */
 859         int max_n = min(limit->n.max, refclk / 19200);
 860         bool found = false;
 861
 862         target *= 5; /* fast clock */
 863
 864         memset(best_clock, 0, sizeof(*best_clock));
 865
 866         /* based on hardware requirement, prefer smaller n to precision */
 867         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 868                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 869                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 870                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 871                                 clock.p = clock.p1 * clock.p2;
 872                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 873                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 874                                         unsigned int ppm;
 875
 876                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 877                                                                      refclk * clock.m1);
 878
 879                                         vlv_calc_dpll_params(refclk, &clock);
 880
 881                                         if (!intel_PLL_is_valid(to_i915(dev),
 882                                                                 limit,
 883                                                                 &clock))
 884                                                 continue;
 885
 886                                         if (!vlv_PLL_is_optimal(dev, target,
 887                                                                 &clock,
 888                                                                 best_clock,
 889                                                                 bestppm, &ppm))
 890                                                 continue;
 891
 892                                         *best_clock = clock;
 893                                         bestppm = ppm;
 894                                         found = true;
 895                                 }
 896                         }
 897                 }
 898         }
 899
 900         return found;
 901 }
 902
 903 /*
 904  * Returns a set of divisors for the desired target clock with the given
 905  * refclk, or FALSE.  The returned values represent the clock equation:
 906  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 907  */
 908 static bool
 909 chv_find_best_dpll(const struct intel_limit *limit,
 910                    struct intel_crtc_state *crtc_state,
 911                    int target, int refclk, struct dpll *match_clock,
 912                    struct dpll *best_clock)
 913 {
 914         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 915         struct drm_device *dev = crtc->base.dev;
 916         unsigned int best_error_ppm;
 917         struct dpll clock;
 918         uint64_t m2;
 919         int found = false;
 920
 921         memset(best_clock, 0, sizeof(*best_clock));
 922         best_error_ppm = 1000000;
 923
 924         /*
 925          * Based on hardware doc, the n always set to 1, and m1 always
 926          * set to 2.  If requires to support 200Mhz refclk, we need to
 927          * revisit this because n may not 1 anymore.
 928          */
 929         clock.n = 1, clock.m1 = 2;
 930         target *= 5;    /* fast clock */
 931
 932         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 933                 for (clock.p2 = limit->p2.p2_fast;
 934                                 clock.p2 >= limit->p2.p2_slow;
 935                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 936                         unsigned int error_ppm;
 937
 938                         clock.p = clock.p1 * clock.p2;
 939
 940                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 941                                         clock.n) << 22, refclk * clock.m1);
 942
 943                         if (m2 > INT_MAX/clock.m1)
 944                                 continue;
 945
 946                         clock.m2 = m2;
 947
 948                         chv_calc_dpll_params(refclk, &clock);
 949
 950                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 951                                 continue;
 952
 953                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 954                                                 best_error_ppm, &error_ppm))
 955                                 continue;
 956
 957                         *best_clock = clock;
 958                         best_error_ppm = error_ppm;
 959                         found = true;
 960                 }
 961         }
 962
 963         return found;
 964 }
 965
 966 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 967                         struct dpll *best_clock)
 968 {
 969         int refclk = 100000;
 970         const struct intel_limit *limit = &intel_limits_bxt;
 971
 972         return chv_find_best_dpll(limit, crtc_state,
 973                                   target_clock, refclk, NULL, best_clock);
 974 }
 975
 976 bool intel_crtc_active(struct intel_crtc *crtc)
 977 {
 978         /* Be paranoid as we can arrive here with only partial
 979          * state retrieved from the hardware during setup.
 980          *
 981          * We can ditch the adjusted_mode.crtc_clock check as soon
 982          * as Haswell has gained clock readout/fastboot support.
 983          *
 984          * We can ditch the crtc->primary->fb check as soon as we can
 985          * properly reconstruct framebuffers.
 986          *
 987          * FIXME: The intel_crtc->active here should be switched to
 988          * crtc->state->active once we have proper CRTC states wired up
 989          * for atomic.
 990          */
 991         return crtc->active && crtc->base.primary->state->fb &&
 992                 crtc->config->base.adjusted_mode.crtc_clock;
 993 }
 994
 995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 996                                              enum pipe pipe)
 997 {
 998         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 999
1000         return crtc->config->cpu_transcoder;
1001 }
1002
1003 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1004 {
1005         i915_reg_t reg = PIPEDSL(pipe);
1006         u32 line1, line2;
1007         u32 line_mask;
1008
1009         if (IS_GEN2(dev_priv))
1010                 line_mask = DSL_LINEMASK_GEN2;
1011         else
1012                 line_mask = DSL_LINEMASK_GEN3;
1013
1014         line1 = I915_READ(reg) & line_mask;
1015         msleep(5);
1016         line2 = I915_READ(reg) & line_mask;
1017
1018         return line1 == line2;
1019 }
1020
1021 /*
1022  * intel_wait_for_pipe_off - wait for pipe to turn off
1023  * @crtc: crtc whose pipe to wait for
1024  *
1025  * After disabling a pipe, we can't wait for vblank in the usual way,
1026  * spinning on the vblank interrupt status bit, since we won't actually
1027  * see an interrupt when the pipe is disabled.
1028  *
1029  * On Gen4 and above:
1030  *   wait for the pipe register state bit to turn off
1031  *
1032  * Otherwise:
1033  *   wait for the display line value to settle (it usually
1034  *   ends up stopping at the start of the next frame).
1035  *
1036  */
1037 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1038 {
1039         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1041         enum pipe pipe = crtc->pipe;
1042
1043         if (INTEL_GEN(dev_priv) >= 4) {
1044                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1045
1046                 /* Wait for the Pipe State to go off */
1047                 if (intel_wait_for_register(dev_priv,
1048                                             reg, I965_PIPECONF_ACTIVE, 0,
1049                                             100))
1050                         WARN(1, "pipe_off wait timed out\n");
1051         } else {
1052                 /* Wait for the display line to settle */
1053                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1054                         WARN(1, "pipe_off wait timed out\n");
1055         }
1056 }
1057
1058 /* Only for pre-ILK configs */
1059 void assert_pll(struct drm_i915_private *dev_priv,
1060                 enum pipe pipe, bool state)
1061 {
1062         u32 val;
1063         bool cur_state;
1064
1065         val = I915_READ(DPLL(pipe));
1066         cur_state = !!(val & DPLL_VCO_ENABLE);
1067         I915_STATE_WARN(cur_state != state,
1068              "PLL state assertion failure (expected %s, current %s)\n",
1069                         onoff(state), onoff(cur_state));
1070 }
1071
1072 /* XXX: the dsi pll is shared between MIPI DSI ports */
1073 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1074 {
1075         u32 val;
1076         bool cur_state;
1077
1078         mutex_lock(&dev_priv->sb_lock);
1079         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1080         mutex_unlock(&dev_priv->sb_lock);
1081
1082         cur_state = val & DSI_PLL_VCO_EN;
1083         I915_STATE_WARN(cur_state != state,
1084              "DSI PLL state assertion failure (expected %s, current %s)\n",
1085                         onoff(state), onoff(cur_state));
1086 }
1087
1088 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1089                           enum pipe pipe, bool state)
1090 {
1091         bool cur_state;
1092         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093                                                                       pipe);
1094
1095         if (HAS_DDI(dev_priv)) {
1096                 /* DDI does not have a specific FDI_TX register */
1097                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1098                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1099         } else {
1100                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1101                 cur_state = !!(val & FDI_TX_ENABLE);
1102         }
1103         I915_STATE_WARN(cur_state != state,
1104              "FDI TX state assertion failure (expected %s, current %s)\n",
1105                         onoff(state), onoff(cur_state));
1106 }
1107 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1108 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1109
1110 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1111                           enum pipe pipe, bool state)
1112 {
1113         u32 val;
1114         bool cur_state;
1115
1116         val = I915_READ(FDI_RX_CTL(pipe));
1117         cur_state = !!(val & FDI_RX_ENABLE);
1118         I915_STATE_WARN(cur_state != state,
1119              "FDI RX state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126                                       enum pipe pipe)
1127 {
1128         u32 val;
1129
1130         /* ILK FDI PLL is always enabled */
1131         if (IS_GEN5(dev_priv))
1132                 return;
1133
1134         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135         if (HAS_DDI(dev_priv))
1136                 return;
1137
1138         val = I915_READ(FDI_TX_CTL(pipe));
1139         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1140 }
1141
1142 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1143                        enum pipe pipe, bool state)
1144 {
1145         u32 val;
1146         bool cur_state;
1147
1148         val = I915_READ(FDI_RX_CTL(pipe));
1149         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1150         I915_STATE_WARN(cur_state != state,
1151              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1152                         onoff(state), onoff(cur_state));
1153 }
1154
1155 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157         i915_reg_t pp_reg;
1158         u32 val;
1159         enum pipe panel_pipe = PIPE_A;
1160         bool locked = true;
1161
1162         if (WARN_ON(HAS_DDI(dev_priv)))
1163                 return;
1164
1165         if (HAS_PCH_SPLIT(dev_priv)) {
1166                 u32 port_sel;
1167
1168                 pp_reg = PP_CONTROL(0);
1169                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1170
1171                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1172                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1173                         panel_pipe = PIPE_B;
1174                 /* XXX: else fix for eDP */
1175         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1176                 /* presumably write lock depends on pipe, not port select */
1177                 pp_reg = PP_CONTROL(pipe);
1178                 panel_pipe = pipe;
1179         } else {
1180                 pp_reg = PP_CONTROL(0);
1181                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1182                         panel_pipe = PIPE_B;
1183         }
1184
1185         val = I915_READ(pp_reg);
1186         if (!(val & PANEL_POWER_ON) ||
1187             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1188                 locked = false;
1189
1190         I915_STATE_WARN(panel_pipe == pipe && locked,
1191              "panel assertion failure, pipe %c regs locked\n",
1192              pipe_name(pipe));
1193 }
1194
1195 static void assert_cursor(struct drm_i915_private *dev_priv,
1196                           enum pipe pipe, bool state)
1197 {
1198         bool cur_state;
1199
1200         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1201                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1202         else
1203                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1204
1205         I915_STATE_WARN(cur_state != state,
1206              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1207                         pipe_name(pipe), onoff(state), onoff(cur_state));
1208 }
1209 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1210 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1211
1212 void assert_pipe(struct drm_i915_private *dev_priv,
1213                  enum pipe pipe, bool state)
1214 {
1215         bool cur_state;
1216         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1217                                                                       pipe);
1218         enum intel_display_power_domain power_domain;
1219
1220         /* we keep both pipes enabled on 830 */
1221         if (IS_I830(dev_priv))
1222                 state = true;
1223
1224         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1225         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1226                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1227                 cur_state = !!(val & PIPECONF_ENABLE);
1228
1229                 intel_display_power_put(dev_priv, power_domain);
1230         } else {
1231                 cur_state = false;
1232         }
1233
1234         I915_STATE_WARN(cur_state != state,
1235              "pipe %c assertion failure (expected %s, current %s)\n",
1236                         pipe_name(pipe), onoff(state), onoff(cur_state));
1237 }
1238
1239 static void assert_plane(struct drm_i915_private *dev_priv,
1240                          enum plane plane, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(DSPCNTR(plane));
1246         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "plane %c assertion failure (expected %s, current %s)\n",
1249                         plane_name(plane), onoff(state), onoff(cur_state));
1250 }
1251
1252 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1253 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1254
1255 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1256                                    enum pipe pipe)
1257 {
1258         int i;
1259
1260         /* Primary planes are fixed to pipes on gen4+ */
1261         if (INTEL_GEN(dev_priv) >= 4) {
1262                 u32 val = I915_READ(DSPCNTR(pipe));
1263                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1264                      "plane %c assertion failure, should be disabled but not\n",
1265                      plane_name(pipe));
1266                 return;
1267         }
1268
1269         /* Need to check both planes against the pipe */
1270         for_each_pipe(dev_priv, i) {
1271                 u32 val = I915_READ(DSPCNTR(i));
1272                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1273                         DISPPLANE_SEL_PIPE_SHIFT;
1274                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1275                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1276                      plane_name(i), pipe_name(pipe));
1277         }
1278 }
1279
1280 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1281                                     enum pipe pipe)
1282 {
1283         int sprite;
1284
1285         if (INTEL_GEN(dev_priv) >= 9) {
1286                 for_each_sprite(dev_priv, pipe, sprite) {
1287                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1288                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1289                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1290                              sprite, pipe_name(pipe));
1291                 }
1292         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1293                 for_each_sprite(dev_priv, pipe, sprite) {
1294                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1295                         I915_STATE_WARN(val & SP_ENABLE,
1296                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297                              sprite_name(pipe, sprite), pipe_name(pipe));
1298                 }
1299         } else if (INTEL_GEN(dev_priv) >= 7) {
1300                 u32 val = I915_READ(SPRCTL(pipe));
1301                 I915_STATE_WARN(val & SPRITE_ENABLE,
1302                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303                      plane_name(pipe), pipe_name(pipe));
1304         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1305                 u32 val = I915_READ(DVSCNTR(pipe));
1306                 I915_STATE_WARN(val & DVS_ENABLE,
1307                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1308                      plane_name(pipe), pipe_name(pipe));
1309         }
1310 }
1311
1312 static void assert_vblank_disabled(struct drm_crtc *crtc)
1313 {
1314         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1315                 drm_crtc_vblank_put(crtc);
1316 }
1317
1318 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1319                                     enum pipe pipe)
1320 {
1321         u32 val;
1322         bool enabled;
1323
1324         val = I915_READ(PCH_TRANSCONF(pipe));
1325         enabled = !!(val & TRANS_ENABLE);
1326         I915_STATE_WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv)) {
1338                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1339                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1340                         return false;
1341         } else if (IS_CHERRYVIEW(dev_priv)) {
1342                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1343                         return false;
1344         } else {
1345                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1346                         return false;
1347         }
1348         return true;
1349 }
1350
1351 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1352                               enum pipe pipe, u32 val)
1353 {
1354         if ((val & SDVO_ENABLE) == 0)
1355                 return false;
1356
1357         if (HAS_PCH_CPT(dev_priv)) {
1358                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1359                         return false;
1360         } else if (IS_CHERRYVIEW(dev_priv)) {
1361                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1362                         return false;
1363         } else {
1364                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1365                         return false;
1366         }
1367         return true;
1368 }
1369
1370 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1371                               enum pipe pipe, u32 val)
1372 {
1373         if ((val & LVDS_PORT_EN) == 0)
1374                 return false;
1375
1376         if (HAS_PCH_CPT(dev_priv)) {
1377                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1378                         return false;
1379         } else {
1380                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1381                         return false;
1382         }
1383         return true;
1384 }
1385
1386 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1387                               enum pipe pipe, u32 val)
1388 {
1389         if ((val & ADPA_DAC_ENABLE) == 0)
1390                 return false;
1391         if (HAS_PCH_CPT(dev_priv)) {
1392                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1393                         return false;
1394         } else {
1395                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1396                         return false;
1397         }
1398         return true;
1399 }
1400
1401 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1402                                    enum pipe pipe, i915_reg_t reg,
1403                                    u32 port_sel)
1404 {
1405         u32 val = I915_READ(reg);
1406         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1407              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1408              i915_mmio_reg_offset(reg), pipe_name(pipe));
1409
1410         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1411              && (val & DP_PIPEB_SELECT),
1412              "IBX PCH dp port still using transcoder B\n");
1413 }
1414
1415 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1416                                      enum pipe pipe, i915_reg_t reg)
1417 {
1418         u32 val = I915_READ(reg);
1419         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1420              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1421              i915_mmio_reg_offset(reg), pipe_name(pipe));
1422
1423         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1424              && (val & SDVO_PIPE_B_SELECT),
1425              "IBX PCH hdmi port still using transcoder B\n");
1426 }
1427
1428 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1429                                       enum pipe pipe)
1430 {
1431         u32 val;
1432
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1434         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1435         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1436
1437         val = I915_READ(PCH_ADPA);
1438         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439              "PCH VGA enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         val = I915_READ(PCH_LVDS);
1443         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1444              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1445              pipe_name(pipe));
1446
1447         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1448         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1449         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1450 }
1451
1452 static void _vlv_enable_pll(struct intel_crtc *crtc,
1453                             const struct intel_crtc_state *pipe_config)
1454 {
1455         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1456         enum pipe pipe = crtc->pipe;
1457
1458         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1459         POSTING_READ(DPLL(pipe));
1460         udelay(150);
1461
1462         if (intel_wait_for_register(dev_priv,
1463                                     DPLL(pipe),
1464                                     DPLL_LOCK_VLV,
1465                                     DPLL_LOCK_VLV,
1466                                     1))
1467                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1468 }
1469
1470 static void vlv_enable_pll(struct intel_crtc *crtc,
1471                            const struct intel_crtc_state *pipe_config)
1472 {
1473         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1474         enum pipe pipe = crtc->pipe;
1475
1476         assert_pipe_disabled(dev_priv, pipe);
1477
1478         /* PLL is protected by panel, make sure we can write it */
1479         assert_panel_unlocked(dev_priv, pipe);
1480
1481         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1482                 _vlv_enable_pll(crtc, pipe_config);
1483
1484         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1485         POSTING_READ(DPLL_MD(pipe));
1486 }
1487
1488
1489 static void _chv_enable_pll(struct intel_crtc *crtc,
1490                             const struct intel_crtc_state *pipe_config)
1491 {
1492         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1493         enum pipe pipe = crtc->pipe;
1494         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1495         u32 tmp;
1496
1497         mutex_lock(&dev_priv->sb_lock);
1498
1499         /* Enable back the 10bit clock to display controller */
1500         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1501         tmp |= DPIO_DCLKP_EN;
1502         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1503
1504         mutex_unlock(&dev_priv->sb_lock);
1505
1506         /*
1507          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1508          */
1509         udelay(1);
1510
1511         /* Enable PLL */
1512         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1513
1514         /* Check PLL is locked */
1515         if (intel_wait_for_register(dev_priv,
1516                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1517                                     1))
1518                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1519 }
1520
1521 static void chv_enable_pll(struct intel_crtc *crtc,
1522                            const struct intel_crtc_state *pipe_config)
1523 {
1524         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1525         enum pipe pipe = crtc->pipe;
1526
1527         assert_pipe_disabled(dev_priv, pipe);
1528
1529         /* PLL is protected by panel, make sure we can write it */
1530         assert_panel_unlocked(dev_priv, pipe);
1531
1532         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1533                 _chv_enable_pll(crtc, pipe_config);
1534
1535         if (pipe != PIPE_A) {
1536                 /*
1537                  * WaPixelRepeatModeFixForC0:chv
1538                  *
1539                  * DPLLCMD is AWOL. Use chicken bits to propagate
1540                  * the value from DPLLBMD to either pipe B or C.
1541                  */
1542                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1543                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1544                 I915_WRITE(CBR4_VLV, 0);
1545                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1546
1547                 /*
1548                  * DPLLB VGA mode also seems to cause problems.
1549                  * We should always have it disabled.
1550                  */
1551                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1552         } else {
1553                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1554                 POSTING_READ(DPLL_MD(pipe));
1555         }
1556 }
1557
1558 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1559 {
1560         struct intel_crtc *crtc;
1561         int count = 0;
1562
1563         for_each_intel_crtc(&dev_priv->drm, crtc) {
1564                 count += crtc->base.state->active &&
1565                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1566         }
1567
1568         return count;
1569 }
1570
1571 static void i9xx_enable_pll(struct intel_crtc *crtc,
1572                             const struct intel_crtc_state *crtc_state)
1573 {
1574         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1575         i915_reg_t reg = DPLL(crtc->pipe);
1576         u32 dpll = crtc_state->dpll_hw_state.dpll;
1577         int i;
1578
1579         assert_pipe_disabled(dev_priv, crtc->pipe);
1580
1581         /* PLL is protected by panel, make sure we can write it */
1582         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1583                 assert_panel_unlocked(dev_priv, crtc->pipe);
1584
1585         /* Enable DVO 2x clock on both PLLs if necessary */
1586         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1587                 /*
1588                  * It appears to be important that we don't enable this
1589                  * for the current pipe before otherwise configuring the
1590                  * PLL. No idea how this should be handled if multiple
1591                  * DVO outputs are enabled simultaneosly.
1592                  */
1593                 dpll |= DPLL_DVO_2X_MODE;
1594                 I915_WRITE(DPLL(!crtc->pipe),
1595                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1596         }
1597
1598         /*
1599          * Apparently we need to have VGA mode enabled prior to changing
1600          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1601          * dividers, even though the register value does change.
1602          */
1603         I915_WRITE(reg, 0);
1604
1605         I915_WRITE(reg, dpll);
1606
1607         /* Wait for the clocks to stabilize. */
1608         POSTING_READ(reg);
1609         udelay(150);
1610
1611         if (INTEL_GEN(dev_priv) >= 4) {
1612                 I915_WRITE(DPLL_MD(crtc->pipe),
1613                            crtc_state->dpll_hw_state.dpll_md);
1614         } else {
1615                 /* The pixel multiplier can only be updated once the
1616                  * DPLL is enabled and the clocks are stable.
1617                  *
1618                  * So write it again.
1619                  */
1620                 I915_WRITE(reg, dpll);
1621         }
1622
1623         /* We do this three times for luck */
1624         for (i = 0; i < 3; i++) {
1625                 I915_WRITE(reg, dpll);
1626                 POSTING_READ(reg);
1627                 udelay(150); /* wait for warmup */
1628         }
1629 }
1630
1631 static void i9xx_disable_pll(struct intel_crtc *crtc)
1632 {
1633         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1634         enum pipe pipe = crtc->pipe;
1635
1636         /* Disable DVO 2x clock on both PLLs if necessary */
1637         if (IS_I830(dev_priv) &&
1638             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1639             !intel_num_dvo_pipes(dev_priv)) {
1640                 I915_WRITE(DPLL(PIPE_B),
1641                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1642                 I915_WRITE(DPLL(PIPE_A),
1643                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1644         }
1645
1646         /* Don't disable pipe or pipe PLLs if needed */
1647         if (IS_I830(dev_priv))
1648                 return;
1649
1650         /* Make sure the pipe isn't still relying on us */
1651         assert_pipe_disabled(dev_priv, pipe);
1652
1653         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1654         POSTING_READ(DPLL(pipe));
1655 }
1656
1657 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1658 {
1659         u32 val;
1660
1661         /* Make sure the pipe isn't still relying on us */
1662         assert_pipe_disabled(dev_priv, pipe);
1663
1664         val = DPLL_INTEGRATED_REF_CLK_VLV |
1665                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1666         if (pipe != PIPE_A)
1667                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1668
1669         I915_WRITE(DPLL(pipe), val);
1670         POSTING_READ(DPLL(pipe));
1671 }
1672
1673 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1674 {
1675         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1676         u32 val;
1677
1678         /* Make sure the pipe isn't still relying on us */
1679         assert_pipe_disabled(dev_priv, pipe);
1680
1681         val = DPLL_SSC_REF_CLK_CHV |
1682                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1683         if (pipe != PIPE_A)
1684                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1685
1686         I915_WRITE(DPLL(pipe), val);
1687         POSTING_READ(DPLL(pipe));
1688
1689         mutex_lock(&dev_priv->sb_lock);
1690
1691         /* Disable 10bit clock to display controller */
1692         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1693         val &= ~DPIO_DCLKP_EN;
1694         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1695
1696         mutex_unlock(&dev_priv->sb_lock);
1697 }
1698
1699 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1700                          struct intel_digital_port *dport,
1701                          unsigned int expected_mask)
1702 {
1703         u32 port_mask;
1704         i915_reg_t dpll_reg;
1705
1706         switch (dport->port) {
1707         case PORT_B:
1708                 port_mask = DPLL_PORTB_READY_MASK;
1709                 dpll_reg = DPLL(0);
1710                 break;
1711         case PORT_C:
1712                 port_mask = DPLL_PORTC_READY_MASK;
1713                 dpll_reg = DPLL(0);
1714                 expected_mask <<= 4;
1715                 break;
1716         case PORT_D:
1717                 port_mask = DPLL_PORTD_READY_MASK;
1718                 dpll_reg = DPIO_PHY_STATUS;
1719                 break;
1720         default:
1721                 BUG();
1722         }
1723
1724         if (intel_wait_for_register(dev_priv,
1725                                     dpll_reg, port_mask, expected_mask,
1726                                     1000))
1727                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1728                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1729 }
1730
1731 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1732                                            enum pipe pipe)
1733 {
1734         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1735                                                                 pipe);
1736         i915_reg_t reg;
1737         uint32_t val, pipeconf_val;
1738
1739         /* Make sure PCH DPLL is enabled */
1740         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1741
1742         /* FDI must be feeding us bits for PCH ports */
1743         assert_fdi_tx_enabled(dev_priv, pipe);
1744         assert_fdi_rx_enabled(dev_priv, pipe);
1745
1746         if (HAS_PCH_CPT(dev_priv)) {
1747                 /* Workaround: Set the timing override bit before enabling the
1748                  * pch transcoder. */
1749                 reg = TRANS_CHICKEN2(pipe);
1750                 val = I915_READ(reg);
1751                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1752                 I915_WRITE(reg, val);
1753         }
1754
1755         reg = PCH_TRANSCONF(pipe);
1756         val = I915_READ(reg);
1757         pipeconf_val = I915_READ(PIPECONF(pipe));
1758
1759         if (HAS_PCH_IBX(dev_priv)) {
1760                 /*
1761                  * Make the BPC in transcoder be consistent with
1762                  * that in pipeconf reg. For HDMI we must use 8bpc
1763                  * here for both 8bpc and 12bpc.
1764                  */
1765                 val &= ~PIPECONF_BPC_MASK;
1766                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1767                         val |= PIPECONF_8BPC;
1768                 else
1769                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1770         }
1771
1772         val &= ~TRANS_INTERLACE_MASK;
1773         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1774                 if (HAS_PCH_IBX(dev_priv) &&
1775                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1776                         val |= TRANS_LEGACY_INTERLACED_ILK;
1777                 else
1778                         val |= TRANS_INTERLACED;
1779         else
1780                 val |= TRANS_PROGRESSIVE;
1781
1782         I915_WRITE(reg, val | TRANS_ENABLE);
1783         if (intel_wait_for_register(dev_priv,
1784                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1785                                     100))
1786                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1787 }
1788
1789 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1790                                       enum transcoder cpu_transcoder)
1791 {
1792         u32 val, pipeconf_val;
1793
1794         /* FDI must be feeding us bits for PCH ports */
1795         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1796         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1797
1798         /* Workaround: set timing override bit. */
1799         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1800         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1801         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1802
1803         val = TRANS_ENABLE;
1804         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1805
1806         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1807             PIPECONF_INTERLACED_ILK)
1808                 val |= TRANS_INTERLACED;
1809         else
1810                 val |= TRANS_PROGRESSIVE;
1811
1812         I915_WRITE(LPT_TRANSCONF, val);
1813         if (intel_wait_for_register(dev_priv,
1814                                     LPT_TRANSCONF,
1815                                     TRANS_STATE_ENABLE,
1816                                     TRANS_STATE_ENABLE,
1817                                     100))
1818                 DRM_ERROR("Failed to enable PCH transcoder\n");
1819 }
1820
1821 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1822                                             enum pipe pipe)
1823 {
1824         i915_reg_t reg;
1825         uint32_t val;
1826
1827         /* FDI relies on the transcoder */
1828         assert_fdi_tx_disabled(dev_priv, pipe);
1829         assert_fdi_rx_disabled(dev_priv, pipe);
1830
1831         /* Ports must be off as well */
1832         assert_pch_ports_disabled(dev_priv, pipe);
1833
1834         reg = PCH_TRANSCONF(pipe);
1835         val = I915_READ(reg);
1836         val &= ~TRANS_ENABLE;
1837         I915_WRITE(reg, val);
1838         /* wait for PCH transcoder off, transcoder state */
1839         if (intel_wait_for_register(dev_priv,
1840                                     reg, TRANS_STATE_ENABLE, 0,
1841                                     50))
1842                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1843
1844         if (HAS_PCH_CPT(dev_priv)) {
1845                 /* Workaround: Clear the timing override chicken bit again. */
1846                 reg = TRANS_CHICKEN2(pipe);
1847                 val = I915_READ(reg);
1848                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1849                 I915_WRITE(reg, val);
1850         }
1851 }
1852
1853 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1854 {
1855         u32 val;
1856
1857         val = I915_READ(LPT_TRANSCONF);
1858         val &= ~TRANS_ENABLE;
1859         I915_WRITE(LPT_TRANSCONF, val);
1860         /* wait for PCH transcoder off, transcoder state */
1861         if (intel_wait_for_register(dev_priv,
1862                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1863                                     50))
1864                 DRM_ERROR("Failed to disable PCH transcoder\n");
1865
1866         /* Workaround: clear timing override bit. */
1867         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1868         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1869         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1870 }
1871
1872 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1873 {
1874         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1875
1876         WARN_ON(!crtc->config->has_pch_encoder);
1877
1878         if (HAS_PCH_LPT(dev_priv))
1879                 return PIPE_A;
1880         else
1881                 return crtc->pipe;
1882 }
1883
1884 /**
1885  * intel_enable_pipe - enable a pipe, asserting requirements
1886  * @crtc: crtc responsible for the pipe
1887  *
1888  * Enable @crtc's pipe, making sure that various hardware specific requirements
1889  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1890  */
1891 static void intel_enable_pipe(struct intel_crtc *crtc)
1892 {
1893         struct drm_device *dev = crtc->base.dev;
1894         struct drm_i915_private *dev_priv = to_i915(dev);
1895         enum pipe pipe = crtc->pipe;
1896         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1897         i915_reg_t reg;
1898         u32 val;
1899
1900         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1901
1902         assert_planes_disabled(dev_priv, pipe);
1903         assert_cursor_disabled(dev_priv, pipe);
1904         assert_sprites_disabled(dev_priv, pipe);
1905
1906         /*
1907          * A pipe without a PLL won't actually be able to drive bits from
1908          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1909          * need the check.
1910          */
1911         if (HAS_GMCH_DISPLAY(dev_priv)) {
1912                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1913                         assert_dsi_pll_enabled(dev_priv);
1914                 else
1915                         assert_pll_enabled(dev_priv, pipe);
1916         } else {
1917                 if (crtc->config->has_pch_encoder) {
1918                         /* if driving the PCH, we need FDI enabled */
1919                         assert_fdi_rx_pll_enabled(dev_priv,
1920                                                   intel_crtc_pch_transcoder(crtc));
1921                         assert_fdi_tx_pll_enabled(dev_priv,
1922                                                   (enum pipe) cpu_transcoder);
1923                 }
1924                 /* FIXME: assert CPU port conditions for SNB+ */
1925         }
1926
1927         reg = PIPECONF(cpu_transcoder);
1928         val = I915_READ(reg);
1929         if (val & PIPECONF_ENABLE) {
1930                 /* we keep both pipes enabled on 830 */
1931                 WARN_ON(!IS_I830(dev_priv));
1932                 return;
1933         }
1934
1935         I915_WRITE(reg, val | PIPECONF_ENABLE);
1936         POSTING_READ(reg);
1937
1938         /*
1939          * Until the pipe starts DSL will read as 0, which would cause
1940          * an apparent vblank timestamp jump, which messes up also the
1941          * frame count when it's derived from the timestamps. So let's
1942          * wait for the pipe to start properly before we call
1943          * drm_crtc_vblank_on()
1944          */
1945         if (dev->max_vblank_count == 0 &&
1946             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1947                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1948 }
1949
1950 /**
1951  * intel_disable_pipe - disable a pipe, asserting requirements
1952  * @crtc: crtc whose pipes is to be disabled
1953  *
1954  * Disable the pipe of @crtc, making sure that various hardware
1955  * specific requirements are met, if applicable, e.g. plane
1956  * disabled, panel fitter off, etc.
1957  *
1958  * Will wait until the pipe has shut down before returning.
1959  */
1960 static void intel_disable_pipe(struct intel_crtc *crtc)
1961 {
1962         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1963         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1964         enum pipe pipe = crtc->pipe;
1965         i915_reg_t reg;
1966         u32 val;
1967
1968         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1969
1970         /*
1971          * Make sure planes won't keep trying to pump pixels to us,
1972          * or we might hang the display.
1973          */
1974         assert_planes_disabled(dev_priv, pipe);
1975         assert_cursor_disabled(dev_priv, pipe);
1976         assert_sprites_disabled(dev_priv, pipe);
1977
1978         reg = PIPECONF(cpu_transcoder);
1979         val = I915_READ(reg);
1980         if ((val & PIPECONF_ENABLE) == 0)
1981                 return;
1982
1983         /*
1984          * Double wide has implications for planes
1985          * so best keep it disabled when not needed.
1986          */
1987         if (crtc->config->double_wide)
1988                 val &= ~PIPECONF_DOUBLE_WIDE;
1989
1990         /* Don't disable pipe or pipe PLLs if needed */
1991         if (!IS_I830(dev_priv))
1992                 val &= ~PIPECONF_ENABLE;
1993
1994         I915_WRITE(reg, val);
1995         if ((val & PIPECONF_ENABLE) == 0)
1996                 intel_wait_for_pipe_off(crtc);
1997 }
1998
1999 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2000 {
2001         return IS_GEN2(dev_priv) ? 2048 : 4096;
2002 }
2003
2004 static unsigned int
2005 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2006 {
2007         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2008         unsigned int cpp = fb->format->cpp[plane];
2009
2010         switch (fb->modifier) {
2011         case DRM_FORMAT_MOD_LINEAR:
2012                 return cpp;
2013         case I915_FORMAT_MOD_X_TILED:
2014                 if (IS_GEN2(dev_priv))
2015                         return 128;
2016                 else
2017                         return 512;
2018         case I915_FORMAT_MOD_Y_TILED_CCS:
2019                 if (plane == 1)
2020                         return 128;
2021                 /* fall through */
2022         case I915_FORMAT_MOD_Y_TILED:
2023                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2024                         return 128;
2025                 else
2026                         return 512;
2027         case I915_FORMAT_MOD_Yf_TILED_CCS:
2028                 if (plane == 1)
2029                         return 128;
2030                 /* fall through */
2031         case I915_FORMAT_MOD_Yf_TILED:
2032                 switch (cpp) {
2033                 case 1:
2034                         return 64;
2035                 case 2:
2036                 case 4:
2037                         return 128;
2038                 case 8:
2039                 case 16:
2040                         return 256;
2041                 default:
2042                         MISSING_CASE(cpp);
2043                         return cpp;
2044                 }
2045                 break;
2046         default:
2047                 MISSING_CASE(fb->modifier);
2048                 return cpp;
2049         }
2050 }
2051
2052 static unsigned int
2053 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2054 {
2055         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2056                 return 1;
2057         else
2058                 return intel_tile_size(to_i915(fb->dev)) /
2059                         intel_tile_width_bytes(fb, plane);
2060 }
2061
2062 /* Return the tile dimensions in pixel units */
2063 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2064                             unsigned int *tile_width,
2065                             unsigned int *tile_height)
2066 {
2067         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2068         unsigned int cpp = fb->format->cpp[plane];
2069
2070         *tile_width = tile_width_bytes / cpp;
2071         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2072 }
2073
2074 unsigned int
2075 intel_fb_align_height(const struct drm_framebuffer *fb,
2076                       int plane, unsigned int height)
2077 {
2078         unsigned int tile_height = intel_tile_height(fb, plane);
2079
2080         return ALIGN(height, tile_height);
2081 }
2082
2083 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2084 {
2085         unsigned int size = 0;
2086         int i;
2087
2088         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2089                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2090
2091         return size;
2092 }
2093
2094 static void
2095 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2096                         const struct drm_framebuffer *fb,
2097                         unsigned int rotation)
2098 {
2099         view->type = I915_GGTT_VIEW_NORMAL;
2100         if (drm_rotation_90_or_270(rotation)) {
2101                 view->type = I915_GGTT_VIEW_ROTATED;
2102                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2103         }
2104 }
2105
2106 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2107 {
2108         if (IS_I830(dev_priv))
2109                 return 16 * 1024;
2110         else if (IS_I85X(dev_priv))
2111                 return 256;
2112         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2113                 return 32;
2114         else
2115                 return 4 * 1024;
2116 }
2117
2118 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2119 {
2120         if (INTEL_INFO(dev_priv)->gen >= 9)
2121                 return 256 * 1024;
2122         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2123                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2124                 return 128 * 1024;
2125         else if (INTEL_INFO(dev_priv)->gen >= 4)
2126                 return 4 * 1024;
2127         else
2128                 return 0;
2129 }
2130
2131 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2132                                          int plane)
2133 {
2134         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2135
2136         /* AUX_DIST needs only 4K alignment */
2137         if (plane == 1)
2138                 return 4096;
2139
2140         switch (fb->modifier) {
2141         case DRM_FORMAT_MOD_LINEAR:
2142                 return intel_linear_alignment(dev_priv);
2143         case I915_FORMAT_MOD_X_TILED:
2144                 if (INTEL_GEN(dev_priv) >= 9)
2145                         return 256 * 1024;
2146                 return 0;
2147         case I915_FORMAT_MOD_Y_TILED_CCS:
2148         case I915_FORMAT_MOD_Yf_TILED_CCS:
2149         case I915_FORMAT_MOD_Y_TILED:
2150         case I915_FORMAT_MOD_Yf_TILED:
2151                 return 1 * 1024 * 1024;
2152         default:
2153                 MISSING_CASE(fb->modifier);
2154                 return 0;
2155         }
2156 }
2157
2158 struct i915_vma *
2159 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2160 {
2161         struct drm_device *dev = fb->dev;
2162         struct drm_i915_private *dev_priv = to_i915(dev);
2163         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2164         struct i915_ggtt_view view;
2165         struct i915_vma *vma;
2166         u32 alignment;
2167
2168         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2169
2170         alignment = intel_surf_alignment(fb, 0);
2171
2172         intel_fill_fb_ggtt_view(&view, fb, rotation);
2173
2174         /* Note that the w/a also requires 64 PTE of padding following the
2175          * bo. We currently fill all unused PTE with the shadow page and so
2176          * we should always have valid PTE following the scanout preventing
2177          * the VT-d warning.
2178          */
2179         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2180                 alignment = 256 * 1024;
2181
2182         /*
2183          * Global gtt pte registers are special registers which actually forward
2184          * writes to a chunk of system memory. Which means that there is no risk
2185          * that the register values disappear as soon as we call
2186          * intel_runtime_pm_put(), so it is correct to wrap only the
2187          * pin/unpin/fence and not more.
2188          */
2189         intel_runtime_pm_get(dev_priv);
2190
2191         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2192
2193         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2194         if (IS_ERR(vma))
2195                 goto err;
2196
2197         if (i915_vma_is_map_and_fenceable(vma)) {
2198                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2199                  * fence, whereas 965+ only requires a fence if using
2200                  * framebuffer compression.  For simplicity, we always, when
2201                  * possible, install a fence as the cost is not that onerous.
2202                  *
2203                  * If we fail to fence the tiled scanout, then either the
2204                  * modeset will reject the change (which is highly unlikely as
2205                  * the affected systems, all but one, do not have unmappable
2206                  * space) or we will not be able to enable full powersaving
2207                  * techniques (also likely not to apply due to various limits
2208                  * FBC and the like impose on the size of the buffer, which
2209                  * presumably we violated anyway with this unmappable buffer).
2210                  * Anyway, it is presumably better to stumble onwards with
2211                  * something and try to run the system in a "less than optimal"
2212                  * mode that matches the user configuration.
2213                  */
2214                 i915_vma_pin_fence(vma);
2215         }
2216
2217         i915_vma_get(vma);
2218 err:
2219         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2220
2221         intel_runtime_pm_put(dev_priv);
2222         return vma;
2223 }
2224
2225 void intel_unpin_fb_vma(struct i915_vma *vma)
2226 {
2227         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2228
2229         i915_vma_unpin_fence(vma);
2230         i915_gem_object_unpin_from_display_plane(vma);
2231         i915_vma_put(vma);
2232 }
2233
2234 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2235                           unsigned int rotation)
2236 {
2237         if (drm_rotation_90_or_270(rotation))
2238                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2239         else
2240                 return fb->pitches[plane];
2241 }
2242
2243 /*
2244  * Convert the x/y offsets into a linear offset.
2245  * Only valid with 0/180 degree rotation, which is fine since linear
2246  * offset is only used with linear buffers on pre-hsw and tiled buffers
2247  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2248  */
2249 u32 intel_fb_xy_to_linear(int x, int y,
2250                           const struct intel_plane_state *state,
2251                           int plane)
2252 {
2253         const struct drm_framebuffer *fb = state->base.fb;
2254         unsigned int cpp = fb->format->cpp[plane];
2255         unsigned int pitch = fb->pitches[plane];
2256
2257         return y * pitch + x * cpp;
2258 }
2259
2260 /*
2261  * Add the x/y offsets derived from fb->offsets[] to the user
2262  * specified plane src x/y offsets. The resulting x/y offsets
2263  * specify the start of scanout from the beginning of the gtt mapping.
2264  */
2265 void intel_add_fb_offsets(int *x, int *y,
2266                           const struct intel_plane_state *state,
2267                           int plane)
2268
2269 {
2270         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2271         unsigned int rotation = state->base.rotation;
2272
2273         if (drm_rotation_90_or_270(rotation)) {
2274                 *x += intel_fb->rotated[plane].x;
2275                 *y += intel_fb->rotated[plane].y;
2276         } else {
2277                 *x += intel_fb->normal[plane].x;
2278                 *y += intel_fb->normal[plane].y;
2279         }
2280 }
2281
2282 static u32 __intel_adjust_tile_offset(int *x, int *y,
2283                                       unsigned int tile_width,
2284                                       unsigned int tile_height,
2285                                       unsigned int tile_size,
2286                                       unsigned int pitch_tiles,
2287                                       u32 old_offset,
2288                                       u32 new_offset)
2289 {
2290         unsigned int pitch_pixels = pitch_tiles * tile_width;
2291         unsigned int tiles;
2292
2293         WARN_ON(old_offset & (tile_size - 1));
2294         WARN_ON(new_offset & (tile_size - 1));
2295         WARN_ON(new_offset > old_offset);
2296
2297         tiles = (old_offset - new_offset) / tile_size;
2298
2299         *y += tiles / pitch_tiles * tile_height;
2300         *x += tiles % pitch_tiles * tile_width;
2301
2302         /* minimize x in case it got needlessly big */
2303         *y += *x / pitch_pixels * tile_height;
2304         *x %= pitch_pixels;
2305
2306         return new_offset;
2307 }
2308
2309 static u32 _intel_adjust_tile_offset(int *x, int *y,
2310                                      const struct drm_framebuffer *fb, int plane,
2311                                      unsigned int rotation,
2312                                      u32 old_offset, u32 new_offset)
2313 {
2314         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2315         unsigned int cpp = fb->format->cpp[plane];
2316         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2317
2318         WARN_ON(new_offset > old_offset);
2319
2320         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2321                 unsigned int tile_size, tile_width, tile_height;
2322                 unsigned int pitch_tiles;
2323
2324                 tile_size = intel_tile_size(dev_priv);
2325                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2326
2327                 if (drm_rotation_90_or_270(rotation)) {
2328                         pitch_tiles = pitch / tile_height;
2329                         swap(tile_width, tile_height);
2330                 } else {
2331                         pitch_tiles = pitch / (tile_width * cpp);
2332                 }
2333
2334                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2335                                            tile_size, pitch_tiles,
2336                                            old_offset, new_offset);
2337         } else {
2338                 old_offset += *y * pitch + *x * cpp;
2339
2340                 *y = (old_offset - new_offset) / pitch;
2341                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2342         }
2343
2344         return new_offset;
2345 }
2346
2347 /*
2348  * Adjust the tile offset by moving the difference into
2349  * the x/y offsets.
2350  */
2351 static u32 intel_adjust_tile_offset(int *x, int *y,
2352                                     const struct intel_plane_state *state, int plane,
2353                                     u32 old_offset, u32 new_offset)
2354 {
2355         return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2356                                          state->base.rotation,
2357                                          old_offset, new_offset);
2358 }
2359
2360 /*
2361  * Computes the linear offset to the base tile and adjusts
2362  * x, y. bytes per pixel is assumed to be a power-of-two.
2363  *
2364  * In the 90/270 rotated case, x and y are assumed
2365  * to be already rotated to match the rotated GTT view, and
2366  * pitch is the tile_height aligned framebuffer height.
2367  *
2368  * This function is used when computing the derived information
2369  * under intel_framebuffer, so using any of that information
2370  * here is not allowed. Anything under drm_framebuffer can be
2371  * used. This is why the user has to pass in the pitch since it
2372  * is specified in the rotated orientation.
2373  */
2374 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2375                                       int *x, int *y,
2376                                       const struct drm_framebuffer *fb, int plane,
2377                                       unsigned int pitch,
2378                                       unsigned int rotation,
2379                                       u32 alignment)
2380 {
2381         uint64_t fb_modifier = fb->modifier;
2382         unsigned int cpp = fb->format->cpp[plane];
2383         u32 offset, offset_aligned;
2384
2385         if (alignment)
2386                 alignment--;
2387
2388         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2389                 unsigned int tile_size, tile_width, tile_height;
2390                 unsigned int tile_rows, tiles, pitch_tiles;
2391
2392                 tile_size = intel_tile_size(dev_priv);
2393                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2394
2395                 if (drm_rotation_90_or_270(rotation)) {
2396                         pitch_tiles = pitch / tile_height;
2397                         swap(tile_width, tile_height);
2398                 } else {
2399                         pitch_tiles = pitch / (tile_width * cpp);
2400                 }
2401
2402                 tile_rows = *y / tile_height;
2403                 *y %= tile_height;
2404
2405                 tiles = *x / tile_width;
2406                 *x %= tile_width;
2407
2408                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2409                 offset_aligned = offset & ~alignment;
2410
2411                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2412                                            tile_size, pitch_tiles,
2413                                            offset, offset_aligned);
2414         } else {
2415                 offset = *y * pitch + *x * cpp;
2416                 offset_aligned = offset & ~alignment;
2417
2418                 *y = (offset & alignment) / pitch;
2419                 *x = ((offset & alignment) - *y * pitch) / cpp;
2420         }
2421
2422         return offset_aligned;
2423 }
2424
2425 u32 intel_compute_tile_offset(int *x, int *y,
2426                               const struct intel_plane_state *state,
2427                               int plane)
2428 {
2429         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2430         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2431         const struct drm_framebuffer *fb = state->base.fb;
2432         unsigned int rotation = state->base.rotation;
2433         int pitch = intel_fb_pitch(fb, plane, rotation);
2434         u32 alignment;
2435
2436         if (intel_plane->id == PLANE_CURSOR)
2437                 alignment = intel_cursor_alignment(dev_priv);
2438         else
2439                 alignment = intel_surf_alignment(fb, plane);
2440
2441         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2442                                           rotation, alignment);
2443 }
2444
2445 /* Convert the fb->offset[] into x/y offsets */
2446 static int intel_fb_offset_to_xy(int *x, int *y,
2447                                  const struct drm_framebuffer *fb, int plane)
2448 {
2449         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2450
2451         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2452             fb->offsets[plane] % intel_tile_size(dev_priv))
2453                 return -EINVAL;
2454
2455         *x = 0;
2456         *y = 0;
2457
2458         _intel_adjust_tile_offset(x, y,
2459                                   fb, plane, DRM_MODE_ROTATE_0,
2460                                   fb->offsets[plane], 0);
2461
2462         return 0;
2463 }
2464
2465 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2466 {
2467         switch (fb_modifier) {
2468         case I915_FORMAT_MOD_X_TILED:
2469                 return I915_TILING_X;
2470         case I915_FORMAT_MOD_Y_TILED:
2471         case I915_FORMAT_MOD_Y_TILED_CCS:
2472                 return I915_TILING_Y;
2473         default:
2474                 return I915_TILING_NONE;
2475         }
2476 }
2477
2478 static const struct drm_format_info ccs_formats[] = {
2479         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2480         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2481         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2482         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2483 };
2484
2485 static const struct drm_format_info *
2486 lookup_format_info(const struct drm_format_info formats[],
2487                    int num_formats, u32 format)
2488 {
2489         int i;
2490
2491         for (i = 0; i < num_formats; i++) {
2492                 if (formats[i].format == format)
2493                         return &formats[i];
2494         }
2495
2496         return NULL;
2497 }
2498
2499 static const struct drm_format_info *
2500 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2501 {
2502         switch (cmd->modifier[0]) {
2503         case I915_FORMAT_MOD_Y_TILED_CCS:
2504         case I915_FORMAT_MOD_Yf_TILED_CCS:
2505                 return lookup_format_info(ccs_formats,
2506                                           ARRAY_SIZE(ccs_formats),
2507                                           cmd->pixel_format);
2508         default:
2509                 return NULL;
2510         }
2511 }
2512
2513 static int
2514 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2515                    struct drm_framebuffer *fb)
2516 {
2517         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2518         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2519         u32 gtt_offset_rotated = 0;
2520         unsigned int max_size = 0;
2521         int i, num_planes = fb->format->num_planes;
2522         unsigned int tile_size = intel_tile_size(dev_priv);
2523
2524         for (i = 0; i < num_planes; i++) {
2525                 unsigned int width, height;
2526                 unsigned int cpp, size;
2527                 u32 offset;
2528                 int x, y;
2529                 int ret;
2530
2531                 cpp = fb->format->cpp[i];
2532                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2533                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2534
2535                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2536                 if (ret) {
2537                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2538                                       i, fb->offsets[i]);
2539                         return ret;
2540                 }
2541
2542                 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2543                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2544                         int hsub = fb->format->hsub;
2545                         int vsub = fb->format->vsub;
2546                         int tile_width, tile_height;
2547                         int main_x, main_y;
2548                         int ccs_x, ccs_y;
2549
2550                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2551                         tile_width *= hsub;
2552                         tile_height *= vsub;
2553
2554                         ccs_x = (x * hsub) % tile_width;
2555                         ccs_y = (y * vsub) % tile_height;
2556                         main_x = intel_fb->normal[0].x % tile_width;
2557                         main_y = intel_fb->normal[0].y % tile_height;
2558
2559                         /*
2560                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2561                          * x/y offsets must match between CCS and the main surface.
2562                          */
2563                         if (main_x != ccs_x || main_y != ccs_y) {
2564                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2565                                               main_x, main_y,
2566                                               ccs_x, ccs_y,
2567                                               intel_fb->normal[0].x,
2568                                               intel_fb->normal[0].y,
2569                                               x, y);
2570                                 return -EINVAL;
2571                         }
2572                 }
2573
2574                 /*
2575                  * The fence (if used) is aligned to the start of the object
2576                  * so having the framebuffer wrap around across the edge of the
2577                  * fenced region doesn't really work. We have no API to configure
2578                  * the fence start offset within the object (nor could we probably
2579                  * on gen2/3). So it's just easier if we just require that the
2580                  * fb layout agrees with the fence layout. We already check that the
2581                  * fb stride matches the fence stride elsewhere.
2582                  */
2583                 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2584                     (x + width) * cpp > fb->pitches[i]) {
2585                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2586                                       i, fb->offsets[i]);
2587                         return -EINVAL;
2588                 }
2589
2590                 /*
2591                  * First pixel of the framebuffer from
2592                  * the start of the normal gtt mapping.
2593                  */
2594                 intel_fb->normal[i].x = x;
2595                 intel_fb->normal[i].y = y;
2596
2597                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2598                                                     fb, i, fb->pitches[i],
2599                                                     DRM_MODE_ROTATE_0, tile_size);
2600                 offset /= tile_size;
2601
2602                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2603                         unsigned int tile_width, tile_height;
2604                         unsigned int pitch_tiles;
2605                         struct drm_rect r;
2606
2607                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2608
2609                         rot_info->plane[i].offset = offset;
2610                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2611                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2612                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2613
2614                         intel_fb->rotated[i].pitch =
2615                                 rot_info->plane[i].height * tile_height;
2616
2617                         /* how many tiles does this plane need */
2618                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2619                         /*
2620                          * If the plane isn't horizontally tile aligned,
2621                          * we need one more tile.
2622                          */
2623                         if (x != 0)
2624                                 size++;
2625
2626                         /* rotate the x/y offsets to match the GTT view */
2627                         r.x1 = x;
2628                         r.y1 = y;
2629                         r.x2 = x + width;
2630                         r.y2 = y + height;
2631                         drm_rect_rotate(&r,
2632                                         rot_info->plane[i].width * tile_width,
2633                                         rot_info->plane[i].height * tile_height,
2634                                         DRM_MODE_ROTATE_270);
2635                         x = r.x1;
2636                         y = r.y1;
2637
2638                         /* rotate the tile dimensions to match the GTT view */
2639                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2640                         swap(tile_width, tile_height);
2641
2642                         /*
2643                          * We only keep the x/y offsets, so push all of the
2644                          * gtt offset into the x/y offsets.
2645                          */
2646                         __intel_adjust_tile_offset(&x, &y,
2647                                                    tile_width, tile_height,
2648                                                    tile_size, pitch_tiles,
2649                                                    gtt_offset_rotated * tile_size, 0);
2650
2651                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2652
2653                         /*
2654                          * First pixel of the framebuffer from
2655                          * the start of the rotated gtt mapping.
2656                          */
2657                         intel_fb->rotated[i].x = x;
2658                         intel_fb->rotated[i].y = y;
2659                 } else {
2660                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2661                                             x * cpp, tile_size);
2662                 }
2663
2664                 /* how many tiles in total needed in the bo */
2665                 max_size = max(max_size, offset + size);
2666         }
2667
2668         if (max_size * tile_size > intel_fb->obj->base.size) {
2669                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2670                               max_size * tile_size, intel_fb->obj->base.size);
2671                 return -EINVAL;
2672         }
2673
2674         return 0;
2675 }
2676
2677 static int i9xx_format_to_fourcc(int format)
2678 {
2679         switch (format) {
2680         case DISPPLANE_8BPP:
2681                 return DRM_FORMAT_C8;
2682         case DISPPLANE_BGRX555:
2683                 return DRM_FORMAT_XRGB1555;
2684         case DISPPLANE_BGRX565:
2685                 return DRM_FORMAT_RGB565;
2686         default:
2687         case DISPPLANE_BGRX888:
2688                 return DRM_FORMAT_XRGB8888;
2689         case DISPPLANE_RGBX888:
2690                 return DRM_FORMAT_XBGR8888;
2691         case DISPPLANE_BGRX101010:
2692                 return DRM_FORMAT_XRGB2101010;
2693         case DISPPLANE_RGBX101010:
2694                 return DRM_FORMAT_XBGR2101010;
2695         }
2696 }
2697
2698 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2699 {
2700         switch (format) {
2701         case PLANE_CTL_FORMAT_RGB_565:
2702                 return DRM_FORMAT_RGB565;
2703         default:
2704         case PLANE_CTL_FORMAT_XRGB_8888:
2705                 if (rgb_order) {
2706                         if (alpha)
2707                                 return DRM_FORMAT_ABGR8888;
2708                         else
2709                                 return DRM_FORMAT_XBGR8888;
2710                 } else {
2711                         if (alpha)
2712                                 return DRM_FORMAT_ARGB8888;
2713                         else
2714                                 return DRM_FORMAT_XRGB8888;
2715                 }
2716         case PLANE_CTL_FORMAT_XRGB_2101010:
2717                 if (rgb_order)
2718                         return DRM_FORMAT_XBGR2101010;
2719                 else
2720                         return DRM_FORMAT_XRGB2101010;
2721         }
2722 }
2723
2724 static bool
2725 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2726                               struct intel_initial_plane_config *plane_config)
2727 {
2728         struct drm_device *dev = crtc->base.dev;
2729         struct drm_i915_private *dev_priv = to_i915(dev);
2730         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2731         struct drm_i915_gem_object *obj = NULL;
2732         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2733         struct drm_framebuffer *fb = &plane_config->fb->base;
2734         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2735         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2736                                     PAGE_SIZE);
2737
2738         size_aligned -= base_aligned;
2739
2740         if (plane_config->size == 0)
2741                 return false;
2742
2743         /* If the FB is too big, just don't use it since fbdev is not very
2744          * important and we should probably use that space with FBC or other
2745          * features. */
2746         if (size_aligned * 2 > ggtt->stolen_usable_size)
2747                 return false;
2748
2749         mutex_lock(&dev->struct_mutex);
2750         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2751                                                              base_aligned,
2752                                                              base_aligned,
2753                                                              size_aligned);
2754         mutex_unlock(&dev->struct_mutex);
2755         if (!obj)
2756                 return false;
2757
2758         if (plane_config->tiling == I915_TILING_X)
2759                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2760
2761         mode_cmd.pixel_format = fb->format->format;
2762         mode_cmd.width = fb->width;
2763         mode_cmd.height = fb->height;
2764         mode_cmd.pitches[0] = fb->pitches[0];
2765         mode_cmd.modifier[0] = fb->modifier;
2766         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2767
2768         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2769                 DRM_DEBUG_KMS("intel fb init failed\n");
2770                 goto out_unref_obj;
2771         }
2772
2773
2774         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2775         return true;
2776
2777 out_unref_obj:
2778         i915_gem_object_put(obj);
2779         return false;
2780 }
2781
2782 static void
2783 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2784                         struct intel_plane_state *plane_state,
2785                         bool visible)
2786 {
2787         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2788
2789         plane_state->base.visible = visible;
2790
2791         /* FIXME pre-g4x don't work like this */
2792         if (visible) {
2793                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2794                 crtc_state->active_planes |= BIT(plane->id);
2795         } else {
2796                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2797                 crtc_state->active_planes &= ~BIT(plane->id);
2798         }
2799
2800         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2801                       crtc_state->base.crtc->name,
2802                       crtc_state->active_planes);
2803 }
2804
2805 static void
2806 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2807                              struct intel_initial_plane_config *plane_config)
2808 {
2809         struct drm_device *dev = intel_crtc->base.dev;
2810         struct drm_i915_private *dev_priv = to_i915(dev);
2811         struct drm_crtc *c;
2812         struct drm_i915_gem_object *obj;
2813         struct drm_plane *primary = intel_crtc->base.primary;
2814         struct drm_plane_state *plane_state = primary->state;
2815         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2816         struct intel_plane *intel_plane = to_intel_plane(primary);
2817         struct intel_plane_state *intel_state =
2818                 to_intel_plane_state(plane_state);
2819         struct drm_framebuffer *fb;
2820
2821         if (!plane_config->fb)
2822                 return;
2823
2824         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2825                 fb = &plane_config->fb->base;
2826                 goto valid_fb;
2827         }
2828
2829         kfree(plane_config->fb);
2830
2831         /*
2832          * Failed to alloc the obj, check to see if we should share
2833          * an fb with another CRTC instead
2834          */
2835         for_each_crtc(dev, c) {
2836                 struct intel_plane_state *state;
2837
2838                 if (c == &intel_crtc->base)
2839                         continue;
2840
2841                 if (!to_intel_crtc(c)->active)
2842                         continue;
2843
2844                 state = to_intel_plane_state(c->primary->state);
2845                 if (!state->vma)
2846                         continue;
2847
2848                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2849                         fb = c->primary->fb;
2850                         drm_framebuffer_get(fb);
2851                         goto valid_fb;
2852                 }
2853         }
2854
2855         /*
2856          * We've failed to reconstruct the BIOS FB.  Current display state
2857          * indicates that the primary plane is visible, but has a NULL FB,
2858          * which will lead to problems later if we don't fix it up.  The
2859          * simplest solution is to just disable the primary plane now and
2860          * pretend the BIOS never had it enabled.
2861          */
2862         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2863                                 to_intel_plane_state(plane_state),
2864                                 false);
2865         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2866         trace_intel_disable_plane(primary, intel_crtc);
2867         intel_plane->disable_plane(intel_plane, intel_crtc);
2868
2869         return;
2870
2871 valid_fb:
2872         mutex_lock(&dev->struct_mutex);
2873         intel_state->vma =
2874                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2875         mutex_unlock(&dev->struct_mutex);
2876         if (IS_ERR(intel_state->vma)) {
2877                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2878                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2879
2880                 intel_state->vma = NULL;
2881                 drm_framebuffer_put(fb);
2882                 return;
2883         }
2884
2885         plane_state->src_x = 0;
2886         plane_state->src_y = 0;
2887         plane_state->src_w = fb->width << 16;
2888         plane_state->src_h = fb->height << 16;
2889
2890         plane_state->crtc_x = 0;
2891         plane_state->crtc_y = 0;
2892         plane_state->crtc_w = fb->width;
2893         plane_state->crtc_h = fb->height;
2894
2895         intel_state->base.src = drm_plane_state_src(plane_state);
2896         intel_state->base.dst = drm_plane_state_dest(plane_state);
2897
2898         obj = intel_fb_obj(fb);
2899         if (i915_gem_object_is_tiled(obj))
2900                 dev_priv->preserve_bios_swizzle = true;
2901
2902         drm_framebuffer_get(fb);
2903         primary->fb = primary->state->fb = fb;
2904         primary->crtc = primary->state->crtc = &intel_crtc->base;
2905
2906         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2907                                 to_intel_plane_state(plane_state),
2908                                 true);
2909
2910         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2911                   &obj->frontbuffer_bits);
2912 }
2913
2914 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2915                                unsigned int rotation)
2916 {
2917         int cpp = fb->format->cpp[plane];
2918
2919         switch (fb->modifier) {
2920         case DRM_FORMAT_MOD_LINEAR:
2921         case I915_FORMAT_MOD_X_TILED:
2922                 switch (cpp) {
2923                 case 8:
2924                         return 4096;
2925                 case 4:
2926                 case 2:
2927                 case 1:
2928                         return 8192;
2929                 default:
2930                         MISSING_CASE(cpp);
2931                         break;
2932                 }
2933                 break;
2934         case I915_FORMAT_MOD_Y_TILED_CCS:
2935         case I915_FORMAT_MOD_Yf_TILED_CCS:
2936                 /* FIXME AUX plane? */
2937         case I915_FORMAT_MOD_Y_TILED:
2938         case I915_FORMAT_MOD_Yf_TILED:
2939                 switch (cpp) {
2940                 case 8:
2941                         return 2048;
2942                 case 4:
2943                         return 4096;
2944                 case 2:
2945                 case 1:
2946                         return 8192;
2947                 default:
2948                         MISSING_CASE(cpp);
2949                         break;
2950                 }
2951                 break;
2952         default:
2953                 MISSING_CASE(fb->modifier);
2954         }
2955
2956         return 2048;
2957 }
2958
2959 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2960                                            int main_x, int main_y, u32 main_offset)
2961 {
2962         const struct drm_framebuffer *fb = plane_state->base.fb;
2963         int hsub = fb->format->hsub;
2964         int vsub = fb->format->vsub;
2965         int aux_x = plane_state->aux.x;
2966         int aux_y = plane_state->aux.y;
2967         u32 aux_offset = plane_state->aux.offset;
2968         u32 alignment = intel_surf_alignment(fb, 1);
2969
2970         while (aux_offset >= main_offset && aux_y <= main_y) {
2971                 int x, y;
2972
2973                 if (aux_x == main_x && aux_y == main_y)
2974                         break;
2975
2976                 if (aux_offset == 0)
2977                         break;
2978
2979                 x = aux_x / hsub;
2980                 y = aux_y / vsub;
2981                 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2982                                                       aux_offset, aux_offset - alignment);
2983                 aux_x = x * hsub + aux_x % hsub;
2984                 aux_y = y * vsub + aux_y % vsub;
2985         }
2986
2987         if (aux_x != main_x || aux_y != main_y)
2988                 return false;
2989
2990         plane_state->aux.offset = aux_offset;
2991         plane_state->aux.x = aux_x;
2992         plane_state->aux.y = aux_y;
2993
2994         return true;
2995 }
2996
2997 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2998 {
2999         const struct drm_framebuffer *fb = plane_state->base.fb;
3000         unsigned int rotation = plane_state->base.rotation;
3001         int x = plane_state->base.src.x1 >> 16;
3002         int y = plane_state->base.src.y1 >> 16;
3003         int w = drm_rect_width(&plane_state->base.src) >> 16;
3004         int h = drm_rect_height(&plane_state->base.src) >> 16;
3005         int max_width = skl_max_plane_width(fb, 0, rotation);
3006         int max_height = 4096;
3007         u32 alignment, offset, aux_offset = plane_state->aux.offset;
3008
3009         if (w > max_width || h > max_height) {
3010                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3011                               w, h, max_width, max_height);
3012                 return -EINVAL;
3013         }
3014
3015         intel_add_fb_offsets(&x, &y, plane_state, 0);
3016         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3017         alignment = intel_surf_alignment(fb, 0);
3018
3019         /*
3020          * AUX surface offset is specified as the distance from the
3021          * main surface offset, and it must be non-negative. Make
3022          * sure that is what we will get.
3023          */
3024         if (offset > aux_offset)
3025                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3026                                                   offset, aux_offset & ~(alignment - 1));
3027
3028         /*
3029          * When using an X-tiled surface, the plane blows up
3030          * if the x offset + width exceed the stride.
3031          *
3032          * TODO: linear and Y-tiled seem fine, Yf untested,
3033          */
3034         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3035                 int cpp = fb->format->cpp[0];
3036
3037                 while ((x + w) * cpp > fb->pitches[0]) {
3038                         if (offset == 0) {
3039                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3040                                 return -EINVAL;
3041                         }
3042
3043                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3044                                                           offset, offset - alignment);
3045                 }
3046         }
3047
3048         /*
3049          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3050          * they match with the main surface x/y offsets.
3051          */
3052         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3053             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3054                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3055                         if (offset == 0)
3056                                 break;
3057
3058                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3059                                                           offset, offset - alignment);
3060                 }
3061
3062                 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3063                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3064                         return -EINVAL;
3065                 }
3066         }
3067
3068         plane_state->main.offset = offset;
3069         plane_state->main.x = x;
3070         plane_state->main.y = y;
3071
3072         return 0;
3073 }
3074
3075 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3076 {
3077         const struct drm_framebuffer *fb = plane_state->base.fb;
3078         unsigned int rotation = plane_state->base.rotation;
3079         int max_width = skl_max_plane_width(fb, 1, rotation);
3080         int max_height = 4096;
3081         int x = plane_state->base.src.x1 >> 17;
3082         int y = plane_state->base.src.y1 >> 17;
3083         int w = drm_rect_width(&plane_state->base.src) >> 17;
3084         int h = drm_rect_height(&plane_state->base.src) >> 17;
3085         u32 offset;
3086
3087         intel_add_fb_offsets(&x, &y, plane_state, 1);
3088         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3089
3090         /* FIXME not quite sure how/if these apply to the chroma plane */
3091         if (w > max_width || h > max_height) {
3092                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3093                               w, h, max_width, max_height);
3094                 return -EINVAL;
3095         }
3096
3097         plane_state->aux.offset = offset;
3098         plane_state->aux.x = x;
3099         plane_state->aux.y = y;
3100
3101         return 0;
3102 }
3103
3104 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3105 {
3106         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3107         struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3108         const struct drm_framebuffer *fb = plane_state->base.fb;
3109         int src_x = plane_state->base.src.x1 >> 16;
3110         int src_y = plane_state->base.src.y1 >> 16;
3111         int hsub = fb->format->hsub;
3112         int vsub = fb->format->vsub;
3113         int x = src_x / hsub;
3114         int y = src_y / vsub;
3115         u32 offset;
3116
3117         switch (plane->id) {
3118         case PLANE_PRIMARY:
3119         case PLANE_SPRITE0:
3120                 break;
3121         default:
3122                 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3123                 return -EINVAL;
3124         }
3125
3126         if (crtc->pipe == PIPE_C) {
3127                 DRM_DEBUG_KMS("No RC support on pipe C\n");
3128                 return -EINVAL;
3129         }
3130
3131         if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3132                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3133                               plane_state->base.rotation);
3134                 return -EINVAL;
3135         }
3136
3137         intel_add_fb_offsets(&x, &y, plane_state, 1);
3138         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3139
3140         plane_state->aux.offset = offset;
3141         plane_state->aux.x = x * hsub + src_x % hsub;
3142         plane_state->aux.y = y * vsub + src_y % vsub;
3143
3144         return 0;
3145 }
3146
3147 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3148 {
3149         const struct drm_framebuffer *fb = plane_state->base.fb;
3150         unsigned int rotation = plane_state->base.rotation;
3151         int ret;
3152
3153         if (!plane_state->base.visible)
3154                 return 0;
3155
3156         /* Rotate src coordinates to match rotated GTT view */
3157         if (drm_rotation_90_or_270(rotation))
3158                 drm_rect_rotate(&plane_state->base.src,
3159                                 fb->width << 16, fb->height << 16,
3160                                 DRM_MODE_ROTATE_270);
3161
3162         /*
3163          * Handle the AUX surface first since
3164          * the main surface setup depends on it.
3165          */
3166         if (fb->format->format == DRM_FORMAT_NV12) {
3167                 ret = skl_check_nv12_aux_surface(plane_state);
3168                 if (ret)
3169                         return ret;
3170         } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3171                    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3172                 ret = skl_check_ccs_aux_surface(plane_state);
3173                 if (ret)
3174                         return ret;
3175         } else {
3176                 plane_state->aux.offset = ~0xfff;
3177                 plane_state->aux.x = 0;
3178                 plane_state->aux.y = 0;
3179         }
3180
3181         ret = skl_check_main_surface(plane_state);
3182         if (ret)
3183                 return ret;
3184
3185         return 0;
3186 }
3187
3188 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3189                           const struct intel_plane_state *plane_state)
3190 {
3191         struct drm_i915_private *dev_priv =
3192                 to_i915(plane_state->base.plane->dev);
3193         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3194         const struct drm_framebuffer *fb = plane_state->base.fb;
3195         unsigned int rotation = plane_state->base.rotation;
3196         u32 dspcntr;
3197
3198         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3199
3200         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3201             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3202                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3203
3204         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3205                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3206
3207         if (INTEL_GEN(dev_priv) < 4)
3208                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3209
3210         switch (fb->format->format) {
3211         case DRM_FORMAT_C8:
3212                 dspcntr |= DISPPLANE_8BPP;
3213                 break;
3214         case DRM_FORMAT_XRGB1555:
3215                 dspcntr |= DISPPLANE_BGRX555;
3216                 break;
3217         case DRM_FORMAT_RGB565:
3218                 dspcntr |= DISPPLANE_BGRX565;
3219                 break;
3220         case DRM_FORMAT_XRGB8888:
3221                 dspcntr |= DISPPLANE_BGRX888;
3222                 break;
3223         case DRM_FORMAT_XBGR8888:
3224                 dspcntr |= DISPPLANE_RGBX888;
3225                 break;
3226         case DRM_FORMAT_XRGB2101010:
3227                 dspcntr |= DISPPLANE_BGRX101010;
3228                 break;
3229         case DRM_FORMAT_XBGR2101010:
3230                 dspcntr |= DISPPLANE_RGBX101010;
3231                 break;
3232         default:
3233                 MISSING_CASE(fb->format->format);
3234                 return 0;
3235         }
3236
3237         if (INTEL_GEN(dev_priv) >= 4 &&
3238             fb->modifier == I915_FORMAT_MOD_X_TILED)
3239                 dspcntr |= DISPPLANE_TILED;
3240
3241         if (rotation & DRM_MODE_ROTATE_180)
3242                 dspcntr |= DISPPLANE_ROTATE_180;
3243
3244         if (rotation & DRM_MODE_REFLECT_X)
3245                 dspcntr |= DISPPLANE_MIRROR;
3246
3247         return dspcntr;
3248 }
3249
3250 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3251 {
3252         struct drm_i915_private *dev_priv =
3253                 to_i915(plane_state->base.plane->dev);
3254         int src_x = plane_state->base.src.x1 >> 16;
3255         int src_y = plane_state->base.src.y1 >> 16;
3256         u32 offset;
3257
3258         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3259
3260         if (INTEL_GEN(dev_priv) >= 4)
3261                 offset = intel_compute_tile_offset(&src_x, &src_y,
3262                                                    plane_state, 0);
3263         else
3264                 offset = 0;
3265
3266         /* HSW/BDW do this automagically in hardware */
3267         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3268                 unsigned int rotation = plane_state->base.rotation;
3269                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3270                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3271
3272                 if (rotation & DRM_MODE_ROTATE_180) {
3273                         src_x += src_w - 1;
3274                         src_y += src_h - 1;
3275                 } else if (rotation & DRM_MODE_REFLECT_X) {
3276                         src_x += src_w - 1;
3277                 }
3278         }
3279
3280         plane_state->main.offset = offset;
3281         plane_state->main.x = src_x;
3282         plane_state->main.y = src_y;
3283
3284         return 0;
3285 }
3286
3287 static void i9xx_update_primary_plane(struct intel_plane *primary,
3288                                       const struct intel_crtc_state *crtc_state,
3289                                       const struct intel_plane_state *plane_state)
3290 {
3291         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3292         const struct drm_framebuffer *fb = plane_state->base.fb;
3293         enum plane plane = primary->plane;
3294         u32 linear_offset;
3295         u32 dspcntr = plane_state->ctl;
3296         i915_reg_t reg = DSPCNTR(plane);
3297         int x = plane_state->main.x;
3298         int y = plane_state->main.y;
3299         unsigned long irqflags;
3300         u32 dspaddr_offset;
3301
3302         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3303
3304         if (INTEL_GEN(dev_priv) >= 4)
3305                 dspaddr_offset = plane_state->main.offset;
3306         else
3307                 dspaddr_offset = linear_offset;
3308
3309         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3310
3311         if (INTEL_GEN(dev_priv) < 4) {
3312                 /* pipesrc and dspsize control the size that is scaled from,
3313                  * which should always be the user's requested size.
3314                  */
3315                 I915_WRITE_FW(DSPSIZE(plane),
3316                               ((crtc_state->pipe_src_h - 1) << 16) |
3317                               (crtc_state->pipe_src_w - 1));
3318                 I915_WRITE_FW(DSPPOS(plane), 0);
3319         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3320                 I915_WRITE_FW(PRIMSIZE(plane),
3321                               ((crtc_state->pipe_src_h - 1) << 16) |
3322                               (crtc_state->pipe_src_w - 1));
3323                 I915_WRITE_FW(PRIMPOS(plane), 0);
3324                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3325         }
3326
3327         I915_WRITE_FW(reg, dspcntr);
3328
3329         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3330         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3331                 I915_WRITE_FW(DSPSURF(plane),
3332                               intel_plane_ggtt_offset(plane_state) +
3333                               dspaddr_offset);
3334                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3335         } else if (INTEL_GEN(dev_priv) >= 4) {
3336                 I915_WRITE_FW(DSPSURF(plane),
3337                               intel_plane_ggtt_offset(plane_state) +
3338                               dspaddr_offset);
3339                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3340                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3341         } else {
3342                 I915_WRITE_FW(DSPADDR(plane),
3343                               intel_plane_ggtt_offset(plane_state) +
3344                               dspaddr_offset);
3345         }
3346         POSTING_READ_FW(reg);
3347
3348         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3349 }
3350
3351 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3352                                        struct intel_crtc *crtc)
3353 {
3354         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3355         enum plane plane = primary->plane;
3356         unsigned long irqflags;
3357
3358         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3359
3360         I915_WRITE_FW(DSPCNTR(plane), 0);
3361         if (INTEL_INFO(dev_priv)->gen >= 4)
3362                 I915_WRITE_FW(DSPSURF(plane), 0);
3363         else
3364                 I915_WRITE_FW(DSPADDR(plane), 0);
3365         POSTING_READ_FW(DSPCNTR(plane));
3366
3367         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3368 }
3369
3370 static u32
3371 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3372 {
3373         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3374                 return 64;
3375         else
3376                 return intel_tile_width_bytes(fb, plane);
3377 }
3378
3379 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3380 {
3381         struct drm_device *dev = intel_crtc->base.dev;
3382         struct drm_i915_private *dev_priv = to_i915(dev);
3383
3384         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3385         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3386         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3387 }
3388
3389 /*
3390  * This function detaches (aka. unbinds) unused scalers in hardware
3391  */
3392 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3393 {
3394         struct intel_crtc_scaler_state *scaler_state;
3395         int i;
3396
3397         scaler_state = &intel_crtc->config->scaler_state;
3398
3399         /* loop through and disable scalers that aren't in use */
3400         for (i = 0; i < intel_crtc->num_scalers; i++) {
3401                 if (!scaler_state->scalers[i].in_use)
3402                         skl_detach_scaler(intel_crtc, i);
3403         }
3404 }
3405
3406 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3407                      unsigned int rotation)
3408 {
3409         u32 stride;
3410
3411         if (plane >= fb->format->num_planes)
3412                 return 0;
3413
3414         stride = intel_fb_pitch(fb, plane, rotation);
3415
3416         /*
3417          * The stride is either expressed as a multiple of 64 bytes chunks for
3418          * linear buffers or in number of tiles for tiled buffers.
3419          */
3420         if (drm_rotation_90_or_270(rotation))
3421                 stride /= intel_tile_height(fb, plane);
3422         else
3423                 stride /= intel_fb_stride_alignment(fb, plane);
3424
3425         return stride;
3426 }
3427
3428 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3429 {
3430         switch (pixel_format) {
3431         case DRM_FORMAT_C8:
3432                 return PLANE_CTL_FORMAT_INDEXED;
3433         case DRM_FORMAT_RGB565:
3434                 return PLANE_CTL_FORMAT_RGB_565;
3435         case DRM_FORMAT_XBGR8888:
3436                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3437         case DRM_FORMAT_XRGB8888:
3438                 return PLANE_CTL_FORMAT_XRGB_8888;
3439         /*
3440          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3441          * to be already pre-multiplied. We need to add a knob (or a different
3442          * DRM_FORMAT) for user-space to configure that.
3443          */
3444         case DRM_FORMAT_ABGR8888:
3445                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3446                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3447         case DRM_FORMAT_ARGB8888:
3448                 return PLANE_CTL_FORMAT_XRGB_8888 |
3449                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3450         case DRM_FORMAT_XRGB2101010:
3451                 return PLANE_CTL_FORMAT_XRGB_2101010;
3452         case DRM_FORMAT_XBGR2101010:
3453                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3454         case DRM_FORMAT_YUYV:
3455                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3456         case DRM_FORMAT_YVYU:
3457                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3458         case DRM_FORMAT_UYVY:
3459                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3460         case DRM_FORMAT_VYUY:
3461                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3462         default:
3463                 MISSING_CASE(pixel_format);
3464         }
3465
3466         return 0;
3467 }
3468
3469 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3470 {
3471         switch (fb_modifier) {
3472         case DRM_FORMAT_MOD_LINEAR:
3473                 break;
3474         case I915_FORMAT_MOD_X_TILED:
3475                 return PLANE_CTL_TILED_X;
3476         case I915_FORMAT_MOD_Y_TILED:
3477                 return PLANE_CTL_TILED_Y;
3478         case I915_FORMAT_MOD_Y_TILED_CCS:
3479                 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3480         case I915_FORMAT_MOD_Yf_TILED:
3481                 return PLANE_CTL_TILED_YF;
3482         case I915_FORMAT_MOD_Yf_TILED_CCS:
3483                 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3484         default:
3485                 MISSING_CASE(fb_modifier);
3486         }
3487
3488         return 0;
3489 }
3490
3491 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3492 {
3493         switch (rotation) {
3494         case DRM_MODE_ROTATE_0:
3495                 break;
3496         /*
3497          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3498          * while i915 HW rotation is clockwise, thats why this swapping.
3499          */
3500         case DRM_MODE_ROTATE_90:
3501                 return PLANE_CTL_ROTATE_270;
3502         case DRM_MODE_ROTATE_180:
3503                 return PLANE_CTL_ROTATE_180;
3504         case DRM_MODE_ROTATE_270:
3505                 return PLANE_CTL_ROTATE_90;
3506         default:
3507                 MISSING_CASE(rotation);
3508         }
3509
3510         return 0;
3511 }
3512
3513 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3514                   const struct intel_plane_state *plane_state)
3515 {
3516         struct drm_i915_private *dev_priv =
3517                 to_i915(plane_state->base.plane->dev);
3518         const struct drm_framebuffer *fb = plane_state->base.fb;
3519         unsigned int rotation = plane_state->base.rotation;
3520         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3521         u32 plane_ctl;
3522
3523         plane_ctl = PLANE_CTL_ENABLE;
3524
3525         if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3526                 plane_ctl |=
3527                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3528                         PLANE_CTL_PIPE_CSC_ENABLE |
3529                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3530         }
3531
3532         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3533         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3534         plane_ctl |= skl_plane_ctl_rotation(rotation);
3535
3536         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3537                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3538         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3539                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3540
3541         return plane_ctl;
3542 }
3543
3544 static int
3545 __intel_display_resume(struct drm_device *dev,
3546                        struct drm_atomic_state *state,
3547                        struct drm_modeset_acquire_ctx *ctx)
3548 {
3549         struct drm_crtc_state *crtc_state;
3550         struct drm_crtc *crtc;
3551         int i, ret;
3552
3553         intel_modeset_setup_hw_state(dev, ctx);
3554         i915_redisable_vga(to_i915(dev));
3555
3556         if (!state)
3557                 return 0;
3558
3559         /*
3560          * We've duplicated the state, pointers to the old state are invalid.
3561          *
3562          * Don't attempt to use the old state until we commit the duplicated state.
3563          */
3564         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3565                 /*
3566                  * Force recalculation even if we restore
3567                  * current state. With fast modeset this may not result
3568                  * in a modeset when the state is compatible.
3569                  */
3570                 crtc_state->mode_changed = true;
3571         }
3572
3573         /* ignore any reset values/BIOS leftovers in the WM registers */
3574         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3575                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3576
3577         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3578
3579         WARN_ON(ret == -EDEADLK);
3580         return ret;
3581 }
3582
3583 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3584 {
3585         return intel_has_gpu_reset(dev_priv) &&
3586                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3587 }
3588
3589 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3590 {
3591         struct drm_device *dev = &dev_priv->drm;
3592         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3593         struct drm_atomic_state *state;
3594         int ret;
3595
3596
3597         /* reset doesn't touch the display */
3598         if (!i915_modparams.force_reset_modeset_test &&
3599             !gpu_reset_clobbers_display(dev_priv))
3600                 return;
3601
3602         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3603         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3604         wake_up_all(&dev_priv->gpu_error.wait_queue);
3605
3606         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3607                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3608                 i915_gem_set_wedged(dev_priv);
3609         }
3610
3611         /*
3612          * Need mode_config.mutex so that we don't
3613          * trample ongoing ->detect() and whatnot.
3614          */
3615         mutex_lock(&dev->mode_config.mutex);
3616         drm_modeset_acquire_init(ctx, 0);
3617         while (1) {
3618                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3619                 if (ret != -EDEADLK)
3620                         break;
3621
3622                 drm_modeset_backoff(ctx);
3623         }
3624         /*
3625          * Disabling the crtcs gracefully seems nicer. Also the
3626          * g33 docs say we should at least disable all the planes.
3627          */
3628         state = drm_atomic_helper_duplicate_state(dev, ctx);
3629         if (IS_ERR(state)) {
3630                 ret = PTR_ERR(state);
3631                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3632                 return;
3633         }
3634
3635         ret = drm_atomic_helper_disable_all(dev, ctx);
3636         if (ret) {
3637                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3638                 drm_atomic_state_put(state);
3639                 return;
3640         }
3641
3642         dev_priv->modeset_restore_state = state;
3643         state->acquire_ctx = ctx;
3644 }
3645
3646 void intel_finish_reset(struct drm_i915_private *dev_priv)
3647 {
3648         struct drm_device *dev = &dev_priv->drm;
3649         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3650         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3651         int ret;
3652
3653         /* reset doesn't touch the display */
3654         if (!i915_modparams.force_reset_modeset_test &&
3655             !gpu_reset_clobbers_display(dev_priv))
3656                 return;
3657
3658         if (!state)
3659                 goto unlock;
3660
3661         dev_priv->modeset_restore_state = NULL;
3662
3663         /* reset doesn't touch the display */
3664         if (!gpu_reset_clobbers_display(dev_priv)) {
3665                 /* for testing only restore the display */
3666                 ret = __intel_display_resume(dev, state, ctx);
3667                 if (ret)
3668                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3669         } else {
3670                 /*
3671                  * The display has been reset as well,
3672                  * so need a full re-initialization.
3673                  */
3674                 intel_runtime_pm_disable_interrupts(dev_priv);
3675                 intel_runtime_pm_enable_interrupts(dev_priv);
3676
3677                 intel_pps_unlock_regs_wa(dev_priv);
3678                 intel_modeset_init_hw(dev);
3679                 intel_init_clock_gating(dev_priv);
3680
3681                 spin_lock_irq(&dev_priv->irq_lock);
3682                 if (dev_priv->display.hpd_irq_setup)
3683                         dev_priv->display.hpd_irq_setup(dev_priv);
3684                 spin_unlock_irq(&dev_priv->irq_lock);
3685
3686                 ret = __intel_display_resume(dev, state, ctx);
3687                 if (ret)
3688                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3689
3690                 intel_hpd_init(dev_priv);
3691         }
3692
3693         drm_atomic_state_put(state);
3694 unlock:
3695         drm_modeset_drop_locks(ctx);
3696         drm_modeset_acquire_fini(ctx);
3697         mutex_unlock(&dev->mode_config.mutex);
3698
3699         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3700 }
3701
3702 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3703                                      const struct intel_crtc_state *new_crtc_state)
3704 {
3705         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3706         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3707
3708         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3709         crtc->base.mode = new_crtc_state->base.mode;
3710
3711         /*
3712          * Update pipe size and adjust fitter if needed: the reason for this is
3713          * that in compute_mode_changes we check the native mode (not the pfit
3714          * mode) to see if we can flip rather than do a full mode set. In the
3715          * fastboot case, we'll flip, but if we don't update the pipesrc and
3716          * pfit state, we'll end up with a big fb scanned out into the wrong
3717          * sized surface.
3718          */
3719
3720         I915_WRITE(PIPESRC(crtc->pipe),
3721                    ((new_crtc_state->pipe_src_w - 1) << 16) |
3722                    (new_crtc_state->pipe_src_h - 1));
3723
3724         /* on skylake this is done by detaching scalers */
3725         if (INTEL_GEN(dev_priv) >= 9) {
3726                 skl_detach_scalers(crtc);
3727
3728                 if (new_crtc_state->pch_pfit.enabled)
3729                         skylake_pfit_enable(crtc);
3730         } else if (HAS_PCH_SPLIT(dev_priv)) {
3731                 if (new_crtc_state->pch_pfit.enabled)
3732                         ironlake_pfit_enable(crtc);
3733                 else if (old_crtc_state->pch_pfit.enabled)
3734                         ironlake_pfit_disable(crtc, true);
3735         }
3736 }
3737
3738 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3739 {
3740         struct drm_device *dev = crtc->base.dev;
3741         struct drm_i915_private *dev_priv = to_i915(dev);
3742         int pipe = crtc->pipe;
3743         i915_reg_t reg;
3744         u32 temp;
3745
3746         /* enable normal train */
3747         reg = FDI_TX_CTL(pipe);
3748         temp = I915_READ(reg);
3749         if (IS_IVYBRIDGE(dev_priv)) {
3750                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3751                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3752         } else {
3753                 temp &= ~FDI_LINK_TRAIN_NONE;
3754                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3755         }
3756         I915_WRITE(reg, temp);
3757
3758         reg = FDI_RX_CTL(pipe);
3759         temp = I915_READ(reg);
3760         if (HAS_PCH_CPT(dev_priv)) {
3761                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3762                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3763         } else {
3764                 temp &= ~FDI_LINK_TRAIN_NONE;
3765                 temp |= FDI_LINK_TRAIN_NONE;
3766         }
3767         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3768
3769         /* wait one idle pattern time */
3770         POSTING_READ(reg);
3771         udelay(1000);
3772
3773         /* IVB wants error correction enabled */
3774         if (IS_IVYBRIDGE(dev_priv))
3775                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3776                            FDI_FE_ERRC_ENABLE);
3777 }
3778
3779 /* The FDI link training functions for ILK/Ibexpeak. */
3780 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3781                                     const struct intel_crtc_state *crtc_state)
3782 {
3783         struct drm_device *dev = crtc->base.dev;
3784         struct drm_i915_private *dev_priv = to_i915(dev);
3785         int pipe = crtc->pipe;
3786         i915_reg_t reg;
3787         u32 temp, tries;
3788
3789         /* FDI needs bits from pipe first */
3790         assert_pipe_enabled(dev_priv, pipe);
3791
3792         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3793            for train result */
3794         reg = FDI_RX_IMR(pipe);
3795         temp = I915_READ(reg);
3796         temp &= ~FDI_RX_SYMBOL_LOCK;
3797         temp &= ~FDI_RX_BIT_LOCK;
3798         I915_WRITE(reg, temp);
3799         I915_READ(reg);
3800         udelay(150);
3801
3802         /* enable CPU FDI TX and PCH FDI RX */
3803         reg = FDI_TX_CTL(pipe);
3804         temp = I915_READ(reg);
3805         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3806         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3807         temp &= ~FDI_LINK_TRAIN_NONE;
3808         temp |= FDI_LINK_TRAIN_PATTERN_1;
3809         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3810
3811         reg = FDI_RX_CTL(pipe);
3812         temp = I915_READ(reg);
3813         temp &= ~FDI_LINK_TRAIN_NONE;
3814         temp |= FDI_LINK_TRAIN_PATTERN_1;
3815         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3816
3817         POSTING_READ(reg);
3818         udelay(150);
3819
3820         /* Ironlake workaround, enable clock pointer after FDI enable*/
3821         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3822         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3823                    FDI_RX_PHASE_SYNC_POINTER_EN);
3824
3825         reg = FDI_RX_IIR(pipe);
3826         for (tries = 0; tries < 5; tries++) {
3827                 temp = I915_READ(reg);
3828                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3829
3830                 if ((temp & FDI_RX_BIT_LOCK)) {
3831                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3832                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3833                         break;
3834                 }
3835         }
3836         if (tries == 5)
3837                 DRM_ERROR("FDI train 1 fail!\n");
3838
3839         /* Train 2 */
3840         reg = FDI_TX_CTL(pipe);
3841         temp = I915_READ(reg);
3842         temp &= ~FDI_LINK_TRAIN_NONE;
3843         temp |= FDI_LINK_TRAIN_PATTERN_2;
3844         I915_WRITE(reg, temp);
3845
3846         reg = FDI_RX_CTL(pipe);
3847         temp = I915_READ(reg);
3848         temp &= ~FDI_LINK_TRAIN_NONE;
3849         temp |= FDI_LINK_TRAIN_PATTERN_2;
3850         I915_WRITE(reg, temp);
3851
3852         POSTING_READ(reg);
3853         udelay(150);
3854
3855         reg = FDI_RX_IIR(pipe);
3856         for (tries = 0; tries < 5; tries++) {
3857                 temp = I915_READ(reg);
3858                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3859
3860                 if (temp & FDI_RX_SYMBOL_LOCK) {
3861                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3862                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3863                         break;
3864                 }
3865         }
3866         if (tries == 5)
3867                 DRM_ERROR("FDI train 2 fail!\n");
3868
3869         DRM_DEBUG_KMS("FDI train done\n");
3870
3871 }
3872
3873 static const int snb_b_fdi_train_param[] = {
3874         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3875         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3876         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3877         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3878 };
3879
3880 /* The FDI link training functions for SNB/Cougarpoint. */
3881 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3882                                 const struct intel_crtc_state *crtc_state)
3883 {
3884         struct drm_device *dev = crtc->base.dev;
3885         struct drm_i915_private *dev_priv = to_i915(dev);
3886         int pipe = crtc->pipe;
3887         i915_reg_t reg;
3888         u32 temp, i, retry;
3889
3890         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3891            for train result */
3892         reg = FDI_RX_IMR(pipe);
3893         temp = I915_READ(reg);
3894         temp &= ~FDI_RX_SYMBOL_LOCK;
3895         temp &= ~FDI_RX_BIT_LOCK;
3896         I915_WRITE(reg, temp);
3897
3898         POSTING_READ(reg);
3899         udelay(150);
3900
3901         /* enable CPU FDI TX and PCH FDI RX */
3902         reg = FDI_TX_CTL(pipe);
3903         temp = I915_READ(reg);
3904         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3905         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3906         temp &= ~FDI_LINK_TRAIN_NONE;
3907         temp |= FDI_LINK_TRAIN_PATTERN_1;
3908         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3909         /* SNB-B */
3910         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3911         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3912
3913         I915_WRITE(FDI_RX_MISC(pipe),
3914                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3915
3916         reg = FDI_RX_CTL(pipe);
3917         temp = I915_READ(reg);
3918         if (HAS_PCH_CPT(dev_priv)) {
3919                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3920                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3921         } else {
3922                 temp &= ~FDI_LINK_TRAIN_NONE;
3923                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3924         }
3925         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3926
3927         POSTING_READ(reg);
3928         udelay(150);
3929
3930         for (i = 0; i < 4; i++) {
3931                 reg = FDI_TX_CTL(pipe);
3932                 temp = I915_READ(reg);
3933                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3934                 temp |= snb_b_fdi_train_param[i];
3935                 I915_WRITE(reg, temp);
3936
3937                 POSTING_READ(reg);
3938                 udelay(500);
3939
3940                 for (retry = 0; retry < 5; retry++) {
3941                         reg = FDI_RX_IIR(pipe);
3942                         temp = I915_READ(reg);
3943                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3944                         if (temp & FDI_RX_BIT_LOCK) {
3945                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3946                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3947                                 break;
3948                         }
3949                         udelay(50);
3950                 }
3951                 if (retry < 5)
3952                         break;
3953         }
3954         if (i == 4)
3955                 DRM_ERROR("FDI train 1 fail!\n");
3956
3957         /* Train 2 */
3958         reg = FDI_TX_CTL(pipe);
3959         temp = I915_READ(reg);
3960         temp &= ~FDI_LINK_TRAIN_NONE;
3961         temp |= FDI_LINK_TRAIN_PATTERN_2;
3962         if (IS_GEN6(dev_priv)) {
3963                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3964                 /* SNB-B */
3965                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3966         }
3967         I915_WRITE(reg, temp);
3968
3969         reg = FDI_RX_CTL(pipe);
3970         temp = I915_READ(reg);
3971         if (HAS_PCH_CPT(dev_priv)) {
3972                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3973                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3974         } else {
3975                 temp &= ~FDI_LINK_TRAIN_NONE;
3976                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3977         }
3978         I915_WRITE(reg, temp);
3979
3980         POSTING_READ(reg);
3981         udelay(150);
3982
3983         for (i = 0; i < 4; i++) {
3984                 reg = FDI_TX_CTL(pipe);
3985                 temp = I915_READ(reg);
3986                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3987                 temp |= snb_b_fdi_train_param[i];
3988                 I915_WRITE(reg, temp);
3989
3990                 POSTING_READ(reg);
3991                 udelay(500);
3992
3993                 for (retry = 0; retry < 5; retry++) {
3994                         reg = FDI_RX_IIR(pipe);
3995                         temp = I915_READ(reg);
3996                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3997                         if (temp & FDI_RX_SYMBOL_LOCK) {
3998                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3999                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4000                                 break;
4001                         }
4002                         udelay(50);
4003                 }
4004                 if (retry < 5)
4005                         break;
4006         }
4007         if (i == 4)
4008                 DRM_ERROR("FDI train 2 fail!\n");
4009
4010         DRM_DEBUG_KMS("FDI train done.\n");
4011 }
4012
4013 /* Manual link training for Ivy Bridge A0 parts */
4014 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4015                                       const struct intel_crtc_state *crtc_state)
4016 {
4017         struct drm_device *dev = crtc->base.dev;
4018         struct drm_i915_private *dev_priv = to_i915(dev);
4019         int pipe = crtc->pipe;
4020         i915_reg_t reg;
4021         u32 temp, i, j;
4022
4023         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4024            for train result */
4025         reg = FDI_RX_IMR(pipe);
4026         temp = I915_READ(reg);
4027         temp &= ~FDI_RX_SYMBOL_LOCK;
4028         temp &= ~FDI_RX_BIT_LOCK;
4029         I915_WRITE(reg, temp);
4030
4031         POSTING_READ(reg);
4032         udelay(150);
4033
4034         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4035                       I915_READ(FDI_RX_IIR(pipe)));
4036
4037         /* Try each vswing and preemphasis setting twice before moving on */
4038         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4039                 /* disable first in case we need to retry */
4040                 reg = FDI_TX_CTL(pipe);
4041                 temp = I915_READ(reg);
4042                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4043                 temp &= ~FDI_TX_ENABLE;
4044                 I915_WRITE(reg, temp);
4045
4046                 reg = FDI_RX_CTL(pipe);
4047                 temp = I915_READ(reg);
4048                 temp &= ~FDI_LINK_TRAIN_AUTO;
4049                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4050                 temp &= ~FDI_RX_ENABLE;
4051                 I915_WRITE(reg, temp);
4052
4053                 /* enable CPU FDI TX and PCH FDI RX */
4054                 reg = FDI_TX_CTL(pipe);
4055                 temp = I915_READ(reg);
4056                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4057                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4058                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4059                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4060                 temp |= snb_b_fdi_train_param[j/2];
4061                 temp |= FDI_COMPOSITE_SYNC;
4062                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4063
4064                 I915_WRITE(FDI_RX_MISC(pipe),
4065                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4066
4067                 reg = FDI_RX_CTL(pipe);
4068                 temp = I915_READ(reg);
4069                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4070                 temp |= FDI_COMPOSITE_SYNC;
4071                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4072
4073                 POSTING_READ(reg);
4074                 udelay(1); /* should be 0.5us */
4075
4076                 for (i = 0; i < 4; i++) {
4077                         reg = FDI_RX_IIR(pipe);
4078                         temp = I915_READ(reg);
4079                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4080
4081                         if (temp & FDI_RX_BIT_LOCK ||
4082                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4083                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4084                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4085                                               i);
4086                                 break;
4087                         }
4088                         udelay(1); /* should be 0.5us */
4089                 }
4090                 if (i == 4) {
4091                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4092                         continue;
4093                 }
4094
4095                 /* Train 2 */
4096                 reg = FDI_TX_CTL(pipe);
4097                 temp = I915_READ(reg);
4098                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4099                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4100                 I915_WRITE(reg, temp);
4101
4102                 reg = FDI_RX_CTL(pipe);
4103                 temp = I915_READ(reg);
4104                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4105                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4106                 I915_WRITE(reg, temp);
4107
4108                 POSTING_READ(reg);
4109                 udelay(2); /* should be 1.5us */
4110
4111                 for (i = 0; i < 4; i++) {
4112                         reg = FDI_RX_IIR(pipe);
4113                         temp = I915_READ(reg);
4114                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4115
4116                         if (temp & FDI_RX_SYMBOL_LOCK ||
4117                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4118                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4119                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4120                                               i);
4121                                 goto train_done;
4122                         }
4123                         udelay(2); /* should be 1.5us */
4124                 }
4125                 if (i == 4)
4126                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4127         }
4128
4129 train_done:
4130         DRM_DEBUG_KMS("FDI train done.\n");
4131 }
4132
4133 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4134 {
4135         struct drm_device *dev = intel_crtc->base.dev;
4136         struct drm_i915_private *dev_priv = to_i915(dev);
4137         int pipe = intel_crtc->pipe;
4138         i915_reg_t reg;
4139         u32 temp;
4140
4141         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4142         reg = FDI_RX_CTL(pipe);
4143         temp = I915_READ(reg);
4144         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4145         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4146         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4147         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4148
4149         POSTING_READ(reg);
4150         udelay(200);
4151
4152         /* Switch from Rawclk to PCDclk */
4153         temp = I915_READ(reg);
4154         I915_WRITE(reg, temp | FDI_PCDCLK);
4155
4156         POSTING_READ(reg);
4157         udelay(200);
4158
4159         /* Enable CPU FDI TX PLL, always on for Ironlake */
4160         reg = FDI_TX_CTL(pipe);
4161         temp = I915_READ(reg);
4162         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4163                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4164
4165                 POSTING_READ(reg);
4166                 udelay(100);
4167         }
4168 }
4169
4170 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4171 {
4172         struct drm_device *dev = intel_crtc->base.dev;
4173         struct drm_i915_private *dev_priv = to_i915(dev);
4174         int pipe = intel_crtc->pipe;
4175         i915_reg_t reg;
4176         u32 temp;
4177
4178         /* Switch from PCDclk to Rawclk */
4179         reg = FDI_RX_CTL(pipe);
4180         temp = I915_READ(reg);
4181         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4182
4183         /* Disable CPU FDI TX PLL */
4184         reg = FDI_TX_CTL(pipe);
4185         temp = I915_READ(reg);
4186         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4187
4188         POSTING_READ(reg);
4189         udelay(100);
4190
4191         reg = FDI_RX_CTL(pipe);
4192         temp = I915_READ(reg);
4193         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4194
4195         /* Wait for the clocks to turn off. */
4196         POSTING_READ(reg);
4197         udelay(100);
4198 }
4199
4200 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4201 {
4202         struct drm_device *dev = crtc->dev;
4203         struct drm_i915_private *dev_priv = to_i915(dev);
4204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4205         int pipe = intel_crtc->pipe;
4206         i915_reg_t reg;
4207         u32 temp;
4208
4209         /* disable CPU FDI tx and PCH FDI rx */
4210         reg = FDI_TX_CTL(pipe);
4211         temp = I915_READ(reg);
4212         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4213         POSTING_READ(reg);
4214
4215         reg = FDI_RX_CTL(pipe);
4216         temp = I915_READ(reg);
4217         temp &= ~(0x7 << 16);
4218         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4219         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4220
4221         POSTING_READ(reg);
4222         udelay(100);
4223
4224         /* Ironlake workaround, disable clock pointer after downing FDI */
4225         if (HAS_PCH_IBX(dev_priv))
4226                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4227
4228         /* still set train pattern 1 */
4229         reg = FDI_TX_CTL(pipe);
4230         temp = I915_READ(reg);
4231         temp &= ~FDI_LINK_TRAIN_NONE;
4232         temp |= FDI_LINK_TRAIN_PATTERN_1;
4233         I915_WRITE(reg, temp);
4234
4235         reg = FDI_RX_CTL(pipe);
4236         temp = I915_READ(reg);
4237         if (HAS_PCH_CPT(dev_priv)) {
4238                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4239                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4240         } else {
4241                 temp &= ~FDI_LINK_TRAIN_NONE;
4242                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4243         }
4244         /* BPC in FDI rx is consistent with that in PIPECONF */
4245         temp &= ~(0x07 << 16);
4246         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4247         I915_WRITE(reg, temp);
4248
4249         POSTING_READ(reg);
4250         udelay(100);
4251 }
4252
4253 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4254 {
4255         struct drm_crtc *crtc;
4256         bool cleanup_done;
4257
4258         drm_for_each_crtc(crtc, &dev_priv->drm) {
4259                 struct drm_crtc_commit *commit;
4260                 spin_lock(&crtc->commit_lock);
4261                 commit = list_first_entry_or_null(&crtc->commit_list,
4262                                                   struct drm_crtc_commit, commit_entry);
4263                 cleanup_done = commit ?
4264                         try_wait_for_completion(&commit->cleanup_done) : true;
4265                 spin_unlock(&crtc->commit_lock);
4266
4267                 if (cleanup_done)
4268                         continue;
4269
4270                 drm_crtc_wait_one_vblank(crtc);
4271
4272                 return true;
4273         }
4274
4275         return false;
4276 }
4277
4278 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4279 {
4280         u32 temp;
4281
4282         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4283
4284         mutex_lock(&dev_priv->sb_lock);
4285
4286         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4287         temp |= SBI_SSCCTL_DISABLE;
4288         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4289
4290         mutex_unlock(&dev_priv->sb_lock);
4291 }
4292
4293 /* Program iCLKIP clock to the desired frequency */
4294 static void lpt_program_iclkip(struct intel_crtc *crtc)
4295 {
4296         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4297         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4298         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4299         u32 temp;
4300
4301         lpt_disable_iclkip(dev_priv);
4302
4303         /* The iCLK virtual clock root frequency is in MHz,
4304          * but the adjusted_mode->crtc_clock in in KHz. To get the
4305          * divisors, it is necessary to divide one by another, so we
4306          * convert the virtual clock precision to KHz here for higher
4307          * precision.
4308          */
4309         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4310                 u32 iclk_virtual_root_freq = 172800 * 1000;
4311                 u32 iclk_pi_range = 64;
4312                 u32 desired_divisor;
4313
4314                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4315                                                     clock << auxdiv);
4316                 divsel = (desired_divisor / iclk_pi_range) - 2;
4317                 phaseinc = desired_divisor % iclk_pi_range;
4318
4319                 /*
4320                  * Near 20MHz is a corner case which is
4321                  * out of range for the 7-bit divisor
4322                  */
4323                 if (divsel <= 0x7f)
4324                         break;
4325         }
4326
4327         /* This should not happen with any sane values */
4328         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4329                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4330         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4331                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4332
4333         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4334                         clock,
4335                         auxdiv,
4336                         divsel,
4337                         phasedir,
4338                         phaseinc);
4339
4340         mutex_lock(&dev_priv->sb_lock);
4341
4342         /* Program SSCDIVINTPHASE6 */
4343         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4344         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4345         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4346         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4347         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4348         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4349         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4350         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4351
4352         /* Program SSCAUXDIV */
4353         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4354         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4355         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4356         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4357
4358         /* Enable modulator and associated divider */
4359         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4360         temp &= ~SBI_SSCCTL_DISABLE;
4361         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4362
4363         mutex_unlock(&dev_priv->sb_lock);
4364
4365         /* Wait for initialization time */
4366         udelay(24);
4367
4368         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4369 }
4370
4371 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4372 {
4373         u32 divsel, phaseinc, auxdiv;
4374         u32 iclk_virtual_root_freq = 172800 * 1000;
4375         u32 iclk_pi_range = 64;
4376         u32 desired_divisor;
4377         u32 temp;
4378
4379         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4380                 return 0;
4381
4382         mutex_lock(&dev_priv->sb_lock);
4383
4384         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4385         if (temp & SBI_SSCCTL_DISABLE) {
4386                 mutex_unlock(&dev_priv->sb_lock);
4387                 return 0;
4388         }
4389
4390         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4391         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4392                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4393         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4394                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4395
4396         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4397         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4398                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4399
4400         mutex_unlock(&dev_priv->sb_lock);
4401
4402         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4403
4404         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4405                                  desired_divisor << auxdiv);
4406 }
4407
4408 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4409                                                 enum pipe pch_transcoder)
4410 {
4411         struct drm_device *dev = crtc->base.dev;
4412         struct drm_i915_private *dev_priv = to_i915(dev);
4413         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4414
4415         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4416                    I915_READ(HTOTAL(cpu_transcoder)));
4417         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4418                    I915_READ(HBLANK(cpu_transcoder)));
4419         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4420                    I915_READ(HSYNC(cpu_transcoder)));
4421
4422         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4423                    I915_READ(VTOTAL(cpu_transcoder)));
4424         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4425                    I915_READ(VBLANK(cpu_transcoder)));
4426         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4427                    I915_READ(VSYNC(cpu_transcoder)));
4428         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4429                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4430 }
4431
4432 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4433 {
4434         struct drm_i915_private *dev_priv = to_i915(dev);
4435         uint32_t temp;
4436
4437         temp = I915_READ(SOUTH_CHICKEN1);
4438         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4439                 return;
4440
4441         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4442         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4443
4444         temp &= ~FDI_BC_BIFURCATION_SELECT;
4445         if (enable)
4446                 temp |= FDI_BC_BIFURCATION_SELECT;
4447
4448         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4449         I915_WRITE(SOUTH_CHICKEN1, temp);
4450         POSTING_READ(SOUTH_CHICKEN1);
4451 }
4452
4453 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4454 {
4455         struct drm_device *dev = intel_crtc->base.dev;
4456
4457         switch (intel_crtc->pipe) {
4458         case PIPE_A:
4459                 break;
4460         case PIPE_B:
4461                 if (intel_crtc->config->fdi_lanes > 2)
4462                         cpt_set_fdi_bc_bifurcation(dev, false);
4463                 else
4464                         cpt_set_fdi_bc_bifurcation(dev, true);
4465
4466                 break;
4467         case PIPE_C:
4468                 cpt_set_fdi_bc_bifurcation(dev, true);
4469
4470                 break;
4471         default:
4472                 BUG();
4473         }
4474 }
4475
4476 /* Return which DP Port should be selected for Transcoder DP control */
4477 static enum port
4478 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4479 {
4480         struct drm_device *dev = crtc->base.dev;
4481         struct intel_encoder *encoder;
4482
4483         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4484                 if (encoder->type == INTEL_OUTPUT_DP ||
4485                     encoder->type == INTEL_OUTPUT_EDP)
4486                         return enc_to_dig_port(&encoder->base)->port;
4487         }
4488
4489         return -1;
4490 }
4491
4492 /*
4493  * Enable PCH resources required for PCH ports:
4494  *   - PCH PLLs
4495  *   - FDI training & RX/TX
4496  *   - update transcoder timings
4497  *   - DP transcoding bits
4498  *   - transcoder
4499  */
4500 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4501 {
4502         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4503         struct drm_device *dev = crtc->base.dev;
4504         struct drm_i915_private *dev_priv = to_i915(dev);
4505         int pipe = crtc->pipe;
4506         u32 temp;
4507
4508         assert_pch_transcoder_disabled(dev_priv, pipe);
4509
4510         if (IS_IVYBRIDGE(dev_priv))
4511                 ivybridge_update_fdi_bc_bifurcation(crtc);
4512
4513         /* Write the TU size bits before fdi link training, so that error
4514          * detection works. */
4515         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4516                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4517
4518         /* For PCH output, training FDI link */
4519         dev_priv->display.fdi_link_train(crtc, crtc_state);
4520
4521         /* We need to program the right clock selection before writing the pixel
4522          * mutliplier into the DPLL. */
4523         if (HAS_PCH_CPT(dev_priv)) {
4524                 u32 sel;
4525
4526                 temp = I915_READ(PCH_DPLL_SEL);
4527                 temp |= TRANS_DPLL_ENABLE(pipe);
4528                 sel = TRANS_DPLLB_SEL(pipe);
4529                 if (crtc_state->shared_dpll ==
4530                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4531                         temp |= sel;
4532                 else
4533                         temp &= ~sel;
4534                 I915_WRITE(PCH_DPLL_SEL, temp);
4535         }
4536
4537         /* XXX: pch pll's can be enabled any time before we enable the PCH
4538          * transcoder, and we actually should do this to not upset any PCH
4539          * transcoder that already use the clock when we share it.
4540          *
4541          * Note that enable_shared_dpll tries to do the right thing, but
4542          * get_shared_dpll unconditionally resets the pll - we need that to have
4543          * the right LVDS enable sequence. */
4544         intel_enable_shared_dpll(crtc);
4545
4546         /* set transcoder timing, panel must allow it */
4547         assert_panel_unlocked(dev_priv, pipe);
4548         ironlake_pch_transcoder_set_timings(crtc, pipe);
4549
4550         intel_fdi_normal_train(crtc);
4551
4552         /* For PCH DP, enable TRANS_DP_CTL */
4553         if (HAS_PCH_CPT(dev_priv) &&
4554             intel_crtc_has_dp_encoder(crtc_state)) {
4555                 const struct drm_display_mode *adjusted_mode =
4556                         &crtc_state->base.adjusted_mode;
4557                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4558                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4559                 temp = I915_READ(reg);
4560                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4561                           TRANS_DP_SYNC_MASK |
4562                           TRANS_DP_BPC_MASK);
4563                 temp |= TRANS_DP_OUTPUT_ENABLE;
4564                 temp |= bpc << 9; /* same format but at 11:9 */
4565
4566                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4567                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4568                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4569                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4570
4571                 switch (intel_trans_dp_port_sel(crtc)) {
4572                 case PORT_B:
4573                         temp |= TRANS_DP_PORT_SEL_B;
4574                         break;
4575                 case PORT_C:
4576                         temp |= TRANS_DP_PORT_SEL_C;
4577                         break;
4578                 case PORT_D:
4579                         temp |= TRANS_DP_PORT_SEL_D;
4580                         break;
4581                 default:
4582                         BUG();
4583                 }
4584
4585                 I915_WRITE(reg, temp);
4586         }
4587
4588         ironlake_enable_pch_transcoder(dev_priv, pipe);
4589 }
4590
4591 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4592 {
4593         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4594         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4595         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4596
4597         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4598
4599         lpt_program_iclkip(crtc);
4600
4601         /* Set transcoder timing. */
4602         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4603
4604         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4605 }
4606
4607 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4608 {
4609         struct drm_i915_private *dev_priv = to_i915(dev);
4610         i915_reg_t dslreg = PIPEDSL(pipe);
4611         u32 temp;
4612
4613         temp = I915_READ(dslreg);
4614         udelay(500);
4615         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4616                 if (wait_for(I915_READ(dslreg) != temp, 5))
4617                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4618         }
4619 }
4620
4621 static int
4622 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4623                   unsigned int scaler_user, int *scaler_id,
4624                   int src_w, int src_h, int dst_w, int dst_h)
4625 {
4626         struct intel_crtc_scaler_state *scaler_state =
4627                 &crtc_state->scaler_state;
4628         struct intel_crtc *intel_crtc =
4629                 to_intel_crtc(crtc_state->base.crtc);
4630         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4631         const struct drm_display_mode *adjusted_mode =
4632                 &crtc_state->base.adjusted_mode;
4633         int need_scaling;
4634
4635         /*
4636          * Src coordinates are already rotated by 270 degrees for
4637          * the 90/270 degree plane rotation cases (to match the
4638          * GTT mapping), hence no need to account for rotation here.
4639          */
4640         need_scaling = src_w != dst_w || src_h != dst_h;
4641
4642         if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4643                 need_scaling = true;
4644
4645         /*
4646          * Scaling/fitting not supported in IF-ID mode in GEN9+
4647          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4648          * Once NV12 is enabled, handle it here while allocating scaler
4649          * for NV12.
4650          */
4651         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4652             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4653                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4654                 return -EINVAL;
4655         }
4656
4657         /*
4658          * if plane is being disabled or scaler is no more required or force detach
4659          *  - free scaler binded to this plane/crtc
4660          *  - in order to do this, update crtc->scaler_usage
4661          *
4662          * Here scaler state in crtc_state is set free so that
4663          * scaler can be assigned to other user. Actual register
4664          * update to free the scaler is done in plane/panel-fit programming.
4665          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4666          */
4667         if (force_detach || !need_scaling) {
4668                 if (*scaler_id >= 0) {
4669                         scaler_state->scaler_users &= ~(1 << scaler_user);
4670                         scaler_state->scalers[*scaler_id].in_use = 0;
4671
4672                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4673                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4674                                 intel_crtc->pipe, scaler_user, *scaler_id,
4675                                 scaler_state->scaler_users);
4676                         *scaler_id = -1;
4677                 }
4678                 return 0;
4679         }
4680
4681         /* range checks */
4682         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4683                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4684
4685                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4686                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4687                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4688                         "size is out of scaler range\n",
4689                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4690                 return -EINVAL;
4691         }
4692
4693         /* mark this plane as a scaler user in crtc_state */
4694         scaler_state->scaler_users |= (1 << scaler_user);
4695         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4696                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4697                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4698                 scaler_state->scaler_users);
4699
4700         return 0;
4701 }
4702
4703 /**
4704  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4705  *
4706  * @state: crtc's scaler state
4707  *
4708  * Return
4709  *     0 - scaler_usage updated successfully
4710  *    error - requested scaling cannot be supported or other error condition
4711  */
4712 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4713 {
4714         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4715
4716         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4717                 &state->scaler_state.scaler_id,
4718                 state->pipe_src_w, state->pipe_src_h,
4719                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4720 }
4721
4722 /**
4723  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4724  *
4725  * @state: crtc's scaler state
4726  * @plane_state: atomic plane state to update
4727  *
4728  * Return
4729  *     0 - scaler_usage updated successfully
4730  *    error - requested scaling cannot be supported or other error condition
4731  */
4732 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4733                                    struct intel_plane_state *plane_state)
4734 {
4735
4736         struct intel_plane *intel_plane =
4737                 to_intel_plane(plane_state->base.plane);
4738         struct drm_framebuffer *fb = plane_state->base.fb;
4739         int ret;
4740
4741         bool force_detach = !fb || !plane_state->base.visible;
4742
4743         ret = skl_update_scaler(crtc_state, force_detach,
4744                                 drm_plane_index(&intel_plane->base),
4745                                 &plane_state->scaler_id,
4746                                 drm_rect_width(&plane_state->base.src) >> 16,
4747                                 drm_rect_height(&plane_state->base.src) >> 16,
4748                                 drm_rect_width(&plane_state->base.dst),
4749                                 drm_rect_height(&plane_state->base.dst));
4750
4751         if (ret || plane_state->scaler_id < 0)
4752                 return ret;
4753
4754         /* check colorkey */
4755         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4756                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4757                               intel_plane->base.base.id,
4758                               intel_plane->base.name);
4759                 return -EINVAL;
4760         }
4761
4762         /* Check src format */
4763         switch (fb->format->format) {
4764         case DRM_FORMAT_RGB565:
4765         case DRM_FORMAT_XBGR8888:
4766         case DRM_FORMAT_XRGB8888:
4767         case DRM_FORMAT_ABGR8888:
4768         case DRM_FORMAT_ARGB8888:
4769         case DRM_FORMAT_XRGB2101010:
4770         case DRM_FORMAT_XBGR2101010:
4771         case DRM_FORMAT_YUYV:
4772         case DRM_FORMAT_YVYU:
4773         case DRM_FORMAT_UYVY:
4774         case DRM_FORMAT_VYUY:
4775                 break;
4776         default:
4777                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4778                               intel_plane->base.base.id, intel_plane->base.name,
4779                               fb->base.id, fb->format->format);
4780                 return -EINVAL;
4781         }
4782
4783         return 0;
4784 }
4785
4786 static void skylake_scaler_disable(struct intel_crtc *crtc)
4787 {
4788         int i;
4789
4790         for (i = 0; i < crtc->num_scalers; i++)
4791                 skl_detach_scaler(crtc, i);
4792 }
4793
4794 static void skylake_pfit_enable(struct intel_crtc *crtc)
4795 {
4796         struct drm_device *dev = crtc->base.dev;
4797         struct drm_i915_private *dev_priv = to_i915(dev);
4798         int pipe = crtc->pipe;
4799         struct intel_crtc_scaler_state *scaler_state =
4800                 &crtc->config->scaler_state;
4801
4802         if (crtc->config->pch_pfit.enabled) {
4803                 int id;
4804
4805                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4806                         return;
4807
4808                 id = scaler_state->scaler_id;
4809                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4810                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4811                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4812                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4813         }
4814 }
4815
4816 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4817 {
4818         struct drm_device *dev = crtc->base.dev;
4819         struct drm_i915_private *dev_priv = to_i915(dev);
4820         int pipe = crtc->pipe;
4821
4822         if (crtc->config->pch_pfit.enabled) {
4823                 /* Force use of hard-coded filter coefficients
4824                  * as some pre-programmed values are broken,
4825                  * e.g. x201.
4826                  */
4827                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4828                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4829                                                  PF_PIPE_SEL_IVB(pipe));
4830                 else
4831                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4832                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4833                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4834         }
4835 }
4836
4837 void hsw_enable_ips(struct intel_crtc *crtc)
4838 {
4839         struct drm_device *dev = crtc->base.dev;
4840         struct drm_i915_private *dev_priv = to_i915(dev);
4841
4842         if (!crtc->config->ips_enabled)
4843                 return;
4844
4845         /*
4846          * We can only enable IPS after we enable a plane and wait for a vblank
4847          * This function is called from post_plane_update, which is run after
4848          * a vblank wait.
4849          */
4850
4851         assert_plane_enabled(dev_priv, crtc->plane);
4852         if (IS_BROADWELL(dev_priv)) {
4853                 mutex_lock(&dev_priv->pcu_lock);
4854                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4855                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
4856                 mutex_unlock(&dev_priv->pcu_lock);
4857                 /* Quoting Art Runyan: "its not safe to expect any particular
4858                  * value in IPS_CTL bit 31 after enabling IPS through the
4859                  * mailbox." Moreover, the mailbox may return a bogus state,
4860                  * so we need to just enable it and continue on.
4861                  */
4862         } else {
4863                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4864                 /* The bit only becomes 1 in the next vblank, so this wait here
4865                  * is essentially intel_wait_for_vblank. If we don't have this
4866                  * and don't wait for vblanks until the end of crtc_enable, then
4867                  * the HW state readout code will complain that the expected
4868                  * IPS_CTL value is not the one we read. */
4869                 if (intel_wait_for_register(dev_priv,
4870                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4871                                             50))
4872                         DRM_ERROR("Timed out waiting for IPS enable\n");
4873         }
4874 }
4875
4876 void hsw_disable_ips(struct intel_crtc *crtc)
4877 {
4878         struct drm_device *dev = crtc->base.dev;
4879         struct drm_i915_private *dev_priv = to_i915(dev);
4880
4881         if (!crtc->config->ips_enabled)
4882                 return;
4883
4884         assert_plane_enabled(dev_priv, crtc->plane);
4885         if (IS_BROADWELL(dev_priv)) {
4886                 mutex_lock(&dev_priv->pcu_lock);
4887                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4888                 mutex_unlock(&dev_priv->pcu_lock);
4889                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4890                 if (intel_wait_for_register(dev_priv,
4891                                             IPS_CTL, IPS_ENABLE, 0,
4892                                             42))
4893                         DRM_ERROR("Timed out waiting for IPS disable\n");
4894         } else {
4895                 I915_WRITE(IPS_CTL, 0);
4896                 POSTING_READ(IPS_CTL);
4897         }
4898
4899         /* We need to wait for a vblank before we can disable the plane. */
4900         intel_wait_for_vblank(dev_priv, crtc->pipe);
4901 }
4902
4903 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4904 {
4905         if (intel_crtc->overlay) {
4906                 struct drm_device *dev = intel_crtc->base.dev;
4907
4908                 mutex_lock(&dev->struct_mutex);
4909                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4910                 mutex_unlock(&dev->struct_mutex);
4911         }
4912
4913         /* Let userspace switch the overlay on again. In most cases userspace
4914          * has to recompute where to put it anyway.
4915          */
4916 }
4917
4918 /**
4919  * intel_post_enable_primary - Perform operations after enabling primary plane
4920  * @crtc: the CRTC whose primary plane was just enabled
4921  *
4922  * Performs potentially sleeping operations that must be done after the primary
4923  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4924  * called due to an explicit primary plane update, or due to an implicit
4925  * re-enable that is caused when a sprite plane is updated to no longer
4926  * completely hide the primary plane.
4927  */
4928 static void
4929 intel_post_enable_primary(struct drm_crtc *crtc)
4930 {
4931         struct drm_device *dev = crtc->dev;
4932         struct drm_i915_private *dev_priv = to_i915(dev);
4933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4934         int pipe = intel_crtc->pipe;
4935
4936         /*
4937          * FIXME IPS should be fine as long as one plane is
4938          * enabled, but in practice it seems to have problems
4939          * when going from primary only to sprite only and vice
4940          * versa.
4941          */
4942         hsw_enable_ips(intel_crtc);
4943
4944         /*
4945          * Gen2 reports pipe underruns whenever all planes are disabled.
4946          * So don't enable underrun reporting before at least some planes
4947          * are enabled.
4948          * FIXME: Need to fix the logic to work when we turn off all planes
4949          * but leave the pipe running.
4950          */
4951         if (IS_GEN2(dev_priv))
4952                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4953
4954         /* Underruns don't always raise interrupts, so check manually. */
4955         intel_check_cpu_fifo_underruns(dev_priv);
4956         intel_check_pch_fifo_underruns(dev_priv);
4957 }
4958
4959 /* FIXME move all this to pre_plane_update() with proper state tracking */
4960 static void
4961 intel_pre_disable_primary(struct drm_crtc *crtc)
4962 {
4963         struct drm_device *dev = crtc->dev;
4964         struct drm_i915_private *dev_priv = to_i915(dev);
4965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4966         int pipe = intel_crtc->pipe;
4967
4968         /*
4969          * Gen2 reports pipe underruns whenever all planes are disabled.
4970          * So diasble underrun reporting before all the planes get disabled.
4971          * FIXME: Need to fix the logic to work when we turn off all planes
4972          * but leave the pipe running.
4973          */
4974         if (IS_GEN2(dev_priv))
4975                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4976
4977         /*
4978          * FIXME IPS should be fine as long as one plane is
4979          * enabled, but in practice it seems to have problems
4980          * when going from primary only to sprite only and vice
4981          * versa.
4982          */
4983         hsw_disable_ips(intel_crtc);
4984 }
4985
4986 /* FIXME get rid of this and use pre_plane_update */
4987 static void
4988 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4989 {
4990         struct drm_device *dev = crtc->dev;
4991         struct drm_i915_private *dev_priv = to_i915(dev);
4992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993         int pipe = intel_crtc->pipe;
4994
4995         intel_pre_disable_primary(crtc);
4996
4997         /*
4998          * Vblank time updates from the shadow to live plane control register
4999          * are blocked if the memory self-refresh mode is active at that
5000          * moment. So to make sure the plane gets truly disabled, disable
5001          * first the self-refresh mode. The self-refresh enable bit in turn
5002          * will be checked/applied by the HW only at the next frame start
5003          * event which is after the vblank start event, so we need to have a
5004          * wait-for-vblank between disabling the plane and the pipe.
5005          */
5006         if (HAS_GMCH_DISPLAY(dev_priv) &&
5007             intel_set_memory_cxsr(dev_priv, false))
5008                 intel_wait_for_vblank(dev_priv, pipe);
5009 }
5010
5011 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5012 {
5013         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5014         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5015         struct intel_crtc_state *pipe_config =
5016                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5017                                                 crtc);
5018         struct drm_plane *primary = crtc->base.primary;
5019         struct drm_plane_state *old_pri_state =
5020                 drm_atomic_get_existing_plane_state(old_state, primary);
5021
5022         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5023
5024         if (pipe_config->update_wm_post && pipe_config->base.active)
5025                 intel_update_watermarks(crtc);
5026
5027         if (old_pri_state) {
5028                 struct intel_plane_state *primary_state =
5029                         intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5030                                                          to_intel_plane(primary));
5031                 struct intel_plane_state *old_primary_state =
5032                         to_intel_plane_state(old_pri_state);
5033
5034                 intel_fbc_post_update(crtc);
5035
5036                 if (primary_state->base.visible &&
5037                     (needs_modeset(&pipe_config->base) ||
5038                      !old_primary_state->base.visible))
5039                         intel_post_enable_primary(&crtc->base);
5040         }
5041 }
5042
5043 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5044                                    struct intel_crtc_state *pipe_config)
5045 {
5046         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5047         struct drm_device *dev = crtc->base.dev;
5048         struct drm_i915_private *dev_priv = to_i915(dev);
5049         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5050         struct drm_plane *primary = crtc->base.primary;
5051         struct drm_plane_state *old_pri_state =
5052                 drm_atomic_get_existing_plane_state(old_state, primary);
5053         bool modeset = needs_modeset(&pipe_config->base);
5054         struct intel_atomic_state *old_intel_state =
5055                 to_intel_atomic_state(old_state);
5056
5057         if (old_pri_state) {
5058                 struct intel_plane_state *primary_state =
5059                         intel_atomic_get_new_plane_state(old_intel_state,
5060                                                          to_intel_plane(primary));
5061                 struct intel_plane_state *old_primary_state =
5062                         to_intel_plane_state(old_pri_state);
5063
5064                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5065
5066                 if (old_primary_state->base.visible &&
5067                     (modeset || !primary_state->base.visible))
5068                         intel_pre_disable_primary(&crtc->base);
5069         }
5070
5071         /*
5072          * Vblank time updates from the shadow to live plane control register
5073          * are blocked if the memory self-refresh mode is active at that
5074          * moment. So to make sure the plane gets truly disabled, disable
5075          * first the self-refresh mode. The self-refresh enable bit in turn
5076          * will be checked/applied by the HW only at the next frame start
5077          * event which is after the vblank start event, so we need to have a
5078          * wait-for-vblank between disabling the plane and the pipe.
5079          */
5080         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5081             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5082                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5083
5084         /*
5085          * IVB workaround: must disable low power watermarks for at least
5086          * one frame before enabling scaling.  LP watermarks can be re-enabled
5087          * when scaling is disabled.
5088          *
5089          * WaCxSRDisabledForSpriteScaling:ivb
5090          */
5091         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5092                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5093
5094         /*
5095          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5096          * watermark programming here.
5097          */
5098         if (needs_modeset(&pipe_config->base))
5099                 return;
5100
5101         /*
5102          * For platforms that support atomic watermarks, program the
5103          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5104          * will be the intermediate values that are safe for both pre- and
5105          * post- vblank; when vblank happens, the 'active' values will be set
5106          * to the final 'target' values and we'll do this again to get the
5107          * optimal watermarks.  For gen9+ platforms, the values we program here
5108          * will be the final target values which will get automatically latched
5109          * at vblank time; no further programming will be necessary.
5110          *
5111          * If a platform hasn't been transitioned to atomic watermarks yet,
5112          * we'll continue to update watermarks the old way, if flags tell
5113          * us to.
5114          */
5115         if (dev_priv->display.initial_watermarks != NULL)
5116                 dev_priv->display.initial_watermarks(old_intel_state,
5117                                                      pipe_config);
5118         else if (pipe_config->update_wm_pre)
5119                 intel_update_watermarks(crtc);
5120 }
5121
5122 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5123 {
5124         struct drm_device *dev = crtc->dev;
5125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5126         struct drm_plane *p;
5127         int pipe = intel_crtc->pipe;
5128
5129         intel_crtc_dpms_overlay_disable(intel_crtc);
5130
5131         drm_for_each_plane_mask(p, dev, plane_mask)
5132                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5133
5134         /*
5135          * FIXME: Once we grow proper nuclear flip support out of this we need
5136          * to compute the mask of flip planes precisely. For the time being
5137          * consider this a flip to a NULL plane.
5138          */
5139         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5140 }
5141
5142 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5143                                           struct intel_crtc_state *crtc_state,
5144                                           struct drm_atomic_state *old_state)
5145 {
5146         struct drm_connector_state *conn_state;
5147         struct drm_connector *conn;
5148         int i;
5149
5150         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5151                 struct intel_encoder *encoder =
5152                         to_intel_encoder(conn_state->best_encoder);
5153
5154                 if (conn_state->crtc != crtc)
5155                         continue;
5156
5157                 if (encoder->pre_pll_enable)
5158                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5159         }
5160 }
5161
5162 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5163                                       struct intel_crtc_state *crtc_state,
5164                                       struct drm_atomic_state *old_state)
5165 {
5166         struct drm_connector_state *conn_state;
5167         struct drm_connector *conn;
5168         int i;
5169
5170         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5171                 struct intel_encoder *encoder =
5172                         to_intel_encoder(conn_state->best_encoder);
5173
5174                 if (conn_state->crtc != crtc)
5175                         continue;
5176
5177                 if (encoder->pre_enable)
5178                         encoder->pre_enable(encoder, crtc_state, conn_state);
5179         }
5180 }
5181
5182 static void intel_encoders_enable(struct drm_crtc *crtc,
5183                                   struct intel_crtc_state *crtc_state,
5184                                   struct drm_atomic_state *old_state)
5185 {
5186         struct drm_connector_state *conn_state;
5187         struct drm_connector *conn;
5188         int i;
5189
5190         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5191                 struct intel_encoder *encoder =
5192                         to_intel_encoder(conn_state->best_encoder);
5193
5194                 if (conn_state->crtc != crtc)
5195                         continue;
5196
5197                 encoder->enable(encoder, crtc_state, conn_state);
5198                 intel_opregion_notify_encoder(encoder, true);
5199         }
5200 }
5201
5202 static void intel_encoders_disable(struct drm_crtc *crtc,
5203                                    struct intel_crtc_state *old_crtc_state,
5204                                    struct drm_atomic_state *old_state)
5205 {
5206         struct drm_connector_state *old_conn_state;
5207         struct drm_connector *conn;
5208         int i;
5209
5210         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5211                 struct intel_encoder *encoder =
5212                         to_intel_encoder(old_conn_state->best_encoder);
5213
5214                 if (old_conn_state->crtc != crtc)
5215                         continue;
5216
5217                 intel_opregion_notify_encoder(encoder, false);
5218                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5219         }
5220 }
5221
5222 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5223                                         struct intel_crtc_state *old_crtc_state,
5224                                         struct drm_atomic_state *old_state)
5225 {
5226         struct drm_connector_state *old_conn_state;
5227         struct drm_connector *conn;
5228         int i;
5229
5230         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5231                 struct intel_encoder *encoder =
5232                         to_intel_encoder(old_conn_state->best_encoder);
5233
5234                 if (old_conn_state->crtc != crtc)
5235                         continue;
5236
5237                 if (encoder->post_disable)
5238                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5239         }
5240 }
5241
5242 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5243                                             struct intel_crtc_state *old_crtc_state,
5244                                             struct drm_atomic_state *old_state)
5245 {
5246         struct drm_connector_state *old_conn_state;
5247         struct drm_connector *conn;
5248         int i;
5249
5250         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5251                 struct intel_encoder *encoder =
5252                         to_intel_encoder(old_conn_state->best_encoder);
5253
5254                 if (old_conn_state->crtc != crtc)
5255                         continue;
5256
5257                 if (encoder->post_pll_disable)
5258                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5259         }
5260 }
5261
5262 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5263                                  struct drm_atomic_state *old_state)
5264 {
5265         struct drm_crtc *crtc = pipe_config->base.crtc;
5266         struct drm_device *dev = crtc->dev;
5267         struct drm_i915_private *dev_priv = to_i915(dev);
5268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5269         int pipe = intel_crtc->pipe;
5270         struct intel_atomic_state *old_intel_state =
5271                 to_intel_atomic_state(old_state);
5272
5273         if (WARN_ON(intel_crtc->active))
5274                 return;
5275
5276         /*
5277          * Sometimes spurious CPU pipe underruns happen during FDI
5278          * training, at least with VGA+HDMI cloning. Suppress them.
5279          *
5280          * On ILK we get an occasional spurious CPU pipe underruns
5281          * between eDP port A enable and vdd enable. Also PCH port
5282          * enable seems to result in the occasional CPU pipe underrun.
5283          *
5284          * Spurious PCH underruns also occur during PCH enabling.
5285          */
5286         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5287                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5288         if (intel_crtc->config->has_pch_encoder)
5289                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5290
5291         if (intel_crtc->config->has_pch_encoder)
5292                 intel_prepare_shared_dpll(intel_crtc);
5293
5294         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5295                 intel_dp_set_m_n(intel_crtc, M1_N1);
5296
5297         intel_set_pipe_timings(intel_crtc);
5298         intel_set_pipe_src_size(intel_crtc);
5299
5300         if (intel_crtc->config->has_pch_encoder) {
5301                 intel_cpu_transcoder_set_m_n(intel_crtc,
5302                                      &intel_crtc->config->fdi_m_n, NULL);
5303         }
5304
5305         ironlake_set_pipeconf(crtc);
5306
5307         intel_crtc->active = true;
5308
5309         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5310
5311         if (intel_crtc->config->has_pch_encoder) {
5312                 /* Note: FDI PLL enabling _must_ be done before we enable the
5313                  * cpu pipes, hence this is separate from all the other fdi/pch
5314                  * enabling. */
5315                 ironlake_fdi_pll_enable(intel_crtc);
5316         } else {
5317                 assert_fdi_tx_disabled(dev_priv, pipe);
5318                 assert_fdi_rx_disabled(dev_priv, pipe);
5319         }
5320
5321         ironlake_pfit_enable(intel_crtc);
5322
5323         /*
5324          * On ILK+ LUT must be loaded before the pipe is running but with
5325          * clocks enabled
5326          */
5327         intel_color_load_luts(&pipe_config->base);
5328
5329         if (dev_priv->display.initial_watermarks != NULL)
5330                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5331         intel_enable_pipe(intel_crtc);
5332
5333         if (intel_crtc->config->has_pch_encoder)
5334                 ironlake_pch_enable(pipe_config);
5335
5336         assert_vblank_disabled(crtc);
5337         drm_crtc_vblank_on(crtc);
5338
5339         intel_encoders_enable(crtc, pipe_config, old_state);
5340
5341         if (HAS_PCH_CPT(dev_priv))
5342                 cpt_verify_modeset(dev, intel_crtc->pipe);
5343
5344         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5345         if (intel_crtc->config->has_pch_encoder)
5346                 intel_wait_for_vblank(dev_priv, pipe);
5347         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5348         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5349 }
5350
5351 /* IPS only exists on ULT machines and is tied to pipe A. */
5352 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5353 {
5354         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5355 }
5356
5357 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5358                                             enum pipe pipe, bool apply)
5359 {
5360         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5361         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5362
5363         if (apply)
5364                 val |= mask;
5365         else
5366                 val &= ~mask;
5367
5368         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5369 }
5370
5371 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5372                                 struct drm_atomic_state *old_state)
5373 {
5374         struct drm_crtc *crtc = pipe_config->base.crtc;
5375         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5377         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5378         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5379         struct intel_atomic_state *old_intel_state =
5380                 to_intel_atomic_state(old_state);
5381         bool psl_clkgate_wa;
5382
5383         if (WARN_ON(intel_crtc->active))
5384                 return;
5385
5386         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5387
5388         if (intel_crtc->config->shared_dpll)
5389                 intel_enable_shared_dpll(intel_crtc);
5390
5391         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5392                 intel_dp_set_m_n(intel_crtc, M1_N1);
5393
5394         if (!transcoder_is_dsi(cpu_transcoder))
5395                 intel_set_pipe_timings(intel_crtc);
5396
5397         intel_set_pipe_src_size(intel_crtc);
5398
5399         if (cpu_transcoder != TRANSCODER_EDP &&
5400             !transcoder_is_dsi(cpu_transcoder)) {
5401                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5402                            intel_crtc->config->pixel_multiplier - 1);
5403         }
5404
5405         if (intel_crtc->config->has_pch_encoder) {
5406                 intel_cpu_transcoder_set_m_n(intel_crtc,
5407                                      &intel_crtc->config->fdi_m_n, NULL);
5408         }
5409
5410         if (!transcoder_is_dsi(cpu_transcoder))
5411                 haswell_set_pipeconf(crtc);
5412
5413         haswell_set_pipemisc(crtc);
5414
5415         intel_color_set_csc(&pipe_config->base);
5416
5417         intel_crtc->active = true;
5418
5419         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5420
5421         if (!transcoder_is_dsi(cpu_transcoder))
5422                 intel_ddi_enable_pipe_clock(pipe_config);
5423
5424         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5425         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5426                          intel_crtc->config->pch_pfit.enabled;
5427         if (psl_clkgate_wa)
5428                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5429
5430         if (INTEL_GEN(dev_priv) >= 9)
5431                 skylake_pfit_enable(intel_crtc);
5432         else
5433                 ironlake_pfit_enable(intel_crtc);
5434
5435         /*
5436          * On ILK+ LUT must be loaded before the pipe is running but with
5437          * clocks enabled
5438          */
5439         intel_color_load_luts(&pipe_config->base);
5440
5441         intel_ddi_set_pipe_settings(pipe_config);
5442         if (!transcoder_is_dsi(cpu_transcoder))
5443                 intel_ddi_enable_transcoder_func(pipe_config);
5444
5445         if (dev_priv->display.initial_watermarks != NULL)
5446                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5447
5448         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5449         if (!transcoder_is_dsi(cpu_transcoder))
5450                 intel_enable_pipe(intel_crtc);
5451
5452         if (intel_crtc->config->has_pch_encoder)
5453                 lpt_pch_enable(pipe_config);
5454
5455         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5456                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5457
5458         assert_vblank_disabled(crtc);
5459         drm_crtc_vblank_on(crtc);
5460
5461         intel_encoders_enable(crtc, pipe_config, old_state);
5462
5463         if (psl_clkgate_wa) {
5464                 intel_wait_for_vblank(dev_priv, pipe);
5465                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5466         }
5467
5468         /* If we change the relative order between pipe/planes enabling, we need
5469          * to change the workaround. */
5470         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5471         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5472                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5473                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5474         }
5475 }
5476
5477 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5478 {
5479         struct drm_device *dev = crtc->base.dev;
5480         struct drm_i915_private *dev_priv = to_i915(dev);
5481         int pipe = crtc->pipe;
5482
5483         /* To avoid upsetting the power well on haswell only disable the pfit if
5484          * it's in use. The hw state code will make sure we get this right. */
5485         if (force || crtc->config->pch_pfit.enabled) {
5486                 I915_WRITE(PF_CTL(pipe), 0);
5487                 I915_WRITE(PF_WIN_POS(pipe), 0);
5488                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5489         }
5490 }
5491
5492 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5493                                   struct drm_atomic_state *old_state)
5494 {
5495         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5496         struct drm_device *dev = crtc->dev;
5497         struct drm_i915_private *dev_priv = to_i915(dev);
5498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5499         int pipe = intel_crtc->pipe;
5500
5501         /*
5502          * Sometimes spurious CPU pipe underruns happen when the
5503          * pipe is already disabled, but FDI RX/TX is still enabled.
5504          * Happens at least with VGA+HDMI cloning. Suppress them.
5505          */
5506         if (intel_crtc->config->has_pch_encoder) {
5507                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5508                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5509         }
5510
5511         intel_encoders_disable(crtc, old_crtc_state, old_state);
5512
5513         drm_crtc_vblank_off(crtc);
5514         assert_vblank_disabled(crtc);
5515
5516         intel_disable_pipe(intel_crtc);
5517
5518         ironlake_pfit_disable(intel_crtc, false);
5519
5520         if (intel_crtc->config->has_pch_encoder)
5521                 ironlake_fdi_disable(crtc);
5522
5523         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5524
5525         if (intel_crtc->config->has_pch_encoder) {
5526                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5527
5528                 if (HAS_PCH_CPT(dev_priv)) {
5529                         i915_reg_t reg;
5530                         u32 temp;
5531
5532                         /* disable TRANS_DP_CTL */
5533                         reg = TRANS_DP_CTL(pipe);
5534                         temp = I915_READ(reg);
5535                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5536                                   TRANS_DP_PORT_SEL_MASK);
5537                         temp |= TRANS_DP_PORT_SEL_NONE;
5538                         I915_WRITE(reg, temp);
5539
5540                         /* disable DPLL_SEL */
5541                         temp = I915_READ(PCH_DPLL_SEL);
5542                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5543                         I915_WRITE(PCH_DPLL_SEL, temp);
5544                 }
5545
5546                 ironlake_fdi_pll_disable(intel_crtc);
5547         }
5548
5549         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5550         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5551 }
5552
5553 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5554                                  struct drm_atomic_state *old_state)
5555 {
5556         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5557         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5559         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5560
5561         intel_encoders_disable(crtc, old_crtc_state, old_state);
5562
5563         drm_crtc_vblank_off(crtc);
5564         assert_vblank_disabled(crtc);
5565
5566         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5567         if (!transcoder_is_dsi(cpu_transcoder))
5568                 intel_disable_pipe(intel_crtc);
5569
5570         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5571                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5572
5573         if (!transcoder_is_dsi(cpu_transcoder))
5574                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5575
5576         if (INTEL_GEN(dev_priv) >= 9)
5577                 skylake_scaler_disable(intel_crtc);
5578         else
5579                 ironlake_pfit_disable(intel_crtc, false);
5580
5581         if (!transcoder_is_dsi(cpu_transcoder))
5582                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5583
5584         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5585 }
5586
5587 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5588 {
5589         struct drm_device *dev = crtc->base.dev;
5590         struct drm_i915_private *dev_priv = to_i915(dev);
5591         struct intel_crtc_state *pipe_config = crtc->config;
5592
5593         if (!pipe_config->gmch_pfit.control)
5594                 return;
5595
5596         /*
5597          * The panel fitter should only be adjusted whilst the pipe is disabled,
5598          * according to register description and PRM.
5599          */
5600         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5601         assert_pipe_disabled(dev_priv, crtc->pipe);
5602
5603         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5604         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5605
5606         /* Border color in case we don't scale up to the full screen. Black by
5607          * default, change to something else for debugging. */
5608         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5609 }
5610
5611 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5612 {
5613         switch (port) {
5614         case PORT_A:
5615                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5616         case PORT_B:
5617                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5618         case PORT_C:
5619                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5620         case PORT_D:
5621                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5622         case PORT_E:
5623                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5624         default:
5625                 MISSING_CASE(port);
5626                 return POWER_DOMAIN_PORT_OTHER;
5627         }
5628 }
5629
5630 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5631                                   struct intel_crtc_state *crtc_state)
5632 {
5633         struct drm_device *dev = crtc->dev;
5634         struct drm_i915_private *dev_priv = to_i915(dev);
5635         struct drm_encoder *encoder;
5636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5637         enum pipe pipe = intel_crtc->pipe;
5638         u64 mask;
5639         enum transcoder transcoder = crtc_state->cpu_transcoder;
5640
5641         if (!crtc_state->base.active)
5642                 return 0;
5643
5644         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5645         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5646         if (crtc_state->pch_pfit.enabled ||
5647             crtc_state->pch_pfit.force_thru)
5648                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5649
5650         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5651                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5652
5653                 mask |= BIT_ULL(intel_encoder->power_domain);
5654         }
5655
5656         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5657                 mask |= BIT(POWER_DOMAIN_AUDIO);
5658
5659         if (crtc_state->shared_dpll)
5660                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5661
5662         return mask;
5663 }
5664
5665 static u64
5666 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5667                                struct intel_crtc_state *crtc_state)
5668 {
5669         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5671         enum intel_display_power_domain domain;
5672         u64 domains, new_domains, old_domains;
5673
5674         old_domains = intel_crtc->enabled_power_domains;
5675         intel_crtc->enabled_power_domains = new_domains =
5676                 get_crtc_power_domains(crtc, crtc_state);
5677
5678         domains = new_domains & ~old_domains;
5679
5680         for_each_power_domain(domain, domains)
5681                 intel_display_power_get(dev_priv, domain);
5682
5683         return old_domains & ~new_domains;
5684 }
5685
5686 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5687                                       u64 domains)
5688 {
5689         enum intel_display_power_domain domain;
5690
5691         for_each_power_domain(domain, domains)
5692                 intel_display_power_put(dev_priv, domain);
5693 }
5694
5695 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5696                                    struct drm_atomic_state *old_state)
5697 {
5698         struct intel_atomic_state *old_intel_state =
5699                 to_intel_atomic_state(old_state);
5700         struct drm_crtc *crtc = pipe_config->base.crtc;
5701         struct drm_device *dev = crtc->dev;
5702         struct drm_i915_private *dev_priv = to_i915(dev);
5703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5704         int pipe = intel_crtc->pipe;
5705
5706         if (WARN_ON(intel_crtc->active))
5707                 return;
5708
5709         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5710                 intel_dp_set_m_n(intel_crtc, M1_N1);
5711
5712         intel_set_pipe_timings(intel_crtc);
5713         intel_set_pipe_src_size(intel_crtc);
5714
5715         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5716                 struct drm_i915_private *dev_priv = to_i915(dev);
5717
5718                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5719                 I915_WRITE(CHV_CANVAS(pipe), 0);
5720         }
5721
5722         i9xx_set_pipeconf(intel_crtc);
5723
5724         intel_crtc->active = true;
5725
5726         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5727
5728         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5729
5730         if (IS_CHERRYVIEW(dev_priv)) {
5731                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5732                 chv_enable_pll(intel_crtc, intel_crtc->config);
5733         } else {
5734                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5735                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5736         }
5737
5738         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5739
5740         i9xx_pfit_enable(intel_crtc);
5741
5742         intel_color_load_luts(&pipe_config->base);
5743
5744         dev_priv->display.initial_watermarks(old_intel_state,
5745                                              pipe_config);
5746         intel_enable_pipe(intel_crtc);
5747
5748         assert_vblank_disabled(crtc);
5749         drm_crtc_vblank_on(crtc);
5750
5751         intel_encoders_enable(crtc, pipe_config, old_state);
5752 }
5753
5754 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5755 {
5756         struct drm_device *dev = crtc->base.dev;
5757         struct drm_i915_private *dev_priv = to_i915(dev);
5758
5759         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5760         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5761 }
5762
5763 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5764                              struct drm_atomic_state *old_state)
5765 {
5766         struct intel_atomic_state *old_intel_state =
5767                 to_intel_atomic_state(old_state);
5768         struct drm_crtc *crtc = pipe_config->base.crtc;
5769         struct drm_device *dev = crtc->dev;
5770         struct drm_i915_private *dev_priv = to_i915(dev);
5771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5772         enum pipe pipe = intel_crtc->pipe;
5773
5774         if (WARN_ON(intel_crtc->active))
5775                 return;
5776
5777         i9xx_set_pll_dividers(intel_crtc);
5778
5779         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5780                 intel_dp_set_m_n(intel_crtc, M1_N1);
5781
5782         intel_set_pipe_timings(intel_crtc);
5783         intel_set_pipe_src_size(intel_crtc);
5784
5785         i9xx_set_pipeconf(intel_crtc);
5786
5787         intel_crtc->active = true;
5788
5789         if (!IS_GEN2(dev_priv))
5790                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5791
5792         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5793
5794         i9xx_enable_pll(intel_crtc, pipe_config);
5795
5796         i9xx_pfit_enable(intel_crtc);
5797
5798         intel_color_load_luts(&pipe_config->base);
5799
5800         if (dev_priv->display.initial_watermarks != NULL)
5801                 dev_priv->display.initial_watermarks(old_intel_state,
5802                                                      intel_crtc->config);
5803         else
5804                 intel_update_watermarks(intel_crtc);
5805         intel_enable_pipe(intel_crtc);
5806
5807         assert_vblank_disabled(crtc);
5808         drm_crtc_vblank_on(crtc);
5809
5810         intel_encoders_enable(crtc, pipe_config, old_state);
5811 }
5812
5813 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5814 {
5815         struct drm_device *dev = crtc->base.dev;
5816         struct drm_i915_private *dev_priv = to_i915(dev);
5817
5818         if (!crtc->config->gmch_pfit.control)
5819                 return;
5820
5821         assert_pipe_disabled(dev_priv, crtc->pipe);
5822
5823         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5824                          I915_READ(PFIT_CONTROL));
5825         I915_WRITE(PFIT_CONTROL, 0);
5826 }
5827
5828 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5829                               struct drm_atomic_state *old_state)
5830 {
5831         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5832         struct drm_device *dev = crtc->dev;
5833         struct drm_i915_private *dev_priv = to_i915(dev);
5834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5835         int pipe = intel_crtc->pipe;
5836
5837         /*
5838          * On gen2 planes are double buffered but the pipe isn't, so we must
5839          * wait for planes to fully turn off before disabling the pipe.
5840          */
5841         if (IS_GEN2(dev_priv))
5842                 intel_wait_for_vblank(dev_priv, pipe);
5843
5844         intel_encoders_disable(crtc, old_crtc_state, old_state);
5845
5846         drm_crtc_vblank_off(crtc);
5847         assert_vblank_disabled(crtc);
5848
5849         intel_disable_pipe(intel_crtc);
5850
5851         i9xx_pfit_disable(intel_crtc);
5852
5853         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5854
5855         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5856                 if (IS_CHERRYVIEW(dev_priv))
5857                         chv_disable_pll(dev_priv, pipe);
5858                 else if (IS_VALLEYVIEW(dev_priv))
5859                         vlv_disable_pll(dev_priv, pipe);
5860                 else
5861                         i9xx_disable_pll(intel_crtc);
5862         }
5863
5864         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5865
5866         if (!IS_GEN2(dev_priv))
5867                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5868
5869         if (!dev_priv->display.initial_watermarks)
5870                 intel_update_watermarks(intel_crtc);
5871
5872         /* clock the pipe down to 640x480@60 to potentially save power */
5873         if (IS_I830(dev_priv))
5874                 i830_enable_pipe(dev_priv, pipe);
5875 }
5876
5877 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5878                                         struct drm_modeset_acquire_ctx *ctx)
5879 {
5880         struct intel_encoder *encoder;
5881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5882         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5883         enum intel_display_power_domain domain;
5884         u64 domains;
5885         struct drm_atomic_state *state;
5886         struct intel_crtc_state *crtc_state;
5887         int ret;
5888
5889         if (!intel_crtc->active)
5890                 return;
5891
5892         if (crtc->primary->state->visible) {
5893                 intel_pre_disable_primary_noatomic(crtc);
5894
5895                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5896                 crtc->primary->state->visible = false;
5897         }
5898
5899         state = drm_atomic_state_alloc(crtc->dev);
5900         if (!state) {
5901                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5902                               crtc->base.id, crtc->name);
5903                 return;
5904         }
5905
5906         state->acquire_ctx = ctx;
5907
5908         /* Everything's already locked, -EDEADLK can't happen. */
5909         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5910         ret = drm_atomic_add_affected_connectors(state, crtc);
5911
5912         WARN_ON(IS_ERR(crtc_state) || ret);
5913
5914         dev_priv->display.crtc_disable(crtc_state, state);
5915
5916         drm_atomic_state_put(state);
5917
5918         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5919                       crtc->base.id, crtc->name);
5920
5921         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5922         crtc->state->active = false;
5923         intel_crtc->active = false;
5924         crtc->enabled = false;
5925         crtc->state->connector_mask = 0;
5926         crtc->state->encoder_mask = 0;
5927
5928         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5929                 encoder->base.crtc = NULL;
5930
5931         intel_fbc_disable(intel_crtc);
5932         intel_update_watermarks(intel_crtc);
5933         intel_disable_shared_dpll(intel_crtc);
5934
5935         domains = intel_crtc->enabled_power_domains;
5936         for_each_power_domain(domain, domains)
5937                 intel_display_power_put(dev_priv, domain);
5938         intel_crtc->enabled_power_domains = 0;
5939
5940         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5941         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
5942 }
5943
5944 /*
5945  * turn all crtc's off, but do not adjust state
5946  * This has to be paired with a call to intel_modeset_setup_hw_state.
5947  */
5948 int intel_display_suspend(struct drm_device *dev)
5949 {
5950         struct drm_i915_private *dev_priv = to_i915(dev);
5951         struct drm_atomic_state *state;
5952         int ret;
5953
5954         state = drm_atomic_helper_suspend(dev);
5955         ret = PTR_ERR_OR_ZERO(state);
5956         if (ret)
5957                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5958         else
5959                 dev_priv->modeset_restore_state = state;
5960         return ret;
5961 }
5962
5963 void intel_encoder_destroy(struct drm_encoder *encoder)
5964 {
5965         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5966
5967         drm_encoder_cleanup(encoder);
5968         kfree(intel_encoder);
5969 }
5970
5971 /* Cross check the actual hw state with our own modeset state tracking (and it's
5972  * internal consistency). */
5973 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5974                                          struct drm_connector_state *conn_state)
5975 {
5976         struct intel_connector *connector = to_intel_connector(conn_state->connector);
5977
5978         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5979                       connector->base.base.id,
5980                       connector->base.name);
5981
5982         if (connector->get_hw_state(connector)) {
5983                 struct intel_encoder *encoder = connector->encoder;
5984
5985                 I915_STATE_WARN(!crtc_state,
5986                          "connector enabled without attached crtc\n");
5987
5988                 if (!crtc_state)
5989                         return;
5990
5991                 I915_STATE_WARN(!crtc_state->active,
5992                       "connector is active, but attached crtc isn't\n");
5993
5994                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5995                         return;
5996
5997                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5998                         "atomic encoder doesn't match attached encoder\n");
5999
6000                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6001                         "attached encoder crtc differs from connector crtc\n");
6002         } else {
6003                 I915_STATE_WARN(crtc_state && crtc_state->active,
6004                         "attached crtc is active, but connector isn't\n");
6005                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6006                         "best encoder set without crtc!\n");
6007         }
6008 }
6009
6010 int intel_connector_init(struct intel_connector *connector)
6011 {
6012         struct intel_digital_connector_state *conn_state;
6013
6014         /*
6015          * Allocate enough memory to hold intel_digital_connector_state,
6016          * This might be a few bytes too many, but for connectors that don't
6017          * need it we'll free the state and allocate a smaller one on the first
6018          * succesful commit anyway.
6019          */
6020         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6021         if (!conn_state)
6022                 return -ENOMEM;
6023
6024         __drm_atomic_helper_connector_reset(&connector->base,
6025                                             &conn_state->base);
6026
6027         return 0;
6028 }
6029
6030 struct intel_connector *intel_connector_alloc(void)
6031 {
6032         struct intel_connector *connector;
6033
6034         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6035         if (!connector)
6036                 return NULL;
6037
6038         if (intel_connector_init(connector) < 0) {
6039                 kfree(connector);
6040                 return NULL;
6041         }
6042
6043         return connector;
6044 }
6045
6046 /*
6047  * Free the bits allocated by intel_connector_alloc.
6048  * This should only be used after intel_connector_alloc has returned
6049  * successfully, and before drm_connector_init returns successfully.
6050  * Otherwise the destroy callbacks for the connector and the state should
6051  * take care of proper cleanup/free
6052  */
6053 void intel_connector_free(struct intel_connector *connector)
6054 {
6055         kfree(to_intel_digital_connector_state(connector->base.state));
6056         kfree(connector);
6057 }
6058
6059 /* Simple connector->get_hw_state implementation for encoders that support only
6060  * one connector and no cloning and hence the encoder state determines the state
6061  * of the connector. */
6062 bool intel_connector_get_hw_state(struct intel_connector *connector)
6063 {
6064         enum pipe pipe = 0;
6065         struct intel_encoder *encoder = connector->encoder;
6066
6067         return encoder->get_hw_state(encoder, &pipe);
6068 }
6069
6070 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6071 {
6072         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6073                 return crtc_state->fdi_lanes;
6074
6075         return 0;
6076 }
6077
6078 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6079                                      struct intel_crtc_state *pipe_config)
6080 {
6081         struct drm_i915_private *dev_priv = to_i915(dev);
6082         struct drm_atomic_state *state = pipe_config->base.state;
6083         struct intel_crtc *other_crtc;
6084         struct intel_crtc_state *other_crtc_state;
6085
6086         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6087                       pipe_name(pipe), pipe_config->fdi_lanes);
6088         if (pipe_config->fdi_lanes > 4) {
6089                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6090                               pipe_name(pipe), pipe_config->fdi_lanes);
6091                 return -EINVAL;
6092         }
6093
6094         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6095                 if (pipe_config->fdi_lanes > 2) {
6096                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6097                                       pipe_config->fdi_lanes);
6098                         return -EINVAL;
6099                 } else {
6100                         return 0;
6101                 }
6102         }
6103
6104         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6105                 return 0;
6106
6107         /* Ivybridge 3 pipe is really complicated */
6108         switch (pipe) {
6109         case PIPE_A:
6110                 return 0;
6111         case PIPE_B:
6112                 if (pipe_config->fdi_lanes <= 2)
6113                         return 0;
6114
6115                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6116                 other_crtc_state =
6117                         intel_atomic_get_crtc_state(state, other_crtc);
6118                 if (IS_ERR(other_crtc_state))
6119                         return PTR_ERR(other_crtc_state);
6120
6121                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6122                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6123                                       pipe_name(pipe), pipe_config->fdi_lanes);
6124                         return -EINVAL;
6125                 }
6126                 return 0;
6127         case PIPE_C:
6128                 if (pipe_config->fdi_lanes > 2) {
6129                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6130                                       pipe_name(pipe), pipe_config->fdi_lanes);
6131                         return -EINVAL;
6132                 }
6133
6134                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6135                 other_crtc_state =
6136                         intel_atomic_get_crtc_state(state, other_crtc);
6137                 if (IS_ERR(other_crtc_state))
6138                         return PTR_ERR(other_crtc_state);
6139
6140                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6141                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6142                         return -EINVAL;
6143                 }
6144                 return 0;
6145         default:
6146                 BUG();
6147         }
6148 }
6149
6150 #define RETRY 1
6151 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6152                                        struct intel_crtc_state *pipe_config)
6153 {
6154         struct drm_device *dev = intel_crtc->base.dev;
6155         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6156         int lane, link_bw, fdi_dotclock, ret;
6157         bool needs_recompute = false;
6158
6159 retry:
6160         /* FDI is a binary signal running at ~2.7GHz, encoding
6161          * each output octet as 10 bits. The actual frequency
6162          * is stored as a divider into a 100MHz clock, and the
6163          * mode pixel clock is stored in units of 1KHz.
6164          * Hence the bw of each lane in terms of the mode signal
6165          * is:
6166          */
6167         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6168
6169         fdi_dotclock = adjusted_mode->crtc_clock;
6170
6171         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6172                                            pipe_config->pipe_bpp);
6173
6174         pipe_config->fdi_lanes = lane;
6175
6176         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6177                                link_bw, &pipe_config->fdi_m_n, false);
6178
6179         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6180         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6181                 pipe_config->pipe_bpp -= 2*3;
6182                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6183                               pipe_config->pipe_bpp);
6184                 needs_recompute = true;
6185                 pipe_config->bw_constrained = true;
6186
6187                 goto retry;
6188         }
6189
6190         if (needs_recompute)
6191                 return RETRY;
6192
6193         return ret;
6194 }
6195
6196 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6197                                      struct intel_crtc_state *pipe_config)
6198 {
6199         if (pipe_config->ips_force_disable)
6200                 return false;
6201
6202         if (pipe_config->pipe_bpp > 24)
6203                 return false;
6204
6205         /* HSW can handle pixel rate up to cdclk? */
6206         if (IS_HASWELL(dev_priv))
6207                 return true;
6208
6209         /*
6210          * We compare against max which means we must take
6211          * the increased cdclk requirement into account when
6212          * calculating the new cdclk.
6213          *
6214          * Should measure whether using a lower cdclk w/o IPS
6215          */
6216         return pipe_config->pixel_rate <=
6217                 dev_priv->max_cdclk_freq * 95 / 100;
6218 }
6219
6220 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6221                                    struct intel_crtc_state *pipe_config)
6222 {
6223         struct drm_device *dev = crtc->base.dev;
6224         struct drm_i915_private *dev_priv = to_i915(dev);
6225
6226         pipe_config->ips_enabled = i915_modparams.enable_ips &&
6227                 hsw_crtc_supports_ips(crtc) &&
6228                 pipe_config_supports_ips(dev_priv, pipe_config);
6229 }
6230
6231 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6232 {
6233         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6234
6235         /* GDG double wide on either pipe, otherwise pipe A only */
6236         return INTEL_INFO(dev_priv)->gen < 4 &&
6237                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6238 }
6239
6240 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6241 {
6242         uint32_t pixel_rate;
6243
6244         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6245
6246         /*
6247          * We only use IF-ID interlacing. If we ever use
6248          * PF-ID we'll need to adjust the pixel_rate here.
6249          */
6250
6251         if (pipe_config->pch_pfit.enabled) {
6252                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6253                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6254
6255                 pipe_w = pipe_config->pipe_src_w;
6256                 pipe_h = pipe_config->pipe_src_h;
6257
6258                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6259                 pfit_h = pfit_size & 0xFFFF;
6260                 if (pipe_w < pfit_w)
6261                         pipe_w = pfit_w;
6262                 if (pipe_h < pfit_h)
6263                         pipe_h = pfit_h;
6264
6265                 if (WARN_ON(!pfit_w || !pfit_h))
6266                         return pixel_rate;
6267
6268                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6269                                      pfit_w * pfit_h);
6270         }
6271
6272         return pixel_rate;
6273 }
6274
6275 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6276 {
6277         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6278
6279         if (HAS_GMCH_DISPLAY(dev_priv))
6280                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6281                 crtc_state->pixel_rate =
6282                         crtc_state->base.adjusted_mode.crtc_clock;
6283         else
6284                 crtc_state->pixel_rate =
6285                         ilk_pipe_pixel_rate(crtc_state);
6286 }
6287
6288 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6289                                      struct intel_crtc_state *pipe_config)
6290 {
6291         struct drm_device *dev = crtc->base.dev;
6292         struct drm_i915_private *dev_priv = to_i915(dev);
6293         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6294         int clock_limit = dev_priv->max_dotclk_freq;
6295
6296         if (INTEL_GEN(dev_priv) < 4) {
6297                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6298
6299                 /*
6300                  * Enable double wide mode when the dot clock
6301                  * is > 90% of the (display) core speed.
6302                  */
6303                 if (intel_crtc_supports_double_wide(crtc) &&
6304                     adjusted_mode->crtc_clock > clock_limit) {
6305                         clock_limit = dev_priv->max_dotclk_freq;
6306                         pipe_config->double_wide = true;
6307                 }
6308         }
6309
6310         if (adjusted_mode->crtc_clock > clock_limit) {
6311                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6312                               adjusted_mode->crtc_clock, clock_limit,
6313                               yesno(pipe_config->double_wide));
6314                 return -EINVAL;
6315         }
6316
6317         if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6318                 /*
6319                  * There is only one pipe CSC unit per pipe, and we need that
6320                  * for output conversion from RGB->YCBCR. So if CTM is already
6321                  * applied we can't support YCBCR420 output.
6322                  */
6323                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6324                 return -EINVAL;
6325         }
6326
6327         /*
6328          * Pipe horizontal size must be even in:
6329          * - DVO ganged mode
6330          * - LVDS dual channel mode
6331          * - Double wide pipe
6332          */
6333         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6334              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6335                 pipe_config->pipe_src_w &= ~1;
6336
6337         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6338          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6339          */
6340         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6341                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6342                 return -EINVAL;
6343
6344         intel_crtc_compute_pixel_rate(pipe_config);
6345
6346         if (HAS_IPS(dev_priv))
6347                 hsw_compute_ips_config(crtc, pipe_config);
6348
6349         if (pipe_config->has_pch_encoder)
6350                 return ironlake_fdi_compute_config(crtc, pipe_config);
6351
6352         return 0;
6353 }
6354
6355 static void
6356 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6357 {
6358         while (*num > DATA_LINK_M_N_MASK ||
6359                *den > DATA_LINK_M_N_MASK) {
6360                 *num >>= 1;
6361                 *den >>= 1;
6362         }
6363 }
6364
6365 static void compute_m_n(unsigned int m, unsigned int n,
6366                         uint32_t *ret_m, uint32_t *ret_n,
6367                         bool reduce_m_n)
6368 {
6369         /*
6370          * Reduce M/N as much as possible without loss in precision. Several DP
6371          * dongles in particular seem to be fussy about too large *link* M/N
6372          * values. The passed in values are more likely to have the least
6373          * significant bits zero than M after rounding below, so do this first.
6374          */
6375         if (reduce_m_n) {
6376                 while ((m & 1) == 0 && (n & 1) == 0) {
6377                         m >>= 1;
6378                         n >>= 1;
6379                 }
6380         }
6381
6382         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6383         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6384         intel_reduce_m_n_ratio(ret_m, ret_n);
6385 }
6386
6387 void
6388 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6389                        int pixel_clock, int link_clock,
6390                        struct intel_link_m_n *m_n,
6391                        bool reduce_m_n)
6392 {
6393         m_n->tu = 64;
6394
6395         compute_m_n(bits_per_pixel * pixel_clock,
6396                     link_clock * nlanes * 8,
6397                     &m_n->gmch_m, &m_n->gmch_n,
6398                     reduce_m_n);
6399
6400         compute_m_n(pixel_clock, link_clock,
6401                     &m_n->link_m, &m_n->link_n,
6402                     reduce_m_n);
6403 }
6404
6405 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6406 {
6407         if (i915_modparams.panel_use_ssc >= 0)
6408                 return i915_modparams.panel_use_ssc != 0;
6409         return dev_priv->vbt.lvds_use_ssc
6410                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6411 }
6412
6413 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6414 {
6415         return (1 << dpll->n) << 16 | dpll->m2;
6416 }
6417
6418 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6419 {
6420         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6421 }
6422
6423 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6424                                      struct intel_crtc_state *crtc_state,
6425                                      struct dpll *reduced_clock)
6426 {
6427         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6428         u32 fp, fp2 = 0;
6429
6430         if (IS_PINEVIEW(dev_priv)) {
6431                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6432                 if (reduced_clock)
6433                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6434         } else {
6435                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6436                 if (reduced_clock)
6437                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6438         }
6439
6440         crtc_state->dpll_hw_state.fp0 = fp;
6441
6442         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6443             reduced_clock) {
6444                 crtc_state->dpll_hw_state.fp1 = fp2;
6445         } else {
6446                 crtc_state->dpll_hw_state.fp1 = fp;
6447         }
6448 }
6449
6450 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6451                 pipe)
6452 {
6453         u32 reg_val;
6454
6455         /*
6456          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6457          * and set it to a reasonable value instead.
6458          */
6459         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6460         reg_val &= 0xffffff00;
6461         reg_val |= 0x00000030;
6462         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6463
6464         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6465         reg_val &= 0x00ffffff;
6466         reg_val |= 0x8c000000;
6467         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6468
6469         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6470         reg_val &= 0xffffff00;
6471         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6472
6473         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6474         reg_val &= 0x00ffffff;
6475         reg_val |= 0xb0000000;
6476         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6477 }
6478
6479 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6480                                          struct intel_link_m_n *m_n)
6481 {
6482         struct drm_device *dev = crtc->base.dev;
6483         struct drm_i915_private *dev_priv = to_i915(dev);
6484         int pipe = crtc->pipe;
6485
6486         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6487         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6488         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6489         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6490 }
6491
6492 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6493                                          struct intel_link_m_n *m_n,
6494                                          struct intel_link_m_n *m2_n2)
6495 {
6496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6497         int pipe = crtc->pipe;
6498         enum transcoder transcoder = crtc->config->cpu_transcoder;
6499
6500         if (INTEL_GEN(dev_priv) >= 5) {
6501                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6502                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6503                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6504                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6505                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6506                  * for gen < 8) and if DRRS is supported (to make sure the
6507                  * registers are not unnecessarily accessed).
6508                  */
6509                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6510                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6511                         I915_WRITE(PIPE_DATA_M2(transcoder),
6512                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6513                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6514                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6515                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6516                 }
6517         } else {
6518                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6519                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6520                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6521                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6522         }
6523 }
6524
6525 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6526 {
6527         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6528
6529         if (m_n == M1_N1) {
6530                 dp_m_n = &crtc->config->dp_m_n;
6531                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6532         } else if (m_n == M2_N2) {
6533
6534                 /*
6535                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6536                  * needs to be programmed into M1_N1.
6537                  */
6538                 dp_m_n = &crtc->config->dp_m2_n2;
6539         } else {
6540                 DRM_ERROR("Unsupported divider value\n");
6541                 return;
6542         }
6543
6544         if (crtc->config->has_pch_encoder)
6545                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6546         else
6547                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6548 }
6549
6550 static void vlv_compute_dpll(struct intel_crtc *crtc,
6551                              struct intel_crtc_state *pipe_config)
6552 {
6553         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6554                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6555         if (crtc->pipe != PIPE_A)
6556                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6557
6558         /* DPLL not used with DSI, but still need the rest set up */
6559         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6560                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6561                         DPLL_EXT_BUFFER_ENABLE_VLV;
6562
6563         pipe_config->dpll_hw_state.dpll_md =
6564                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6565 }
6566
6567 static void chv_compute_dpll(struct intel_crtc *crtc,
6568                              struct intel_crtc_state *pipe_config)
6569 {
6570         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6571                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6572         if (crtc->pipe != PIPE_A)
6573                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6574
6575         /* DPLL not used with DSI, but still need the rest set up */
6576         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6577                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6578
6579         pipe_config->dpll_hw_state.dpll_md =
6580                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6581 }
6582
6583 static void vlv_prepare_pll(struct intel_crtc *crtc,
6584                             const struct intel_crtc_state *pipe_config)
6585 {
6586         struct drm_device *dev = crtc->base.dev;
6587         struct drm_i915_private *dev_priv = to_i915(dev);
6588         enum pipe pipe = crtc->pipe;
6589         u32 mdiv;
6590         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6591         u32 coreclk, reg_val;
6592
6593         /* Enable Refclk */
6594         I915_WRITE(DPLL(pipe),
6595                    pipe_config->dpll_hw_state.dpll &
6596                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6597
6598         /* No need to actually set up the DPLL with DSI */
6599         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6600                 return;
6601
6602         mutex_lock(&dev_priv->sb_lock);
6603
6604         bestn = pipe_config->dpll.n;
6605         bestm1 = pipe_config->dpll.m1;
6606         bestm2 = pipe_config->dpll.m2;
6607         bestp1 = pipe_config->dpll.p1;
6608         bestp2 = pipe_config->dpll.p2;
6609
6610         /* See eDP HDMI DPIO driver vbios notes doc */
6611
6612         /* PLL B needs special handling */
6613         if (pipe == PIPE_B)
6614                 vlv_pllb_recal_opamp(dev_priv, pipe);
6615
6616         /* Set up Tx target for periodic Rcomp update */
6617         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6618
6619         /* Disable target IRef on PLL */
6620         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6621         reg_val &= 0x00ffffff;
6622         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6623
6624         /* Disable fast lock */
6625         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6626
6627         /* Set idtafcrecal before PLL is enabled */
6628         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6629         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6630         mdiv |= ((bestn << DPIO_N_SHIFT));
6631         mdiv |= (1 << DPIO_K_SHIFT);
6632
6633         /*
6634          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6635          * but we don't support that).
6636          * Note: don't use the DAC post divider as it seems unstable.
6637          */
6638         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6639         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6640
6641         mdiv |= DPIO_ENABLE_CALIBRATION;
6642         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6643
6644         /* Set HBR and RBR LPF coefficients */
6645         if (pipe_config->port_clock == 162000 ||
6646             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6647             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6648                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6649                                  0x009f0003);
6650         else
6651                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6652                                  0x00d0000f);
6653
6654         if (intel_crtc_has_dp_encoder(pipe_config)) {
6655                 /* Use SSC source */
6656                 if (pipe == PIPE_A)
6657                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6658                                          0x0df40000);
6659                 else
6660                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6661                                          0x0df70000);
6662         } else { /* HDMI or VGA */
6663                 /* Use bend source */
6664                 if (pipe == PIPE_A)
6665                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6666                                          0x0df70000);
6667                 else
6668                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6669                                          0x0df40000);
6670         }
6671
6672         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6673         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6674         if (intel_crtc_has_dp_encoder(crtc->config))
6675                 coreclk |= 0x01000000;
6676         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6677
6678         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6679         mutex_unlock(&dev_priv->sb_lock);
6680 }
6681
6682 static void chv_prepare_pll(struct intel_crtc *crtc,
6683                             const struct intel_crtc_state *pipe_config)
6684 {
6685         struct drm_device *dev = crtc->base.dev;
6686         struct drm_i915_private *dev_priv = to_i915(dev);
6687         enum pipe pipe = crtc->pipe;
6688         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6689         u32 loopfilter, tribuf_calcntr;
6690         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6691         u32 dpio_val;
6692         int vco;
6693
6694         /* Enable Refclk and SSC */
6695         I915_WRITE(DPLL(pipe),
6696                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6697
6698         /* No need to actually set up the DPLL with DSI */
6699         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6700                 return;
6701
6702         bestn = pipe_config->dpll.n;
6703         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6704         bestm1 = pipe_config->dpll.m1;
6705         bestm2 = pipe_config->dpll.m2 >> 22;
6706         bestp1 = pipe_config->dpll.p1;
6707         bestp2 = pipe_config->dpll.p2;
6708         vco = pipe_config->dpll.vco;
6709         dpio_val = 0;
6710         loopfilter = 0;
6711
6712         mutex_lock(&dev_priv->sb_lock);
6713
6714         /* p1 and p2 divider */
6715         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6716                         5 << DPIO_CHV_S1_DIV_SHIFT |
6717                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6718                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6719                         1 << DPIO_CHV_K_DIV_SHIFT);
6720
6721         /* Feedback post-divider - m2 */
6722         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6723
6724         /* Feedback refclk divider - n and m1 */
6725         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6726                         DPIO_CHV_M1_DIV_BY_2 |
6727                         1 << DPIO_CHV_N_DIV_SHIFT);
6728
6729         /* M2 fraction division */
6730         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6731
6732         /* M2 fraction division enable */
6733         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6734         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6735         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6736         if (bestm2_frac)
6737                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6738         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6739
6740         /* Program digital lock detect threshold */
6741         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6742         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6743                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6744         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6745         if (!bestm2_frac)
6746                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6747         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6748
6749         /* Loop filter */
6750         if (vco == 5400000) {
6751                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6752                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6753                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6754                 tribuf_calcntr = 0x9;
6755         } else if (vco <= 6200000) {
6756                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6757                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6758                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6759                 tribuf_calcntr = 0x9;
6760         } else if (vco <= 6480000) {
6761                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6762                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6763                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6764                 tribuf_calcntr = 0x8;
6765         } else {
6766                 /* Not supported. Apply the same limits as in the max case */
6767                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6768                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6769                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6770                 tribuf_calcntr = 0;
6771         }
6772         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6773
6774         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6775         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6776         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6777         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6778
6779         /* AFC Recal */
6780         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6781                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6782                         DPIO_AFC_RECAL);
6783
6784         mutex_unlock(&dev_priv->sb_lock);
6785 }
6786
6787 /**
6788  * vlv_force_pll_on - forcibly enable just the PLL
6789  * @dev_priv: i915 private structure
6790  * @pipe: pipe PLL to enable
6791  * @dpll: PLL configuration
6792  *
6793  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6794  * in cases where we need the PLL enabled even when @pipe is not going to
6795  * be enabled.
6796  */
6797 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6798                      const struct dpll *dpll)
6799 {
6800         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6801         struct intel_crtc_state *pipe_config;
6802
6803         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6804         if (!pipe_config)
6805                 return -ENOMEM;
6806
6807         pipe_config->base.crtc = &crtc->base;
6808         pipe_config->pixel_multiplier = 1;
6809         pipe_config->dpll = *dpll;
6810
6811         if (IS_CHERRYVIEW(dev_priv)) {
6812                 chv_compute_dpll(crtc, pipe_config);
6813                 chv_prepare_pll(crtc, pipe_config);
6814                 chv_enable_pll(crtc, pipe_config);
6815         } else {
6816                 vlv_compute_dpll(crtc, pipe_config);
6817                 vlv_prepare_pll(crtc, pipe_config);
6818                 vlv_enable_pll(crtc, pipe_config);
6819         }
6820
6821         kfree(pipe_config);
6822
6823         return 0;
6824 }
6825
6826 /**
6827  * vlv_force_pll_off - forcibly disable just the PLL
6828  * @dev_priv: i915 private structure
6829  * @pipe: pipe PLL to disable
6830  *
6831  * Disable the PLL for @pipe. To be used in cases where we need
6832  * the PLL enabled even when @pipe is not going to be enabled.
6833  */
6834 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6835 {
6836         if (IS_CHERRYVIEW(dev_priv))
6837                 chv_disable_pll(dev_priv, pipe);
6838         else
6839                 vlv_disable_pll(dev_priv, pipe);
6840 }
6841
6842 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6843                               struct intel_crtc_state *crtc_state,
6844                               struct dpll *reduced_clock)
6845 {
6846         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6847         u32 dpll;
6848         struct dpll *clock = &crtc_state->dpll;
6849
6850         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6851
6852         dpll = DPLL_VGA_MODE_DIS;
6853
6854         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6855                 dpll |= DPLLB_MODE_LVDS;
6856         else
6857                 dpll |= DPLLB_MODE_DAC_SERIAL;
6858
6859         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6860             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6861                 dpll |= (crtc_state->pixel_multiplier - 1)
6862                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6863         }
6864
6865         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6866             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6867                 dpll |= DPLL_SDVO_HIGH_SPEED;
6868
6869         if (intel_crtc_has_dp_encoder(crtc_state))
6870                 dpll |= DPLL_SDVO_HIGH_SPEED;
6871
6872         /* compute bitmask from p1 value */
6873         if (IS_PINEVIEW(dev_priv))
6874                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6875         else {
6876                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6877                 if (IS_G4X(dev_priv) && reduced_clock)
6878                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6879         }
6880         switch (clock->p2) {
6881         case 5:
6882                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6883                 break;
6884         case 7:
6885                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6886                 break;
6887         case 10:
6888                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6889                 break;
6890         case 14:
6891                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6892                 break;
6893         }
6894         if (INTEL_GEN(dev_priv) >= 4)
6895                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6896
6897         if (crtc_state->sdvo_tv_clock)
6898                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6899         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6900                  intel_panel_use_ssc(dev_priv))
6901                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6902         else
6903                 dpll |= PLL_REF_INPUT_DREFCLK;
6904
6905         dpll |= DPLL_VCO_ENABLE;
6906         crtc_state->dpll_hw_state.dpll = dpll;
6907
6908         if (INTEL_GEN(dev_priv) >= 4) {
6909                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6910                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6911                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6912         }
6913 }
6914
6915 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6916                               struct intel_crtc_state *crtc_state,
6917                               struct dpll *reduced_clock)
6918 {
6919         struct drm_device *dev = crtc->base.dev;
6920         struct drm_i915_private *dev_priv = to_i915(dev);
6921         u32 dpll;
6922         struct dpll *clock = &crtc_state->dpll;
6923
6924         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6925
6926         dpll = DPLL_VGA_MODE_DIS;
6927
6928         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6929                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6930         } else {
6931                 if (clock->p1 == 2)
6932                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6933                 else
6934                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6935                 if (clock->p2 == 4)
6936                         dpll |= PLL_P2_DIVIDE_BY_4;
6937         }
6938
6939         if (!IS_I830(dev_priv) &&
6940             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6941                 dpll |= DPLL_DVO_2X_MODE;
6942
6943         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6944             intel_panel_use_ssc(dev_priv))
6945                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6946         else
6947                 dpll |= PLL_REF_INPUT_DREFCLK;
6948
6949         dpll |= DPLL_VCO_ENABLE;
6950         crtc_state->dpll_hw_state.dpll = dpll;
6951 }
6952
6953 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6954 {
6955         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6956         enum pipe pipe = intel_crtc->pipe;
6957         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6958         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6959         uint32_t crtc_vtotal, crtc_vblank_end;
6960         int vsyncshift = 0;
6961
6962         /* We need to be careful not to changed the adjusted mode, for otherwise
6963          * the hw state checker will get angry at the mismatch. */
6964         crtc_vtotal = adjusted_mode->crtc_vtotal;
6965         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6966
6967         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6968                 /* the chip adds 2 halflines automatically */
6969                 crtc_vtotal -= 1;
6970                 crtc_vblank_end -= 1;
6971
6972                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6973                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6974                 else
6975                         vsyncshift = adjusted_mode->crtc_hsync_start -
6976                                 adjusted_mode->crtc_htotal / 2;
6977                 if (vsyncshift < 0)
6978                         vsyncshift += adjusted_mode->crtc_htotal;
6979         }
6980
6981         if (INTEL_GEN(dev_priv) > 3)
6982                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6983
6984         I915_WRITE(HTOTAL(cpu_transcoder),
6985                    (adjusted_mode->crtc_hdisplay - 1) |
6986                    ((adjusted_mode->crtc_htotal - 1) << 16));
6987         I915_WRITE(HBLANK(cpu_transcoder),
6988                    (adjusted_mode->crtc_hblank_start - 1) |
6989                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6990         I915_WRITE(HSYNC(cpu_transcoder),
6991                    (adjusted_mode->crtc_hsync_start - 1) |
6992                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6993
6994         I915_WRITE(VTOTAL(cpu_transcoder),
6995                    (adjusted_mode->crtc_vdisplay - 1) |
6996                    ((crtc_vtotal - 1) << 16));
6997         I915_WRITE(VBLANK(cpu_transcoder),
6998                    (adjusted_mode->crtc_vblank_start - 1) |
6999                    ((crtc_vblank_end - 1) << 16));
7000         I915_WRITE(VSYNC(cpu_transcoder),
7001                    (adjusted_mode->crtc_vsync_start - 1) |
7002                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7003
7004         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7005          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7006          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7007          * bits. */
7008         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7009             (pipe == PIPE_B || pipe == PIPE_C))
7010                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7011
7012 }
7013
7014 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7015 {
7016         struct drm_device *dev = intel_crtc->base.dev;
7017         struct drm_i915_private *dev_priv = to_i915(dev);
7018         enum pipe pipe = intel_crtc->pipe;
7019
7020         /* pipesrc controls the size that is scaled from, which should
7021          * always be the user's requested size.
7022          */
7023         I915_WRITE(PIPESRC(pipe),
7024                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7025                    (intel_crtc->config->pipe_src_h - 1));
7026 }
7027
7028 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7029                                    struct intel_crtc_state *pipe_config)
7030 {
7031         struct drm_device *dev = crtc->base.dev;
7032         struct drm_i915_private *dev_priv = to_i915(dev);
7033         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7034         uint32_t tmp;
7035
7036         tmp = I915_READ(HTOTAL(cpu_transcoder));
7037         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7038         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7039         tmp = I915_READ(HBLANK(cpu_transcoder));
7040         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7041         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7042         tmp = I915_READ(HSYNC(cpu_transcoder));
7043         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7044         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7045
7046         tmp = I915_READ(VTOTAL(cpu_transcoder));
7047         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7048         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7049         tmp = I915_READ(VBLANK(cpu_transcoder));
7050         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7051         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7052         tmp = I915_READ(VSYNC(cpu_transcoder));
7053         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7054         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7055
7056         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7057                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7058                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7059                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7060         }
7061 }
7062
7063 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7064                                     struct intel_crtc_state *pipe_config)
7065 {
7066         struct drm_device *dev = crtc->base.dev;
7067         struct drm_i915_private *dev_priv = to_i915(dev);
7068         u32 tmp;
7069
7070         tmp = I915_READ(PIPESRC(crtc->pipe));
7071         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7072         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7073
7074         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7075         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7076 }
7077
7078 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7079                                  struct intel_crtc_state *pipe_config)
7080 {
7081         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7082         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7083         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7084         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7085
7086         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7087         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7088         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7089         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7090
7091         mode->flags = pipe_config->base.adjusted_mode.flags;
7092         mode->type = DRM_MODE_TYPE_DRIVER;
7093
7094         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7095
7096         mode->hsync = drm_mode_hsync(mode);
7097         mode->vrefresh = drm_mode_vrefresh(mode);
7098         drm_mode_set_name(mode);
7099 }
7100
7101 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7102 {
7103         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7104         uint32_t pipeconf;
7105
7106         pipeconf = 0;
7107
7108         /* we keep both pipes enabled on 830 */
7109         if (IS_I830(dev_priv))
7110                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7111
7112         if (intel_crtc->config->double_wide)
7113                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7114
7115         /* only g4x and later have fancy bpc/dither controls */
7116         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7117             IS_CHERRYVIEW(dev_priv)) {
7118                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7119                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7120                         pipeconf |= PIPECONF_DITHER_EN |
7121                                     PIPECONF_DITHER_TYPE_SP;
7122
7123                 switch (intel_crtc->config->pipe_bpp) {
7124                 case 18:
7125                         pipeconf |= PIPECONF_6BPC;
7126                         break;
7127                 case 24:
7128                         pipeconf |= PIPECONF_8BPC;
7129                         break;
7130                 case 30:
7131                         pipeconf |= PIPECONF_10BPC;
7132                         break;
7133                 default:
7134                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7135                         BUG();
7136                 }
7137         }
7138
7139         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7140                 if (INTEL_GEN(dev_priv) < 4 ||
7141                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7142                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7143                 else
7144                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7145         } else
7146                 pipeconf |= PIPECONF_PROGRESSIVE;
7147
7148         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7149              intel_crtc->config->limited_color_range)
7150                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7151
7152         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7153         POSTING_READ(PIPECONF(intel_crtc->pipe));
7154 }
7155
7156 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7157                                    struct intel_crtc_state *crtc_state)
7158 {
7159         struct drm_device *dev = crtc->base.dev;
7160         struct drm_i915_private *dev_priv = to_i915(dev);
7161         const struct intel_limit *limit;
7162         int refclk = 48000;
7163
7164         memset(&crtc_state->dpll_hw_state, 0,
7165                sizeof(crtc_state->dpll_hw_state));
7166
7167         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7168                 if (intel_panel_use_ssc(dev_priv)) {
7169                         refclk = dev_priv->vbt.lvds_ssc_freq;
7170                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7171                 }
7172
7173                 limit = &intel_limits_i8xx_lvds;
7174         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7175                 limit = &intel_limits_i8xx_dvo;
7176         } else {
7177                 limit = &intel_limits_i8xx_dac;
7178         }
7179
7180         if (!crtc_state->clock_set &&
7181             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7182                                  refclk, NULL, &crtc_state->dpll)) {
7183                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7184                 return -EINVAL;
7185         }
7186
7187         i8xx_compute_dpll(crtc, crtc_state, NULL);
7188
7189         return 0;
7190 }
7191
7192 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7193                                   struct intel_crtc_state *crtc_state)
7194 {
7195         struct drm_device *dev = crtc->base.dev;
7196         struct drm_i915_private *dev_priv = to_i915(dev);
7197         const struct intel_limit *limit;
7198         int refclk = 96000;
7199
7200         memset(&crtc_state->dpll_hw_state, 0,
7201                sizeof(crtc_state->dpll_hw_state));
7202
7203         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7204                 if (intel_panel_use_ssc(dev_priv)) {
7205                         refclk = dev_priv->vbt.lvds_ssc_freq;
7206                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7207                 }
7208
7209                 if (intel_is_dual_link_lvds(dev))
7210                         limit = &intel_limits_g4x_dual_channel_lvds;
7211                 else
7212                         limit = &intel_limits_g4x_single_channel_lvds;
7213         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7214                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7215                 limit = &intel_limits_g4x_hdmi;
7216         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7217                 limit = &intel_limits_g4x_sdvo;
7218         } else {
7219                 /* The option is for other outputs */
7220                 limit = &intel_limits_i9xx_sdvo;
7221         }
7222
7223         if (!crtc_state->clock_set &&
7224             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7225                                 refclk, NULL, &crtc_state->dpll)) {
7226                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7227                 return -EINVAL;
7228         }
7229
7230         i9xx_compute_dpll(crtc, crtc_state, NULL);
7231
7232         return 0;
7233 }
7234
7235 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7236                                   struct intel_crtc_state *crtc_state)
7237 {
7238         struct drm_device *dev = crtc->base.dev;
7239         struct drm_i915_private *dev_priv = to_i915(dev);
7240         const struct intel_limit *limit;
7241         int refclk = 96000;
7242
7243         memset(&crtc_state->dpll_hw_state, 0,
7244                sizeof(crtc_state->dpll_hw_state));
7245
7246         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7247                 if (intel_panel_use_ssc(dev_priv)) {
7248                         refclk = dev_priv->vbt.lvds_ssc_freq;
7249                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7250                 }
7251
7252                 limit = &intel_limits_pineview_lvds;
7253         } else {
7254                 limit = &intel_limits_pineview_sdvo;
7255         }
7256
7257         if (!crtc_state->clock_set &&
7258             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7259                                 refclk, NULL, &crtc_state->dpll)) {
7260                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7261                 return -EINVAL;
7262         }
7263
7264         i9xx_compute_dpll(crtc, crtc_state, NULL);
7265
7266         return 0;
7267 }
7268
7269 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7270                                    struct intel_crtc_state *crtc_state)
7271 {
7272         struct drm_device *dev = crtc->base.dev;
7273         struct drm_i915_private *dev_priv = to_i915(dev);
7274         const struct intel_limit *limit;
7275         int refclk = 96000;
7276
7277         memset(&crtc_state->dpll_hw_state, 0,
7278                sizeof(crtc_state->dpll_hw_state));
7279
7280         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7281                 if (intel_panel_use_ssc(dev_priv)) {
7282                         refclk = dev_priv->vbt.lvds_ssc_freq;
7283                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7284                 }
7285
7286                 limit = &intel_limits_i9xx_lvds;
7287         } else {
7288                 limit = &intel_limits_i9xx_sdvo;
7289         }
7290
7291         if (!crtc_state->clock_set &&
7292             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7293                                  refclk, NULL, &crtc_state->dpll)) {
7294                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7295                 return -EINVAL;
7296         }
7297
7298         i9xx_compute_dpll(crtc, crtc_state, NULL);
7299
7300         return 0;
7301 }
7302
7303 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7304                                   struct intel_crtc_state *crtc_state)
7305 {
7306         int refclk = 100000;
7307         const struct intel_limit *limit = &intel_limits_chv;
7308
7309         memset(&crtc_state->dpll_hw_state, 0,
7310                sizeof(crtc_state->dpll_hw_state));
7311
7312         if (!crtc_state->clock_set &&
7313             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7314                                 refclk, NULL, &crtc_state->dpll)) {
7315                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7316                 return -EINVAL;
7317         }
7318
7319         chv_compute_dpll(crtc, crtc_state);
7320
7321         return 0;
7322 }
7323
7324 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7325                                   struct intel_crtc_state *crtc_state)
7326 {
7327         int refclk = 100000;
7328         const struct intel_limit *limit = &intel_limits_vlv;
7329
7330         memset(&crtc_state->dpll_hw_state, 0,
7331                sizeof(crtc_state->dpll_hw_state));
7332
7333         if (!crtc_state->clock_set &&
7334             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7335                                 refclk, NULL, &crtc_state->dpll)) {
7336                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7337                 return -EINVAL;
7338         }
7339
7340         vlv_compute_dpll(crtc, crtc_state);
7341
7342         return 0;
7343 }
7344
7345 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7346                                  struct intel_crtc_state *pipe_config)
7347 {
7348         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7349         uint32_t tmp;
7350
7351         if (INTEL_GEN(dev_priv) <= 3 &&
7352             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7353                 return;
7354
7355         tmp = I915_READ(PFIT_CONTROL);
7356         if (!(tmp & PFIT_ENABLE))
7357                 return;
7358
7359         /* Check whether the pfit is attached to our pipe. */
7360         if (INTEL_GEN(dev_priv) < 4) {
7361                 if (crtc->pipe != PIPE_B)
7362                         return;
7363         } else {
7364                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7365                         return;
7366         }
7367
7368         pipe_config->gmch_pfit.control = tmp;
7369         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7370 }
7371
7372 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7373                                struct intel_crtc_state *pipe_config)
7374 {
7375         struct drm_device *dev = crtc->base.dev;
7376         struct drm_i915_private *dev_priv = to_i915(dev);
7377         int pipe = pipe_config->cpu_transcoder;
7378         struct dpll clock;
7379         u32 mdiv;
7380         int refclk = 100000;
7381
7382         /* In case of DSI, DPLL will not be used */
7383         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7384                 return;
7385
7386         mutex_lock(&dev_priv->sb_lock);
7387         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7388         mutex_unlock(&dev_priv->sb_lock);
7389
7390         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7391         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7392         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7393         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7394         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7395
7396         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7397 }
7398
7399 static void
7400 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7401                               struct intel_initial_plane_config *plane_config)
7402 {
7403         struct drm_device *dev = crtc->base.dev;
7404         struct drm_i915_private *dev_priv = to_i915(dev);
7405         u32 val, base, offset;
7406         int pipe = crtc->pipe, plane = crtc->plane;
7407         int fourcc, pixel_format;
7408         unsigned int aligned_height;
7409         struct drm_framebuffer *fb;
7410         struct intel_framebuffer *intel_fb;
7411
7412         val = I915_READ(DSPCNTR(plane));
7413         if (!(val & DISPLAY_PLANE_ENABLE))
7414                 return;
7415
7416         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7417         if (!intel_fb) {
7418                 DRM_DEBUG_KMS("failed to alloc fb\n");
7419                 return;
7420         }
7421
7422         fb = &intel_fb->base;
7423
7424         fb->dev = dev;
7425
7426         if (INTEL_GEN(dev_priv) >= 4) {
7427                 if (val & DISPPLANE_TILED) {
7428                         plane_config->tiling = I915_TILING_X;
7429                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7430                 }
7431         }
7432
7433         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7434         fourcc = i9xx_format_to_fourcc(pixel_format);
7435         fb->format = drm_format_info(fourcc);
7436
7437         if (INTEL_GEN(dev_priv) >= 4) {
7438                 if (plane_config->tiling)
7439                         offset = I915_READ(DSPTILEOFF(plane));
7440                 else
7441                         offset = I915_READ(DSPLINOFF(plane));
7442                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7443         } else {
7444                 base = I915_READ(DSPADDR(plane));
7445         }
7446         plane_config->base = base;
7447
7448         val = I915_READ(PIPESRC(pipe));
7449         fb->width = ((val >> 16) & 0xfff) + 1;
7450         fb->height = ((val >> 0) & 0xfff) + 1;
7451
7452         val = I915_READ(DSPSTRIDE(pipe));
7453         fb->pitches[0] = val & 0xffffffc0;
7454
7455         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7456
7457         plane_config->size = fb->pitches[0] * aligned_height;
7458
7459         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7460                       pipe_name(pipe), plane, fb->width, fb->height,
7461                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7462                       plane_config->size);
7463
7464         plane_config->fb = intel_fb;
7465 }
7466
7467 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7468                                struct intel_crtc_state *pipe_config)
7469 {
7470         struct drm_device *dev = crtc->base.dev;
7471         struct drm_i915_private *dev_priv = to_i915(dev);
7472         int pipe = pipe_config->cpu_transcoder;
7473         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7474         struct dpll clock;
7475         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7476         int refclk = 100000;
7477
7478         /* In case of DSI, DPLL will not be used */
7479         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7480                 return;
7481
7482         mutex_lock(&dev_priv->sb_lock);
7483         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7484         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7485         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7486         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7487         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7488         mutex_unlock(&dev_priv->sb_lock);
7489
7490         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7491         clock.m2 = (pll_dw0 & 0xff) << 22;
7492         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7493                 clock.m2 |= pll_dw2 & 0x3fffff;
7494         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7495         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7496         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7497
7498         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7499 }
7500
7501 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7502                                  struct intel_crtc_state *pipe_config)
7503 {
7504         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7505         enum intel_display_power_domain power_domain;
7506         uint32_t tmp;
7507         bool ret;
7508
7509         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7510         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7511                 return false;
7512
7513         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7514         pipe_config->shared_dpll = NULL;
7515
7516         ret = false;
7517
7518         tmp = I915_READ(PIPECONF(crtc->pipe));
7519         if (!(tmp & PIPECONF_ENABLE))
7520                 goto out;
7521
7522         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7523             IS_CHERRYVIEW(dev_priv)) {
7524                 switch (tmp & PIPECONF_BPC_MASK) {
7525                 case PIPECONF_6BPC:
7526                         pipe_config->pipe_bpp = 18;
7527                         break;
7528                 case PIPECONF_8BPC:
7529                         pipe_config->pipe_bpp = 24;
7530                         break;
7531                 case PIPECONF_10BPC:
7532                         pipe_config->pipe_bpp = 30;
7533                         break;
7534                 default:
7535                         break;
7536                 }
7537         }
7538
7539         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7540             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7541                 pipe_config->limited_color_range = true;
7542
7543         if (INTEL_GEN(dev_priv) < 4)
7544                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7545
7546         intel_get_pipe_timings(crtc, pipe_config);
7547         intel_get_pipe_src_size(crtc, pipe_config);
7548
7549         i9xx_get_pfit_config(crtc, pipe_config);
7550
7551         if (INTEL_GEN(dev_priv) >= 4) {
7552                 /* No way to read it out on pipes B and C */
7553                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7554                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7555                 else
7556                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7557                 pipe_config->pixel_multiplier =
7558                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7559                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7560                 pipe_config->dpll_hw_state.dpll_md = tmp;
7561         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7562                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7563                 tmp = I915_READ(DPLL(crtc->pipe));
7564                 pipe_config->pixel_multiplier =
7565                         ((tmp & SDVO_MULTIPLIER_MASK)
7566                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7567         } else {
7568                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7569                  * port and will be fixed up in the encoder->get_config
7570                  * function. */
7571                 pipe_config->pixel_multiplier = 1;
7572         }
7573         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7574         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7575                 /*
7576                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7577                  * on 830. Filter it out here so that we don't
7578                  * report errors due to that.
7579                  */
7580                 if (IS_I830(dev_priv))
7581                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7582
7583                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7584                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7585         } else {
7586                 /* Mask out read-only status bits. */
7587                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7588                                                      DPLL_PORTC_READY_MASK |
7589                                                      DPLL_PORTB_READY_MASK);
7590         }
7591
7592         if (IS_CHERRYVIEW(dev_priv))
7593                 chv_crtc_clock_get(crtc, pipe_config);
7594         else if (IS_VALLEYVIEW(dev_priv))
7595                 vlv_crtc_clock_get(crtc, pipe_config);
7596         else
7597                 i9xx_crtc_clock_get(crtc, pipe_config);
7598
7599         /*
7600          * Normally the dotclock is filled in by the encoder .get_config()
7601          * but in case the pipe is enabled w/o any ports we need a sane
7602          * default.
7603          */
7604         pipe_config->base.adjusted_mode.crtc_clock =
7605                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7606
7607         ret = true;
7608
7609 out:
7610         intel_display_power_put(dev_priv, power_domain);
7611
7612         return ret;
7613 }
7614
7615 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7616 {
7617         struct intel_encoder *encoder;
7618         int i;
7619         u32 val, final;
7620         bool has_lvds = false;
7621         bool has_cpu_edp = false;
7622         bool has_panel = false;
7623         bool has_ck505 = false;
7624         bool can_ssc = false;
7625         bool using_ssc_source = false;
7626
7627         /* We need to take the global config into account */
7628         for_each_intel_encoder(&dev_priv->drm, encoder) {
7629                 switch (encoder->type) {
7630                 case INTEL_OUTPUT_LVDS:
7631                         has_panel = true;
7632                         has_lvds = true;
7633                         break;
7634                 case INTEL_OUTPUT_EDP:
7635                         has_panel = true;
7636                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7637                                 has_cpu_edp = true;
7638                         break;
7639                 default:
7640                         break;
7641                 }
7642         }
7643
7644         if (HAS_PCH_IBX(dev_priv)) {
7645                 has_ck505 = dev_priv->vbt.display_clock_mode;
7646                 can_ssc = has_ck505;
7647         } else {
7648                 has_ck505 = false;
7649                 can_ssc = true;
7650         }
7651
7652         /* Check if any DPLLs are using the SSC source */
7653         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7654                 u32 temp = I915_READ(PCH_DPLL(i));
7655
7656                 if (!(temp & DPLL_VCO_ENABLE))
7657                         continue;
7658
7659                 if ((temp & PLL_REF_INPUT_MASK) ==
7660                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7661                         using_ssc_source = true;
7662                         break;
7663                 }
7664         }
7665
7666         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7667                       has_panel, has_lvds, has_ck505, using_ssc_source);
7668
7669         /* Ironlake: try to setup display ref clock before DPLL
7670          * enabling. This is only under driver's control after
7671          * PCH B stepping, previous chipset stepping should be
7672          * ignoring this setting.
7673          */
7674         val = I915_READ(PCH_DREF_CONTROL);
7675
7676         /* As we must carefully and slowly disable/enable each source in turn,
7677          * compute the final state we want first and check if we need to
7678          * make any changes at all.
7679          */
7680         final = val;
7681         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7682         if (has_ck505)
7683                 final |= DREF_NONSPREAD_CK505_ENABLE;
7684         else
7685                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7686
7687         final &= ~DREF_SSC_SOURCE_MASK;
7688         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7689         final &= ~DREF_SSC1_ENABLE;
7690
7691         if (has_panel) {
7692                 final |= DREF_SSC_SOURCE_ENABLE;
7693
7694                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7695                         final |= DREF_SSC1_ENABLE;
7696
7697                 if (has_cpu_edp) {
7698                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7699                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7700                         else
7701                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7702                 } else
7703                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7704         } else if (using_ssc_source) {
7705                 final |= DREF_SSC_SOURCE_ENABLE;
7706                 final |= DREF_SSC1_ENABLE;
7707         }
7708
7709         if (final == val)
7710                 return;
7711
7712         /* Always enable nonspread source */
7713         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7714
7715         if (has_ck505)
7716                 val |= DREF_NONSPREAD_CK505_ENABLE;
7717         else
7718                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7719
7720         if (has_panel) {
7721                 val &= ~DREF_SSC_SOURCE_MASK;
7722                 val |= DREF_SSC_SOURCE_ENABLE;
7723
7724                 /* SSC must be turned on before enabling the CPU output  */
7725                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7726                         DRM_DEBUG_KMS("Using SSC on panel\n");
7727                         val |= DREF_SSC1_ENABLE;
7728                 } else
7729                         val &= ~DREF_SSC1_ENABLE;
7730
7731                 /* Get SSC going before enabling the outputs */
7732                 I915_WRITE(PCH_DREF_CONTROL, val);
7733                 POSTING_READ(PCH_DREF_CONTROL);
7734                 udelay(200);
7735
7736                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7737
7738                 /* Enable CPU source on CPU attached eDP */
7739                 if (has_cpu_edp) {
7740                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7741                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7742                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7743                         } else
7744                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7745                 } else
7746                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7747
7748                 I915_WRITE(PCH_DREF_CONTROL, val);
7749                 POSTING_READ(PCH_DREF_CONTROL);
7750                 udelay(200);
7751         } else {
7752                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7753
7754                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7755
7756                 /* Turn off CPU output */
7757                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7758
7759                 I915_WRITE(PCH_DREF_CONTROL, val);
7760                 POSTING_READ(PCH_DREF_CONTROL);
7761                 udelay(200);
7762
7763                 if (!using_ssc_source) {
7764                         DRM_DEBUG_KMS("Disabling SSC source\n");
7765
7766                         /* Turn off the SSC source */
7767                         val &= ~DREF_SSC_SOURCE_MASK;
7768                         val |= DREF_SSC_SOURCE_DISABLE;
7769
7770                         /* Turn off SSC1 */
7771                         val &= ~DREF_SSC1_ENABLE;
7772
7773                         I915_WRITE(PCH_DREF_CONTROL, val);
7774                         POSTING_READ(PCH_DREF_CONTROL);
7775                         udelay(200);
7776                 }
7777         }
7778
7779         BUG_ON(val != final);
7780 }
7781
7782 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7783 {
7784         uint32_t tmp;
7785
7786         tmp = I915_READ(SOUTH_CHICKEN2);
7787         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7788         I915_WRITE(SOUTH_CHICKEN2, tmp);
7789
7790         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7791                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7792                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7793
7794         tmp = I915_READ(SOUTH_CHICKEN2);
7795         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7796         I915_WRITE(SOUTH_CHICKEN2, tmp);
7797
7798         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7799                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7800                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7801 }
7802
7803 /* WaMPhyProgramming:hsw */
7804 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7805 {
7806         uint32_t tmp;
7807
7808         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7809         tmp &= ~(0xFF << 24);
7810         tmp |= (0x12 << 24);
7811         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7812
7813         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7814         tmp |= (1 << 11);
7815         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7816
7817         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7818         tmp |= (1 << 11);
7819         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7820
7821         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7822         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7823         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7824
7825         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7826         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7827         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7828
7829         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7830         tmp &= ~(7 << 13);
7831         tmp |= (5 << 13);
7832         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7833
7834         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7835         tmp &= ~(7 << 13);
7836         tmp |= (5 << 13);
7837         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7838
7839         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7840         tmp &= ~0xFF;
7841         tmp |= 0x1C;
7842         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7843
7844         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7845         tmp &= ~0xFF;
7846         tmp |= 0x1C;
7847         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7848
7849         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7850         tmp &= ~(0xFF << 16);
7851         tmp |= (0x1C << 16);
7852         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7853
7854         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7855         tmp &= ~(0xFF << 16);
7856         tmp |= (0x1C << 16);
7857         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7858
7859         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7860         tmp |= (1 << 27);
7861         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7862
7863         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7864         tmp |= (1 << 27);
7865         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7866
7867         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7868         tmp &= ~(0xF << 28);
7869         tmp |= (4 << 28);
7870         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7871
7872         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7873         tmp &= ~(0xF << 28);
7874         tmp |= (4 << 28);
7875         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7876 }
7877
7878 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7879  * Programming" based on the parameters passed:
7880  * - Sequence to enable CLKOUT_DP
7881  * - Sequence to enable CLKOUT_DP without spread
7882  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7883  */
7884 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7885                                  bool with_spread, bool with_fdi)
7886 {
7887         uint32_t reg, tmp;
7888
7889         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7890                 with_spread = true;
7891         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7892             with_fdi, "LP PCH doesn't have FDI\n"))
7893                 with_fdi = false;
7894
7895         mutex_lock(&dev_priv->sb_lock);
7896
7897         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7898         tmp &= ~SBI_SSCCTL_DISABLE;
7899         tmp |= SBI_SSCCTL_PATHALT;
7900         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7901
7902         udelay(24);
7903
7904         if (with_spread) {
7905                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7906                 tmp &= ~SBI_SSCCTL_PATHALT;
7907                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7908
7909                 if (with_fdi) {
7910                         lpt_reset_fdi_mphy(dev_priv);
7911                         lpt_program_fdi_mphy(dev_priv);
7912                 }
7913         }
7914
7915         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7916         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7917         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7918         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7919
7920         mutex_unlock(&dev_priv->sb_lock);
7921 }
7922
7923 /* Sequence to disable CLKOUT_DP */
7924 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7925 {
7926         uint32_t reg, tmp;
7927
7928         mutex_lock(&dev_priv->sb_lock);
7929
7930         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7931         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7932         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7933         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7934
7935         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7936         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7937                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7938                         tmp |= SBI_SSCCTL_PATHALT;
7939                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7940                         udelay(32);
7941                 }
7942                 tmp |= SBI_SSCCTL_DISABLE;
7943                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7944         }
7945
7946         mutex_unlock(&dev_priv->sb_lock);
7947 }
7948
7949 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7950
7951 static const uint16_t sscdivintphase[] = {
7952         [BEND_IDX( 50)] = 0x3B23,
7953         [BEND_IDX( 45)] = 0x3B23,
7954         [BEND_IDX( 40)] = 0x3C23,
7955         [BEND_IDX( 35)] = 0x3C23,
7956         [BEND_IDX( 30)] = 0x3D23,
7957         [BEND_IDX( 25)] = 0x3D23,
7958         [BEND_IDX( 20)] = 0x3E23,
7959         [BEND_IDX( 15)] = 0x3E23,
7960         [BEND_IDX( 10)] = 0x3F23,
7961         [BEND_IDX(  5)] = 0x3F23,
7962         [BEND_IDX(  0)] = 0x0025,
7963         [BEND_IDX( -5)] = 0x0025,
7964         [BEND_IDX(-10)] = 0x0125,
7965         [BEND_IDX(-15)] = 0x0125,
7966         [BEND_IDX(-20)] = 0x0225,
7967         [BEND_IDX(-25)] = 0x0225,
7968         [BEND_IDX(-30)] = 0x0325,
7969         [BEND_IDX(-35)] = 0x0325,
7970         [BEND_IDX(-40)] = 0x0425,
7971         [BEND_IDX(-45)] = 0x0425,
7972         [BEND_IDX(-50)] = 0x0525,
7973 };
7974
7975 /*
7976  * Bend CLKOUT_DP
7977  * steps -50 to 50 inclusive, in steps of 5
7978  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7979  * change in clock period = -(steps / 10) * 5.787 ps
7980  */
7981 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7982 {
7983         uint32_t tmp;
7984         int idx = BEND_IDX(steps);
7985
7986         if (WARN_ON(steps % 5 != 0))
7987                 return;
7988
7989         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7990                 return;
7991
7992         mutex_lock(&dev_priv->sb_lock);
7993
7994         if (steps % 10 != 0)
7995                 tmp = 0xAAAAAAAB;
7996         else
7997                 tmp = 0x00000000;
7998         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7999
8000         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8001         tmp &= 0xffff0000;
8002         tmp |= sscdivintphase[idx];
8003         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8004
8005         mutex_unlock(&dev_priv->sb_lock);
8006 }
8007
8008 #undef BEND_IDX
8009
8010 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8011 {
8012         struct intel_encoder *encoder;
8013         bool has_vga = false;
8014
8015         for_each_intel_encoder(&dev_priv->drm, encoder) {
8016                 switch (encoder->type) {
8017                 case INTEL_OUTPUT_ANALOG:
8018                         has_vga = true;
8019                         break;
8020                 default:
8021                         break;
8022                 }
8023         }
8024
8025         if (has_vga) {
8026                 lpt_bend_clkout_dp(dev_priv, 0);
8027                 lpt_enable_clkout_dp(dev_priv, true, true);
8028         } else {
8029                 lpt_disable_clkout_dp(dev_priv);
8030         }
8031 }
8032
8033 /*
8034  * Initialize reference clocks when the driver loads
8035  */
8036 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8037 {
8038         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8039                 ironlake_init_pch_refclk(dev_priv);
8040         else if (HAS_PCH_LPT(dev_priv))
8041                 lpt_init_pch_refclk(dev_priv);
8042 }
8043
8044 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8045 {
8046         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8048         int pipe = intel_crtc->pipe;
8049         uint32_t val;
8050
8051         val = 0;
8052
8053         switch (intel_crtc->config->pipe_bpp) {
8054         case 18:
8055                 val |= PIPECONF_6BPC;
8056                 break;
8057         case 24:
8058                 val |= PIPECONF_8BPC;
8059                 break;
8060         case 30:
8061                 val |= PIPECONF_10BPC;
8062                 break;
8063         case 36:
8064                 val |= PIPECONF_12BPC;
8065                 break;
8066         default:
8067                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8068                 BUG();
8069         }
8070
8071         if (intel_crtc->config->dither)
8072                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8073
8074         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8075                 val |= PIPECONF_INTERLACED_ILK;
8076         else
8077                 val |= PIPECONF_PROGRESSIVE;
8078
8079         if (intel_crtc->config->limited_color_range)
8080                 val |= PIPECONF_COLOR_RANGE_SELECT;
8081
8082         I915_WRITE(PIPECONF(pipe), val);
8083         POSTING_READ(PIPECONF(pipe));
8084 }
8085
8086 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8087 {
8088         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8090         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8091         u32 val = 0;
8092
8093         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8094                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8095
8096         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8097                 val |= PIPECONF_INTERLACED_ILK;
8098         else
8099                 val |= PIPECONF_PROGRESSIVE;
8100
8101         I915_WRITE(PIPECONF(cpu_transcoder), val);
8102         POSTING_READ(PIPECONF(cpu_transcoder));
8103 }
8104
8105 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8106 {
8107         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8109         struct intel_crtc_state *config = intel_crtc->config;
8110
8111         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8112                 u32 val = 0;
8113
8114                 switch (intel_crtc->config->pipe_bpp) {
8115                 case 18:
8116                         val |= PIPEMISC_DITHER_6_BPC;
8117                         break;
8118                 case 24:
8119                         val |= PIPEMISC_DITHER_8_BPC;
8120                         break;
8121                 case 30:
8122                         val |= PIPEMISC_DITHER_10_BPC;
8123                         break;
8124                 case 36:
8125                         val |= PIPEMISC_DITHER_12_BPC;
8126                         break;
8127                 default:
8128                         /* Case prevented by pipe_config_set_bpp. */
8129                         BUG();
8130                 }
8131
8132                 if (intel_crtc->config->dither)
8133                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8134
8135                 if (config->ycbcr420) {
8136                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8137                                 PIPEMISC_YUV420_ENABLE |
8138                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8139                 }
8140
8141                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8142         }
8143 }
8144
8145 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8146 {
8147         /*
8148          * Account for spread spectrum to avoid
8149          * oversubscribing the link. Max center spread
8150          * is 2.5%; use 5% for safety's sake.
8151          */
8152         u32 bps = target_clock * bpp * 21 / 20;
8153         return DIV_ROUND_UP(bps, link_bw * 8);
8154 }
8155
8156 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8157 {
8158         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8159 }
8160
8161 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8162                                   struct intel_crtc_state *crtc_state,
8163                                   struct dpll *reduced_clock)
8164 {
8165         struct drm_crtc *crtc = &intel_crtc->base;
8166         struct drm_device *dev = crtc->dev;
8167         struct drm_i915_private *dev_priv = to_i915(dev);
8168         u32 dpll, fp, fp2;
8169         int factor;
8170
8171         /* Enable autotuning of the PLL clock (if permissible) */
8172         factor = 21;
8173         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8174                 if ((intel_panel_use_ssc(dev_priv) &&
8175                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8176                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8177                         factor = 25;
8178         } else if (crtc_state->sdvo_tv_clock)
8179                 factor = 20;
8180
8181         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8182
8183         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8184                 fp |= FP_CB_TUNE;
8185
8186         if (reduced_clock) {
8187                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8188
8189                 if (reduced_clock->m < factor * reduced_clock->n)
8190                         fp2 |= FP_CB_TUNE;
8191         } else {
8192                 fp2 = fp;
8193         }
8194
8195         dpll = 0;
8196
8197         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8198                 dpll |= DPLLB_MODE_LVDS;
8199         else
8200                 dpll |= DPLLB_MODE_DAC_SERIAL;
8201
8202         dpll |= (crtc_state->pixel_multiplier - 1)
8203                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8204
8205         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8206             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8207                 dpll |= DPLL_SDVO_HIGH_SPEED;
8208
8209         if (intel_crtc_has_dp_encoder(crtc_state))
8210                 dpll |= DPLL_SDVO_HIGH_SPEED;
8211
8212         /*
8213          * The high speed IO clock is only really required for
8214          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8215          * possible to share the DPLL between CRT and HDMI. Enabling
8216          * the clock needlessly does no real harm, except use up a
8217          * bit of power potentially.
8218          *
8219          * We'll limit this to IVB with 3 pipes, since it has only two
8220          * DPLLs and so DPLL sharing is the only way to get three pipes
8221          * driving PCH ports at the same time. On SNB we could do this,
8222          * and potentially avoid enabling the second DPLL, but it's not
8223          * clear if it''s a win or loss power wise. No point in doing
8224          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8225          */
8226         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8227             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8228                 dpll |= DPLL_SDVO_HIGH_SPEED;
8229
8230         /* compute bitmask from p1 value */
8231         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8232         /* also FPA1 */
8233         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8234
8235         switch (crtc_state->dpll.p2) {
8236         case 5:
8237                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8238                 break;
8239         case 7:
8240                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8241                 break;
8242         case 10:
8243                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8244                 break;
8245         case 14:
8246                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8247                 break;
8248         }
8249
8250         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8251             intel_panel_use_ssc(dev_priv))
8252                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8253         else
8254                 dpll |= PLL_REF_INPUT_DREFCLK;
8255
8256         dpll |= DPLL_VCO_ENABLE;
8257
8258         crtc_state->dpll_hw_state.dpll = dpll;
8259         crtc_state->dpll_hw_state.fp0 = fp;
8260         crtc_state->dpll_hw_state.fp1 = fp2;
8261 }
8262
8263 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8264                                        struct intel_crtc_state *crtc_state)
8265 {
8266         struct drm_device *dev = crtc->base.dev;
8267         struct drm_i915_private *dev_priv = to_i915(dev);
8268         const struct intel_limit *limit;
8269         int refclk = 120000;
8270
8271         memset(&crtc_state->dpll_hw_state, 0,
8272                sizeof(crtc_state->dpll_hw_state));
8273
8274         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8275         if (!crtc_state->has_pch_encoder)
8276                 return 0;
8277
8278         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8279                 if (intel_panel_use_ssc(dev_priv)) {
8280                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8281                                       dev_priv->vbt.lvds_ssc_freq);
8282                         refclk = dev_priv->vbt.lvds_ssc_freq;
8283                 }
8284
8285                 if (intel_is_dual_link_lvds(dev)) {
8286                         if (refclk == 100000)
8287                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8288                         else
8289                                 limit = &intel_limits_ironlake_dual_lvds;
8290                 } else {
8291                         if (refclk == 100000)
8292                                 limit = &intel_limits_ironlake_single_lvds_100m;
8293                         else
8294                                 limit = &intel_limits_ironlake_single_lvds;
8295                 }
8296         } else {
8297                 limit = &intel_limits_ironlake_dac;
8298         }
8299
8300         if (!crtc_state->clock_set &&
8301             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8302                                 refclk, NULL, &crtc_state->dpll)) {
8303                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8304                 return -EINVAL;
8305         }
8306
8307         ironlake_compute_dpll(crtc, crtc_state, NULL);
8308
8309         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8310                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8311                                  pipe_name(crtc->pipe));
8312                 return -EINVAL;
8313         }
8314
8315         return 0;
8316 }
8317
8318 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8319                                          struct intel_link_m_n *m_n)
8320 {
8321         struct drm_device *dev = crtc->base.dev;
8322         struct drm_i915_private *dev_priv = to_i915(dev);
8323         enum pipe pipe = crtc->pipe;
8324
8325         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8326         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8327         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8328                 & ~TU_SIZE_MASK;
8329         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8330         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8331                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8332 }
8333
8334 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8335                                          enum transcoder transcoder,
8336                                          struct intel_link_m_n *m_n,
8337                                          struct intel_link_m_n *m2_n2)
8338 {
8339         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8340         enum pipe pipe = crtc->pipe;
8341
8342         if (INTEL_GEN(dev_priv) >= 5) {
8343                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8344                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8345                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8346                         & ~TU_SIZE_MASK;
8347                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8348                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8349                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8350                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8351                  * gen < 8) and if DRRS is supported (to make sure the
8352                  * registers are not unnecessarily read).
8353                  */
8354                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8355                         crtc->config->has_drrs) {
8356                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8357                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8358                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8359                                         & ~TU_SIZE_MASK;
8360                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8361                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8362                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8363                 }
8364         } else {
8365                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8366                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8367                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8368                         & ~TU_SIZE_MASK;
8369                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8370                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8371                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8372         }
8373 }
8374
8375 void intel_dp_get_m_n(struct intel_crtc *crtc,
8376                       struct intel_crtc_state *pipe_config)
8377 {
8378         if (pipe_config->has_pch_encoder)
8379                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8380         else
8381                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8382                                              &pipe_config->dp_m_n,
8383                                              &pipe_config->dp_m2_n2);
8384 }
8385
8386 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8387                                         struct intel_crtc_state *pipe_config)
8388 {
8389         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8390                                      &pipe_config->fdi_m_n, NULL);
8391 }
8392
8393 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8394                                     struct intel_crtc_state *pipe_config)
8395 {
8396         struct drm_device *dev = crtc->base.dev;
8397         struct drm_i915_private *dev_priv = to_i915(dev);
8398         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8399         uint32_t ps_ctrl = 0;
8400         int id = -1;
8401         int i;
8402
8403         /* find scaler attached to this pipe */
8404         for (i = 0; i < crtc->num_scalers; i++) {
8405                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8406                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8407                         id = i;
8408                         pipe_config->pch_pfit.enabled = true;
8409                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8410                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8411                         break;
8412                 }
8413         }
8414
8415         scaler_state->scaler_id = id;
8416         if (id >= 0) {
8417                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8418         } else {
8419                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8420         }
8421 }
8422
8423 static void
8424 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8425                                  struct intel_initial_plane_config *plane_config)
8426 {
8427         struct drm_device *dev = crtc->base.dev;
8428         struct drm_i915_private *dev_priv = to_i915(dev);
8429         u32 val, base, offset, stride_mult, tiling;
8430         int pipe = crtc->pipe;
8431         int fourcc, pixel_format;
8432         unsigned int aligned_height;
8433         struct drm_framebuffer *fb;
8434         struct intel_framebuffer *intel_fb;
8435
8436         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8437         if (!intel_fb) {
8438                 DRM_DEBUG_KMS("failed to alloc fb\n");
8439                 return;
8440         }
8441
8442         fb = &intel_fb->base;
8443
8444         fb->dev = dev;
8445
8446         val = I915_READ(PLANE_CTL(pipe, 0));
8447         if (!(val & PLANE_CTL_ENABLE))
8448                 goto error;
8449
8450         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8451         fourcc = skl_format_to_fourcc(pixel_format,
8452                                       val & PLANE_CTL_ORDER_RGBX,
8453                                       val & PLANE_CTL_ALPHA_MASK);
8454         fb->format = drm_format_info(fourcc);
8455
8456         tiling = val & PLANE_CTL_TILED_MASK;
8457         switch (tiling) {
8458         case PLANE_CTL_TILED_LINEAR:
8459                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8460                 break;
8461         case PLANE_CTL_TILED_X:
8462                 plane_config->tiling = I915_TILING_X;
8463                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8464                 break;
8465         case PLANE_CTL_TILED_Y:
8466                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8467                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8468                 else
8469                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
8470                 break;
8471         case PLANE_CTL_TILED_YF:
8472                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8473                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8474                 else
8475                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8476                 break;
8477         default:
8478                 MISSING_CASE(tiling);
8479                 goto error;
8480         }
8481
8482         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8483         plane_config->base = base;
8484
8485         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8486
8487         val = I915_READ(PLANE_SIZE(pipe, 0));
8488         fb->height = ((val >> 16) & 0xfff) + 1;
8489         fb->width = ((val >> 0) & 0x1fff) + 1;
8490
8491         val = I915_READ(PLANE_STRIDE(pipe, 0));
8492         stride_mult = intel_fb_stride_alignment(fb, 0);
8493         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8494
8495         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8496
8497         plane_config->size = fb->pitches[0] * aligned_height;
8498
8499         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8500                       pipe_name(pipe), fb->width, fb->height,
8501                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8502                       plane_config->size);
8503
8504         plane_config->fb = intel_fb;
8505         return;
8506
8507 error:
8508         kfree(intel_fb);
8509 }
8510
8511 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8512                                      struct intel_crtc_state *pipe_config)
8513 {
8514         struct drm_device *dev = crtc->base.dev;
8515         struct drm_i915_private *dev_priv = to_i915(dev);
8516         uint32_t tmp;
8517
8518         tmp = I915_READ(PF_CTL(crtc->pipe));
8519
8520         if (tmp & PF_ENABLE) {
8521                 pipe_config->pch_pfit.enabled = true;
8522                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8523                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8524
8525                 /* We currently do not free assignements of panel fitters on
8526                  * ivb/hsw (since we don't use the higher upscaling modes which
8527                  * differentiates them) so just WARN about this case for now. */
8528                 if (IS_GEN7(dev_priv)) {
8529                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8530                                 PF_PIPE_SEL_IVB(crtc->pipe));
8531                 }
8532         }
8533 }
8534
8535 static void
8536 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8537                                   struct intel_initial_plane_config *plane_config)
8538 {
8539         struct drm_device *dev = crtc->base.dev;
8540         struct drm_i915_private *dev_priv = to_i915(dev);
8541         u32 val, base, offset;
8542         int pipe = crtc->pipe;
8543         int fourcc, pixel_format;
8544         unsigned int aligned_height;
8545         struct drm_framebuffer *fb;
8546         struct intel_framebuffer *intel_fb;
8547
8548         val = I915_READ(DSPCNTR(pipe));
8549         if (!(val & DISPLAY_PLANE_ENABLE))
8550                 return;
8551
8552         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8553         if (!intel_fb) {
8554                 DRM_DEBUG_KMS("failed to alloc fb\n");
8555                 return;
8556         }
8557
8558         fb = &intel_fb->base;
8559
8560         fb->dev = dev;
8561
8562         if (INTEL_GEN(dev_priv) >= 4) {
8563                 if (val & DISPPLANE_TILED) {
8564                         plane_config->tiling = I915_TILING_X;
8565                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8566                 }
8567         }
8568
8569         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8570         fourcc = i9xx_format_to_fourcc(pixel_format);
8571         fb->format = drm_format_info(fourcc);
8572
8573         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8574         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8575                 offset = I915_READ(DSPOFFSET(pipe));
8576         } else {
8577                 if (plane_config->tiling)
8578                         offset = I915_READ(DSPTILEOFF(pipe));
8579                 else
8580                         offset = I915_READ(DSPLINOFF(pipe));
8581         }
8582         plane_config->base = base;
8583
8584         val = I915_READ(PIPESRC(pipe));
8585         fb->width = ((val >> 16) & 0xfff) + 1;
8586         fb->height = ((val >> 0) & 0xfff) + 1;
8587
8588         val = I915_READ(DSPSTRIDE(pipe));
8589         fb->pitches[0] = val & 0xffffffc0;
8590
8591         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8592
8593         plane_config->size = fb->pitches[0] * aligned_height;
8594
8595         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8596                       pipe_name(pipe), fb->width, fb->height,
8597                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8598                       plane_config->size);
8599
8600         plane_config->fb = intel_fb;
8601 }
8602
8603 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8604                                      struct intel_crtc_state *pipe_config)
8605 {
8606         struct drm_device *dev = crtc->base.dev;
8607         struct drm_i915_private *dev_priv = to_i915(dev);
8608         enum intel_display_power_domain power_domain;
8609         uint32_t tmp;
8610         bool ret;
8611
8612         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8613         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8614                 return false;
8615
8616         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8617         pipe_config->shared_dpll = NULL;
8618
8619         ret = false;
8620         tmp = I915_READ(PIPECONF(crtc->pipe));
8621         if (!(tmp & PIPECONF_ENABLE))
8622                 goto out;
8623
8624         switch (tmp & PIPECONF_BPC_MASK) {
8625         case PIPECONF_6BPC:
8626                 pipe_config->pipe_bpp = 18;
8627                 break;
8628         case PIPECONF_8BPC:
8629                 pipe_config->pipe_bpp = 24;
8630                 break;
8631         case PIPECONF_10BPC:
8632                 pipe_config->pipe_bpp = 30;
8633                 break;
8634         case PIPECONF_12BPC:
8635                 pipe_config->pipe_bpp = 36;
8636                 break;
8637         default:
8638                 break;
8639         }
8640
8641         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8642                 pipe_config->limited_color_range = true;
8643
8644         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8645                 struct intel_shared_dpll *pll;
8646                 enum intel_dpll_id pll_id;
8647
8648                 pipe_config->has_pch_encoder = true;
8649
8650                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8651                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8652                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8653
8654                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8655
8656                 if (HAS_PCH_IBX(dev_priv)) {
8657                         /*
8658                          * The pipe->pch transcoder and pch transcoder->pll
8659                          * mapping is fixed.
8660                          */
8661                         pll_id = (enum intel_dpll_id) crtc->pipe;
8662                 } else {
8663                         tmp = I915_READ(PCH_DPLL_SEL);
8664                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8665                                 pll_id = DPLL_ID_PCH_PLL_B;
8666                         else
8667                                 pll_id= DPLL_ID_PCH_PLL_A;
8668                 }
8669
8670                 pipe_config->shared_dpll =
8671                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8672                 pll = pipe_config->shared_dpll;
8673
8674                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8675                                                  &pipe_config->dpll_hw_state));
8676
8677                 tmp = pipe_config->dpll_hw_state.dpll;
8678                 pipe_config->pixel_multiplier =
8679                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8680                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8681
8682                 ironlake_pch_clock_get(crtc, pipe_config);
8683         } else {
8684                 pipe_config->pixel_multiplier = 1;
8685         }
8686
8687         intel_get_pipe_timings(crtc, pipe_config);
8688         intel_get_pipe_src_size(crtc, pipe_config);
8689
8690         ironlake_get_pfit_config(crtc, pipe_config);
8691
8692         ret = true;
8693
8694 out:
8695         intel_display_power_put(dev_priv, power_domain);
8696
8697         return ret;
8698 }
8699
8700 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8701 {
8702         struct drm_device *dev = &dev_priv->drm;
8703         struct intel_crtc *crtc;
8704
8705         for_each_intel_crtc(dev, crtc)
8706                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8707                      pipe_name(crtc->pipe));
8708
8709         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8710                         "Display power well on\n");
8711         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8712         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8713         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8714         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8715         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8716              "CPU PWM1 enabled\n");
8717         if (IS_HASWELL(dev_priv))
8718                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8719                      "CPU PWM2 enabled\n");
8720         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8721              "PCH PWM1 enabled\n");
8722         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8723              "Utility pin enabled\n");
8724         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8725
8726         /*
8727          * In theory we can still leave IRQs enabled, as long as only the HPD
8728          * interrupts remain enabled. We used to check for that, but since it's
8729          * gen-specific and since we only disable LCPLL after we fully disable
8730          * the interrupts, the check below should be enough.
8731          */
8732         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8733 }
8734
8735 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8736 {
8737         if (IS_HASWELL(dev_priv))
8738                 return I915_READ(D_COMP_HSW);
8739         else
8740                 return I915_READ(D_COMP_BDW);
8741 }
8742
8743 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8744 {
8745         if (IS_HASWELL(dev_priv)) {
8746                 mutex_lock(&dev_priv->pcu_lock);
8747                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8748                                             val))
8749                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8750                 mutex_unlock(&dev_priv->pcu_lock);
8751         } else {
8752                 I915_WRITE(D_COMP_BDW, val);
8753                 POSTING_READ(D_COMP_BDW);
8754         }
8755 }
8756
8757 /*
8758  * This function implements pieces of two sequences from BSpec:
8759  * - Sequence for display software to disable LCPLL
8760  * - Sequence for display software to allow package C8+
8761  * The steps implemented here are just the steps that actually touch the LCPLL
8762  * register. Callers should take care of disabling all the display engine
8763  * functions, doing the mode unset, fixing interrupts, etc.
8764  */
8765 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8766                               bool switch_to_fclk, bool allow_power_down)
8767 {
8768         uint32_t val;
8769
8770         assert_can_disable_lcpll(dev_priv);
8771
8772         val = I915_READ(LCPLL_CTL);
8773
8774         if (switch_to_fclk) {
8775                 val |= LCPLL_CD_SOURCE_FCLK;
8776                 I915_WRITE(LCPLL_CTL, val);
8777
8778                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8779                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8780                         DRM_ERROR("Switching to FCLK failed\n");
8781
8782                 val = I915_READ(LCPLL_CTL);
8783         }
8784
8785         val |= LCPLL_PLL_DISABLE;
8786         I915_WRITE(LCPLL_CTL, val);
8787         POSTING_READ(LCPLL_CTL);
8788
8789         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8790                 DRM_ERROR("LCPLL still locked\n");
8791
8792         val = hsw_read_dcomp(dev_priv);
8793         val |= D_COMP_COMP_DISABLE;
8794         hsw_write_dcomp(dev_priv, val);
8795         ndelay(100);
8796
8797         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8798                      1))
8799                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8800
8801         if (allow_power_down) {
8802                 val = I915_READ(LCPLL_CTL);
8803                 val |= LCPLL_POWER_DOWN_ALLOW;
8804                 I915_WRITE(LCPLL_CTL, val);
8805                 POSTING_READ(LCPLL_CTL);
8806         }
8807 }
8808
8809 /*
8810  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8811  * source.
8812  */
8813 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8814 {
8815         uint32_t val;
8816
8817         val = I915_READ(LCPLL_CTL);
8818
8819         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8820                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8821                 return;
8822
8823         /*
8824          * Make sure we're not on PC8 state before disabling PC8, otherwise
8825          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8826          */
8827         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8828
8829         if (val & LCPLL_POWER_DOWN_ALLOW) {
8830                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8831                 I915_WRITE(LCPLL_CTL, val);
8832                 POSTING_READ(LCPLL_CTL);
8833         }
8834
8835         val = hsw_read_dcomp(dev_priv);
8836         val |= D_COMP_COMP_FORCE;
8837         val &= ~D_COMP_COMP_DISABLE;
8838         hsw_write_dcomp(dev_priv, val);
8839
8840         val = I915_READ(LCPLL_CTL);
8841         val &= ~LCPLL_PLL_DISABLE;
8842         I915_WRITE(LCPLL_CTL, val);
8843
8844         if (intel_wait_for_register(dev_priv,
8845                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8846                                     5))
8847                 DRM_ERROR("LCPLL not locked yet\n");
8848
8849         if (val & LCPLL_CD_SOURCE_FCLK) {
8850                 val = I915_READ(LCPLL_CTL);
8851                 val &= ~LCPLL_CD_SOURCE_FCLK;
8852                 I915_WRITE(LCPLL_CTL, val);
8853
8854                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8855                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8856                         DRM_ERROR("Switching back to LCPLL failed\n");
8857         }
8858
8859         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8860         intel_update_cdclk(dev_priv);
8861 }
8862
8863 /*
8864  * Package states C8 and deeper are really deep PC states that can only be
8865  * reached when all the devices on the system allow it, so even if the graphics
8866  * device allows PC8+, it doesn't mean the system will actually get to these
8867  * states. Our driver only allows PC8+ when going into runtime PM.
8868  *
8869  * The requirements for PC8+ are that all the outputs are disabled, the power
8870  * well is disabled and most interrupts are disabled, and these are also
8871  * requirements for runtime PM. When these conditions are met, we manually do
8872  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8873  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8874  * hang the machine.
8875  *
8876  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8877  * the state of some registers, so when we come back from PC8+ we need to
8878  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8879  * need to take care of the registers kept by RC6. Notice that this happens even
8880  * if we don't put the device in PCI D3 state (which is what currently happens
8881  * because of the runtime PM support).
8882  *
8883  * For more, read "Display Sequences for Package C8" on the hardware
8884  * documentation.
8885  */
8886 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8887 {
8888         uint32_t val;
8889
8890         DRM_DEBUG_KMS("Enabling package C8+\n");
8891
8892         if (HAS_PCH_LPT_LP(dev_priv)) {
8893                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8894                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8895                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8896         }
8897
8898         lpt_disable_clkout_dp(dev_priv);
8899         hsw_disable_lcpll(dev_priv, true, true);
8900 }
8901
8902 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8903 {
8904         uint32_t val;
8905
8906         DRM_DEBUG_KMS("Disabling package C8+\n");
8907
8908         hsw_restore_lcpll(dev_priv);
8909         lpt_init_pch_refclk(dev_priv);
8910
8911         if (HAS_PCH_LPT_LP(dev_priv)) {
8912                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8913                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8914                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8915         }
8916 }
8917
8918 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8919                                       struct intel_crtc_state *crtc_state)
8920 {
8921         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8922                 struct intel_encoder *encoder =
8923                         intel_ddi_get_crtc_new_encoder(crtc_state);
8924
8925                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8926                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8927                                          pipe_name(crtc->pipe));
8928                         return -EINVAL;
8929                 }
8930         }
8931
8932         return 0;
8933 }
8934
8935 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8936                                    enum port port,
8937                                    struct intel_crtc_state *pipe_config)
8938 {
8939         enum intel_dpll_id id;
8940         u32 temp;
8941
8942         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8943         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
8944
8945         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8946                 return;
8947
8948         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8949 }
8950
8951 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8952                                 enum port port,
8953                                 struct intel_crtc_state *pipe_config)
8954 {
8955         enum intel_dpll_id id;
8956
8957         switch (port) {
8958         case PORT_A:
8959                 id = DPLL_ID_SKL_DPLL0;
8960                 break;
8961         case PORT_B:
8962                 id = DPLL_ID_SKL_DPLL1;
8963                 break;
8964         case PORT_C:
8965                 id = DPLL_ID_SKL_DPLL2;
8966                 break;
8967         default:
8968                 DRM_ERROR("Incorrect port type\n");
8969                 return;
8970         }
8971
8972         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8973 }
8974
8975 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8976                                 enum port port,
8977                                 struct intel_crtc_state *pipe_config)
8978 {
8979         enum intel_dpll_id id;
8980         u32 temp;
8981
8982         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8983         id = temp >> (port * 3 + 1);
8984
8985         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8986                 return;
8987
8988         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8989 }
8990
8991 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8992                                 enum port port,
8993                                 struct intel_crtc_state *pipe_config)
8994 {
8995         enum intel_dpll_id id;
8996         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8997
8998         switch (ddi_pll_sel) {
8999         case PORT_CLK_SEL_WRPLL1:
9000                 id = DPLL_ID_WRPLL1;
9001                 break;
9002         case PORT_CLK_SEL_WRPLL2:
9003                 id = DPLL_ID_WRPLL2;
9004                 break;
9005         case PORT_CLK_SEL_SPLL:
9006                 id = DPLL_ID_SPLL;
9007                 break;
9008         case PORT_CLK_SEL_LCPLL_810:
9009                 id = DPLL_ID_LCPLL_810;
9010                 break;
9011         case PORT_CLK_SEL_LCPLL_1350:
9012                 id = DPLL_ID_LCPLL_1350;
9013                 break;
9014         case PORT_CLK_SEL_LCPLL_2700:
9015                 id = DPLL_ID_LCPLL_2700;
9016                 break;
9017         default:
9018                 MISSING_CASE(ddi_pll_sel);
9019                 /* fall through */
9020         case PORT_CLK_SEL_NONE:
9021                 return;
9022         }
9023
9024         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9025 }
9026
9027 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9028                                      struct intel_crtc_state *pipe_config,
9029                                      u64 *power_domain_mask)
9030 {
9031         struct drm_device *dev = crtc->base.dev;
9032         struct drm_i915_private *dev_priv = to_i915(dev);
9033         enum intel_display_power_domain power_domain;
9034         u32 tmp;
9035
9036         /*
9037          * The pipe->transcoder mapping is fixed with the exception of the eDP
9038          * transcoder handled below.
9039          */
9040         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9041
9042         /*
9043          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9044          * consistency and less surprising code; it's in always on power).
9045          */
9046         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9047         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9048                 enum pipe trans_edp_pipe;
9049                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9050                 default:
9051                         WARN(1, "unknown pipe linked to edp transcoder\n");
9052                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9053                 case TRANS_DDI_EDP_INPUT_A_ON:
9054                         trans_edp_pipe = PIPE_A;
9055                         break;
9056                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9057                         trans_edp_pipe = PIPE_B;
9058                         break;
9059                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9060                         trans_edp_pipe = PIPE_C;
9061                         break;
9062                 }
9063
9064                 if (trans_edp_pipe == crtc->pipe)
9065                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9066         }
9067
9068         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9069         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9070                 return false;
9071         *power_domain_mask |= BIT_ULL(power_domain);
9072
9073         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9074
9075         return tmp & PIPECONF_ENABLE;
9076 }
9077
9078 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9079                                          struct intel_crtc_state *pipe_config,
9080                                          u64 *power_domain_mask)
9081 {
9082         struct drm_device *dev = crtc->base.dev;
9083         struct drm_i915_private *dev_priv = to_i915(dev);
9084         enum intel_display_power_domain power_domain;
9085         enum port port;
9086         enum transcoder cpu_transcoder;
9087         u32 tmp;
9088
9089         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9090                 if (port == PORT_A)
9091                         cpu_transcoder = TRANSCODER_DSI_A;
9092                 else
9093                         cpu_transcoder = TRANSCODER_DSI_C;
9094
9095                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9096                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9097                         continue;
9098                 *power_domain_mask |= BIT_ULL(power_domain);
9099
9100                 /*
9101                  * The PLL needs to be enabled with a valid divider
9102                  * configuration, otherwise accessing DSI registers will hang
9103                  * the machine. See BSpec North Display Engine
9104                  * registers/MIPI[BXT]. We can break out here early, since we
9105                  * need the same DSI PLL to be enabled for both DSI ports.
9106                  */
9107                 if (!intel_dsi_pll_is_enabled(dev_priv))
9108                         break;
9109
9110                 /* XXX: this works for video mode only */
9111                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9112                 if (!(tmp & DPI_ENABLE))
9113                         continue;
9114
9115                 tmp = I915_READ(MIPI_CTRL(port));
9116                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9117                         continue;
9118
9119                 pipe_config->cpu_transcoder = cpu_transcoder;
9120                 break;
9121         }
9122
9123         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9124 }
9125
9126 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9127                                        struct intel_crtc_state *pipe_config)
9128 {
9129         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9130         struct intel_shared_dpll *pll;
9131         enum port port;
9132         uint32_t tmp;
9133
9134         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9135
9136         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9137
9138         if (IS_CANNONLAKE(dev_priv))
9139                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9140         else if (IS_GEN9_BC(dev_priv))
9141                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9142         else if (IS_GEN9_LP(dev_priv))
9143                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9144         else
9145                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9146
9147         pll = pipe_config->shared_dpll;
9148         if (pll) {
9149                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9150                                                  &pipe_config->dpll_hw_state));
9151         }
9152
9153         /*
9154          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9155          * DDI E. So just check whether this pipe is wired to DDI E and whether
9156          * the PCH transcoder is on.
9157          */
9158         if (INTEL_GEN(dev_priv) < 9 &&
9159             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9160                 pipe_config->has_pch_encoder = true;
9161
9162                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9163                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9164                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9165
9166                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9167         }
9168 }
9169
9170 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9171                                     struct intel_crtc_state *pipe_config)
9172 {
9173         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9174         enum intel_display_power_domain power_domain;
9175         u64 power_domain_mask;
9176         bool active;
9177
9178         intel_crtc_init_scalers(crtc, pipe_config);
9179
9180         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9181         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9182                 return false;
9183         power_domain_mask = BIT_ULL(power_domain);
9184
9185         pipe_config->shared_dpll = NULL;
9186
9187         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9188
9189         if (IS_GEN9_LP(dev_priv) &&
9190             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9191                 WARN_ON(active);
9192                 active = true;
9193         }
9194
9195         if (!active)
9196                 goto out;
9197
9198         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9199                 haswell_get_ddi_port_state(crtc, pipe_config);
9200                 intel_get_pipe_timings(crtc, pipe_config);
9201         }
9202
9203         intel_get_pipe_src_size(crtc, pipe_config);
9204
9205         pipe_config->gamma_mode =
9206                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9207
9208         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9209                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9210                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9211
9212                 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9213                         bool blend_mode_420 = tmp &
9214                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
9215
9216                         pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9217                         if (pipe_config->ycbcr420 != clrspace_yuv ||
9218                             pipe_config->ycbcr420 != blend_mode_420)
9219                                 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9220                 } else if (clrspace_yuv) {
9221                         DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9222                 }
9223         }
9224
9225         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9226         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9227                 power_domain_mask |= BIT_ULL(power_domain);
9228                 if (INTEL_GEN(dev_priv) >= 9)
9229                         skylake_get_pfit_config(crtc, pipe_config);
9230                 else
9231                         ironlake_get_pfit_config(crtc, pipe_config);
9232         }
9233
9234         if (IS_HASWELL(dev_priv))
9235                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9236                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9237
9238         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9239             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9240                 pipe_config->pixel_multiplier =
9241                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9242         } else {
9243                 pipe_config->pixel_multiplier = 1;
9244         }
9245
9246 out:
9247         for_each_power_domain(power_domain, power_domain_mask)
9248                 intel_display_power_put(dev_priv, power_domain);
9249
9250         return active;
9251 }
9252
9253 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9254 {
9255         struct drm_i915_private *dev_priv =
9256                 to_i915(plane_state->base.plane->dev);
9257         const struct drm_framebuffer *fb = plane_state->base.fb;
9258         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9259         u32 base;
9260
9261         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9262                 base = obj->phys_handle->busaddr;
9263         else
9264                 base = intel_plane_ggtt_offset(plane_state);
9265
9266         base += plane_state->main.offset;
9267
9268         /* ILK+ do this automagically */
9269         if (HAS_GMCH_DISPLAY(dev_priv) &&
9270             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9271                 base += (plane_state->base.crtc_h *
9272                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9273
9274         return base;
9275 }
9276
9277 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9278 {
9279         int x = plane_state->base.crtc_x;
9280         int y = plane_state->base.crtc_y;
9281         u32 pos = 0;
9282
9283         if (x < 0) {
9284                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9285                 x = -x;
9286         }
9287         pos |= x << CURSOR_X_SHIFT;
9288
9289         if (y < 0) {
9290                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9291                 y = -y;
9292         }
9293         pos |= y << CURSOR_Y_SHIFT;
9294
9295         return pos;
9296 }
9297
9298 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9299 {
9300         const struct drm_mode_config *config =
9301                 &plane_state->base.plane->dev->mode_config;
9302         int width = plane_state->base.crtc_w;
9303         int height = plane_state->base.crtc_h;
9304
9305         return width > 0 && width <= config->cursor_width &&
9306                 height > 0 && height <= config->cursor_height;
9307 }
9308
9309 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9310                               struct intel_plane_state *plane_state)
9311 {
9312         const struct drm_framebuffer *fb = plane_state->base.fb;
9313         int src_x, src_y;
9314         u32 offset;
9315         int ret;
9316
9317         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9318                                                   &crtc_state->base,
9319                                                   &plane_state->clip,
9320                                                   DRM_PLANE_HELPER_NO_SCALING,
9321                                                   DRM_PLANE_HELPER_NO_SCALING,
9322                                                   true, true);
9323         if (ret)
9324                 return ret;
9325
9326         if (!fb)
9327                 return 0;
9328
9329         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9330                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9331                 return -EINVAL;
9332         }
9333
9334         src_x = plane_state->base.src_x >> 16;
9335         src_y = plane_state->base.src_y >> 16;
9336
9337         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9338         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9339
9340         if (src_x != 0 || src_y != 0) {
9341                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9342                 return -EINVAL;
9343         }
9344
9345         plane_state->main.offset = offset;
9346
9347         return 0;
9348 }
9349
9350 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9351                            const struct intel_plane_state *plane_state)
9352 {
9353         const struct drm_framebuffer *fb = plane_state->base.fb;
9354
9355         return CURSOR_ENABLE |
9356                 CURSOR_GAMMA_ENABLE |
9357                 CURSOR_FORMAT_ARGB |
9358                 CURSOR_STRIDE(fb->pitches[0]);
9359 }
9360
9361 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9362 {
9363         int width = plane_state->base.crtc_w;
9364
9365         /*
9366          * 845g/865g are only limited by the width of their cursors,
9367          * the height is arbitrary up to the precision of the register.
9368          */
9369         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9370 }
9371
9372 static int i845_check_cursor(struct intel_plane *plane,
9373                              struct intel_crtc_state *crtc_state,
9374                              struct intel_plane_state *plane_state)
9375 {
9376         const struct drm_framebuffer *fb = plane_state->base.fb;
9377         int ret;
9378
9379         ret = intel_check_cursor(crtc_state, plane_state);
9380         if (ret)
9381                 return ret;
9382
9383         /* if we want to turn off the cursor ignore width and height */
9384         if (!fb)
9385                 return 0;
9386
9387         /* Check for which cursor types we support */
9388         if (!i845_cursor_size_ok(plane_state)) {
9389                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9390                           plane_state->base.crtc_w,
9391                           plane_state->base.crtc_h);
9392                 return -EINVAL;
9393         }
9394
9395         switch (fb->pitches[0]) {
9396         case 256:
9397         case 512:
9398         case 1024:
9399         case 2048:
9400                 break;
9401         default:
9402                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9403                               fb->pitches[0]);
9404                 return -EINVAL;
9405         }
9406
9407         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9408
9409         return 0;
9410 }
9411
9412 static void i845_update_cursor(struct intel_plane *plane,
9413                                const struct intel_crtc_state *crtc_state,
9414                                const struct intel_plane_state *plane_state)
9415 {
9416         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9417         u32 cntl = 0, base = 0, pos = 0, size = 0;
9418         unsigned long irqflags;
9419
9420         if (plane_state && plane_state->base.visible) {
9421                 unsigned int width = plane_state->base.crtc_w;
9422                 unsigned int height = plane_state->base.crtc_h;
9423
9424                 cntl = plane_state->ctl;
9425                 size = (height << 12) | width;
9426
9427                 base = intel_cursor_base(plane_state);
9428                 pos = intel_cursor_position(plane_state);
9429         }
9430
9431         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9432
9433         /* On these chipsets we can only modify the base/size/stride
9434          * whilst the cursor is disabled.
9435          */
9436         if (plane->cursor.base != base ||
9437             plane->cursor.size != size ||
9438             plane->cursor.cntl != cntl) {
9439                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9440                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9441                 I915_WRITE_FW(CURSIZE, size);
9442                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9443                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9444
9445                 plane->cursor.base = base;
9446                 plane->cursor.size = size;
9447                 plane->cursor.cntl = cntl;
9448         } else {
9449                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9450         }
9451
9452         POSTING_READ_FW(CURCNTR(PIPE_A));
9453
9454         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9455 }
9456
9457 static void i845_disable_cursor(struct intel_plane *plane,
9458                                 struct intel_crtc *crtc)
9459 {
9460         i845_update_cursor(plane, NULL, NULL);
9461 }
9462
9463 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9464                            const struct intel_plane_state *plane_state)
9465 {
9466         struct drm_i915_private *dev_priv =
9467                 to_i915(plane_state->base.plane->dev);
9468         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9469         u32 cntl;
9470
9471         cntl = MCURSOR_GAMMA_ENABLE;
9472
9473         if (HAS_DDI(dev_priv))
9474                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9475
9476         cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9477
9478         switch (plane_state->base.crtc_w) {
9479         case 64:
9480                 cntl |= CURSOR_MODE_64_ARGB_AX;
9481                 break;
9482         case 128:
9483                 cntl |= CURSOR_MODE_128_ARGB_AX;
9484                 break;
9485         case 256:
9486                 cntl |= CURSOR_MODE_256_ARGB_AX;
9487                 break;
9488         default:
9489                 MISSING_CASE(plane_state->base.crtc_w);
9490                 return 0;
9491         }
9492
9493         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9494                 cntl |= CURSOR_ROTATE_180;
9495
9496         return cntl;
9497 }
9498
9499 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9500 {
9501         struct drm_i915_private *dev_priv =
9502                 to_i915(plane_state->base.plane->dev);
9503         int width = plane_state->base.crtc_w;
9504         int height = plane_state->base.crtc_h;
9505
9506         if (!intel_cursor_size_ok(plane_state))
9507                 return false;
9508
9509         /* Cursor width is limited to a few power-of-two sizes */
9510         switch (width) {
9511         case 256:
9512         case 128:
9513         case 64:
9514                 break;
9515         default:
9516                 return false;
9517         }
9518
9519         /*
9520          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9521          * height from 8 lines up to the cursor width, when the
9522          * cursor is not rotated. Everything else requires square
9523          * cursors.
9524          */
9525         if (HAS_CUR_FBC(dev_priv) &&
9526             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9527                 if (height < 8 || height > width)
9528                         return false;
9529         } else {
9530                 if (height != width)
9531                         return false;
9532         }
9533
9534         return true;
9535 }
9536
9537 static int i9xx_check_cursor(struct intel_plane *plane,
9538                              struct intel_crtc_state *crtc_state,
9539                              struct intel_plane_state *plane_state)
9540 {
9541         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9542         const struct drm_framebuffer *fb = plane_state->base.fb;
9543         enum pipe pipe = plane->pipe;
9544         int ret;
9545
9546         ret = intel_check_cursor(crtc_state, plane_state);
9547         if (ret)
9548                 return ret;
9549
9550         /* if we want to turn off the cursor ignore width and height */
9551         if (!fb)
9552                 return 0;
9553
9554         /* Check for which cursor types we support */
9555         if (!i9xx_cursor_size_ok(plane_state)) {
9556                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9557                           plane_state->base.crtc_w,
9558                           plane_state->base.crtc_h);
9559                 return -EINVAL;
9560         }
9561
9562         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9563                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9564                               fb->pitches[0], plane_state->base.crtc_w);
9565                 return -EINVAL;
9566         }
9567
9568         /*
9569          * There's something wrong with the cursor on CHV pipe C.
9570          * If it straddles the left edge of the screen then
9571          * moving it away from the edge or disabling it often
9572          * results in a pipe underrun, and often that can lead to
9573          * dead pipe (constant underrun reported, and it scans
9574          * out just a solid color). To recover from that, the
9575          * display power well must be turned off and on again.
9576          * Refuse the put the cursor into that compromised position.
9577          */
9578         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9579             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9580                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9581                 return -EINVAL;
9582         }
9583
9584         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9585
9586         return 0;
9587 }
9588
9589 static void i9xx_update_cursor(struct intel_plane *plane,
9590                                const struct intel_crtc_state *crtc_state,
9591                                const struct intel_plane_state *plane_state)
9592 {
9593         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9594         enum pipe pipe = plane->pipe;
9595         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9596         unsigned long irqflags;
9597
9598         if (plane_state && plane_state->base.visible) {
9599                 cntl = plane_state->ctl;
9600
9601                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9602                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9603
9604                 base = intel_cursor_base(plane_state);
9605                 pos = intel_cursor_position(plane_state);
9606         }
9607
9608         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9609
9610         /*
9611          * On some platforms writing CURCNTR first will also
9612          * cause CURPOS to be armed by the CURBASE write.
9613          * Without the CURCNTR write the CURPOS write would
9614          * arm itself. Thus we always start the full update
9615          * with a CURCNTR write.
9616          *
9617          * On other platforms CURPOS always requires the
9618          * CURBASE write to arm the update. Additonally
9619          * a write to any of the cursor register will cancel
9620          * an already armed cursor update. Thus leaving out
9621          * the CURBASE write after CURPOS could lead to a
9622          * cursor that doesn't appear to move, or even change
9623          * shape. Thus we always write CURBASE.
9624          *
9625          * CURCNTR and CUR_FBC_CTL are always
9626          * armed by the CURBASE write only.
9627          */
9628         if (plane->cursor.base != base ||
9629             plane->cursor.size != fbc_ctl ||
9630             plane->cursor.cntl != cntl) {
9631                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9632                 if (HAS_CUR_FBC(dev_priv))
9633                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9634                 I915_WRITE_FW(CURPOS(pipe), pos);
9635                 I915_WRITE_FW(CURBASE(pipe), base);
9636
9637                 plane->cursor.base = base;
9638                 plane->cursor.size = fbc_ctl;
9639                 plane->cursor.cntl = cntl;
9640         } else {
9641                 I915_WRITE_FW(CURPOS(pipe), pos);
9642                 I915_WRITE_FW(CURBASE(pipe), base);
9643         }
9644
9645         POSTING_READ_FW(CURBASE(pipe));
9646
9647         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9648 }
9649
9650 static void i9xx_disable_cursor(struct intel_plane *plane,
9651                                 struct intel_crtc *crtc)
9652 {
9653         i9xx_update_cursor(plane, NULL, NULL);
9654 }
9655
9656
9657 /* VESA 640x480x72Hz mode to set on the pipe */
9658 static const struct drm_display_mode load_detect_mode = {
9659         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9660                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9661 };
9662
9663 struct drm_framebuffer *
9664 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9665                          struct drm_mode_fb_cmd2 *mode_cmd)
9666 {
9667         struct intel_framebuffer *intel_fb;
9668         int ret;
9669
9670         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9671         if (!intel_fb)
9672                 return ERR_PTR(-ENOMEM);
9673
9674         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9675         if (ret)
9676                 goto err;
9677
9678         return &intel_fb->base;
9679
9680 err:
9681         kfree(intel_fb);
9682         return ERR_PTR(ret);
9683 }
9684
9685 static u32
9686 intel_framebuffer_pitch_for_width(int width, int bpp)
9687 {
9688         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9689         return ALIGN(pitch, 64);
9690 }
9691
9692 static u32
9693 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9694 {
9695         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9696         return PAGE_ALIGN(pitch * mode->vdisplay);
9697 }
9698
9699 static struct drm_framebuffer *
9700 intel_framebuffer_create_for_mode(struct drm_device *dev,
9701                                   const struct drm_display_mode *mode,
9702                                   int depth, int bpp)
9703 {
9704         struct drm_framebuffer *fb;
9705         struct drm_i915_gem_object *obj;
9706         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9707
9708         obj = i915_gem_object_create(to_i915(dev),
9709                                     intel_framebuffer_size_for_mode(mode, bpp));
9710         if (IS_ERR(obj))
9711                 return ERR_CAST(obj);
9712
9713         mode_cmd.width = mode->hdisplay;
9714         mode_cmd.height = mode->vdisplay;
9715         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9716                                                                 bpp);
9717         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9718
9719         fb = intel_framebuffer_create(obj, &mode_cmd);
9720         if (IS_ERR(fb))
9721                 i915_gem_object_put(obj);
9722
9723         return fb;
9724 }
9725
9726 static struct drm_framebuffer *
9727 mode_fits_in_fbdev(struct drm_device *dev,
9728                    const struct drm_display_mode *mode)
9729 {
9730 #ifdef CONFIG_DRM_FBDEV_EMULATION
9731         struct drm_i915_private *dev_priv = to_i915(dev);
9732         struct drm_i915_gem_object *obj;
9733         struct drm_framebuffer *fb;
9734
9735         if (!dev_priv->fbdev)
9736                 return NULL;
9737
9738         if (!dev_priv->fbdev->fb)
9739                 return NULL;
9740
9741         obj = dev_priv->fbdev->fb->obj;
9742         BUG_ON(!obj);
9743
9744         fb = &dev_priv->fbdev->fb->base;
9745         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9746                                                                fb->format->cpp[0] * 8))
9747                 return NULL;
9748
9749         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9750                 return NULL;
9751
9752         drm_framebuffer_get(fb);
9753         return fb;
9754 #else
9755         return NULL;
9756 #endif
9757 }
9758
9759 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9760                                            struct drm_crtc *crtc,
9761                                            const struct drm_display_mode *mode,
9762                                            struct drm_framebuffer *fb,
9763                                            int x, int y)
9764 {
9765         struct drm_plane_state *plane_state;
9766         int hdisplay, vdisplay;
9767         int ret;
9768
9769         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9770         if (IS_ERR(plane_state))
9771                 return PTR_ERR(plane_state);
9772
9773         if (mode)
9774                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9775         else
9776                 hdisplay = vdisplay = 0;
9777
9778         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9779         if (ret)
9780                 return ret;
9781         drm_atomic_set_fb_for_plane(plane_state, fb);
9782         plane_state->crtc_x = 0;
9783         plane_state->crtc_y = 0;
9784         plane_state->crtc_w = hdisplay;
9785         plane_state->crtc_h = vdisplay;
9786         plane_state->src_x = x << 16;
9787         plane_state->src_y = y << 16;
9788         plane_state->src_w = hdisplay << 16;
9789         plane_state->src_h = vdisplay << 16;
9790
9791         return 0;
9792 }
9793
9794 int intel_get_load_detect_pipe(struct drm_connector *connector,
9795                                const struct drm_display_mode *mode,
9796                                struct intel_load_detect_pipe *old,
9797                                struct drm_modeset_acquire_ctx *ctx)
9798 {
9799         struct intel_crtc *intel_crtc;
9800         struct intel_encoder *intel_encoder =
9801                 intel_attached_encoder(connector);
9802         struct drm_crtc *possible_crtc;
9803         struct drm_encoder *encoder = &intel_encoder->base;
9804         struct drm_crtc *crtc = NULL;
9805         struct drm_device *dev = encoder->dev;
9806         struct drm_i915_private *dev_priv = to_i915(dev);
9807         struct drm_framebuffer *fb;
9808         struct drm_mode_config *config = &dev->mode_config;
9809         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9810         struct drm_connector_state *connector_state;
9811         struct intel_crtc_state *crtc_state;
9812         int ret, i = -1;
9813
9814         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9815                       connector->base.id, connector->name,
9816                       encoder->base.id, encoder->name);
9817
9818         old->restore_state = NULL;
9819
9820         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9821
9822         /*
9823          * Algorithm gets a little messy:
9824          *
9825          *   - if the connector already has an assigned crtc, use it (but make
9826          *     sure it's on first)
9827          *
9828          *   - try to find the first unused crtc that can drive this connector,
9829          *     and use that if we find one
9830          */
9831
9832         /* See if we already have a CRTC for this connector */
9833         if (connector->state->crtc) {
9834                 crtc = connector->state->crtc;
9835
9836                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9837                 if (ret)
9838                         goto fail;
9839
9840                 /* Make sure the crtc and connector are running */
9841                 goto found;
9842         }
9843
9844         /* Find an unused one (if possible) */
9845         for_each_crtc(dev, possible_crtc) {
9846                 i++;
9847                 if (!(encoder->possible_crtcs & (1 << i)))
9848                         continue;
9849
9850                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9851                 if (ret)
9852                         goto fail;
9853
9854                 if (possible_crtc->state->enable) {
9855                         drm_modeset_unlock(&possible_crtc->mutex);
9856                         continue;
9857                 }
9858
9859                 crtc = possible_crtc;
9860                 break;
9861         }
9862
9863         /*
9864          * If we didn't find an unused CRTC, don't use any.
9865          */
9866         if (!crtc) {
9867                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9868                 ret = -ENODEV;
9869                 goto fail;
9870         }
9871
9872 found:
9873         intel_crtc = to_intel_crtc(crtc);
9874
9875         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9876         if (ret)
9877                 goto fail;
9878
9879         state = drm_atomic_state_alloc(dev);
9880         restore_state = drm_atomic_state_alloc(dev);
9881         if (!state || !restore_state) {
9882                 ret = -ENOMEM;
9883                 goto fail;
9884         }
9885
9886         state->acquire_ctx = ctx;
9887         restore_state->acquire_ctx = ctx;
9888
9889         connector_state = drm_atomic_get_connector_state(state, connector);
9890         if (IS_ERR(connector_state)) {
9891                 ret = PTR_ERR(connector_state);
9892                 goto fail;
9893         }
9894
9895         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9896         if (ret)
9897                 goto fail;
9898
9899         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9900         if (IS_ERR(crtc_state)) {
9901                 ret = PTR_ERR(crtc_state);
9902                 goto fail;
9903         }
9904
9905         crtc_state->base.active = crtc_state->base.enable = true;
9906
9907         if (!mode)
9908                 mode = &load_detect_mode;
9909
9910         /* We need a framebuffer large enough to accommodate all accesses
9911          * that the plane may generate whilst we perform load detection.
9912          * We can not rely on the fbcon either being present (we get called
9913          * during its initialisation to detect all boot displays, or it may
9914          * not even exist) or that it is large enough to satisfy the
9915          * requested mode.
9916          */
9917         fb = mode_fits_in_fbdev(dev, mode);
9918         if (fb == NULL) {
9919                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9920                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9921         } else
9922                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9923         if (IS_ERR(fb)) {
9924                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9925                 ret = PTR_ERR(fb);
9926                 goto fail;
9927         }
9928
9929         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9930         if (ret)
9931                 goto fail;
9932
9933         drm_framebuffer_put(fb);
9934
9935         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9936         if (ret)
9937                 goto fail;
9938
9939         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9940         if (!ret)
9941                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9942         if (!ret)
9943                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9944         if (ret) {
9945                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9946                 goto fail;
9947         }
9948
9949         ret = drm_atomic_commit(state);
9950         if (ret) {
9951                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9952                 goto fail;
9953         }
9954
9955         old->restore_state = restore_state;
9956         drm_atomic_state_put(state);
9957
9958         /* let the connector get through one full cycle before testing */
9959         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9960         return true;
9961
9962 fail:
9963         if (state) {
9964                 drm_atomic_state_put(state);
9965                 state = NULL;
9966         }
9967         if (restore_state) {
9968                 drm_atomic_state_put(restore_state);
9969                 restore_state = NULL;
9970         }
9971
9972         if (ret == -EDEADLK)
9973                 return ret;
9974
9975         return false;
9976 }
9977
9978 void intel_release_load_detect_pipe(struct drm_connector *connector,
9979                                     struct intel_load_detect_pipe *old,
9980                                     struct drm_modeset_acquire_ctx *ctx)
9981 {
9982         struct intel_encoder *intel_encoder =
9983                 intel_attached_encoder(connector);
9984         struct drm_encoder *encoder = &intel_encoder->base;
9985         struct drm_atomic_state *state = old->restore_state;
9986         int ret;
9987
9988         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9989                       connector->base.id, connector->name,
9990                       encoder->base.id, encoder->name);
9991
9992         if (!state)
9993                 return;
9994
9995         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9996         if (ret)
9997                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9998         drm_atomic_state_put(state);
9999 }
10000
10001 static int i9xx_pll_refclk(struct drm_device *dev,
10002                            const struct intel_crtc_state *pipe_config)
10003 {
10004         struct drm_i915_private *dev_priv = to_i915(dev);
10005         u32 dpll = pipe_config->dpll_hw_state.dpll;
10006
10007         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10008                 return dev_priv->vbt.lvds_ssc_freq;
10009         else if (HAS_PCH_SPLIT(dev_priv))
10010                 return 120000;
10011         else if (!IS_GEN2(dev_priv))
10012                 return 96000;
10013         else
10014                 return 48000;
10015 }
10016
10017 /* Returns the clock of the currently programmed mode of the given pipe. */
10018 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10019                                 struct intel_crtc_state *pipe_config)
10020 {
10021         struct drm_device *dev = crtc->base.dev;
10022         struct drm_i915_private *dev_priv = to_i915(dev);
10023         int pipe = pipe_config->cpu_transcoder;
10024         u32 dpll = pipe_config->dpll_hw_state.dpll;
10025         u32 fp;
10026         struct dpll clock;
10027         int port_clock;
10028         int refclk = i9xx_pll_refclk(dev, pipe_config);
10029
10030         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10031                 fp = pipe_config->dpll_hw_state.fp0;
10032         else
10033                 fp = pipe_config->dpll_hw_state.fp1;
10034
10035         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10036         if (IS_PINEVIEW(dev_priv)) {
10037                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10038                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10039         } else {
10040                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10041                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10042         }
10043
10044         if (!IS_GEN2(dev_priv)) {
10045                 if (IS_PINEVIEW(dev_priv))
10046                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10047                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10048                 else
10049                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10050                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10051
10052                 switch (dpll & DPLL_MODE_MASK) {
10053                 case DPLLB_MODE_DAC_SERIAL:
10054                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10055                                 5 : 10;
10056                         break;
10057                 case DPLLB_MODE_LVDS:
10058                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10059                                 7 : 14;
10060                         break;
10061                 default:
10062                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10063                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10064                         return;
10065                 }
10066
10067                 if (IS_PINEVIEW(dev_priv))
10068                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10069                 else
10070                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10071         } else {
10072                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10073                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10074
10075                 if (is_lvds) {
10076                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10077                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10078
10079                         if (lvds & LVDS_CLKB_POWER_UP)
10080                                 clock.p2 = 7;
10081                         else
10082                                 clock.p2 = 14;
10083                 } else {
10084                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10085                                 clock.p1 = 2;
10086                         else {
10087                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10088                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10089                         }
10090                         if (dpll & PLL_P2_DIVIDE_BY_4)
10091                                 clock.p2 = 4;
10092                         else
10093                                 clock.p2 = 2;
10094                 }
10095
10096                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10097         }
10098
10099         /*
10100          * This value includes pixel_multiplier. We will use
10101          * port_clock to compute adjusted_mode.crtc_clock in the
10102          * encoder's get_config() function.
10103          */
10104         pipe_config->port_clock = port_clock;
10105 }
10106
10107 int intel_dotclock_calculate(int link_freq,
10108                              const struct intel_link_m_n *m_n)
10109 {
10110         /*
10111          * The calculation for the data clock is:
10112          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10113          * But we want to avoid losing precison if possible, so:
10114          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10115          *
10116          * and the link clock is simpler:
10117          * link_clock = (m * link_clock) / n
10118          */
10119
10120         if (!m_n->link_n)
10121                 return 0;
10122
10123         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10124 }
10125
10126 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10127                                    struct intel_crtc_state *pipe_config)
10128 {
10129         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10130
10131         /* read out port_clock from the DPLL */
10132         i9xx_crtc_clock_get(crtc, pipe_config);
10133
10134         /*
10135          * In case there is an active pipe without active ports,
10136          * we may need some idea for the dotclock anyway.
10137          * Calculate one based on the FDI configuration.
10138          */
10139         pipe_config->base.adjusted_mode.crtc_clock =
10140                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10141                                          &pipe_config->fdi_m_n);
10142 }
10143
10144 /* Returns the currently programmed mode of the given encoder. */
10145 struct drm_display_mode *
10146 intel_encoder_current_mode(struct intel_encoder *encoder)
10147 {
10148         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10149         struct intel_crtc_state *crtc_state;
10150         struct drm_display_mode *mode;
10151         struct intel_crtc *crtc;
10152         enum pipe pipe;
10153
10154         if (!encoder->get_hw_state(encoder, &pipe))
10155                 return NULL;
10156
10157         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10158
10159         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10160         if (!mode)
10161                 return NULL;
10162
10163         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10164         if (!crtc_state) {
10165                 kfree(mode);
10166                 return NULL;
10167         }
10168
10169         crtc_state->base.crtc = &crtc->base;
10170
10171         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10172                 kfree(crtc_state);
10173                 kfree(mode);
10174                 return NULL;
10175         }
10176
10177         encoder->get_config(encoder, crtc_state);
10178
10179         intel_mode_from_pipe_config(mode, crtc_state);
10180
10181         kfree(crtc_state);
10182
10183         return mode;
10184 }
10185
10186 static void intel_crtc_destroy(struct drm_crtc *crtc)
10187 {
10188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10189
10190         drm_crtc_cleanup(crtc);
10191         kfree(intel_crtc);
10192 }
10193
10194 /**
10195  * intel_wm_need_update - Check whether watermarks need updating
10196  * @plane: drm plane
10197  * @state: new plane state
10198  *
10199  * Check current plane state versus the new one to determine whether
10200  * watermarks need to be recalculated.
10201  *
10202  * Returns true or false.
10203  */
10204 static bool intel_wm_need_update(struct drm_plane *plane,
10205                                  struct drm_plane_state *state)
10206 {
10207         struct intel_plane_state *new = to_intel_plane_state(state);
10208         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10209
10210         /* Update watermarks on tiling or size changes. */
10211         if (new->base.visible != cur->base.visible)
10212                 return true;
10213
10214         if (!cur->base.fb || !new->base.fb)
10215                 return false;
10216
10217         if (cur->base.fb->modifier != new->base.fb->modifier ||
10218             cur->base.rotation != new->base.rotation ||
10219             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10220             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10221             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10222             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10223                 return true;
10224
10225         return false;
10226 }
10227
10228 static bool needs_scaling(const struct intel_plane_state *state)
10229 {
10230         int src_w = drm_rect_width(&state->base.src) >> 16;
10231         int src_h = drm_rect_height(&state->base.src) >> 16;
10232         int dst_w = drm_rect_width(&state->base.dst);
10233         int dst_h = drm_rect_height(&state->base.dst);
10234
10235         return (src_w != dst_w || src_h != dst_h);
10236 }
10237
10238 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10239                                     struct drm_crtc_state *crtc_state,
10240                                     const struct intel_plane_state *old_plane_state,
10241                                     struct drm_plane_state *plane_state)
10242 {
10243         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10244         struct drm_crtc *crtc = crtc_state->crtc;
10245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10246         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10247         struct drm_device *dev = crtc->dev;
10248         struct drm_i915_private *dev_priv = to_i915(dev);
10249         bool mode_changed = needs_modeset(crtc_state);
10250         bool was_crtc_enabled = old_crtc_state->base.active;
10251         bool is_crtc_enabled = crtc_state->active;
10252         bool turn_off, turn_on, visible, was_visible;
10253         struct drm_framebuffer *fb = plane_state->fb;
10254         int ret;
10255
10256         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10257                 ret = skl_update_scaler_plane(
10258                         to_intel_crtc_state(crtc_state),
10259                         to_intel_plane_state(plane_state));
10260                 if (ret)
10261                         return ret;
10262         }
10263
10264         was_visible = old_plane_state->base.visible;
10265         visible = plane_state->visible;
10266
10267         if (!was_crtc_enabled && WARN_ON(was_visible))
10268                 was_visible = false;
10269
10270         /*
10271          * Visibility is calculated as if the crtc was on, but
10272          * after scaler setup everything depends on it being off
10273          * when the crtc isn't active.
10274          *
10275          * FIXME this is wrong for watermarks. Watermarks should also
10276          * be computed as if the pipe would be active. Perhaps move
10277          * per-plane wm computation to the .check_plane() hook, and
10278          * only combine the results from all planes in the current place?
10279          */
10280         if (!is_crtc_enabled) {
10281                 plane_state->visible = visible = false;
10282                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10283         }
10284
10285         if (!was_visible && !visible)
10286                 return 0;
10287
10288         if (fb != old_plane_state->base.fb)
10289                 pipe_config->fb_changed = true;
10290
10291         turn_off = was_visible && (!visible || mode_changed);
10292         turn_on = visible && (!was_visible || mode_changed);
10293
10294         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10295                          intel_crtc->base.base.id, intel_crtc->base.name,
10296                          plane->base.base.id, plane->base.name,
10297                          fb ? fb->base.id : -1);
10298
10299         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10300                          plane->base.base.id, plane->base.name,
10301                          was_visible, visible,
10302                          turn_off, turn_on, mode_changed);
10303
10304         if (turn_on) {
10305                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10306                         pipe_config->update_wm_pre = true;
10307
10308                 /* must disable cxsr around plane enable/disable */
10309                 if (plane->id != PLANE_CURSOR)
10310                         pipe_config->disable_cxsr = true;
10311         } else if (turn_off) {
10312                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10313                         pipe_config->update_wm_post = true;
10314
10315                 /* must disable cxsr around plane enable/disable */
10316                 if (plane->id != PLANE_CURSOR)
10317                         pipe_config->disable_cxsr = true;
10318         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10319                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10320                         /* FIXME bollocks */
10321                         pipe_config->update_wm_pre = true;
10322                         pipe_config->update_wm_post = true;
10323                 }
10324         }
10325
10326         if (visible || was_visible)
10327                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10328
10329         /*
10330          * WaCxSRDisabledForSpriteScaling:ivb
10331          *
10332          * cstate->update_wm was already set above, so this flag will
10333          * take effect when we commit and program watermarks.
10334          */
10335         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10336             needs_scaling(to_intel_plane_state(plane_state)) &&
10337             !needs_scaling(old_plane_state))
10338                 pipe_config->disable_lp_wm = true;
10339
10340         return 0;
10341 }
10342
10343 static bool encoders_cloneable(const struct intel_encoder *a,
10344                                const struct intel_encoder *b)
10345 {
10346         /* masks could be asymmetric, so check both ways */
10347         return a == b || (a->cloneable & (1 << b->type) &&
10348                           b->cloneable & (1 << a->type));
10349 }
10350
10351 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10352                                          struct intel_crtc *crtc,
10353                                          struct intel_encoder *encoder)
10354 {
10355         struct intel_encoder *source_encoder;
10356         struct drm_connector *connector;
10357         struct drm_connector_state *connector_state;
10358         int i;
10359
10360         for_each_new_connector_in_state(state, connector, connector_state, i) {
10361                 if (connector_state->crtc != &crtc->base)
10362                         continue;
10363
10364                 source_encoder =
10365                         to_intel_encoder(connector_state->best_encoder);
10366                 if (!encoders_cloneable(encoder, source_encoder))
10367                         return false;
10368         }
10369
10370         return true;
10371 }
10372
10373 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10374                                    struct drm_crtc_state *crtc_state)
10375 {
10376         struct drm_device *dev = crtc->dev;
10377         struct drm_i915_private *dev_priv = to_i915(dev);
10378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10379         struct intel_crtc_state *pipe_config =
10380                 to_intel_crtc_state(crtc_state);
10381         struct drm_atomic_state *state = crtc_state->state;
10382         int ret;
10383         bool mode_changed = needs_modeset(crtc_state);
10384
10385         if (mode_changed && !crtc_state->active)
10386                 pipe_config->update_wm_post = true;
10387
10388         if (mode_changed && crtc_state->enable &&
10389             dev_priv->display.crtc_compute_clock &&
10390             !WARN_ON(pipe_config->shared_dpll)) {
10391                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10392                                                            pipe_config);
10393                 if (ret)
10394                         return ret;
10395         }
10396
10397         if (crtc_state->color_mgmt_changed) {
10398                 ret = intel_color_check(crtc, crtc_state);
10399                 if (ret)
10400                         return ret;
10401
10402                 /*
10403                  * Changing color management on Intel hardware is
10404                  * handled as part of planes update.
10405                  */
10406                 crtc_state->planes_changed = true;
10407         }
10408
10409         ret = 0;
10410         if (dev_priv->display.compute_pipe_wm) {
10411                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10412                 if (ret) {
10413                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10414                         return ret;
10415                 }
10416         }
10417
10418         if (dev_priv->display.compute_intermediate_wm &&
10419             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10420                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10421                         return 0;
10422
10423                 /*
10424                  * Calculate 'intermediate' watermarks that satisfy both the
10425                  * old state and the new state.  We can program these
10426                  * immediately.
10427                  */
10428                 ret = dev_priv->display.compute_intermediate_wm(dev,
10429                                                                 intel_crtc,
10430                                                                 pipe_config);
10431                 if (ret) {
10432                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10433                         return ret;
10434                 }
10435         } else if (dev_priv->display.compute_intermediate_wm) {
10436                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10437                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10438         }
10439
10440         if (INTEL_GEN(dev_priv) >= 9) {
10441                 if (mode_changed)
10442                         ret = skl_update_scaler_crtc(pipe_config);
10443
10444                 if (!ret)
10445                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10446                                                             pipe_config);
10447                 if (!ret)
10448                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10449                                                          pipe_config);
10450         }
10451
10452         return ret;
10453 }
10454
10455 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10456         .atomic_begin = intel_begin_crtc_commit,
10457         .atomic_flush = intel_finish_crtc_commit,
10458         .atomic_check = intel_crtc_atomic_check,
10459 };
10460
10461 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10462 {
10463         struct intel_connector *connector;
10464         struct drm_connector_list_iter conn_iter;
10465
10466         drm_connector_list_iter_begin(dev, &conn_iter);
10467         for_each_intel_connector_iter(connector, &conn_iter) {
10468                 if (connector->base.state->crtc)
10469                         drm_connector_unreference(&connector->base);
10470
10471                 if (connector->base.encoder) {
10472                         connector->base.state->best_encoder =
10473                                 connector->base.encoder;
10474                         connector->base.state->crtc =
10475                                 connector->base.encoder->crtc;
10476
10477                         drm_connector_reference(&connector->base);
10478                 } else {
10479                         connector->base.state->best_encoder = NULL;
10480                         connector->base.state->crtc = NULL;
10481                 }
10482         }
10483         drm_connector_list_iter_end(&conn_iter);
10484 }
10485
10486 static void
10487 connected_sink_compute_bpp(struct intel_connector *connector,
10488                            struct intel_crtc_state *pipe_config)
10489 {
10490         const struct drm_display_info *info = &connector->base.display_info;
10491         int bpp = pipe_config->pipe_bpp;
10492
10493         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10494                       connector->base.base.id,
10495                       connector->base.name);
10496
10497         /* Don't use an invalid EDID bpc value */
10498         if (info->bpc != 0 && info->bpc * 3 < bpp) {
10499                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10500                               bpp, info->bpc * 3);
10501                 pipe_config->pipe_bpp = info->bpc * 3;
10502         }
10503
10504         /* Clamp bpp to 8 on screens without EDID 1.4 */
10505         if (info->bpc == 0 && bpp > 24) {
10506                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10507                               bpp);
10508                 pipe_config->pipe_bpp = 24;
10509         }
10510 }
10511
10512 static int
10513 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10514                           struct intel_crtc_state *pipe_config)
10515 {
10516         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10517         struct drm_atomic_state *state;
10518         struct drm_connector *connector;
10519         struct drm_connector_state *connector_state;
10520         int bpp, i;
10521
10522         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10523             IS_CHERRYVIEW(dev_priv)))
10524                 bpp = 10*3;
10525         else if (INTEL_GEN(dev_priv) >= 5)
10526                 bpp = 12*3;
10527         else
10528                 bpp = 8*3;
10529
10530
10531         pipe_config->pipe_bpp = bpp;
10532
10533         state = pipe_config->base.state;
10534
10535         /* Clamp display bpp to EDID value */
10536         for_each_new_connector_in_state(state, connector, connector_state, i) {
10537                 if (connector_state->crtc != &crtc->base)
10538                         continue;
10539
10540                 connected_sink_compute_bpp(to_intel_connector(connector),
10541                                            pipe_config);
10542         }
10543
10544         return bpp;
10545 }
10546
10547 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10548 {
10549         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10550                         "type: 0x%x flags: 0x%x\n",
10551                 mode->crtc_clock,
10552                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10553                 mode->crtc_hsync_end, mode->crtc_htotal,
10554                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10555                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10556 }
10557
10558 static inline void
10559 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10560                       unsigned int lane_count, struct intel_link_m_n *m_n)
10561 {
10562         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10563                       id, lane_count,
10564                       m_n->gmch_m, m_n->gmch_n,
10565                       m_n->link_m, m_n->link_n, m_n->tu);
10566 }
10567
10568 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10569
10570 static const char * const output_type_str[] = {
10571         OUTPUT_TYPE(UNUSED),
10572         OUTPUT_TYPE(ANALOG),
10573         OUTPUT_TYPE(DVO),
10574         OUTPUT_TYPE(SDVO),
10575         OUTPUT_TYPE(LVDS),
10576         OUTPUT_TYPE(TVOUT),
10577         OUTPUT_TYPE(HDMI),
10578         OUTPUT_TYPE(DP),
10579         OUTPUT_TYPE(EDP),
10580         OUTPUT_TYPE(DSI),
10581         OUTPUT_TYPE(UNKNOWN),
10582         OUTPUT_TYPE(DP_MST),
10583 };
10584
10585 #undef OUTPUT_TYPE
10586
10587 static void snprintf_output_types(char *buf, size_t len,
10588                                   unsigned int output_types)
10589 {
10590         char *str = buf;
10591         int i;
10592
10593         str[0] = '\0';
10594
10595         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10596                 int r;
10597
10598                 if ((output_types & BIT(i)) == 0)
10599                         continue;
10600
10601                 r = snprintf(str, len, "%s%s",
10602                              str != buf ? "," : "", output_type_str[i]);
10603                 if (r >= len)
10604                         break;
10605                 str += r;
10606                 len -= r;
10607
10608                 output_types &= ~BIT(i);
10609         }
10610
10611         WARN_ON_ONCE(output_types != 0);
10612 }
10613
10614 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10615                                    struct intel_crtc_state *pipe_config,
10616                                    const char *context)
10617 {
10618         struct drm_device *dev = crtc->base.dev;
10619         struct drm_i915_private *dev_priv = to_i915(dev);
10620         struct drm_plane *plane;
10621         struct intel_plane *intel_plane;
10622         struct intel_plane_state *state;
10623         struct drm_framebuffer *fb;
10624         char buf[64];
10625
10626         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10627                       crtc->base.base.id, crtc->base.name, context);
10628
10629         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10630         DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10631                       buf, pipe_config->output_types);
10632
10633         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10634                       transcoder_name(pipe_config->cpu_transcoder),
10635                       pipe_config->pipe_bpp, pipe_config->dither);
10636
10637         if (pipe_config->has_pch_encoder)
10638                 intel_dump_m_n_config(pipe_config, "fdi",
10639                                       pipe_config->fdi_lanes,
10640                                       &pipe_config->fdi_m_n);
10641
10642         if (pipe_config->ycbcr420)
10643                 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10644
10645         if (intel_crtc_has_dp_encoder(pipe_config)) {
10646                 intel_dump_m_n_config(pipe_config, "dp m_n",
10647                                 pipe_config->lane_count, &pipe_config->dp_m_n);
10648                 if (pipe_config->has_drrs)
10649                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
10650                                               pipe_config->lane_count,
10651                                               &pipe_config->dp_m2_n2);
10652         }
10653
10654         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10655                       pipe_config->has_audio, pipe_config->has_infoframe);
10656
10657         DRM_DEBUG_KMS("requested mode:\n");
10658         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10659         DRM_DEBUG_KMS("adjusted mode:\n");
10660         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10661         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10662         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10663                       pipe_config->port_clock,
10664                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10665                       pipe_config->pixel_rate);
10666
10667         if (INTEL_GEN(dev_priv) >= 9)
10668                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10669                               crtc->num_scalers,
10670                               pipe_config->scaler_state.scaler_users,
10671                               pipe_config->scaler_state.scaler_id);
10672
10673         if (HAS_GMCH_DISPLAY(dev_priv))
10674                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10675                               pipe_config->gmch_pfit.control,
10676                               pipe_config->gmch_pfit.pgm_ratios,
10677                               pipe_config->gmch_pfit.lvds_border_bits);
10678         else
10679                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10680                               pipe_config->pch_pfit.pos,
10681                               pipe_config->pch_pfit.size,
10682                               enableddisabled(pipe_config->pch_pfit.enabled));
10683
10684         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10685                       pipe_config->ips_enabled, pipe_config->double_wide);
10686
10687         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10688
10689         DRM_DEBUG_KMS("planes on this crtc\n");
10690         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10691                 struct drm_format_name_buf format_name;
10692                 intel_plane = to_intel_plane(plane);
10693                 if (intel_plane->pipe != crtc->pipe)
10694                         continue;
10695
10696                 state = to_intel_plane_state(plane->state);
10697                 fb = state->base.fb;
10698                 if (!fb) {
10699                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10700                                       plane->base.id, plane->name, state->scaler_id);
10701                         continue;
10702                 }
10703
10704                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10705                               plane->base.id, plane->name,
10706                               fb->base.id, fb->width, fb->height,
10707                               drm_get_format_name(fb->format->format, &format_name));
10708                 if (INTEL_GEN(dev_priv) >= 9)
10709                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10710                                       state->scaler_id,
10711                                       state->base.src.x1 >> 16,
10712                                       state->base.src.y1 >> 16,
10713                                       drm_rect_width(&state->base.src) >> 16,
10714                                       drm_rect_height(&state->base.src) >> 16,
10715                                       state->base.dst.x1, state->base.dst.y1,
10716                                       drm_rect_width(&state->base.dst),
10717                                       drm_rect_height(&state->base.dst));
10718         }
10719 }
10720
10721 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10722 {
10723         struct drm_device *dev = state->dev;
10724         struct drm_connector *connector;
10725         struct drm_connector_list_iter conn_iter;
10726         unsigned int used_ports = 0;
10727         unsigned int used_mst_ports = 0;
10728
10729         /*
10730          * Walk the connector list instead of the encoder
10731          * list to detect the problem on ddi platforms
10732          * where there's just one encoder per digital port.
10733          */
10734         drm_connector_list_iter_begin(dev, &conn_iter);
10735         drm_for_each_connector_iter(connector, &conn_iter) {
10736                 struct drm_connector_state *connector_state;
10737                 struct intel_encoder *encoder;
10738
10739                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10740                 if (!connector_state)
10741                         connector_state = connector->state;
10742
10743                 if (!connector_state->best_encoder)
10744                         continue;
10745
10746                 encoder = to_intel_encoder(connector_state->best_encoder);
10747
10748                 WARN_ON(!connector_state->crtc);
10749
10750                 switch (encoder->type) {
10751                         unsigned int port_mask;
10752                 case INTEL_OUTPUT_UNKNOWN:
10753                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
10754                                 break;
10755                 case INTEL_OUTPUT_DP:
10756                 case INTEL_OUTPUT_HDMI:
10757                 case INTEL_OUTPUT_EDP:
10758                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10759
10760                         /* the same port mustn't appear more than once */
10761                         if (used_ports & port_mask)
10762                                 return false;
10763
10764                         used_ports |= port_mask;
10765                         break;
10766                 case INTEL_OUTPUT_DP_MST:
10767                         used_mst_ports |=
10768                                 1 << enc_to_mst(&encoder->base)->primary->port;
10769                         break;
10770                 default:
10771                         break;
10772                 }
10773         }
10774         drm_connector_list_iter_end(&conn_iter);
10775
10776         /* can't mix MST and SST/HDMI on the same port */
10777         if (used_ports & used_mst_ports)
10778                 return false;
10779
10780         return true;
10781 }
10782
10783 static void
10784 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10785 {
10786         struct drm_i915_private *dev_priv =
10787                 to_i915(crtc_state->base.crtc->dev);
10788         struct intel_crtc_scaler_state scaler_state;
10789         struct intel_dpll_hw_state dpll_hw_state;
10790         struct intel_shared_dpll *shared_dpll;
10791         struct intel_crtc_wm_state wm_state;
10792         bool force_thru, ips_force_disable;
10793
10794         /* FIXME: before the switch to atomic started, a new pipe_config was
10795          * kzalloc'd. Code that depends on any field being zero should be
10796          * fixed, so that the crtc_state can be safely duplicated. For now,
10797          * only fields that are know to not cause problems are preserved. */
10798
10799         scaler_state = crtc_state->scaler_state;
10800         shared_dpll = crtc_state->shared_dpll;
10801         dpll_hw_state = crtc_state->dpll_hw_state;
10802         force_thru = crtc_state->pch_pfit.force_thru;
10803         ips_force_disable = crtc_state->ips_force_disable;
10804         if (IS_G4X(dev_priv) ||
10805             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10806                 wm_state = crtc_state->wm;
10807
10808         /* Keep base drm_crtc_state intact, only clear our extended struct */
10809         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10810         memset(&crtc_state->base + 1, 0,
10811                sizeof(*crtc_state) - sizeof(crtc_state->base));
10812
10813         crtc_state->scaler_state = scaler_state;
10814         crtc_state->shared_dpll = shared_dpll;
10815         crtc_state->dpll_hw_state = dpll_hw_state;
10816         crtc_state->pch_pfit.force_thru = force_thru;
10817         crtc_state->ips_force_disable = ips_force_disable;
10818         if (IS_G4X(dev_priv) ||
10819             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10820                 crtc_state->wm = wm_state;
10821 }
10822
10823 static int
10824 intel_modeset_pipe_config(struct drm_crtc *crtc,
10825                           struct intel_crtc_state *pipe_config)
10826 {
10827         struct drm_atomic_state *state = pipe_config->base.state;
10828         struct intel_encoder *encoder;
10829         struct drm_connector *connector;
10830         struct drm_connector_state *connector_state;
10831         int base_bpp, ret = -EINVAL;
10832         int i;
10833         bool retry = true;
10834
10835         clear_intel_crtc_state(pipe_config);
10836
10837         pipe_config->cpu_transcoder =
10838                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10839
10840         /*
10841          * Sanitize sync polarity flags based on requested ones. If neither
10842          * positive or negative polarity is requested, treat this as meaning
10843          * negative polarity.
10844          */
10845         if (!(pipe_config->base.adjusted_mode.flags &
10846               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10847                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10848
10849         if (!(pipe_config->base.adjusted_mode.flags &
10850               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10851                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10852
10853         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10854                                              pipe_config);
10855         if (base_bpp < 0)
10856                 goto fail;
10857
10858         /*
10859          * Determine the real pipe dimensions. Note that stereo modes can
10860          * increase the actual pipe size due to the frame doubling and
10861          * insertion of additional space for blanks between the frame. This
10862          * is stored in the crtc timings. We use the requested mode to do this
10863          * computation to clearly distinguish it from the adjusted mode, which
10864          * can be changed by the connectors in the below retry loop.
10865          */
10866         drm_mode_get_hv_timing(&pipe_config->base.mode,
10867                                &pipe_config->pipe_src_w,
10868                                &pipe_config->pipe_src_h);
10869
10870         for_each_new_connector_in_state(state, connector, connector_state, i) {
10871                 if (connector_state->crtc != crtc)
10872                         continue;
10873
10874                 encoder = to_intel_encoder(connector_state->best_encoder);
10875
10876                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10877                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10878                         goto fail;
10879                 }
10880
10881                 /*
10882                  * Determine output_types before calling the .compute_config()
10883                  * hooks so that the hooks can use this information safely.
10884                  */
10885                 pipe_config->output_types |= 1 << encoder->type;
10886         }
10887
10888 encoder_retry:
10889         /* Ensure the port clock defaults are reset when retrying. */
10890         pipe_config->port_clock = 0;
10891         pipe_config->pixel_multiplier = 1;
10892
10893         /* Fill in default crtc timings, allow encoders to overwrite them. */
10894         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10895                               CRTC_STEREO_DOUBLE);
10896
10897         /* Pass our mode to the connectors and the CRTC to give them a chance to
10898          * adjust it according to limitations or connector properties, and also
10899          * a chance to reject the mode entirely.
10900          */
10901         for_each_new_connector_in_state(state, connector, connector_state, i) {
10902                 if (connector_state->crtc != crtc)
10903                         continue;
10904
10905                 encoder = to_intel_encoder(connector_state->best_encoder);
10906
10907                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10908                         DRM_DEBUG_KMS("Encoder config failure\n");
10909                         goto fail;
10910                 }
10911         }
10912
10913         /* Set default port clock if not overwritten by the encoder. Needs to be
10914          * done afterwards in case the encoder adjusts the mode. */
10915         if (!pipe_config->port_clock)
10916                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10917                         * pipe_config->pixel_multiplier;
10918
10919         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10920         if (ret < 0) {
10921                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10922                 goto fail;
10923         }
10924
10925         if (ret == RETRY) {
10926                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10927                         ret = -EINVAL;
10928                         goto fail;
10929                 }
10930
10931                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10932                 retry = false;
10933                 goto encoder_retry;
10934         }
10935
10936         /* Dithering seems to not pass-through bits correctly when it should, so
10937          * only enable it on 6bpc panels and when its not a compliance
10938          * test requesting 6bpc video pattern.
10939          */
10940         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10941                 !pipe_config->dither_force_disable;
10942         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10943                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10944
10945 fail:
10946         return ret;
10947 }
10948
10949 static void
10950 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10951 {
10952         struct drm_crtc *crtc;
10953         struct drm_crtc_state *new_crtc_state;
10954         int i;
10955
10956         /* Double check state. */
10957         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10958                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
10959
10960                 /*
10961                  * Update legacy state to satisfy fbc code. This can
10962                  * be removed when fbc uses the atomic state.
10963                  */
10964                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
10965                         struct drm_plane_state *plane_state = crtc->primary->state;
10966
10967                         crtc->primary->fb = plane_state->fb;
10968                         crtc->x = plane_state->src_x >> 16;
10969                         crtc->y = plane_state->src_y >> 16;
10970                 }
10971         }
10972 }
10973
10974 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10975 {
10976         int diff;
10977
10978         if (clock1 == clock2)
10979                 return true;
10980
10981         if (!clock1 || !clock2)
10982                 return false;
10983
10984         diff = abs(clock1 - clock2);
10985
10986         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10987                 return true;
10988
10989         return false;
10990 }
10991
10992 static bool
10993 intel_compare_m_n(unsigned int m, unsigned int n,
10994                   unsigned int m2, unsigned int n2,
10995                   bool exact)
10996 {
10997         if (m == m2 && n == n2)
10998                 return true;
10999
11000         if (exact || !m || !n || !m2 || !n2)
11001                 return false;
11002
11003         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11004
11005         if (n > n2) {
11006                 while (n > n2) {
11007                         m2 <<= 1;
11008                         n2 <<= 1;
11009                 }
11010         } else if (n < n2) {
11011                 while (n < n2) {
11012                         m <<= 1;
11013                         n <<= 1;
11014                 }
11015         }
11016
11017         if (n != n2)
11018                 return false;
11019
11020         return intel_fuzzy_clock_check(m, m2);
11021 }
11022
11023 static bool
11024 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11025                        struct intel_link_m_n *m2_n2,
11026                        bool adjust)
11027 {
11028         if (m_n->tu == m2_n2->tu &&
11029             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11030                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11031             intel_compare_m_n(m_n->link_m, m_n->link_n,
11032                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11033                 if (adjust)
11034                         *m2_n2 = *m_n;
11035
11036                 return true;
11037         }
11038
11039         return false;
11040 }
11041
11042 static void __printf(3, 4)
11043 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11044 {
11045         char *level;
11046         unsigned int category;
11047         struct va_format vaf;
11048         va_list args;
11049
11050         if (adjust) {
11051                 level = KERN_DEBUG;
11052                 category = DRM_UT_KMS;
11053         } else {
11054                 level = KERN_ERR;
11055                 category = DRM_UT_NONE;
11056         }
11057
11058         va_start(args, format);
11059         vaf.fmt = format;
11060         vaf.va = &args;
11061
11062         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11063
11064         va_end(args);
11065 }
11066
11067 static bool
11068 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11069                           struct intel_crtc_state *current_config,
11070                           struct intel_crtc_state *pipe_config,
11071                           bool adjust)
11072 {
11073         bool ret = true;
11074
11075 #define PIPE_CONF_CHECK_X(name) \
11076         if (current_config->name != pipe_config->name) { \
11077                 pipe_config_err(adjust, __stringify(name), \
11078                           "(expected 0x%08x, found 0x%08x)\n", \
11079                           current_config->name, \
11080                           pipe_config->name); \
11081                 ret = false; \
11082         }
11083
11084 #define PIPE_CONF_CHECK_I(name) \
11085         if (current_config->name != pipe_config->name) { \
11086                 pipe_config_err(adjust, __stringify(name), \
11087                           "(expected %i, found %i)\n", \
11088                           current_config->name, \
11089                           pipe_config->name); \
11090                 ret = false; \
11091         }
11092
11093 #define PIPE_CONF_CHECK_P(name) \
11094         if (current_config->name != pipe_config->name) { \
11095                 pipe_config_err(adjust, __stringify(name), \
11096                           "(expected %p, found %p)\n", \
11097                           current_config->name, \
11098                           pipe_config->name); \
11099                 ret = false; \
11100         }
11101
11102 #define PIPE_CONF_CHECK_M_N(name) \
11103         if (!intel_compare_link_m_n(&current_config->name, \
11104                                     &pipe_config->name,\
11105                                     adjust)) { \
11106                 pipe_config_err(adjust, __stringify(name), \
11107                           "(expected tu %i gmch %i/%i link %i/%i, " \
11108                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11109                           current_config->name.tu, \
11110                           current_config->name.gmch_m, \
11111                           current_config->name.gmch_n, \
11112                           current_config->name.link_m, \
11113                           current_config->name.link_n, \
11114                           pipe_config->name.tu, \
11115                           pipe_config->name.gmch_m, \
11116                           pipe_config->name.gmch_n, \
11117                           pipe_config->name.link_m, \
11118                           pipe_config->name.link_n); \
11119                 ret = false; \
11120         }
11121
11122 /* This is required for BDW+ where there is only one set of registers for
11123  * switching between high and low RR.
11124  * This macro can be used whenever a comparison has to be made between one
11125  * hw state and multiple sw state variables.
11126  */
11127 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11128         if (!intel_compare_link_m_n(&current_config->name, \
11129                                     &pipe_config->name, adjust) && \
11130             !intel_compare_link_m_n(&current_config->alt_name, \
11131                                     &pipe_config->name, adjust)) { \
11132                 pipe_config_err(adjust, __stringify(name), \
11133                           "(expected tu %i gmch %i/%i link %i/%i, " \
11134                           "or tu %i gmch %i/%i link %i/%i, " \
11135                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11136                           current_config->name.tu, \
11137                           current_config->name.gmch_m, \
11138                           current_config->name.gmch_n, \
11139                           current_config->name.link_m, \
11140                           current_config->name.link_n, \
11141                           current_config->alt_name.tu, \
11142                           current_config->alt_name.gmch_m, \
11143                           current_config->alt_name.gmch_n, \
11144                           current_config->alt_name.link_m, \
11145                           current_config->alt_name.link_n, \
11146                           pipe_config->name.tu, \
11147                           pipe_config->name.gmch_m, \
11148                           pipe_config->name.gmch_n, \
11149                           pipe_config->name.link_m, \
11150                           pipe_config->name.link_n); \
11151                 ret = false; \
11152         }
11153
11154 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11155         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11156                 pipe_config_err(adjust, __stringify(name), \
11157                           "(%x) (expected %i, found %i)\n", \
11158                           (mask), \
11159                           current_config->name & (mask), \
11160                           pipe_config->name & (mask)); \
11161                 ret = false; \
11162         }
11163
11164 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11165         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11166                 pipe_config_err(adjust, __stringify(name), \
11167                           "(expected %i, found %i)\n", \
11168                           current_config->name, \
11169                           pipe_config->name); \
11170                 ret = false; \
11171         }
11172
11173 #define PIPE_CONF_QUIRK(quirk)  \
11174         ((current_config->quirks | pipe_config->quirks) & (quirk))
11175
11176         PIPE_CONF_CHECK_I(cpu_transcoder);
11177
11178         PIPE_CONF_CHECK_I(has_pch_encoder);
11179         PIPE_CONF_CHECK_I(fdi_lanes);
11180         PIPE_CONF_CHECK_M_N(fdi_m_n);
11181
11182         PIPE_CONF_CHECK_I(lane_count);
11183         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11184
11185         if (INTEL_GEN(dev_priv) < 8) {
11186                 PIPE_CONF_CHECK_M_N(dp_m_n);
11187
11188                 if (current_config->has_drrs)
11189                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11190         } else
11191                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11192
11193         PIPE_CONF_CHECK_X(output_types);
11194
11195         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11196         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11197         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11198         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11199         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11200         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11201
11202         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11203         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11204         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11205         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11206         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11207         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11208
11209         PIPE_CONF_CHECK_I(pixel_multiplier);
11210         PIPE_CONF_CHECK_I(has_hdmi_sink);
11211         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11212             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11213                 PIPE_CONF_CHECK_I(limited_color_range);
11214
11215         PIPE_CONF_CHECK_I(hdmi_scrambling);
11216         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11217         PIPE_CONF_CHECK_I(has_infoframe);
11218         PIPE_CONF_CHECK_I(ycbcr420);
11219
11220         PIPE_CONF_CHECK_I(has_audio);
11221
11222         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11223                               DRM_MODE_FLAG_INTERLACE);
11224
11225         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11226                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11227                                       DRM_MODE_FLAG_PHSYNC);
11228                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11229                                       DRM_MODE_FLAG_NHSYNC);
11230                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11231                                       DRM_MODE_FLAG_PVSYNC);
11232                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11233                                       DRM_MODE_FLAG_NVSYNC);
11234         }
11235
11236         PIPE_CONF_CHECK_X(gmch_pfit.control);
11237         /* pfit ratios are autocomputed by the hw on gen4+ */
11238         if (INTEL_GEN(dev_priv) < 4)
11239                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11240         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11241
11242         if (!adjust) {
11243                 PIPE_CONF_CHECK_I(pipe_src_w);
11244                 PIPE_CONF_CHECK_I(pipe_src_h);
11245
11246                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11247                 if (current_config->pch_pfit.enabled) {
11248                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11249                         PIPE_CONF_CHECK_X(pch_pfit.size);
11250                 }
11251
11252                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11253                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11254         }
11255
11256         /* BDW+ don't expose a synchronous way to read the state */
11257         if (IS_HASWELL(dev_priv))
11258                 PIPE_CONF_CHECK_I(ips_enabled);
11259
11260         PIPE_CONF_CHECK_I(double_wide);
11261
11262         PIPE_CONF_CHECK_P(shared_dpll);
11263         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11264         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11265         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11266         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11267         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11268         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11269         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11270         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11271         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11272         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11273         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11274         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11275         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11276         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11277         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11278         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11279         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11280         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11281         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11282         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11283         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11284
11285         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11286         PIPE_CONF_CHECK_X(dsi_pll.div);
11287
11288         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11289                 PIPE_CONF_CHECK_I(pipe_bpp);
11290
11291         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11292         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11293
11294 #undef PIPE_CONF_CHECK_X
11295 #undef PIPE_CONF_CHECK_I
11296 #undef PIPE_CONF_CHECK_P
11297 #undef PIPE_CONF_CHECK_FLAGS
11298 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11299 #undef PIPE_CONF_QUIRK
11300
11301         return ret;
11302 }
11303
11304 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11305                                            const struct intel_crtc_state *pipe_config)
11306 {
11307         if (pipe_config->has_pch_encoder) {
11308                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11309                                                             &pipe_config->fdi_m_n);
11310                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11311
11312                 /*
11313                  * FDI already provided one idea for the dotclock.
11314                  * Yell if the encoder disagrees.
11315                  */
11316                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11317                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11318                      fdi_dotclock, dotclock);
11319         }
11320 }
11321
11322 static void verify_wm_state(struct drm_crtc *crtc,
11323                             struct drm_crtc_state *new_state)
11324 {
11325         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11326         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11327         struct skl_pipe_wm hw_wm, *sw_wm;
11328         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11329         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11331         const enum pipe pipe = intel_crtc->pipe;
11332         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11333
11334         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11335                 return;
11336
11337         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11338         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11339
11340         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11341         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11342
11343         /* planes */
11344         for_each_universal_plane(dev_priv, pipe, plane) {
11345                 hw_plane_wm = &hw_wm.planes[plane];
11346                 sw_plane_wm = &sw_wm->planes[plane];
11347
11348                 /* Watermarks */
11349                 for (level = 0; level <= max_level; level++) {
11350                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11351                                                 &sw_plane_wm->wm[level]))
11352                                 continue;
11353
11354                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11355                                   pipe_name(pipe), plane + 1, level,
11356                                   sw_plane_wm->wm[level].plane_en,
11357                                   sw_plane_wm->wm[level].plane_res_b,
11358                                   sw_plane_wm->wm[level].plane_res_l,
11359                                   hw_plane_wm->wm[level].plane_en,
11360                                   hw_plane_wm->wm[level].plane_res_b,
11361                                   hw_plane_wm->wm[level].plane_res_l);
11362                 }
11363
11364                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11365                                          &sw_plane_wm->trans_wm)) {
11366                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11367                                   pipe_name(pipe), plane + 1,
11368                                   sw_plane_wm->trans_wm.plane_en,
11369                                   sw_plane_wm->trans_wm.plane_res_b,
11370                                   sw_plane_wm->trans_wm.plane_res_l,
11371                                   hw_plane_wm->trans_wm.plane_en,
11372                                   hw_plane_wm->trans_wm.plane_res_b,
11373                                   hw_plane_wm->trans_wm.plane_res_l);
11374                 }
11375
11376                 /* DDB */
11377                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11378                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11379
11380                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11381                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11382                                   pipe_name(pipe), plane + 1,
11383                                   sw_ddb_entry->start, sw_ddb_entry->end,
11384                                   hw_ddb_entry->start, hw_ddb_entry->end);
11385                 }
11386         }
11387
11388         /*
11389          * cursor
11390          * If the cursor plane isn't active, we may not have updated it's ddb
11391          * allocation. In that case since the ddb allocation will be updated
11392          * once the plane becomes visible, we can skip this check
11393          */
11394         if (1) {
11395                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11396                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11397
11398                 /* Watermarks */
11399                 for (level = 0; level <= max_level; level++) {
11400                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11401                                                 &sw_plane_wm->wm[level]))
11402                                 continue;
11403
11404                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11405                                   pipe_name(pipe), level,
11406                                   sw_plane_wm->wm[level].plane_en,
11407                                   sw_plane_wm->wm[level].plane_res_b,
11408                                   sw_plane_wm->wm[level].plane_res_l,
11409                                   hw_plane_wm->wm[level].plane_en,
11410                                   hw_plane_wm->wm[level].plane_res_b,
11411                                   hw_plane_wm->wm[level].plane_res_l);
11412                 }
11413
11414                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11415                                          &sw_plane_wm->trans_wm)) {
11416                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11417                                   pipe_name(pipe),
11418                                   sw_plane_wm->trans_wm.plane_en,
11419                                   sw_plane_wm->trans_wm.plane_res_b,
11420                                   sw_plane_wm->trans_wm.plane_res_l,
11421                                   hw_plane_wm->trans_wm.plane_en,
11422                                   hw_plane_wm->trans_wm.plane_res_b,
11423                                   hw_plane_wm->trans_wm.plane_res_l);
11424                 }
11425
11426                 /* DDB */
11427                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11428                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11429
11430                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11431                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11432                                   pipe_name(pipe),
11433                                   sw_ddb_entry->start, sw_ddb_entry->end,
11434                                   hw_ddb_entry->start, hw_ddb_entry->end);
11435                 }
11436         }
11437 }
11438
11439 static void
11440 verify_connector_state(struct drm_device *dev,
11441                        struct drm_atomic_state *state,
11442                        struct drm_crtc *crtc)
11443 {
11444         struct drm_connector *connector;
11445         struct drm_connector_state *new_conn_state;
11446         int i;
11447
11448         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11449                 struct drm_encoder *encoder = connector->encoder;
11450                 struct drm_crtc_state *crtc_state = NULL;
11451
11452                 if (new_conn_state->crtc != crtc)
11453                         continue;
11454
11455                 if (crtc)
11456                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11457
11458                 intel_connector_verify_state(crtc_state, new_conn_state);
11459
11460                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11461                      "connector's atomic encoder doesn't match legacy encoder\n");
11462         }
11463 }
11464
11465 static void
11466 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11467 {
11468         struct intel_encoder *encoder;
11469         struct drm_connector *connector;
11470         struct drm_connector_state *old_conn_state, *new_conn_state;
11471         int i;
11472
11473         for_each_intel_encoder(dev, encoder) {
11474                 bool enabled = false, found = false;
11475                 enum pipe pipe;
11476
11477                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11478                               encoder->base.base.id,
11479                               encoder->base.name);
11480
11481                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11482                                                    new_conn_state, i) {
11483                         if (old_conn_state->best_encoder == &encoder->base)
11484                                 found = true;
11485
11486                         if (new_conn_state->best_encoder != &encoder->base)
11487                                 continue;
11488                         found = enabled = true;
11489
11490                         I915_STATE_WARN(new_conn_state->crtc !=
11491                                         encoder->base.crtc,
11492                              "connector's crtc doesn't match encoder crtc\n");
11493                 }
11494
11495                 if (!found)
11496                         continue;
11497
11498                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11499                      "encoder's enabled state mismatch "
11500                      "(expected %i, found %i)\n",
11501                      !!encoder->base.crtc, enabled);
11502
11503                 if (!encoder->base.crtc) {
11504                         bool active;
11505
11506                         active = encoder->get_hw_state(encoder, &pipe);
11507                         I915_STATE_WARN(active,
11508                              "encoder detached but still enabled on pipe %c.\n",
11509                              pipe_name(pipe));
11510                 }
11511         }
11512 }
11513
11514 static void
11515 verify_crtc_state(struct drm_crtc *crtc,
11516                   struct drm_crtc_state *old_crtc_state,
11517                   struct drm_crtc_state *new_crtc_state)
11518 {
11519         struct drm_device *dev = crtc->dev;
11520         struct drm_i915_private *dev_priv = to_i915(dev);
11521         struct intel_encoder *encoder;
11522         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11523         struct intel_crtc_state *pipe_config, *sw_config;
11524         struct drm_atomic_state *old_state;
11525         bool active;
11526
11527         old_state = old_crtc_state->state;
11528         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11529         pipe_config = to_intel_crtc_state(old_crtc_state);
11530         memset(pipe_config, 0, sizeof(*pipe_config));
11531         pipe_config->base.crtc = crtc;
11532         pipe_config->base.state = old_state;
11533
11534         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11535
11536         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11537
11538         /* we keep both pipes enabled on 830 */
11539         if (IS_I830(dev_priv))
11540                 active = new_crtc_state->active;
11541
11542         I915_STATE_WARN(new_crtc_state->active != active,
11543              "crtc active state doesn't match with hw state "
11544              "(expected %i, found %i)\n", new_crtc_state->active, active);
11545
11546         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11547              "transitional active state does not match atomic hw state "
11548              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11549
11550         for_each_encoder_on_crtc(dev, crtc, encoder) {
11551                 enum pipe pipe;
11552
11553                 active = encoder->get_hw_state(encoder, &pipe);
11554                 I915_STATE_WARN(active != new_crtc_state->active,
11555                         "[ENCODER:%i] active %i with crtc active %i\n",
11556                         encoder->base.base.id, active, new_crtc_state->active);
11557
11558                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11559                                 "Encoder connected to wrong pipe %c\n",
11560                                 pipe_name(pipe));
11561
11562                 if (active) {
11563                         pipe_config->output_types |= 1 << encoder->type;
11564                         encoder->get_config(encoder, pipe_config);
11565                 }
11566         }
11567
11568         intel_crtc_compute_pixel_rate(pipe_config);
11569
11570         if (!new_crtc_state->active)
11571                 return;
11572
11573         intel_pipe_config_sanity_check(dev_priv, pipe_config);
11574
11575         sw_config = to_intel_crtc_state(new_crtc_state);
11576         if (!intel_pipe_config_compare(dev_priv, sw_config,
11577                                        pipe_config, false)) {
11578                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11579                 intel_dump_pipe_config(intel_crtc, pipe_config,
11580                                        "[hw state]");
11581                 intel_dump_pipe_config(intel_crtc, sw_config,
11582                                        "[sw state]");
11583         }
11584 }
11585
11586 static void
11587 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11588                          struct intel_shared_dpll *pll,
11589                          struct drm_crtc *crtc,
11590                          struct drm_crtc_state *new_state)
11591 {
11592         struct intel_dpll_hw_state dpll_hw_state;
11593         unsigned crtc_mask;
11594         bool active;
11595
11596         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11597
11598         DRM_DEBUG_KMS("%s\n", pll->name);
11599
11600         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11601
11602         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11603                 I915_STATE_WARN(!pll->on && pll->active_mask,
11604                      "pll in active use but not on in sw tracking\n");
11605                 I915_STATE_WARN(pll->on && !pll->active_mask,
11606                      "pll is on but not used by any active crtc\n");
11607                 I915_STATE_WARN(pll->on != active,
11608                      "pll on state mismatch (expected %i, found %i)\n",
11609                      pll->on, active);
11610         }
11611
11612         if (!crtc) {
11613                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11614                                 "more active pll users than references: %x vs %x\n",
11615                                 pll->active_mask, pll->state.crtc_mask);
11616
11617                 return;
11618         }
11619
11620         crtc_mask = 1 << drm_crtc_index(crtc);
11621
11622         if (new_state->active)
11623                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11624                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11625                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11626         else
11627                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11628                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11629                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11630
11631         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11632                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11633                         crtc_mask, pll->state.crtc_mask);
11634
11635         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11636                                           &dpll_hw_state,
11637                                           sizeof(dpll_hw_state)),
11638                         "pll hw state mismatch\n");
11639 }
11640
11641 static void
11642 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11643                          struct drm_crtc_state *old_crtc_state,
11644                          struct drm_crtc_state *new_crtc_state)
11645 {
11646         struct drm_i915_private *dev_priv = to_i915(dev);
11647         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11648         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11649
11650         if (new_state->shared_dpll)
11651                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11652
11653         if (old_state->shared_dpll &&
11654             old_state->shared_dpll != new_state->shared_dpll) {
11655                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11656                 struct intel_shared_dpll *pll = old_state->shared_dpll;
11657
11658                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11659                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11660                                 pipe_name(drm_crtc_index(crtc)));
11661                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11662                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11663                                 pipe_name(drm_crtc_index(crtc)));
11664         }
11665 }
11666
11667 static void
11668 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11669                           struct drm_atomic_state *state,
11670                           struct drm_crtc_state *old_state,
11671                           struct drm_crtc_state *new_state)
11672 {
11673         if (!needs_modeset(new_state) &&
11674             !to_intel_crtc_state(new_state)->update_pipe)
11675                 return;
11676
11677         verify_wm_state(crtc, new_state);
11678         verify_connector_state(crtc->dev, state, crtc);
11679         verify_crtc_state(crtc, old_state, new_state);
11680         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11681 }
11682
11683 static void
11684 verify_disabled_dpll_state(struct drm_device *dev)
11685 {
11686         struct drm_i915_private *dev_priv = to_i915(dev);
11687         int i;
11688
11689         for (i = 0; i < dev_priv->num_shared_dpll; i++)
11690                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11691 }
11692
11693 static void
11694 intel_modeset_verify_disabled(struct drm_device *dev,
11695                               struct drm_atomic_state *state)
11696 {
11697         verify_encoder_state(dev, state);
11698         verify_connector_state(dev, state, NULL);
11699         verify_disabled_dpll_state(dev);
11700 }
11701
11702 static void update_scanline_offset(struct intel_crtc *crtc)
11703 {
11704         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11705
11706         /*
11707          * The scanline counter increments at the leading edge of hsync.
11708          *
11709          * On most platforms it starts counting from vtotal-1 on the
11710          * first active line. That means the scanline counter value is
11711          * always one less than what we would expect. Ie. just after
11712          * start of vblank, which also occurs at start of hsync (on the
11713          * last active line), the scanline counter will read vblank_start-1.
11714          *
11715          * On gen2 the scanline counter starts counting from 1 instead
11716          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11717          * to keep the value positive), instead of adding one.
11718          *
11719          * On HSW+ the behaviour of the scanline counter depends on the output
11720          * type. For DP ports it behaves like most other platforms, but on HDMI
11721          * there's an extra 1 line difference. So we need to add two instead of
11722          * one to the value.
11723          *
11724          * On VLV/CHV DSI the scanline counter would appear to increment
11725          * approx. 1/3 of a scanline before start of vblank. Unfortunately
11726          * that means we can't tell whether we're in vblank or not while
11727          * we're on that particular line. We must still set scanline_offset
11728          * to 1 so that the vblank timestamps come out correct when we query
11729          * the scanline counter from within the vblank interrupt handler.
11730          * However if queried just before the start of vblank we'll get an
11731          * answer that's slightly in the future.
11732          */
11733         if (IS_GEN2(dev_priv)) {
11734                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11735                 int vtotal;
11736
11737                 vtotal = adjusted_mode->crtc_vtotal;
11738                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11739                         vtotal /= 2;
11740
11741                 crtc->scanline_offset = vtotal - 1;
11742         } else if (HAS_DDI(dev_priv) &&
11743                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11744                 crtc->scanline_offset = 2;
11745         } else
11746                 crtc->scanline_offset = 1;
11747 }
11748
11749 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11750 {
11751         struct drm_device *dev = state->dev;
11752         struct drm_i915_private *dev_priv = to_i915(dev);
11753         struct drm_crtc *crtc;
11754         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11755         int i;
11756
11757         if (!dev_priv->display.crtc_compute_clock)
11758                 return;
11759
11760         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11761                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11762                 struct intel_shared_dpll *old_dpll =
11763                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
11764
11765                 if (!needs_modeset(new_crtc_state))
11766                         continue;
11767
11768                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11769
11770                 if (!old_dpll)
11771                         continue;
11772
11773                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11774         }
11775 }
11776
11777 /*
11778  * This implements the workaround described in the "notes" section of the mode
11779  * set sequence documentation. When going from no pipes or single pipe to
11780  * multiple pipes, and planes are enabled after the pipe, we need to wait at
11781  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11782  */
11783 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11784 {
11785         struct drm_crtc_state *crtc_state;
11786         struct intel_crtc *intel_crtc;
11787         struct drm_crtc *crtc;
11788         struct intel_crtc_state *first_crtc_state = NULL;
11789         struct intel_crtc_state *other_crtc_state = NULL;
11790         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11791         int i;
11792
11793         /* look at all crtc's that are going to be enabled in during modeset */
11794         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11795                 intel_crtc = to_intel_crtc(crtc);
11796
11797                 if (!crtc_state->active || !needs_modeset(crtc_state))
11798                         continue;
11799
11800                 if (first_crtc_state) {
11801                         other_crtc_state = to_intel_crtc_state(crtc_state);
11802                         break;
11803                 } else {
11804                         first_crtc_state = to_intel_crtc_state(crtc_state);
11805                         first_pipe = intel_crtc->pipe;
11806                 }
11807         }
11808
11809         /* No workaround needed? */
11810         if (!first_crtc_state)
11811                 return 0;
11812
11813         /* w/a possibly needed, check how many crtc's are already enabled. */
11814         for_each_intel_crtc(state->dev, intel_crtc) {
11815                 struct intel_crtc_state *pipe_config;
11816
11817                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11818                 if (IS_ERR(pipe_config))
11819                         return PTR_ERR(pipe_config);
11820
11821                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11822
11823                 if (!pipe_config->base.active ||
11824                     needs_modeset(&pipe_config->base))
11825                         continue;
11826
11827                 /* 2 or more enabled crtcs means no need for w/a */
11828                 if (enabled_pipe != INVALID_PIPE)
11829                         return 0;
11830
11831                 enabled_pipe = intel_crtc->pipe;
11832         }
11833
11834         if (enabled_pipe != INVALID_PIPE)
11835                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11836         else if (other_crtc_state)
11837                 other_crtc_state->hsw_workaround_pipe = first_pipe;
11838
11839         return 0;
11840 }
11841
11842 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11843 {
11844         struct drm_crtc *crtc;
11845
11846         /* Add all pipes to the state */
11847         for_each_crtc(state->dev, crtc) {
11848                 struct drm_crtc_state *crtc_state;
11849
11850                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11851                 if (IS_ERR(crtc_state))
11852                         return PTR_ERR(crtc_state);
11853         }
11854
11855         return 0;
11856 }
11857
11858 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11859 {
11860         struct drm_crtc *crtc;
11861
11862         /*
11863          * Add all pipes to the state, and force
11864          * a modeset on all the active ones.
11865          */
11866         for_each_crtc(state->dev, crtc) {
11867                 struct drm_crtc_state *crtc_state;
11868                 int ret;
11869
11870                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11871                 if (IS_ERR(crtc_state))
11872                         return PTR_ERR(crtc_state);
11873
11874                 if (!crtc_state->active || needs_modeset(crtc_state))
11875                         continue;
11876
11877                 crtc_state->mode_changed = true;
11878
11879                 ret = drm_atomic_add_affected_connectors(state, crtc);
11880                 if (ret)
11881                         return ret;
11882
11883                 ret = drm_atomic_add_affected_planes(state, crtc);
11884                 if (ret)
11885                         return ret;
11886         }
11887
11888         return 0;
11889 }
11890
11891 static int intel_modeset_checks(struct drm_atomic_state *state)
11892 {
11893         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11894         struct drm_i915_private *dev_priv = to_i915(state->dev);
11895         struct drm_crtc *crtc;
11896         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11897         int ret = 0, i;
11898
11899         if (!check_digital_port_conflicts(state)) {
11900                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11901                 return -EINVAL;
11902         }
11903
11904         intel_state->modeset = true;
11905         intel_state->active_crtcs = dev_priv->active_crtcs;
11906         intel_state->cdclk.logical = dev_priv->cdclk.logical;
11907         intel_state->cdclk.actual = dev_priv->cdclk.actual;
11908
11909         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11910                 if (new_crtc_state->active)
11911                         intel_state->active_crtcs |= 1 << i;
11912                 else
11913                         intel_state->active_crtcs &= ~(1 << i);
11914
11915                 if (old_crtc_state->active != new_crtc_state->active)
11916                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11917         }
11918
11919         /*
11920          * See if the config requires any additional preparation, e.g.
11921          * to adjust global state with pipes off.  We need to do this
11922          * here so we can get the modeset_pipe updated config for the new
11923          * mode set on this crtc.  For other crtcs we need to use the
11924          * adjusted_mode bits in the crtc directly.
11925          */
11926         if (dev_priv->display.modeset_calc_cdclk) {
11927                 ret = dev_priv->display.modeset_calc_cdclk(state);
11928                 if (ret < 0)
11929                         return ret;
11930
11931                 /*
11932                  * Writes to dev_priv->cdclk.logical must protected by
11933                  * holding all the crtc locks, even if we don't end up
11934                  * touching the hardware
11935                  */
11936                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11937                                                &intel_state->cdclk.logical)) {
11938                         ret = intel_lock_all_pipes(state);
11939                         if (ret < 0)
11940                                 return ret;
11941                 }
11942
11943                 /* All pipes must be switched off while we change the cdclk. */
11944                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
11945                                                &intel_state->cdclk.actual)) {
11946                         ret = intel_modeset_all_pipes(state);
11947                         if (ret < 0)
11948                                 return ret;
11949                 }
11950
11951                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11952                               intel_state->cdclk.logical.cdclk,
11953                               intel_state->cdclk.actual.cdclk);
11954         } else {
11955                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
11956         }
11957
11958         intel_modeset_clear_plls(state);
11959
11960         if (IS_HASWELL(dev_priv))
11961                 return haswell_mode_set_planes_workaround(state);
11962
11963         return 0;
11964 }
11965
11966 /*
11967  * Handle calculation of various watermark data at the end of the atomic check
11968  * phase.  The code here should be run after the per-crtc and per-plane 'check'
11969  * handlers to ensure that all derived state has been updated.
11970  */
11971 static int calc_watermark_data(struct drm_atomic_state *state)
11972 {
11973         struct drm_device *dev = state->dev;
11974         struct drm_i915_private *dev_priv = to_i915(dev);
11975
11976         /* Is there platform-specific watermark information to calculate? */
11977         if (dev_priv->display.compute_global_watermarks)
11978                 return dev_priv->display.compute_global_watermarks(state);
11979
11980         return 0;
11981 }
11982
11983 /**
11984  * intel_atomic_check - validate state object
11985  * @dev: drm device
11986  * @state: state to validate
11987  */
11988 static int intel_atomic_check(struct drm_device *dev,
11989                               struct drm_atomic_state *state)
11990 {
11991         struct drm_i915_private *dev_priv = to_i915(dev);
11992         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11993         struct drm_crtc *crtc;
11994         struct drm_crtc_state *old_crtc_state, *crtc_state;
11995         int ret, i;
11996         bool any_ms = false;
11997
11998         ret = drm_atomic_helper_check_modeset(dev, state);
11999         if (ret)
12000                 return ret;
12001
12002         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12003                 struct intel_crtc_state *pipe_config =
12004                         to_intel_crtc_state(crtc_state);
12005
12006                 /* Catch I915_MODE_FLAG_INHERITED */
12007                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12008                         crtc_state->mode_changed = true;
12009
12010                 if (!needs_modeset(crtc_state))
12011                         continue;
12012
12013                 if (!crtc_state->enable) {
12014                         any_ms = true;
12015                         continue;
12016                 }
12017
12018                 /* FIXME: For only active_changed we shouldn't need to do any
12019                  * state recomputation at all. */
12020
12021                 ret = drm_atomic_add_affected_connectors(state, crtc);
12022                 if (ret)
12023                         return ret;
12024
12025                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12026                 if (ret) {
12027                         intel_dump_pipe_config(to_intel_crtc(crtc),
12028                                                pipe_config, "[failed]");
12029                         return ret;
12030                 }
12031
12032                 if (i915_modparams.fastboot &&
12033                     intel_pipe_config_compare(dev_priv,
12034                                         to_intel_crtc_state(old_crtc_state),
12035                                         pipe_config, true)) {
12036                         crtc_state->mode_changed = false;
12037                         pipe_config->update_pipe = true;
12038                 }
12039
12040                 if (needs_modeset(crtc_state))
12041                         any_ms = true;
12042
12043                 ret = drm_atomic_add_affected_planes(state, crtc);
12044                 if (ret)
12045                         return ret;
12046
12047                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12048                                        needs_modeset(crtc_state) ?
12049                                        "[modeset]" : "[fastset]");
12050         }
12051
12052         if (any_ms) {
12053                 ret = intel_modeset_checks(state);
12054
12055                 if (ret)
12056                         return ret;
12057         } else {
12058                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12059         }
12060
12061         ret = drm_atomic_helper_check_planes(dev, state);
12062         if (ret)
12063                 return ret;
12064
12065         intel_fbc_choose_crtc(dev_priv, state);
12066         return calc_watermark_data(state);
12067 }
12068
12069 static int intel_atomic_prepare_commit(struct drm_device *dev,
12070                                        struct drm_atomic_state *state)
12071 {
12072         return drm_atomic_helper_prepare_planes(dev, state);
12073 }
12074
12075 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12076 {
12077         struct drm_device *dev = crtc->base.dev;
12078
12079         if (!dev->max_vblank_count)
12080                 return drm_crtc_accurate_vblank_count(&crtc->base);
12081
12082         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12083 }
12084
12085 static void intel_update_crtc(struct drm_crtc *crtc,
12086                               struct drm_atomic_state *state,
12087                               struct drm_crtc_state *old_crtc_state,
12088                               struct drm_crtc_state *new_crtc_state)
12089 {
12090         struct drm_device *dev = crtc->dev;
12091         struct drm_i915_private *dev_priv = to_i915(dev);
12092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12093         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12094         bool modeset = needs_modeset(new_crtc_state);
12095
12096         if (modeset) {
12097                 update_scanline_offset(intel_crtc);
12098                 dev_priv->display.crtc_enable(pipe_config, state);
12099         } else {
12100                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12101                                        pipe_config);
12102         }
12103
12104         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12105                 intel_fbc_enable(
12106                     intel_crtc, pipe_config,
12107                     to_intel_plane_state(crtc->primary->state));
12108         }
12109
12110         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12111 }
12112
12113 static void intel_update_crtcs(struct drm_atomic_state *state)
12114 {
12115         struct drm_crtc *crtc;
12116         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12117         int i;
12118
12119         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12120                 if (!new_crtc_state->active)
12121                         continue;
12122
12123                 intel_update_crtc(crtc, state, old_crtc_state,
12124                                   new_crtc_state);
12125         }
12126 }
12127
12128 static void skl_update_crtcs(struct drm_atomic_state *state)
12129 {
12130         struct drm_i915_private *dev_priv = to_i915(state->dev);
12131         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12132         struct drm_crtc *crtc;
12133         struct intel_crtc *intel_crtc;
12134         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12135         struct intel_crtc_state *cstate;
12136         unsigned int updated = 0;
12137         bool progress;
12138         enum pipe pipe;
12139         int i;
12140
12141         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12142
12143         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12144                 /* ignore allocations for crtc's that have been turned off. */
12145                 if (new_crtc_state->active)
12146                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12147
12148         /*
12149          * Whenever the number of active pipes changes, we need to make sure we
12150          * update the pipes in the right order so that their ddb allocations
12151          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12152          * cause pipe underruns and other bad stuff.
12153          */
12154         do {
12155                 progress = false;
12156
12157                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12158                         bool vbl_wait = false;
12159                         unsigned int cmask = drm_crtc_mask(crtc);
12160
12161                         intel_crtc = to_intel_crtc(crtc);
12162                         cstate = to_intel_crtc_state(new_crtc_state);
12163                         pipe = intel_crtc->pipe;
12164
12165                         if (updated & cmask || !cstate->base.active)
12166                                 continue;
12167
12168                         if (skl_ddb_allocation_overlaps(dev_priv,
12169                                                         entries,
12170                                                         &cstate->wm.skl.ddb,
12171                                                         i))
12172                                 continue;
12173
12174                         updated |= cmask;
12175                         entries[i] = &cstate->wm.skl.ddb;
12176
12177                         /*
12178                          * If this is an already active pipe, it's DDB changed,
12179                          * and this isn't the last pipe that needs updating
12180                          * then we need to wait for a vblank to pass for the
12181                          * new ddb allocation to take effect.
12182                          */
12183                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12184                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12185                             !new_crtc_state->active_changed &&
12186                             intel_state->wm_results.dirty_pipes != updated)
12187                                 vbl_wait = true;
12188
12189                         intel_update_crtc(crtc, state, old_crtc_state,
12190                                           new_crtc_state);
12191
12192                         if (vbl_wait)
12193                                 intel_wait_for_vblank(dev_priv, pipe);
12194
12195                         progress = true;
12196                 }
12197         } while (progress);
12198 }
12199
12200 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12201 {
12202         struct intel_atomic_state *state, *next;
12203         struct llist_node *freed;
12204
12205         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12206         llist_for_each_entry_safe(state, next, freed, freed)
12207                 drm_atomic_state_put(&state->base);
12208 }
12209
12210 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12211 {
12212         struct drm_i915_private *dev_priv =
12213                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12214
12215         intel_atomic_helper_free_state(dev_priv);
12216 }
12217
12218 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12219 {
12220         struct wait_queue_entry wait_fence, wait_reset;
12221         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12222
12223         init_wait_entry(&wait_fence, 0);
12224         init_wait_entry(&wait_reset, 0);
12225         for (;;) {
12226                 prepare_to_wait(&intel_state->commit_ready.wait,
12227                                 &wait_fence, TASK_UNINTERRUPTIBLE);
12228                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12229                                 &wait_reset, TASK_UNINTERRUPTIBLE);
12230
12231
12232                 if (i915_sw_fence_done(&intel_state->commit_ready)
12233                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12234                         break;
12235
12236                 schedule();
12237         }
12238         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12239         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12240 }
12241
12242 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12243 {
12244         struct drm_device *dev = state->dev;
12245         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12246         struct drm_i915_private *dev_priv = to_i915(dev);
12247         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12248         struct drm_crtc *crtc;
12249         struct intel_crtc_state *intel_cstate;
12250         u64 put_domains[I915_MAX_PIPES] = {};
12251         int i;
12252
12253         intel_atomic_commit_fence_wait(intel_state);
12254
12255         drm_atomic_helper_wait_for_dependencies(state);
12256
12257         if (intel_state->modeset)
12258                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12259
12260         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12261                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12262
12263                 if (needs_modeset(new_crtc_state) ||
12264                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12265
12266                         put_domains[to_intel_crtc(crtc)->pipe] =
12267                                 modeset_get_crtc_power_domains(crtc,
12268                                         to_intel_crtc_state(new_crtc_state));
12269                 }
12270
12271                 if (!needs_modeset(new_crtc_state))
12272                         continue;
12273
12274                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12275                                        to_intel_crtc_state(new_crtc_state));
12276
12277                 if (old_crtc_state->active) {
12278                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12279                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12280                         intel_crtc->active = false;
12281                         intel_fbc_disable(intel_crtc);
12282                         intel_disable_shared_dpll(intel_crtc);
12283
12284                         /*
12285                          * Underruns don't always raise
12286                          * interrupts, so check manually.
12287                          */
12288                         intel_check_cpu_fifo_underruns(dev_priv);
12289                         intel_check_pch_fifo_underruns(dev_priv);
12290
12291                         if (!new_crtc_state->active) {
12292                                 /*
12293                                  * Make sure we don't call initial_watermarks
12294                                  * for ILK-style watermark updates.
12295                                  *
12296                                  * No clue what this is supposed to achieve.
12297                                  */
12298                                 if (INTEL_GEN(dev_priv) >= 9)
12299                                         dev_priv->display.initial_watermarks(intel_state,
12300                                                                              to_intel_crtc_state(new_crtc_state));
12301                         }
12302                 }
12303         }
12304
12305         /* Only after disabling all output pipelines that will be changed can we
12306          * update the the output configuration. */
12307         intel_modeset_update_crtc_state(state);
12308
12309         if (intel_state->modeset) {
12310                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12311
12312                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12313
12314                 /*
12315                  * SKL workaround: bspec recommends we disable the SAGV when we
12316                  * have more then one pipe enabled
12317                  */
12318                 if (!intel_can_enable_sagv(state))
12319                         intel_disable_sagv(dev_priv);
12320
12321                 intel_modeset_verify_disabled(dev, state);
12322         }
12323
12324         /* Complete the events for pipes that have now been disabled */
12325         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12326                 bool modeset = needs_modeset(new_crtc_state);
12327
12328                 /* Complete events for now disable pipes here. */
12329                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12330                         spin_lock_irq(&dev->event_lock);
12331                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12332                         spin_unlock_irq(&dev->event_lock);
12333
12334                         new_crtc_state->event = NULL;
12335                 }
12336         }
12337
12338         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12339         dev_priv->display.update_crtcs(state);
12340
12341         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12342          * already, but still need the state for the delayed optimization. To
12343          * fix this:
12344          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12345          * - schedule that vblank worker _before_ calling hw_done
12346          * - at the start of commit_tail, cancel it _synchrously
12347          * - switch over to the vblank wait helper in the core after that since
12348          *   we don't need out special handling any more.
12349          */
12350         drm_atomic_helper_wait_for_flip_done(dev, state);
12351
12352         /*
12353          * Now that the vblank has passed, we can go ahead and program the
12354          * optimal watermarks on platforms that need two-step watermark
12355          * programming.
12356          *
12357          * TODO: Move this (and other cleanup) to an async worker eventually.
12358          */
12359         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12360                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12361
12362                 if (dev_priv->display.optimize_watermarks)
12363                         dev_priv->display.optimize_watermarks(intel_state,
12364                                                               intel_cstate);
12365         }
12366
12367         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12368                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12369
12370                 if (put_domains[i])
12371                         modeset_put_power_domains(dev_priv, put_domains[i]);
12372
12373                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12374         }
12375
12376         if (intel_state->modeset && intel_can_enable_sagv(state))
12377                 intel_enable_sagv(dev_priv);
12378
12379         drm_atomic_helper_commit_hw_done(state);
12380
12381         if (intel_state->modeset) {
12382                 /* As one of the primary mmio accessors, KMS has a high
12383                  * likelihood of triggering bugs in unclaimed access. After we
12384                  * finish modesetting, see if an error has been flagged, and if
12385                  * so enable debugging for the next modeset - and hope we catch
12386                  * the culprit.
12387                  */
12388                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12389                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12390         }
12391
12392         drm_atomic_helper_cleanup_planes(dev, state);
12393
12394         drm_atomic_helper_commit_cleanup_done(state);
12395
12396         drm_atomic_state_put(state);
12397
12398         intel_atomic_helper_free_state(dev_priv);
12399 }
12400
12401 static void intel_atomic_commit_work(struct work_struct *work)
12402 {
12403         struct drm_atomic_state *state =
12404                 container_of(work, struct drm_atomic_state, commit_work);
12405
12406         intel_atomic_commit_tail(state);
12407 }
12408
12409 static int __i915_sw_fence_call
12410 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12411                           enum i915_sw_fence_notify notify)
12412 {
12413         struct intel_atomic_state *state =
12414                 container_of(fence, struct intel_atomic_state, commit_ready);
12415
12416         switch (notify) {
12417         case FENCE_COMPLETE:
12418                 /* we do blocking waits in the worker, nothing to do here */
12419                 break;
12420         case FENCE_FREE:
12421                 {
12422                         struct intel_atomic_helper *helper =
12423                                 &to_i915(state->base.dev)->atomic_helper;
12424
12425                         if (llist_add(&state->freed, &helper->free_list))
12426                                 schedule_work(&helper->free_work);
12427                         break;
12428                 }
12429         }
12430
12431         return NOTIFY_DONE;
12432 }
12433
12434 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12435 {
12436         struct drm_plane_state *old_plane_state, *new_plane_state;
12437         struct drm_plane *plane;
12438         int i;
12439
12440         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12441                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12442                                   intel_fb_obj(new_plane_state->fb),
12443                                   to_intel_plane(plane)->frontbuffer_bit);
12444 }
12445
12446 /**
12447  * intel_atomic_commit - commit validated state object
12448  * @dev: DRM device
12449  * @state: the top-level driver state object
12450  * @nonblock: nonblocking commit
12451  *
12452  * This function commits a top-level state object that has been validated
12453  * with drm_atomic_helper_check().
12454  *
12455  * RETURNS
12456  * Zero for success or -errno.
12457  */
12458 static int intel_atomic_commit(struct drm_device *dev,
12459                                struct drm_atomic_state *state,
12460                                bool nonblock)
12461 {
12462         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12463         struct drm_i915_private *dev_priv = to_i915(dev);
12464         int ret = 0;
12465
12466         drm_atomic_state_get(state);
12467         i915_sw_fence_init(&intel_state->commit_ready,
12468                            intel_atomic_commit_ready);
12469
12470         /*
12471          * The intel_legacy_cursor_update() fast path takes care
12472          * of avoiding the vblank waits for simple cursor
12473          * movement and flips. For cursor on/off and size changes,
12474          * we want to perform the vblank waits so that watermark
12475          * updates happen during the correct frames. Gen9+ have
12476          * double buffered watermarks and so shouldn't need this.
12477          *
12478          * Unset state->legacy_cursor_update before the call to
12479          * drm_atomic_helper_setup_commit() because otherwise
12480          * drm_atomic_helper_wait_for_flip_done() is a noop and
12481          * we get FIFO underruns because we didn't wait
12482          * for vblank.
12483          *
12484          * FIXME doing watermarks and fb cleanup from a vblank worker
12485          * (assuming we had any) would solve these problems.
12486          */
12487         if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12488                 struct intel_crtc_state *new_crtc_state;
12489                 struct intel_crtc *crtc;
12490                 int i;
12491
12492                 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12493                         if (new_crtc_state->wm.need_postvbl_update ||
12494                             new_crtc_state->update_wm_post)
12495                                 state->legacy_cursor_update = false;
12496         }
12497
12498         ret = intel_atomic_prepare_commit(dev, state);
12499         if (ret) {
12500                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12501                 i915_sw_fence_commit(&intel_state->commit_ready);
12502                 return ret;
12503         }
12504
12505         ret = drm_atomic_helper_setup_commit(state, nonblock);
12506         if (!ret)
12507                 ret = drm_atomic_helper_swap_state(state, true);
12508
12509         if (ret) {
12510                 i915_sw_fence_commit(&intel_state->commit_ready);
12511
12512                 drm_atomic_helper_cleanup_planes(dev, state);
12513                 return ret;
12514         }
12515         dev_priv->wm.distrust_bios_wm = false;
12516         intel_shared_dpll_swap_state(state);
12517         intel_atomic_track_fbs(state);
12518
12519         if (intel_state->modeset) {
12520                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12521                        sizeof(intel_state->min_cdclk));
12522                 dev_priv->active_crtcs = intel_state->active_crtcs;
12523                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12524                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12525         }
12526
12527         drm_atomic_state_get(state);
12528         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12529
12530         i915_sw_fence_commit(&intel_state->commit_ready);
12531         if (nonblock)
12532                 queue_work(system_unbound_wq, &state->commit_work);
12533         else
12534                 intel_atomic_commit_tail(state);
12535
12536
12537         return 0;
12538 }
12539
12540 static const struct drm_crtc_funcs intel_crtc_funcs = {
12541         .gamma_set = drm_atomic_helper_legacy_gamma_set,
12542         .set_config = drm_atomic_helper_set_config,
12543         .destroy = intel_crtc_destroy,
12544         .page_flip = drm_atomic_helper_page_flip,
12545         .atomic_duplicate_state = intel_crtc_duplicate_state,
12546         .atomic_destroy_state = intel_crtc_destroy_state,
12547         .set_crc_source = intel_crtc_set_crc_source,
12548 };
12549
12550 struct wait_rps_boost {
12551         struct wait_queue_entry wait;
12552
12553         struct drm_crtc *crtc;
12554         struct drm_i915_gem_request *request;
12555 };
12556
12557 static int do_rps_boost(struct wait_queue_entry *_wait,
12558                         unsigned mode, int sync, void *key)
12559 {
12560         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12561         struct drm_i915_gem_request *rq = wait->request;
12562
12563         gen6_rps_boost(rq, NULL);
12564         i915_gem_request_put(rq);
12565
12566         drm_crtc_vblank_put(wait->crtc);
12567
12568         list_del(&wait->wait.entry);
12569         kfree(wait);
12570         return 1;
12571 }
12572
12573 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12574                                        struct dma_fence *fence)
12575 {
12576         struct wait_rps_boost *wait;
12577
12578         if (!dma_fence_is_i915(fence))
12579                 return;
12580
12581         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12582                 return;
12583
12584         if (drm_crtc_vblank_get(crtc))
12585                 return;
12586
12587         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12588         if (!wait) {
12589                 drm_crtc_vblank_put(crtc);
12590                 return;
12591         }
12592
12593         wait->request = to_request(dma_fence_get(fence));
12594         wait->crtc = crtc;
12595
12596         wait->wait.func = do_rps_boost;
12597         wait->wait.flags = 0;
12598
12599         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12600 }
12601
12602 /**
12603  * intel_prepare_plane_fb - Prepare fb for usage on plane
12604  * @plane: drm plane to prepare for
12605  * @fb: framebuffer to prepare for presentation
12606  *
12607  * Prepares a framebuffer for usage on a display plane.  Generally this
12608  * involves pinning the underlying object and updating the frontbuffer tracking
12609  * bits.  Some older platforms need special physical address handling for
12610  * cursor planes.
12611  *
12612  * Must be called with struct_mutex held.
12613  *
12614  * Returns 0 on success, negative error code on failure.
12615  */
12616 int
12617 intel_prepare_plane_fb(struct drm_plane *plane,
12618                        struct drm_plane_state *new_state)
12619 {
12620         struct intel_atomic_state *intel_state =
12621                 to_intel_atomic_state(new_state->state);
12622         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12623         struct drm_framebuffer *fb = new_state->fb;
12624         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12625         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12626         int ret;
12627
12628         if (old_obj) {
12629                 struct drm_crtc_state *crtc_state =
12630                         drm_atomic_get_existing_crtc_state(new_state->state,
12631                                                            plane->state->crtc);
12632
12633                 /* Big Hammer, we also need to ensure that any pending
12634                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12635                  * current scanout is retired before unpinning the old
12636                  * framebuffer. Note that we rely on userspace rendering
12637                  * into the buffer attached to the pipe they are waiting
12638                  * on. If not, userspace generates a GPU hang with IPEHR
12639                  * point to the MI_WAIT_FOR_EVENT.
12640                  *
12641                  * This should only fail upon a hung GPU, in which case we
12642                  * can safely continue.
12643                  */
12644                 if (needs_modeset(crtc_state)) {
12645                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12646                                                               old_obj->resv, NULL,
12647                                                               false, 0,
12648                                                               GFP_KERNEL);
12649                         if (ret < 0)
12650                                 return ret;
12651                 }
12652         }
12653
12654         if (new_state->fence) { /* explicit fencing */
12655                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12656                                                     new_state->fence,
12657                                                     I915_FENCE_TIMEOUT,
12658                                                     GFP_KERNEL);
12659                 if (ret < 0)
12660                         return ret;
12661         }
12662
12663         if (!obj)
12664                 return 0;
12665
12666         ret = i915_gem_object_pin_pages(obj);
12667         if (ret)
12668                 return ret;
12669
12670         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12671         if (ret) {
12672                 i915_gem_object_unpin_pages(obj);
12673                 return ret;
12674         }
12675
12676         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12677             INTEL_INFO(dev_priv)->cursor_needs_physical) {
12678                 const int align = intel_cursor_alignment(dev_priv);
12679
12680                 ret = i915_gem_object_attach_phys(obj, align);
12681         } else {
12682                 struct i915_vma *vma;
12683
12684                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12685                 if (!IS_ERR(vma))
12686                         to_intel_plane_state(new_state)->vma = vma;
12687                 else
12688                         ret =  PTR_ERR(vma);
12689         }
12690
12691         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12692
12693         mutex_unlock(&dev_priv->drm.struct_mutex);
12694         i915_gem_object_unpin_pages(obj);
12695         if (ret)
12696                 return ret;
12697
12698         if (!new_state->fence) { /* implicit fencing */
12699                 struct dma_fence *fence;
12700
12701                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12702                                                       obj->resv, NULL,
12703                                                       false, I915_FENCE_TIMEOUT,
12704                                                       GFP_KERNEL);
12705                 if (ret < 0)
12706                         return ret;
12707
12708                 fence = reservation_object_get_excl_rcu(obj->resv);
12709                 if (fence) {
12710                         add_rps_boost_after_vblank(new_state->crtc, fence);
12711                         dma_fence_put(fence);
12712                 }
12713         } else {
12714                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12715         }
12716
12717         return 0;
12718 }
12719
12720 /**
12721  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12722  * @plane: drm plane to clean up for
12723  * @fb: old framebuffer that was on plane
12724  *
12725  * Cleans up a framebuffer that has just been removed from a plane.
12726  *
12727  * Must be called with struct_mutex held.
12728  */
12729 void
12730 intel_cleanup_plane_fb(struct drm_plane *plane,
12731                        struct drm_plane_state *old_state)
12732 {
12733         struct i915_vma *vma;
12734
12735         /* Should only be called after a successful intel_prepare_plane_fb()! */
12736         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12737         if (vma) {
12738                 mutex_lock(&plane->dev->struct_mutex);
12739                 intel_unpin_fb_vma(vma);
12740                 mutex_unlock(&plane->dev->struct_mutex);
12741         }
12742 }
12743
12744 int
12745 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12746 {
12747         struct drm_i915_private *dev_priv;
12748         int max_scale;
12749         int crtc_clock, max_dotclk;
12750
12751         if (!intel_crtc || !crtc_state->base.enable)
12752                 return DRM_PLANE_HELPER_NO_SCALING;
12753
12754         dev_priv = to_i915(intel_crtc->base.dev);
12755
12756         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12757         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12758
12759         if (IS_GEMINILAKE(dev_priv))
12760                 max_dotclk *= 2;
12761
12762         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12763                 return DRM_PLANE_HELPER_NO_SCALING;
12764
12765         /*
12766          * skl max scale is lower of:
12767          *    close to 3 but not 3, -1 is for that purpose
12768          *            or
12769          *    cdclk/crtc_clock
12770          */
12771         max_scale = min((1 << 16) * 3 - 1,
12772                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12773
12774         return max_scale;
12775 }
12776
12777 static int
12778 intel_check_primary_plane(struct intel_plane *plane,
12779                           struct intel_crtc_state *crtc_state,
12780                           struct intel_plane_state *state)
12781 {
12782         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12783         struct drm_crtc *crtc = state->base.crtc;
12784         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12785         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12786         bool can_position = false;
12787         int ret;
12788
12789         if (INTEL_GEN(dev_priv) >= 9) {
12790                 /* use scaler when colorkey is not required */
12791                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12792                         min_scale = 1;
12793                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12794                 }
12795                 can_position = true;
12796         }
12797
12798         ret = drm_atomic_helper_check_plane_state(&state->base,
12799                                                   &crtc_state->base,
12800                                                   &state->clip,
12801                                                   min_scale, max_scale,
12802                                                   can_position, true);
12803         if (ret)
12804                 return ret;
12805
12806         if (!state->base.fb)
12807                 return 0;
12808
12809         if (INTEL_GEN(dev_priv) >= 9) {
12810                 ret = skl_check_plane_surface(state);
12811                 if (ret)
12812                         return ret;
12813
12814                 state->ctl = skl_plane_ctl(crtc_state, state);
12815         } else {
12816                 ret = i9xx_check_plane_surface(state);
12817                 if (ret)
12818                         return ret;
12819
12820                 state->ctl = i9xx_plane_ctl(crtc_state, state);
12821         }
12822
12823         return 0;
12824 }
12825
12826 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12827                                     struct drm_crtc_state *old_crtc_state)
12828 {
12829         struct drm_device *dev = crtc->dev;
12830         struct drm_i915_private *dev_priv = to_i915(dev);
12831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12832         struct intel_crtc_state *old_intel_cstate =
12833                 to_intel_crtc_state(old_crtc_state);
12834         struct intel_atomic_state *old_intel_state =
12835                 to_intel_atomic_state(old_crtc_state->state);
12836         struct intel_crtc_state *intel_cstate =
12837                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12838         bool modeset = needs_modeset(&intel_cstate->base);
12839
12840         if (!modeset &&
12841             (intel_cstate->base.color_mgmt_changed ||
12842              intel_cstate->update_pipe)) {
12843                 intel_color_set_csc(&intel_cstate->base);
12844                 intel_color_load_luts(&intel_cstate->base);
12845         }
12846
12847         /* Perform vblank evasion around commit operation */
12848         intel_pipe_update_start(intel_cstate);
12849
12850         if (modeset)
12851                 goto out;
12852
12853         if (intel_cstate->update_pipe)
12854                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12855         else if (INTEL_GEN(dev_priv) >= 9)
12856                 skl_detach_scalers(intel_crtc);
12857
12858 out:
12859         if (dev_priv->display.atomic_update_watermarks)
12860                 dev_priv->display.atomic_update_watermarks(old_intel_state,
12861                                                            intel_cstate);
12862 }
12863
12864 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12865                                      struct drm_crtc_state *old_crtc_state)
12866 {
12867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12868         struct intel_atomic_state *old_intel_state =
12869                 to_intel_atomic_state(old_crtc_state->state);
12870         struct intel_crtc_state *new_crtc_state =
12871                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12872
12873         intel_pipe_update_end(new_crtc_state);
12874 }
12875
12876 /**
12877  * intel_plane_destroy - destroy a plane
12878  * @plane: plane to destroy
12879  *
12880  * Common destruction function for all types of planes (primary, cursor,
12881  * sprite).
12882  */
12883 void intel_plane_destroy(struct drm_plane *plane)
12884 {
12885         drm_plane_cleanup(plane);
12886         kfree(to_intel_plane(plane));
12887 }
12888
12889 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12890 {
12891         switch (format) {
12892         case DRM_FORMAT_C8:
12893         case DRM_FORMAT_RGB565:
12894         case DRM_FORMAT_XRGB1555:
12895         case DRM_FORMAT_XRGB8888:
12896                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12897                         modifier == I915_FORMAT_MOD_X_TILED;
12898         default:
12899                 return false;
12900         }
12901 }
12902
12903 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12904 {
12905         switch (format) {
12906         case DRM_FORMAT_C8:
12907         case DRM_FORMAT_RGB565:
12908         case DRM_FORMAT_XRGB8888:
12909         case DRM_FORMAT_XBGR8888:
12910         case DRM_FORMAT_XRGB2101010:
12911         case DRM_FORMAT_XBGR2101010:
12912                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12913                         modifier == I915_FORMAT_MOD_X_TILED;
12914         default:
12915                 return false;
12916         }
12917 }
12918
12919 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
12920 {
12921         switch (format) {
12922         case DRM_FORMAT_XRGB8888:
12923         case DRM_FORMAT_XBGR8888:
12924         case DRM_FORMAT_ARGB8888:
12925         case DRM_FORMAT_ABGR8888:
12926                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
12927                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
12928                         return true;
12929                 /* fall through */
12930         case DRM_FORMAT_RGB565:
12931         case DRM_FORMAT_XRGB2101010:
12932         case DRM_FORMAT_XBGR2101010:
12933         case DRM_FORMAT_YUYV:
12934         case DRM_FORMAT_YVYU:
12935         case DRM_FORMAT_UYVY:
12936         case DRM_FORMAT_VYUY:
12937                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
12938                         return true;
12939                 /* fall through */
12940         case DRM_FORMAT_C8:
12941                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
12942                     modifier == I915_FORMAT_MOD_X_TILED ||
12943                     modifier == I915_FORMAT_MOD_Y_TILED)
12944                         return true;
12945                 /* fall through */
12946         default:
12947                 return false;
12948         }
12949 }
12950
12951 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
12952                                                      uint32_t format,
12953                                                      uint64_t modifier)
12954 {
12955         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12956
12957         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12958                 return false;
12959
12960         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
12961             modifier != DRM_FORMAT_MOD_LINEAR)
12962                 return false;
12963
12964         if (INTEL_GEN(dev_priv) >= 9)
12965                 return skl_mod_supported(format, modifier);
12966         else if (INTEL_GEN(dev_priv) >= 4)
12967                 return i965_mod_supported(format, modifier);
12968         else
12969                 return i8xx_mod_supported(format, modifier);
12970
12971         unreachable();
12972 }
12973
12974 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
12975                                                     uint32_t format,
12976                                                     uint64_t modifier)
12977 {
12978         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12979                 return false;
12980
12981         return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
12982 }
12983
12984 static struct drm_plane_funcs intel_plane_funcs = {
12985         .update_plane = drm_atomic_helper_update_plane,
12986         .disable_plane = drm_atomic_helper_disable_plane,
12987         .destroy = intel_plane_destroy,
12988         .atomic_get_property = intel_plane_atomic_get_property,
12989         .atomic_set_property = intel_plane_atomic_set_property,
12990         .atomic_duplicate_state = intel_plane_duplicate_state,
12991         .atomic_destroy_state = intel_plane_destroy_state,
12992         .format_mod_supported = intel_primary_plane_format_mod_supported,
12993 };
12994
12995 static int
12996 intel_legacy_cursor_update(struct drm_plane *plane,
12997                            struct drm_crtc *crtc,
12998                            struct drm_framebuffer *fb,
12999                            int crtc_x, int crtc_y,
13000                            unsigned int crtc_w, unsigned int crtc_h,
13001                            uint32_t src_x, uint32_t src_y,
13002                            uint32_t src_w, uint32_t src_h,
13003                            struct drm_modeset_acquire_ctx *ctx)
13004 {
13005         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13006         int ret;
13007         struct drm_plane_state *old_plane_state, *new_plane_state;
13008         struct intel_plane *intel_plane = to_intel_plane(plane);
13009         struct drm_framebuffer *old_fb;
13010         struct drm_crtc_state *crtc_state = crtc->state;
13011         struct i915_vma *old_vma, *vma;
13012
13013         /*
13014          * When crtc is inactive or there is a modeset pending,
13015          * wait for it to complete in the slowpath
13016          */
13017         if (!crtc_state->active || needs_modeset(crtc_state) ||
13018             to_intel_crtc_state(crtc_state)->update_pipe)
13019                 goto slow;
13020
13021         old_plane_state = plane->state;
13022         /*
13023          * Don't do an async update if there is an outstanding commit modifying
13024          * the plane.  This prevents our async update's changes from getting
13025          * overridden by a previous synchronous update's state.
13026          */
13027         if (old_plane_state->commit &&
13028             !try_wait_for_completion(&old_plane_state->commit->hw_done))
13029                 goto slow;
13030
13031         /*
13032          * If any parameters change that may affect watermarks,
13033          * take the slowpath. Only changing fb or position should be
13034          * in the fastpath.
13035          */
13036         if (old_plane_state->crtc != crtc ||
13037             old_plane_state->src_w != src_w ||
13038             old_plane_state->src_h != src_h ||
13039             old_plane_state->crtc_w != crtc_w ||
13040             old_plane_state->crtc_h != crtc_h ||
13041             !old_plane_state->fb != !fb)
13042                 goto slow;
13043
13044         new_plane_state = intel_plane_duplicate_state(plane);
13045         if (!new_plane_state)
13046                 return -ENOMEM;
13047
13048         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13049
13050         new_plane_state->src_x = src_x;
13051         new_plane_state->src_y = src_y;
13052         new_plane_state->src_w = src_w;
13053         new_plane_state->src_h = src_h;
13054         new_plane_state->crtc_x = crtc_x;
13055         new_plane_state->crtc_y = crtc_y;
13056         new_plane_state->crtc_w = crtc_w;
13057         new_plane_state->crtc_h = crtc_h;
13058
13059         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13060                                                   to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13061                                                   to_intel_plane_state(plane->state),
13062                                                   to_intel_plane_state(new_plane_state));
13063         if (ret)
13064                 goto out_free;
13065
13066         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13067         if (ret)
13068                 goto out_free;
13069
13070         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13071                 int align = intel_cursor_alignment(dev_priv);
13072
13073                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13074                 if (ret) {
13075                         DRM_DEBUG_KMS("failed to attach phys object\n");
13076                         goto out_unlock;
13077                 }
13078         } else {
13079                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13080                 if (IS_ERR(vma)) {
13081                         DRM_DEBUG_KMS("failed to pin object\n");
13082
13083                         ret = PTR_ERR(vma);
13084                         goto out_unlock;
13085                 }
13086
13087                 to_intel_plane_state(new_plane_state)->vma = vma;
13088         }
13089
13090         old_fb = old_plane_state->fb;
13091
13092         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13093                           intel_plane->frontbuffer_bit);
13094
13095         /* Swap plane state */
13096         plane->state = new_plane_state;
13097
13098         if (plane->state->visible) {
13099                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13100                 intel_plane->update_plane(intel_plane,
13101                                           to_intel_crtc_state(crtc->state),
13102                                           to_intel_plane_state(plane->state));
13103         } else {
13104                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13105                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13106         }
13107
13108         old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13109         if (old_vma)
13110                 intel_unpin_fb_vma(old_vma);
13111
13112 out_unlock:
13113         mutex_unlock(&dev_priv->drm.struct_mutex);
13114 out_free:
13115         if (ret)
13116                 intel_plane_destroy_state(plane, new_plane_state);
13117         else
13118                 intel_plane_destroy_state(plane, old_plane_state);
13119         return ret;
13120
13121 slow:
13122         return drm_atomic_helper_update_plane(plane, crtc, fb,
13123                                               crtc_x, crtc_y, crtc_w, crtc_h,
13124                                               src_x, src_y, src_w, src_h, ctx);
13125 }
13126
13127 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13128         .update_plane = intel_legacy_cursor_update,
13129         .disable_plane = drm_atomic_helper_disable_plane,
13130         .destroy = intel_plane_destroy,
13131         .atomic_get_property = intel_plane_atomic_get_property,
13132         .atomic_set_property = intel_plane_atomic_set_property,
13133         .atomic_duplicate_state = intel_plane_duplicate_state,
13134         .atomic_destroy_state = intel_plane_destroy_state,
13135         .format_mod_supported = intel_cursor_plane_format_mod_supported,
13136 };
13137
13138 static struct intel_plane *
13139 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13140 {
13141         struct intel_plane *primary = NULL;
13142         struct intel_plane_state *state = NULL;
13143         const uint32_t *intel_primary_formats;
13144         unsigned int supported_rotations;
13145         unsigned int num_formats;
13146         const uint64_t *modifiers;
13147         int ret;
13148
13149         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13150         if (!primary) {
13151                 ret = -ENOMEM;
13152                 goto fail;
13153         }
13154
13155         state = intel_create_plane_state(&primary->base);
13156         if (!state) {
13157                 ret = -ENOMEM;
13158                 goto fail;
13159         }
13160
13161         primary->base.state = &state->base;
13162
13163         primary->can_scale = false;
13164         primary->max_downscale = 1;
13165         if (INTEL_GEN(dev_priv) >= 9) {
13166                 primary->can_scale = true;
13167                 state->scaler_id = -1;
13168         }
13169         primary->pipe = pipe;
13170         /*
13171          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13172          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13173          */
13174         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13175                 primary->plane = (enum plane) !pipe;
13176         else
13177                 primary->plane = (enum plane) pipe;
13178         primary->id = PLANE_PRIMARY;
13179         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13180         primary->check_plane = intel_check_primary_plane;
13181
13182         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13183                 intel_primary_formats = skl_primary_formats;
13184                 num_formats = ARRAY_SIZE(skl_primary_formats);
13185                 modifiers = skl_format_modifiers_ccs;
13186
13187                 primary->update_plane = skl_update_plane;
13188                 primary->disable_plane = skl_disable_plane;
13189         } else if (INTEL_GEN(dev_priv) >= 9) {
13190                 intel_primary_formats = skl_primary_formats;
13191                 num_formats = ARRAY_SIZE(skl_primary_formats);
13192                 if (pipe < PIPE_C)
13193                         modifiers = skl_format_modifiers_ccs;
13194                 else
13195                         modifiers = skl_format_modifiers_noccs;
13196
13197                 primary->update_plane = skl_update_plane;
13198                 primary->disable_plane = skl_disable_plane;
13199         } else if (INTEL_GEN(dev_priv) >= 4) {
13200                 intel_primary_formats = i965_primary_formats;
13201                 num_formats = ARRAY_SIZE(i965_primary_formats);
13202                 modifiers = i9xx_format_modifiers;
13203
13204                 primary->update_plane = i9xx_update_primary_plane;
13205                 primary->disable_plane = i9xx_disable_primary_plane;
13206         } else {
13207                 intel_primary_formats = i8xx_primary_formats;
13208                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13209                 modifiers = i9xx_format_modifiers;
13210
13211                 primary->update_plane = i9xx_update_primary_plane;
13212                 primary->disable_plane = i9xx_disable_primary_plane;
13213         }
13214
13215         if (INTEL_GEN(dev_priv) >= 9)
13216                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13217                                                0, &intel_plane_funcs,
13218                                                intel_primary_formats, num_formats,
13219                                                modifiers,
13220                                                DRM_PLANE_TYPE_PRIMARY,
13221                                                "plane 1%c", pipe_name(pipe));
13222         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13223                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13224                                                0, &intel_plane_funcs,
13225                                                intel_primary_formats, num_formats,
13226                                                modifiers,
13227                                                DRM_PLANE_TYPE_PRIMARY,
13228                                                "primary %c", pipe_name(pipe));
13229         else
13230                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13231                                                0, &intel_plane_funcs,
13232                                                intel_primary_formats, num_formats,
13233                                                modifiers,
13234                                                DRM_PLANE_TYPE_PRIMARY,
13235                                                "plane %c", plane_name(primary->plane));
13236         if (ret)
13237                 goto fail;
13238
13239         if (INTEL_GEN(dev_priv) >= 9) {
13240                 supported_rotations =
13241                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13242                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13243         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13244                 supported_rotations =
13245                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13246                         DRM_MODE_REFLECT_X;
13247         } else if (INTEL_GEN(dev_priv) >= 4) {
13248                 supported_rotations =
13249                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13250         } else {
13251                 supported_rotations = DRM_MODE_ROTATE_0;
13252         }
13253
13254         if (INTEL_GEN(dev_priv) >= 4)
13255                 drm_plane_create_rotation_property(&primary->base,
13256                                                    DRM_MODE_ROTATE_0,
13257                                                    supported_rotations);
13258
13259         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13260
13261         return primary;
13262
13263 fail:
13264         kfree(state);
13265         kfree(primary);
13266
13267         return ERR_PTR(ret);
13268 }
13269
13270 static struct intel_plane *
13271 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13272                           enum pipe pipe)
13273 {
13274         struct intel_plane *cursor = NULL;
13275         struct intel_plane_state *state = NULL;
13276         int ret;
13277
13278         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13279         if (!cursor) {
13280                 ret = -ENOMEM;
13281                 goto fail;
13282         }
13283
13284         state = intel_create_plane_state(&cursor->base);
13285         if (!state) {
13286                 ret = -ENOMEM;
13287                 goto fail;
13288         }
13289
13290         cursor->base.state = &state->base;
13291
13292         cursor->can_scale = false;
13293         cursor->max_downscale = 1;
13294         cursor->pipe = pipe;
13295         cursor->plane = pipe;
13296         cursor->id = PLANE_CURSOR;
13297         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13298
13299         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13300                 cursor->update_plane = i845_update_cursor;
13301                 cursor->disable_plane = i845_disable_cursor;
13302                 cursor->check_plane = i845_check_cursor;
13303         } else {
13304                 cursor->update_plane = i9xx_update_cursor;
13305                 cursor->disable_plane = i9xx_disable_cursor;
13306                 cursor->check_plane = i9xx_check_cursor;
13307         }
13308
13309         cursor->cursor.base = ~0;
13310         cursor->cursor.cntl = ~0;
13311
13312         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13313                 cursor->cursor.size = ~0;
13314
13315         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13316                                        0, &intel_cursor_plane_funcs,
13317                                        intel_cursor_formats,
13318                                        ARRAY_SIZE(intel_cursor_formats),
13319                                        cursor_format_modifiers,
13320                                        DRM_PLANE_TYPE_CURSOR,
13321                                        "cursor %c", pipe_name(pipe));
13322         if (ret)
13323                 goto fail;
13324
13325         if (INTEL_GEN(dev_priv) >= 4)
13326                 drm_plane_create_rotation_property(&cursor->base,
13327                                                    DRM_MODE_ROTATE_0,
13328                                                    DRM_MODE_ROTATE_0 |
13329                                                    DRM_MODE_ROTATE_180);
13330
13331         if (INTEL_GEN(dev_priv) >= 9)
13332                 state->scaler_id = -1;
13333
13334         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13335
13336         return cursor;
13337
13338 fail:
13339         kfree(state);
13340         kfree(cursor);
13341
13342         return ERR_PTR(ret);
13343 }
13344
13345 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13346                                     struct intel_crtc_state *crtc_state)
13347 {
13348         struct intel_crtc_scaler_state *scaler_state =
13349                 &crtc_state->scaler_state;
13350         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13351         int i;
13352
13353         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13354         if (!crtc->num_scalers)
13355                 return;
13356
13357         for (i = 0; i < crtc->num_scalers; i++) {
13358                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13359
13360                 scaler->in_use = 0;
13361                 scaler->mode = PS_SCALER_MODE_DYN;
13362         }
13363
13364         scaler_state->scaler_id = -1;
13365 }
13366
13367 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13368 {
13369         struct intel_crtc *intel_crtc;
13370         struct intel_crtc_state *crtc_state = NULL;
13371         struct intel_plane *primary = NULL;
13372         struct intel_plane *cursor = NULL;
13373         int sprite, ret;
13374
13375         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13376         if (!intel_crtc)
13377                 return -ENOMEM;
13378
13379         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13380         if (!crtc_state) {
13381                 ret = -ENOMEM;
13382                 goto fail;
13383         }
13384         intel_crtc->config = crtc_state;
13385         intel_crtc->base.state = &crtc_state->base;
13386         crtc_state->base.crtc = &intel_crtc->base;
13387
13388         primary = intel_primary_plane_create(dev_priv, pipe);
13389         if (IS_ERR(primary)) {
13390                 ret = PTR_ERR(primary);
13391                 goto fail;
13392         }
13393         intel_crtc->plane_ids_mask |= BIT(primary->id);
13394
13395         for_each_sprite(dev_priv, pipe, sprite) {
13396                 struct intel_plane *plane;
13397
13398                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13399                 if (IS_ERR(plane)) {
13400                         ret = PTR_ERR(plane);
13401                         goto fail;
13402                 }
13403                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13404         }
13405
13406         cursor = intel_cursor_plane_create(dev_priv, pipe);
13407         if (IS_ERR(cursor)) {
13408                 ret = PTR_ERR(cursor);
13409                 goto fail;
13410         }
13411         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13412
13413         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13414                                         &primary->base, &cursor->base,
13415                                         &intel_crtc_funcs,
13416                                         "pipe %c", pipe_name(pipe));
13417         if (ret)
13418                 goto fail;
13419
13420         intel_crtc->pipe = pipe;
13421         intel_crtc->plane = primary->plane;
13422
13423         /* initialize shared scalers */
13424         intel_crtc_init_scalers(intel_crtc, crtc_state);
13425
13426         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13427                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13428         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13429         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13430
13431         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13432
13433         intel_color_init(&intel_crtc->base);
13434
13435         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13436
13437         return 0;
13438
13439 fail:
13440         /*
13441          * drm_mode_config_cleanup() will free up any
13442          * crtcs/planes already initialized.
13443          */
13444         kfree(crtc_state);
13445         kfree(intel_crtc);
13446
13447         return ret;
13448 }
13449
13450 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13451 {
13452         struct drm_device *dev = connector->base.dev;
13453
13454         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13455
13456         if (!connector->base.state->crtc)
13457                 return INVALID_PIPE;
13458
13459         return to_intel_crtc(connector->base.state->crtc)->pipe;
13460 }
13461
13462 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13463                                 struct drm_file *file)
13464 {
13465         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13466         struct drm_crtc *drmmode_crtc;
13467         struct intel_crtc *crtc;
13468
13469         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13470         if (!drmmode_crtc)
13471                 return -ENOENT;
13472
13473         crtc = to_intel_crtc(drmmode_crtc);
13474         pipe_from_crtc_id->pipe = crtc->pipe;
13475
13476         return 0;
13477 }
13478
13479 static int intel_encoder_clones(struct intel_encoder *encoder)
13480 {
13481         struct drm_device *dev = encoder->base.dev;
13482         struct intel_encoder *source_encoder;
13483         int index_mask = 0;
13484         int entry = 0;
13485
13486         for_each_intel_encoder(dev, source_encoder) {
13487                 if (encoders_cloneable(encoder, source_encoder))
13488                         index_mask |= (1 << entry);
13489
13490                 entry++;
13491         }
13492
13493         return index_mask;
13494 }
13495
13496 static bool has_edp_a(struct drm_i915_private *dev_priv)
13497 {
13498         if (!IS_MOBILE(dev_priv))
13499                 return false;
13500
13501         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13502                 return false;
13503
13504         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13505                 return false;
13506
13507         return true;
13508 }
13509
13510 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13511 {
13512         if (INTEL_GEN(dev_priv) >= 9)
13513                 return false;
13514
13515         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13516                 return false;
13517
13518         if (IS_CHERRYVIEW(dev_priv))
13519                 return false;
13520
13521         if (HAS_PCH_LPT_H(dev_priv) &&
13522             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13523                 return false;
13524
13525         /* DDI E can't be used if DDI A requires 4 lanes */
13526         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13527                 return false;
13528
13529         if (!dev_priv->vbt.int_crt_support)
13530                 return false;
13531
13532         return true;
13533 }
13534
13535 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13536 {
13537         int pps_num;
13538         int pps_idx;
13539
13540         if (HAS_DDI(dev_priv))
13541                 return;
13542         /*
13543          * This w/a is needed at least on CPT/PPT, but to be sure apply it
13544          * everywhere where registers can be write protected.
13545          */
13546         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13547                 pps_num = 2;
13548         else
13549                 pps_num = 1;
13550
13551         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13552                 u32 val = I915_READ(PP_CONTROL(pps_idx));
13553
13554                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13555                 I915_WRITE(PP_CONTROL(pps_idx), val);
13556         }
13557 }
13558
13559 static void intel_pps_init(struct drm_i915_private *dev_priv)
13560 {
13561         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13562                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13563         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13564                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13565         else
13566                 dev_priv->pps_mmio_base = PPS_BASE;
13567
13568         intel_pps_unlock_regs_wa(dev_priv);
13569 }
13570
13571 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13572 {
13573         struct intel_encoder *encoder;
13574         bool dpd_is_edp = false;
13575
13576         intel_pps_init(dev_priv);
13577
13578         /*
13579          * intel_edp_init_connector() depends on this completing first, to
13580          * prevent the registeration of both eDP and LVDS and the incorrect
13581          * sharing of the PPS.
13582          */
13583         intel_lvds_init(dev_priv);
13584
13585         if (intel_crt_present(dev_priv))
13586                 intel_crt_init(dev_priv);
13587
13588         if (IS_GEN9_LP(dev_priv)) {
13589                 /*
13590                  * FIXME: Broxton doesn't support port detection via the
13591                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13592                  * detect the ports.
13593                  */
13594                 intel_ddi_init(dev_priv, PORT_A);
13595                 intel_ddi_init(dev_priv, PORT_B);
13596                 intel_ddi_init(dev_priv, PORT_C);
13597
13598                 intel_dsi_init(dev_priv);
13599         } else if (HAS_DDI(dev_priv)) {
13600                 int found;
13601
13602                 /*
13603                  * Haswell uses DDI functions to detect digital outputs.
13604                  * On SKL pre-D0 the strap isn't connected, so we assume
13605                  * it's there.
13606                  */
13607                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13608                 /* WaIgnoreDDIAStrap: skl */
13609                 if (found || IS_GEN9_BC(dev_priv))
13610                         intel_ddi_init(dev_priv, PORT_A);
13611
13612                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13613                  * register */
13614                 found = I915_READ(SFUSE_STRAP);
13615
13616                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13617                         intel_ddi_init(dev_priv, PORT_B);
13618                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13619                         intel_ddi_init(dev_priv, PORT_C);
13620                 if (found & SFUSE_STRAP_DDID_DETECTED)
13621                         intel_ddi_init(dev_priv, PORT_D);
13622                 /*
13623                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13624                  */
13625                 if (IS_GEN9_BC(dev_priv) &&
13626                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13627                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13628                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13629                         intel_ddi_init(dev_priv, PORT_E);
13630
13631         } else if (HAS_PCH_SPLIT(dev_priv)) {
13632                 int found;
13633                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13634
13635                 if (has_edp_a(dev_priv))
13636                         intel_dp_init(dev_priv, DP_A, PORT_A);
13637
13638                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13639                         /* PCH SDVOB multiplex with HDMIB */
13640                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13641                         if (!found)
13642                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13643                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13644                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13645                 }
13646
13647                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13648                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13649
13650                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13651                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13652
13653                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13654                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13655
13656                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13657                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13658         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13659                 bool has_edp, has_port;
13660
13661                 /*
13662                  * The DP_DETECTED bit is the latched state of the DDC
13663                  * SDA pin at boot. However since eDP doesn't require DDC
13664                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13665                  * eDP ports may have been muxed to an alternate function.
13666                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13667                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13668                  * detect eDP ports.
13669                  *
13670                  * Sadly the straps seem to be missing sometimes even for HDMI
13671                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13672                  * and VBT for the presence of the port. Additionally we can't
13673                  * trust the port type the VBT declares as we've seen at least
13674                  * HDMI ports that the VBT claim are DP or eDP.
13675                  */
13676                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13677                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13678                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13679                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13680                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13681                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13682
13683                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13684                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13685                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13686                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13687                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13688                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13689
13690                 if (IS_CHERRYVIEW(dev_priv)) {
13691                         /*
13692                          * eDP not supported on port D,
13693                          * so no need to worry about it
13694                          */
13695                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13696                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13697                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13698                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13699                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13700                 }
13701
13702                 intel_dsi_init(dev_priv);
13703         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13704                 bool found = false;
13705
13706                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13707                         DRM_DEBUG_KMS("probing SDVOB\n");
13708                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13709                         if (!found && IS_G4X(dev_priv)) {
13710                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13711                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13712                         }
13713
13714                         if (!found && IS_G4X(dev_priv))
13715                                 intel_dp_init(dev_priv, DP_B, PORT_B);
13716                 }
13717
13718                 /* Before G4X SDVOC doesn't have its own detect register */
13719
13720                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13721                         DRM_DEBUG_KMS("probing SDVOC\n");
13722                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13723                 }
13724
13725                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13726
13727                         if (IS_G4X(dev_priv)) {
13728                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13729                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13730                         }
13731                         if (IS_G4X(dev_priv))
13732                                 intel_dp_init(dev_priv, DP_C, PORT_C);
13733                 }
13734
13735                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13736                         intel_dp_init(dev_priv, DP_D, PORT_D);
13737         } else if (IS_GEN2(dev_priv))
13738                 intel_dvo_init(dev_priv);
13739
13740         if (SUPPORTS_TV(dev_priv))
13741                 intel_tv_init(dev_priv);
13742
13743         intel_psr_init(dev_priv);
13744
13745         for_each_intel_encoder(&dev_priv->drm, encoder) {
13746                 encoder->base.possible_crtcs = encoder->crtc_mask;
13747                 encoder->base.possible_clones =
13748                         intel_encoder_clones(encoder);
13749         }
13750
13751         intel_init_pch_refclk(dev_priv);
13752
13753         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13754 }
13755
13756 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13757 {
13758         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13759
13760         drm_framebuffer_cleanup(fb);
13761
13762         i915_gem_object_lock(intel_fb->obj);
13763         WARN_ON(!intel_fb->obj->framebuffer_references--);
13764         i915_gem_object_unlock(intel_fb->obj);
13765
13766         i915_gem_object_put(intel_fb->obj);
13767
13768         kfree(intel_fb);
13769 }
13770
13771 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13772                                                 struct drm_file *file,
13773                                                 unsigned int *handle)
13774 {
13775         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13776         struct drm_i915_gem_object *obj = intel_fb->obj;
13777
13778         if (obj->userptr.mm) {
13779                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13780                 return -EINVAL;
13781         }
13782
13783         return drm_gem_handle_create(file, &obj->base, handle);
13784 }
13785
13786 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13787                                         struct drm_file *file,
13788                                         unsigned flags, unsigned color,
13789                                         struct drm_clip_rect *clips,
13790                                         unsigned num_clips)
13791 {
13792         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13793
13794         i915_gem_object_flush_if_display(obj);
13795         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13796
13797         return 0;
13798 }
13799
13800 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13801         .destroy = intel_user_framebuffer_destroy,
13802         .create_handle = intel_user_framebuffer_create_handle,
13803         .dirty = intel_user_framebuffer_dirty,
13804 };
13805
13806 static
13807 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13808                          uint64_t fb_modifier, uint32_t pixel_format)
13809 {
13810         u32 gen = INTEL_GEN(dev_priv);
13811
13812         if (gen >= 9) {
13813                 int cpp = drm_format_plane_cpp(pixel_format, 0);
13814
13815                 /* "The stride in bytes must not exceed the of the size of 8K
13816                  *  pixels and 32K bytes."
13817                  */
13818                 return min(8192 * cpp, 32768);
13819         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13820                 return 32*1024;
13821         } else if (gen >= 4) {
13822                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13823                         return 16*1024;
13824                 else
13825                         return 32*1024;
13826         } else if (gen >= 3) {
13827                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13828                         return 8*1024;
13829                 else
13830                         return 16*1024;
13831         } else {
13832                 /* XXX DSPC is limited to 4k tiled */
13833                 return 8*1024;
13834         }
13835 }
13836
13837 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13838                                   struct drm_i915_gem_object *obj,
13839                                   struct drm_mode_fb_cmd2 *mode_cmd)
13840 {
13841         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13842         struct drm_framebuffer *fb = &intel_fb->base;
13843         struct drm_format_name_buf format_name;
13844         u32 pitch_limit;
13845         unsigned int tiling, stride;
13846         int ret = -EINVAL;
13847         int i;
13848
13849         i915_gem_object_lock(obj);
13850         obj->framebuffer_references++;
13851         tiling = i915_gem_object_get_tiling(obj);
13852         stride = i915_gem_object_get_stride(obj);
13853         i915_gem_object_unlock(obj);
13854
13855         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13856                 /*
13857                  * If there's a fence, enforce that
13858                  * the fb modifier and tiling mode match.
13859                  */
13860                 if (tiling != I915_TILING_NONE &&
13861                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13862                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13863                         goto err;
13864                 }
13865         } else {
13866                 if (tiling == I915_TILING_X) {
13867                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13868                 } else if (tiling == I915_TILING_Y) {
13869                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13870                         goto err;
13871                 }
13872         }
13873
13874         /* Passed in modifier sanity checking. */
13875         switch (mode_cmd->modifier[0]) {
13876         case I915_FORMAT_MOD_Y_TILED_CCS:
13877         case I915_FORMAT_MOD_Yf_TILED_CCS:
13878                 switch (mode_cmd->pixel_format) {
13879                 case DRM_FORMAT_XBGR8888:
13880                 case DRM_FORMAT_ABGR8888:
13881                 case DRM_FORMAT_XRGB8888:
13882                 case DRM_FORMAT_ARGB8888:
13883                         break;
13884                 default:
13885                         DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13886                         goto err;
13887                 }
13888                 /* fall through */
13889         case I915_FORMAT_MOD_Y_TILED:
13890         case I915_FORMAT_MOD_Yf_TILED:
13891                 if (INTEL_GEN(dev_priv) < 9) {
13892                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13893                                       mode_cmd->modifier[0]);
13894                         goto err;
13895                 }
13896         case DRM_FORMAT_MOD_LINEAR:
13897         case I915_FORMAT_MOD_X_TILED:
13898                 break;
13899         default:
13900                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13901                               mode_cmd->modifier[0]);
13902                 goto err;
13903         }
13904
13905         /*
13906          * gen2/3 display engine uses the fence if present,
13907          * so the tiling mode must match the fb modifier exactly.
13908          */
13909         if (INTEL_INFO(dev_priv)->gen < 4 &&
13910             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13911                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13912                 goto err;
13913         }
13914
13915         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13916                                            mode_cmd->pixel_format);
13917         if (mode_cmd->pitches[0] > pitch_limit) {
13918                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13919                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13920                               "tiled" : "linear",
13921                               mode_cmd->pitches[0], pitch_limit);
13922                 goto err;
13923         }
13924
13925         /*
13926          * If there's a fence, enforce that
13927          * the fb pitch and fence stride match.
13928          */
13929         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13930                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13931                               mode_cmd->pitches[0], stride);
13932                 goto err;
13933         }
13934
13935         /* Reject formats not supported by any plane early. */
13936         switch (mode_cmd->pixel_format) {
13937         case DRM_FORMAT_C8:
13938         case DRM_FORMAT_RGB565:
13939         case DRM_FORMAT_XRGB8888:
13940         case DRM_FORMAT_ARGB8888:
13941                 break;
13942         case DRM_FORMAT_XRGB1555:
13943                 if (INTEL_GEN(dev_priv) > 3) {
13944                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13945                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13946                         goto err;
13947                 }
13948                 break;
13949         case DRM_FORMAT_ABGR8888:
13950                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13951                     INTEL_GEN(dev_priv) < 9) {
13952                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13953                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13954                         goto err;
13955                 }
13956                 break;
13957         case DRM_FORMAT_XBGR8888:
13958         case DRM_FORMAT_XRGB2101010:
13959         case DRM_FORMAT_XBGR2101010:
13960                 if (INTEL_GEN(dev_priv) < 4) {
13961                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13962                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13963                         goto err;
13964                 }
13965                 break;
13966         case DRM_FORMAT_ABGR2101010:
13967                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13968                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13969                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13970                         goto err;
13971                 }
13972                 break;
13973         case DRM_FORMAT_YUYV:
13974         case DRM_FORMAT_UYVY:
13975         case DRM_FORMAT_YVYU:
13976         case DRM_FORMAT_VYUY:
13977                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13978                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13979                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13980                         goto err;
13981                 }
13982                 break;
13983         default:
13984                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13985                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
13986                 goto err;
13987         }
13988
13989         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13990         if (mode_cmd->offsets[0] != 0)
13991                 goto err;
13992
13993         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
13994
13995         for (i = 0; i < fb->format->num_planes; i++) {
13996                 u32 stride_alignment;
13997
13998                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
13999                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
14000                         goto err;
14001                 }
14002
14003                 stride_alignment = intel_fb_stride_alignment(fb, i);
14004
14005                 /*
14006                  * Display WA #0531: skl,bxt,kbl,glk
14007                  *
14008                  * Render decompression and plane width > 3840
14009                  * combined with horizontal panning requires the
14010                  * plane stride to be a multiple of 4. We'll just
14011                  * require the entire fb to accommodate that to avoid
14012                  * potential runtime errors at plane configuration time.
14013                  */
14014                 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14015                     (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14016                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14017                         stride_alignment *= 4;
14018
14019                 if (fb->pitches[i] & (stride_alignment - 1)) {
14020                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14021                                       i, fb->pitches[i], stride_alignment);
14022                         goto err;
14023                 }
14024         }
14025
14026         intel_fb->obj = obj;
14027
14028         ret = intel_fill_fb_info(dev_priv, fb);
14029         if (ret)
14030                 goto err;
14031
14032         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14033         if (ret) {
14034                 DRM_ERROR("framebuffer init failed %d\n", ret);
14035                 goto err;
14036         }
14037
14038         return 0;
14039
14040 err:
14041         i915_gem_object_lock(obj);
14042         obj->framebuffer_references--;
14043         i915_gem_object_unlock(obj);
14044         return ret;
14045 }
14046
14047 static struct drm_framebuffer *
14048 intel_user_framebuffer_create(struct drm_device *dev,
14049                               struct drm_file *filp,
14050                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14051 {
14052         struct drm_framebuffer *fb;
14053         struct drm_i915_gem_object *obj;
14054         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14055
14056         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14057         if (!obj)
14058                 return ERR_PTR(-ENOENT);
14059
14060         fb = intel_framebuffer_create(obj, &mode_cmd);
14061         if (IS_ERR(fb))
14062                 i915_gem_object_put(obj);
14063
14064         return fb;
14065 }
14066
14067 static void intel_atomic_state_free(struct drm_atomic_state *state)
14068 {
14069         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14070
14071         drm_atomic_state_default_release(state);
14072
14073         i915_sw_fence_fini(&intel_state->commit_ready);
14074
14075         kfree(state);
14076 }
14077
14078 static const struct drm_mode_config_funcs intel_mode_funcs = {
14079         .fb_create = intel_user_framebuffer_create,
14080         .get_format_info = intel_get_format_info,
14081         .output_poll_changed = intel_fbdev_output_poll_changed,
14082         .atomic_check = intel_atomic_check,
14083         .atomic_commit = intel_atomic_commit,
14084         .atomic_state_alloc = intel_atomic_state_alloc,
14085         .atomic_state_clear = intel_atomic_state_clear,
14086         .atomic_state_free = intel_atomic_state_free,
14087 };
14088
14089 /**
14090  * intel_init_display_hooks - initialize the display modesetting hooks
14091  * @dev_priv: device private
14092  */
14093 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14094 {
14095         intel_init_cdclk_hooks(dev_priv);
14096
14097         if (INTEL_INFO(dev_priv)->gen >= 9) {
14098                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14099                 dev_priv->display.get_initial_plane_config =
14100                         skylake_get_initial_plane_config;
14101                 dev_priv->display.crtc_compute_clock =
14102                         haswell_crtc_compute_clock;
14103                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14104                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14105         } else if (HAS_DDI(dev_priv)) {
14106                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14107                 dev_priv->display.get_initial_plane_config =
14108                         ironlake_get_initial_plane_config;
14109                 dev_priv->display.crtc_compute_clock =
14110                         haswell_crtc_compute_clock;
14111                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14112                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14113         } else if (HAS_PCH_SPLIT(dev_priv)) {
14114                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14115                 dev_priv->display.get_initial_plane_config =
14116                         ironlake_get_initial_plane_config;
14117                 dev_priv->display.crtc_compute_clock =
14118                         ironlake_crtc_compute_clock;
14119                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14120                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14121         } else if (IS_CHERRYVIEW(dev_priv)) {
14122                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14123                 dev_priv->display.get_initial_plane_config =
14124                         i9xx_get_initial_plane_config;
14125                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14126                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14127                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14128         } else if (IS_VALLEYVIEW(dev_priv)) {
14129                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14130                 dev_priv->display.get_initial_plane_config =
14131                         i9xx_get_initial_plane_config;
14132                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14133                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14134                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14135         } else if (IS_G4X(dev_priv)) {
14136                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14137                 dev_priv->display.get_initial_plane_config =
14138                         i9xx_get_initial_plane_config;
14139                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14140                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14141                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14142         } else if (IS_PINEVIEW(dev_priv)) {
14143                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14144                 dev_priv->display.get_initial_plane_config =
14145                         i9xx_get_initial_plane_config;
14146                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14147                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14148                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14149         } else if (!IS_GEN2(dev_priv)) {
14150                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14151                 dev_priv->display.get_initial_plane_config =
14152                         i9xx_get_initial_plane_config;
14153                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14154                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14155                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14156         } else {
14157                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14158                 dev_priv->display.get_initial_plane_config =
14159                         i9xx_get_initial_plane_config;
14160                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14161                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14162                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14163         }
14164
14165         if (IS_GEN5(dev_priv)) {
14166                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14167         } else if (IS_GEN6(dev_priv)) {
14168                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14169         } else if (IS_IVYBRIDGE(dev_priv)) {
14170                 /* FIXME: detect B0+ stepping and use auto training */
14171                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14172         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14173                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14174         }
14175
14176         if (INTEL_GEN(dev_priv) >= 9)
14177                 dev_priv->display.update_crtcs = skl_update_crtcs;
14178         else
14179                 dev_priv->display.update_crtcs = intel_update_crtcs;
14180 }
14181
14182 /*
14183  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14184  */
14185 static void quirk_ssc_force_disable(struct drm_device *dev)
14186 {
14187         struct drm_i915_private *dev_priv = to_i915(dev);
14188         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14189         DRM_INFO("applying lvds SSC disable quirk\n");
14190 }
14191
14192 /*
14193  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14194  * brightness value
14195  */
14196 static void quirk_invert_brightness(struct drm_device *dev)
14197 {
14198         struct drm_i915_private *dev_priv = to_i915(dev);
14199         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14200         DRM_INFO("applying inverted panel brightness quirk\n");
14201 }
14202
14203 /* Some VBT's incorrectly indicate no backlight is present */
14204 static void quirk_backlight_present(struct drm_device *dev)
14205 {
14206         struct drm_i915_private *dev_priv = to_i915(dev);
14207         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14208         DRM_INFO("applying backlight present quirk\n");
14209 }
14210
14211 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14212  * which is 300 ms greater than eDP spec T12 min.
14213  */
14214 static void quirk_increase_t12_delay(struct drm_device *dev)
14215 {
14216         struct drm_i915_private *dev_priv = to_i915(dev);
14217
14218         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14219         DRM_INFO("Applying T12 delay quirk\n");
14220 }
14221
14222 struct intel_quirk {
14223         int device;
14224         int subsystem_vendor;
14225         int subsystem_device;
14226         void (*hook)(struct drm_device *dev);
14227 };
14228
14229 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14230 struct intel_dmi_quirk {
14231         void (*hook)(struct drm_device *dev);
14232         const struct dmi_system_id (*dmi_id_list)[];
14233 };
14234
14235 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14236 {
14237         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14238         return 1;
14239 }
14240
14241 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14242         {
14243                 .dmi_id_list = &(const struct dmi_system_id[]) {
14244                         {
14245                                 .callback = intel_dmi_reverse_brightness,
14246                                 .ident = "NCR Corporation",
14247                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14248                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14249                                 },
14250                         },
14251                         { }  /* terminating entry */
14252                 },
14253                 .hook = quirk_invert_brightness,
14254         },
14255 };
14256
14257 static struct intel_quirk intel_quirks[] = {
14258         /* Lenovo U160 cannot use SSC on LVDS */
14259         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14260
14261         /* Sony Vaio Y cannot use SSC on LVDS */
14262         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14263
14264         /* Acer Aspire 5734Z must invert backlight brightness */
14265         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14266
14267         /* Acer/eMachines G725 */
14268         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14269
14270         /* Acer/eMachines e725 */
14271         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14272
14273         /* Acer/Packard Bell NCL20 */
14274         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14275
14276         /* Acer Aspire 4736Z */
14277         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14278
14279         /* Acer Aspire 5336 */
14280         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14281
14282         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14283         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14284
14285         /* Acer C720 Chromebook (Core i3 4005U) */
14286         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14287
14288         /* Apple Macbook 2,1 (Core 2 T7400) */
14289         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14290
14291         /* Apple Macbook 4,1 */
14292         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14293
14294         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14295         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14296
14297         /* HP Chromebook 14 (Celeron 2955U) */
14298         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14299
14300         /* Dell Chromebook 11 */
14301         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14302
14303         /* Dell Chromebook 11 (2015 version) */
14304         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14305
14306         /* Toshiba Satellite P50-C-18C */
14307         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14308 };
14309
14310 static void intel_init_quirks(struct drm_device *dev)
14311 {
14312         struct pci_dev *d = dev->pdev;
14313         int i;
14314
14315         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14316                 struct intel_quirk *q = &intel_quirks[i];
14317
14318                 if (d->device == q->device &&
14319                     (d->subsystem_vendor == q->subsystem_vendor ||
14320                      q->subsystem_vendor == PCI_ANY_ID) &&
14321                     (d->subsystem_device == q->subsystem_device ||
14322                      q->subsystem_device == PCI_ANY_ID))
14323                         q->hook(dev);
14324         }
14325         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14326                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14327                         intel_dmi_quirks[i].hook(dev);
14328         }
14329 }
14330
14331 /* Disable the VGA plane that we never use */
14332 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14333 {
14334         struct pci_dev *pdev = dev_priv->drm.pdev;
14335         u8 sr1;
14336         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14337
14338         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14339         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14340         outb(SR01, VGA_SR_INDEX);
14341         sr1 = inb(VGA_SR_DATA);
14342         outb(sr1 | 1<<5, VGA_SR_DATA);
14343         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14344         udelay(300);
14345
14346         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14347         POSTING_READ(vga_reg);
14348 }
14349
14350 void intel_modeset_init_hw(struct drm_device *dev)
14351 {
14352         struct drm_i915_private *dev_priv = to_i915(dev);
14353
14354         intel_update_cdclk(dev_priv);
14355         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14356 }
14357
14358 /*
14359  * Calculate what we think the watermarks should be for the state we've read
14360  * out of the hardware and then immediately program those watermarks so that
14361  * we ensure the hardware settings match our internal state.
14362  *
14363  * We can calculate what we think WM's should be by creating a duplicate of the
14364  * current state (which was constructed during hardware readout) and running it
14365  * through the atomic check code to calculate new watermark values in the
14366  * state object.
14367  */
14368 static void sanitize_watermarks(struct drm_device *dev)
14369 {
14370         struct drm_i915_private *dev_priv = to_i915(dev);
14371         struct drm_atomic_state *state;
14372         struct intel_atomic_state *intel_state;
14373         struct drm_crtc *crtc;
14374         struct drm_crtc_state *cstate;
14375         struct drm_modeset_acquire_ctx ctx;
14376         int ret;
14377         int i;
14378
14379         /* Only supported on platforms that use atomic watermark design */
14380         if (!dev_priv->display.optimize_watermarks)
14381                 return;
14382
14383         /*
14384          * We need to hold connection_mutex before calling duplicate_state so
14385          * that the connector loop is protected.
14386          */
14387         drm_modeset_acquire_init(&ctx, 0);
14388 retry:
14389         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14390         if (ret == -EDEADLK) {
14391                 drm_modeset_backoff(&ctx);
14392                 goto retry;
14393         } else if (WARN_ON(ret)) {
14394                 goto fail;
14395         }
14396
14397         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14398         if (WARN_ON(IS_ERR(state)))
14399                 goto fail;
14400
14401         intel_state = to_intel_atomic_state(state);
14402
14403         /*
14404          * Hardware readout is the only time we don't want to calculate
14405          * intermediate watermarks (since we don't trust the current
14406          * watermarks).
14407          */
14408         if (!HAS_GMCH_DISPLAY(dev_priv))
14409                 intel_state->skip_intermediate_wm = true;
14410
14411         ret = intel_atomic_check(dev, state);
14412         if (ret) {
14413                 /*
14414                  * If we fail here, it means that the hardware appears to be
14415                  * programmed in a way that shouldn't be possible, given our
14416                  * understanding of watermark requirements.  This might mean a
14417                  * mistake in the hardware readout code or a mistake in the
14418                  * watermark calculations for a given platform.  Raise a WARN
14419                  * so that this is noticeable.
14420                  *
14421                  * If this actually happens, we'll have to just leave the
14422                  * BIOS-programmed watermarks untouched and hope for the best.
14423                  */
14424                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14425                 goto put_state;
14426         }
14427
14428         /* Write calculated watermark values back */
14429         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14430                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14431
14432                 cs->wm.need_postvbl_update = true;
14433                 dev_priv->display.optimize_watermarks(intel_state, cs);
14434         }
14435
14436 put_state:
14437         drm_atomic_state_put(state);
14438 fail:
14439         drm_modeset_drop_locks(&ctx);
14440         drm_modeset_acquire_fini(&ctx);
14441 }
14442
14443 int intel_modeset_init(struct drm_device *dev)
14444 {
14445         struct drm_i915_private *dev_priv = to_i915(dev);
14446         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14447         enum pipe pipe;
14448         struct intel_crtc *crtc;
14449
14450         drm_mode_config_init(dev);
14451
14452         dev->mode_config.min_width = 0;
14453         dev->mode_config.min_height = 0;
14454
14455         dev->mode_config.preferred_depth = 24;
14456         dev->mode_config.prefer_shadow = 1;
14457
14458         dev->mode_config.allow_fb_modifiers = true;
14459
14460         dev->mode_config.funcs = &intel_mode_funcs;
14461
14462         init_llist_head(&dev_priv->atomic_helper.free_list);
14463         INIT_WORK(&dev_priv->atomic_helper.free_work,
14464                   intel_atomic_helper_free_state_worker);
14465
14466         intel_init_quirks(dev);
14467
14468         intel_init_pm(dev_priv);
14469
14470         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14471                 return 0;
14472
14473         /*
14474          * There may be no VBT; and if the BIOS enabled SSC we can
14475          * just keep using it to avoid unnecessary flicker.  Whereas if the
14476          * BIOS isn't using it, don't assume it will work even if the VBT
14477          * indicates as much.
14478          */
14479         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14480                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14481                                             DREF_SSC1_ENABLE);
14482
14483                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14484                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14485                                      bios_lvds_use_ssc ? "en" : "dis",
14486                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14487                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14488                 }
14489         }
14490
14491         if (IS_GEN2(dev_priv)) {
14492                 dev->mode_config.max_width = 2048;
14493                 dev->mode_config.max_height = 2048;
14494         } else if (IS_GEN3(dev_priv)) {
14495                 dev->mode_config.max_width = 4096;
14496                 dev->mode_config.max_height = 4096;
14497         } else {
14498                 dev->mode_config.max_width = 8192;
14499                 dev->mode_config.max_height = 8192;
14500         }
14501
14502         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14503                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14504                 dev->mode_config.cursor_height = 1023;
14505         } else if (IS_GEN2(dev_priv)) {
14506                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14507                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14508         } else {
14509                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14510                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14511         }
14512
14513         dev->mode_config.fb_base = ggtt->mappable_base;
14514
14515         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14516                       INTEL_INFO(dev_priv)->num_pipes,
14517                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14518
14519         for_each_pipe(dev_priv, pipe) {
14520                 int ret;
14521
14522                 ret = intel_crtc_init(dev_priv, pipe);
14523                 if (ret) {
14524                         drm_mode_config_cleanup(dev);
14525                         return ret;
14526                 }
14527         }
14528
14529         intel_shared_dpll_init(dev);
14530
14531         intel_update_czclk(dev_priv);
14532         intel_modeset_init_hw(dev);
14533
14534         if (dev_priv->max_cdclk_freq == 0)
14535                 intel_update_max_cdclk(dev_priv);
14536
14537         /* Just disable it once at startup */
14538         i915_disable_vga(dev_priv);
14539         intel_setup_outputs(dev_priv);
14540
14541         drm_modeset_lock_all(dev);
14542         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14543         drm_modeset_unlock_all(dev);
14544
14545         for_each_intel_crtc(dev, crtc) {
14546                 struct intel_initial_plane_config plane_config = {};
14547
14548                 if (!crtc->active)
14549                         continue;
14550
14551                 /*
14552                  * Note that reserving the BIOS fb up front prevents us
14553                  * from stuffing other stolen allocations like the ring
14554                  * on top.  This prevents some ugliness at boot time, and
14555                  * can even allow for smooth boot transitions if the BIOS
14556                  * fb is large enough for the active pipe configuration.
14557                  */
14558                 dev_priv->display.get_initial_plane_config(crtc,
14559                                                            &plane_config);
14560
14561                 /*
14562                  * If the fb is shared between multiple heads, we'll
14563                  * just get the first one.
14564                  */
14565                 intel_find_initial_plane_obj(crtc, &plane_config);
14566         }
14567
14568         /*
14569          * Make sure hardware watermarks really match the state we read out.
14570          * Note that we need to do this after reconstructing the BIOS fb's
14571          * since the watermark calculation done here will use pstate->fb.
14572          */
14573         if (!HAS_GMCH_DISPLAY(dev_priv))
14574                 sanitize_watermarks(dev);
14575
14576         return 0;
14577 }
14578
14579 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14580 {
14581         /* 640x480@60Hz, ~25175 kHz */
14582         struct dpll clock = {
14583                 .m1 = 18,
14584                 .m2 = 7,
14585                 .p1 = 13,
14586                 .p2 = 4,
14587                 .n = 2,
14588         };
14589         u32 dpll, fp;
14590         int i;
14591
14592         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14593
14594         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14595                       pipe_name(pipe), clock.vco, clock.dot);
14596
14597         fp = i9xx_dpll_compute_fp(&clock);
14598         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14599                 DPLL_VGA_MODE_DIS |
14600                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14601                 PLL_P2_DIVIDE_BY_4 |
14602                 PLL_REF_INPUT_DREFCLK |
14603                 DPLL_VCO_ENABLE;
14604
14605         I915_WRITE(FP0(pipe), fp);
14606         I915_WRITE(FP1(pipe), fp);
14607
14608         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14609         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14610         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14611         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14612         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14613         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14614         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14615
14616         /*
14617          * Apparently we need to have VGA mode enabled prior to changing
14618          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14619          * dividers, even though the register value does change.
14620          */
14621         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14622         I915_WRITE(DPLL(pipe), dpll);
14623
14624         /* Wait for the clocks to stabilize. */
14625         POSTING_READ(DPLL(pipe));
14626         udelay(150);
14627
14628         /* The pixel multiplier can only be updated once the
14629          * DPLL is enabled and the clocks are stable.
14630          *
14631          * So write it again.
14632          */
14633         I915_WRITE(DPLL(pipe), dpll);
14634
14635         /* We do this three times for luck */
14636         for (i = 0; i < 3 ; i++) {
14637                 I915_WRITE(DPLL(pipe), dpll);
14638                 POSTING_READ(DPLL(pipe));
14639                 udelay(150); /* wait for warmup */
14640         }
14641
14642         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14643         POSTING_READ(PIPECONF(pipe));
14644 }
14645
14646 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14647 {
14648         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14649                       pipe_name(pipe));
14650
14651         assert_plane_disabled(dev_priv, PLANE_A);
14652         assert_plane_disabled(dev_priv, PLANE_B);
14653
14654         I915_WRITE(PIPECONF(pipe), 0);
14655         POSTING_READ(PIPECONF(pipe));
14656
14657         if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14658                 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14659
14660         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14661         POSTING_READ(DPLL(pipe));
14662 }
14663
14664 static bool
14665 intel_check_plane_mapping(struct intel_crtc *crtc)
14666 {
14667         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14668         u32 val;
14669
14670         if (INTEL_INFO(dev_priv)->num_pipes == 1)
14671                 return true;
14672
14673         val = I915_READ(DSPCNTR(!crtc->plane));
14674
14675         if ((val & DISPLAY_PLANE_ENABLE) &&
14676             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14677                 return false;
14678
14679         return true;
14680 }
14681
14682 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14683 {
14684         struct drm_device *dev = crtc->base.dev;
14685         struct intel_encoder *encoder;
14686
14687         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14688                 return true;
14689
14690         return false;
14691 }
14692
14693 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14694 {
14695         struct drm_device *dev = encoder->base.dev;
14696         struct intel_connector *connector;
14697
14698         for_each_connector_on_encoder(dev, &encoder->base, connector)
14699                 return connector;
14700
14701         return NULL;
14702 }
14703
14704 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14705                               enum pipe pch_transcoder)
14706 {
14707         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14708                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14709 }
14710
14711 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14712                                 struct drm_modeset_acquire_ctx *ctx)
14713 {
14714         struct drm_device *dev = crtc->base.dev;
14715         struct drm_i915_private *dev_priv = to_i915(dev);
14716         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14717
14718         /* Clear any frame start delays used for debugging left by the BIOS */
14719         if (!transcoder_is_dsi(cpu_transcoder)) {
14720                 i915_reg_t reg = PIPECONF(cpu_transcoder);
14721
14722                 I915_WRITE(reg,
14723                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14724         }
14725
14726         /* restore vblank interrupts to correct state */
14727         drm_crtc_vblank_reset(&crtc->base);
14728         if (crtc->active) {
14729                 struct intel_plane *plane;
14730
14731                 drm_crtc_vblank_on(&crtc->base);
14732
14733                 /* Disable everything but the primary plane */
14734                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14735                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14736                                 continue;
14737
14738                         trace_intel_disable_plane(&plane->base, crtc);
14739                         plane->disable_plane(plane, crtc);
14740                 }
14741         }
14742
14743         /* We need to sanitize the plane -> pipe mapping first because this will
14744          * disable the crtc (and hence change the state) if it is wrong. Note
14745          * that gen4+ has a fixed plane -> pipe mapping.  */
14746         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14747                 bool plane;
14748
14749                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14750                               crtc->base.base.id, crtc->base.name);
14751
14752                 /* Pipe has the wrong plane attached and the plane is active.
14753                  * Temporarily change the plane mapping and disable everything
14754                  * ...  */
14755                 plane = crtc->plane;
14756                 crtc->base.primary->state->visible = true;
14757                 crtc->plane = !plane;
14758                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14759                 crtc->plane = plane;
14760         }
14761
14762         /* Adjust the state of the output pipe according to whether we
14763          * have active connectors/encoders. */
14764         if (crtc->active && !intel_crtc_has_encoders(crtc))
14765                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14766
14767         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14768                 /*
14769                  * We start out with underrun reporting disabled to avoid races.
14770                  * For correct bookkeeping mark this on active crtcs.
14771                  *
14772                  * Also on gmch platforms we dont have any hardware bits to
14773                  * disable the underrun reporting. Which means we need to start
14774                  * out with underrun reporting disabled also on inactive pipes,
14775                  * since otherwise we'll complain about the garbage we read when
14776                  * e.g. coming up after runtime pm.
14777                  *
14778                  * No protection against concurrent access is required - at
14779                  * worst a fifo underrun happens which also sets this to false.
14780                  */
14781                 crtc->cpu_fifo_underrun_disabled = true;
14782                 /*
14783                  * We track the PCH trancoder underrun reporting state
14784                  * within the crtc. With crtc for pipe A housing the underrun
14785                  * reporting state for PCH transcoder A, crtc for pipe B housing
14786                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14787                  * and marking underrun reporting as disabled for the non-existing
14788                  * PCH transcoders B and C would prevent enabling the south
14789                  * error interrupt (see cpt_can_enable_serr_int()).
14790                  */
14791                 if (has_pch_trancoder(dev_priv, crtc->pipe))
14792                         crtc->pch_fifo_underrun_disabled = true;
14793         }
14794 }
14795
14796 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14797 {
14798         struct intel_connector *connector;
14799
14800         /* We need to check both for a crtc link (meaning that the
14801          * encoder is active and trying to read from a pipe) and the
14802          * pipe itself being active. */
14803         bool has_active_crtc = encoder->base.crtc &&
14804                 to_intel_crtc(encoder->base.crtc)->active;
14805
14806         connector = intel_encoder_find_connector(encoder);
14807         if (connector && !has_active_crtc) {
14808                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14809                               encoder->base.base.id,
14810                               encoder->base.name);
14811
14812                 /* Connector is active, but has no active pipe. This is
14813                  * fallout from our resume register restoring. Disable
14814                  * the encoder manually again. */
14815                 if (encoder->base.crtc) {
14816                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14817
14818                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14819                                       encoder->base.base.id,
14820                                       encoder->base.name);
14821                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14822                         if (encoder->post_disable)
14823                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14824                 }
14825                 encoder->base.crtc = NULL;
14826
14827                 /* Inconsistent output/port/pipe state happens presumably due to
14828                  * a bug in one of the get_hw_state functions. Or someplace else
14829                  * in our code, like the register restore mess on resume. Clamp
14830                  * things to off as a safer default. */
14831
14832                 connector->base.dpms = DRM_MODE_DPMS_OFF;
14833                 connector->base.encoder = NULL;
14834         }
14835         /* Enabled encoders without active connectors will be fixed in
14836          * the crtc fixup. */
14837 }
14838
14839 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14840 {
14841         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14842
14843         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14844                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14845                 i915_disable_vga(dev_priv);
14846         }
14847 }
14848
14849 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14850 {
14851         /* This function can be called both from intel_modeset_setup_hw_state or
14852          * at a very early point in our resume sequence, where the power well
14853          * structures are not yet restored. Since this function is at a very
14854          * paranoid "someone might have enabled VGA while we were not looking"
14855          * level, just check if the power well is enabled instead of trying to
14856          * follow the "don't touch the power well if we don't need it" policy
14857          * the rest of the driver uses. */
14858         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14859                 return;
14860
14861         i915_redisable_vga_power_on(dev_priv);
14862
14863         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14864 }
14865
14866 static bool primary_get_hw_state(struct intel_plane *plane)
14867 {
14868         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14869
14870         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14871 }
14872
14873 /* FIXME read out full plane state for all planes */
14874 static void readout_plane_state(struct intel_crtc *crtc)
14875 {
14876         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14877         bool visible;
14878
14879         visible = crtc->active && primary_get_hw_state(primary);
14880
14881         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14882                                 to_intel_plane_state(primary->base.state),
14883                                 visible);
14884 }
14885
14886 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14887 {
14888         struct drm_i915_private *dev_priv = to_i915(dev);
14889         enum pipe pipe;
14890         struct intel_crtc *crtc;
14891         struct intel_encoder *encoder;
14892         struct intel_connector *connector;
14893         struct drm_connector_list_iter conn_iter;
14894         int i;
14895
14896         dev_priv->active_crtcs = 0;
14897
14898         for_each_intel_crtc(dev, crtc) {
14899                 struct intel_crtc_state *crtc_state =
14900                         to_intel_crtc_state(crtc->base.state);
14901
14902                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14903                 memset(crtc_state, 0, sizeof(*crtc_state));
14904                 crtc_state->base.crtc = &crtc->base;
14905
14906                 crtc_state->base.active = crtc_state->base.enable =
14907                         dev_priv->display.get_pipe_config(crtc, crtc_state);
14908
14909                 crtc->base.enabled = crtc_state->base.enable;
14910                 crtc->active = crtc_state->base.active;
14911
14912                 if (crtc_state->base.active)
14913                         dev_priv->active_crtcs |= 1 << crtc->pipe;
14914
14915                 readout_plane_state(crtc);
14916
14917                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14918                               crtc->base.base.id, crtc->base.name,
14919                               enableddisabled(crtc_state->base.active));
14920         }
14921
14922         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14923                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14924
14925                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14926                                                   &pll->state.hw_state);
14927                 pll->state.crtc_mask = 0;
14928                 for_each_intel_crtc(dev, crtc) {
14929                         struct intel_crtc_state *crtc_state =
14930                                 to_intel_crtc_state(crtc->base.state);
14931
14932                         if (crtc_state->base.active &&
14933                             crtc_state->shared_dpll == pll)
14934                                 pll->state.crtc_mask |= 1 << crtc->pipe;
14935                 }
14936                 pll->active_mask = pll->state.crtc_mask;
14937
14938                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14939                               pll->name, pll->state.crtc_mask, pll->on);
14940         }
14941
14942         for_each_intel_encoder(dev, encoder) {
14943                 pipe = 0;
14944
14945                 if (encoder->get_hw_state(encoder, &pipe)) {
14946                         struct intel_crtc_state *crtc_state;
14947
14948                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14949                         crtc_state = to_intel_crtc_state(crtc->base.state);
14950
14951                         encoder->base.crtc = &crtc->base;
14952                         crtc_state->output_types |= 1 << encoder->type;
14953                         encoder->get_config(encoder, crtc_state);
14954                 } else {
14955                         encoder->base.crtc = NULL;
14956                 }
14957
14958                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14959                               encoder->base.base.id, encoder->base.name,
14960                               enableddisabled(encoder->base.crtc),
14961                               pipe_name(pipe));
14962         }
14963
14964         drm_connector_list_iter_begin(dev, &conn_iter);
14965         for_each_intel_connector_iter(connector, &conn_iter) {
14966                 if (connector->get_hw_state(connector)) {
14967                         connector->base.dpms = DRM_MODE_DPMS_ON;
14968
14969                         encoder = connector->encoder;
14970                         connector->base.encoder = &encoder->base;
14971
14972                         if (encoder->base.crtc &&
14973                             encoder->base.crtc->state->active) {
14974                                 /*
14975                                  * This has to be done during hardware readout
14976                                  * because anything calling .crtc_disable may
14977                                  * rely on the connector_mask being accurate.
14978                                  */
14979                                 encoder->base.crtc->state->connector_mask |=
14980                                         1 << drm_connector_index(&connector->base);
14981                                 encoder->base.crtc->state->encoder_mask |=
14982                                         1 << drm_encoder_index(&encoder->base);
14983                         }
14984
14985                 } else {
14986                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14987                         connector->base.encoder = NULL;
14988                 }
14989                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14990                               connector->base.base.id, connector->base.name,
14991                               enableddisabled(connector->base.encoder));
14992         }
14993         drm_connector_list_iter_end(&conn_iter);
14994
14995         for_each_intel_crtc(dev, crtc) {
14996                 struct intel_crtc_state *crtc_state =
14997                         to_intel_crtc_state(crtc->base.state);
14998                 int min_cdclk = 0;
14999
15000                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15001                 if (crtc_state->base.active) {
15002                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15003                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15004                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15005
15006                         /*
15007                          * The initial mode needs to be set in order to keep
15008                          * the atomic core happy. It wants a valid mode if the
15009                          * crtc's enabled, so we do the above call.
15010                          *
15011                          * But we don't set all the derived state fully, hence
15012                          * set a flag to indicate that a full recalculation is
15013                          * needed on the next commit.
15014                          */
15015                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15016
15017                         intel_crtc_compute_pixel_rate(crtc_state);
15018
15019                         if (dev_priv->display.modeset_calc_cdclk) {
15020                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15021                                 if (WARN_ON(min_cdclk < 0))
15022                                         min_cdclk = 0;
15023                         }
15024
15025                         drm_calc_timestamping_constants(&crtc->base,
15026                                                         &crtc_state->base.adjusted_mode);
15027                         update_scanline_offset(crtc);
15028                 }
15029
15030                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15031
15032                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15033         }
15034 }
15035
15036 static void
15037 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15038 {
15039         struct intel_encoder *encoder;
15040
15041         for_each_intel_encoder(&dev_priv->drm, encoder) {
15042                 u64 get_domains;
15043                 enum intel_display_power_domain domain;
15044
15045                 if (!encoder->get_power_domains)
15046                         continue;
15047
15048                 get_domains = encoder->get_power_domains(encoder);
15049                 for_each_power_domain(domain, get_domains)
15050                         intel_display_power_get(dev_priv, domain);
15051         }
15052 }
15053
15054 /* Scan out the current hw modeset state,
15055  * and sanitizes it to the current state
15056  */
15057 static void
15058 intel_modeset_setup_hw_state(struct drm_device *dev,
15059                              struct drm_modeset_acquire_ctx *ctx)
15060 {
15061         struct drm_i915_private *dev_priv = to_i915(dev);
15062         enum pipe pipe;
15063         struct intel_crtc *crtc;
15064         struct intel_encoder *encoder;
15065         int i;
15066
15067         if (IS_HASWELL(dev_priv)) {
15068                 /*
15069                  * WaRsPkgCStateDisplayPMReq:hsw
15070                  * System hang if this isn't done before disabling all planes!
15071                  */
15072                 I915_WRITE(CHICKEN_PAR1_1,
15073                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15074         }
15075
15076         intel_modeset_readout_hw_state(dev);
15077
15078         /* HW state is read out, now we need to sanitize this mess. */
15079         get_encoder_power_domains(dev_priv);
15080
15081         for_each_intel_encoder(dev, encoder) {
15082                 intel_sanitize_encoder(encoder);
15083         }
15084
15085         for_each_pipe(dev_priv, pipe) {
15086                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15087
15088                 intel_sanitize_crtc(crtc, ctx);
15089                 intel_dump_pipe_config(crtc, crtc->config,
15090                                        "[setup_hw_state]");
15091         }
15092
15093         intel_modeset_update_connector_atomic_state(dev);
15094
15095         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15096                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15097
15098                 if (!pll->on || pll->active_mask)
15099                         continue;
15100
15101                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15102
15103                 pll->funcs.disable(dev_priv, pll);
15104                 pll->on = false;
15105         }
15106
15107         if (IS_G4X(dev_priv)) {
15108                 g4x_wm_get_hw_state(dev);
15109                 g4x_wm_sanitize(dev_priv);
15110         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15111                 vlv_wm_get_hw_state(dev);
15112                 vlv_wm_sanitize(dev_priv);
15113         } else if (INTEL_GEN(dev_priv) >= 9) {
15114                 skl_wm_get_hw_state(dev);
15115         } else if (HAS_PCH_SPLIT(dev_priv)) {
15116                 ilk_wm_get_hw_state(dev);
15117         }
15118
15119         for_each_intel_crtc(dev, crtc) {
15120                 u64 put_domains;
15121
15122                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15123                 if (WARN_ON(put_domains))
15124                         modeset_put_power_domains(dev_priv, put_domains);
15125         }
15126         intel_display_set_init_power(dev_priv, false);
15127
15128         intel_power_domains_verify_state(dev_priv);
15129
15130         intel_fbc_init_pipe_state(dev_priv);
15131 }
15132
15133 void intel_display_resume(struct drm_device *dev)
15134 {
15135         struct drm_i915_private *dev_priv = to_i915(dev);
15136         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15137         struct drm_modeset_acquire_ctx ctx;
15138         int ret;
15139
15140         dev_priv->modeset_restore_state = NULL;
15141         if (state)
15142                 state->acquire_ctx = &ctx;
15143
15144         drm_modeset_acquire_init(&ctx, 0);
15145
15146         while (1) {
15147                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15148                 if (ret != -EDEADLK)
15149                         break;
15150
15151                 drm_modeset_backoff(&ctx);
15152         }
15153
15154         if (!ret)
15155                 ret = __intel_display_resume(dev, state, &ctx);
15156
15157         intel_enable_ipc(dev_priv);
15158         drm_modeset_drop_locks(&ctx);
15159         drm_modeset_acquire_fini(&ctx);
15160
15161         if (ret)
15162                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15163         if (state)
15164                 drm_atomic_state_put(state);
15165 }
15166
15167 void intel_modeset_gem_init(struct drm_device *dev)
15168 {
15169         struct drm_i915_private *dev_priv = to_i915(dev);
15170
15171         intel_init_gt_powersave(dev_priv);
15172
15173         intel_init_clock_gating(dev_priv);
15174
15175         intel_setup_overlay(dev_priv);
15176 }
15177
15178 int intel_connector_register(struct drm_connector *connector)
15179 {
15180         struct intel_connector *intel_connector = to_intel_connector(connector);
15181         int ret;
15182
15183         ret = intel_backlight_device_register(intel_connector);
15184         if (ret)
15185                 goto err;
15186
15187         return 0;
15188
15189 err:
15190         return ret;
15191 }
15192
15193 void intel_connector_unregister(struct drm_connector *connector)
15194 {
15195         struct intel_connector *intel_connector = to_intel_connector(connector);
15196
15197         intel_backlight_device_unregister(intel_connector);
15198         intel_panel_destroy_backlight(connector);
15199 }
15200
15201 void intel_modeset_cleanup(struct drm_device *dev)
15202 {
15203         struct drm_i915_private *dev_priv = to_i915(dev);
15204
15205         flush_work(&dev_priv->atomic_helper.free_work);
15206         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15207
15208         intel_disable_gt_powersave(dev_priv);
15209
15210         /*
15211          * Interrupts and polling as the first thing to avoid creating havoc.
15212          * Too much stuff here (turning of connectors, ...) would
15213          * experience fancy races otherwise.
15214          */
15215         intel_irq_uninstall(dev_priv);
15216
15217         /*
15218          * Due to the hpd irq storm handling the hotplug work can re-arm the
15219          * poll handlers. Hence disable polling after hpd handling is shut down.
15220          */
15221         drm_kms_helper_poll_fini(dev);
15222
15223         /* poll work can call into fbdev, hence clean that up afterwards */
15224         intel_fbdev_fini(dev_priv);
15225
15226         intel_unregister_dsm_handler();
15227
15228         intel_fbc_global_disable(dev_priv);
15229
15230         /* flush any delayed tasks or pending work */
15231         flush_scheduled_work();
15232
15233         drm_mode_config_cleanup(dev);
15234
15235         intel_cleanup_overlay(dev_priv);
15236
15237         intel_cleanup_gt_powersave(dev_priv);
15238
15239         intel_teardown_gmbus(dev_priv);
15240 }
15241
15242 void intel_connector_attach_encoder(struct intel_connector *connector,
15243                                     struct intel_encoder *encoder)
15244 {
15245         connector->encoder = encoder;
15246         drm_mode_connector_attach_encoder(&connector->base,
15247                                           &encoder->base);
15248 }
15249
15250 /*
15251  * set vga decode state - true == enable VGA decode
15252  */
15253 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15254 {
15255         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15256         u16 gmch_ctrl;
15257
15258         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15259                 DRM_ERROR("failed to read control word\n");
15260                 return -EIO;
15261         }
15262
15263         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15264                 return 0;
15265
15266         if (state)
15267                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15268         else
15269                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15270
15271         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15272                 DRM_ERROR("failed to write control word\n");
15273                 return -EIO;
15274         }
15275
15276         return 0;
15277 }
15278
15279 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15280
15281 struct intel_display_error_state {
15282
15283         u32 power_well_driver;
15284
15285         int num_transcoders;
15286
15287         struct intel_cursor_error_state {
15288                 u32 control;
15289                 u32 position;
15290                 u32 base;
15291                 u32 size;
15292         } cursor[I915_MAX_PIPES];
15293
15294         struct intel_pipe_error_state {
15295                 bool power_domain_on;
15296                 u32 source;
15297                 u32 stat;
15298         } pipe[I915_MAX_PIPES];
15299
15300         struct intel_plane_error_state {
15301                 u32 control;
15302                 u32 stride;
15303                 u32 size;
15304                 u32 pos;
15305                 u32 addr;
15306                 u32 surface;
15307                 u32 tile_offset;
15308         } plane[I915_MAX_PIPES];
15309
15310         struct intel_transcoder_error_state {
15311                 bool power_domain_on;
15312                 enum transcoder cpu_transcoder;
15313
15314                 u32 conf;
15315
15316                 u32 htotal;
15317                 u32 hblank;
15318                 u32 hsync;
15319                 u32 vtotal;
15320                 u32 vblank;
15321                 u32 vsync;
15322         } transcoder[4];
15323 };
15324
15325 struct intel_display_error_state *
15326 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15327 {
15328         struct intel_display_error_state *error;
15329         int transcoders[] = {
15330                 TRANSCODER_A,
15331                 TRANSCODER_B,
15332                 TRANSCODER_C,
15333                 TRANSCODER_EDP,
15334         };
15335         int i;
15336
15337         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15338                 return NULL;
15339
15340         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15341         if (error == NULL)
15342                 return NULL;
15343
15344         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15345                 error->power_well_driver =
15346                         I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15347
15348         for_each_pipe(dev_priv, i) {
15349                 error->pipe[i].power_domain_on =
15350                         __intel_display_power_is_enabled(dev_priv,
15351                                                          POWER_DOMAIN_PIPE(i));
15352                 if (!error->pipe[i].power_domain_on)
15353                         continue;
15354
15355                 error->cursor[i].control = I915_READ(CURCNTR(i));
15356                 error->cursor[i].position = I915_READ(CURPOS(i));
15357                 error->cursor[i].base = I915_READ(CURBASE(i));
15358
15359                 error->plane[i].control = I915_READ(DSPCNTR(i));
15360                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15361                 if (INTEL_GEN(dev_priv) <= 3) {
15362                         error->plane[i].size = I915_READ(DSPSIZE(i));
15363                         error->plane[i].pos = I915_READ(DSPPOS(i));
15364                 }
15365                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15366                         error->plane[i].addr = I915_READ(DSPADDR(i));
15367                 if (INTEL_GEN(dev_priv) >= 4) {
15368                         error->plane[i].surface = I915_READ(DSPSURF(i));
15369                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15370                 }
15371
15372                 error->pipe[i].source = I915_READ(PIPESRC(i));
15373
15374                 if (HAS_GMCH_DISPLAY(dev_priv))
15375                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15376         }
15377
15378         /* Note: this does not include DSI transcoders. */
15379         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15380         if (HAS_DDI(dev_priv))
15381                 error->num_transcoders++; /* Account for eDP. */
15382
15383         for (i = 0; i < error->num_transcoders; i++) {
15384                 enum transcoder cpu_transcoder = transcoders[i];
15385
15386                 error->transcoder[i].power_domain_on =
15387                         __intel_display_power_is_enabled(dev_priv,
15388                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15389                 if (!error->transcoder[i].power_domain_on)
15390                         continue;
15391
15392                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15393
15394                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15395                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15396                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15397                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15398                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15399                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15400                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15401         }
15402
15403         return error;
15404 }
15405
15406 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15407
15408 void
15409 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15410                                 struct intel_display_error_state *error)
15411 {
15412         struct drm_i915_private *dev_priv = m->i915;
15413         int i;
15414
15415         if (!error)
15416                 return;
15417
15418         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15419         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15420                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15421                            error->power_well_driver);
15422         for_each_pipe(dev_priv, i) {
15423                 err_printf(m, "Pipe [%d]:\n", i);
15424                 err_printf(m, "  Power: %s\n",
15425                            onoff(error->pipe[i].power_domain_on));
15426                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15427                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15428
15429                 err_printf(m, "Plane [%d]:\n", i);
15430                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15431                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15432                 if (INTEL_GEN(dev_priv) <= 3) {
15433                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15434                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15435                 }
15436                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15437                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15438                 if (INTEL_GEN(dev_priv) >= 4) {
15439                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15440                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15441                 }
15442
15443                 err_printf(m, "Cursor [%d]:\n", i);
15444                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15445                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15446                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15447         }
15448
15449         for (i = 0; i < error->num_transcoders; i++) {
15450                 err_printf(m, "CPU transcoder: %s\n",
15451                            transcoder_name(error->transcoder[i].cpu_transcoder));
15452                 err_printf(m, "  Power: %s\n",
15453                            onoff(error->transcoder[i].power_domain_on));
15454                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15455                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15456                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15457                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15458                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15459                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15460                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15461         }
15462 }
15463
15464 #endif