drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 101                                   struct drm_i915_gem_object *obj,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125
 126 struct intel_limit {
 127         struct {
 128                 int min, max;
 129         } dot, vco, n, m, m1, m2, p, p1;
 130
 131         struct {
 132                 int dot_limit;
 133                 int p2_slow, p2_fast;
 134         } p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 152                       const char *name, u32 reg, int ref_freq)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         mutex_lock(&dev_priv->sb_lock);
 158         val = vlv_cck_read(dev_priv, reg);
 159         mutex_unlock(&dev_priv->sb_lock);
 160
 161         divider = val & CCK_FREQUENCY_VALUES;
 162
 163         WARN((val & CCK_FREQUENCY_STATUS) !=
 164              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 165              "%s change in progress\n", name);
 166
 167         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 168 }
 169
 170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 171                            const char *name, u32 reg)
 172 {
 173         if (dev_priv->hpll_freq == 0)
 174                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 175
 176         return vlv_get_cck_clock(dev_priv, name, reg,
 177                                  dev_priv->hpll_freq);
 178 }
 179
 180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 181 {
 182         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 183                 return;
 184
 185         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 186                                                       CCK_CZ_CLOCK_CONTROL);
 187
 188         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 189 }
 190
 191 static inline u32 /* units of 100MHz */
 192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 193                     const struct intel_crtc_state *pipe_config)
 194 {
 195         if (HAS_DDI(dev_priv))
 196                 return pipe_config->port_clock; /* SPLL */
 197         else if (IS_GEN5(dev_priv))
 198                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 199         else
 200                 return 270000;
 201 }
 202
 203 static const struct intel_limit intel_limits_i8xx_dac = {
 204         .dot = { .min = 25000, .max = 350000 },
 205         .vco = { .min = 908000, .max = 1512000 },
 206         .n = { .min = 2, .max = 16 },
 207         .m = { .min = 96, .max = 140 },
 208         .m1 = { .min = 18, .max = 26 },
 209         .m2 = { .min = 6, .max = 16 },
 210         .p = { .min = 4, .max = 128 },
 211         .p1 = { .min = 2, .max = 33 },
 212         .p2 = { .dot_limit = 165000,
 213                 .p2_slow = 4, .p2_fast = 2 },
 214 };
 215
 216 static const struct intel_limit intel_limits_i8xx_dvo = {
 217         .dot = { .min = 25000, .max = 350000 },
 218         .vco = { .min = 908000, .max = 1512000 },
 219         .n = { .min = 2, .max = 16 },
 220         .m = { .min = 96, .max = 140 },
 221         .m1 = { .min = 18, .max = 26 },
 222         .m2 = { .min = 6, .max = 16 },
 223         .p = { .min = 4, .max = 128 },
 224         .p1 = { .min = 2, .max = 33 },
 225         .p2 = { .dot_limit = 165000,
 226                 .p2_slow = 4, .p2_fast = 4 },
 227 };
 228
 229 static const struct intel_limit intel_limits_i8xx_lvds = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 908000, .max = 1512000 },
 232         .n = { .min = 2, .max = 16 },
 233         .m = { .min = 96, .max = 140 },
 234         .m1 = { .min = 18, .max = 26 },
 235         .m2 = { .min = 6, .max = 16 },
 236         .p = { .min = 4, .max = 128 },
 237         .p1 = { .min = 1, .max = 6 },
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 14, .p2_fast = 7 },
 240 };
 241
 242 static const struct intel_limit intel_limits_i9xx_sdvo = {
 243         .dot = { .min = 20000, .max = 400000 },
 244         .vco = { .min = 1400000, .max = 2800000 },
 245         .n = { .min = 1, .max = 6 },
 246         .m = { .min = 70, .max = 120 },
 247         .m1 = { .min = 8, .max = 18 },
 248         .m2 = { .min = 3, .max = 7 },
 249         .p = { .min = 5, .max = 80 },
 250         .p1 = { .min = 1, .max = 8 },
 251         .p2 = { .dot_limit = 200000,
 252                 .p2_slow = 10, .p2_fast = 5 },
 253 };
 254
 255 static const struct intel_limit intel_limits_i9xx_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1400000, .max = 2800000 },
 258         .n = { .min = 1, .max = 6 },
 259         .m = { .min = 70, .max = 120 },
 260         .m1 = { .min = 8, .max = 18 },
 261         .m2 = { .min = 3, .max = 7 },
 262         .p = { .min = 7, .max = 98 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 7 },
 266 };
 267
 268
 269 static const struct intel_limit intel_limits_g4x_sdvo = {
 270         .dot = { .min = 25000, .max = 270000 },
 271         .vco = { .min = 1750000, .max = 3500000},
 272         .n = { .min = 1, .max = 4 },
 273         .m = { .min = 104, .max = 138 },
 274         .m1 = { .min = 17, .max = 23 },
 275         .m2 = { .min = 5, .max = 11 },
 276         .p = { .min = 10, .max = 30 },
 277         .p1 = { .min = 1, .max = 3},
 278         .p2 = { .dot_limit = 270000,
 279                 .p2_slow = 10,
 280                 .p2_fast = 10
 281         },
 282 };
 283
 284 static const struct intel_limit intel_limits_g4x_hdmi = {
 285         .dot = { .min = 22000, .max = 400000 },
 286         .vco = { .min = 1750000, .max = 3500000},
 287         .n = { .min = 1, .max = 4 },
 288         .m = { .min = 104, .max = 138 },
 289         .m1 = { .min = 16, .max = 23 },
 290         .m2 = { .min = 5, .max = 11 },
 291         .p = { .min = 5, .max = 80 },
 292         .p1 = { .min = 1, .max = 8},
 293         .p2 = { .dot_limit = 165000,
 294                 .p2_slow = 10, .p2_fast = 5 },
 295 };
 296
 297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 298         .dot = { .min = 20000, .max = 115000 },
 299         .vco = { .min = 1750000, .max = 3500000 },
 300         .n = { .min = 1, .max = 3 },
 301         .m = { .min = 104, .max = 138 },
 302         .m1 = { .min = 17, .max = 23 },
 303         .m2 = { .min = 5, .max = 11 },
 304         .p = { .min = 28, .max = 112 },
 305         .p1 = { .min = 2, .max = 8 },
 306         .p2 = { .dot_limit = 0,
 307                 .p2_slow = 14, .p2_fast = 14
 308         },
 309 };
 310
 311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 312         .dot = { .min = 80000, .max = 224000 },
 313         .vco = { .min = 1750000, .max = 3500000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 104, .max = 138 },
 316         .m1 = { .min = 17, .max = 23 },
 317         .m2 = { .min = 5, .max = 11 },
 318         .p = { .min = 14, .max = 42 },
 319         .p1 = { .min = 2, .max = 6 },
 320         .p2 = { .dot_limit = 0,
 321                 .p2_slow = 7, .p2_fast = 7
 322         },
 323 };
 324
 325 static const struct intel_limit intel_limits_pineview_sdvo = {
 326         .dot = { .min = 20000, .max = 400000},
 327         .vco = { .min = 1700000, .max = 3500000 },
 328         /* Pineview's Ncounter is a ring counter */
 329         .n = { .min = 3, .max = 6 },
 330         .m = { .min = 2, .max = 256 },
 331         /* Pineview only has one combined m divider, which we treat as m2. */
 332         .m1 = { .min = 0, .max = 0 },
 333         .m2 = { .min = 0, .max = 254 },
 334         .p = { .min = 5, .max = 80 },
 335         .p1 = { .min = 1, .max = 8 },
 336         .p2 = { .dot_limit = 200000,
 337                 .p2_slow = 10, .p2_fast = 5 },
 338 };
 339
 340 static const struct intel_limit intel_limits_pineview_lvds = {
 341         .dot = { .min = 20000, .max = 400000 },
 342         .vco = { .min = 1700000, .max = 3500000 },
 343         .n = { .min = 3, .max = 6 },
 344         .m = { .min = 2, .max = 256 },
 345         .m1 = { .min = 0, .max = 0 },
 346         .m2 = { .min = 0, .max = 254 },
 347         .p = { .min = 7, .max = 112 },
 348         .p1 = { .min = 1, .max = 8 },
 349         .p2 = { .dot_limit = 112000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 /* Ironlake / Sandybridge
 354  *
 355  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 356  * the range value for them is (actual_value - 2).
 357  */
 358 static const struct intel_limit intel_limits_ironlake_dac = {
 359         .dot = { .min = 25000, .max = 350000 },
 360         .vco = { .min = 1760000, .max = 3510000 },
 361         .n = { .min = 1, .max = 5 },
 362         .m = { .min = 79, .max = 127 },
 363         .m1 = { .min = 12, .max = 22 },
 364         .m2 = { .min = 5, .max = 9 },
 365         .p = { .min = 5, .max = 80 },
 366         .p1 = { .min = 1, .max = 8 },
 367         .p2 = { .dot_limit = 225000,
 368                 .p2_slow = 10, .p2_fast = 5 },
 369 };
 370
 371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 372         .dot = { .min = 25000, .max = 350000 },
 373         .vco = { .min = 1760000, .max = 3510000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 79, .max = 118 },
 376         .m1 = { .min = 12, .max = 22 },
 377         .m2 = { .min = 5, .max = 9 },
 378         .p = { .min = 28, .max = 112 },
 379         .p1 = { .min = 2, .max = 8 },
 380         .p2 = { .dot_limit = 225000,
 381                 .p2_slow = 14, .p2_fast = 14 },
 382 };
 383
 384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 385         .dot = { .min = 25000, .max = 350000 },
 386         .vco = { .min = 1760000, .max = 3510000 },
 387         .n = { .min = 1, .max = 3 },
 388         .m = { .min = 79, .max = 127 },
 389         .m1 = { .min = 12, .max = 22 },
 390         .m2 = { .min = 5, .max = 9 },
 391         .p = { .min = 14, .max = 56 },
 392         .p1 = { .min = 2, .max = 8 },
 393         .p2 = { .dot_limit = 225000,
 394                 .p2_slow = 7, .p2_fast = 7 },
 395 };
 396
 397 /* LVDS 100mhz refclk limits. */
 398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 399         .dot = { .min = 25000, .max = 350000 },
 400         .vco = { .min = 1760000, .max = 3510000 },
 401         .n = { .min = 1, .max = 2 },
 402         .m = { .min = 79, .max = 126 },
 403         .m1 = { .min = 12, .max = 22 },
 404         .m2 = { .min = 5, .max = 9 },
 405         .p = { .min = 28, .max = 112 },
 406         .p1 = { .min = 2, .max = 8 },
 407         .p2 = { .dot_limit = 225000,
 408                 .p2_slow = 14, .p2_fast = 14 },
 409 };
 410
 411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 412         .dot = { .min = 25000, .max = 350000 },
 413         .vco = { .min = 1760000, .max = 3510000 },
 414         .n = { .min = 1, .max = 3 },
 415         .m = { .min = 79, .max = 126 },
 416         .m1 = { .min = 12, .max = 22 },
 417         .m2 = { .min = 5, .max = 9 },
 418         .p = { .min = 14, .max = 42 },
 419         .p1 = { .min = 2, .max = 6 },
 420         .p2 = { .dot_limit = 225000,
 421                 .p2_slow = 7, .p2_fast = 7 },
 422 };
 423
 424 static const struct intel_limit intel_limits_vlv = {
 425          /*
 426           * These are the data rate limits (measured in fast clocks)
 427           * since those are the strictest limits we have. The fast
 428           * clock and actual rate limits are more relaxed, so checking
 429           * them would make no difference.
 430           */
 431         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 432         .vco = { .min = 4000000, .max = 6000000 },
 433         .n = { .min = 1, .max = 7 },
 434         .m1 = { .min = 2, .max = 3 },
 435         .m2 = { .min = 11, .max = 156 },
 436         .p1 = { .min = 2, .max = 3 },
 437         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 438 };
 439
 440 static const struct intel_limit intel_limits_chv = {
 441         /*
 442          * These are the data rate limits (measured in fast clocks)
 443          * since those are the strictest limits we have.  The fast
 444          * clock and actual rate limits are more relaxed, so checking
 445          * them would make no difference.
 446          */
 447         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 448         .vco = { .min = 4800000, .max = 6480000 },
 449         .n = { .min = 1, .max = 1 },
 450         .m1 = { .min = 2, .max = 2 },
 451         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 452         .p1 = { .min = 2, .max = 4 },
 453         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 454 };
 455
 456 static const struct intel_limit intel_limits_bxt = {
 457         /* FIXME: find real dot limits */
 458         .dot = { .min = 0, .max = INT_MAX },
 459         .vco = { .min = 4800000, .max = 6700000 },
 460         .n = { .min = 1, .max = 1 },
 461         .m1 = { .min = 2, .max = 2 },
 462         /* FIXME: find real m2 limits */
 463         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 464         .p1 = { .min = 2, .max = 4 },
 465         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 466 };
 467
 468 static bool
 469 needs_modeset(struct drm_crtc_state *state)
 470 {
 471         return drm_atomic_crtc_needs_modeset(state);
 472 }
 473
 474 /*
 475  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 476  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 477  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 478  * The helpers' return value is the rate of the clock that is fed to the
 479  * display engine's pipe which can be the above fast dot clock rate or a
 480  * divided-down version of it.
 481  */
 482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 484 {
 485         clock->m = clock->m2 + 2;
 486         clock->p = clock->p1 * clock->p2;
 487         if (WARN_ON(clock->n == 0 || clock->p == 0))
 488                 return 0;
 489         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 490         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 491
 492         return clock->dot;
 493 }
 494
 495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 496 {
 497         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 498 }
 499
 500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 501 {
 502         clock->m = i9xx_dpll_compute_m(clock);
 503         clock->p = clock->p1 * clock->p2;
 504         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 505                 return 0;
 506         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 507         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 508
 509         return clock->dot;
 510 }
 511
 512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 513 {
 514         clock->m = clock->m1 * clock->m2;
 515         clock->p = clock->p1 * clock->p2;
 516         if (WARN_ON(clock->n == 0 || clock->p == 0))
 517                 return 0;
 518         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 519         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 520
 521         return clock->dot / 5;
 522 }
 523
 524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 525 {
 526         clock->m = clock->m1 * clock->m2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return 0;
 530         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 531                         clock->n << 22);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot / 5;
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 544                                const struct intel_limit *limit,
 545                                const struct dpll *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 557             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 558                 if (clock->m1 <= clock->m2)
 559                         INTELPllInvalid("m1 <= m2\n");
 560
 561         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 562             !IS_GEN9_LP(dev_priv)) {
 563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 564                         INTELPllInvalid("p out of range\n");
 565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 566                         INTELPllInvalid("m out of range\n");
 567         }
 568
 569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 570                 INTELPllInvalid("vco out of range\n");
 571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 572          * connector, etc., rather than just a single range.
 573          */
 574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 575                 INTELPllInvalid("dot out of range\n");
 576
 577         return true;
 578 }
 579
 580 static int
 581 i9xx_select_p2_div(const struct intel_limit *limit,
 582                    const struct intel_crtc_state *crtc_state,
 583                    int target)
 584 {
 585         struct drm_device *dev = crtc_state->base.crtc->dev;
 586
 587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         return limit->p2.p2_fast;
 595                 else
 596                         return limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         return limit->p2.p2_slow;
 600                 else
 601                         return limit->p2.p2_fast;
 602         }
 603 }
 604
 605 /*
 606  * Returns a set of divisors for the desired target clock with the given
 607  * refclk, or FALSE.  The returned values represent the clock equation:
 608  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 609  *
 610  * Target and reference clocks are specified in kHz.
 611  *
 612  * If match_clock is provided, then best_clock P divider must match the P
 613  * divider from @match_clock used for LVDS downclocking.
 614  */
 615 static bool
 616 i9xx_find_best_dpll(const struct intel_limit *limit,
 617                     struct intel_crtc_state *crtc_state,
 618                     int target, int refclk, struct dpll *match_clock,
 619                     struct dpll *best_clock)
 620 {
 621         struct drm_device *dev = crtc_state->base.crtc->dev;
 622         struct dpll clock;
 623         int err = target;
 624
 625         memset(best_clock, 0, sizeof(*best_clock));
 626
 627         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_calc_dpll_params(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(to_i915(dev),
 643                                                                 limit,
 644                                                                 &clock))
 645                                                 continue;
 646                                         if (match_clock &&
 647                                             clock.p != match_clock->p)
 648                                                 continue;
 649
 650                                         this_err = abs(clock.dot - target);
 651                                         if (this_err < err) {
 652                                                 *best_clock = clock;
 653                                                 err = this_err;
 654                                         }
 655                                 }
 656                         }
 657                 }
 658         }
 659
 660         return (err != target);
 661 }
 662
 663 /*
 664  * Returns a set of divisors for the desired target clock with the given
 665  * refclk, or FALSE.  The returned values represent the clock equation:
 666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 667  *
 668  * Target and reference clocks are specified in kHz.
 669  *
 670  * If match_clock is provided, then best_clock P divider must match the P
 671  * divider from @match_clock used for LVDS downclocking.
 672  */
 673 static bool
 674 pnv_find_best_dpll(const struct intel_limit *limit,
 675                    struct intel_crtc_state *crtc_state,
 676                    int target, int refclk, struct dpll *match_clock,
 677                    struct dpll *best_clock)
 678 {
 679         struct drm_device *dev = crtc_state->base.crtc->dev;
 680         struct dpll clock;
 681         int err = target;
 682
 683         memset(best_clock, 0, sizeof(*best_clock));
 684
 685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pnv_calc_dpll_params(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(to_i915(dev),
 699                                                                 limit,
 700                                                                 &clock))
 701                                                 continue;
 702                                         if (match_clock &&
 703                                             clock.p != match_clock->p)
 704                                                 continue;
 705
 706                                         this_err = abs(clock.dot - target);
 707                                         if (this_err < err) {
 708                                                 *best_clock = clock;
 709                                                 err = this_err;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715
 716         return (err != target);
 717 }
 718
 719 /*
 720  * Returns a set of divisors for the desired target clock with the given
 721  * refclk, or FALSE.  The returned values represent the clock equation:
 722  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 723  *
 724  * Target and reference clocks are specified in kHz.
 725  *
 726  * If match_clock is provided, then best_clock P divider must match the P
 727  * divider from @match_clock used for LVDS downclocking.
 728  */
 729 static bool
 730 g4x_find_best_dpll(const struct intel_limit *limit,
 731                    struct intel_crtc_state *crtc_state,
 732                    int target, int refclk, struct dpll *match_clock,
 733                    struct dpll *best_clock)
 734 {
 735         struct drm_device *dev = crtc_state->base.crtc->dev;
 736         struct dpll clock;
 737         int max_n;
 738         bool found = false;
 739         /* approximately equals target * 0.00585 */
 740         int err_most = (target >> 8) + (target >> 9);
 741
 742         memset(best_clock, 0, sizeof(*best_clock));
 743
 744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 745
 746         max_n = limit->n.max;
 747         /* based on hardware requirement, prefer smaller n to precision */
 748         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 749                 /* based on hardware requirement, prefere larger m1,m2 */
 750                 for (clock.m1 = limit->m1.max;
 751                      clock.m1 >= limit->m1.min; clock.m1--) {
 752                         for (clock.m2 = limit->m2.max;
 753                              clock.m2 >= limit->m2.min; clock.m2--) {
 754                                 for (clock.p1 = limit->p1.max;
 755                                      clock.p1 >= limit->p1.min; clock.p1--) {
 756                                         int this_err;
 757
 758                                         i9xx_calc_dpll_params(refclk, &clock);
 759                                         if (!intel_PLL_is_valid(to_i915(dev),
 760                                                                 limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 /*
 779  * Check if the calculated PLL configuration is more optimal compared to the
 780  * best configuration and error found so far. Return the calculated error.
 781  */
 782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 783                                const struct dpll *calculated_clock,
 784                                const struct dpll *best_clock,
 785                                unsigned int best_error_ppm,
 786                                unsigned int *error_ppm)
 787 {
 788         /*
 789          * For CHV ignore the error and consider only the P value.
 790          * Prefer a bigger P value based on HW requirements.
 791          */
 792         if (IS_CHERRYVIEW(to_i915(dev))) {
 793                 *error_ppm = 0;
 794
 795                 return calculated_clock->p > best_clock->p;
 796         }
 797
 798         if (WARN_ON_ONCE(!target_freq))
 799                 return false;
 800
 801         *error_ppm = div_u64(1000000ULL *
 802                                 abs(target_freq - calculated_clock->dot),
 803                              target_freq);
 804         /*
 805          * Prefer a better P value over a better (smaller) error if the error
 806          * is small. Ensure this preference for future configurations too by
 807          * setting the error to 0.
 808          */
 809         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 810                 *error_ppm = 0;
 811
 812                 return true;
 813         }
 814
 815         return *error_ppm + 10 < best_error_ppm;
 816 }
 817
 818 /*
 819  * Returns a set of divisors for the desired target clock with the given
 820  * refclk, or FALSE.  The returned values represent the clock equation:
 821  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 822  */
 823 static bool
 824 vlv_find_best_dpll(const struct intel_limit *limit,
 825                    struct intel_crtc_state *crtc_state,
 826                    int target, int refclk, struct dpll *match_clock,
 827                    struct dpll *best_clock)
 828 {
 829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 830         struct drm_device *dev = crtc->base.dev;
 831         struct dpll clock;
 832         unsigned int bestppm = 1000000;
 833         /* min update 19.2 MHz */
 834         int max_n = min(limit->n.max, refclk / 19200);
 835         bool found = false;
 836
 837         target *= 5; /* fast clock */
 838
 839         memset(best_clock, 0, sizeof(*best_clock));
 840
 841         /* based on hardware requirement, prefer smaller n to precision */
 842         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 843                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 844                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 845                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 846                                 clock.p = clock.p1 * clock.p2;
 847                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 848                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 849                                         unsigned int ppm;
 850
 851                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 852                                                                      refclk * clock.m1);
 853
 854                                         vlv_calc_dpll_params(refclk, &clock);
 855
 856                                         if (!intel_PLL_is_valid(to_i915(dev),
 857                                                                 limit,
 858                                                                 &clock))
 859                                                 continue;
 860
 861                                         if (!vlv_PLL_is_optimal(dev, target,
 862                                                                 &clock,
 863                                                                 best_clock,
 864                                                                 bestppm, &ppm))
 865                                                 continue;
 866
 867                                         *best_clock = clock;
 868                                         bestppm = ppm;
 869                                         found = true;
 870                                 }
 871                         }
 872                 }
 873         }
 874
 875         return found;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 chv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         unsigned int best_error_ppm;
 892         struct dpll clock;
 893         uint64_t m2;
 894         int found = false;
 895
 896         memset(best_clock, 0, sizeof(*best_clock));
 897         best_error_ppm = 1000000;
 898
 899         /*
 900          * Based on hardware doc, the n always set to 1, and m1 always
 901          * set to 2.  If requires to support 200Mhz refclk, we need to
 902          * revisit this because n may not 1 anymore.
 903          */
 904         clock.n = 1, clock.m1 = 2;
 905         target *= 5;    /* fast clock */
 906
 907         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 908                 for (clock.p2 = limit->p2.p2_fast;
 909                                 clock.p2 >= limit->p2.p2_slow;
 910                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 911                         unsigned int error_ppm;
 912
 913                         clock.p = clock.p1 * clock.p2;
 914
 915                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 916                                         clock.n) << 22, refclk * clock.m1);
 917
 918                         if (m2 > INT_MAX/clock.m1)
 919                                 continue;
 920
 921                         clock.m2 = m2;
 922
 923                         chv_calc_dpll_params(refclk, &clock);
 924
 925                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 926                                 continue;
 927
 928                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 929                                                 best_error_ppm, &error_ppm))
 930                                 continue;
 931
 932                         *best_clock = clock;
 933                         best_error_ppm = error_ppm;
 934                         found = true;
 935                 }
 936         }
 937
 938         return found;
 939 }
 940
 941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 942                         struct dpll *best_clock)
 943 {
 944         int refclk = 100000;
 945         const struct intel_limit *limit = &intel_limits_bxt;
 946
 947         return chv_find_best_dpll(limit, crtc_state,
 948                                   target_clock, refclk, NULL, best_clock);
 949 }
 950
 951 bool intel_crtc_active(struct intel_crtc *crtc)
 952 {
 953         /* Be paranoid as we can arrive here with only partial
 954          * state retrieved from the hardware during setup.
 955          *
 956          * We can ditch the adjusted_mode.crtc_clock check as soon
 957          * as Haswell has gained clock readout/fastboot support.
 958          *
 959          * We can ditch the crtc->primary->fb check as soon as we can
 960          * properly reconstruct framebuffers.
 961          *
 962          * FIXME: The intel_crtc->active here should be switched to
 963          * crtc->state->active once we have proper CRTC states wired up
 964          * for atomic.
 965          */
 966         return crtc->active && crtc->base.primary->state->fb &&
 967                 crtc->config->base.adjusted_mode.crtc_clock;
 968 }
 969
 970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 971                                              enum pipe pipe)
 972 {
 973         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 974
 975         return crtc->config->cpu_transcoder;
 976 }
 977
 978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
 979 {
 980         i915_reg_t reg = PIPEDSL(pipe);
 981         u32 line1, line2;
 982         u32 line_mask;
 983
 984         if (IS_GEN2(dev_priv))
 985                 line_mask = DSL_LINEMASK_GEN2;
 986         else
 987                 line_mask = DSL_LINEMASK_GEN3;
 988
 989         line1 = I915_READ(reg) & line_mask;
 990         msleep(5);
 991         line2 = I915_READ(reg) & line_mask;
 992
 993         return line1 == line2;
 994 }
 995
 996 /*
 997  * intel_wait_for_pipe_off - wait for pipe to turn off
 998  * @crtc: crtc whose pipe to wait for
 999  *
1000  * After disabling a pipe, we can't wait for vblank in the usual way,
1001  * spinning on the vblank interrupt status bit, since we won't actually
1002  * see an interrupt when the pipe is disabled.
1003  *
1004  * On Gen4 and above:
1005  *   wait for the pipe register state bit to turn off
1006  *
1007  * Otherwise:
1008  *   wait for the display line value to settle (it usually
1009  *   ends up stopping at the start of the next frame).
1010  *
1011  */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016         enum pipe pipe = crtc->pipe;
1017
1018         if (INTEL_GEN(dev_priv) >= 4) {
1019                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021                 /* Wait for the Pipe State to go off */
1022                 if (intel_wait_for_register(dev_priv,
1023                                             reg, I965_PIPECONF_ACTIVE, 0,
1024                                             100))
1025                         WARN(1, "pipe_off wait timed out\n");
1026         } else {
1027                 /* Wait for the display line to settle */
1028                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029                         WARN(1, "pipe_off wait timed out\n");
1030         }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035                 enum pipe pipe, bool state)
1036 {
1037         u32 val;
1038         bool cur_state;
1039
1040         val = I915_READ(DPLL(pipe));
1041         cur_state = !!(val & DPLL_VCO_ENABLE);
1042         I915_STATE_WARN(cur_state != state,
1043              "PLL state assertion failure (expected %s, current %s)\n",
1044                         onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050         u32 val;
1051         bool cur_state;
1052
1053         mutex_lock(&dev_priv->sb_lock);
1054         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055         mutex_unlock(&dev_priv->sb_lock);
1056
1057         cur_state = val & DSI_PLL_VCO_EN;
1058         I915_STATE_WARN(cur_state != state,
1059              "DSI PLL state assertion failure (expected %s, current %s)\n",
1060                         onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064                           enum pipe pipe, bool state)
1065 {
1066         bool cur_state;
1067         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068                                                                       pipe);
1069
1070         if (HAS_DDI(dev_priv)) {
1071                 /* DDI does not have a specific FDI_TX register */
1072                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074         } else {
1075                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         I915_STATE_WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080                         onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         u32 val;
1089         bool cur_state;
1090
1091         val = I915_READ(FDI_RX_CTL(pipe));
1092         cur_state = !!(val & FDI_RX_ENABLE);
1093         I915_STATE_WARN(cur_state != state,
1094              "FDI RX state assertion failure (expected %s, current %s)\n",
1095                         onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101                                       enum pipe pipe)
1102 {
1103         u32 val;
1104
1105         /* ILK FDI PLL is always enabled */
1106         if (IS_GEN5(dev_priv))
1107                 return;
1108
1109         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110         if (HAS_DDI(dev_priv))
1111                 return;
1112
1113         val = I915_READ(FDI_TX_CTL(pipe));
1114         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118                        enum pipe pipe, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         val = I915_READ(FDI_RX_CTL(pipe));
1124         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127                         onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132         i915_reg_t pp_reg;
1133         u32 val;
1134         enum pipe panel_pipe = PIPE_A;
1135         bool locked = true;
1136
1137         if (WARN_ON(HAS_DDI(dev_priv)))
1138                 return;
1139
1140         if (HAS_PCH_SPLIT(dev_priv)) {
1141                 u32 port_sel;
1142
1143                 pp_reg = PP_CONTROL(0);
1144                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148                         panel_pipe = PIPE_B;
1149                 /* XXX: else fix for eDP */
1150         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151                 /* presumably write lock depends on pipe, not port select */
1152                 pp_reg = PP_CONTROL(pipe);
1153                 panel_pipe = pipe;
1154         } else {
1155                 pp_reg = PP_CONTROL(0);
1156                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157                         panel_pipe = PIPE_B;
1158         }
1159
1160         val = I915_READ(pp_reg);
1161         if (!(val & PANEL_POWER_ON) ||
1162             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163                 locked = false;
1164
1165         I915_STATE_WARN(panel_pipe == pipe && locked,
1166              "panel assertion failure, pipe %c regs locked\n",
1167              pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171                           enum pipe pipe, bool state)
1172 {
1173         bool cur_state;
1174
1175         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177         else
1178                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180         I915_STATE_WARN(cur_state != state,
1181              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182                         pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188                  enum pipe pipe, bool state)
1189 {
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193         enum intel_display_power_domain power_domain;
1194
1195         /* if we need the pipe quirk it must be always on */
1196         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198                 state = true;
1199
1200         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203                 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205                 intel_display_power_put(dev_priv, power_domain);
1206         } else {
1207                 cur_state = false;
1208         }
1209
1210         I915_STATE_WARN(cur_state != state,
1211              "pipe %c assertion failure (expected %s, current %s)\n",
1212                         pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216                          enum plane plane, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(DSPCNTR(plane));
1222         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "plane %c assertion failure (expected %s, current %s)\n",
1225                         plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232                                    enum pipe pipe)
1233 {
1234         int i;
1235
1236         /* Primary planes are fixed to pipes on gen4+ */
1237         if (INTEL_GEN(dev_priv) >= 4) {
1238                 u32 val = I915_READ(DSPCNTR(pipe));
1239                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240                      "plane %c assertion failure, should be disabled but not\n",
1241                      plane_name(pipe));
1242                 return;
1243         }
1244
1245         /* Need to check both planes against the pipe */
1246         for_each_pipe(dev_priv, i) {
1247                 u32 val = I915_READ(DSPCNTR(i));
1248                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249                         DISPPLANE_SEL_PIPE_SHIFT;
1250                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252                      plane_name(i), pipe_name(pipe));
1253         }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257                                     enum pipe pipe)
1258 {
1259         int sprite;
1260
1261         if (INTEL_GEN(dev_priv) >= 9) {
1262                 for_each_sprite(dev_priv, pipe, sprite) {
1263                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266                              sprite, pipe_name(pipe));
1267                 }
1268         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269                 for_each_sprite(dev_priv, pipe, sprite) {
1270                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271                         I915_STATE_WARN(val & SP_ENABLE,
1272                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273                              sprite_name(pipe, sprite), pipe_name(pipe));
1274                 }
1275         } else if (INTEL_GEN(dev_priv) >= 7) {
1276                 u32 val = I915_READ(SPRCTL(pipe));
1277                 I915_STATE_WARN(val & SPRITE_ENABLE,
1278                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279                      plane_name(pipe), pipe_name(pipe));
1280         } else if (INTEL_GEN(dev_priv) >= 5) {
1281                 u32 val = I915_READ(DVSCNTR(pipe));
1282                 I915_STATE_WARN(val & DVS_ENABLE,
1283                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                      plane_name(pipe), pipe_name(pipe));
1285         }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291                 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                     enum pipe pipe)
1296 {
1297         u32 val;
1298         bool enabled;
1299
1300         val = I915_READ(PCH_TRANSCONF(pipe));
1301         enabled = !!(val & TRANS_ENABLE);
1302         I915_STATE_WARN(enabled,
1303              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304              pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308                             enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310         if ((val & DP_PORT_EN) == 0)
1311                 return false;
1312
1313         if (HAS_PCH_CPT(dev_priv)) {
1314                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else if (IS_CHERRYVIEW(dev_priv)) {
1318                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & SDVO_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv)) {
1334                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335                         return false;
1336         } else if (IS_CHERRYVIEW(dev_priv)) {
1337                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338                         return false;
1339         } else {
1340                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347                               enum pipe pipe, u32 val)
1348 {
1349         if ((val & LVDS_PORT_EN) == 0)
1350                 return false;
1351
1352         if (HAS_PCH_CPT(dev_priv)) {
1353                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354                         return false;
1355         } else {
1356                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357                         return false;
1358         }
1359         return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363                               enum pipe pipe, u32 val)
1364 {
1365         if ((val & ADPA_DAC_ENABLE) == 0)
1366                 return false;
1367         if (HAS_PCH_CPT(dev_priv)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378                                    enum pipe pipe, i915_reg_t reg,
1379                                    u32 port_sel)
1380 {
1381         u32 val = I915_READ(reg);
1382         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384              i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387              && (val & DP_PIPEB_SELECT),
1388              "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392                                      enum pipe pipe, i915_reg_t reg)
1393 {
1394         u32 val = I915_READ(reg);
1395         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397              i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400              && (val & SDVO_PIPE_B_SELECT),
1401              "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405                                       enum pipe pipe)
1406 {
1407         u32 val;
1408
1409         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413         val = I915_READ(PCH_ADPA);
1414         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415              "PCH VGA enabled on transcoder %c, should be disabled\n",
1416              pipe_name(pipe));
1417
1418         val = I915_READ(PCH_LVDS);
1419         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433
1434         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435         POSTING_READ(DPLL(pipe));
1436         udelay(150);
1437
1438         if (intel_wait_for_register(dev_priv,
1439                                     DPLL(pipe),
1440                                     DPLL_LOCK_VLV,
1441                                     DPLL_LOCK_VLV,
1442                                     1))
1443                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447                            const struct intel_crtc_state *pipe_config)
1448 {
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         enum pipe pipe = crtc->pipe;
1451
1452         assert_pipe_disabled(dev_priv, pipe);
1453
1454         /* PLL is protected by panel, make sure we can write it */
1455         assert_panel_unlocked(dev_priv, pipe);
1456
1457         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458                 _vlv_enable_pll(crtc, pipe_config);
1459
1460         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461         POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466                             const struct intel_crtc_state *pipe_config)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469         enum pipe pipe = crtc->pipe;
1470         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471         u32 tmp;
1472
1473         mutex_lock(&dev_priv->sb_lock);
1474
1475         /* Enable back the 10bit clock to display controller */
1476         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477         tmp |= DPIO_DCLKP_EN;
1478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480         mutex_unlock(&dev_priv->sb_lock);
1481
1482         /*
1483          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484          */
1485         udelay(1);
1486
1487         /* Enable PLL */
1488         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490         /* Check PLL is locked */
1491         if (intel_wait_for_register(dev_priv,
1492                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493                                     1))
1494                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498                            const struct intel_crtc_state *pipe_config)
1499 {
1500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501         enum pipe pipe = crtc->pipe;
1502
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         /* PLL is protected by panel, make sure we can write it */
1506         assert_panel_unlocked(dev_priv, pipe);
1507
1508         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509                 _chv_enable_pll(crtc, pipe_config);
1510
1511         if (pipe != PIPE_A) {
1512                 /*
1513                  * WaPixelRepeatModeFixForC0:chv
1514                  *
1515                  * DPLLCMD is AWOL. Use chicken bits to propagate
1516                  * the value from DPLLBMD to either pipe B or C.
1517                  */
1518                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520                 I915_WRITE(CBR4_VLV, 0);
1521                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523                 /*
1524                  * DPLLB VGA mode also seems to cause problems.
1525                  * We should always have it disabled.
1526                  */
1527                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528         } else {
1529                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530                 POSTING_READ(DPLL_MD(pipe));
1531         }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536         struct intel_crtc *crtc;
1537         int count = 0;
1538
1539         for_each_intel_crtc(&dev_priv->drm, crtc) {
1540                 count += crtc->base.state->active &&
1541                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542         }
1543
1544         return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         i915_reg_t reg = DPLL(crtc->pipe);
1551         u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553         assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555         /* PLL is protected by panel, make sure we can write it */
1556         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557                 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559         /* Enable DVO 2x clock on both PLLs if necessary */
1560         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561                 /*
1562                  * It appears to be important that we don't enable this
1563                  * for the current pipe before otherwise configuring the
1564                  * PLL. No idea how this should be handled if multiple
1565                  * DVO outputs are enabled simultaneosly.
1566                  */
1567                 dpll |= DPLL_DVO_2X_MODE;
1568                 I915_WRITE(DPLL(!crtc->pipe),
1569                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570         }
1571
1572         /*
1573          * Apparently we need to have VGA mode enabled prior to changing
1574          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575          * dividers, even though the register value does change.
1576          */
1577         I915_WRITE(reg, 0);
1578
1579         I915_WRITE(reg, dpll);
1580
1581         /* Wait for the clocks to stabilize. */
1582         POSTING_READ(reg);
1583         udelay(150);
1584
1585         if (INTEL_GEN(dev_priv) >= 4) {
1586                 I915_WRITE(DPLL_MD(crtc->pipe),
1587                            crtc->config->dpll_hw_state.dpll_md);
1588         } else {
1589                 /* The pixel multiplier can only be updated once the
1590                  * DPLL is enabled and the clocks are stable.
1591                  *
1592                  * So write it again.
1593                  */
1594                 I915_WRITE(reg, dpll);
1595         }
1596
1597         /* We do this three times for luck */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604         I915_WRITE(reg, dpll);
1605         POSTING_READ(reg);
1606         udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610  * i9xx_disable_pll - disable a PLL
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe PLL to disable
1613  *
1614  * Disable the PLL for @pipe, making sure the pipe is off first.
1615  *
1616  * Note!  This is for pre-ILK only.
1617  */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621         enum pipe pipe = crtc->pipe;
1622
1623         /* Disable DVO 2x clock on both PLLs if necessary */
1624         if (IS_I830(dev_priv) &&
1625             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626             !intel_num_dvo_pipes(dev_priv)) {
1627                 I915_WRITE(DPLL(PIPE_B),
1628                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629                 I915_WRITE(DPLL(PIPE_A),
1630                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631         }
1632
1633         /* Don't disable pipe or pipe PLLs if needed */
1634         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636                 return;
1637
1638         /* Make sure the pipe isn't still relying on us */
1639         assert_pipe_disabled(dev_priv, pipe);
1640
1641         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642         POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647         u32 val;
1648
1649         /* Make sure the pipe isn't still relying on us */
1650         assert_pipe_disabled(dev_priv, pipe);
1651
1652         val = DPLL_INTEGRATED_REF_CLK_VLV |
1653                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654         if (pipe != PIPE_A)
1655                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657         I915_WRITE(DPLL(pipe), val);
1658         POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664         u32 val;
1665
1666         /* Make sure the pipe isn't still relying on us */
1667         assert_pipe_disabled(dev_priv, pipe);
1668
1669         val = DPLL_SSC_REF_CLK_CHV |
1670                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671         if (pipe != PIPE_A)
1672                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674         I915_WRITE(DPLL(pipe), val);
1675         POSTING_READ(DPLL(pipe));
1676
1677         mutex_lock(&dev_priv->sb_lock);
1678
1679         /* Disable 10bit clock to display controller */
1680         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681         val &= ~DPIO_DCLKP_EN;
1682         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684         mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688                          struct intel_digital_port *dport,
1689                          unsigned int expected_mask)
1690 {
1691         u32 port_mask;
1692         i915_reg_t dpll_reg;
1693
1694         switch (dport->port) {
1695         case PORT_B:
1696                 port_mask = DPLL_PORTB_READY_MASK;
1697                 dpll_reg = DPLL(0);
1698                 break;
1699         case PORT_C:
1700                 port_mask = DPLL_PORTC_READY_MASK;
1701                 dpll_reg = DPLL(0);
1702                 expected_mask <<= 4;
1703                 break;
1704         case PORT_D:
1705                 port_mask = DPLL_PORTD_READY_MASK;
1706                 dpll_reg = DPIO_PHY_STATUS;
1707                 break;
1708         default:
1709                 BUG();
1710         }
1711
1712         if (intel_wait_for_register(dev_priv,
1713                                     dpll_reg, port_mask, expected_mask,
1714                                     1000))
1715                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720                                            enum pipe pipe)
1721 {
1722         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723                                                                 pipe);
1724         i915_reg_t reg;
1725         uint32_t val, pipeconf_val;
1726
1727         /* Make sure PCH DPLL is enabled */
1728         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730         /* FDI must be feeding us bits for PCH ports */
1731         assert_fdi_tx_enabled(dev_priv, pipe);
1732         assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734         if (HAS_PCH_CPT(dev_priv)) {
1735                 /* Workaround: Set the timing override bit before enabling the
1736                  * pch transcoder. */
1737                 reg = TRANS_CHICKEN2(pipe);
1738                 val = I915_READ(reg);
1739                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740                 I915_WRITE(reg, val);
1741         }
1742
1743         reg = PCH_TRANSCONF(pipe);
1744         val = I915_READ(reg);
1745         pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747         if (HAS_PCH_IBX(dev_priv)) {
1748                 /*
1749                  * Make the BPC in transcoder be consistent with
1750                  * that in pipeconf reg. For HDMI we must use 8bpc
1751                  * here for both 8bpc and 12bpc.
1752                  */
1753                 val &= ~PIPECONF_BPC_MASK;
1754                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755                         val |= PIPECONF_8BPC;
1756                 else
1757                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1758         }
1759
1760         val &= ~TRANS_INTERLACE_MASK;
1761         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762                 if (HAS_PCH_IBX(dev_priv) &&
1763                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764                         val |= TRANS_LEGACY_INTERLACED_ILK;
1765                 else
1766                         val |= TRANS_INTERLACED;
1767         else
1768                 val |= TRANS_PROGRESSIVE;
1769
1770         I915_WRITE(reg, val | TRANS_ENABLE);
1771         if (intel_wait_for_register(dev_priv,
1772                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773                                     100))
1774                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778                                       enum transcoder cpu_transcoder)
1779 {
1780         u32 val, pipeconf_val;
1781
1782         /* FDI must be feeding us bits for PCH ports */
1783         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786         /* Workaround: set timing override bit. */
1787         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791         val = TRANS_ENABLE;
1792         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795             PIPECONF_INTERLACED_ILK)
1796                 val |= TRANS_INTERLACED;
1797         else
1798                 val |= TRANS_PROGRESSIVE;
1799
1800         I915_WRITE(LPT_TRANSCONF, val);
1801         if (intel_wait_for_register(dev_priv,
1802                                     LPT_TRANSCONF,
1803                                     TRANS_STATE_ENABLE,
1804                                     TRANS_STATE_ENABLE,
1805                                     100))
1806                 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810                                             enum pipe pipe)
1811 {
1812         i915_reg_t reg;
1813         uint32_t val;
1814
1815         /* FDI relies on the transcoder */
1816         assert_fdi_tx_disabled(dev_priv, pipe);
1817         assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819         /* Ports must be off as well */
1820         assert_pch_ports_disabled(dev_priv, pipe);
1821
1822         reg = PCH_TRANSCONF(pipe);
1823         val = I915_READ(reg);
1824         val &= ~TRANS_ENABLE;
1825         I915_WRITE(reg, val);
1826         /* wait for PCH transcoder off, transcoder state */
1827         if (intel_wait_for_register(dev_priv,
1828                                     reg, TRANS_STATE_ENABLE, 0,
1829                                     50))
1830                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832         if (HAS_PCH_CPT(dev_priv)) {
1833                 /* Workaround: Clear the timing override chicken bit again. */
1834                 reg = TRANS_CHICKEN2(pipe);
1835                 val = I915_READ(reg);
1836                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837                 I915_WRITE(reg, val);
1838         }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843         u32 val;
1844
1845         val = I915_READ(LPT_TRANSCONF);
1846         val &= ~TRANS_ENABLE;
1847         I915_WRITE(LPT_TRANSCONF, val);
1848         /* wait for PCH transcoder off, transcoder state */
1849         if (intel_wait_for_register(dev_priv,
1850                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851                                     50))
1852                 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854         /* Workaround: clear timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864         WARN_ON(!crtc->config->has_pch_encoder);
1865
1866         if (HAS_PCH_LPT(dev_priv))
1867                 return TRANSCODER_A;
1868         else
1869                 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873  * intel_enable_pipe - enable a pipe, asserting requirements
1874  * @crtc: crtc responsible for the pipe
1875  *
1876  * Enable @crtc's pipe, making sure that various hardware specific requirements
1877  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878  */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881         struct drm_device *dev = crtc->base.dev;
1882         struct drm_i915_private *dev_priv = to_i915(dev);
1883         enum pipe pipe = crtc->pipe;
1884         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885         i915_reg_t reg;
1886         u32 val;
1887
1888         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890         assert_planes_disabled(dev_priv, pipe);
1891         assert_cursor_disabled(dev_priv, pipe);
1892         assert_sprites_disabled(dev_priv, pipe);
1893
1894         /*
1895          * A pipe without a PLL won't actually be able to drive bits from
1896          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1897          * need the check.
1898          */
1899         if (HAS_GMCH_DISPLAY(dev_priv)) {
1900                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901                         assert_dsi_pll_enabled(dev_priv);
1902                 else
1903                         assert_pll_enabled(dev_priv, pipe);
1904         } else {
1905                 if (crtc->config->has_pch_encoder) {
1906                         /* if driving the PCH, we need FDI enabled */
1907                         assert_fdi_rx_pll_enabled(dev_priv,
1908                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1909                         assert_fdi_tx_pll_enabled(dev_priv,
1910                                                   (enum pipe) cpu_transcoder);
1911                 }
1912                 /* FIXME: assert CPU port conditions for SNB+ */
1913         }
1914
1915         reg = PIPECONF(cpu_transcoder);
1916         val = I915_READ(reg);
1917         if (val & PIPECONF_ENABLE) {
1918                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920                 return;
1921         }
1922
1923         I915_WRITE(reg, val | PIPECONF_ENABLE);
1924         POSTING_READ(reg);
1925
1926         /*
1927          * Until the pipe starts DSL will read as 0, which would cause
1928          * an apparent vblank timestamp jump, which messes up also the
1929          * frame count when it's derived from the timestamps. So let's
1930          * wait for the pipe to start properly before we call
1931          * drm_crtc_vblank_on()
1932          */
1933         if (dev->max_vblank_count == 0 &&
1934             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939  * intel_disable_pipe - disable a pipe, asserting requirements
1940  * @crtc: crtc whose pipes is to be disabled
1941  *
1942  * Disable the pipe of @crtc, making sure that various hardware
1943  * specific requirements are met, if applicable, e.g. plane
1944  * disabled, panel fitter off, etc.
1945  *
1946  * Will wait until the pipe has shut down before returning.
1947  */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952         enum pipe pipe = crtc->pipe;
1953         i915_reg_t reg;
1954         u32 val;
1955
1956         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958         /*
1959          * Make sure planes won't keep trying to pump pixels to us,
1960          * or we might hang the display.
1961          */
1962         assert_planes_disabled(dev_priv, pipe);
1963         assert_cursor_disabled(dev_priv, pipe);
1964         assert_sprites_disabled(dev_priv, pipe);
1965
1966         reg = PIPECONF(cpu_transcoder);
1967         val = I915_READ(reg);
1968         if ((val & PIPECONF_ENABLE) == 0)
1969                 return;
1970
1971         /*
1972          * Double wide has implications for planes
1973          * so best keep it disabled when not needed.
1974          */
1975         if (crtc->config->double_wide)
1976                 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978         /* Don't disable pipe or pipe PLLs if needed */
1979         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981                 val &= ~PIPECONF_ENABLE;
1982
1983         I915_WRITE(reg, val);
1984         if ((val & PIPECONF_ENABLE) == 0)
1985                 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990         return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
1994                                            uint64_t fb_modifier, unsigned int cpp)
1995 {
1996         switch (fb_modifier) {
1997         case DRM_FORMAT_MOD_NONE:
1998                 return cpp;
1999         case I915_FORMAT_MOD_X_TILED:
2000                 if (IS_GEN2(dev_priv))
2001                         return 128;
2002                 else
2003                         return 512;
2004         case I915_FORMAT_MOD_Y_TILED:
2005                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2006                         return 128;
2007                 else
2008                         return 512;
2009         case I915_FORMAT_MOD_Yf_TILED:
2010                 switch (cpp) {
2011                 case 1:
2012                         return 64;
2013                 case 2:
2014                 case 4:
2015                         return 128;
2016                 case 8:
2017                 case 16:
2018                         return 256;
2019                 default:
2020                         MISSING_CASE(cpp);
2021                         return cpp;
2022                 }
2023                 break;
2024         default:
2025                 MISSING_CASE(fb_modifier);
2026                 return cpp;
2027         }
2028 }
2029
2030 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2031                                uint64_t fb_modifier, unsigned int cpp)
2032 {
2033         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2034                 return 1;
2035         else
2036                 return intel_tile_size(dev_priv) /
2037                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2038 }
2039
2040 /* Return the tile dimensions in pixel units */
2041 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2042                             unsigned int *tile_width,
2043                             unsigned int *tile_height,
2044                             uint64_t fb_modifier,
2045                             unsigned int cpp)
2046 {
2047         unsigned int tile_width_bytes =
2048                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2049
2050         *tile_width = tile_width_bytes / cpp;
2051         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2052 }
2053
2054 unsigned int
2055 intel_fb_align_height(struct drm_i915_private *dev_priv,
2056                       unsigned int height,
2057                       uint32_t pixel_format,
2058                       uint64_t fb_modifier)
2059 {
2060         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2061         unsigned int tile_height = intel_tile_height(dev_priv, fb_modifier, cpp);
2062
2063         return ALIGN(height, tile_height);
2064 }
2065
2066 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2067 {
2068         unsigned int size = 0;
2069         int i;
2070
2071         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2072                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2073
2074         return size;
2075 }
2076
2077 static void
2078 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2079                         const struct drm_framebuffer *fb,
2080                         unsigned int rotation)
2081 {
2082         view->type = I915_GGTT_VIEW_NORMAL;
2083         if (drm_rotation_90_or_270(rotation)) {
2084                 view->type = I915_GGTT_VIEW_ROTATED;
2085                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2086         }
2087 }
2088
2089 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2090 {
2091         if (INTEL_INFO(dev_priv)->gen >= 9)
2092                 return 256 * 1024;
2093         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2094                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2095                 return 128 * 1024;
2096         else if (INTEL_INFO(dev_priv)->gen >= 4)
2097                 return 4 * 1024;
2098         else
2099                 return 0;
2100 }
2101
2102 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2103                                          uint64_t fb_modifier)
2104 {
2105         switch (fb_modifier) {
2106         case DRM_FORMAT_MOD_NONE:
2107                 return intel_linear_alignment(dev_priv);
2108         case I915_FORMAT_MOD_X_TILED:
2109                 if (INTEL_INFO(dev_priv)->gen >= 9)
2110                         return 256 * 1024;
2111                 return 0;
2112         case I915_FORMAT_MOD_Y_TILED:
2113         case I915_FORMAT_MOD_Yf_TILED:
2114                 return 1 * 1024 * 1024;
2115         default:
2116                 MISSING_CASE(fb_modifier);
2117                 return 0;
2118         }
2119 }
2120
2121 struct i915_vma *
2122 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2123 {
2124         struct drm_device *dev = fb->dev;
2125         struct drm_i915_private *dev_priv = to_i915(dev);
2126         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2127         struct i915_ggtt_view view;
2128         struct i915_vma *vma;
2129         u32 alignment;
2130
2131         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2132
2133         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2134
2135         intel_fill_fb_ggtt_view(&view, fb, rotation);
2136
2137         /* Note that the w/a also requires 64 PTE of padding following the
2138          * bo. We currently fill all unused PTE with the shadow page and so
2139          * we should always have valid PTE following the scanout preventing
2140          * the VT-d warning.
2141          */
2142         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2143                 alignment = 256 * 1024;
2144
2145         /*
2146          * Global gtt pte registers are special registers which actually forward
2147          * writes to a chunk of system memory. Which means that there is no risk
2148          * that the register values disappear as soon as we call
2149          * intel_runtime_pm_put(), so it is correct to wrap only the
2150          * pin/unpin/fence and not more.
2151          */
2152         intel_runtime_pm_get(dev_priv);
2153
2154         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2155         if (IS_ERR(vma))
2156                 goto err;
2157
2158         if (i915_vma_is_map_and_fenceable(vma)) {
2159                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2160                  * fence, whereas 965+ only requires a fence if using
2161                  * framebuffer compression.  For simplicity, we always, when
2162                  * possible, install a fence as the cost is not that onerous.
2163                  *
2164                  * If we fail to fence the tiled scanout, then either the
2165                  * modeset will reject the change (which is highly unlikely as
2166                  * the affected systems, all but one, do not have unmappable
2167                  * space) or we will not be able to enable full powersaving
2168                  * techniques (also likely not to apply due to various limits
2169                  * FBC and the like impose on the size of the buffer, which
2170                  * presumably we violated anyway with this unmappable buffer).
2171                  * Anyway, it is presumably better to stumble onwards with
2172                  * something and try to run the system in a "less than optimal"
2173                  * mode that matches the user configuration.
2174                  */
2175                 if (i915_vma_get_fence(vma) == 0)
2176                         i915_vma_pin_fence(vma);
2177         }
2178
2179         i915_vma_get(vma);
2180 err:
2181         intel_runtime_pm_put(dev_priv);
2182         return vma;
2183 }
2184
2185 void intel_unpin_fb_vma(struct i915_vma *vma)
2186 {
2187         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2188
2189         i915_vma_unpin_fence(vma);
2190         i915_gem_object_unpin_from_display_plane(vma);
2191         i915_vma_put(vma);
2192 }
2193
2194 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2195                           unsigned int rotation)
2196 {
2197         if (drm_rotation_90_or_270(rotation))
2198                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2199         else
2200                 return fb->pitches[plane];
2201 }
2202
2203 /*
2204  * Convert the x/y offsets into a linear offset.
2205  * Only valid with 0/180 degree rotation, which is fine since linear
2206  * offset is only used with linear buffers on pre-hsw and tiled buffers
2207  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2208  */
2209 u32 intel_fb_xy_to_linear(int x, int y,
2210                           const struct intel_plane_state *state,
2211                           int plane)
2212 {
2213         const struct drm_framebuffer *fb = state->base.fb;
2214         unsigned int cpp = fb->format->cpp[plane];
2215         unsigned int pitch = fb->pitches[plane];
2216
2217         return y * pitch + x * cpp;
2218 }
2219
2220 /*
2221  * Add the x/y offsets derived from fb->offsets[] to the user
2222  * specified plane src x/y offsets. The resulting x/y offsets
2223  * specify the start of scanout from the beginning of the gtt mapping.
2224  */
2225 void intel_add_fb_offsets(int *x, int *y,
2226                           const struct intel_plane_state *state,
2227                           int plane)
2228
2229 {
2230         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2231         unsigned int rotation = state->base.rotation;
2232
2233         if (drm_rotation_90_or_270(rotation)) {
2234                 *x += intel_fb->rotated[plane].x;
2235                 *y += intel_fb->rotated[plane].y;
2236         } else {
2237                 *x += intel_fb->normal[plane].x;
2238                 *y += intel_fb->normal[plane].y;
2239         }
2240 }
2241
2242 /*
2243  * Input tile dimensions and pitch must already be
2244  * rotated to match x and y, and in pixel units.
2245  */
2246 static u32 _intel_adjust_tile_offset(int *x, int *y,
2247                                      unsigned int tile_width,
2248                                      unsigned int tile_height,
2249                                      unsigned int tile_size,
2250                                      unsigned int pitch_tiles,
2251                                      u32 old_offset,
2252                                      u32 new_offset)
2253 {
2254         unsigned int pitch_pixels = pitch_tiles * tile_width;
2255         unsigned int tiles;
2256
2257         WARN_ON(old_offset & (tile_size - 1));
2258         WARN_ON(new_offset & (tile_size - 1));
2259         WARN_ON(new_offset > old_offset);
2260
2261         tiles = (old_offset - new_offset) / tile_size;
2262
2263         *y += tiles / pitch_tiles * tile_height;
2264         *x += tiles % pitch_tiles * tile_width;
2265
2266         /* minimize x in case it got needlessly big */
2267         *y += *x / pitch_pixels * tile_height;
2268         *x %= pitch_pixels;
2269
2270         return new_offset;
2271 }
2272
2273 /*
2274  * Adjust the tile offset by moving the difference into
2275  * the x/y offsets.
2276  */
2277 static u32 intel_adjust_tile_offset(int *x, int *y,
2278                                     const struct intel_plane_state *state, int plane,
2279                                     u32 old_offset, u32 new_offset)
2280 {
2281         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2282         const struct drm_framebuffer *fb = state->base.fb;
2283         unsigned int cpp = fb->format->cpp[plane];
2284         unsigned int rotation = state->base.rotation;
2285         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2286
2287         WARN_ON(new_offset > old_offset);
2288
2289         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2290                 unsigned int tile_size, tile_width, tile_height;
2291                 unsigned int pitch_tiles;
2292
2293                 tile_size = intel_tile_size(dev_priv);
2294                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2295                                 fb->modifier, cpp);
2296
2297                 if (drm_rotation_90_or_270(rotation)) {
2298                         pitch_tiles = pitch / tile_height;
2299                         swap(tile_width, tile_height);
2300                 } else {
2301                         pitch_tiles = pitch / (tile_width * cpp);
2302                 }
2303
2304                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2305                                           tile_size, pitch_tiles,
2306                                           old_offset, new_offset);
2307         } else {
2308                 old_offset += *y * pitch + *x * cpp;
2309
2310                 *y = (old_offset - new_offset) / pitch;
2311                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2312         }
2313
2314         return new_offset;
2315 }
2316
2317 /*
2318  * Computes the linear offset to the base tile and adjusts
2319  * x, y. bytes per pixel is assumed to be a power-of-two.
2320  *
2321  * In the 90/270 rotated case, x and y are assumed
2322  * to be already rotated to match the rotated GTT view, and
2323  * pitch is the tile_height aligned framebuffer height.
2324  *
2325  * This function is used when computing the derived information
2326  * under intel_framebuffer, so using any of that information
2327  * here is not allowed. Anything under drm_framebuffer can be
2328  * used. This is why the user has to pass in the pitch since it
2329  * is specified in the rotated orientation.
2330  */
2331 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2332                                       int *x, int *y,
2333                                       const struct drm_framebuffer *fb, int plane,
2334                                       unsigned int pitch,
2335                                       unsigned int rotation,
2336                                       u32 alignment)
2337 {
2338         uint64_t fb_modifier = fb->modifier;
2339         unsigned int cpp = fb->format->cpp[plane];
2340         u32 offset, offset_aligned;
2341
2342         if (alignment)
2343                 alignment--;
2344
2345         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2346                 unsigned int tile_size, tile_width, tile_height;
2347                 unsigned int tile_rows, tiles, pitch_tiles;
2348
2349                 tile_size = intel_tile_size(dev_priv);
2350                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2351                                 fb_modifier, cpp);
2352
2353                 if (drm_rotation_90_or_270(rotation)) {
2354                         pitch_tiles = pitch / tile_height;
2355                         swap(tile_width, tile_height);
2356                 } else {
2357                         pitch_tiles = pitch / (tile_width * cpp);
2358                 }
2359
2360                 tile_rows = *y / tile_height;
2361                 *y %= tile_height;
2362
2363                 tiles = *x / tile_width;
2364                 *x %= tile_width;
2365
2366                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2367                 offset_aligned = offset & ~alignment;
2368
2369                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2370                                           tile_size, pitch_tiles,
2371                                           offset, offset_aligned);
2372         } else {
2373                 offset = *y * pitch + *x * cpp;
2374                 offset_aligned = offset & ~alignment;
2375
2376                 *y = (offset & alignment) / pitch;
2377                 *x = ((offset & alignment) - *y * pitch) / cpp;
2378         }
2379
2380         return offset_aligned;
2381 }
2382
2383 u32 intel_compute_tile_offset(int *x, int *y,
2384                               const struct intel_plane_state *state,
2385                               int plane)
2386 {
2387         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2388         const struct drm_framebuffer *fb = state->base.fb;
2389         unsigned int rotation = state->base.rotation;
2390         int pitch = intel_fb_pitch(fb, plane, rotation);
2391         u32 alignment;
2392
2393         /* AUX_DIST needs only 4K alignment */
2394         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2395                 alignment = 4096;
2396         else
2397                 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2398
2399         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2400                                           rotation, alignment);
2401 }
2402
2403 /* Convert the fb->offset[] linear offset into x/y offsets */
2404 static void intel_fb_offset_to_xy(int *x, int *y,
2405                                   const struct drm_framebuffer *fb, int plane)
2406 {
2407         unsigned int cpp = fb->format->cpp[plane];
2408         unsigned int pitch = fb->pitches[plane];
2409         u32 linear_offset = fb->offsets[plane];
2410
2411         *y = linear_offset / pitch;
2412         *x = linear_offset % pitch / cpp;
2413 }
2414
2415 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2416 {
2417         switch (fb_modifier) {
2418         case I915_FORMAT_MOD_X_TILED:
2419                 return I915_TILING_X;
2420         case I915_FORMAT_MOD_Y_TILED:
2421                 return I915_TILING_Y;
2422         default:
2423                 return I915_TILING_NONE;
2424         }
2425 }
2426
2427 static int
2428 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2429                    struct drm_framebuffer *fb)
2430 {
2431         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2432         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2433         u32 gtt_offset_rotated = 0;
2434         unsigned int max_size = 0;
2435         int i, num_planes = fb->format->num_planes;
2436         unsigned int tile_size = intel_tile_size(dev_priv);
2437
2438         for (i = 0; i < num_planes; i++) {
2439                 unsigned int width, height;
2440                 unsigned int cpp, size;
2441                 u32 offset;
2442                 int x, y;
2443
2444                 cpp = fb->format->cpp[i];
2445                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2446                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2447
2448                 intel_fb_offset_to_xy(&x, &y, fb, i);
2449
2450                 /*
2451                  * The fence (if used) is aligned to the start of the object
2452                  * so having the framebuffer wrap around across the edge of the
2453                  * fenced region doesn't really work. We have no API to configure
2454                  * the fence start offset within the object (nor could we probably
2455                  * on gen2/3). So it's just easier if we just require that the
2456                  * fb layout agrees with the fence layout. We already check that the
2457                  * fb stride matches the fence stride elsewhere.
2458                  */
2459                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2460                     (x + width) * cpp > fb->pitches[i]) {
2461                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2462                                   i, fb->offsets[i]);
2463                         return -EINVAL;
2464                 }
2465
2466                 /*
2467                  * First pixel of the framebuffer from
2468                  * the start of the normal gtt mapping.
2469                  */
2470                 intel_fb->normal[i].x = x;
2471                 intel_fb->normal[i].y = y;
2472
2473                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2474                                                     fb, 0, fb->pitches[i],
2475                                                     DRM_ROTATE_0, tile_size);
2476                 offset /= tile_size;
2477
2478                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2479                         unsigned int tile_width, tile_height;
2480                         unsigned int pitch_tiles;
2481                         struct drm_rect r;
2482
2483                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2484                                         fb->modifier, cpp);
2485
2486                         rot_info->plane[i].offset = offset;
2487                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2488                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2489                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2490
2491                         intel_fb->rotated[i].pitch =
2492                                 rot_info->plane[i].height * tile_height;
2493
2494                         /* how many tiles does this plane need */
2495                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2496                         /*
2497                          * If the plane isn't horizontally tile aligned,
2498                          * we need one more tile.
2499                          */
2500                         if (x != 0)
2501                                 size++;
2502
2503                         /* rotate the x/y offsets to match the GTT view */
2504                         r.x1 = x;
2505                         r.y1 = y;
2506                         r.x2 = x + width;
2507                         r.y2 = y + height;
2508                         drm_rect_rotate(&r,
2509                                         rot_info->plane[i].width * tile_width,
2510                                         rot_info->plane[i].height * tile_height,
2511                                         DRM_ROTATE_270);
2512                         x = r.x1;
2513                         y = r.y1;
2514
2515                         /* rotate the tile dimensions to match the GTT view */
2516                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2517                         swap(tile_width, tile_height);
2518
2519                         /*
2520                          * We only keep the x/y offsets, so push all of the
2521                          * gtt offset into the x/y offsets.
2522                          */
2523                         _intel_adjust_tile_offset(&x, &y,
2524                                                   tile_width, tile_height,
2525                                                   tile_size, pitch_tiles,
2526                                                   gtt_offset_rotated * tile_size, 0);
2527
2528                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2529
2530                         /*
2531                          * First pixel of the framebuffer from
2532                          * the start of the rotated gtt mapping.
2533                          */
2534                         intel_fb->rotated[i].x = x;
2535                         intel_fb->rotated[i].y = y;
2536                 } else {
2537                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2538                                             x * cpp, tile_size);
2539                 }
2540
2541                 /* how many tiles in total needed in the bo */
2542                 max_size = max(max_size, offset + size);
2543         }
2544
2545         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2546                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2547                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2548                 return -EINVAL;
2549         }
2550
2551         return 0;
2552 }
2553
2554 static int i9xx_format_to_fourcc(int format)
2555 {
2556         switch (format) {
2557         case DISPPLANE_8BPP:
2558                 return DRM_FORMAT_C8;
2559         case DISPPLANE_BGRX555:
2560                 return DRM_FORMAT_XRGB1555;
2561         case DISPPLANE_BGRX565:
2562                 return DRM_FORMAT_RGB565;
2563         default:
2564         case DISPPLANE_BGRX888:
2565                 return DRM_FORMAT_XRGB8888;
2566         case DISPPLANE_RGBX888:
2567                 return DRM_FORMAT_XBGR8888;
2568         case DISPPLANE_BGRX101010:
2569                 return DRM_FORMAT_XRGB2101010;
2570         case DISPPLANE_RGBX101010:
2571                 return DRM_FORMAT_XBGR2101010;
2572         }
2573 }
2574
2575 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2576 {
2577         switch (format) {
2578         case PLANE_CTL_FORMAT_RGB_565:
2579                 return DRM_FORMAT_RGB565;
2580         default:
2581         case PLANE_CTL_FORMAT_XRGB_8888:
2582                 if (rgb_order) {
2583                         if (alpha)
2584                                 return DRM_FORMAT_ABGR8888;
2585                         else
2586                                 return DRM_FORMAT_XBGR8888;
2587                 } else {
2588                         if (alpha)
2589                                 return DRM_FORMAT_ARGB8888;
2590                         else
2591                                 return DRM_FORMAT_XRGB8888;
2592                 }
2593         case PLANE_CTL_FORMAT_XRGB_2101010:
2594                 if (rgb_order)
2595                         return DRM_FORMAT_XBGR2101010;
2596                 else
2597                         return DRM_FORMAT_XRGB2101010;
2598         }
2599 }
2600
2601 static bool
2602 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2603                               struct intel_initial_plane_config *plane_config)
2604 {
2605         struct drm_device *dev = crtc->base.dev;
2606         struct drm_i915_private *dev_priv = to_i915(dev);
2607         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2608         struct drm_i915_gem_object *obj = NULL;
2609         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2610         struct drm_framebuffer *fb = &plane_config->fb->base;
2611         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2612         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2613                                     PAGE_SIZE);
2614
2615         size_aligned -= base_aligned;
2616
2617         if (plane_config->size == 0)
2618                 return false;
2619
2620         /* If the FB is too big, just don't use it since fbdev is not very
2621          * important and we should probably use that space with FBC or other
2622          * features. */
2623         if (size_aligned * 2 > ggtt->stolen_usable_size)
2624                 return false;
2625
2626         mutex_lock(&dev->struct_mutex);
2627         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2628                                                              base_aligned,
2629                                                              base_aligned,
2630                                                              size_aligned);
2631         mutex_unlock(&dev->struct_mutex);
2632         if (!obj)
2633                 return false;
2634
2635         if (plane_config->tiling == I915_TILING_X)
2636                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2637
2638         mode_cmd.pixel_format = fb->format->format;
2639         mode_cmd.width = fb->width;
2640         mode_cmd.height = fb->height;
2641         mode_cmd.pitches[0] = fb->pitches[0];
2642         mode_cmd.modifier[0] = fb->modifier;
2643         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2644
2645         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2646                 DRM_DEBUG_KMS("intel fb init failed\n");
2647                 goto out_unref_obj;
2648         }
2649
2650
2651         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2652         return true;
2653
2654 out_unref_obj:
2655         i915_gem_object_put(obj);
2656         return false;
2657 }
2658
2659 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2660 static void
2661 update_state_fb(struct drm_plane *plane)
2662 {
2663         if (plane->fb == plane->state->fb)
2664                 return;
2665
2666         if (plane->state->fb)
2667                 drm_framebuffer_unreference(plane->state->fb);
2668         plane->state->fb = plane->fb;
2669         if (plane->state->fb)
2670                 drm_framebuffer_reference(plane->state->fb);
2671 }
2672
2673 static void
2674 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2675                         struct intel_plane_state *plane_state,
2676                         bool visible)
2677 {
2678         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2679
2680         plane_state->base.visible = visible;
2681
2682         /* FIXME pre-g4x don't work like this */
2683         if (visible) {
2684                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2685                 crtc_state->active_planes |= BIT(plane->id);
2686         } else {
2687                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2688                 crtc_state->active_planes &= ~BIT(plane->id);
2689         }
2690
2691         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2692                       crtc_state->base.crtc->name,
2693                       crtc_state->active_planes);
2694 }
2695
2696 static void
2697 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2698                              struct intel_initial_plane_config *plane_config)
2699 {
2700         struct drm_device *dev = intel_crtc->base.dev;
2701         struct drm_i915_private *dev_priv = to_i915(dev);
2702         struct drm_crtc *c;
2703         struct drm_i915_gem_object *obj;
2704         struct drm_plane *primary = intel_crtc->base.primary;
2705         struct drm_plane_state *plane_state = primary->state;
2706         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2707         struct intel_plane *intel_plane = to_intel_plane(primary);
2708         struct intel_plane_state *intel_state =
2709                 to_intel_plane_state(plane_state);
2710         struct drm_framebuffer *fb;
2711
2712         if (!plane_config->fb)
2713                 return;
2714
2715         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2716                 fb = &plane_config->fb->base;
2717                 goto valid_fb;
2718         }
2719
2720         kfree(plane_config->fb);
2721
2722         /*
2723          * Failed to alloc the obj, check to see if we should share
2724          * an fb with another CRTC instead
2725          */
2726         for_each_crtc(dev, c) {
2727                 struct intel_plane_state *state;
2728
2729                 if (c == &intel_crtc->base)
2730                         continue;
2731
2732                 if (!to_intel_crtc(c)->active)
2733                         continue;
2734
2735                 state = to_intel_plane_state(c->primary->state);
2736                 if (!state->vma)
2737                         continue;
2738
2739                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2740                         fb = c->primary->fb;
2741                         drm_framebuffer_reference(fb);
2742                         goto valid_fb;
2743                 }
2744         }
2745
2746         /*
2747          * We've failed to reconstruct the BIOS FB.  Current display state
2748          * indicates that the primary plane is visible, but has a NULL FB,
2749          * which will lead to problems later if we don't fix it up.  The
2750          * simplest solution is to just disable the primary plane now and
2751          * pretend the BIOS never had it enabled.
2752          */
2753         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2754                                 to_intel_plane_state(plane_state),
2755                                 false);
2756         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2757         trace_intel_disable_plane(primary, intel_crtc);
2758         intel_plane->disable_plane(primary, &intel_crtc->base);
2759
2760         return;
2761
2762 valid_fb:
2763         mutex_lock(&dev->struct_mutex);
2764         intel_state->vma =
2765                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2766         mutex_unlock(&dev->struct_mutex);
2767         if (IS_ERR(intel_state->vma)) {
2768                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2769                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2770
2771                 intel_state->vma = NULL;
2772                 drm_framebuffer_unreference(fb);
2773                 return;
2774         }
2775
2776         plane_state->src_x = 0;
2777         plane_state->src_y = 0;
2778         plane_state->src_w = fb->width << 16;
2779         plane_state->src_h = fb->height << 16;
2780
2781         plane_state->crtc_x = 0;
2782         plane_state->crtc_y = 0;
2783         plane_state->crtc_w = fb->width;
2784         plane_state->crtc_h = fb->height;
2785
2786         intel_state->base.src = drm_plane_state_src(plane_state);
2787         intel_state->base.dst = drm_plane_state_dest(plane_state);
2788
2789         obj = intel_fb_obj(fb);
2790         if (i915_gem_object_is_tiled(obj))
2791                 dev_priv->preserve_bios_swizzle = true;
2792
2793         drm_framebuffer_reference(fb);
2794         primary->fb = primary->state->fb = fb;
2795         primary->crtc = primary->state->crtc = &intel_crtc->base;
2796
2797         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2798                                 to_intel_plane_state(plane_state),
2799                                 true);
2800
2801         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2802                   &obj->frontbuffer_bits);
2803 }
2804
2805 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2806                                unsigned int rotation)
2807 {
2808         int cpp = fb->format->cpp[plane];
2809
2810         switch (fb->modifier) {
2811         case DRM_FORMAT_MOD_NONE:
2812         case I915_FORMAT_MOD_X_TILED:
2813                 switch (cpp) {
2814                 case 8:
2815                         return 4096;
2816                 case 4:
2817                 case 2:
2818                 case 1:
2819                         return 8192;
2820                 default:
2821                         MISSING_CASE(cpp);
2822                         break;
2823                 }
2824                 break;
2825         case I915_FORMAT_MOD_Y_TILED:
2826         case I915_FORMAT_MOD_Yf_TILED:
2827                 switch (cpp) {
2828                 case 8:
2829                         return 2048;
2830                 case 4:
2831                         return 4096;
2832                 case 2:
2833                 case 1:
2834                         return 8192;
2835                 default:
2836                         MISSING_CASE(cpp);
2837                         break;
2838                 }
2839                 break;
2840         default:
2841                 MISSING_CASE(fb->modifier);
2842         }
2843
2844         return 2048;
2845 }
2846
2847 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2848 {
2849         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2850         const struct drm_framebuffer *fb = plane_state->base.fb;
2851         unsigned int rotation = plane_state->base.rotation;
2852         int x = plane_state->base.src.x1 >> 16;
2853         int y = plane_state->base.src.y1 >> 16;
2854         int w = drm_rect_width(&plane_state->base.src) >> 16;
2855         int h = drm_rect_height(&plane_state->base.src) >> 16;
2856         int max_width = skl_max_plane_width(fb, 0, rotation);
2857         int max_height = 4096;
2858         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2859
2860         if (w > max_width || h > max_height) {
2861                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2862                               w, h, max_width, max_height);
2863                 return -EINVAL;
2864         }
2865
2866         intel_add_fb_offsets(&x, &y, plane_state, 0);
2867         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2868
2869         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2870
2871         /*
2872          * AUX surface offset is specified as the distance from the
2873          * main surface offset, and it must be non-negative. Make
2874          * sure that is what we will get.
2875          */
2876         if (offset > aux_offset)
2877                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2878                                                   offset, aux_offset & ~(alignment - 1));
2879
2880         /*
2881          * When using an X-tiled surface, the plane blows up
2882          * if the x offset + width exceed the stride.
2883          *
2884          * TODO: linear and Y-tiled seem fine, Yf untested,
2885          */
2886         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2887                 int cpp = fb->format->cpp[0];
2888
2889                 while ((x + w) * cpp > fb->pitches[0]) {
2890                         if (offset == 0) {
2891                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2892                                 return -EINVAL;
2893                         }
2894
2895                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2896                                                           offset, offset - alignment);
2897                 }
2898         }
2899
2900         plane_state->main.offset = offset;
2901         plane_state->main.x = x;
2902         plane_state->main.y = y;
2903
2904         return 0;
2905 }
2906
2907 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2908 {
2909         const struct drm_framebuffer *fb = plane_state->base.fb;
2910         unsigned int rotation = plane_state->base.rotation;
2911         int max_width = skl_max_plane_width(fb, 1, rotation);
2912         int max_height = 4096;
2913         int x = plane_state->base.src.x1 >> 17;
2914         int y = plane_state->base.src.y1 >> 17;
2915         int w = drm_rect_width(&plane_state->base.src) >> 17;
2916         int h = drm_rect_height(&plane_state->base.src) >> 17;
2917         u32 offset;
2918
2919         intel_add_fb_offsets(&x, &y, plane_state, 1);
2920         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2921
2922         /* FIXME not quite sure how/if these apply to the chroma plane */
2923         if (w > max_width || h > max_height) {
2924                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2925                               w, h, max_width, max_height);
2926                 return -EINVAL;
2927         }
2928
2929         plane_state->aux.offset = offset;
2930         plane_state->aux.x = x;
2931         plane_state->aux.y = y;
2932
2933         return 0;
2934 }
2935
2936 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2937 {
2938         const struct drm_framebuffer *fb = plane_state->base.fb;
2939         unsigned int rotation = plane_state->base.rotation;
2940         int ret;
2941
2942         if (!plane_state->base.visible)
2943                 return 0;
2944
2945         /* Rotate src coordinates to match rotated GTT view */
2946         if (drm_rotation_90_or_270(rotation))
2947                 drm_rect_rotate(&plane_state->base.src,
2948                                 fb->width << 16, fb->height << 16,
2949                                 DRM_ROTATE_270);
2950
2951         /*
2952          * Handle the AUX surface first since
2953          * the main surface setup depends on it.
2954          */
2955         if (fb->format->format == DRM_FORMAT_NV12) {
2956                 ret = skl_check_nv12_aux_surface(plane_state);
2957                 if (ret)
2958                         return ret;
2959         } else {
2960                 plane_state->aux.offset = ~0xfff;
2961                 plane_state->aux.x = 0;
2962                 plane_state->aux.y = 0;
2963         }
2964
2965         ret = skl_check_main_surface(plane_state);
2966         if (ret)
2967                 return ret;
2968
2969         return 0;
2970 }
2971
2972 static void i9xx_update_primary_plane(struct drm_plane *primary,
2973                                       const struct intel_crtc_state *crtc_state,
2974                                       const struct intel_plane_state *plane_state)
2975 {
2976         struct drm_i915_private *dev_priv = to_i915(primary->dev);
2977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2978         struct drm_framebuffer *fb = plane_state->base.fb;
2979         int plane = intel_crtc->plane;
2980         u32 linear_offset;
2981         u32 dspcntr;
2982         i915_reg_t reg = DSPCNTR(plane);
2983         unsigned int rotation = plane_state->base.rotation;
2984         int x = plane_state->base.src.x1 >> 16;
2985         int y = plane_state->base.src.y1 >> 16;
2986
2987         dspcntr = DISPPLANE_GAMMA_ENABLE;
2988
2989         dspcntr |= DISPLAY_PLANE_ENABLE;
2990
2991         if (INTEL_GEN(dev_priv) < 4) {
2992                 if (intel_crtc->pipe == PIPE_B)
2993                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2994
2995                 /* pipesrc and dspsize control the size that is scaled from,
2996                  * which should always be the user's requested size.
2997                  */
2998                 I915_WRITE(DSPSIZE(plane),
2999                            ((crtc_state->pipe_src_h - 1) << 16) |
3000                            (crtc_state->pipe_src_w - 1));
3001                 I915_WRITE(DSPPOS(plane), 0);
3002         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3003                 I915_WRITE(PRIMSIZE(plane),
3004                            ((crtc_state->pipe_src_h - 1) << 16) |
3005                            (crtc_state->pipe_src_w - 1));
3006                 I915_WRITE(PRIMPOS(plane), 0);
3007                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3008         }
3009
3010         switch (fb->format->format) {
3011         case DRM_FORMAT_C8:
3012                 dspcntr |= DISPPLANE_8BPP;
3013                 break;
3014         case DRM_FORMAT_XRGB1555:
3015                 dspcntr |= DISPPLANE_BGRX555;
3016                 break;
3017         case DRM_FORMAT_RGB565:
3018                 dspcntr |= DISPPLANE_BGRX565;
3019                 break;
3020         case DRM_FORMAT_XRGB8888:
3021                 dspcntr |= DISPPLANE_BGRX888;
3022                 break;
3023         case DRM_FORMAT_XBGR8888:
3024                 dspcntr |= DISPPLANE_RGBX888;
3025                 break;
3026         case DRM_FORMAT_XRGB2101010:
3027                 dspcntr |= DISPPLANE_BGRX101010;
3028                 break;
3029         case DRM_FORMAT_XBGR2101010:
3030                 dspcntr |= DISPPLANE_RGBX101010;
3031                 break;
3032         default:
3033                 BUG();
3034         }
3035
3036         if (INTEL_GEN(dev_priv) >= 4 &&
3037             fb->modifier == I915_FORMAT_MOD_X_TILED)
3038                 dspcntr |= DISPPLANE_TILED;
3039
3040         if (rotation & DRM_ROTATE_180)
3041                 dspcntr |= DISPPLANE_ROTATE_180;
3042
3043         if (rotation & DRM_REFLECT_X)
3044                 dspcntr |= DISPPLANE_MIRROR;
3045
3046         if (IS_G4X(dev_priv))
3047                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3048
3049         intel_add_fb_offsets(&x, &y, plane_state, 0);
3050
3051         if (INTEL_GEN(dev_priv) >= 4)
3052                 intel_crtc->dspaddr_offset =
3053                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3054
3055         if (rotation & DRM_ROTATE_180) {
3056                 x += crtc_state->pipe_src_w - 1;
3057                 y += crtc_state->pipe_src_h - 1;
3058         } else if (rotation & DRM_REFLECT_X) {
3059                 x += crtc_state->pipe_src_w - 1;
3060         }
3061
3062         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3063
3064         if (INTEL_GEN(dev_priv) < 4)
3065                 intel_crtc->dspaddr_offset = linear_offset;
3066
3067         intel_crtc->adjusted_x = x;
3068         intel_crtc->adjusted_y = y;
3069
3070         I915_WRITE(reg, dspcntr);
3071
3072         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3073         if (INTEL_GEN(dev_priv) >= 4) {
3074                 I915_WRITE(DSPSURF(plane),
3075                            intel_plane_ggtt_offset(plane_state) +
3076                            intel_crtc->dspaddr_offset);
3077                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3078                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3079         } else {
3080                 I915_WRITE(DSPADDR(plane),
3081                            intel_plane_ggtt_offset(plane_state) +
3082                            intel_crtc->dspaddr_offset);
3083         }
3084         POSTING_READ(reg);
3085 }
3086
3087 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3088                                        struct drm_crtc *crtc)
3089 {
3090         struct drm_device *dev = crtc->dev;
3091         struct drm_i915_private *dev_priv = to_i915(dev);
3092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3093         int plane = intel_crtc->plane;
3094
3095         I915_WRITE(DSPCNTR(plane), 0);
3096         if (INTEL_INFO(dev_priv)->gen >= 4)
3097                 I915_WRITE(DSPSURF(plane), 0);
3098         else
3099                 I915_WRITE(DSPADDR(plane), 0);
3100         POSTING_READ(DSPCNTR(plane));
3101 }
3102
3103 static void ironlake_update_primary_plane(struct drm_plane *primary,
3104                                           const struct intel_crtc_state *crtc_state,
3105                                           const struct intel_plane_state *plane_state)
3106 {
3107         struct drm_device *dev = primary->dev;
3108         struct drm_i915_private *dev_priv = to_i915(dev);
3109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3110         struct drm_framebuffer *fb = plane_state->base.fb;
3111         int plane = intel_crtc->plane;
3112         u32 linear_offset;
3113         u32 dspcntr;
3114         i915_reg_t reg = DSPCNTR(plane);
3115         unsigned int rotation = plane_state->base.rotation;
3116         int x = plane_state->base.src.x1 >> 16;
3117         int y = plane_state->base.src.y1 >> 16;
3118
3119         dspcntr = DISPPLANE_GAMMA_ENABLE;
3120         dspcntr |= DISPLAY_PLANE_ENABLE;
3121
3122         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3123                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3124
3125         switch (fb->format->format) {
3126         case DRM_FORMAT_C8:
3127                 dspcntr |= DISPPLANE_8BPP;
3128                 break;
3129         case DRM_FORMAT_RGB565:
3130                 dspcntr |= DISPPLANE_BGRX565;
3131                 break;
3132         case DRM_FORMAT_XRGB8888:
3133                 dspcntr |= DISPPLANE_BGRX888;
3134                 break;
3135         case DRM_FORMAT_XBGR8888:
3136                 dspcntr |= DISPPLANE_RGBX888;
3137                 break;
3138         case DRM_FORMAT_XRGB2101010:
3139                 dspcntr |= DISPPLANE_BGRX101010;
3140                 break;
3141         case DRM_FORMAT_XBGR2101010:
3142                 dspcntr |= DISPPLANE_RGBX101010;
3143                 break;
3144         default:
3145                 BUG();
3146         }
3147
3148         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3149                 dspcntr |= DISPPLANE_TILED;
3150
3151         if (rotation & DRM_ROTATE_180)
3152                 dspcntr |= DISPPLANE_ROTATE_180;
3153
3154         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3155                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3156
3157         intel_add_fb_offsets(&x, &y, plane_state, 0);
3158
3159         intel_crtc->dspaddr_offset =
3160                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3161
3162         /* HSW+ does this automagically in hardware */
3163         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3164             rotation & DRM_ROTATE_180) {
3165                 x += crtc_state->pipe_src_w - 1;
3166                 y += crtc_state->pipe_src_h - 1;
3167         }
3168
3169         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3170
3171         intel_crtc->adjusted_x = x;
3172         intel_crtc->adjusted_y = y;
3173
3174         I915_WRITE(reg, dspcntr);
3175
3176         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3177         I915_WRITE(DSPSURF(plane),
3178                    intel_plane_ggtt_offset(plane_state) +
3179                    intel_crtc->dspaddr_offset);
3180         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3181                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3182         } else {
3183                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3184                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3185         }
3186         POSTING_READ(reg);
3187 }
3188
3189 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3190                               uint64_t fb_modifier, uint32_t pixel_format)
3191 {
3192         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3193                 return 64;
3194         } else {
3195                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3196
3197                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3198         }
3199 }
3200
3201 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3202 {
3203         struct drm_device *dev = intel_crtc->base.dev;
3204         struct drm_i915_private *dev_priv = to_i915(dev);
3205
3206         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3207         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3208         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3209 }
3210
3211 /*
3212  * This function detaches (aka. unbinds) unused scalers in hardware
3213  */
3214 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3215 {
3216         struct intel_crtc_scaler_state *scaler_state;
3217         int i;
3218
3219         scaler_state = &intel_crtc->config->scaler_state;
3220
3221         /* loop through and disable scalers that aren't in use */
3222         for (i = 0; i < intel_crtc->num_scalers; i++) {
3223                 if (!scaler_state->scalers[i].in_use)
3224                         skl_detach_scaler(intel_crtc, i);
3225         }
3226 }
3227
3228 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3229                      unsigned int rotation)
3230 {
3231         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3232         u32 stride = intel_fb_pitch(fb, plane, rotation);
3233
3234         /*
3235          * The stride is either expressed as a multiple of 64 bytes chunks for
3236          * linear buffers or in number of tiles for tiled buffers.
3237          */
3238         if (drm_rotation_90_or_270(rotation)) {
3239                 int cpp = fb->format->cpp[plane];
3240
3241                 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3242         } else {
3243                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3244                                                     fb->format->format);
3245         }
3246
3247         return stride;
3248 }
3249
3250 u32 skl_plane_ctl_format(uint32_t pixel_format)
3251 {
3252         switch (pixel_format) {
3253         case DRM_FORMAT_C8:
3254                 return PLANE_CTL_FORMAT_INDEXED;
3255         case DRM_FORMAT_RGB565:
3256                 return PLANE_CTL_FORMAT_RGB_565;
3257         case DRM_FORMAT_XBGR8888:
3258                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3259         case DRM_FORMAT_XRGB8888:
3260                 return PLANE_CTL_FORMAT_XRGB_8888;
3261         /*
3262          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3263          * to be already pre-multiplied. We need to add a knob (or a different
3264          * DRM_FORMAT) for user-space to configure that.
3265          */
3266         case DRM_FORMAT_ABGR8888:
3267                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3268                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3269         case DRM_FORMAT_ARGB8888:
3270                 return PLANE_CTL_FORMAT_XRGB_8888 |
3271                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3272         case DRM_FORMAT_XRGB2101010:
3273                 return PLANE_CTL_FORMAT_XRGB_2101010;
3274         case DRM_FORMAT_XBGR2101010:
3275                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3276         case DRM_FORMAT_YUYV:
3277                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3278         case DRM_FORMAT_YVYU:
3279                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3280         case DRM_FORMAT_UYVY:
3281                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3282         case DRM_FORMAT_VYUY:
3283                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3284         default:
3285                 MISSING_CASE(pixel_format);
3286         }
3287
3288         return 0;
3289 }
3290
3291 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3292 {
3293         switch (fb_modifier) {
3294         case DRM_FORMAT_MOD_NONE:
3295                 break;
3296         case I915_FORMAT_MOD_X_TILED:
3297                 return PLANE_CTL_TILED_X;
3298         case I915_FORMAT_MOD_Y_TILED:
3299                 return PLANE_CTL_TILED_Y;
3300         case I915_FORMAT_MOD_Yf_TILED:
3301                 return PLANE_CTL_TILED_YF;
3302         default:
3303                 MISSING_CASE(fb_modifier);
3304         }
3305
3306         return 0;
3307 }
3308
3309 u32 skl_plane_ctl_rotation(unsigned int rotation)
3310 {
3311         switch (rotation) {
3312         case DRM_ROTATE_0:
3313                 break;
3314         /*
3315          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3316          * while i915 HW rotation is clockwise, thats why this swapping.
3317          */
3318         case DRM_ROTATE_90:
3319                 return PLANE_CTL_ROTATE_270;
3320         case DRM_ROTATE_180:
3321                 return PLANE_CTL_ROTATE_180;
3322         case DRM_ROTATE_270:
3323                 return PLANE_CTL_ROTATE_90;
3324         default:
3325                 MISSING_CASE(rotation);
3326         }
3327
3328         return 0;
3329 }
3330
3331 static void skylake_update_primary_plane(struct drm_plane *plane,
3332                                          const struct intel_crtc_state *crtc_state,
3333                                          const struct intel_plane_state *plane_state)
3334 {
3335         struct drm_device *dev = plane->dev;
3336         struct drm_i915_private *dev_priv = to_i915(dev);
3337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3338         struct drm_framebuffer *fb = plane_state->base.fb;
3339         enum plane_id plane_id = to_intel_plane(plane)->id;
3340         enum pipe pipe = to_intel_plane(plane)->pipe;
3341         u32 plane_ctl;
3342         unsigned int rotation = plane_state->base.rotation;
3343         u32 stride = skl_plane_stride(fb, 0, rotation);
3344         u32 surf_addr = plane_state->main.offset;
3345         int scaler_id = plane_state->scaler_id;
3346         int src_x = plane_state->main.x;
3347         int src_y = plane_state->main.y;
3348         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3349         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3350         int dst_x = plane_state->base.dst.x1;
3351         int dst_y = plane_state->base.dst.y1;
3352         int dst_w = drm_rect_width(&plane_state->base.dst);
3353         int dst_h = drm_rect_height(&plane_state->base.dst);
3354
3355         plane_ctl = PLANE_CTL_ENABLE;
3356
3357         if (IS_GEMINILAKE(dev_priv)) {
3358                 I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
3359                            PLANE_COLOR_PIPE_GAMMA_ENABLE |
3360                            PLANE_COLOR_PIPE_CSC_ENABLE |
3361                            PLANE_COLOR_PLANE_GAMMA_DISABLE);
3362         } else {
3363                 plane_ctl |=
3364                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3365                         PLANE_CTL_PIPE_CSC_ENABLE |
3366                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3367         }
3368
3369         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3370         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3371         plane_ctl |= skl_plane_ctl_rotation(rotation);
3372
3373         /* Sizes are 0 based */
3374         src_w--;
3375         src_h--;
3376         dst_w--;
3377         dst_h--;
3378
3379         intel_crtc->dspaddr_offset = surf_addr;
3380
3381         intel_crtc->adjusted_x = src_x;
3382         intel_crtc->adjusted_y = src_y;
3383
3384         I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
3385         I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3386         I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
3387         I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3388
3389         if (scaler_id >= 0) {
3390                 uint32_t ps_ctrl = 0;
3391
3392                 WARN_ON(!dst_w || !dst_h);
3393                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3394                         crtc_state->scaler_state.scalers[scaler_id].mode;
3395                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3396                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3397                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3398                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3399                 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
3400         } else {
3401                 I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3402         }
3403
3404         I915_WRITE(PLANE_SURF(pipe, plane_id),
3405                    intel_plane_ggtt_offset(plane_state) + surf_addr);
3406
3407         POSTING_READ(PLANE_SURF(pipe, plane_id));
3408 }
3409
3410 static void skylake_disable_primary_plane(struct drm_plane *primary,
3411                                           struct drm_crtc *crtc)
3412 {
3413         struct drm_device *dev = crtc->dev;
3414         struct drm_i915_private *dev_priv = to_i915(dev);
3415         enum plane_id plane_id = to_intel_plane(primary)->id;
3416         enum pipe pipe = to_intel_plane(primary)->pipe;
3417
3418         I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
3419         I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
3420         POSTING_READ(PLANE_SURF(pipe, plane_id));
3421 }
3422
3423 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3424 static int
3425 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3426                            int x, int y, enum mode_set_atomic state)
3427 {
3428         /* Support for kgdboc is disabled, this needs a major rework. */
3429         DRM_ERROR("legacy panic handler not supported any more.\n");
3430
3431         return -ENODEV;
3432 }
3433
3434 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3435 {
3436         struct intel_crtc *crtc;
3437
3438         for_each_intel_crtc(&dev_priv->drm, crtc)
3439                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3440 }
3441
3442 static void intel_update_primary_planes(struct drm_device *dev)
3443 {
3444         struct drm_crtc *crtc;
3445
3446         for_each_crtc(dev, crtc) {
3447                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3448                 struct intel_plane_state *plane_state =
3449                         to_intel_plane_state(plane->base.state);
3450
3451                 if (plane_state->base.visible) {
3452                         trace_intel_update_plane(&plane->base,
3453                                                  to_intel_crtc(crtc));
3454
3455                         plane->update_plane(&plane->base,
3456                                             to_intel_crtc_state(crtc->state),
3457                                             plane_state);
3458                 }
3459         }
3460 }
3461
3462 static int
3463 __intel_display_resume(struct drm_device *dev,
3464                        struct drm_atomic_state *state,
3465                        struct drm_modeset_acquire_ctx *ctx)
3466 {
3467         struct drm_crtc_state *crtc_state;
3468         struct drm_crtc *crtc;
3469         int i, ret;
3470
3471         intel_modeset_setup_hw_state(dev);
3472         i915_redisable_vga(to_i915(dev));
3473
3474         if (!state)
3475                 return 0;
3476
3477         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3478                 /*
3479                  * Force recalculation even if we restore
3480                  * current state. With fast modeset this may not result
3481                  * in a modeset when the state is compatible.
3482                  */
3483                 crtc_state->mode_changed = true;
3484         }
3485
3486         /* ignore any reset values/BIOS leftovers in the WM registers */
3487         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3488                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3489
3490         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3491
3492         WARN_ON(ret == -EDEADLK);
3493         return ret;
3494 }
3495
3496 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3497 {
3498         return intel_has_gpu_reset(dev_priv) &&
3499                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3500 }
3501
3502 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3503 {
3504         struct drm_device *dev = &dev_priv->drm;
3505         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3506         struct drm_atomic_state *state;
3507         int ret;
3508
3509         /*
3510          * Need mode_config.mutex so that we don't
3511          * trample ongoing ->detect() and whatnot.
3512          */
3513         mutex_lock(&dev->mode_config.mutex);
3514         drm_modeset_acquire_init(ctx, 0);
3515         while (1) {
3516                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3517                 if (ret != -EDEADLK)
3518                         break;
3519
3520                 drm_modeset_backoff(ctx);
3521         }
3522
3523         /* reset doesn't touch the display, but flips might get nuked anyway, */
3524         if (!i915.force_reset_modeset_test &&
3525             !gpu_reset_clobbers_display(dev_priv))
3526                 return;
3527
3528         /*
3529          * Disabling the crtcs gracefully seems nicer. Also the
3530          * g33 docs say we should at least disable all the planes.
3531          */
3532         state = drm_atomic_helper_duplicate_state(dev, ctx);
3533         if (IS_ERR(state)) {
3534                 ret = PTR_ERR(state);
3535                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3536                 return;
3537         }
3538
3539         ret = drm_atomic_helper_disable_all(dev, ctx);
3540         if (ret) {
3541                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3542                 drm_atomic_state_put(state);
3543                 return;
3544         }
3545
3546         dev_priv->modeset_restore_state = state;
3547         state->acquire_ctx = ctx;
3548 }
3549
3550 void intel_finish_reset(struct drm_i915_private *dev_priv)
3551 {
3552         struct drm_device *dev = &dev_priv->drm;
3553         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3554         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3555         int ret;
3556
3557         /*
3558          * Flips in the rings will be nuked by the reset,
3559          * so complete all pending flips so that user space
3560          * will get its events and not get stuck.
3561          */
3562         intel_complete_page_flips(dev_priv);
3563
3564         dev_priv->modeset_restore_state = NULL;
3565
3566         /* reset doesn't touch the display */
3567         if (!gpu_reset_clobbers_display(dev_priv)) {
3568                 if (!state) {
3569                         /*
3570                          * Flips in the rings have been nuked by the reset,
3571                          * so update the base address of all primary
3572                          * planes to the the last fb to make sure we're
3573                          * showing the correct fb after a reset.
3574                          *
3575                          * FIXME: Atomic will make this obsolete since we won't schedule
3576                          * CS-based flips (which might get lost in gpu resets) any more.
3577                          */
3578                         intel_update_primary_planes(dev);
3579                 } else {
3580                         ret = __intel_display_resume(dev, state, ctx);
3581                         if (ret)
3582                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3583                 }
3584         } else {
3585                 /*
3586                  * The display has been reset as well,
3587                  * so need a full re-initialization.
3588                  */
3589                 intel_runtime_pm_disable_interrupts(dev_priv);
3590                 intel_runtime_pm_enable_interrupts(dev_priv);
3591
3592                 intel_pps_unlock_regs_wa(dev_priv);
3593                 intel_modeset_init_hw(dev);
3594
3595                 spin_lock_irq(&dev_priv->irq_lock);
3596                 if (dev_priv->display.hpd_irq_setup)
3597                         dev_priv->display.hpd_irq_setup(dev_priv);
3598                 spin_unlock_irq(&dev_priv->irq_lock);
3599
3600                 ret = __intel_display_resume(dev, state, ctx);
3601                 if (ret)
3602                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3603
3604                 intel_hpd_init(dev_priv);
3605         }
3606
3607         if (state)
3608                 drm_atomic_state_put(state);
3609         drm_modeset_drop_locks(ctx);
3610         drm_modeset_acquire_fini(ctx);
3611         mutex_unlock(&dev->mode_config.mutex);
3612 }
3613
3614 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3615 {
3616         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3617
3618         if (i915_reset_in_progress(error))
3619                 return true;
3620
3621         if (crtc->reset_count != i915_reset_count(error))
3622                 return true;
3623
3624         return false;
3625 }
3626
3627 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3628 {
3629         struct drm_device *dev = crtc->dev;
3630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631         bool pending;
3632
3633         if (abort_flip_on_reset(intel_crtc))
3634                 return false;
3635
3636         spin_lock_irq(&dev->event_lock);
3637         pending = to_intel_crtc(crtc)->flip_work != NULL;
3638         spin_unlock_irq(&dev->event_lock);
3639
3640         return pending;
3641 }
3642
3643 static void intel_update_pipe_config(struct intel_crtc *crtc,
3644                                      struct intel_crtc_state *old_crtc_state)
3645 {
3646         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3647         struct intel_crtc_state *pipe_config =
3648                 to_intel_crtc_state(crtc->base.state);
3649
3650         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3651         crtc->base.mode = crtc->base.state->mode;
3652
3653         /*
3654          * Update pipe size and adjust fitter if needed: the reason for this is
3655          * that in compute_mode_changes we check the native mode (not the pfit
3656          * mode) to see if we can flip rather than do a full mode set. In the
3657          * fastboot case, we'll flip, but if we don't update the pipesrc and
3658          * pfit state, we'll end up with a big fb scanned out into the wrong
3659          * sized surface.
3660          */
3661
3662         I915_WRITE(PIPESRC(crtc->pipe),
3663                    ((pipe_config->pipe_src_w - 1) << 16) |
3664                    (pipe_config->pipe_src_h - 1));
3665
3666         /* on skylake this is done by detaching scalers */
3667         if (INTEL_GEN(dev_priv) >= 9) {
3668                 skl_detach_scalers(crtc);
3669
3670                 if (pipe_config->pch_pfit.enabled)
3671                         skylake_pfit_enable(crtc);
3672         } else if (HAS_PCH_SPLIT(dev_priv)) {
3673                 if (pipe_config->pch_pfit.enabled)
3674                         ironlake_pfit_enable(crtc);
3675                 else if (old_crtc_state->pch_pfit.enabled)
3676                         ironlake_pfit_disable(crtc, true);
3677         }
3678 }
3679
3680 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3681 {
3682         struct drm_device *dev = crtc->base.dev;
3683         struct drm_i915_private *dev_priv = to_i915(dev);
3684         int pipe = crtc->pipe;
3685         i915_reg_t reg;
3686         u32 temp;
3687
3688         /* enable normal train */
3689         reg = FDI_TX_CTL(pipe);
3690         temp = I915_READ(reg);
3691         if (IS_IVYBRIDGE(dev_priv)) {
3692                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3693                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3694         } else {
3695                 temp &= ~FDI_LINK_TRAIN_NONE;
3696                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3697         }
3698         I915_WRITE(reg, temp);
3699
3700         reg = FDI_RX_CTL(pipe);
3701         temp = I915_READ(reg);
3702         if (HAS_PCH_CPT(dev_priv)) {
3703                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3704                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3705         } else {
3706                 temp &= ~FDI_LINK_TRAIN_NONE;
3707                 temp |= FDI_LINK_TRAIN_NONE;
3708         }
3709         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3710
3711         /* wait one idle pattern time */
3712         POSTING_READ(reg);
3713         udelay(1000);
3714
3715         /* IVB wants error correction enabled */
3716         if (IS_IVYBRIDGE(dev_priv))
3717                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3718                            FDI_FE_ERRC_ENABLE);
3719 }
3720
3721 /* The FDI link training functions for ILK/Ibexpeak. */
3722 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3723                                     const struct intel_crtc_state *crtc_state)
3724 {
3725         struct drm_device *dev = crtc->base.dev;
3726         struct drm_i915_private *dev_priv = to_i915(dev);
3727         int pipe = crtc->pipe;
3728         i915_reg_t reg;
3729         u32 temp, tries;
3730
3731         /* FDI needs bits from pipe first */
3732         assert_pipe_enabled(dev_priv, pipe);
3733
3734         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3735            for train result */
3736         reg = FDI_RX_IMR(pipe);
3737         temp = I915_READ(reg);
3738         temp &= ~FDI_RX_SYMBOL_LOCK;
3739         temp &= ~FDI_RX_BIT_LOCK;
3740         I915_WRITE(reg, temp);
3741         I915_READ(reg);
3742         udelay(150);
3743
3744         /* enable CPU FDI TX and PCH FDI RX */
3745         reg = FDI_TX_CTL(pipe);
3746         temp = I915_READ(reg);
3747         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3748         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3749         temp &= ~FDI_LINK_TRAIN_NONE;
3750         temp |= FDI_LINK_TRAIN_PATTERN_1;
3751         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3752
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         temp &= ~FDI_LINK_TRAIN_NONE;
3756         temp |= FDI_LINK_TRAIN_PATTERN_1;
3757         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3758
3759         POSTING_READ(reg);
3760         udelay(150);
3761
3762         /* Ironlake workaround, enable clock pointer after FDI enable*/
3763         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3764         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3765                    FDI_RX_PHASE_SYNC_POINTER_EN);
3766
3767         reg = FDI_RX_IIR(pipe);
3768         for (tries = 0; tries < 5; tries++) {
3769                 temp = I915_READ(reg);
3770                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3771
3772                 if ((temp & FDI_RX_BIT_LOCK)) {
3773                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3774                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3775                         break;
3776                 }
3777         }
3778         if (tries == 5)
3779                 DRM_ERROR("FDI train 1 fail!\n");
3780
3781         /* Train 2 */
3782         reg = FDI_TX_CTL(pipe);
3783         temp = I915_READ(reg);
3784         temp &= ~FDI_LINK_TRAIN_NONE;
3785         temp |= FDI_LINK_TRAIN_PATTERN_2;
3786         I915_WRITE(reg, temp);
3787
3788         reg = FDI_RX_CTL(pipe);
3789         temp = I915_READ(reg);
3790         temp &= ~FDI_LINK_TRAIN_NONE;
3791         temp |= FDI_LINK_TRAIN_PATTERN_2;
3792         I915_WRITE(reg, temp);
3793
3794         POSTING_READ(reg);
3795         udelay(150);
3796
3797         reg = FDI_RX_IIR(pipe);
3798         for (tries = 0; tries < 5; tries++) {
3799                 temp = I915_READ(reg);
3800                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3801
3802                 if (temp & FDI_RX_SYMBOL_LOCK) {
3803                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3804                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3805                         break;
3806                 }
3807         }
3808         if (tries == 5)
3809                 DRM_ERROR("FDI train 2 fail!\n");
3810
3811         DRM_DEBUG_KMS("FDI train done\n");
3812
3813 }
3814
3815 static const int snb_b_fdi_train_param[] = {
3816         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3817         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3818         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3819         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3820 };
3821
3822 /* The FDI link training functions for SNB/Cougarpoint. */
3823 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3824                                 const struct intel_crtc_state *crtc_state)
3825 {
3826         struct drm_device *dev = crtc->base.dev;
3827         struct drm_i915_private *dev_priv = to_i915(dev);
3828         int pipe = crtc->pipe;
3829         i915_reg_t reg;
3830         u32 temp, i, retry;
3831
3832         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3833            for train result */
3834         reg = FDI_RX_IMR(pipe);
3835         temp = I915_READ(reg);
3836         temp &= ~FDI_RX_SYMBOL_LOCK;
3837         temp &= ~FDI_RX_BIT_LOCK;
3838         I915_WRITE(reg, temp);
3839
3840         POSTING_READ(reg);
3841         udelay(150);
3842
3843         /* enable CPU FDI TX and PCH FDI RX */
3844         reg = FDI_TX_CTL(pipe);
3845         temp = I915_READ(reg);
3846         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3847         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3848         temp &= ~FDI_LINK_TRAIN_NONE;
3849         temp |= FDI_LINK_TRAIN_PATTERN_1;
3850         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3851         /* SNB-B */
3852         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3853         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3854
3855         I915_WRITE(FDI_RX_MISC(pipe),
3856                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3857
3858         reg = FDI_RX_CTL(pipe);
3859         temp = I915_READ(reg);
3860         if (HAS_PCH_CPT(dev_priv)) {
3861                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3862                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3863         } else {
3864                 temp &= ~FDI_LINK_TRAIN_NONE;
3865                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3866         }
3867         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3868
3869         POSTING_READ(reg);
3870         udelay(150);
3871
3872         for (i = 0; i < 4; i++) {
3873                 reg = FDI_TX_CTL(pipe);
3874                 temp = I915_READ(reg);
3875                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3876                 temp |= snb_b_fdi_train_param[i];
3877                 I915_WRITE(reg, temp);
3878
3879                 POSTING_READ(reg);
3880                 udelay(500);
3881
3882                 for (retry = 0; retry < 5; retry++) {
3883                         reg = FDI_RX_IIR(pipe);
3884                         temp = I915_READ(reg);
3885                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3886                         if (temp & FDI_RX_BIT_LOCK) {
3887                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3888                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3889                                 break;
3890                         }
3891                         udelay(50);
3892                 }
3893                 if (retry < 5)
3894                         break;
3895         }
3896         if (i == 4)
3897                 DRM_ERROR("FDI train 1 fail!\n");
3898
3899         /* Train 2 */
3900         reg = FDI_TX_CTL(pipe);
3901         temp = I915_READ(reg);
3902         temp &= ~FDI_LINK_TRAIN_NONE;
3903         temp |= FDI_LINK_TRAIN_PATTERN_2;
3904         if (IS_GEN6(dev_priv)) {
3905                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3906                 /* SNB-B */
3907                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3908         }
3909         I915_WRITE(reg, temp);
3910
3911         reg = FDI_RX_CTL(pipe);
3912         temp = I915_READ(reg);
3913         if (HAS_PCH_CPT(dev_priv)) {
3914                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3915                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3916         } else {
3917                 temp &= ~FDI_LINK_TRAIN_NONE;
3918                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3919         }
3920         I915_WRITE(reg, temp);
3921
3922         POSTING_READ(reg);
3923         udelay(150);
3924
3925         for (i = 0; i < 4; i++) {
3926                 reg = FDI_TX_CTL(pipe);
3927                 temp = I915_READ(reg);
3928                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3929                 temp |= snb_b_fdi_train_param[i];
3930                 I915_WRITE(reg, temp);
3931
3932                 POSTING_READ(reg);
3933                 udelay(500);
3934
3935                 for (retry = 0; retry < 5; retry++) {
3936                         reg = FDI_RX_IIR(pipe);
3937                         temp = I915_READ(reg);
3938                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3939                         if (temp & FDI_RX_SYMBOL_LOCK) {
3940                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3941                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3942                                 break;
3943                         }
3944                         udelay(50);
3945                 }
3946                 if (retry < 5)
3947                         break;
3948         }
3949         if (i == 4)
3950                 DRM_ERROR("FDI train 2 fail!\n");
3951
3952         DRM_DEBUG_KMS("FDI train done.\n");
3953 }
3954
3955 /* Manual link training for Ivy Bridge A0 parts */
3956 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3957                                       const struct intel_crtc_state *crtc_state)
3958 {
3959         struct drm_device *dev = crtc->base.dev;
3960         struct drm_i915_private *dev_priv = to_i915(dev);
3961         int pipe = crtc->pipe;
3962         i915_reg_t reg;
3963         u32 temp, i, j;
3964
3965         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3966            for train result */
3967         reg = FDI_RX_IMR(pipe);
3968         temp = I915_READ(reg);
3969         temp &= ~FDI_RX_SYMBOL_LOCK;
3970         temp &= ~FDI_RX_BIT_LOCK;
3971         I915_WRITE(reg, temp);
3972
3973         POSTING_READ(reg);
3974         udelay(150);
3975
3976         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3977                       I915_READ(FDI_RX_IIR(pipe)));
3978
3979         /* Try each vswing and preemphasis setting twice before moving on */
3980         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3981                 /* disable first in case we need to retry */
3982                 reg = FDI_TX_CTL(pipe);
3983                 temp = I915_READ(reg);
3984                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3985                 temp &= ~FDI_TX_ENABLE;
3986                 I915_WRITE(reg, temp);
3987
3988                 reg = FDI_RX_CTL(pipe);
3989                 temp = I915_READ(reg);
3990                 temp &= ~FDI_LINK_TRAIN_AUTO;
3991                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3992                 temp &= ~FDI_RX_ENABLE;
3993                 I915_WRITE(reg, temp);
3994
3995                 /* enable CPU FDI TX and PCH FDI RX */
3996                 reg = FDI_TX_CTL(pipe);
3997                 temp = I915_READ(reg);
3998                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3999                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4000                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4001                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4002                 temp |= snb_b_fdi_train_param[j/2];
4003                 temp |= FDI_COMPOSITE_SYNC;
4004                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4005
4006                 I915_WRITE(FDI_RX_MISC(pipe),
4007                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4008
4009                 reg = FDI_RX_CTL(pipe);
4010                 temp = I915_READ(reg);
4011                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4012                 temp |= FDI_COMPOSITE_SYNC;
4013                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4014
4015                 POSTING_READ(reg);
4016                 udelay(1); /* should be 0.5us */
4017
4018                 for (i = 0; i < 4; i++) {
4019                         reg = FDI_RX_IIR(pipe);
4020                         temp = I915_READ(reg);
4021                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4022
4023                         if (temp & FDI_RX_BIT_LOCK ||
4024                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4025                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4026                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4027                                               i);
4028                                 break;
4029                         }
4030                         udelay(1); /* should be 0.5us */
4031                 }
4032                 if (i == 4) {
4033                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4034                         continue;
4035                 }
4036
4037                 /* Train 2 */
4038                 reg = FDI_TX_CTL(pipe);
4039                 temp = I915_READ(reg);
4040                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4041                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4042                 I915_WRITE(reg, temp);
4043
4044                 reg = FDI_RX_CTL(pipe);
4045                 temp = I915_READ(reg);
4046                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4047                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4048                 I915_WRITE(reg, temp);
4049
4050                 POSTING_READ(reg);
4051                 udelay(2); /* should be 1.5us */
4052
4053                 for (i = 0; i < 4; i++) {
4054                         reg = FDI_RX_IIR(pipe);
4055                         temp = I915_READ(reg);
4056                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4057
4058                         if (temp & FDI_RX_SYMBOL_LOCK ||
4059                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4060                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4061                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4062                                               i);
4063                                 goto train_done;
4064                         }
4065                         udelay(2); /* should be 1.5us */
4066                 }
4067                 if (i == 4)
4068                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4069         }
4070
4071 train_done:
4072         DRM_DEBUG_KMS("FDI train done.\n");
4073 }
4074
4075 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4076 {
4077         struct drm_device *dev = intel_crtc->base.dev;
4078         struct drm_i915_private *dev_priv = to_i915(dev);
4079         int pipe = intel_crtc->pipe;
4080         i915_reg_t reg;
4081         u32 temp;
4082
4083         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4084         reg = FDI_RX_CTL(pipe);
4085         temp = I915_READ(reg);
4086         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4087         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4088         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4089         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4090
4091         POSTING_READ(reg);
4092         udelay(200);
4093
4094         /* Switch from Rawclk to PCDclk */
4095         temp = I915_READ(reg);
4096         I915_WRITE(reg, temp | FDI_PCDCLK);
4097
4098         POSTING_READ(reg);
4099         udelay(200);
4100
4101         /* Enable CPU FDI TX PLL, always on for Ironlake */
4102         reg = FDI_TX_CTL(pipe);
4103         temp = I915_READ(reg);
4104         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4105                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4106
4107                 POSTING_READ(reg);
4108                 udelay(100);
4109         }
4110 }
4111
4112 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4113 {
4114         struct drm_device *dev = intel_crtc->base.dev;
4115         struct drm_i915_private *dev_priv = to_i915(dev);
4116         int pipe = intel_crtc->pipe;
4117         i915_reg_t reg;
4118         u32 temp;
4119
4120         /* Switch from PCDclk to Rawclk */
4121         reg = FDI_RX_CTL(pipe);
4122         temp = I915_READ(reg);
4123         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4124
4125         /* Disable CPU FDI TX PLL */
4126         reg = FDI_TX_CTL(pipe);
4127         temp = I915_READ(reg);
4128         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4129
4130         POSTING_READ(reg);
4131         udelay(100);
4132
4133         reg = FDI_RX_CTL(pipe);
4134         temp = I915_READ(reg);
4135         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4136
4137         /* Wait for the clocks to turn off. */
4138         POSTING_READ(reg);
4139         udelay(100);
4140 }
4141
4142 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4143 {
4144         struct drm_device *dev = crtc->dev;
4145         struct drm_i915_private *dev_priv = to_i915(dev);
4146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4147         int pipe = intel_crtc->pipe;
4148         i915_reg_t reg;
4149         u32 temp;
4150
4151         /* disable CPU FDI tx and PCH FDI rx */
4152         reg = FDI_TX_CTL(pipe);
4153         temp = I915_READ(reg);
4154         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4155         POSTING_READ(reg);
4156
4157         reg = FDI_RX_CTL(pipe);
4158         temp = I915_READ(reg);
4159         temp &= ~(0x7 << 16);
4160         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4161         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4162
4163         POSTING_READ(reg);
4164         udelay(100);
4165
4166         /* Ironlake workaround, disable clock pointer after downing FDI */
4167         if (HAS_PCH_IBX(dev_priv))
4168                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4169
4170         /* still set train pattern 1 */
4171         reg = FDI_TX_CTL(pipe);
4172         temp = I915_READ(reg);
4173         temp &= ~FDI_LINK_TRAIN_NONE;
4174         temp |= FDI_LINK_TRAIN_PATTERN_1;
4175         I915_WRITE(reg, temp);
4176
4177         reg = FDI_RX_CTL(pipe);
4178         temp = I915_READ(reg);
4179         if (HAS_PCH_CPT(dev_priv)) {
4180                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4181                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4182         } else {
4183                 temp &= ~FDI_LINK_TRAIN_NONE;
4184                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4185         }
4186         /* BPC in FDI rx is consistent with that in PIPECONF */
4187         temp &= ~(0x07 << 16);
4188         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4189         I915_WRITE(reg, temp);
4190
4191         POSTING_READ(reg);
4192         udelay(100);
4193 }
4194
4195 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4196 {
4197         struct intel_crtc *crtc;
4198
4199         /* Note that we don't need to be called with mode_config.lock here
4200          * as our list of CRTC objects is static for the lifetime of the
4201          * device and so cannot disappear as we iterate. Similarly, we can
4202          * happily treat the predicates as racy, atomic checks as userspace
4203          * cannot claim and pin a new fb without at least acquring the
4204          * struct_mutex and so serialising with us.
4205          */
4206         for_each_intel_crtc(&dev_priv->drm, crtc) {
4207                 if (atomic_read(&crtc->unpin_work_count) == 0)
4208                         continue;
4209
4210                 if (crtc->flip_work)
4211                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4212
4213                 return true;
4214         }
4215
4216         return false;
4217 }
4218
4219 static void page_flip_completed(struct intel_crtc *intel_crtc)
4220 {
4221         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4222         struct intel_flip_work *work = intel_crtc->flip_work;
4223
4224         intel_crtc->flip_work = NULL;
4225
4226         if (work->event)
4227                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4228
4229         drm_crtc_vblank_put(&intel_crtc->base);
4230
4231         wake_up_all(&dev_priv->pending_flip_queue);
4232         trace_i915_flip_complete(intel_crtc->plane,
4233                                  work->pending_flip_obj);
4234
4235         queue_work(dev_priv->wq, &work->unpin_work);
4236 }
4237
4238 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4239 {
4240         struct drm_device *dev = crtc->dev;
4241         struct drm_i915_private *dev_priv = to_i915(dev);
4242         long ret;
4243
4244         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4245
4246         ret = wait_event_interruptible_timeout(
4247                                         dev_priv->pending_flip_queue,
4248                                         !intel_crtc_has_pending_flip(crtc),
4249                                         60*HZ);
4250
4251         if (ret < 0)
4252                 return ret;
4253
4254         if (ret == 0) {
4255                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4256                 struct intel_flip_work *work;
4257
4258                 spin_lock_irq(&dev->event_lock);
4259                 work = intel_crtc->flip_work;
4260                 if (work && !is_mmio_work(work)) {
4261                         WARN_ONCE(1, "Removing stuck page flip\n");
4262                         page_flip_completed(intel_crtc);
4263                 }
4264                 spin_unlock_irq(&dev->event_lock);
4265         }
4266
4267         return 0;
4268 }
4269
4270 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4271 {
4272         u32 temp;
4273
4274         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4275
4276         mutex_lock(&dev_priv->sb_lock);
4277
4278         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4279         temp |= SBI_SSCCTL_DISABLE;
4280         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4281
4282         mutex_unlock(&dev_priv->sb_lock);
4283 }
4284
4285 /* Program iCLKIP clock to the desired frequency */
4286 static void lpt_program_iclkip(struct intel_crtc *crtc)
4287 {
4288         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4289         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4290         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4291         u32 temp;
4292
4293         lpt_disable_iclkip(dev_priv);
4294
4295         /* The iCLK virtual clock root frequency is in MHz,
4296          * but the adjusted_mode->crtc_clock in in KHz. To get the
4297          * divisors, it is necessary to divide one by another, so we
4298          * convert the virtual clock precision to KHz here for higher
4299          * precision.
4300          */
4301         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4302                 u32 iclk_virtual_root_freq = 172800 * 1000;
4303                 u32 iclk_pi_range = 64;
4304                 u32 desired_divisor;
4305
4306                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4307                                                     clock << auxdiv);
4308                 divsel = (desired_divisor / iclk_pi_range) - 2;
4309                 phaseinc = desired_divisor % iclk_pi_range;
4310
4311                 /*
4312                  * Near 20MHz is a corner case which is
4313                  * out of range for the 7-bit divisor
4314                  */
4315                 if (divsel <= 0x7f)
4316                         break;
4317         }
4318
4319         /* This should not happen with any sane values */
4320         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4321                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4322         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4323                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4324
4325         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4326                         clock,
4327                         auxdiv,
4328                         divsel,
4329                         phasedir,
4330                         phaseinc);
4331
4332         mutex_lock(&dev_priv->sb_lock);
4333
4334         /* Program SSCDIVINTPHASE6 */
4335         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4336         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4337         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4338         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4339         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4340         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4341         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4342         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4343
4344         /* Program SSCAUXDIV */
4345         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4346         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4347         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4348         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4349
4350         /* Enable modulator and associated divider */
4351         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4352         temp &= ~SBI_SSCCTL_DISABLE;
4353         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4354
4355         mutex_unlock(&dev_priv->sb_lock);
4356
4357         /* Wait for initialization time */
4358         udelay(24);
4359
4360         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4361 }
4362
4363 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4364 {
4365         u32 divsel, phaseinc, auxdiv;
4366         u32 iclk_virtual_root_freq = 172800 * 1000;
4367         u32 iclk_pi_range = 64;
4368         u32 desired_divisor;
4369         u32 temp;
4370
4371         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4372                 return 0;
4373
4374         mutex_lock(&dev_priv->sb_lock);
4375
4376         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4377         if (temp & SBI_SSCCTL_DISABLE) {
4378                 mutex_unlock(&dev_priv->sb_lock);
4379                 return 0;
4380         }
4381
4382         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4383         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4384                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4385         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4386                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4387
4388         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4389         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4390                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4391
4392         mutex_unlock(&dev_priv->sb_lock);
4393
4394         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4395
4396         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4397                                  desired_divisor << auxdiv);
4398 }
4399
4400 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4401                                                 enum pipe pch_transcoder)
4402 {
4403         struct drm_device *dev = crtc->base.dev;
4404         struct drm_i915_private *dev_priv = to_i915(dev);
4405         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4406
4407         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4408                    I915_READ(HTOTAL(cpu_transcoder)));
4409         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4410                    I915_READ(HBLANK(cpu_transcoder)));
4411         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4412                    I915_READ(HSYNC(cpu_transcoder)));
4413
4414         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4415                    I915_READ(VTOTAL(cpu_transcoder)));
4416         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4417                    I915_READ(VBLANK(cpu_transcoder)));
4418         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4419                    I915_READ(VSYNC(cpu_transcoder)));
4420         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4421                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4422 }
4423
4424 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4425 {
4426         struct drm_i915_private *dev_priv = to_i915(dev);
4427         uint32_t temp;
4428
4429         temp = I915_READ(SOUTH_CHICKEN1);
4430         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4431                 return;
4432
4433         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4434         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4435
4436         temp &= ~FDI_BC_BIFURCATION_SELECT;
4437         if (enable)
4438                 temp |= FDI_BC_BIFURCATION_SELECT;
4439
4440         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4441         I915_WRITE(SOUTH_CHICKEN1, temp);
4442         POSTING_READ(SOUTH_CHICKEN1);
4443 }
4444
4445 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4446 {
4447         struct drm_device *dev = intel_crtc->base.dev;
4448
4449         switch (intel_crtc->pipe) {
4450         case PIPE_A:
4451                 break;
4452         case PIPE_B:
4453                 if (intel_crtc->config->fdi_lanes > 2)
4454                         cpt_set_fdi_bc_bifurcation(dev, false);
4455                 else
4456                         cpt_set_fdi_bc_bifurcation(dev, true);
4457
4458                 break;
4459         case PIPE_C:
4460                 cpt_set_fdi_bc_bifurcation(dev, true);
4461
4462                 break;
4463         default:
4464                 BUG();
4465         }
4466 }
4467
4468 /* Return which DP Port should be selected for Transcoder DP control */
4469 static enum port
4470 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4471 {
4472         struct drm_device *dev = crtc->base.dev;
4473         struct intel_encoder *encoder;
4474
4475         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4476                 if (encoder->type == INTEL_OUTPUT_DP ||
4477                     encoder->type == INTEL_OUTPUT_EDP)
4478                         return enc_to_dig_port(&encoder->base)->port;
4479         }
4480
4481         return -1;
4482 }
4483
4484 /*
4485  * Enable PCH resources required for PCH ports:
4486  *   - PCH PLLs
4487  *   - FDI training & RX/TX
4488  *   - update transcoder timings
4489  *   - DP transcoding bits
4490  *   - transcoder
4491  */
4492 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4493 {
4494         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4495         struct drm_device *dev = crtc->base.dev;
4496         struct drm_i915_private *dev_priv = to_i915(dev);
4497         int pipe = crtc->pipe;
4498         u32 temp;
4499
4500         assert_pch_transcoder_disabled(dev_priv, pipe);
4501
4502         if (IS_IVYBRIDGE(dev_priv))
4503                 ivybridge_update_fdi_bc_bifurcation(crtc);
4504
4505         /* Write the TU size bits before fdi link training, so that error
4506          * detection works. */
4507         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4508                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4509
4510         /* For PCH output, training FDI link */
4511         dev_priv->display.fdi_link_train(crtc, crtc_state);
4512
4513         /* We need to program the right clock selection before writing the pixel
4514          * mutliplier into the DPLL. */
4515         if (HAS_PCH_CPT(dev_priv)) {
4516                 u32 sel;
4517
4518                 temp = I915_READ(PCH_DPLL_SEL);
4519                 temp |= TRANS_DPLL_ENABLE(pipe);
4520                 sel = TRANS_DPLLB_SEL(pipe);
4521                 if (crtc_state->shared_dpll ==
4522                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4523                         temp |= sel;
4524                 else
4525                         temp &= ~sel;
4526                 I915_WRITE(PCH_DPLL_SEL, temp);
4527         }
4528
4529         /* XXX: pch pll's can be enabled any time before we enable the PCH
4530          * transcoder, and we actually should do this to not upset any PCH
4531          * transcoder that already use the clock when we share it.
4532          *
4533          * Note that enable_shared_dpll tries to do the right thing, but
4534          * get_shared_dpll unconditionally resets the pll - we need that to have
4535          * the right LVDS enable sequence. */
4536         intel_enable_shared_dpll(crtc);
4537
4538         /* set transcoder timing, panel must allow it */
4539         assert_panel_unlocked(dev_priv, pipe);
4540         ironlake_pch_transcoder_set_timings(crtc, pipe);
4541
4542         intel_fdi_normal_train(crtc);
4543
4544         /* For PCH DP, enable TRANS_DP_CTL */
4545         if (HAS_PCH_CPT(dev_priv) &&
4546             intel_crtc_has_dp_encoder(crtc_state)) {
4547                 const struct drm_display_mode *adjusted_mode =
4548                         &crtc_state->base.adjusted_mode;
4549                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4550                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4551                 temp = I915_READ(reg);
4552                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4553                           TRANS_DP_SYNC_MASK |
4554                           TRANS_DP_BPC_MASK);
4555                 temp |= TRANS_DP_OUTPUT_ENABLE;
4556                 temp |= bpc << 9; /* same format but at 11:9 */
4557
4558                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4559                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4560                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4561                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4562
4563                 switch (intel_trans_dp_port_sel(crtc)) {
4564                 case PORT_B:
4565                         temp |= TRANS_DP_PORT_SEL_B;
4566                         break;
4567                 case PORT_C:
4568                         temp |= TRANS_DP_PORT_SEL_C;
4569                         break;
4570                 case PORT_D:
4571                         temp |= TRANS_DP_PORT_SEL_D;
4572                         break;
4573                 default:
4574                         BUG();
4575                 }
4576
4577                 I915_WRITE(reg, temp);
4578         }
4579
4580         ironlake_enable_pch_transcoder(dev_priv, pipe);
4581 }
4582
4583 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4584 {
4585         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4586         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4587         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4588
4589         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4590
4591         lpt_program_iclkip(crtc);
4592
4593         /* Set transcoder timing. */
4594         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4595
4596         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4597 }
4598
4599 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4600 {
4601         struct drm_i915_private *dev_priv = to_i915(dev);
4602         i915_reg_t dslreg = PIPEDSL(pipe);
4603         u32 temp;
4604
4605         temp = I915_READ(dslreg);
4606         udelay(500);
4607         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4608                 if (wait_for(I915_READ(dslreg) != temp, 5))
4609                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4610         }
4611 }
4612
4613 static int
4614 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4615                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4616                   int src_w, int src_h, int dst_w, int dst_h)
4617 {
4618         struct intel_crtc_scaler_state *scaler_state =
4619                 &crtc_state->scaler_state;
4620         struct intel_crtc *intel_crtc =
4621                 to_intel_crtc(crtc_state->base.crtc);
4622         int need_scaling;
4623
4624         need_scaling = drm_rotation_90_or_270(rotation) ?
4625                 (src_h != dst_w || src_w != dst_h):
4626                 (src_w != dst_w || src_h != dst_h);
4627
4628         /*
4629          * if plane is being disabled or scaler is no more required or force detach
4630          *  - free scaler binded to this plane/crtc
4631          *  - in order to do this, update crtc->scaler_usage
4632          *
4633          * Here scaler state in crtc_state is set free so that
4634          * scaler can be assigned to other user. Actual register
4635          * update to free the scaler is done in plane/panel-fit programming.
4636          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4637          */
4638         if (force_detach || !need_scaling) {
4639                 if (*scaler_id >= 0) {
4640                         scaler_state->scaler_users &= ~(1 << scaler_user);
4641                         scaler_state->scalers[*scaler_id].in_use = 0;
4642
4643                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4644                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4645                                 intel_crtc->pipe, scaler_user, *scaler_id,
4646                                 scaler_state->scaler_users);
4647                         *scaler_id = -1;
4648                 }
4649                 return 0;
4650         }
4651
4652         /* range checks */
4653         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4654                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4655
4656                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4657                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4658                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4659                         "size is out of scaler range\n",
4660                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4661                 return -EINVAL;
4662         }
4663
4664         /* mark this plane as a scaler user in crtc_state */
4665         scaler_state->scaler_users |= (1 << scaler_user);
4666         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4667                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4668                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4669                 scaler_state->scaler_users);
4670
4671         return 0;
4672 }
4673
4674 /**
4675  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4676  *
4677  * @state: crtc's scaler state
4678  *
4679  * Return
4680  *     0 - scaler_usage updated successfully
4681  *    error - requested scaling cannot be supported or other error condition
4682  */
4683 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4684 {
4685         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4686
4687         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4688                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4689                 state->pipe_src_w, state->pipe_src_h,
4690                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4691 }
4692
4693 /**
4694  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4695  *
4696  * @state: crtc's scaler state
4697  * @plane_state: atomic plane state to update
4698  *
4699  * Return
4700  *     0 - scaler_usage updated successfully
4701  *    error - requested scaling cannot be supported or other error condition
4702  */
4703 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4704                                    struct intel_plane_state *plane_state)
4705 {
4706
4707         struct intel_plane *intel_plane =
4708                 to_intel_plane(plane_state->base.plane);
4709         struct drm_framebuffer *fb = plane_state->base.fb;
4710         int ret;
4711
4712         bool force_detach = !fb || !plane_state->base.visible;
4713
4714         ret = skl_update_scaler(crtc_state, force_detach,
4715                                 drm_plane_index(&intel_plane->base),
4716                                 &plane_state->scaler_id,
4717                                 plane_state->base.rotation,
4718                                 drm_rect_width(&plane_state->base.src) >> 16,
4719                                 drm_rect_height(&plane_state->base.src) >> 16,
4720                                 drm_rect_width(&plane_state->base.dst),
4721                                 drm_rect_height(&plane_state->base.dst));
4722
4723         if (ret || plane_state->scaler_id < 0)
4724                 return ret;
4725
4726         /* check colorkey */
4727         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4728                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4729                               intel_plane->base.base.id,
4730                               intel_plane->base.name);
4731                 return -EINVAL;
4732         }
4733
4734         /* Check src format */
4735         switch (fb->format->format) {
4736         case DRM_FORMAT_RGB565:
4737         case DRM_FORMAT_XBGR8888:
4738         case DRM_FORMAT_XRGB8888:
4739         case DRM_FORMAT_ABGR8888:
4740         case DRM_FORMAT_ARGB8888:
4741         case DRM_FORMAT_XRGB2101010:
4742         case DRM_FORMAT_XBGR2101010:
4743         case DRM_FORMAT_YUYV:
4744         case DRM_FORMAT_YVYU:
4745         case DRM_FORMAT_UYVY:
4746         case DRM_FORMAT_VYUY:
4747                 break;
4748         default:
4749                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4750                               intel_plane->base.base.id, intel_plane->base.name,
4751                               fb->base.id, fb->format->format);
4752                 return -EINVAL;
4753         }
4754
4755         return 0;
4756 }
4757
4758 static void skylake_scaler_disable(struct intel_crtc *crtc)
4759 {
4760         int i;
4761
4762         for (i = 0; i < crtc->num_scalers; i++)
4763                 skl_detach_scaler(crtc, i);
4764 }
4765
4766 static void skylake_pfit_enable(struct intel_crtc *crtc)
4767 {
4768         struct drm_device *dev = crtc->base.dev;
4769         struct drm_i915_private *dev_priv = to_i915(dev);
4770         int pipe = crtc->pipe;
4771         struct intel_crtc_scaler_state *scaler_state =
4772                 &crtc->config->scaler_state;
4773
4774         if (crtc->config->pch_pfit.enabled) {
4775                 int id;
4776
4777                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4778                         return;
4779
4780                 id = scaler_state->scaler_id;
4781                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4782                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4783                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4784                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4785         }
4786 }
4787
4788 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4789 {
4790         struct drm_device *dev = crtc->base.dev;
4791         struct drm_i915_private *dev_priv = to_i915(dev);
4792         int pipe = crtc->pipe;
4793
4794         if (crtc->config->pch_pfit.enabled) {
4795                 /* Force use of hard-coded filter coefficients
4796                  * as some pre-programmed values are broken,
4797                  * e.g. x201.
4798                  */
4799                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4800                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4801                                                  PF_PIPE_SEL_IVB(pipe));
4802                 else
4803                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4804                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4805                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4806         }
4807 }
4808
4809 void hsw_enable_ips(struct intel_crtc *crtc)
4810 {
4811         struct drm_device *dev = crtc->base.dev;
4812         struct drm_i915_private *dev_priv = to_i915(dev);
4813
4814         if (!crtc->config->ips_enabled)
4815                 return;
4816
4817         /*
4818          * We can only enable IPS after we enable a plane and wait for a vblank
4819          * This function is called from post_plane_update, which is run after
4820          * a vblank wait.
4821          */
4822
4823         assert_plane_enabled(dev_priv, crtc->plane);
4824         if (IS_BROADWELL(dev_priv)) {
4825                 mutex_lock(&dev_priv->rps.hw_lock);
4826                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4827                 mutex_unlock(&dev_priv->rps.hw_lock);
4828                 /* Quoting Art Runyan: "its not safe to expect any particular
4829                  * value in IPS_CTL bit 31 after enabling IPS through the
4830                  * mailbox." Moreover, the mailbox may return a bogus state,
4831                  * so we need to just enable it and continue on.
4832                  */
4833         } else {
4834                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4835                 /* The bit only becomes 1 in the next vblank, so this wait here
4836                  * is essentially intel_wait_for_vblank. If we don't have this
4837                  * and don't wait for vblanks until the end of crtc_enable, then
4838                  * the HW state readout code will complain that the expected
4839                  * IPS_CTL value is not the one we read. */
4840                 if (intel_wait_for_register(dev_priv,
4841                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4842                                             50))
4843                         DRM_ERROR("Timed out waiting for IPS enable\n");
4844         }
4845 }
4846
4847 void hsw_disable_ips(struct intel_crtc *crtc)
4848 {
4849         struct drm_device *dev = crtc->base.dev;
4850         struct drm_i915_private *dev_priv = to_i915(dev);
4851
4852         if (!crtc->config->ips_enabled)
4853                 return;
4854
4855         assert_plane_enabled(dev_priv, crtc->plane);
4856         if (IS_BROADWELL(dev_priv)) {
4857                 mutex_lock(&dev_priv->rps.hw_lock);
4858                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4859                 mutex_unlock(&dev_priv->rps.hw_lock);
4860                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4861                 if (intel_wait_for_register(dev_priv,
4862                                             IPS_CTL, IPS_ENABLE, 0,
4863                                             42))
4864                         DRM_ERROR("Timed out waiting for IPS disable\n");
4865         } else {
4866                 I915_WRITE(IPS_CTL, 0);
4867                 POSTING_READ(IPS_CTL);
4868         }
4869
4870         /* We need to wait for a vblank before we can disable the plane. */
4871         intel_wait_for_vblank(dev_priv, crtc->pipe);
4872 }
4873
4874 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4875 {
4876         if (intel_crtc->overlay) {
4877                 struct drm_device *dev = intel_crtc->base.dev;
4878                 struct drm_i915_private *dev_priv = to_i915(dev);
4879
4880                 mutex_lock(&dev->struct_mutex);
4881                 dev_priv->mm.interruptible = false;
4882                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4883                 dev_priv->mm.interruptible = true;
4884                 mutex_unlock(&dev->struct_mutex);
4885         }
4886
4887         /* Let userspace switch the overlay on again. In most cases userspace
4888          * has to recompute where to put it anyway.
4889          */
4890 }
4891
4892 /**
4893  * intel_post_enable_primary - Perform operations after enabling primary plane
4894  * @crtc: the CRTC whose primary plane was just enabled
4895  *
4896  * Performs potentially sleeping operations that must be done after the primary
4897  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4898  * called due to an explicit primary plane update, or due to an implicit
4899  * re-enable that is caused when a sprite plane is updated to no longer
4900  * completely hide the primary plane.
4901  */
4902 static void
4903 intel_post_enable_primary(struct drm_crtc *crtc)
4904 {
4905         struct drm_device *dev = crtc->dev;
4906         struct drm_i915_private *dev_priv = to_i915(dev);
4907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4908         int pipe = intel_crtc->pipe;
4909
4910         /*
4911          * FIXME IPS should be fine as long as one plane is
4912          * enabled, but in practice it seems to have problems
4913          * when going from primary only to sprite only and vice
4914          * versa.
4915          */
4916         hsw_enable_ips(intel_crtc);
4917
4918         /*
4919          * Gen2 reports pipe underruns whenever all planes are disabled.
4920          * So don't enable underrun reporting before at least some planes
4921          * are enabled.
4922          * FIXME: Need to fix the logic to work when we turn off all planes
4923          * but leave the pipe running.
4924          */
4925         if (IS_GEN2(dev_priv))
4926                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4927
4928         /* Underruns don't always raise interrupts, so check manually. */
4929         intel_check_cpu_fifo_underruns(dev_priv);
4930         intel_check_pch_fifo_underruns(dev_priv);
4931 }
4932
4933 /* FIXME move all this to pre_plane_update() with proper state tracking */
4934 static void
4935 intel_pre_disable_primary(struct drm_crtc *crtc)
4936 {
4937         struct drm_device *dev = crtc->dev;
4938         struct drm_i915_private *dev_priv = to_i915(dev);
4939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4940         int pipe = intel_crtc->pipe;
4941
4942         /*
4943          * Gen2 reports pipe underruns whenever all planes are disabled.
4944          * So diasble underrun reporting before all the planes get disabled.
4945          * FIXME: Need to fix the logic to work when we turn off all planes
4946          * but leave the pipe running.
4947          */
4948         if (IS_GEN2(dev_priv))
4949                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4950
4951         /*
4952          * FIXME IPS should be fine as long as one plane is
4953          * enabled, but in practice it seems to have problems
4954          * when going from primary only to sprite only and vice
4955          * versa.
4956          */
4957         hsw_disable_ips(intel_crtc);
4958 }
4959
4960 /* FIXME get rid of this and use pre_plane_update */
4961 static void
4962 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4963 {
4964         struct drm_device *dev = crtc->dev;
4965         struct drm_i915_private *dev_priv = to_i915(dev);
4966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967         int pipe = intel_crtc->pipe;
4968
4969         intel_pre_disable_primary(crtc);
4970
4971         /*
4972          * Vblank time updates from the shadow to live plane control register
4973          * are blocked if the memory self-refresh mode is active at that
4974          * moment. So to make sure the plane gets truly disabled, disable
4975          * first the self-refresh mode. The self-refresh enable bit in turn
4976          * will be checked/applied by the HW only at the next frame start
4977          * event which is after the vblank start event, so we need to have a
4978          * wait-for-vblank between disabling the plane and the pipe.
4979          */
4980         if (HAS_GMCH_DISPLAY(dev_priv) &&
4981             intel_set_memory_cxsr(dev_priv, false))
4982                 intel_wait_for_vblank(dev_priv, pipe);
4983 }
4984
4985 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4986 {
4987         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4988         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4989         struct intel_crtc_state *pipe_config =
4990                 to_intel_crtc_state(crtc->base.state);
4991         struct drm_plane *primary = crtc->base.primary;
4992         struct drm_plane_state *old_pri_state =
4993                 drm_atomic_get_existing_plane_state(old_state, primary);
4994
4995         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4996
4997         if (pipe_config->update_wm_post && pipe_config->base.active)
4998                 intel_update_watermarks(crtc);
4999
5000         if (old_pri_state) {
5001                 struct intel_plane_state *primary_state =
5002                         to_intel_plane_state(primary->state);
5003                 struct intel_plane_state *old_primary_state =
5004                         to_intel_plane_state(old_pri_state);
5005
5006                 intel_fbc_post_update(crtc);
5007
5008                 if (primary_state->base.visible &&
5009                     (needs_modeset(&pipe_config->base) ||
5010                      !old_primary_state->base.visible))
5011                         intel_post_enable_primary(&crtc->base);
5012         }
5013 }
5014
5015 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5016 {
5017         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5018         struct drm_device *dev = crtc->base.dev;
5019         struct drm_i915_private *dev_priv = to_i915(dev);
5020         struct intel_crtc_state *pipe_config =
5021                 to_intel_crtc_state(crtc->base.state);
5022         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5023         struct drm_plane *primary = crtc->base.primary;
5024         struct drm_plane_state *old_pri_state =
5025                 drm_atomic_get_existing_plane_state(old_state, primary);
5026         bool modeset = needs_modeset(&pipe_config->base);
5027         struct intel_atomic_state *old_intel_state =
5028                 to_intel_atomic_state(old_state);
5029
5030         if (old_pri_state) {
5031                 struct intel_plane_state *primary_state =
5032                         to_intel_plane_state(primary->state);
5033                 struct intel_plane_state *old_primary_state =
5034                         to_intel_plane_state(old_pri_state);
5035
5036                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5037
5038                 if (old_primary_state->base.visible &&
5039                     (modeset || !primary_state->base.visible))
5040                         intel_pre_disable_primary(&crtc->base);
5041         }
5042
5043         /*
5044          * Vblank time updates from the shadow to live plane control register
5045          * are blocked if the memory self-refresh mode is active at that
5046          * moment. So to make sure the plane gets truly disabled, disable
5047          * first the self-refresh mode. The self-refresh enable bit in turn
5048          * will be checked/applied by the HW only at the next frame start
5049          * event which is after the vblank start event, so we need to have a
5050          * wait-for-vblank between disabling the plane and the pipe.
5051          */
5052         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5053             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5054                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5055
5056         /*
5057          * IVB workaround: must disable low power watermarks for at least
5058          * one frame before enabling scaling.  LP watermarks can be re-enabled
5059          * when scaling is disabled.
5060          *
5061          * WaCxSRDisabledForSpriteScaling:ivb
5062          */
5063         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5064                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5065
5066         /*
5067          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5068          * watermark programming here.
5069          */
5070         if (needs_modeset(&pipe_config->base))
5071                 return;
5072
5073         /*
5074          * For platforms that support atomic watermarks, program the
5075          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5076          * will be the intermediate values that are safe for both pre- and
5077          * post- vblank; when vblank happens, the 'active' values will be set
5078          * to the final 'target' values and we'll do this again to get the
5079          * optimal watermarks.  For gen9+ platforms, the values we program here
5080          * will be the final target values which will get automatically latched
5081          * at vblank time; no further programming will be necessary.
5082          *
5083          * If a platform hasn't been transitioned to atomic watermarks yet,
5084          * we'll continue to update watermarks the old way, if flags tell
5085          * us to.
5086          */
5087         if (dev_priv->display.initial_watermarks != NULL)
5088                 dev_priv->display.initial_watermarks(old_intel_state,
5089                                                      pipe_config);
5090         else if (pipe_config->update_wm_pre)
5091                 intel_update_watermarks(crtc);
5092 }
5093
5094 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5095 {
5096         struct drm_device *dev = crtc->dev;
5097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5098         struct drm_plane *p;
5099         int pipe = intel_crtc->pipe;
5100
5101         intel_crtc_dpms_overlay_disable(intel_crtc);
5102
5103         drm_for_each_plane_mask(p, dev, plane_mask)
5104                 to_intel_plane(p)->disable_plane(p, crtc);
5105
5106         /*
5107          * FIXME: Once we grow proper nuclear flip support out of this we need
5108          * to compute the mask of flip planes precisely. For the time being
5109          * consider this a flip to a NULL plane.
5110          */
5111         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5112 }
5113
5114 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5115                                           struct intel_crtc_state *crtc_state,
5116                                           struct drm_atomic_state *old_state)
5117 {
5118         struct drm_connector_state *old_conn_state;
5119         struct drm_connector *conn;
5120         int i;
5121
5122         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5123                 struct drm_connector_state *conn_state = conn->state;
5124                 struct intel_encoder *encoder =
5125                         to_intel_encoder(conn_state->best_encoder);
5126
5127                 if (conn_state->crtc != crtc)
5128                         continue;
5129
5130                 if (encoder->pre_pll_enable)
5131                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5132         }
5133 }
5134
5135 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5136                                       struct intel_crtc_state *crtc_state,
5137                                       struct drm_atomic_state *old_state)
5138 {
5139         struct drm_connector_state *old_conn_state;
5140         struct drm_connector *conn;
5141         int i;
5142
5143         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5144                 struct drm_connector_state *conn_state = conn->state;
5145                 struct intel_encoder *encoder =
5146                         to_intel_encoder(conn_state->best_encoder);
5147
5148                 if (conn_state->crtc != crtc)
5149                         continue;
5150
5151                 if (encoder->pre_enable)
5152                         encoder->pre_enable(encoder, crtc_state, conn_state);
5153         }
5154 }
5155
5156 static void intel_encoders_enable(struct drm_crtc *crtc,
5157                                   struct intel_crtc_state *crtc_state,
5158                                   struct drm_atomic_state *old_state)
5159 {
5160         struct drm_connector_state *old_conn_state;
5161         struct drm_connector *conn;
5162         int i;
5163
5164         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5165                 struct drm_connector_state *conn_state = conn->state;
5166                 struct intel_encoder *encoder =
5167                         to_intel_encoder(conn_state->best_encoder);
5168
5169                 if (conn_state->crtc != crtc)
5170                         continue;
5171
5172                 encoder->enable(encoder, crtc_state, conn_state);
5173                 intel_opregion_notify_encoder(encoder, true);
5174         }
5175 }
5176
5177 static void intel_encoders_disable(struct drm_crtc *crtc,
5178                                    struct intel_crtc_state *old_crtc_state,
5179                                    struct drm_atomic_state *old_state)
5180 {
5181         struct drm_connector_state *old_conn_state;
5182         struct drm_connector *conn;
5183         int i;
5184
5185         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5186                 struct intel_encoder *encoder =
5187                         to_intel_encoder(old_conn_state->best_encoder);
5188
5189                 if (old_conn_state->crtc != crtc)
5190                         continue;
5191
5192                 intel_opregion_notify_encoder(encoder, false);
5193                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5194         }
5195 }
5196
5197 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5198                                         struct intel_crtc_state *old_crtc_state,
5199                                         struct drm_atomic_state *old_state)
5200 {
5201         struct drm_connector_state *old_conn_state;
5202         struct drm_connector *conn;
5203         int i;
5204
5205         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5206                 struct intel_encoder *encoder =
5207                         to_intel_encoder(old_conn_state->best_encoder);
5208
5209                 if (old_conn_state->crtc != crtc)
5210                         continue;
5211
5212                 if (encoder->post_disable)
5213                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5214         }
5215 }
5216
5217 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5218                                             struct intel_crtc_state *old_crtc_state,
5219                                             struct drm_atomic_state *old_state)
5220 {
5221         struct drm_connector_state *old_conn_state;
5222         struct drm_connector *conn;
5223         int i;
5224
5225         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5226                 struct intel_encoder *encoder =
5227                         to_intel_encoder(old_conn_state->best_encoder);
5228
5229                 if (old_conn_state->crtc != crtc)
5230                         continue;
5231
5232                 if (encoder->post_pll_disable)
5233                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5234         }
5235 }
5236
5237 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5238                                  struct drm_atomic_state *old_state)
5239 {
5240         struct drm_crtc *crtc = pipe_config->base.crtc;
5241         struct drm_device *dev = crtc->dev;
5242         struct drm_i915_private *dev_priv = to_i915(dev);
5243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5244         int pipe = intel_crtc->pipe;
5245         struct intel_atomic_state *old_intel_state =
5246                 to_intel_atomic_state(old_state);
5247
5248         if (WARN_ON(intel_crtc->active))
5249                 return;
5250
5251         /*
5252          * Sometimes spurious CPU pipe underruns happen during FDI
5253          * training, at least with VGA+HDMI cloning. Suppress them.
5254          *
5255          * On ILK we get an occasional spurious CPU pipe underruns
5256          * between eDP port A enable and vdd enable. Also PCH port
5257          * enable seems to result in the occasional CPU pipe underrun.
5258          *
5259          * Spurious PCH underruns also occur during PCH enabling.
5260          */
5261         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5262                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5263         if (intel_crtc->config->has_pch_encoder)
5264                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5265
5266         if (intel_crtc->config->has_pch_encoder)
5267                 intel_prepare_shared_dpll(intel_crtc);
5268
5269         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5270                 intel_dp_set_m_n(intel_crtc, M1_N1);
5271
5272         intel_set_pipe_timings(intel_crtc);
5273         intel_set_pipe_src_size(intel_crtc);
5274
5275         if (intel_crtc->config->has_pch_encoder) {
5276                 intel_cpu_transcoder_set_m_n(intel_crtc,
5277                                      &intel_crtc->config->fdi_m_n, NULL);
5278         }
5279
5280         ironlake_set_pipeconf(crtc);
5281
5282         intel_crtc->active = true;
5283
5284         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5285
5286         if (intel_crtc->config->has_pch_encoder) {
5287                 /* Note: FDI PLL enabling _must_ be done before we enable the
5288                  * cpu pipes, hence this is separate from all the other fdi/pch
5289                  * enabling. */
5290                 ironlake_fdi_pll_enable(intel_crtc);
5291         } else {
5292                 assert_fdi_tx_disabled(dev_priv, pipe);
5293                 assert_fdi_rx_disabled(dev_priv, pipe);
5294         }
5295
5296         ironlake_pfit_enable(intel_crtc);
5297
5298         /*
5299          * On ILK+ LUT must be loaded before the pipe is running but with
5300          * clocks enabled
5301          */
5302         intel_color_load_luts(&pipe_config->base);
5303
5304         if (dev_priv->display.initial_watermarks != NULL)
5305                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5306         intel_enable_pipe(intel_crtc);
5307
5308         if (intel_crtc->config->has_pch_encoder)
5309                 ironlake_pch_enable(pipe_config);
5310
5311         assert_vblank_disabled(crtc);
5312         drm_crtc_vblank_on(crtc);
5313
5314         intel_encoders_enable(crtc, pipe_config, old_state);
5315
5316         if (HAS_PCH_CPT(dev_priv))
5317                 cpt_verify_modeset(dev, intel_crtc->pipe);
5318
5319         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5320         if (intel_crtc->config->has_pch_encoder)
5321                 intel_wait_for_vblank(dev_priv, pipe);
5322         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5323         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5324 }
5325
5326 /* IPS only exists on ULT machines and is tied to pipe A. */
5327 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5328 {
5329         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5330 }
5331
5332 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5333                                 struct drm_atomic_state *old_state)
5334 {
5335         struct drm_crtc *crtc = pipe_config->base.crtc;
5336         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5338         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5339         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5340         struct intel_atomic_state *old_intel_state =
5341                 to_intel_atomic_state(old_state);
5342
5343         if (WARN_ON(intel_crtc->active))
5344                 return;
5345
5346         if (intel_crtc->config->has_pch_encoder)
5347                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5348                                                       false);
5349
5350         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5351
5352         if (intel_crtc->config->shared_dpll)
5353                 intel_enable_shared_dpll(intel_crtc);
5354
5355         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5356                 intel_dp_set_m_n(intel_crtc, M1_N1);
5357
5358         if (!transcoder_is_dsi(cpu_transcoder))
5359                 intel_set_pipe_timings(intel_crtc);
5360
5361         intel_set_pipe_src_size(intel_crtc);
5362
5363         if (cpu_transcoder != TRANSCODER_EDP &&
5364             !transcoder_is_dsi(cpu_transcoder)) {
5365                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5366                            intel_crtc->config->pixel_multiplier - 1);
5367         }
5368
5369         if (intel_crtc->config->has_pch_encoder) {
5370                 intel_cpu_transcoder_set_m_n(intel_crtc,
5371                                      &intel_crtc->config->fdi_m_n, NULL);
5372         }
5373
5374         if (!transcoder_is_dsi(cpu_transcoder))
5375                 haswell_set_pipeconf(crtc);
5376
5377         haswell_set_pipemisc(crtc);
5378
5379         intel_color_set_csc(&pipe_config->base);
5380
5381         intel_crtc->active = true;
5382
5383         if (intel_crtc->config->has_pch_encoder)
5384                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5385         else
5386                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5387
5388         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5389
5390         if (intel_crtc->config->has_pch_encoder)
5391                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5392
5393         if (!transcoder_is_dsi(cpu_transcoder))
5394                 intel_ddi_enable_pipe_clock(pipe_config);
5395
5396         if (INTEL_GEN(dev_priv) >= 9)
5397                 skylake_pfit_enable(intel_crtc);
5398         else
5399                 ironlake_pfit_enable(intel_crtc);
5400
5401         /*
5402          * On ILK+ LUT must be loaded before the pipe is running but with
5403          * clocks enabled
5404          */
5405         intel_color_load_luts(&pipe_config->base);
5406
5407         intel_ddi_set_pipe_settings(pipe_config);
5408         if (!transcoder_is_dsi(cpu_transcoder))
5409                 intel_ddi_enable_transcoder_func(pipe_config);
5410
5411         if (dev_priv->display.initial_watermarks != NULL)
5412                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5413
5414         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5415         if (!transcoder_is_dsi(cpu_transcoder))
5416                 intel_enable_pipe(intel_crtc);
5417
5418         if (intel_crtc->config->has_pch_encoder)
5419                 lpt_pch_enable(pipe_config);
5420
5421         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5422                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5423
5424         assert_vblank_disabled(crtc);
5425         drm_crtc_vblank_on(crtc);
5426
5427         intel_encoders_enable(crtc, pipe_config, old_state);
5428
5429         if (intel_crtc->config->has_pch_encoder) {
5430                 intel_wait_for_vblank(dev_priv, pipe);
5431                 intel_wait_for_vblank(dev_priv, pipe);
5432                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5433                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5434                                                       true);
5435         }
5436
5437         /* If we change the relative order between pipe/planes enabling, we need
5438          * to change the workaround. */
5439         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5440         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5441                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5442                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5443         }
5444 }
5445
5446 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5447 {
5448         struct drm_device *dev = crtc->base.dev;
5449         struct drm_i915_private *dev_priv = to_i915(dev);
5450         int pipe = crtc->pipe;
5451
5452         /* To avoid upsetting the power well on haswell only disable the pfit if
5453          * it's in use. The hw state code will make sure we get this right. */
5454         if (force || crtc->config->pch_pfit.enabled) {
5455                 I915_WRITE(PF_CTL(pipe), 0);
5456                 I915_WRITE(PF_WIN_POS(pipe), 0);
5457                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5458         }
5459 }
5460
5461 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5462                                   struct drm_atomic_state *old_state)
5463 {
5464         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5465         struct drm_device *dev = crtc->dev;
5466         struct drm_i915_private *dev_priv = to_i915(dev);
5467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5468         int pipe = intel_crtc->pipe;
5469
5470         /*
5471          * Sometimes spurious CPU pipe underruns happen when the
5472          * pipe is already disabled, but FDI RX/TX is still enabled.
5473          * Happens at least with VGA+HDMI cloning. Suppress them.
5474          */
5475         if (intel_crtc->config->has_pch_encoder) {
5476                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5477                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5478         }
5479
5480         intel_encoders_disable(crtc, old_crtc_state, old_state);
5481
5482         drm_crtc_vblank_off(crtc);
5483         assert_vblank_disabled(crtc);
5484
5485         intel_disable_pipe(intel_crtc);
5486
5487         ironlake_pfit_disable(intel_crtc, false);
5488
5489         if (intel_crtc->config->has_pch_encoder)
5490                 ironlake_fdi_disable(crtc);
5491
5492         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5493
5494         if (intel_crtc->config->has_pch_encoder) {
5495                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5496
5497                 if (HAS_PCH_CPT(dev_priv)) {
5498                         i915_reg_t reg;
5499                         u32 temp;
5500
5501                         /* disable TRANS_DP_CTL */
5502                         reg = TRANS_DP_CTL(pipe);
5503                         temp = I915_READ(reg);
5504                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5505                                   TRANS_DP_PORT_SEL_MASK);
5506                         temp |= TRANS_DP_PORT_SEL_NONE;
5507                         I915_WRITE(reg, temp);
5508
5509                         /* disable DPLL_SEL */
5510                         temp = I915_READ(PCH_DPLL_SEL);
5511                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5512                         I915_WRITE(PCH_DPLL_SEL, temp);
5513                 }
5514
5515                 ironlake_fdi_pll_disable(intel_crtc);
5516         }
5517
5518         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5519         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5520 }
5521
5522 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5523                                  struct drm_atomic_state *old_state)
5524 {
5525         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5526         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5528         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5529
5530         if (intel_crtc->config->has_pch_encoder)
5531                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5532                                                       false);
5533
5534         intel_encoders_disable(crtc, old_crtc_state, old_state);
5535
5536         drm_crtc_vblank_off(crtc);
5537         assert_vblank_disabled(crtc);
5538
5539         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5540         if (!transcoder_is_dsi(cpu_transcoder))
5541                 intel_disable_pipe(intel_crtc);
5542
5543         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5544                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5545
5546         if (!transcoder_is_dsi(cpu_transcoder))
5547                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5548
5549         if (INTEL_GEN(dev_priv) >= 9)
5550                 skylake_scaler_disable(intel_crtc);
5551         else
5552                 ironlake_pfit_disable(intel_crtc, false);
5553
5554         if (!transcoder_is_dsi(cpu_transcoder))
5555                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5556
5557         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5558
5559         if (old_crtc_state->has_pch_encoder)
5560                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5561                                                       true);
5562 }
5563
5564 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5565 {
5566         struct drm_device *dev = crtc->base.dev;
5567         struct drm_i915_private *dev_priv = to_i915(dev);
5568         struct intel_crtc_state *pipe_config = crtc->config;
5569
5570         if (!pipe_config->gmch_pfit.control)
5571                 return;
5572
5573         /*
5574          * The panel fitter should only be adjusted whilst the pipe is disabled,
5575          * according to register description and PRM.
5576          */
5577         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5578         assert_pipe_disabled(dev_priv, crtc->pipe);
5579
5580         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5581         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5582
5583         /* Border color in case we don't scale up to the full screen. Black by
5584          * default, change to something else for debugging. */
5585         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5586 }
5587
5588 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5589 {
5590         switch (port) {
5591         case PORT_A:
5592                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5593         case PORT_B:
5594                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5595         case PORT_C:
5596                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5597         case PORT_D:
5598                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5599         case PORT_E:
5600                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5601         default:
5602                 MISSING_CASE(port);
5603                 return POWER_DOMAIN_PORT_OTHER;
5604         }
5605 }
5606
5607 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5608                                   struct intel_crtc_state *crtc_state)
5609 {
5610         struct drm_device *dev = crtc->dev;
5611         struct drm_i915_private *dev_priv = to_i915(dev);
5612         struct drm_encoder *encoder;
5613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5614         enum pipe pipe = intel_crtc->pipe;
5615         u64 mask;
5616         enum transcoder transcoder = crtc_state->cpu_transcoder;
5617
5618         if (!crtc_state->base.active)
5619                 return 0;
5620
5621         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5622         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5623         if (crtc_state->pch_pfit.enabled ||
5624             crtc_state->pch_pfit.force_thru)
5625                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5626
5627         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5628                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5629
5630                 mask |= BIT_ULL(intel_encoder->power_domain);
5631         }
5632
5633         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5634                 mask |= BIT(POWER_DOMAIN_AUDIO);
5635
5636         if (crtc_state->shared_dpll)
5637                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5638
5639         return mask;
5640 }
5641
5642 static u64
5643 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5644                                struct intel_crtc_state *crtc_state)
5645 {
5646         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5648         enum intel_display_power_domain domain;
5649         u64 domains, new_domains, old_domains;
5650
5651         old_domains = intel_crtc->enabled_power_domains;
5652         intel_crtc->enabled_power_domains = new_domains =
5653                 get_crtc_power_domains(crtc, crtc_state);
5654
5655         domains = new_domains & ~old_domains;
5656
5657         for_each_power_domain(domain, domains)
5658                 intel_display_power_get(dev_priv, domain);
5659
5660         return old_domains & ~new_domains;
5661 }
5662
5663 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5664                                       u64 domains)
5665 {
5666         enum intel_display_power_domain domain;
5667
5668         for_each_power_domain(domain, domains)
5669                 intel_display_power_put(dev_priv, domain);
5670 }
5671
5672 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5673                                    struct drm_atomic_state *old_state)
5674 {
5675         struct intel_atomic_state *old_intel_state =
5676                 to_intel_atomic_state(old_state);
5677         struct drm_crtc *crtc = pipe_config->base.crtc;
5678         struct drm_device *dev = crtc->dev;
5679         struct drm_i915_private *dev_priv = to_i915(dev);
5680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5681         int pipe = intel_crtc->pipe;
5682
5683         if (WARN_ON(intel_crtc->active))
5684                 return;
5685
5686         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5687                 intel_dp_set_m_n(intel_crtc, M1_N1);
5688
5689         intel_set_pipe_timings(intel_crtc);
5690         intel_set_pipe_src_size(intel_crtc);
5691
5692         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5693                 struct drm_i915_private *dev_priv = to_i915(dev);
5694
5695                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5696                 I915_WRITE(CHV_CANVAS(pipe), 0);
5697         }
5698
5699         i9xx_set_pipeconf(intel_crtc);
5700
5701         intel_crtc->active = true;
5702
5703         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5704
5705         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5706
5707         if (IS_CHERRYVIEW(dev_priv)) {
5708                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5709                 chv_enable_pll(intel_crtc, intel_crtc->config);
5710         } else {
5711                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5712                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5713         }
5714
5715         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5716
5717         i9xx_pfit_enable(intel_crtc);
5718
5719         intel_color_load_luts(&pipe_config->base);
5720
5721         dev_priv->display.initial_watermarks(old_intel_state,
5722                                              pipe_config);
5723         intel_enable_pipe(intel_crtc);
5724
5725         assert_vblank_disabled(crtc);
5726         drm_crtc_vblank_on(crtc);
5727
5728         intel_encoders_enable(crtc, pipe_config, old_state);
5729 }
5730
5731 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5732 {
5733         struct drm_device *dev = crtc->base.dev;
5734         struct drm_i915_private *dev_priv = to_i915(dev);
5735
5736         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5737         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5738 }
5739
5740 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5741                              struct drm_atomic_state *old_state)
5742 {
5743         struct drm_crtc *crtc = pipe_config->base.crtc;
5744         struct drm_device *dev = crtc->dev;
5745         struct drm_i915_private *dev_priv = to_i915(dev);
5746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5747         enum pipe pipe = intel_crtc->pipe;
5748
5749         if (WARN_ON(intel_crtc->active))
5750                 return;
5751
5752         i9xx_set_pll_dividers(intel_crtc);
5753
5754         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5755                 intel_dp_set_m_n(intel_crtc, M1_N1);
5756
5757         intel_set_pipe_timings(intel_crtc);
5758         intel_set_pipe_src_size(intel_crtc);
5759
5760         i9xx_set_pipeconf(intel_crtc);
5761
5762         intel_crtc->active = true;
5763
5764         if (!IS_GEN2(dev_priv))
5765                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5766
5767         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5768
5769         i9xx_enable_pll(intel_crtc);
5770
5771         i9xx_pfit_enable(intel_crtc);
5772
5773         intel_color_load_luts(&pipe_config->base);
5774
5775         intel_update_watermarks(intel_crtc);
5776         intel_enable_pipe(intel_crtc);
5777
5778         assert_vblank_disabled(crtc);
5779         drm_crtc_vblank_on(crtc);
5780
5781         intel_encoders_enable(crtc, pipe_config, old_state);
5782 }
5783
5784 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5785 {
5786         struct drm_device *dev = crtc->base.dev;
5787         struct drm_i915_private *dev_priv = to_i915(dev);
5788
5789         if (!crtc->config->gmch_pfit.control)
5790                 return;
5791
5792         assert_pipe_disabled(dev_priv, crtc->pipe);
5793
5794         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5795                          I915_READ(PFIT_CONTROL));
5796         I915_WRITE(PFIT_CONTROL, 0);
5797 }
5798
5799 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5800                               struct drm_atomic_state *old_state)
5801 {
5802         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5803         struct drm_device *dev = crtc->dev;
5804         struct drm_i915_private *dev_priv = to_i915(dev);
5805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5806         int pipe = intel_crtc->pipe;
5807
5808         /*
5809          * On gen2 planes are double buffered but the pipe isn't, so we must
5810          * wait for planes to fully turn off before disabling the pipe.
5811          */
5812         if (IS_GEN2(dev_priv))
5813                 intel_wait_for_vblank(dev_priv, pipe);
5814
5815         intel_encoders_disable(crtc, old_crtc_state, old_state);
5816
5817         drm_crtc_vblank_off(crtc);
5818         assert_vblank_disabled(crtc);
5819
5820         intel_disable_pipe(intel_crtc);
5821
5822         i9xx_pfit_disable(intel_crtc);
5823
5824         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5825
5826         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5827                 if (IS_CHERRYVIEW(dev_priv))
5828                         chv_disable_pll(dev_priv, pipe);
5829                 else if (IS_VALLEYVIEW(dev_priv))
5830                         vlv_disable_pll(dev_priv, pipe);
5831                 else
5832                         i9xx_disable_pll(intel_crtc);
5833         }
5834
5835         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5836
5837         if (!IS_GEN2(dev_priv))
5838                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5839
5840         if (!dev_priv->display.initial_watermarks)
5841                 intel_update_watermarks(intel_crtc);
5842 }
5843
5844 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5845 {
5846         struct intel_encoder *encoder;
5847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5848         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5849         enum intel_display_power_domain domain;
5850         u64 domains;
5851         struct drm_atomic_state *state;
5852         struct intel_crtc_state *crtc_state;
5853         int ret;
5854
5855         if (!intel_crtc->active)
5856                 return;
5857
5858         if (crtc->primary->state->visible) {
5859                 WARN_ON(intel_crtc->flip_work);
5860
5861                 intel_pre_disable_primary_noatomic(crtc);
5862
5863                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5864                 crtc->primary->state->visible = false;
5865         }
5866
5867         state = drm_atomic_state_alloc(crtc->dev);
5868         if (!state) {
5869                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5870                               crtc->base.id, crtc->name);
5871                 return;
5872         }
5873
5874         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5875
5876         /* Everything's already locked, -EDEADLK can't happen. */
5877         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5878         ret = drm_atomic_add_affected_connectors(state, crtc);
5879
5880         WARN_ON(IS_ERR(crtc_state) || ret);
5881
5882         dev_priv->display.crtc_disable(crtc_state, state);
5883
5884         drm_atomic_state_put(state);
5885
5886         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5887                       crtc->base.id, crtc->name);
5888
5889         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5890         crtc->state->active = false;
5891         intel_crtc->active = false;
5892         crtc->enabled = false;
5893         crtc->state->connector_mask = 0;
5894         crtc->state->encoder_mask = 0;
5895
5896         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5897                 encoder->base.crtc = NULL;
5898
5899         intel_fbc_disable(intel_crtc);
5900         intel_update_watermarks(intel_crtc);
5901         intel_disable_shared_dpll(intel_crtc);
5902
5903         domains = intel_crtc->enabled_power_domains;
5904         for_each_power_domain(domain, domains)
5905                 intel_display_power_put(dev_priv, domain);
5906         intel_crtc->enabled_power_domains = 0;
5907
5908         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5909         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5910 }
5911
5912 /*
5913  * turn all crtc's off, but do not adjust state
5914  * This has to be paired with a call to intel_modeset_setup_hw_state.
5915  */
5916 int intel_display_suspend(struct drm_device *dev)
5917 {
5918         struct drm_i915_private *dev_priv = to_i915(dev);
5919         struct drm_atomic_state *state;
5920         int ret;
5921
5922         state = drm_atomic_helper_suspend(dev);
5923         ret = PTR_ERR_OR_ZERO(state);
5924         if (ret)
5925                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5926         else
5927                 dev_priv->modeset_restore_state = state;
5928         return ret;
5929 }
5930
5931 void intel_encoder_destroy(struct drm_encoder *encoder)
5932 {
5933         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5934
5935         drm_encoder_cleanup(encoder);
5936         kfree(intel_encoder);
5937 }
5938
5939 /* Cross check the actual hw state with our own modeset state tracking (and it's
5940  * internal consistency). */
5941 static void intel_connector_verify_state(struct intel_connector *connector)
5942 {
5943         struct drm_crtc *crtc = connector->base.state->crtc;
5944
5945         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5946                       connector->base.base.id,
5947                       connector->base.name);
5948
5949         if (connector->get_hw_state(connector)) {
5950                 struct intel_encoder *encoder = connector->encoder;
5951                 struct drm_connector_state *conn_state = connector->base.state;
5952
5953                 I915_STATE_WARN(!crtc,
5954                          "connector enabled without attached crtc\n");
5955
5956                 if (!crtc)
5957                         return;
5958
5959                 I915_STATE_WARN(!crtc->state->active,
5960                       "connector is active, but attached crtc isn't\n");
5961
5962                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5963                         return;
5964
5965                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5966                         "atomic encoder doesn't match attached encoder\n");
5967
5968                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5969                         "attached encoder crtc differs from connector crtc\n");
5970         } else {
5971                 I915_STATE_WARN(crtc && crtc->state->active,
5972                         "attached crtc is active, but connector isn't\n");
5973                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
5974                         "best encoder set without crtc!\n");
5975         }
5976 }
5977
5978 int intel_connector_init(struct intel_connector *connector)
5979 {
5980         drm_atomic_helper_connector_reset(&connector->base);
5981
5982         if (!connector->base.state)
5983                 return -ENOMEM;
5984
5985         return 0;
5986 }
5987
5988 struct intel_connector *intel_connector_alloc(void)
5989 {
5990         struct intel_connector *connector;
5991
5992         connector = kzalloc(sizeof *connector, GFP_KERNEL);
5993         if (!connector)
5994                 return NULL;
5995
5996         if (intel_connector_init(connector) < 0) {
5997                 kfree(connector);
5998                 return NULL;
5999         }
6000
6001         return connector;
6002 }
6003
6004 /* Simple connector->get_hw_state implementation for encoders that support only
6005  * one connector and no cloning and hence the encoder state determines the state
6006  * of the connector. */
6007 bool intel_connector_get_hw_state(struct intel_connector *connector)
6008 {
6009         enum pipe pipe = 0;
6010         struct intel_encoder *encoder = connector->encoder;
6011
6012         return encoder->get_hw_state(encoder, &pipe);
6013 }
6014
6015 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6016 {
6017         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6018                 return crtc_state->fdi_lanes;
6019
6020         return 0;
6021 }
6022
6023 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6024                                      struct intel_crtc_state *pipe_config)
6025 {
6026         struct drm_i915_private *dev_priv = to_i915(dev);
6027         struct drm_atomic_state *state = pipe_config->base.state;
6028         struct intel_crtc *other_crtc;
6029         struct intel_crtc_state *other_crtc_state;
6030
6031         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6032                       pipe_name(pipe), pipe_config->fdi_lanes);
6033         if (pipe_config->fdi_lanes > 4) {
6034                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6035                               pipe_name(pipe), pipe_config->fdi_lanes);
6036                 return -EINVAL;
6037         }
6038
6039         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6040                 if (pipe_config->fdi_lanes > 2) {
6041                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6042                                       pipe_config->fdi_lanes);
6043                         return -EINVAL;
6044                 } else {
6045                         return 0;
6046                 }
6047         }
6048
6049         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6050                 return 0;
6051
6052         /* Ivybridge 3 pipe is really complicated */
6053         switch (pipe) {
6054         case PIPE_A:
6055                 return 0;
6056         case PIPE_B:
6057                 if (pipe_config->fdi_lanes <= 2)
6058                         return 0;
6059
6060                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6061                 other_crtc_state =
6062                         intel_atomic_get_crtc_state(state, other_crtc);
6063                 if (IS_ERR(other_crtc_state))
6064                         return PTR_ERR(other_crtc_state);
6065
6066                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6067                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6068                                       pipe_name(pipe), pipe_config->fdi_lanes);
6069                         return -EINVAL;
6070                 }
6071                 return 0;
6072         case PIPE_C:
6073                 if (pipe_config->fdi_lanes > 2) {
6074                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6075                                       pipe_name(pipe), pipe_config->fdi_lanes);
6076                         return -EINVAL;
6077                 }
6078
6079                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6080                 other_crtc_state =
6081                         intel_atomic_get_crtc_state(state, other_crtc);
6082                 if (IS_ERR(other_crtc_state))
6083                         return PTR_ERR(other_crtc_state);
6084
6085                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6086                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6087                         return -EINVAL;
6088                 }
6089                 return 0;
6090         default:
6091                 BUG();
6092         }
6093 }
6094
6095 #define RETRY 1
6096 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6097                                        struct intel_crtc_state *pipe_config)
6098 {
6099         struct drm_device *dev = intel_crtc->base.dev;
6100         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6101         int lane, link_bw, fdi_dotclock, ret;
6102         bool needs_recompute = false;
6103
6104 retry:
6105         /* FDI is a binary signal running at ~2.7GHz, encoding
6106          * each output octet as 10 bits. The actual frequency
6107          * is stored as a divider into a 100MHz clock, and the
6108          * mode pixel clock is stored in units of 1KHz.
6109          * Hence the bw of each lane in terms of the mode signal
6110          * is:
6111          */
6112         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6113
6114         fdi_dotclock = adjusted_mode->crtc_clock;
6115
6116         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6117                                            pipe_config->pipe_bpp);
6118
6119         pipe_config->fdi_lanes = lane;
6120
6121         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6122                                link_bw, &pipe_config->fdi_m_n);
6123
6124         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6125         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6126                 pipe_config->pipe_bpp -= 2*3;
6127                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6128                               pipe_config->pipe_bpp);
6129                 needs_recompute = true;
6130                 pipe_config->bw_constrained = true;
6131
6132                 goto retry;
6133         }
6134
6135         if (needs_recompute)
6136                 return RETRY;
6137
6138         return ret;
6139 }
6140
6141 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6142                                      struct intel_crtc_state *pipe_config)
6143 {
6144         if (pipe_config->pipe_bpp > 24)
6145                 return false;
6146
6147         /* HSW can handle pixel rate up to cdclk? */
6148         if (IS_HASWELL(dev_priv))
6149                 return true;
6150
6151         /*
6152          * We compare against max which means we must take
6153          * the increased cdclk requirement into account when
6154          * calculating the new cdclk.
6155          *
6156          * Should measure whether using a lower cdclk w/o IPS
6157          */
6158         return pipe_config->pixel_rate <=
6159                 dev_priv->max_cdclk_freq * 95 / 100;
6160 }
6161
6162 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6163                                    struct intel_crtc_state *pipe_config)
6164 {
6165         struct drm_device *dev = crtc->base.dev;
6166         struct drm_i915_private *dev_priv = to_i915(dev);
6167
6168         pipe_config->ips_enabled = i915.enable_ips &&
6169                 hsw_crtc_supports_ips(crtc) &&
6170                 pipe_config_supports_ips(dev_priv, pipe_config);
6171 }
6172
6173 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6174 {
6175         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6176
6177         /* GDG double wide on either pipe, otherwise pipe A only */
6178         return INTEL_INFO(dev_priv)->gen < 4 &&
6179                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6180 }
6181
6182 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6183 {
6184         uint32_t pixel_rate;
6185
6186         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6187
6188         /*
6189          * We only use IF-ID interlacing. If we ever use
6190          * PF-ID we'll need to adjust the pixel_rate here.
6191          */
6192
6193         if (pipe_config->pch_pfit.enabled) {
6194                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6195                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6196
6197                 pipe_w = pipe_config->pipe_src_w;
6198                 pipe_h = pipe_config->pipe_src_h;
6199
6200                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6201                 pfit_h = pfit_size & 0xFFFF;
6202                 if (pipe_w < pfit_w)
6203                         pipe_w = pfit_w;
6204                 if (pipe_h < pfit_h)
6205                         pipe_h = pfit_h;
6206
6207                 if (WARN_ON(!pfit_w || !pfit_h))
6208                         return pixel_rate;
6209
6210                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6211                                      pfit_w * pfit_h);
6212         }
6213
6214         return pixel_rate;
6215 }
6216
6217 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6218 {
6219         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6220
6221         if (HAS_GMCH_DISPLAY(dev_priv))
6222                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6223                 crtc_state->pixel_rate =
6224                         crtc_state->base.adjusted_mode.crtc_clock;
6225         else
6226                 crtc_state->pixel_rate =
6227                         ilk_pipe_pixel_rate(crtc_state);
6228 }
6229
6230 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6231                                      struct intel_crtc_state *pipe_config)
6232 {
6233         struct drm_device *dev = crtc->base.dev;
6234         struct drm_i915_private *dev_priv = to_i915(dev);
6235         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6236         int clock_limit = dev_priv->max_dotclk_freq;
6237
6238         if (INTEL_GEN(dev_priv) < 4) {
6239                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6240
6241                 /*
6242                  * Enable double wide mode when the dot clock
6243                  * is > 90% of the (display) core speed.
6244                  */
6245                 if (intel_crtc_supports_double_wide(crtc) &&
6246                     adjusted_mode->crtc_clock > clock_limit) {
6247                         clock_limit = dev_priv->max_dotclk_freq;
6248                         pipe_config->double_wide = true;
6249                 }
6250         }
6251
6252         if (adjusted_mode->crtc_clock > clock_limit) {
6253                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6254                               adjusted_mode->crtc_clock, clock_limit,
6255                               yesno(pipe_config->double_wide));
6256                 return -EINVAL;
6257         }
6258
6259         /*
6260          * Pipe horizontal size must be even in:
6261          * - DVO ganged mode
6262          * - LVDS dual channel mode
6263          * - Double wide pipe
6264          */
6265         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6266              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6267                 pipe_config->pipe_src_w &= ~1;
6268
6269         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6270          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6271          */
6272         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6273                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6274                 return -EINVAL;
6275
6276         intel_crtc_compute_pixel_rate(pipe_config);
6277
6278         if (HAS_IPS(dev_priv))
6279                 hsw_compute_ips_config(crtc, pipe_config);
6280
6281         if (pipe_config->has_pch_encoder)
6282                 return ironlake_fdi_compute_config(crtc, pipe_config);
6283
6284         return 0;
6285 }
6286
6287 static void
6288 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6289 {
6290         while (*num > DATA_LINK_M_N_MASK ||
6291                *den > DATA_LINK_M_N_MASK) {
6292                 *num >>= 1;
6293                 *den >>= 1;
6294         }
6295 }
6296
6297 static void compute_m_n(unsigned int m, unsigned int n,
6298                         uint32_t *ret_m, uint32_t *ret_n)
6299 {
6300         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6301         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6302         intel_reduce_m_n_ratio(ret_m, ret_n);
6303 }
6304
6305 void
6306 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6307                        int pixel_clock, int link_clock,
6308                        struct intel_link_m_n *m_n)
6309 {
6310         m_n->tu = 64;
6311
6312         compute_m_n(bits_per_pixel * pixel_clock,
6313                     link_clock * nlanes * 8,
6314                     &m_n->gmch_m, &m_n->gmch_n);
6315
6316         compute_m_n(pixel_clock, link_clock,
6317                     &m_n->link_m, &m_n->link_n);
6318 }
6319
6320 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6321 {
6322         if (i915.panel_use_ssc >= 0)
6323                 return i915.panel_use_ssc != 0;
6324         return dev_priv->vbt.lvds_use_ssc
6325                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6326 }
6327
6328 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6329 {
6330         return (1 << dpll->n) << 16 | dpll->m2;
6331 }
6332
6333 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6334 {
6335         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6336 }
6337
6338 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6339                                      struct intel_crtc_state *crtc_state,
6340                                      struct dpll *reduced_clock)
6341 {
6342         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6343         u32 fp, fp2 = 0;
6344
6345         if (IS_PINEVIEW(dev_priv)) {
6346                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6347                 if (reduced_clock)
6348                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6349         } else {
6350                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6351                 if (reduced_clock)
6352                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6353         }
6354
6355         crtc_state->dpll_hw_state.fp0 = fp;
6356
6357         crtc->lowfreq_avail = false;
6358         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6359             reduced_clock) {
6360                 crtc_state->dpll_hw_state.fp1 = fp2;
6361                 crtc->lowfreq_avail = true;
6362         } else {
6363                 crtc_state->dpll_hw_state.fp1 = fp;
6364         }
6365 }
6366
6367 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6368                 pipe)
6369 {
6370         u32 reg_val;
6371
6372         /*
6373          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6374          * and set it to a reasonable value instead.
6375          */
6376         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6377         reg_val &= 0xffffff00;
6378         reg_val |= 0x00000030;
6379         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6380
6381         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6382         reg_val &= 0x8cffffff;
6383         reg_val = 0x8c000000;
6384         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6385
6386         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6387         reg_val &= 0xffffff00;
6388         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6389
6390         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6391         reg_val &= 0x00ffffff;
6392         reg_val |= 0xb0000000;
6393         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6394 }
6395
6396 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6397                                          struct intel_link_m_n *m_n)
6398 {
6399         struct drm_device *dev = crtc->base.dev;
6400         struct drm_i915_private *dev_priv = to_i915(dev);
6401         int pipe = crtc->pipe;
6402
6403         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6404         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6405         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6406         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6407 }
6408
6409 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6410                                          struct intel_link_m_n *m_n,
6411                                          struct intel_link_m_n *m2_n2)
6412 {
6413         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6414         int pipe = crtc->pipe;
6415         enum transcoder transcoder = crtc->config->cpu_transcoder;
6416
6417         if (INTEL_GEN(dev_priv) >= 5) {
6418                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6419                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6420                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6421                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6422                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6423                  * for gen < 8) and if DRRS is supported (to make sure the
6424                  * registers are not unnecessarily accessed).
6425                  */
6426                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6427                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6428                         I915_WRITE(PIPE_DATA_M2(transcoder),
6429                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6430                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6431                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6432                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6433                 }
6434         } else {
6435                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6436                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6437                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6438                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6439         }
6440 }
6441
6442 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6443 {
6444         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6445
6446         if (m_n == M1_N1) {
6447                 dp_m_n = &crtc->config->dp_m_n;
6448                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6449         } else if (m_n == M2_N2) {
6450
6451                 /*
6452                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6453                  * needs to be programmed into M1_N1.
6454                  */
6455                 dp_m_n = &crtc->config->dp_m2_n2;
6456         } else {
6457                 DRM_ERROR("Unsupported divider value\n");
6458                 return;
6459         }
6460
6461         if (crtc->config->has_pch_encoder)
6462                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6463         else
6464                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6465 }
6466
6467 static void vlv_compute_dpll(struct intel_crtc *crtc,
6468                              struct intel_crtc_state *pipe_config)
6469 {
6470         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6471                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6472         if (crtc->pipe != PIPE_A)
6473                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6474
6475         /* DPLL not used with DSI, but still need the rest set up */
6476         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6477                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6478                         DPLL_EXT_BUFFER_ENABLE_VLV;
6479
6480         pipe_config->dpll_hw_state.dpll_md =
6481                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6482 }
6483
6484 static void chv_compute_dpll(struct intel_crtc *crtc,
6485                              struct intel_crtc_state *pipe_config)
6486 {
6487         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6488                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6489         if (crtc->pipe != PIPE_A)
6490                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6491
6492         /* DPLL not used with DSI, but still need the rest set up */
6493         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6494                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6495
6496         pipe_config->dpll_hw_state.dpll_md =
6497                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6498 }
6499
6500 static void vlv_prepare_pll(struct intel_crtc *crtc,
6501                             const struct intel_crtc_state *pipe_config)
6502 {
6503         struct drm_device *dev = crtc->base.dev;
6504         struct drm_i915_private *dev_priv = to_i915(dev);
6505         enum pipe pipe = crtc->pipe;
6506         u32 mdiv;
6507         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6508         u32 coreclk, reg_val;
6509
6510         /* Enable Refclk */
6511         I915_WRITE(DPLL(pipe),
6512                    pipe_config->dpll_hw_state.dpll &
6513                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6514
6515         /* No need to actually set up the DPLL with DSI */
6516         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6517                 return;
6518
6519         mutex_lock(&dev_priv->sb_lock);
6520
6521         bestn = pipe_config->dpll.n;
6522         bestm1 = pipe_config->dpll.m1;
6523         bestm2 = pipe_config->dpll.m2;
6524         bestp1 = pipe_config->dpll.p1;
6525         bestp2 = pipe_config->dpll.p2;
6526
6527         /* See eDP HDMI DPIO driver vbios notes doc */
6528
6529         /* PLL B needs special handling */
6530         if (pipe == PIPE_B)
6531                 vlv_pllb_recal_opamp(dev_priv, pipe);
6532
6533         /* Set up Tx target for periodic Rcomp update */
6534         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6535
6536         /* Disable target IRef on PLL */
6537         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6538         reg_val &= 0x00ffffff;
6539         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6540
6541         /* Disable fast lock */
6542         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6543
6544         /* Set idtafcrecal before PLL is enabled */
6545         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6546         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6547         mdiv |= ((bestn << DPIO_N_SHIFT));
6548         mdiv |= (1 << DPIO_K_SHIFT);
6549
6550         /*
6551          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6552          * but we don't support that).
6553          * Note: don't use the DAC post divider as it seems unstable.
6554          */
6555         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6556         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6557
6558         mdiv |= DPIO_ENABLE_CALIBRATION;
6559         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6560
6561         /* Set HBR and RBR LPF coefficients */
6562         if (pipe_config->port_clock == 162000 ||
6563             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6564             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6565                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6566                                  0x009f0003);
6567         else
6568                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6569                                  0x00d0000f);
6570
6571         if (intel_crtc_has_dp_encoder(pipe_config)) {
6572                 /* Use SSC source */
6573                 if (pipe == PIPE_A)
6574                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6575                                          0x0df40000);
6576                 else
6577                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6578                                          0x0df70000);
6579         } else { /* HDMI or VGA */
6580                 /* Use bend source */
6581                 if (pipe == PIPE_A)
6582                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6583                                          0x0df70000);
6584                 else
6585                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6586                                          0x0df40000);
6587         }
6588
6589         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6590         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6591         if (intel_crtc_has_dp_encoder(crtc->config))
6592                 coreclk |= 0x01000000;
6593         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6594
6595         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6596         mutex_unlock(&dev_priv->sb_lock);
6597 }
6598
6599 static void chv_prepare_pll(struct intel_crtc *crtc,
6600                             const struct intel_crtc_state *pipe_config)
6601 {
6602         struct drm_device *dev = crtc->base.dev;
6603         struct drm_i915_private *dev_priv = to_i915(dev);
6604         enum pipe pipe = crtc->pipe;
6605         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6606         u32 loopfilter, tribuf_calcntr;
6607         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6608         u32 dpio_val;
6609         int vco;
6610
6611         /* Enable Refclk and SSC */
6612         I915_WRITE(DPLL(pipe),
6613                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6614
6615         /* No need to actually set up the DPLL with DSI */
6616         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6617                 return;
6618
6619         bestn = pipe_config->dpll.n;
6620         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6621         bestm1 = pipe_config->dpll.m1;
6622         bestm2 = pipe_config->dpll.m2 >> 22;
6623         bestp1 = pipe_config->dpll.p1;
6624         bestp2 = pipe_config->dpll.p2;
6625         vco = pipe_config->dpll.vco;
6626         dpio_val = 0;
6627         loopfilter = 0;
6628
6629         mutex_lock(&dev_priv->sb_lock);
6630
6631         /* p1 and p2 divider */
6632         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6633                         5 << DPIO_CHV_S1_DIV_SHIFT |
6634                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6635                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6636                         1 << DPIO_CHV_K_DIV_SHIFT);
6637
6638         /* Feedback post-divider - m2 */
6639         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6640
6641         /* Feedback refclk divider - n and m1 */
6642         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6643                         DPIO_CHV_M1_DIV_BY_2 |
6644                         1 << DPIO_CHV_N_DIV_SHIFT);
6645
6646         /* M2 fraction division */
6647         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6648
6649         /* M2 fraction division enable */
6650         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6651         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6652         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6653         if (bestm2_frac)
6654                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6655         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6656
6657         /* Program digital lock detect threshold */
6658         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6659         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6660                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6661         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6662         if (!bestm2_frac)
6663                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6664         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6665
6666         /* Loop filter */
6667         if (vco == 5400000) {
6668                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6669                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6670                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6671                 tribuf_calcntr = 0x9;
6672         } else if (vco <= 6200000) {
6673                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6674                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6675                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6676                 tribuf_calcntr = 0x9;
6677         } else if (vco <= 6480000) {
6678                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6679                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6680                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6681                 tribuf_calcntr = 0x8;
6682         } else {
6683                 /* Not supported. Apply the same limits as in the max case */
6684                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6685                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6686                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6687                 tribuf_calcntr = 0;
6688         }
6689         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6690
6691         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6692         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6693         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6694         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6695
6696         /* AFC Recal */
6697         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6698                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6699                         DPIO_AFC_RECAL);
6700
6701         mutex_unlock(&dev_priv->sb_lock);
6702 }
6703
6704 /**
6705  * vlv_force_pll_on - forcibly enable just the PLL
6706  * @dev_priv: i915 private structure
6707  * @pipe: pipe PLL to enable
6708  * @dpll: PLL configuration
6709  *
6710  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6711  * in cases where we need the PLL enabled even when @pipe is not going to
6712  * be enabled.
6713  */
6714 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6715                      const struct dpll *dpll)
6716 {
6717         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6718         struct intel_crtc_state *pipe_config;
6719
6720         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6721         if (!pipe_config)
6722                 return -ENOMEM;
6723
6724         pipe_config->base.crtc = &crtc->base;
6725         pipe_config->pixel_multiplier = 1;
6726         pipe_config->dpll = *dpll;
6727
6728         if (IS_CHERRYVIEW(dev_priv)) {
6729                 chv_compute_dpll(crtc, pipe_config);
6730                 chv_prepare_pll(crtc, pipe_config);
6731                 chv_enable_pll(crtc, pipe_config);
6732         } else {
6733                 vlv_compute_dpll(crtc, pipe_config);
6734                 vlv_prepare_pll(crtc, pipe_config);
6735                 vlv_enable_pll(crtc, pipe_config);
6736         }
6737
6738         kfree(pipe_config);
6739
6740         return 0;
6741 }
6742
6743 /**
6744  * vlv_force_pll_off - forcibly disable just the PLL
6745  * @dev_priv: i915 private structure
6746  * @pipe: pipe PLL to disable
6747  *
6748  * Disable the PLL for @pipe. To be used in cases where we need
6749  * the PLL enabled even when @pipe is not going to be enabled.
6750  */
6751 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6752 {
6753         if (IS_CHERRYVIEW(dev_priv))
6754                 chv_disable_pll(dev_priv, pipe);
6755         else
6756                 vlv_disable_pll(dev_priv, pipe);
6757 }
6758
6759 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6760                               struct intel_crtc_state *crtc_state,
6761                               struct dpll *reduced_clock)
6762 {
6763         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6764         u32 dpll;
6765         struct dpll *clock = &crtc_state->dpll;
6766
6767         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6768
6769         dpll = DPLL_VGA_MODE_DIS;
6770
6771         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6772                 dpll |= DPLLB_MODE_LVDS;
6773         else
6774                 dpll |= DPLLB_MODE_DAC_SERIAL;
6775
6776         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6777             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6778                 dpll |= (crtc_state->pixel_multiplier - 1)
6779                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6780         }
6781
6782         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6783             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6784                 dpll |= DPLL_SDVO_HIGH_SPEED;
6785
6786         if (intel_crtc_has_dp_encoder(crtc_state))
6787                 dpll |= DPLL_SDVO_HIGH_SPEED;
6788
6789         /* compute bitmask from p1 value */
6790         if (IS_PINEVIEW(dev_priv))
6791                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6792         else {
6793                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6794                 if (IS_G4X(dev_priv) && reduced_clock)
6795                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6796         }
6797         switch (clock->p2) {
6798         case 5:
6799                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6800                 break;
6801         case 7:
6802                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6803                 break;
6804         case 10:
6805                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6806                 break;
6807         case 14:
6808                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6809                 break;
6810         }
6811         if (INTEL_GEN(dev_priv) >= 4)
6812                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6813
6814         if (crtc_state->sdvo_tv_clock)
6815                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6816         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6817                  intel_panel_use_ssc(dev_priv))
6818                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6819         else
6820                 dpll |= PLL_REF_INPUT_DREFCLK;
6821
6822         dpll |= DPLL_VCO_ENABLE;
6823         crtc_state->dpll_hw_state.dpll = dpll;
6824
6825         if (INTEL_GEN(dev_priv) >= 4) {
6826                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6827                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6828                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6829         }
6830 }
6831
6832 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6833                               struct intel_crtc_state *crtc_state,
6834                               struct dpll *reduced_clock)
6835 {
6836         struct drm_device *dev = crtc->base.dev;
6837         struct drm_i915_private *dev_priv = to_i915(dev);
6838         u32 dpll;
6839         struct dpll *clock = &crtc_state->dpll;
6840
6841         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6842
6843         dpll = DPLL_VGA_MODE_DIS;
6844
6845         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6846                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6847         } else {
6848                 if (clock->p1 == 2)
6849                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6850                 else
6851                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6852                 if (clock->p2 == 4)
6853                         dpll |= PLL_P2_DIVIDE_BY_4;
6854         }
6855
6856         if (!IS_I830(dev_priv) &&
6857             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6858                 dpll |= DPLL_DVO_2X_MODE;
6859
6860         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6861             intel_panel_use_ssc(dev_priv))
6862                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6863         else
6864                 dpll |= PLL_REF_INPUT_DREFCLK;
6865
6866         dpll |= DPLL_VCO_ENABLE;
6867         crtc_state->dpll_hw_state.dpll = dpll;
6868 }
6869
6870 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6871 {
6872         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6873         enum pipe pipe = intel_crtc->pipe;
6874         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6875         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6876         uint32_t crtc_vtotal, crtc_vblank_end;
6877         int vsyncshift = 0;
6878
6879         /* We need to be careful not to changed the adjusted mode, for otherwise
6880          * the hw state checker will get angry at the mismatch. */
6881         crtc_vtotal = adjusted_mode->crtc_vtotal;
6882         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6883
6884         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6885                 /* the chip adds 2 halflines automatically */
6886                 crtc_vtotal -= 1;
6887                 crtc_vblank_end -= 1;
6888
6889                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6890                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6891                 else
6892                         vsyncshift = adjusted_mode->crtc_hsync_start -
6893                                 adjusted_mode->crtc_htotal / 2;
6894                 if (vsyncshift < 0)
6895                         vsyncshift += adjusted_mode->crtc_htotal;
6896         }
6897
6898         if (INTEL_GEN(dev_priv) > 3)
6899                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6900
6901         I915_WRITE(HTOTAL(cpu_transcoder),
6902                    (adjusted_mode->crtc_hdisplay - 1) |
6903                    ((adjusted_mode->crtc_htotal - 1) << 16));
6904         I915_WRITE(HBLANK(cpu_transcoder),
6905                    (adjusted_mode->crtc_hblank_start - 1) |
6906                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6907         I915_WRITE(HSYNC(cpu_transcoder),
6908                    (adjusted_mode->crtc_hsync_start - 1) |
6909                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6910
6911         I915_WRITE(VTOTAL(cpu_transcoder),
6912                    (adjusted_mode->crtc_vdisplay - 1) |
6913                    ((crtc_vtotal - 1) << 16));
6914         I915_WRITE(VBLANK(cpu_transcoder),
6915                    (adjusted_mode->crtc_vblank_start - 1) |
6916                    ((crtc_vblank_end - 1) << 16));
6917         I915_WRITE(VSYNC(cpu_transcoder),
6918                    (adjusted_mode->crtc_vsync_start - 1) |
6919                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6920
6921         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6922          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6923          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6924          * bits. */
6925         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6926             (pipe == PIPE_B || pipe == PIPE_C))
6927                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6928
6929 }
6930
6931 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6932 {
6933         struct drm_device *dev = intel_crtc->base.dev;
6934         struct drm_i915_private *dev_priv = to_i915(dev);
6935         enum pipe pipe = intel_crtc->pipe;
6936
6937         /* pipesrc controls the size that is scaled from, which should
6938          * always be the user's requested size.
6939          */
6940         I915_WRITE(PIPESRC(pipe),
6941                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6942                    (intel_crtc->config->pipe_src_h - 1));
6943 }
6944
6945 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6946                                    struct intel_crtc_state *pipe_config)
6947 {
6948         struct drm_device *dev = crtc->base.dev;
6949         struct drm_i915_private *dev_priv = to_i915(dev);
6950         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6951         uint32_t tmp;
6952
6953         tmp = I915_READ(HTOTAL(cpu_transcoder));
6954         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6955         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6956         tmp = I915_READ(HBLANK(cpu_transcoder));
6957         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6958         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6959         tmp = I915_READ(HSYNC(cpu_transcoder));
6960         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6961         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6962
6963         tmp = I915_READ(VTOTAL(cpu_transcoder));
6964         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6965         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6966         tmp = I915_READ(VBLANK(cpu_transcoder));
6967         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6968         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6969         tmp = I915_READ(VSYNC(cpu_transcoder));
6970         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6971         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6972
6973         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6974                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6975                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6976                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6977         }
6978 }
6979
6980 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6981                                     struct intel_crtc_state *pipe_config)
6982 {
6983         struct drm_device *dev = crtc->base.dev;
6984         struct drm_i915_private *dev_priv = to_i915(dev);
6985         u32 tmp;
6986
6987         tmp = I915_READ(PIPESRC(crtc->pipe));
6988         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6989         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6990
6991         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6992         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6993 }
6994
6995 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6996                                  struct intel_crtc_state *pipe_config)
6997 {
6998         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6999         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7000         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7001         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7002
7003         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7004         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7005         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7006         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7007
7008         mode->flags = pipe_config->base.adjusted_mode.flags;
7009         mode->type = DRM_MODE_TYPE_DRIVER;
7010
7011         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7012
7013         mode->hsync = drm_mode_hsync(mode);
7014         mode->vrefresh = drm_mode_vrefresh(mode);
7015         drm_mode_set_name(mode);
7016 }
7017
7018 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7019 {
7020         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7021         uint32_t pipeconf;
7022
7023         pipeconf = 0;
7024
7025         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7026             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7027                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7028
7029         if (intel_crtc->config->double_wide)
7030                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7031
7032         /* only g4x and later have fancy bpc/dither controls */
7033         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7034             IS_CHERRYVIEW(dev_priv)) {
7035                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7036                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7037                         pipeconf |= PIPECONF_DITHER_EN |
7038                                     PIPECONF_DITHER_TYPE_SP;
7039
7040                 switch (intel_crtc->config->pipe_bpp) {
7041                 case 18:
7042                         pipeconf |= PIPECONF_6BPC;
7043                         break;
7044                 case 24:
7045                         pipeconf |= PIPECONF_8BPC;
7046                         break;
7047                 case 30:
7048                         pipeconf |= PIPECONF_10BPC;
7049                         break;
7050                 default:
7051                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7052                         BUG();
7053                 }
7054         }
7055
7056         if (HAS_PIPE_CXSR(dev_priv)) {
7057                 if (intel_crtc->lowfreq_avail) {
7058                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7059                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7060                 } else {
7061                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7062                 }
7063         }
7064
7065         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7066                 if (INTEL_GEN(dev_priv) < 4 ||
7067                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7068                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7069                 else
7070                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7071         } else
7072                 pipeconf |= PIPECONF_PROGRESSIVE;
7073
7074         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7075              intel_crtc->config->limited_color_range)
7076                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7077
7078         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7079         POSTING_READ(PIPECONF(intel_crtc->pipe));
7080 }
7081
7082 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7083                                    struct intel_crtc_state *crtc_state)
7084 {
7085         struct drm_device *dev = crtc->base.dev;
7086         struct drm_i915_private *dev_priv = to_i915(dev);
7087         const struct intel_limit *limit;
7088         int refclk = 48000;
7089
7090         memset(&crtc_state->dpll_hw_state, 0,
7091                sizeof(crtc_state->dpll_hw_state));
7092
7093         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7094                 if (intel_panel_use_ssc(dev_priv)) {
7095                         refclk = dev_priv->vbt.lvds_ssc_freq;
7096                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7097                 }
7098
7099                 limit = &intel_limits_i8xx_lvds;
7100         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7101                 limit = &intel_limits_i8xx_dvo;
7102         } else {
7103                 limit = &intel_limits_i8xx_dac;
7104         }
7105
7106         if (!crtc_state->clock_set &&
7107             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7108                                  refclk, NULL, &crtc_state->dpll)) {
7109                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7110                 return -EINVAL;
7111         }
7112
7113         i8xx_compute_dpll(crtc, crtc_state, NULL);
7114
7115         return 0;
7116 }
7117
7118 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7119                                   struct intel_crtc_state *crtc_state)
7120 {
7121         struct drm_device *dev = crtc->base.dev;
7122         struct drm_i915_private *dev_priv = to_i915(dev);
7123         const struct intel_limit *limit;
7124         int refclk = 96000;
7125
7126         memset(&crtc_state->dpll_hw_state, 0,
7127                sizeof(crtc_state->dpll_hw_state));
7128
7129         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7130                 if (intel_panel_use_ssc(dev_priv)) {
7131                         refclk = dev_priv->vbt.lvds_ssc_freq;
7132                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7133                 }
7134
7135                 if (intel_is_dual_link_lvds(dev))
7136                         limit = &intel_limits_g4x_dual_channel_lvds;
7137                 else
7138                         limit = &intel_limits_g4x_single_channel_lvds;
7139         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7140                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7141                 limit = &intel_limits_g4x_hdmi;
7142         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7143                 limit = &intel_limits_g4x_sdvo;
7144         } else {
7145                 /* The option is for other outputs */
7146                 limit = &intel_limits_i9xx_sdvo;
7147         }
7148
7149         if (!crtc_state->clock_set &&
7150             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7151                                 refclk, NULL, &crtc_state->dpll)) {
7152                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7153                 return -EINVAL;
7154         }
7155
7156         i9xx_compute_dpll(crtc, crtc_state, NULL);
7157
7158         return 0;
7159 }
7160
7161 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7162                                   struct intel_crtc_state *crtc_state)
7163 {
7164         struct drm_device *dev = crtc->base.dev;
7165         struct drm_i915_private *dev_priv = to_i915(dev);
7166         const struct intel_limit *limit;
7167         int refclk = 96000;
7168
7169         memset(&crtc_state->dpll_hw_state, 0,
7170                sizeof(crtc_state->dpll_hw_state));
7171
7172         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7173                 if (intel_panel_use_ssc(dev_priv)) {
7174                         refclk = dev_priv->vbt.lvds_ssc_freq;
7175                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7176                 }
7177
7178                 limit = &intel_limits_pineview_lvds;
7179         } else {
7180                 limit = &intel_limits_pineview_sdvo;
7181         }
7182
7183         if (!crtc_state->clock_set &&
7184             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7185                                 refclk, NULL, &crtc_state->dpll)) {
7186                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7187                 return -EINVAL;
7188         }
7189
7190         i9xx_compute_dpll(crtc, crtc_state, NULL);
7191
7192         return 0;
7193 }
7194
7195 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7196                                    struct intel_crtc_state *crtc_state)
7197 {
7198         struct drm_device *dev = crtc->base.dev;
7199         struct drm_i915_private *dev_priv = to_i915(dev);
7200         const struct intel_limit *limit;
7201         int refclk = 96000;
7202
7203         memset(&crtc_state->dpll_hw_state, 0,
7204                sizeof(crtc_state->dpll_hw_state));
7205
7206         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7207                 if (intel_panel_use_ssc(dev_priv)) {
7208                         refclk = dev_priv->vbt.lvds_ssc_freq;
7209                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7210                 }
7211
7212                 limit = &intel_limits_i9xx_lvds;
7213         } else {
7214                 limit = &intel_limits_i9xx_sdvo;
7215         }
7216
7217         if (!crtc_state->clock_set &&
7218             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7219                                  refclk, NULL, &crtc_state->dpll)) {
7220                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7221                 return -EINVAL;
7222         }
7223
7224         i9xx_compute_dpll(crtc, crtc_state, NULL);
7225
7226         return 0;
7227 }
7228
7229 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7230                                   struct intel_crtc_state *crtc_state)
7231 {
7232         int refclk = 100000;
7233         const struct intel_limit *limit = &intel_limits_chv;
7234
7235         memset(&crtc_state->dpll_hw_state, 0,
7236                sizeof(crtc_state->dpll_hw_state));
7237
7238         if (!crtc_state->clock_set &&
7239             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7240                                 refclk, NULL, &crtc_state->dpll)) {
7241                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7242                 return -EINVAL;
7243         }
7244
7245         chv_compute_dpll(crtc, crtc_state);
7246
7247         return 0;
7248 }
7249
7250 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7251                                   struct intel_crtc_state *crtc_state)
7252 {
7253         int refclk = 100000;
7254         const struct intel_limit *limit = &intel_limits_vlv;
7255
7256         memset(&crtc_state->dpll_hw_state, 0,
7257                sizeof(crtc_state->dpll_hw_state));
7258
7259         if (!crtc_state->clock_set &&
7260             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7261                                 refclk, NULL, &crtc_state->dpll)) {
7262                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7263                 return -EINVAL;
7264         }
7265
7266         vlv_compute_dpll(crtc, crtc_state);
7267
7268         return 0;
7269 }
7270
7271 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7272                                  struct intel_crtc_state *pipe_config)
7273 {
7274         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7275         uint32_t tmp;
7276
7277         if (INTEL_GEN(dev_priv) <= 3 &&
7278             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7279                 return;
7280
7281         tmp = I915_READ(PFIT_CONTROL);
7282         if (!(tmp & PFIT_ENABLE))
7283                 return;
7284
7285         /* Check whether the pfit is attached to our pipe. */
7286         if (INTEL_GEN(dev_priv) < 4) {
7287                 if (crtc->pipe != PIPE_B)
7288                         return;
7289         } else {
7290                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7291                         return;
7292         }
7293
7294         pipe_config->gmch_pfit.control = tmp;
7295         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7296 }
7297
7298 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7299                                struct intel_crtc_state *pipe_config)
7300 {
7301         struct drm_device *dev = crtc->base.dev;
7302         struct drm_i915_private *dev_priv = to_i915(dev);
7303         int pipe = pipe_config->cpu_transcoder;
7304         struct dpll clock;
7305         u32 mdiv;
7306         int refclk = 100000;
7307
7308         /* In case of DSI, DPLL will not be used */
7309         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7310                 return;
7311
7312         mutex_lock(&dev_priv->sb_lock);
7313         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7314         mutex_unlock(&dev_priv->sb_lock);
7315
7316         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7317         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7318         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7319         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7320         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7321
7322         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7323 }
7324
7325 static void
7326 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7327                               struct intel_initial_plane_config *plane_config)
7328 {
7329         struct drm_device *dev = crtc->base.dev;
7330         struct drm_i915_private *dev_priv = to_i915(dev);
7331         u32 val, base, offset;
7332         int pipe = crtc->pipe, plane = crtc->plane;
7333         int fourcc, pixel_format;
7334         unsigned int aligned_height;
7335         struct drm_framebuffer *fb;
7336         struct intel_framebuffer *intel_fb;
7337
7338         val = I915_READ(DSPCNTR(plane));
7339         if (!(val & DISPLAY_PLANE_ENABLE))
7340                 return;
7341
7342         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7343         if (!intel_fb) {
7344                 DRM_DEBUG_KMS("failed to alloc fb\n");
7345                 return;
7346         }
7347
7348         fb = &intel_fb->base;
7349
7350         fb->dev = dev;
7351
7352         if (INTEL_GEN(dev_priv) >= 4) {
7353                 if (val & DISPPLANE_TILED) {
7354                         plane_config->tiling = I915_TILING_X;
7355                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7356                 }
7357         }
7358
7359         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7360         fourcc = i9xx_format_to_fourcc(pixel_format);
7361         fb->format = drm_format_info(fourcc);
7362
7363         if (INTEL_GEN(dev_priv) >= 4) {
7364                 if (plane_config->tiling)
7365                         offset = I915_READ(DSPTILEOFF(plane));
7366                 else
7367                         offset = I915_READ(DSPLINOFF(plane));
7368                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7369         } else {
7370                 base = I915_READ(DSPADDR(plane));
7371         }
7372         plane_config->base = base;
7373
7374         val = I915_READ(PIPESRC(pipe));
7375         fb->width = ((val >> 16) & 0xfff) + 1;
7376         fb->height = ((val >> 0) & 0xfff) + 1;
7377
7378         val = I915_READ(DSPSTRIDE(pipe));
7379         fb->pitches[0] = val & 0xffffffc0;
7380
7381         aligned_height = intel_fb_align_height(dev_priv,
7382                                                fb->height,
7383                                                fb->format->format,
7384                                                fb->modifier);
7385
7386         plane_config->size = fb->pitches[0] * aligned_height;
7387
7388         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7389                       pipe_name(pipe), plane, fb->width, fb->height,
7390                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7391                       plane_config->size);
7392
7393         plane_config->fb = intel_fb;
7394 }
7395
7396 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7397                                struct intel_crtc_state *pipe_config)
7398 {
7399         struct drm_device *dev = crtc->base.dev;
7400         struct drm_i915_private *dev_priv = to_i915(dev);
7401         int pipe = pipe_config->cpu_transcoder;
7402         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7403         struct dpll clock;
7404         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7405         int refclk = 100000;
7406
7407         /* In case of DSI, DPLL will not be used */
7408         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7409                 return;
7410
7411         mutex_lock(&dev_priv->sb_lock);
7412         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7413         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7414         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7415         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7416         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7417         mutex_unlock(&dev_priv->sb_lock);
7418
7419         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7420         clock.m2 = (pll_dw0 & 0xff) << 22;
7421         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7422                 clock.m2 |= pll_dw2 & 0x3fffff;
7423         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7424         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7425         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7426
7427         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7428 }
7429
7430 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7431                                  struct intel_crtc_state *pipe_config)
7432 {
7433         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7434         enum intel_display_power_domain power_domain;
7435         uint32_t tmp;
7436         bool ret;
7437
7438         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7439         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7440                 return false;
7441
7442         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7443         pipe_config->shared_dpll = NULL;
7444
7445         ret = false;
7446
7447         tmp = I915_READ(PIPECONF(crtc->pipe));
7448         if (!(tmp & PIPECONF_ENABLE))
7449                 goto out;
7450
7451         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7452             IS_CHERRYVIEW(dev_priv)) {
7453                 switch (tmp & PIPECONF_BPC_MASK) {
7454                 case PIPECONF_6BPC:
7455                         pipe_config->pipe_bpp = 18;
7456                         break;
7457                 case PIPECONF_8BPC:
7458                         pipe_config->pipe_bpp = 24;
7459                         break;
7460                 case PIPECONF_10BPC:
7461                         pipe_config->pipe_bpp = 30;
7462                         break;
7463                 default:
7464                         break;
7465                 }
7466         }
7467
7468         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7469             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7470                 pipe_config->limited_color_range = true;
7471
7472         if (INTEL_GEN(dev_priv) < 4)
7473                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7474
7475         intel_get_pipe_timings(crtc, pipe_config);
7476         intel_get_pipe_src_size(crtc, pipe_config);
7477
7478         i9xx_get_pfit_config(crtc, pipe_config);
7479
7480         if (INTEL_GEN(dev_priv) >= 4) {
7481                 /* No way to read it out on pipes B and C */
7482                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7483                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7484                 else
7485                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7486                 pipe_config->pixel_multiplier =
7487                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7488                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7489                 pipe_config->dpll_hw_state.dpll_md = tmp;
7490         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7491                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7492                 tmp = I915_READ(DPLL(crtc->pipe));
7493                 pipe_config->pixel_multiplier =
7494                         ((tmp & SDVO_MULTIPLIER_MASK)
7495                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7496         } else {
7497                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7498                  * port and will be fixed up in the encoder->get_config
7499                  * function. */
7500                 pipe_config->pixel_multiplier = 1;
7501         }
7502         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7503         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7504                 /*
7505                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7506                  * on 830. Filter it out here so that we don't
7507                  * report errors due to that.
7508                  */
7509                 if (IS_I830(dev_priv))
7510                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7511
7512                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7513                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7514         } else {
7515                 /* Mask out read-only status bits. */
7516                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7517                                                      DPLL_PORTC_READY_MASK |
7518                                                      DPLL_PORTB_READY_MASK);
7519         }
7520
7521         if (IS_CHERRYVIEW(dev_priv))
7522                 chv_crtc_clock_get(crtc, pipe_config);
7523         else if (IS_VALLEYVIEW(dev_priv))
7524                 vlv_crtc_clock_get(crtc, pipe_config);
7525         else
7526                 i9xx_crtc_clock_get(crtc, pipe_config);
7527
7528         /*
7529          * Normally the dotclock is filled in by the encoder .get_config()
7530          * but in case the pipe is enabled w/o any ports we need a sane
7531          * default.
7532          */
7533         pipe_config->base.adjusted_mode.crtc_clock =
7534                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7535
7536         ret = true;
7537
7538 out:
7539         intel_display_power_put(dev_priv, power_domain);
7540
7541         return ret;
7542 }
7543
7544 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7545 {
7546         struct intel_encoder *encoder;
7547         int i;
7548         u32 val, final;
7549         bool has_lvds = false;
7550         bool has_cpu_edp = false;
7551         bool has_panel = false;
7552         bool has_ck505 = false;
7553         bool can_ssc = false;
7554         bool using_ssc_source = false;
7555
7556         /* We need to take the global config into account */
7557         for_each_intel_encoder(&dev_priv->drm, encoder) {
7558                 switch (encoder->type) {
7559                 case INTEL_OUTPUT_LVDS:
7560                         has_panel = true;
7561                         has_lvds = true;
7562                         break;
7563                 case INTEL_OUTPUT_EDP:
7564                         has_panel = true;
7565                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7566                                 has_cpu_edp = true;
7567                         break;
7568                 default:
7569                         break;
7570                 }
7571         }
7572
7573         if (HAS_PCH_IBX(dev_priv)) {
7574                 has_ck505 = dev_priv->vbt.display_clock_mode;
7575                 can_ssc = has_ck505;
7576         } else {
7577                 has_ck505 = false;
7578                 can_ssc = true;
7579         }
7580
7581         /* Check if any DPLLs are using the SSC source */
7582         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7583                 u32 temp = I915_READ(PCH_DPLL(i));
7584
7585                 if (!(temp & DPLL_VCO_ENABLE))
7586                         continue;
7587
7588                 if ((temp & PLL_REF_INPUT_MASK) ==
7589                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7590                         using_ssc_source = true;
7591                         break;
7592                 }
7593         }
7594
7595         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7596                       has_panel, has_lvds, has_ck505, using_ssc_source);
7597
7598         /* Ironlake: try to setup display ref clock before DPLL
7599          * enabling. This is only under driver's control after
7600          * PCH B stepping, previous chipset stepping should be
7601          * ignoring this setting.
7602          */
7603         val = I915_READ(PCH_DREF_CONTROL);
7604
7605         /* As we must carefully and slowly disable/enable each source in turn,
7606          * compute the final state we want first and check if we need to
7607          * make any changes at all.
7608          */
7609         final = val;
7610         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7611         if (has_ck505)
7612                 final |= DREF_NONSPREAD_CK505_ENABLE;
7613         else
7614                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7615
7616         final &= ~DREF_SSC_SOURCE_MASK;
7617         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7618         final &= ~DREF_SSC1_ENABLE;
7619
7620         if (has_panel) {
7621                 final |= DREF_SSC_SOURCE_ENABLE;
7622
7623                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7624                         final |= DREF_SSC1_ENABLE;
7625
7626                 if (has_cpu_edp) {
7627                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7628                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7629                         else
7630                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7631                 } else
7632                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7633         } else if (using_ssc_source) {
7634                 final |= DREF_SSC_SOURCE_ENABLE;
7635                 final |= DREF_SSC1_ENABLE;
7636         }
7637
7638         if (final == val)
7639                 return;
7640
7641         /* Always enable nonspread source */
7642         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7643
7644         if (has_ck505)
7645                 val |= DREF_NONSPREAD_CK505_ENABLE;
7646         else
7647                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7648
7649         if (has_panel) {
7650                 val &= ~DREF_SSC_SOURCE_MASK;
7651                 val |= DREF_SSC_SOURCE_ENABLE;
7652
7653                 /* SSC must be turned on before enabling the CPU output  */
7654                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7655                         DRM_DEBUG_KMS("Using SSC on panel\n");
7656                         val |= DREF_SSC1_ENABLE;
7657                 } else
7658                         val &= ~DREF_SSC1_ENABLE;
7659
7660                 /* Get SSC going before enabling the outputs */
7661                 I915_WRITE(PCH_DREF_CONTROL, val);
7662                 POSTING_READ(PCH_DREF_CONTROL);
7663                 udelay(200);
7664
7665                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7666
7667                 /* Enable CPU source on CPU attached eDP */
7668                 if (has_cpu_edp) {
7669                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7670                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7671                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7672                         } else
7673                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7674                 } else
7675                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7676
7677                 I915_WRITE(PCH_DREF_CONTROL, val);
7678                 POSTING_READ(PCH_DREF_CONTROL);
7679                 udelay(200);
7680         } else {
7681                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7682
7683                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7684
7685                 /* Turn off CPU output */
7686                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7687
7688                 I915_WRITE(PCH_DREF_CONTROL, val);
7689                 POSTING_READ(PCH_DREF_CONTROL);
7690                 udelay(200);
7691
7692                 if (!using_ssc_source) {
7693                         DRM_DEBUG_KMS("Disabling SSC source\n");
7694
7695                         /* Turn off the SSC source */
7696                         val &= ~DREF_SSC_SOURCE_MASK;
7697                         val |= DREF_SSC_SOURCE_DISABLE;
7698
7699                         /* Turn off SSC1 */
7700                         val &= ~DREF_SSC1_ENABLE;
7701
7702                         I915_WRITE(PCH_DREF_CONTROL, val);
7703                         POSTING_READ(PCH_DREF_CONTROL);
7704                         udelay(200);
7705                 }
7706         }
7707
7708         BUG_ON(val != final);
7709 }
7710
7711 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7712 {
7713         uint32_t tmp;
7714
7715         tmp = I915_READ(SOUTH_CHICKEN2);
7716         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7717         I915_WRITE(SOUTH_CHICKEN2, tmp);
7718
7719         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7720                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7721                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7722
7723         tmp = I915_READ(SOUTH_CHICKEN2);
7724         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7725         I915_WRITE(SOUTH_CHICKEN2, tmp);
7726
7727         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7728                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7729                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7730 }
7731
7732 /* WaMPhyProgramming:hsw */
7733 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7734 {
7735         uint32_t tmp;
7736
7737         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7738         tmp &= ~(0xFF << 24);
7739         tmp |= (0x12 << 24);
7740         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7741
7742         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7743         tmp |= (1 << 11);
7744         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7745
7746         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7747         tmp |= (1 << 11);
7748         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7749
7750         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7751         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7752         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7753
7754         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7755         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7756         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7757
7758         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7759         tmp &= ~(7 << 13);
7760         tmp |= (5 << 13);
7761         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7762
7763         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7764         tmp &= ~(7 << 13);
7765         tmp |= (5 << 13);
7766         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7767
7768         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7769         tmp &= ~0xFF;
7770         tmp |= 0x1C;
7771         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7772
7773         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7774         tmp &= ~0xFF;
7775         tmp |= 0x1C;
7776         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7777
7778         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7779         tmp &= ~(0xFF << 16);
7780         tmp |= (0x1C << 16);
7781         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7782
7783         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7784         tmp &= ~(0xFF << 16);
7785         tmp |= (0x1C << 16);
7786         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7787
7788         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7789         tmp |= (1 << 27);
7790         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7791
7792         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7793         tmp |= (1 << 27);
7794         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7795
7796         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7797         tmp &= ~(0xF << 28);
7798         tmp |= (4 << 28);
7799         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7800
7801         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7802         tmp &= ~(0xF << 28);
7803         tmp |= (4 << 28);
7804         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7805 }
7806
7807 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7808  * Programming" based on the parameters passed:
7809  * - Sequence to enable CLKOUT_DP
7810  * - Sequence to enable CLKOUT_DP without spread
7811  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7812  */
7813 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7814                                  bool with_spread, bool with_fdi)
7815 {
7816         uint32_t reg, tmp;
7817
7818         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7819                 with_spread = true;
7820         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7821             with_fdi, "LP PCH doesn't have FDI\n"))
7822                 with_fdi = false;
7823
7824         mutex_lock(&dev_priv->sb_lock);
7825
7826         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7827         tmp &= ~SBI_SSCCTL_DISABLE;
7828         tmp |= SBI_SSCCTL_PATHALT;
7829         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7830
7831         udelay(24);
7832
7833         if (with_spread) {
7834                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7835                 tmp &= ~SBI_SSCCTL_PATHALT;
7836                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7837
7838                 if (with_fdi) {
7839                         lpt_reset_fdi_mphy(dev_priv);
7840                         lpt_program_fdi_mphy(dev_priv);
7841                 }
7842         }
7843
7844         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7845         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7846         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7847         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7848
7849         mutex_unlock(&dev_priv->sb_lock);
7850 }
7851
7852 /* Sequence to disable CLKOUT_DP */
7853 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7854 {
7855         uint32_t reg, tmp;
7856
7857         mutex_lock(&dev_priv->sb_lock);
7858
7859         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7860         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7861         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7862         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7863
7864         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7865         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7866                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7867                         tmp |= SBI_SSCCTL_PATHALT;
7868                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7869                         udelay(32);
7870                 }
7871                 tmp |= SBI_SSCCTL_DISABLE;
7872                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7873         }
7874
7875         mutex_unlock(&dev_priv->sb_lock);
7876 }
7877
7878 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7879
7880 static const uint16_t sscdivintphase[] = {
7881         [BEND_IDX( 50)] = 0x3B23,
7882         [BEND_IDX( 45)] = 0x3B23,
7883         [BEND_IDX( 40)] = 0x3C23,
7884         [BEND_IDX( 35)] = 0x3C23,
7885         [BEND_IDX( 30)] = 0x3D23,
7886         [BEND_IDX( 25)] = 0x3D23,
7887         [BEND_IDX( 20)] = 0x3E23,
7888         [BEND_IDX( 15)] = 0x3E23,
7889         [BEND_IDX( 10)] = 0x3F23,
7890         [BEND_IDX(  5)] = 0x3F23,
7891         [BEND_IDX(  0)] = 0x0025,
7892         [BEND_IDX( -5)] = 0x0025,
7893         [BEND_IDX(-10)] = 0x0125,
7894         [BEND_IDX(-15)] = 0x0125,
7895         [BEND_IDX(-20)] = 0x0225,
7896         [BEND_IDX(-25)] = 0x0225,
7897         [BEND_IDX(-30)] = 0x0325,
7898         [BEND_IDX(-35)] = 0x0325,
7899         [BEND_IDX(-40)] = 0x0425,
7900         [BEND_IDX(-45)] = 0x0425,
7901         [BEND_IDX(-50)] = 0x0525,
7902 };
7903
7904 /*
7905  * Bend CLKOUT_DP
7906  * steps -50 to 50 inclusive, in steps of 5
7907  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7908  * change in clock period = -(steps / 10) * 5.787 ps
7909  */
7910 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7911 {
7912         uint32_t tmp;
7913         int idx = BEND_IDX(steps);
7914
7915         if (WARN_ON(steps % 5 != 0))
7916                 return;
7917
7918         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7919                 return;
7920
7921         mutex_lock(&dev_priv->sb_lock);
7922
7923         if (steps % 10 != 0)
7924                 tmp = 0xAAAAAAAB;
7925         else
7926                 tmp = 0x00000000;
7927         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7928
7929         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7930         tmp &= 0xffff0000;
7931         tmp |= sscdivintphase[idx];
7932         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7933
7934         mutex_unlock(&dev_priv->sb_lock);
7935 }
7936
7937 #undef BEND_IDX
7938
7939 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7940 {
7941         struct intel_encoder *encoder;
7942         bool has_vga = false;
7943
7944         for_each_intel_encoder(&dev_priv->drm, encoder) {
7945                 switch (encoder->type) {
7946                 case INTEL_OUTPUT_ANALOG:
7947                         has_vga = true;
7948                         break;
7949                 default:
7950                         break;
7951                 }
7952         }
7953
7954         if (has_vga) {
7955                 lpt_bend_clkout_dp(dev_priv, 0);
7956                 lpt_enable_clkout_dp(dev_priv, true, true);
7957         } else {
7958                 lpt_disable_clkout_dp(dev_priv);
7959         }
7960 }
7961
7962 /*
7963  * Initialize reference clocks when the driver loads
7964  */
7965 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7966 {
7967         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7968                 ironlake_init_pch_refclk(dev_priv);
7969         else if (HAS_PCH_LPT(dev_priv))
7970                 lpt_init_pch_refclk(dev_priv);
7971 }
7972
7973 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7974 {
7975         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7976         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7977         int pipe = intel_crtc->pipe;
7978         uint32_t val;
7979
7980         val = 0;
7981
7982         switch (intel_crtc->config->pipe_bpp) {
7983         case 18:
7984                 val |= PIPECONF_6BPC;
7985                 break;
7986         case 24:
7987                 val |= PIPECONF_8BPC;
7988                 break;
7989         case 30:
7990                 val |= PIPECONF_10BPC;
7991                 break;
7992         case 36:
7993                 val |= PIPECONF_12BPC;
7994                 break;
7995         default:
7996                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7997                 BUG();
7998         }
7999
8000         if (intel_crtc->config->dither)
8001                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8002
8003         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8004                 val |= PIPECONF_INTERLACED_ILK;
8005         else
8006                 val |= PIPECONF_PROGRESSIVE;
8007
8008         if (intel_crtc->config->limited_color_range)
8009                 val |= PIPECONF_COLOR_RANGE_SELECT;
8010
8011         I915_WRITE(PIPECONF(pipe), val);
8012         POSTING_READ(PIPECONF(pipe));
8013 }
8014
8015 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8016 {
8017         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8019         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8020         u32 val = 0;
8021
8022         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8023                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8024
8025         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8026                 val |= PIPECONF_INTERLACED_ILK;
8027         else
8028                 val |= PIPECONF_PROGRESSIVE;
8029
8030         I915_WRITE(PIPECONF(cpu_transcoder), val);
8031         POSTING_READ(PIPECONF(cpu_transcoder));
8032 }
8033
8034 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8035 {
8036         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8038
8039         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8040                 u32 val = 0;
8041
8042                 switch (intel_crtc->config->pipe_bpp) {
8043                 case 18:
8044                         val |= PIPEMISC_DITHER_6_BPC;
8045                         break;
8046                 case 24:
8047                         val |= PIPEMISC_DITHER_8_BPC;
8048                         break;
8049                 case 30:
8050                         val |= PIPEMISC_DITHER_10_BPC;
8051                         break;
8052                 case 36:
8053                         val |= PIPEMISC_DITHER_12_BPC;
8054                         break;
8055                 default:
8056                         /* Case prevented by pipe_config_set_bpp. */
8057                         BUG();
8058                 }
8059
8060                 if (intel_crtc->config->dither)
8061                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8062
8063                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8064         }
8065 }
8066
8067 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8068 {
8069         /*
8070          * Account for spread spectrum to avoid
8071          * oversubscribing the link. Max center spread
8072          * is 2.5%; use 5% for safety's sake.
8073          */
8074         u32 bps = target_clock * bpp * 21 / 20;
8075         return DIV_ROUND_UP(bps, link_bw * 8);
8076 }
8077
8078 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8079 {
8080         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8081 }
8082
8083 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8084                                   struct intel_crtc_state *crtc_state,
8085                                   struct dpll *reduced_clock)
8086 {
8087         struct drm_crtc *crtc = &intel_crtc->base;
8088         struct drm_device *dev = crtc->dev;
8089         struct drm_i915_private *dev_priv = to_i915(dev);
8090         u32 dpll, fp, fp2;
8091         int factor;
8092
8093         /* Enable autotuning of the PLL clock (if permissible) */
8094         factor = 21;
8095         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8096                 if ((intel_panel_use_ssc(dev_priv) &&
8097                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8098                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8099                         factor = 25;
8100         } else if (crtc_state->sdvo_tv_clock)
8101                 factor = 20;
8102
8103         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8104
8105         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8106                 fp |= FP_CB_TUNE;
8107
8108         if (reduced_clock) {
8109                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8110
8111                 if (reduced_clock->m < factor * reduced_clock->n)
8112                         fp2 |= FP_CB_TUNE;
8113         } else {
8114                 fp2 = fp;
8115         }
8116
8117         dpll = 0;
8118
8119         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8120                 dpll |= DPLLB_MODE_LVDS;
8121         else
8122                 dpll |= DPLLB_MODE_DAC_SERIAL;
8123
8124         dpll |= (crtc_state->pixel_multiplier - 1)
8125                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8126
8127         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8128             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8129                 dpll |= DPLL_SDVO_HIGH_SPEED;
8130
8131         if (intel_crtc_has_dp_encoder(crtc_state))
8132                 dpll |= DPLL_SDVO_HIGH_SPEED;
8133
8134         /*
8135          * The high speed IO clock is only really required for
8136          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8137          * possible to share the DPLL between CRT and HDMI. Enabling
8138          * the clock needlessly does no real harm, except use up a
8139          * bit of power potentially.
8140          *
8141          * We'll limit this to IVB with 3 pipes, since it has only two
8142          * DPLLs and so DPLL sharing is the only way to get three pipes
8143          * driving PCH ports at the same time. On SNB we could do this,
8144          * and potentially avoid enabling the second DPLL, but it's not
8145          * clear if it''s a win or loss power wise. No point in doing
8146          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8147          */
8148         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8149             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8150                 dpll |= DPLL_SDVO_HIGH_SPEED;
8151
8152         /* compute bitmask from p1 value */
8153         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8154         /* also FPA1 */
8155         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8156
8157         switch (crtc_state->dpll.p2) {
8158         case 5:
8159                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8160                 break;
8161         case 7:
8162                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8163                 break;
8164         case 10:
8165                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8166                 break;
8167         case 14:
8168                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8169                 break;
8170         }
8171
8172         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8173             intel_panel_use_ssc(dev_priv))
8174                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8175         else
8176                 dpll |= PLL_REF_INPUT_DREFCLK;
8177
8178         dpll |= DPLL_VCO_ENABLE;
8179
8180         crtc_state->dpll_hw_state.dpll = dpll;
8181         crtc_state->dpll_hw_state.fp0 = fp;
8182         crtc_state->dpll_hw_state.fp1 = fp2;
8183 }
8184
8185 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8186                                        struct intel_crtc_state *crtc_state)
8187 {
8188         struct drm_device *dev = crtc->base.dev;
8189         struct drm_i915_private *dev_priv = to_i915(dev);
8190         struct dpll reduced_clock;
8191         bool has_reduced_clock = false;
8192         struct intel_shared_dpll *pll;
8193         const struct intel_limit *limit;
8194         int refclk = 120000;
8195
8196         memset(&crtc_state->dpll_hw_state, 0,
8197                sizeof(crtc_state->dpll_hw_state));
8198
8199         crtc->lowfreq_avail = false;
8200
8201         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8202         if (!crtc_state->has_pch_encoder)
8203                 return 0;
8204
8205         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8206                 if (intel_panel_use_ssc(dev_priv)) {
8207                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8208                                       dev_priv->vbt.lvds_ssc_freq);
8209                         refclk = dev_priv->vbt.lvds_ssc_freq;
8210                 }
8211
8212                 if (intel_is_dual_link_lvds(dev)) {
8213                         if (refclk == 100000)
8214                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8215                         else
8216                                 limit = &intel_limits_ironlake_dual_lvds;
8217                 } else {
8218                         if (refclk == 100000)
8219                                 limit = &intel_limits_ironlake_single_lvds_100m;
8220                         else
8221                                 limit = &intel_limits_ironlake_single_lvds;
8222                 }
8223         } else {
8224                 limit = &intel_limits_ironlake_dac;
8225         }
8226
8227         if (!crtc_state->clock_set &&
8228             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8229                                 refclk, NULL, &crtc_state->dpll)) {
8230                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8231                 return -EINVAL;
8232         }
8233
8234         ironlake_compute_dpll(crtc, crtc_state,
8235                               has_reduced_clock ? &reduced_clock : NULL);
8236
8237         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8238         if (pll == NULL) {
8239                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8240                                  pipe_name(crtc->pipe));
8241                 return -EINVAL;
8242         }
8243
8244         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8245             has_reduced_clock)
8246                 crtc->lowfreq_avail = true;
8247
8248         return 0;
8249 }
8250
8251 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8252                                          struct intel_link_m_n *m_n)
8253 {
8254         struct drm_device *dev = crtc->base.dev;
8255         struct drm_i915_private *dev_priv = to_i915(dev);
8256         enum pipe pipe = crtc->pipe;
8257
8258         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8259         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8260         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8261                 & ~TU_SIZE_MASK;
8262         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8263         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8264                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8265 }
8266
8267 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8268                                          enum transcoder transcoder,
8269                                          struct intel_link_m_n *m_n,
8270                                          struct intel_link_m_n *m2_n2)
8271 {
8272         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8273         enum pipe pipe = crtc->pipe;
8274
8275         if (INTEL_GEN(dev_priv) >= 5) {
8276                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8277                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8278                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8279                         & ~TU_SIZE_MASK;
8280                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8281                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8282                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8283                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8284                  * gen < 8) and if DRRS is supported (to make sure the
8285                  * registers are not unnecessarily read).
8286                  */
8287                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8288                         crtc->config->has_drrs) {
8289                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8290                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8291                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8292                                         & ~TU_SIZE_MASK;
8293                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8294                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8295                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8296                 }
8297         } else {
8298                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8299                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8300                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8301                         & ~TU_SIZE_MASK;
8302                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8303                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8304                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8305         }
8306 }
8307
8308 void intel_dp_get_m_n(struct intel_crtc *crtc,
8309                       struct intel_crtc_state *pipe_config)
8310 {
8311         if (pipe_config->has_pch_encoder)
8312                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8313         else
8314                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8315                                              &pipe_config->dp_m_n,
8316                                              &pipe_config->dp_m2_n2);
8317 }
8318
8319 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8320                                         struct intel_crtc_state *pipe_config)
8321 {
8322         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8323                                      &pipe_config->fdi_m_n, NULL);
8324 }
8325
8326 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8327                                     struct intel_crtc_state *pipe_config)
8328 {
8329         struct drm_device *dev = crtc->base.dev;
8330         struct drm_i915_private *dev_priv = to_i915(dev);
8331         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8332         uint32_t ps_ctrl = 0;
8333         int id = -1;
8334         int i;
8335
8336         /* find scaler attached to this pipe */
8337         for (i = 0; i < crtc->num_scalers; i++) {
8338                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8339                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8340                         id = i;
8341                         pipe_config->pch_pfit.enabled = true;
8342                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8343                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8344                         break;
8345                 }
8346         }
8347
8348         scaler_state->scaler_id = id;
8349         if (id >= 0) {
8350                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8351         } else {
8352                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8353         }
8354 }
8355
8356 static void
8357 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8358                                  struct intel_initial_plane_config *plane_config)
8359 {
8360         struct drm_device *dev = crtc->base.dev;
8361         struct drm_i915_private *dev_priv = to_i915(dev);
8362         u32 val, base, offset, stride_mult, tiling;
8363         int pipe = crtc->pipe;
8364         int fourcc, pixel_format;
8365         unsigned int aligned_height;
8366         struct drm_framebuffer *fb;
8367         struct intel_framebuffer *intel_fb;
8368
8369         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8370         if (!intel_fb) {
8371                 DRM_DEBUG_KMS("failed to alloc fb\n");
8372                 return;
8373         }
8374
8375         fb = &intel_fb->base;
8376
8377         fb->dev = dev;
8378
8379         val = I915_READ(PLANE_CTL(pipe, 0));
8380         if (!(val & PLANE_CTL_ENABLE))
8381                 goto error;
8382
8383         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8384         fourcc = skl_format_to_fourcc(pixel_format,
8385                                       val & PLANE_CTL_ORDER_RGBX,
8386                                       val & PLANE_CTL_ALPHA_MASK);
8387         fb->format = drm_format_info(fourcc);
8388
8389         tiling = val & PLANE_CTL_TILED_MASK;
8390         switch (tiling) {
8391         case PLANE_CTL_TILED_LINEAR:
8392                 fb->modifier = DRM_FORMAT_MOD_NONE;
8393                 break;
8394         case PLANE_CTL_TILED_X:
8395                 plane_config->tiling = I915_TILING_X;
8396                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8397                 break;
8398         case PLANE_CTL_TILED_Y:
8399                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8400                 break;
8401         case PLANE_CTL_TILED_YF:
8402                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8403                 break;
8404         default:
8405                 MISSING_CASE(tiling);
8406                 goto error;
8407         }
8408
8409         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8410         plane_config->base = base;
8411
8412         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8413
8414         val = I915_READ(PLANE_SIZE(pipe, 0));
8415         fb->height = ((val >> 16) & 0xfff) + 1;
8416         fb->width = ((val >> 0) & 0x1fff) + 1;
8417
8418         val = I915_READ(PLANE_STRIDE(pipe, 0));
8419         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
8420                                                 fb->format->format);
8421         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8422
8423         aligned_height = intel_fb_align_height(dev_priv,
8424                                                fb->height,
8425                                                fb->format->format,
8426                                                fb->modifier);
8427
8428         plane_config->size = fb->pitches[0] * aligned_height;
8429
8430         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8431                       pipe_name(pipe), fb->width, fb->height,
8432                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8433                       plane_config->size);
8434
8435         plane_config->fb = intel_fb;
8436         return;
8437
8438 error:
8439         kfree(intel_fb);
8440 }
8441
8442 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8443                                      struct intel_crtc_state *pipe_config)
8444 {
8445         struct drm_device *dev = crtc->base.dev;
8446         struct drm_i915_private *dev_priv = to_i915(dev);
8447         uint32_t tmp;
8448
8449         tmp = I915_READ(PF_CTL(crtc->pipe));
8450
8451         if (tmp & PF_ENABLE) {
8452                 pipe_config->pch_pfit.enabled = true;
8453                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8454                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8455
8456                 /* We currently do not free assignements of panel fitters on
8457                  * ivb/hsw (since we don't use the higher upscaling modes which
8458                  * differentiates them) so just WARN about this case for now. */
8459                 if (IS_GEN7(dev_priv)) {
8460                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8461                                 PF_PIPE_SEL_IVB(crtc->pipe));
8462                 }
8463         }
8464 }
8465
8466 static void
8467 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8468                                   struct intel_initial_plane_config *plane_config)
8469 {
8470         struct drm_device *dev = crtc->base.dev;
8471         struct drm_i915_private *dev_priv = to_i915(dev);
8472         u32 val, base, offset;
8473         int pipe = crtc->pipe;
8474         int fourcc, pixel_format;
8475         unsigned int aligned_height;
8476         struct drm_framebuffer *fb;
8477         struct intel_framebuffer *intel_fb;
8478
8479         val = I915_READ(DSPCNTR(pipe));
8480         if (!(val & DISPLAY_PLANE_ENABLE))
8481                 return;
8482
8483         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8484         if (!intel_fb) {
8485                 DRM_DEBUG_KMS("failed to alloc fb\n");
8486                 return;
8487         }
8488
8489         fb = &intel_fb->base;
8490
8491         fb->dev = dev;
8492
8493         if (INTEL_GEN(dev_priv) >= 4) {
8494                 if (val & DISPPLANE_TILED) {
8495                         plane_config->tiling = I915_TILING_X;
8496                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8497                 }
8498         }
8499
8500         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8501         fourcc = i9xx_format_to_fourcc(pixel_format);
8502         fb->format = drm_format_info(fourcc);
8503
8504         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8505         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8506                 offset = I915_READ(DSPOFFSET(pipe));
8507         } else {
8508                 if (plane_config->tiling)
8509                         offset = I915_READ(DSPTILEOFF(pipe));
8510                 else
8511                         offset = I915_READ(DSPLINOFF(pipe));
8512         }
8513         plane_config->base = base;
8514
8515         val = I915_READ(PIPESRC(pipe));
8516         fb->width = ((val >> 16) & 0xfff) + 1;
8517         fb->height = ((val >> 0) & 0xfff) + 1;
8518
8519         val = I915_READ(DSPSTRIDE(pipe));
8520         fb->pitches[0] = val & 0xffffffc0;
8521
8522         aligned_height = intel_fb_align_height(dev_priv,
8523                                                fb->height,
8524                                                fb->format->format,
8525                                                fb->modifier);
8526
8527         plane_config->size = fb->pitches[0] * aligned_height;
8528
8529         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8530                       pipe_name(pipe), fb->width, fb->height,
8531                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8532                       plane_config->size);
8533
8534         plane_config->fb = intel_fb;
8535 }
8536
8537 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8538                                      struct intel_crtc_state *pipe_config)
8539 {
8540         struct drm_device *dev = crtc->base.dev;
8541         struct drm_i915_private *dev_priv = to_i915(dev);
8542         enum intel_display_power_domain power_domain;
8543         uint32_t tmp;
8544         bool ret;
8545
8546         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8547         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8548                 return false;
8549
8550         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8551         pipe_config->shared_dpll = NULL;
8552
8553         ret = false;
8554         tmp = I915_READ(PIPECONF(crtc->pipe));
8555         if (!(tmp & PIPECONF_ENABLE))
8556                 goto out;
8557
8558         switch (tmp & PIPECONF_BPC_MASK) {
8559         case PIPECONF_6BPC:
8560                 pipe_config->pipe_bpp = 18;
8561                 break;
8562         case PIPECONF_8BPC:
8563                 pipe_config->pipe_bpp = 24;
8564                 break;
8565         case PIPECONF_10BPC:
8566                 pipe_config->pipe_bpp = 30;
8567                 break;
8568         case PIPECONF_12BPC:
8569                 pipe_config->pipe_bpp = 36;
8570                 break;
8571         default:
8572                 break;
8573         }
8574
8575         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8576                 pipe_config->limited_color_range = true;
8577
8578         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8579                 struct intel_shared_dpll *pll;
8580                 enum intel_dpll_id pll_id;
8581
8582                 pipe_config->has_pch_encoder = true;
8583
8584                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8585                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8586                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8587
8588                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8589
8590                 if (HAS_PCH_IBX(dev_priv)) {
8591                         /*
8592                          * The pipe->pch transcoder and pch transcoder->pll
8593                          * mapping is fixed.
8594                          */
8595                         pll_id = (enum intel_dpll_id) crtc->pipe;
8596                 } else {
8597                         tmp = I915_READ(PCH_DPLL_SEL);
8598                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8599                                 pll_id = DPLL_ID_PCH_PLL_B;
8600                         else
8601                                 pll_id= DPLL_ID_PCH_PLL_A;
8602                 }
8603
8604                 pipe_config->shared_dpll =
8605                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8606                 pll = pipe_config->shared_dpll;
8607
8608                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8609                                                  &pipe_config->dpll_hw_state));
8610
8611                 tmp = pipe_config->dpll_hw_state.dpll;
8612                 pipe_config->pixel_multiplier =
8613                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8614                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8615
8616                 ironlake_pch_clock_get(crtc, pipe_config);
8617         } else {
8618                 pipe_config->pixel_multiplier = 1;
8619         }
8620
8621         intel_get_pipe_timings(crtc, pipe_config);
8622         intel_get_pipe_src_size(crtc, pipe_config);
8623
8624         ironlake_get_pfit_config(crtc, pipe_config);
8625
8626         ret = true;
8627
8628 out:
8629         intel_display_power_put(dev_priv, power_domain);
8630
8631         return ret;
8632 }
8633
8634 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8635 {
8636         struct drm_device *dev = &dev_priv->drm;
8637         struct intel_crtc *crtc;
8638
8639         for_each_intel_crtc(dev, crtc)
8640                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8641                      pipe_name(crtc->pipe));
8642
8643         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8644         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8645         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8646         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8647         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8648         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8649              "CPU PWM1 enabled\n");
8650         if (IS_HASWELL(dev_priv))
8651                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8652                      "CPU PWM2 enabled\n");
8653         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8654              "PCH PWM1 enabled\n");
8655         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8656              "Utility pin enabled\n");
8657         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8658
8659         /*
8660          * In theory we can still leave IRQs enabled, as long as only the HPD
8661          * interrupts remain enabled. We used to check for that, but since it's
8662          * gen-specific and since we only disable LCPLL after we fully disable
8663          * the interrupts, the check below should be enough.
8664          */
8665         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8666 }
8667
8668 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8669 {
8670         if (IS_HASWELL(dev_priv))
8671                 return I915_READ(D_COMP_HSW);
8672         else
8673                 return I915_READ(D_COMP_BDW);
8674 }
8675
8676 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8677 {
8678         if (IS_HASWELL(dev_priv)) {
8679                 mutex_lock(&dev_priv->rps.hw_lock);
8680                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8681                                             val))
8682                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8683                 mutex_unlock(&dev_priv->rps.hw_lock);
8684         } else {
8685                 I915_WRITE(D_COMP_BDW, val);
8686                 POSTING_READ(D_COMP_BDW);
8687         }
8688 }
8689
8690 /*
8691  * This function implements pieces of two sequences from BSpec:
8692  * - Sequence for display software to disable LCPLL
8693  * - Sequence for display software to allow package C8+
8694  * The steps implemented here are just the steps that actually touch the LCPLL
8695  * register. Callers should take care of disabling all the display engine
8696  * functions, doing the mode unset, fixing interrupts, etc.
8697  */
8698 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8699                               bool switch_to_fclk, bool allow_power_down)
8700 {
8701         uint32_t val;
8702
8703         assert_can_disable_lcpll(dev_priv);
8704
8705         val = I915_READ(LCPLL_CTL);
8706
8707         if (switch_to_fclk) {
8708                 val |= LCPLL_CD_SOURCE_FCLK;
8709                 I915_WRITE(LCPLL_CTL, val);
8710
8711                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8712                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8713                         DRM_ERROR("Switching to FCLK failed\n");
8714
8715                 val = I915_READ(LCPLL_CTL);
8716         }
8717
8718         val |= LCPLL_PLL_DISABLE;
8719         I915_WRITE(LCPLL_CTL, val);
8720         POSTING_READ(LCPLL_CTL);
8721
8722         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8723                 DRM_ERROR("LCPLL still locked\n");
8724
8725         val = hsw_read_dcomp(dev_priv);
8726         val |= D_COMP_COMP_DISABLE;
8727         hsw_write_dcomp(dev_priv, val);
8728         ndelay(100);
8729
8730         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8731                      1))
8732                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8733
8734         if (allow_power_down) {
8735                 val = I915_READ(LCPLL_CTL);
8736                 val |= LCPLL_POWER_DOWN_ALLOW;
8737                 I915_WRITE(LCPLL_CTL, val);
8738                 POSTING_READ(LCPLL_CTL);
8739         }
8740 }
8741
8742 /*
8743  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8744  * source.
8745  */
8746 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8747 {
8748         uint32_t val;
8749
8750         val = I915_READ(LCPLL_CTL);
8751
8752         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8753                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8754                 return;
8755
8756         /*
8757          * Make sure we're not on PC8 state before disabling PC8, otherwise
8758          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8759          */
8760         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8761
8762         if (val & LCPLL_POWER_DOWN_ALLOW) {
8763                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8764                 I915_WRITE(LCPLL_CTL, val);
8765                 POSTING_READ(LCPLL_CTL);
8766         }
8767
8768         val = hsw_read_dcomp(dev_priv);
8769         val |= D_COMP_COMP_FORCE;
8770         val &= ~D_COMP_COMP_DISABLE;
8771         hsw_write_dcomp(dev_priv, val);
8772
8773         val = I915_READ(LCPLL_CTL);
8774         val &= ~LCPLL_PLL_DISABLE;
8775         I915_WRITE(LCPLL_CTL, val);
8776
8777         if (intel_wait_for_register(dev_priv,
8778                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8779                                     5))
8780                 DRM_ERROR("LCPLL not locked yet\n");
8781
8782         if (val & LCPLL_CD_SOURCE_FCLK) {
8783                 val = I915_READ(LCPLL_CTL);
8784                 val &= ~LCPLL_CD_SOURCE_FCLK;
8785                 I915_WRITE(LCPLL_CTL, val);
8786
8787                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8788                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8789                         DRM_ERROR("Switching back to LCPLL failed\n");
8790         }
8791
8792         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8793         intel_update_cdclk(dev_priv);
8794 }
8795
8796 /*
8797  * Package states C8 and deeper are really deep PC states that can only be
8798  * reached when all the devices on the system allow it, so even if the graphics
8799  * device allows PC8+, it doesn't mean the system will actually get to these
8800  * states. Our driver only allows PC8+ when going into runtime PM.
8801  *
8802  * The requirements for PC8+ are that all the outputs are disabled, the power
8803  * well is disabled and most interrupts are disabled, and these are also
8804  * requirements for runtime PM. When these conditions are met, we manually do
8805  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8806  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8807  * hang the machine.
8808  *
8809  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8810  * the state of some registers, so when we come back from PC8+ we need to
8811  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8812  * need to take care of the registers kept by RC6. Notice that this happens even
8813  * if we don't put the device in PCI D3 state (which is what currently happens
8814  * because of the runtime PM support).
8815  *
8816  * For more, read "Display Sequences for Package C8" on the hardware
8817  * documentation.
8818  */
8819 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8820 {
8821         uint32_t val;
8822
8823         DRM_DEBUG_KMS("Enabling package C8+\n");
8824
8825         if (HAS_PCH_LPT_LP(dev_priv)) {
8826                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8827                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8828                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8829         }
8830
8831         lpt_disable_clkout_dp(dev_priv);
8832         hsw_disable_lcpll(dev_priv, true, true);
8833 }
8834
8835 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8836 {
8837         uint32_t val;
8838
8839         DRM_DEBUG_KMS("Disabling package C8+\n");
8840
8841         hsw_restore_lcpll(dev_priv);
8842         lpt_init_pch_refclk(dev_priv);
8843
8844         if (HAS_PCH_LPT_LP(dev_priv)) {
8845                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8846                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8847                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8848         }
8849 }
8850
8851 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8852                                       struct intel_crtc_state *crtc_state)
8853 {
8854         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8855                 if (!intel_ddi_pll_select(crtc, crtc_state))
8856                         return -EINVAL;
8857         }
8858
8859         crtc->lowfreq_avail = false;
8860
8861         return 0;
8862 }
8863
8864 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8865                                 enum port port,
8866                                 struct intel_crtc_state *pipe_config)
8867 {
8868         enum intel_dpll_id id;
8869
8870         switch (port) {
8871         case PORT_A:
8872                 id = DPLL_ID_SKL_DPLL0;
8873                 break;
8874         case PORT_B:
8875                 id = DPLL_ID_SKL_DPLL1;
8876                 break;
8877         case PORT_C:
8878                 id = DPLL_ID_SKL_DPLL2;
8879                 break;
8880         default:
8881                 DRM_ERROR("Incorrect port type\n");
8882                 return;
8883         }
8884
8885         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8886 }
8887
8888 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8889                                 enum port port,
8890                                 struct intel_crtc_state *pipe_config)
8891 {
8892         enum intel_dpll_id id;
8893         u32 temp;
8894
8895         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8896         id = temp >> (port * 3 + 1);
8897
8898         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8899                 return;
8900
8901         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8902 }
8903
8904 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8905                                 enum port port,
8906                                 struct intel_crtc_state *pipe_config)
8907 {
8908         enum intel_dpll_id id;
8909         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8910
8911         switch (ddi_pll_sel) {
8912         case PORT_CLK_SEL_WRPLL1:
8913                 id = DPLL_ID_WRPLL1;
8914                 break;
8915         case PORT_CLK_SEL_WRPLL2:
8916                 id = DPLL_ID_WRPLL2;
8917                 break;
8918         case PORT_CLK_SEL_SPLL:
8919                 id = DPLL_ID_SPLL;
8920                 break;
8921         case PORT_CLK_SEL_LCPLL_810:
8922                 id = DPLL_ID_LCPLL_810;
8923                 break;
8924         case PORT_CLK_SEL_LCPLL_1350:
8925                 id = DPLL_ID_LCPLL_1350;
8926                 break;
8927         case PORT_CLK_SEL_LCPLL_2700:
8928                 id = DPLL_ID_LCPLL_2700;
8929                 break;
8930         default:
8931                 MISSING_CASE(ddi_pll_sel);
8932                 /* fall through */
8933         case PORT_CLK_SEL_NONE:
8934                 return;
8935         }
8936
8937         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8938 }
8939
8940 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8941                                      struct intel_crtc_state *pipe_config,
8942                                      u64 *power_domain_mask)
8943 {
8944         struct drm_device *dev = crtc->base.dev;
8945         struct drm_i915_private *dev_priv = to_i915(dev);
8946         enum intel_display_power_domain power_domain;
8947         u32 tmp;
8948
8949         /*
8950          * The pipe->transcoder mapping is fixed with the exception of the eDP
8951          * transcoder handled below.
8952          */
8953         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8954
8955         /*
8956          * XXX: Do intel_display_power_get_if_enabled before reading this (for
8957          * consistency and less surprising code; it's in always on power).
8958          */
8959         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8960         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8961                 enum pipe trans_edp_pipe;
8962                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8963                 default:
8964                         WARN(1, "unknown pipe linked to edp transcoder\n");
8965                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8966                 case TRANS_DDI_EDP_INPUT_A_ON:
8967                         trans_edp_pipe = PIPE_A;
8968                         break;
8969                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8970                         trans_edp_pipe = PIPE_B;
8971                         break;
8972                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8973                         trans_edp_pipe = PIPE_C;
8974                         break;
8975                 }
8976
8977                 if (trans_edp_pipe == crtc->pipe)
8978                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8979         }
8980
8981         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8982         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8983                 return false;
8984         *power_domain_mask |= BIT_ULL(power_domain);
8985
8986         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8987
8988         return tmp & PIPECONF_ENABLE;
8989 }
8990
8991 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8992                                          struct intel_crtc_state *pipe_config,
8993                                          u64 *power_domain_mask)
8994 {
8995         struct drm_device *dev = crtc->base.dev;
8996         struct drm_i915_private *dev_priv = to_i915(dev);
8997         enum intel_display_power_domain power_domain;
8998         enum port port;
8999         enum transcoder cpu_transcoder;
9000         u32 tmp;
9001
9002         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9003                 if (port == PORT_A)
9004                         cpu_transcoder = TRANSCODER_DSI_A;
9005                 else
9006                         cpu_transcoder = TRANSCODER_DSI_C;
9007
9008                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9009                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9010                         continue;
9011                 *power_domain_mask |= BIT_ULL(power_domain);
9012
9013                 /*
9014                  * The PLL needs to be enabled with a valid divider
9015                  * configuration, otherwise accessing DSI registers will hang
9016                  * the machine. See BSpec North Display Engine
9017                  * registers/MIPI[BXT]. We can break out here early, since we
9018                  * need the same DSI PLL to be enabled for both DSI ports.
9019                  */
9020                 if (!intel_dsi_pll_is_enabled(dev_priv))
9021                         break;
9022
9023                 /* XXX: this works for video mode only */
9024                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9025                 if (!(tmp & DPI_ENABLE))
9026                         continue;
9027
9028                 tmp = I915_READ(MIPI_CTRL(port));
9029                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9030                         continue;
9031
9032                 pipe_config->cpu_transcoder = cpu_transcoder;
9033                 break;
9034         }
9035
9036         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9037 }
9038
9039 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9040                                        struct intel_crtc_state *pipe_config)
9041 {
9042         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9043         struct intel_shared_dpll *pll;
9044         enum port port;
9045         uint32_t tmp;
9046
9047         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9048
9049         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9050
9051         if (IS_GEN9_BC(dev_priv))
9052                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9053         else if (IS_GEN9_LP(dev_priv))
9054                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9055         else
9056                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9057
9058         pll = pipe_config->shared_dpll;
9059         if (pll) {
9060                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9061                                                  &pipe_config->dpll_hw_state));
9062         }
9063
9064         /*
9065          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9066          * DDI E. So just check whether this pipe is wired to DDI E and whether
9067          * the PCH transcoder is on.
9068          */
9069         if (INTEL_GEN(dev_priv) < 9 &&
9070             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9071                 pipe_config->has_pch_encoder = true;
9072
9073                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9074                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9075                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9076
9077                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9078         }
9079 }
9080
9081 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9082                                     struct intel_crtc_state *pipe_config)
9083 {
9084         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9085         enum intel_display_power_domain power_domain;
9086         u64 power_domain_mask;
9087         bool active;
9088
9089         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9090         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9091                 return false;
9092         power_domain_mask = BIT_ULL(power_domain);
9093
9094         pipe_config->shared_dpll = NULL;
9095
9096         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9097
9098         if (IS_GEN9_LP(dev_priv) &&
9099             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9100                 WARN_ON(active);
9101                 active = true;
9102         }
9103
9104         if (!active)
9105                 goto out;
9106
9107         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9108                 haswell_get_ddi_port_state(crtc, pipe_config);
9109                 intel_get_pipe_timings(crtc, pipe_config);
9110         }
9111
9112         intel_get_pipe_src_size(crtc, pipe_config);
9113
9114         pipe_config->gamma_mode =
9115                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9116
9117         if (INTEL_GEN(dev_priv) >= 9) {
9118                 intel_crtc_init_scalers(crtc, pipe_config);
9119
9120                 pipe_config->scaler_state.scaler_id = -1;
9121                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9122         }
9123
9124         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9125         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9126                 power_domain_mask |= BIT_ULL(power_domain);
9127                 if (INTEL_GEN(dev_priv) >= 9)
9128                         skylake_get_pfit_config(crtc, pipe_config);
9129                 else
9130                         ironlake_get_pfit_config(crtc, pipe_config);
9131         }
9132
9133         if (IS_HASWELL(dev_priv))
9134                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9135                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9136
9137         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9138             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9139                 pipe_config->pixel_multiplier =
9140                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9141         } else {
9142                 pipe_config->pixel_multiplier = 1;
9143         }
9144
9145 out:
9146         for_each_power_domain(power_domain, power_domain_mask)
9147                 intel_display_power_put(dev_priv, power_domain);
9148
9149         return active;
9150 }
9151
9152 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9153                                const struct intel_plane_state *plane_state)
9154 {
9155         struct drm_device *dev = crtc->dev;
9156         struct drm_i915_private *dev_priv = to_i915(dev);
9157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9158         uint32_t cntl = 0, size = 0;
9159
9160         if (plane_state && plane_state->base.visible) {
9161                 unsigned int width = plane_state->base.crtc_w;
9162                 unsigned int height = plane_state->base.crtc_h;
9163                 unsigned int stride = roundup_pow_of_two(width) * 4;
9164
9165                 switch (stride) {
9166                 default:
9167                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9168                                   width, stride);
9169                         stride = 256;
9170                         /* fallthrough */
9171                 case 256:
9172                 case 512:
9173                 case 1024:
9174                 case 2048:
9175                         break;
9176                 }
9177
9178                 cntl |= CURSOR_ENABLE |
9179                         CURSOR_GAMMA_ENABLE |
9180                         CURSOR_FORMAT_ARGB |
9181                         CURSOR_STRIDE(stride);
9182
9183                 size = (height << 12) | width;
9184         }
9185
9186         if (intel_crtc->cursor_cntl != 0 &&
9187             (intel_crtc->cursor_base != base ||
9188              intel_crtc->cursor_size != size ||
9189              intel_crtc->cursor_cntl != cntl)) {
9190                 /* On these chipsets we can only modify the base/size/stride
9191                  * whilst the cursor is disabled.
9192                  */
9193                 I915_WRITE(CURCNTR(PIPE_A), 0);
9194                 POSTING_READ(CURCNTR(PIPE_A));
9195                 intel_crtc->cursor_cntl = 0;
9196         }
9197
9198         if (intel_crtc->cursor_base != base) {
9199                 I915_WRITE(CURBASE(PIPE_A), base);
9200                 intel_crtc->cursor_base = base;
9201         }
9202
9203         if (intel_crtc->cursor_size != size) {
9204                 I915_WRITE(CURSIZE, size);
9205                 intel_crtc->cursor_size = size;
9206         }
9207
9208         if (intel_crtc->cursor_cntl != cntl) {
9209                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9210                 POSTING_READ(CURCNTR(PIPE_A));
9211                 intel_crtc->cursor_cntl = cntl;
9212         }
9213 }
9214
9215 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9216                                const struct intel_plane_state *plane_state)
9217 {
9218         struct drm_device *dev = crtc->dev;
9219         struct drm_i915_private *dev_priv = to_i915(dev);
9220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9221         int pipe = intel_crtc->pipe;
9222         uint32_t cntl = 0;
9223
9224         if (plane_state && plane_state->base.visible) {
9225                 cntl = MCURSOR_GAMMA_ENABLE;
9226                 switch (plane_state->base.crtc_w) {
9227                         case 64:
9228                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9229                                 break;
9230                         case 128:
9231                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9232                                 break;
9233                         case 256:
9234                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9235                                 break;
9236                         default:
9237                                 MISSING_CASE(plane_state->base.crtc_w);
9238                                 return;
9239                 }
9240                 cntl |= pipe << 28; /* Connect to correct pipe */
9241
9242                 if (HAS_DDI(dev_priv))
9243                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9244
9245                 if (plane_state->base.rotation & DRM_ROTATE_180)
9246                         cntl |= CURSOR_ROTATE_180;
9247         }
9248
9249         if (intel_crtc->cursor_cntl != cntl) {
9250                 I915_WRITE(CURCNTR(pipe), cntl);
9251                 POSTING_READ(CURCNTR(pipe));
9252                 intel_crtc->cursor_cntl = cntl;
9253         }
9254
9255         /* and commit changes on next vblank */
9256         I915_WRITE(CURBASE(pipe), base);
9257         POSTING_READ(CURBASE(pipe));
9258
9259         intel_crtc->cursor_base = base;
9260 }
9261
9262 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9263 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9264                                      const struct intel_plane_state *plane_state)
9265 {
9266         struct drm_device *dev = crtc->dev;
9267         struct drm_i915_private *dev_priv = to_i915(dev);
9268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9269         int pipe = intel_crtc->pipe;
9270         u32 base = intel_crtc->cursor_addr;
9271         u32 pos = 0;
9272
9273         if (plane_state) {
9274                 int x = plane_state->base.crtc_x;
9275                 int y = plane_state->base.crtc_y;
9276
9277                 if (x < 0) {
9278                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9279                         x = -x;
9280                 }
9281                 pos |= x << CURSOR_X_SHIFT;
9282
9283                 if (y < 0) {
9284                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9285                         y = -y;
9286                 }
9287                 pos |= y << CURSOR_Y_SHIFT;
9288
9289                 /* ILK+ do this automagically */
9290                 if (HAS_GMCH_DISPLAY(dev_priv) &&
9291                     plane_state->base.rotation & DRM_ROTATE_180) {
9292                         base += (plane_state->base.crtc_h *
9293                                  plane_state->base.crtc_w - 1) * 4;
9294                 }
9295         }
9296
9297         I915_WRITE(CURPOS(pipe), pos);
9298
9299         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9300                 i845_update_cursor(crtc, base, plane_state);
9301         else
9302                 i9xx_update_cursor(crtc, base, plane_state);
9303 }
9304
9305 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9306                            uint32_t width, uint32_t height)
9307 {
9308         if (width == 0 || height == 0)
9309                 return false;
9310
9311         /*
9312          * 845g/865g are special in that they are only limited by
9313          * the width of their cursors, the height is arbitrary up to
9314          * the precision of the register. Everything else requires
9315          * square cursors, limited to a few power-of-two sizes.
9316          */
9317         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9318                 if ((width & 63) != 0)
9319                         return false;
9320
9321                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9322                         return false;
9323
9324                 if (height > 1023)
9325                         return false;
9326         } else {
9327                 switch (width | height) {
9328                 case 256:
9329                 case 128:
9330                         if (IS_GEN2(dev_priv))
9331                                 return false;
9332                 case 64:
9333                         break;
9334                 default:
9335                         return false;
9336                 }
9337         }
9338
9339         return true;
9340 }
9341
9342 /* VESA 640x480x72Hz mode to set on the pipe */
9343 static struct drm_display_mode load_detect_mode = {
9344         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9345                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9346 };
9347
9348 struct drm_framebuffer *
9349 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9350                          struct drm_mode_fb_cmd2 *mode_cmd)
9351 {
9352         struct intel_framebuffer *intel_fb;
9353         int ret;
9354
9355         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9356         if (!intel_fb)
9357                 return ERR_PTR(-ENOMEM);
9358
9359         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9360         if (ret)
9361                 goto err;
9362
9363         return &intel_fb->base;
9364
9365 err:
9366         kfree(intel_fb);
9367         return ERR_PTR(ret);
9368 }
9369
9370 static u32
9371 intel_framebuffer_pitch_for_width(int width, int bpp)
9372 {
9373         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9374         return ALIGN(pitch, 64);
9375 }
9376
9377 static u32
9378 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9379 {
9380         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9381         return PAGE_ALIGN(pitch * mode->vdisplay);
9382 }
9383
9384 static struct drm_framebuffer *
9385 intel_framebuffer_create_for_mode(struct drm_device *dev,
9386                                   struct drm_display_mode *mode,
9387                                   int depth, int bpp)
9388 {
9389         struct drm_framebuffer *fb;
9390         struct drm_i915_gem_object *obj;
9391         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9392
9393         obj = i915_gem_object_create(to_i915(dev),
9394                                     intel_framebuffer_size_for_mode(mode, bpp));
9395         if (IS_ERR(obj))
9396                 return ERR_CAST(obj);
9397
9398         mode_cmd.width = mode->hdisplay;
9399         mode_cmd.height = mode->vdisplay;
9400         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9401                                                                 bpp);
9402         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9403
9404         fb = intel_framebuffer_create(obj, &mode_cmd);
9405         if (IS_ERR(fb))
9406                 i915_gem_object_put(obj);
9407
9408         return fb;
9409 }
9410
9411 static struct drm_framebuffer *
9412 mode_fits_in_fbdev(struct drm_device *dev,
9413                    struct drm_display_mode *mode)
9414 {
9415 #ifdef CONFIG_DRM_FBDEV_EMULATION
9416         struct drm_i915_private *dev_priv = to_i915(dev);
9417         struct drm_i915_gem_object *obj;
9418         struct drm_framebuffer *fb;
9419
9420         if (!dev_priv->fbdev)
9421                 return NULL;
9422
9423         if (!dev_priv->fbdev->fb)
9424                 return NULL;
9425
9426         obj = dev_priv->fbdev->fb->obj;
9427         BUG_ON(!obj);
9428
9429         fb = &dev_priv->fbdev->fb->base;
9430         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9431                                                                fb->format->cpp[0] * 8))
9432                 return NULL;
9433
9434         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9435                 return NULL;
9436
9437         drm_framebuffer_reference(fb);
9438         return fb;
9439 #else
9440         return NULL;
9441 #endif
9442 }
9443
9444 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9445                                            struct drm_crtc *crtc,
9446                                            struct drm_display_mode *mode,
9447                                            struct drm_framebuffer *fb,
9448                                            int x, int y)
9449 {
9450         struct drm_plane_state *plane_state;
9451         int hdisplay, vdisplay;
9452         int ret;
9453
9454         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9455         if (IS_ERR(plane_state))
9456                 return PTR_ERR(plane_state);
9457
9458         if (mode)
9459                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9460         else
9461                 hdisplay = vdisplay = 0;
9462
9463         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9464         if (ret)
9465                 return ret;
9466         drm_atomic_set_fb_for_plane(plane_state, fb);
9467         plane_state->crtc_x = 0;
9468         plane_state->crtc_y = 0;
9469         plane_state->crtc_w = hdisplay;
9470         plane_state->crtc_h = vdisplay;
9471         plane_state->src_x = x << 16;
9472         plane_state->src_y = y << 16;
9473         plane_state->src_w = hdisplay << 16;
9474         plane_state->src_h = vdisplay << 16;
9475
9476         return 0;
9477 }
9478
9479 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9480                                 struct drm_display_mode *mode,
9481                                 struct intel_load_detect_pipe *old,
9482                                 struct drm_modeset_acquire_ctx *ctx)
9483 {
9484         struct intel_crtc *intel_crtc;
9485         struct intel_encoder *intel_encoder =
9486                 intel_attached_encoder(connector);
9487         struct drm_crtc *possible_crtc;
9488         struct drm_encoder *encoder = &intel_encoder->base;
9489         struct drm_crtc *crtc = NULL;
9490         struct drm_device *dev = encoder->dev;
9491         struct drm_i915_private *dev_priv = to_i915(dev);
9492         struct drm_framebuffer *fb;
9493         struct drm_mode_config *config = &dev->mode_config;
9494         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9495         struct drm_connector_state *connector_state;
9496         struct intel_crtc_state *crtc_state;
9497         int ret, i = -1;
9498
9499         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9500                       connector->base.id, connector->name,
9501                       encoder->base.id, encoder->name);
9502
9503         old->restore_state = NULL;
9504
9505 retry:
9506         ret = drm_modeset_lock(&config->connection_mutex, ctx);
9507         if (ret)
9508                 goto fail;
9509
9510         /*
9511          * Algorithm gets a little messy:
9512          *
9513          *   - if the connector already has an assigned crtc, use it (but make
9514          *     sure it's on first)
9515          *
9516          *   - try to find the first unused crtc that can drive this connector,
9517          *     and use that if we find one
9518          */
9519
9520         /* See if we already have a CRTC for this connector */
9521         if (connector->state->crtc) {
9522                 crtc = connector->state->crtc;
9523
9524                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9525                 if (ret)
9526                         goto fail;
9527
9528                 /* Make sure the crtc and connector are running */
9529                 goto found;
9530         }
9531
9532         /* Find an unused one (if possible) */
9533         for_each_crtc(dev, possible_crtc) {
9534                 i++;
9535                 if (!(encoder->possible_crtcs & (1 << i)))
9536                         continue;
9537
9538                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9539                 if (ret)
9540                         goto fail;
9541
9542                 if (possible_crtc->state->enable) {
9543                         drm_modeset_unlock(&possible_crtc->mutex);
9544                         continue;
9545                 }
9546
9547                 crtc = possible_crtc;
9548                 break;
9549         }
9550
9551         /*
9552          * If we didn't find an unused CRTC, don't use any.
9553          */
9554         if (!crtc) {
9555                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9556                 goto fail;
9557         }
9558
9559 found:
9560         intel_crtc = to_intel_crtc(crtc);
9561
9562         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9563         if (ret)
9564                 goto fail;
9565
9566         state = drm_atomic_state_alloc(dev);
9567         restore_state = drm_atomic_state_alloc(dev);
9568         if (!state || !restore_state) {
9569                 ret = -ENOMEM;
9570                 goto fail;
9571         }
9572
9573         state->acquire_ctx = ctx;
9574         restore_state->acquire_ctx = ctx;
9575
9576         connector_state = drm_atomic_get_connector_state(state, connector);
9577         if (IS_ERR(connector_state)) {
9578                 ret = PTR_ERR(connector_state);
9579                 goto fail;
9580         }
9581
9582         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9583         if (ret)
9584                 goto fail;
9585
9586         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9587         if (IS_ERR(crtc_state)) {
9588                 ret = PTR_ERR(crtc_state);
9589                 goto fail;
9590         }
9591
9592         crtc_state->base.active = crtc_state->base.enable = true;
9593
9594         if (!mode)
9595                 mode = &load_detect_mode;
9596
9597         /* We need a framebuffer large enough to accommodate all accesses
9598          * that the plane may generate whilst we perform load detection.
9599          * We can not rely on the fbcon either being present (we get called
9600          * during its initialisation to detect all boot displays, or it may
9601          * not even exist) or that it is large enough to satisfy the
9602          * requested mode.
9603          */
9604         fb = mode_fits_in_fbdev(dev, mode);
9605         if (fb == NULL) {
9606                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9607                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9608         } else
9609                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9610         if (IS_ERR(fb)) {
9611                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9612                 goto fail;
9613         }
9614
9615         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9616         if (ret)
9617                 goto fail;
9618
9619         drm_framebuffer_unreference(fb);
9620
9621         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9622         if (ret)
9623                 goto fail;
9624
9625         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9626         if (!ret)
9627                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9628         if (!ret)
9629                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9630         if (ret) {
9631                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9632                 goto fail;
9633         }
9634
9635         ret = drm_atomic_commit(state);
9636         if (ret) {
9637                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9638                 goto fail;
9639         }
9640
9641         old->restore_state = restore_state;
9642         drm_atomic_state_put(state);
9643
9644         /* let the connector get through one full cycle before testing */
9645         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9646         return true;
9647
9648 fail:
9649         if (state) {
9650                 drm_atomic_state_put(state);
9651                 state = NULL;
9652         }
9653         if (restore_state) {
9654                 drm_atomic_state_put(restore_state);
9655                 restore_state = NULL;
9656         }
9657
9658         if (ret == -EDEADLK) {
9659                 drm_modeset_backoff(ctx);
9660                 goto retry;
9661         }
9662
9663         return false;
9664 }
9665
9666 void intel_release_load_detect_pipe(struct drm_connector *connector,
9667                                     struct intel_load_detect_pipe *old,
9668                                     struct drm_modeset_acquire_ctx *ctx)
9669 {
9670         struct intel_encoder *intel_encoder =
9671                 intel_attached_encoder(connector);
9672         struct drm_encoder *encoder = &intel_encoder->base;
9673         struct drm_atomic_state *state = old->restore_state;
9674         int ret;
9675
9676         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9677                       connector->base.id, connector->name,
9678                       encoder->base.id, encoder->name);
9679
9680         if (!state)
9681                 return;
9682
9683         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9684         if (ret)
9685                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9686         drm_atomic_state_put(state);
9687 }
9688
9689 static int i9xx_pll_refclk(struct drm_device *dev,
9690                            const struct intel_crtc_state *pipe_config)
9691 {
9692         struct drm_i915_private *dev_priv = to_i915(dev);
9693         u32 dpll = pipe_config->dpll_hw_state.dpll;
9694
9695         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9696                 return dev_priv->vbt.lvds_ssc_freq;
9697         else if (HAS_PCH_SPLIT(dev_priv))
9698                 return 120000;
9699         else if (!IS_GEN2(dev_priv))
9700                 return 96000;
9701         else
9702                 return 48000;
9703 }
9704
9705 /* Returns the clock of the currently programmed mode of the given pipe. */
9706 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9707                                 struct intel_crtc_state *pipe_config)
9708 {
9709         struct drm_device *dev = crtc->base.dev;
9710         struct drm_i915_private *dev_priv = to_i915(dev);
9711         int pipe = pipe_config->cpu_transcoder;
9712         u32 dpll = pipe_config->dpll_hw_state.dpll;
9713         u32 fp;
9714         struct dpll clock;
9715         int port_clock;
9716         int refclk = i9xx_pll_refclk(dev, pipe_config);
9717
9718         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9719                 fp = pipe_config->dpll_hw_state.fp0;
9720         else
9721                 fp = pipe_config->dpll_hw_state.fp1;
9722
9723         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9724         if (IS_PINEVIEW(dev_priv)) {
9725                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9726                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9727         } else {
9728                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9729                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9730         }
9731
9732         if (!IS_GEN2(dev_priv)) {
9733                 if (IS_PINEVIEW(dev_priv))
9734                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9735                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9736                 else
9737                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9738                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9739
9740                 switch (dpll & DPLL_MODE_MASK) {
9741                 case DPLLB_MODE_DAC_SERIAL:
9742                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9743                                 5 : 10;
9744                         break;
9745                 case DPLLB_MODE_LVDS:
9746                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9747                                 7 : 14;
9748                         break;
9749                 default:
9750                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9751                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9752                         return;
9753                 }
9754
9755                 if (IS_PINEVIEW(dev_priv))
9756                         port_clock = pnv_calc_dpll_params(refclk, &clock);
9757                 else
9758                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
9759         } else {
9760                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9761                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9762
9763                 if (is_lvds) {
9764                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9765                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9766
9767                         if (lvds & LVDS_CLKB_POWER_UP)
9768                                 clock.p2 = 7;
9769                         else
9770                                 clock.p2 = 14;
9771                 } else {
9772                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9773                                 clock.p1 = 2;
9774                         else {
9775                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9776                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9777                         }
9778                         if (dpll & PLL_P2_DIVIDE_BY_4)
9779                                 clock.p2 = 4;
9780                         else
9781                                 clock.p2 = 2;
9782                 }
9783
9784                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9785         }
9786
9787         /*
9788          * This value includes pixel_multiplier. We will use
9789          * port_clock to compute adjusted_mode.crtc_clock in the
9790          * encoder's get_config() function.
9791          */
9792         pipe_config->port_clock = port_clock;
9793 }
9794
9795 int intel_dotclock_calculate(int link_freq,
9796                              const struct intel_link_m_n *m_n)
9797 {
9798         /*
9799          * The calculation for the data clock is:
9800          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9801          * But we want to avoid losing precison if possible, so:
9802          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9803          *
9804          * and the link clock is simpler:
9805          * link_clock = (m * link_clock) / n
9806          */
9807
9808         if (!m_n->link_n)
9809                 return 0;
9810
9811         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9812 }
9813
9814 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9815                                    struct intel_crtc_state *pipe_config)
9816 {
9817         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9818
9819         /* read out port_clock from the DPLL */
9820         i9xx_crtc_clock_get(crtc, pipe_config);
9821
9822         /*
9823          * In case there is an active pipe without active ports,
9824          * we may need some idea for the dotclock anyway.
9825          * Calculate one based on the FDI configuration.
9826          */
9827         pipe_config->base.adjusted_mode.crtc_clock =
9828                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9829                                          &pipe_config->fdi_m_n);
9830 }
9831
9832 /** Returns the currently programmed mode of the given pipe. */
9833 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9834                                              struct drm_crtc *crtc)
9835 {
9836         struct drm_i915_private *dev_priv = to_i915(dev);
9837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9838         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9839         struct drm_display_mode *mode;
9840         struct intel_crtc_state *pipe_config;
9841         int htot = I915_READ(HTOTAL(cpu_transcoder));
9842         int hsync = I915_READ(HSYNC(cpu_transcoder));
9843         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9844         int vsync = I915_READ(VSYNC(cpu_transcoder));
9845         enum pipe pipe = intel_crtc->pipe;
9846
9847         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9848         if (!mode)
9849                 return NULL;
9850
9851         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9852         if (!pipe_config) {
9853                 kfree(mode);
9854                 return NULL;
9855         }
9856
9857         /*
9858          * Construct a pipe_config sufficient for getting the clock info
9859          * back out of crtc_clock_get.
9860          *
9861          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9862          * to use a real value here instead.
9863          */
9864         pipe_config->cpu_transcoder = (enum transcoder) pipe;
9865         pipe_config->pixel_multiplier = 1;
9866         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9867         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9868         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9869         i9xx_crtc_clock_get(intel_crtc, pipe_config);
9870
9871         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9872         mode->hdisplay = (htot & 0xffff) + 1;
9873         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9874         mode->hsync_start = (hsync & 0xffff) + 1;
9875         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9876         mode->vdisplay = (vtot & 0xffff) + 1;
9877         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9878         mode->vsync_start = (vsync & 0xffff) + 1;
9879         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9880
9881         drm_mode_set_name(mode);
9882
9883         kfree(pipe_config);
9884
9885         return mode;
9886 }
9887
9888 static void intel_crtc_destroy(struct drm_crtc *crtc)
9889 {
9890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9891         struct drm_device *dev = crtc->dev;
9892         struct intel_flip_work *work;
9893
9894         spin_lock_irq(&dev->event_lock);
9895         work = intel_crtc->flip_work;
9896         intel_crtc->flip_work = NULL;
9897         spin_unlock_irq(&dev->event_lock);
9898
9899         if (work) {
9900                 cancel_work_sync(&work->mmio_work);
9901                 cancel_work_sync(&work->unpin_work);
9902                 kfree(work);
9903         }
9904
9905         drm_crtc_cleanup(crtc);
9906
9907         kfree(intel_crtc);
9908 }
9909
9910 static void intel_unpin_work_fn(struct work_struct *__work)
9911 {
9912         struct intel_flip_work *work =
9913                 container_of(__work, struct intel_flip_work, unpin_work);
9914         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9915         struct drm_device *dev = crtc->base.dev;
9916         struct drm_plane *primary = crtc->base.primary;
9917
9918         if (is_mmio_work(work))
9919                 flush_work(&work->mmio_work);
9920
9921         mutex_lock(&dev->struct_mutex);
9922         intel_unpin_fb_vma(work->old_vma);
9923         i915_gem_object_put(work->pending_flip_obj);
9924         mutex_unlock(&dev->struct_mutex);
9925
9926         i915_gem_request_put(work->flip_queued_req);
9927
9928         intel_frontbuffer_flip_complete(to_i915(dev),
9929                                         to_intel_plane(primary)->frontbuffer_bit);
9930         intel_fbc_post_update(crtc);
9931         drm_framebuffer_unreference(work->old_fb);
9932
9933         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9934         atomic_dec(&crtc->unpin_work_count);
9935
9936         kfree(work);
9937 }
9938
9939 /* Is 'a' after or equal to 'b'? */
9940 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9941 {
9942         return !((a - b) & 0x80000000);
9943 }
9944
9945 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9946                                    struct intel_flip_work *work)
9947 {
9948         struct drm_device *dev = crtc->base.dev;
9949         struct drm_i915_private *dev_priv = to_i915(dev);
9950
9951         if (abort_flip_on_reset(crtc))
9952                 return true;
9953
9954         /*
9955          * The relevant registers doen't exist on pre-ctg.
9956          * As the flip done interrupt doesn't trigger for mmio
9957          * flips on gmch platforms, a flip count check isn't
9958          * really needed there. But since ctg has the registers,
9959          * include it in the check anyway.
9960          */
9961         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9962                 return true;
9963
9964         /*
9965          * BDW signals flip done immediately if the plane
9966          * is disabled, even if the plane enable is already
9967          * armed to occur at the next vblank :(
9968          */
9969
9970         /*
9971          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9972          * used the same base address. In that case the mmio flip might
9973          * have completed, but the CS hasn't even executed the flip yet.
9974          *
9975          * A flip count check isn't enough as the CS might have updated
9976          * the base address just after start of vblank, but before we
9977          * managed to process the interrupt. This means we'd complete the
9978          * CS flip too soon.
9979          *
9980          * Combining both checks should get us a good enough result. It may
9981          * still happen that the CS flip has been executed, but has not
9982          * yet actually completed. But in case the base address is the same
9983          * anyway, we don't really care.
9984          */
9985         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9986                 crtc->flip_work->gtt_offset &&
9987                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
9988                                     crtc->flip_work->flip_count);
9989 }
9990
9991 static bool
9992 __pageflip_finished_mmio(struct intel_crtc *crtc,
9993                                struct intel_flip_work *work)
9994 {
9995         /*
9996          * MMIO work completes when vblank is different from
9997          * flip_queued_vblank.
9998          *
9999          * Reset counter value doesn't matter, this is handled by
10000          * i915_wait_request finishing early, so no need to handle
10001          * reset here.
10002          */
10003         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10004 }
10005
10006
10007 static bool pageflip_finished(struct intel_crtc *crtc,
10008                               struct intel_flip_work *work)
10009 {
10010         if (!atomic_read(&work->pending))
10011                 return false;
10012
10013         smp_rmb();
10014
10015         if (is_mmio_work(work))
10016                 return __pageflip_finished_mmio(crtc, work);
10017         else
10018                 return __pageflip_finished_cs(crtc, work);
10019 }
10020
10021 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10022 {
10023         struct drm_device *dev = &dev_priv->drm;
10024         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10025         struct intel_flip_work *work;
10026         unsigned long flags;
10027
10028         /* Ignore early vblank irqs */
10029         if (!crtc)
10030                 return;
10031
10032         /*
10033          * This is called both by irq handlers and the reset code (to complete
10034          * lost pageflips) so needs the full irqsave spinlocks.
10035          */
10036         spin_lock_irqsave(&dev->event_lock, flags);
10037         work = crtc->flip_work;
10038
10039         if (work != NULL &&
10040             !is_mmio_work(work) &&
10041             pageflip_finished(crtc, work))
10042                 page_flip_completed(crtc);
10043
10044         spin_unlock_irqrestore(&dev->event_lock, flags);
10045 }
10046
10047 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10048 {
10049         struct drm_device *dev = &dev_priv->drm;
10050         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10051         struct intel_flip_work *work;
10052         unsigned long flags;
10053
10054         /* Ignore early vblank irqs */
10055         if (!crtc)
10056                 return;
10057
10058         /*
10059          * This is called both by irq handlers and the reset code (to complete
10060          * lost pageflips) so needs the full irqsave spinlocks.
10061          */
10062         spin_lock_irqsave(&dev->event_lock, flags);
10063         work = crtc->flip_work;
10064
10065         if (work != NULL &&
10066             is_mmio_work(work) &&
10067             pageflip_finished(crtc, work))
10068                 page_flip_completed(crtc);
10069
10070         spin_unlock_irqrestore(&dev->event_lock, flags);
10071 }
10072
10073 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10074                                                struct intel_flip_work *work)
10075 {
10076         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10077
10078         /* Ensure that the work item is consistent when activating it ... */
10079         smp_mb__before_atomic();
10080         atomic_set(&work->pending, 1);
10081 }
10082
10083 static int intel_gen2_queue_flip(struct drm_device *dev,
10084                                  struct drm_crtc *crtc,
10085                                  struct drm_framebuffer *fb,
10086                                  struct drm_i915_gem_object *obj,
10087                                  struct drm_i915_gem_request *req,
10088                                  uint32_t flags)
10089 {
10090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10091         u32 flip_mask, *cs;
10092
10093         cs = intel_ring_begin(req, 6);
10094         if (IS_ERR(cs))
10095                 return PTR_ERR(cs);
10096
10097         /* Can't queue multiple flips, so wait for the previous
10098          * one to finish before executing the next.
10099          */
10100         if (intel_crtc->plane)
10101                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10102         else
10103                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10104         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10105         *cs++ = MI_NOOP;
10106         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10107         *cs++ = fb->pitches[0];
10108         *cs++ = intel_crtc->flip_work->gtt_offset;
10109         *cs++ = 0; /* aux display base address, unused */
10110
10111         return 0;
10112 }
10113
10114 static int intel_gen3_queue_flip(struct drm_device *dev,
10115                                  struct drm_crtc *crtc,
10116                                  struct drm_framebuffer *fb,
10117                                  struct drm_i915_gem_object *obj,
10118                                  struct drm_i915_gem_request *req,
10119                                  uint32_t flags)
10120 {
10121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10122         u32 flip_mask, *cs;
10123
10124         cs = intel_ring_begin(req, 6);
10125         if (IS_ERR(cs))
10126                 return PTR_ERR(cs);
10127
10128         if (intel_crtc->plane)
10129                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10130         else
10131                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10132         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10133         *cs++ = MI_NOOP;
10134         *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10135         *cs++ = fb->pitches[0];
10136         *cs++ = intel_crtc->flip_work->gtt_offset;
10137         *cs++ = MI_NOOP;
10138
10139         return 0;
10140 }
10141
10142 static int intel_gen4_queue_flip(struct drm_device *dev,
10143                                  struct drm_crtc *crtc,
10144                                  struct drm_framebuffer *fb,
10145                                  struct drm_i915_gem_object *obj,
10146                                  struct drm_i915_gem_request *req,
10147                                  uint32_t flags)
10148 {
10149         struct drm_i915_private *dev_priv = to_i915(dev);
10150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10151         u32 pf, pipesrc, *cs;
10152
10153         cs = intel_ring_begin(req, 4);
10154         if (IS_ERR(cs))
10155                 return PTR_ERR(cs);
10156
10157         /* i965+ uses the linear or tiled offsets from the
10158          * Display Registers (which do not change across a page-flip)
10159          * so we need only reprogram the base address.
10160          */
10161         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10162         *cs++ = fb->pitches[0];
10163         *cs++ = intel_crtc->flip_work->gtt_offset |
10164                 intel_fb_modifier_to_tiling(fb->modifier);
10165
10166         /* XXX Enabling the panel-fitter across page-flip is so far
10167          * untested on non-native modes, so ignore it for now.
10168          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10169          */
10170         pf = 0;
10171         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10172         *cs++ = pf | pipesrc;
10173
10174         return 0;
10175 }
10176
10177 static int intel_gen6_queue_flip(struct drm_device *dev,
10178                                  struct drm_crtc *crtc,
10179                                  struct drm_framebuffer *fb,
10180                                  struct drm_i915_gem_object *obj,
10181                                  struct drm_i915_gem_request *req,
10182                                  uint32_t flags)
10183 {
10184         struct drm_i915_private *dev_priv = to_i915(dev);
10185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10186         u32 pf, pipesrc, *cs;
10187
10188         cs = intel_ring_begin(req, 4);
10189         if (IS_ERR(cs))
10190                 return PTR_ERR(cs);
10191
10192         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10193         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10194         *cs++ = intel_crtc->flip_work->gtt_offset;
10195
10196         /* Contrary to the suggestions in the documentation,
10197          * "Enable Panel Fitter" does not seem to be required when page
10198          * flipping with a non-native mode, and worse causes a normal
10199          * modeset to fail.
10200          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10201          */
10202         pf = 0;
10203         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10204         *cs++ = pf | pipesrc;
10205
10206         return 0;
10207 }
10208
10209 static int intel_gen7_queue_flip(struct drm_device *dev,
10210                                  struct drm_crtc *crtc,
10211                                  struct drm_framebuffer *fb,
10212                                  struct drm_i915_gem_object *obj,
10213                                  struct drm_i915_gem_request *req,
10214                                  uint32_t flags)
10215 {
10216         struct drm_i915_private *dev_priv = to_i915(dev);
10217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10218         u32 *cs, plane_bit = 0;
10219         int len, ret;
10220
10221         switch (intel_crtc->plane) {
10222         case PLANE_A:
10223                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10224                 break;
10225         case PLANE_B:
10226                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10227                 break;
10228         case PLANE_C:
10229                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10230                 break;
10231         default:
10232                 WARN_ONCE(1, "unknown plane in flip command\n");
10233                 return -ENODEV;
10234         }
10235
10236         len = 4;
10237         if (req->engine->id == RCS) {
10238                 len += 6;
10239                 /*
10240                  * On Gen 8, SRM is now taking an extra dword to accommodate
10241                  * 48bits addresses, and we need a NOOP for the batch size to
10242                  * stay even.
10243                  */
10244                 if (IS_GEN8(dev_priv))
10245                         len += 2;
10246         }
10247
10248         /*
10249          * BSpec MI_DISPLAY_FLIP for IVB:
10250          * "The full packet must be contained within the same cache line."
10251          *
10252          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10253          * cacheline, if we ever start emitting more commands before
10254          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10255          * then do the cacheline alignment, and finally emit the
10256          * MI_DISPLAY_FLIP.
10257          */
10258         ret = intel_ring_cacheline_align(req);
10259         if (ret)
10260                 return ret;
10261
10262         cs = intel_ring_begin(req, len);
10263         if (IS_ERR(cs))
10264                 return PTR_ERR(cs);
10265
10266         /* Unmask the flip-done completion message. Note that the bspec says that
10267          * we should do this for both the BCS and RCS, and that we must not unmask
10268          * more than one flip event at any time (or ensure that one flip message
10269          * can be sent by waiting for flip-done prior to queueing new flips).
10270          * Experimentation says that BCS works despite DERRMR masking all
10271          * flip-done completion events and that unmasking all planes at once
10272          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10273          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10274          */
10275         if (req->engine->id == RCS) {
10276                 *cs++ = MI_LOAD_REGISTER_IMM(1);
10277                 *cs++ = i915_mmio_reg_offset(DERRMR);
10278                 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10279                           DERRMR_PIPEB_PRI_FLIP_DONE |
10280                           DERRMR_PIPEC_PRI_FLIP_DONE);
10281                 if (IS_GEN8(dev_priv))
10282                         *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10283                                 MI_SRM_LRM_GLOBAL_GTT;
10284                 else
10285                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10286                 *cs++ = i915_mmio_reg_offset(DERRMR);
10287                 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10288                 if (IS_GEN8(dev_priv)) {
10289                         *cs++ = 0;
10290                         *cs++ = MI_NOOP;
10291                 }
10292         }
10293
10294         *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10295         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10296         *cs++ = intel_crtc->flip_work->gtt_offset;
10297         *cs++ = MI_NOOP;
10298
10299         return 0;
10300 }
10301
10302 static bool use_mmio_flip(struct intel_engine_cs *engine,
10303                           struct drm_i915_gem_object *obj)
10304 {
10305         /*
10306          * This is not being used for older platforms, because
10307          * non-availability of flip done interrupt forces us to use
10308          * CS flips. Older platforms derive flip done using some clever
10309          * tricks involving the flip_pending status bits and vblank irqs.
10310          * So using MMIO flips there would disrupt this mechanism.
10311          */
10312
10313         if (engine == NULL)
10314                 return true;
10315
10316         if (INTEL_GEN(engine->i915) < 5)
10317                 return false;
10318
10319         if (i915.use_mmio_flip < 0)
10320                 return false;
10321         else if (i915.use_mmio_flip > 0)
10322                 return true;
10323         else if (i915.enable_execlists)
10324                 return true;
10325
10326         return engine != i915_gem_object_last_write_engine(obj);
10327 }
10328
10329 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10330                              unsigned int rotation,
10331                              struct intel_flip_work *work)
10332 {
10333         struct drm_device *dev = intel_crtc->base.dev;
10334         struct drm_i915_private *dev_priv = to_i915(dev);
10335         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10336         const enum pipe pipe = intel_crtc->pipe;
10337         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10338
10339         ctl = I915_READ(PLANE_CTL(pipe, 0));
10340         ctl &= ~PLANE_CTL_TILED_MASK;
10341         switch (fb->modifier) {
10342         case DRM_FORMAT_MOD_NONE:
10343                 break;
10344         case I915_FORMAT_MOD_X_TILED:
10345                 ctl |= PLANE_CTL_TILED_X;
10346                 break;
10347         case I915_FORMAT_MOD_Y_TILED:
10348                 ctl |= PLANE_CTL_TILED_Y;
10349                 break;
10350         case I915_FORMAT_MOD_Yf_TILED:
10351                 ctl |= PLANE_CTL_TILED_YF;
10352                 break;
10353         default:
10354                 MISSING_CASE(fb->modifier);
10355         }
10356
10357         /*
10358          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10359          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10360          */
10361         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10362         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10363
10364         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10365         POSTING_READ(PLANE_SURF(pipe, 0));
10366 }
10367
10368 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10369                              struct intel_flip_work *work)
10370 {
10371         struct drm_device *dev = intel_crtc->base.dev;
10372         struct drm_i915_private *dev_priv = to_i915(dev);
10373         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10374         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10375         u32 dspcntr;
10376
10377         dspcntr = I915_READ(reg);
10378
10379         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10380                 dspcntr |= DISPPLANE_TILED;
10381         else
10382                 dspcntr &= ~DISPPLANE_TILED;
10383
10384         I915_WRITE(reg, dspcntr);
10385
10386         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10387         POSTING_READ(DSPSURF(intel_crtc->plane));
10388 }
10389
10390 static void intel_mmio_flip_work_func(struct work_struct *w)
10391 {
10392         struct intel_flip_work *work =
10393                 container_of(w, struct intel_flip_work, mmio_work);
10394         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10395         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10396         struct intel_framebuffer *intel_fb =
10397                 to_intel_framebuffer(crtc->base.primary->fb);
10398         struct drm_i915_gem_object *obj = intel_fb->obj;
10399
10400         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10401
10402         intel_pipe_update_start(crtc);
10403
10404         if (INTEL_GEN(dev_priv) >= 9)
10405                 skl_do_mmio_flip(crtc, work->rotation, work);
10406         else
10407                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10408                 ilk_do_mmio_flip(crtc, work);
10409
10410         intel_pipe_update_end(crtc, work);
10411 }
10412
10413 static int intel_default_queue_flip(struct drm_device *dev,
10414                                     struct drm_crtc *crtc,
10415                                     struct drm_framebuffer *fb,
10416                                     struct drm_i915_gem_object *obj,
10417                                     struct drm_i915_gem_request *req,
10418                                     uint32_t flags)
10419 {
10420         return -ENODEV;
10421 }
10422
10423 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10424                                       struct intel_crtc *intel_crtc,
10425                                       struct intel_flip_work *work)
10426 {
10427         u32 addr, vblank;
10428
10429         if (!atomic_read(&work->pending))
10430                 return false;
10431
10432         smp_rmb();
10433
10434         vblank = intel_crtc_get_vblank_counter(intel_crtc);
10435         if (work->flip_ready_vblank == 0) {
10436                 if (work->flip_queued_req &&
10437                     !i915_gem_request_completed(work->flip_queued_req))
10438                         return false;
10439
10440                 work->flip_ready_vblank = vblank;
10441         }
10442
10443         if (vblank - work->flip_ready_vblank < 3)
10444                 return false;
10445
10446         /* Potential stall - if we see that the flip has happened,
10447          * assume a missed interrupt. */
10448         if (INTEL_GEN(dev_priv) >= 4)
10449                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10450         else
10451                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10452
10453         /* There is a potential issue here with a false positive after a flip
10454          * to the same address. We could address this by checking for a
10455          * non-incrementing frame counter.
10456          */
10457         return addr == work->gtt_offset;
10458 }
10459
10460 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10461 {
10462         struct drm_device *dev = &dev_priv->drm;
10463         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10464         struct intel_flip_work *work;
10465
10466         WARN_ON(!in_interrupt());
10467
10468         if (crtc == NULL)
10469                 return;
10470
10471         spin_lock(&dev->event_lock);
10472         work = crtc->flip_work;
10473
10474         if (work != NULL && !is_mmio_work(work) &&
10475             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10476                 WARN_ONCE(1,
10477                           "Kicking stuck page flip: queued at %d, now %d\n",
10478                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10479                 page_flip_completed(crtc);
10480                 work = NULL;
10481         }
10482
10483         if (work != NULL && !is_mmio_work(work) &&
10484             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10485                 intel_queue_rps_boost_for_request(work->flip_queued_req);
10486         spin_unlock(&dev->event_lock);
10487 }
10488
10489 __maybe_unused
10490 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10491                                 struct drm_framebuffer *fb,
10492                                 struct drm_pending_vblank_event *event,
10493                                 uint32_t page_flip_flags)
10494 {
10495         struct drm_device *dev = crtc->dev;
10496         struct drm_i915_private *dev_priv = to_i915(dev);
10497         struct drm_framebuffer *old_fb = crtc->primary->fb;
10498         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10500         struct drm_plane *primary = crtc->primary;
10501         enum pipe pipe = intel_crtc->pipe;
10502         struct intel_flip_work *work;
10503         struct intel_engine_cs *engine;
10504         bool mmio_flip;
10505         struct drm_i915_gem_request *request;
10506         struct i915_vma *vma;
10507         int ret;
10508
10509         /*
10510          * drm_mode_page_flip_ioctl() should already catch this, but double
10511          * check to be safe.  In the future we may enable pageflipping from
10512          * a disabled primary plane.
10513          */
10514         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10515                 return -EBUSY;
10516
10517         /* Can't change pixel format via MI display flips. */
10518         if (fb->format != crtc->primary->fb->format)
10519                 return -EINVAL;
10520
10521         /*
10522          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10523          * Note that pitch changes could also affect these register.
10524          */
10525         if (INTEL_GEN(dev_priv) > 3 &&
10526             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10527              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10528                 return -EINVAL;
10529
10530         if (i915_terminally_wedged(&dev_priv->gpu_error))
10531                 goto out_hang;
10532
10533         work = kzalloc(sizeof(*work), GFP_KERNEL);
10534         if (work == NULL)
10535                 return -ENOMEM;
10536
10537         work->event = event;
10538         work->crtc = crtc;
10539         work->old_fb = old_fb;
10540         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10541
10542         ret = drm_crtc_vblank_get(crtc);
10543         if (ret)
10544                 goto free_work;
10545
10546         /* We borrow the event spin lock for protecting flip_work */
10547         spin_lock_irq(&dev->event_lock);
10548         if (intel_crtc->flip_work) {
10549                 /* Before declaring the flip queue wedged, check if
10550                  * the hardware completed the operation behind our backs.
10551                  */
10552                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10553                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10554                         page_flip_completed(intel_crtc);
10555                 } else {
10556                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10557                         spin_unlock_irq(&dev->event_lock);
10558
10559                         drm_crtc_vblank_put(crtc);
10560                         kfree(work);
10561                         return -EBUSY;
10562                 }
10563         }
10564         intel_crtc->flip_work = work;
10565         spin_unlock_irq(&dev->event_lock);
10566
10567         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10568                 flush_workqueue(dev_priv->wq);
10569
10570         /* Reference the objects for the scheduled work. */
10571         drm_framebuffer_reference(work->old_fb);
10572
10573         crtc->primary->fb = fb;
10574         update_state_fb(crtc->primary);
10575
10576         work->pending_flip_obj = i915_gem_object_get(obj);
10577
10578         ret = i915_mutex_lock_interruptible(dev);
10579         if (ret)
10580                 goto cleanup;
10581
10582         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10583         if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
10584                 ret = -EIO;
10585                 goto unlock;
10586         }
10587
10588         atomic_inc(&intel_crtc->unpin_work_count);
10589
10590         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10591                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10592
10593         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10594                 engine = dev_priv->engine[BCS];
10595                 if (fb->modifier != old_fb->modifier)
10596                         /* vlv: DISPLAY_FLIP fails to change tiling */
10597                         engine = NULL;
10598         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10599                 engine = dev_priv->engine[BCS];
10600         } else if (INTEL_GEN(dev_priv) >= 7) {
10601                 engine = i915_gem_object_last_write_engine(obj);
10602                 if (engine == NULL || engine->id != RCS)
10603                         engine = dev_priv->engine[BCS];
10604         } else {
10605                 engine = dev_priv->engine[RCS];
10606         }
10607
10608         mmio_flip = use_mmio_flip(engine, obj);
10609
10610         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10611         if (IS_ERR(vma)) {
10612                 ret = PTR_ERR(vma);
10613                 goto cleanup_pending;
10614         }
10615
10616         work->old_vma = to_intel_plane_state(primary->state)->vma;
10617         to_intel_plane_state(primary->state)->vma = vma;
10618
10619         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10620         work->rotation = crtc->primary->state->rotation;
10621
10622         /*
10623          * There's the potential that the next frame will not be compatible with
10624          * FBC, so we want to call pre_update() before the actual page flip.
10625          * The problem is that pre_update() caches some information about the fb
10626          * object, so we want to do this only after the object is pinned. Let's
10627          * be on the safe side and do this immediately before scheduling the
10628          * flip.
10629          */
10630         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10631                              to_intel_plane_state(primary->state));
10632
10633         if (mmio_flip) {
10634                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10635                 queue_work(system_unbound_wq, &work->mmio_work);
10636         } else {
10637                 request = i915_gem_request_alloc(engine,
10638                                                  dev_priv->kernel_context);
10639                 if (IS_ERR(request)) {
10640                         ret = PTR_ERR(request);
10641                         goto cleanup_unpin;
10642                 }
10643
10644                 ret = i915_gem_request_await_object(request, obj, false);
10645                 if (ret)
10646                         goto cleanup_request;
10647
10648                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10649                                                    page_flip_flags);
10650                 if (ret)
10651                         goto cleanup_request;
10652
10653                 intel_mark_page_flip_active(intel_crtc, work);
10654
10655                 work->flip_queued_req = i915_gem_request_get(request);
10656                 i915_add_request_no_flush(request);
10657         }
10658
10659         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10660         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10661                           to_intel_plane(primary)->frontbuffer_bit);
10662         mutex_unlock(&dev->struct_mutex);
10663
10664         intel_frontbuffer_flip_prepare(to_i915(dev),
10665                                        to_intel_plane(primary)->frontbuffer_bit);
10666
10667         trace_i915_flip_request(intel_crtc->plane, obj);
10668
10669         return 0;
10670
10671 cleanup_request:
10672         i915_add_request_no_flush(request);
10673 cleanup_unpin:
10674         to_intel_plane_state(primary->state)->vma = work->old_vma;
10675         intel_unpin_fb_vma(vma);
10676 cleanup_pending:
10677         atomic_dec(&intel_crtc->unpin_work_count);
10678 unlock:
10679         mutex_unlock(&dev->struct_mutex);
10680 cleanup:
10681         crtc->primary->fb = old_fb;
10682         update_state_fb(crtc->primary);
10683
10684         i915_gem_object_put(obj);
10685         drm_framebuffer_unreference(work->old_fb);
10686
10687         spin_lock_irq(&dev->event_lock);
10688         intel_crtc->flip_work = NULL;
10689         spin_unlock_irq(&dev->event_lock);
10690
10691         drm_crtc_vblank_put(crtc);
10692 free_work:
10693         kfree(work);
10694
10695         if (ret == -EIO) {
10696                 struct drm_atomic_state *state;
10697                 struct drm_plane_state *plane_state;
10698
10699 out_hang:
10700                 state = drm_atomic_state_alloc(dev);
10701                 if (!state)
10702                         return -ENOMEM;
10703                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
10704
10705 retry:
10706                 plane_state = drm_atomic_get_plane_state(state, primary);
10707                 ret = PTR_ERR_OR_ZERO(plane_state);
10708                 if (!ret) {
10709                         drm_atomic_set_fb_for_plane(plane_state, fb);
10710
10711                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10712                         if (!ret)
10713                                 ret = drm_atomic_commit(state);
10714                 }
10715
10716                 if (ret == -EDEADLK) {
10717                         drm_modeset_backoff(state->acquire_ctx);
10718                         drm_atomic_state_clear(state);
10719                         goto retry;
10720                 }
10721
10722                 drm_atomic_state_put(state);
10723
10724                 if (ret == 0 && event) {
10725                         spin_lock_irq(&dev->event_lock);
10726                         drm_crtc_send_vblank_event(crtc, event);
10727                         spin_unlock_irq(&dev->event_lock);
10728                 }
10729         }
10730         return ret;
10731 }
10732
10733
10734 /**
10735  * intel_wm_need_update - Check whether watermarks need updating
10736  * @plane: drm plane
10737  * @state: new plane state
10738  *
10739  * Check current plane state versus the new one to determine whether
10740  * watermarks need to be recalculated.
10741  *
10742  * Returns true or false.
10743  */
10744 static bool intel_wm_need_update(struct drm_plane *plane,
10745                                  struct drm_plane_state *state)
10746 {
10747         struct intel_plane_state *new = to_intel_plane_state(state);
10748         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10749
10750         /* Update watermarks on tiling or size changes. */
10751         if (new->base.visible != cur->base.visible)
10752                 return true;
10753
10754         if (!cur->base.fb || !new->base.fb)
10755                 return false;
10756
10757         if (cur->base.fb->modifier != new->base.fb->modifier ||
10758             cur->base.rotation != new->base.rotation ||
10759             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10760             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10761             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10762             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10763                 return true;
10764
10765         return false;
10766 }
10767
10768 static bool needs_scaling(struct intel_plane_state *state)
10769 {
10770         int src_w = drm_rect_width(&state->base.src) >> 16;
10771         int src_h = drm_rect_height(&state->base.src) >> 16;
10772         int dst_w = drm_rect_width(&state->base.dst);
10773         int dst_h = drm_rect_height(&state->base.dst);
10774
10775         return (src_w != dst_w || src_h != dst_h);
10776 }
10777
10778 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10779                                     struct drm_plane_state *plane_state)
10780 {
10781         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10782         struct drm_crtc *crtc = crtc_state->crtc;
10783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10784         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10785         struct drm_device *dev = crtc->dev;
10786         struct drm_i915_private *dev_priv = to_i915(dev);
10787         struct intel_plane_state *old_plane_state =
10788                 to_intel_plane_state(plane->base.state);
10789         bool mode_changed = needs_modeset(crtc_state);
10790         bool was_crtc_enabled = crtc->state->active;
10791         bool is_crtc_enabled = crtc_state->active;
10792         bool turn_off, turn_on, visible, was_visible;
10793         struct drm_framebuffer *fb = plane_state->fb;
10794         int ret;
10795
10796         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10797                 ret = skl_update_scaler_plane(
10798                         to_intel_crtc_state(crtc_state),
10799                         to_intel_plane_state(plane_state));
10800                 if (ret)
10801                         return ret;
10802         }
10803
10804         was_visible = old_plane_state->base.visible;
10805         visible = plane_state->visible;
10806
10807         if (!was_crtc_enabled && WARN_ON(was_visible))
10808                 was_visible = false;
10809
10810         /*
10811          * Visibility is calculated as if the crtc was on, but
10812          * after scaler setup everything depends on it being off
10813          * when the crtc isn't active.
10814          *
10815          * FIXME this is wrong for watermarks. Watermarks should also
10816          * be computed as if the pipe would be active. Perhaps move
10817          * per-plane wm computation to the .check_plane() hook, and
10818          * only combine the results from all planes in the current place?
10819          */
10820         if (!is_crtc_enabled) {
10821                 plane_state->visible = visible = false;
10822                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10823         }
10824
10825         if (!was_visible && !visible)
10826                 return 0;
10827
10828         if (fb != old_plane_state->base.fb)
10829                 pipe_config->fb_changed = true;
10830
10831         turn_off = was_visible && (!visible || mode_changed);
10832         turn_on = visible && (!was_visible || mode_changed);
10833
10834         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10835                          intel_crtc->base.base.id, intel_crtc->base.name,
10836                          plane->base.base.id, plane->base.name,
10837                          fb ? fb->base.id : -1);
10838
10839         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10840                          plane->base.base.id, plane->base.name,
10841                          was_visible, visible,
10842                          turn_off, turn_on, mode_changed);
10843
10844         if (turn_on) {
10845                 if (INTEL_GEN(dev_priv) < 5)
10846                         pipe_config->update_wm_pre = true;
10847
10848                 /* must disable cxsr around plane enable/disable */
10849                 if (plane->id != PLANE_CURSOR)
10850                         pipe_config->disable_cxsr = true;
10851         } else if (turn_off) {
10852                 if (INTEL_GEN(dev_priv) < 5)
10853                         pipe_config->update_wm_post = true;
10854
10855                 /* must disable cxsr around plane enable/disable */
10856                 if (plane->id != PLANE_CURSOR)
10857                         pipe_config->disable_cxsr = true;
10858         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10859                 if (INTEL_GEN(dev_priv) < 5) {
10860                         /* FIXME bollocks */
10861                         pipe_config->update_wm_pre = true;
10862                         pipe_config->update_wm_post = true;
10863                 }
10864         }
10865
10866         if (visible || was_visible)
10867                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10868
10869         /*
10870          * WaCxSRDisabledForSpriteScaling:ivb
10871          *
10872          * cstate->update_wm was already set above, so this flag will
10873          * take effect when we commit and program watermarks.
10874          */
10875         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10876             needs_scaling(to_intel_plane_state(plane_state)) &&
10877             !needs_scaling(old_plane_state))
10878                 pipe_config->disable_lp_wm = true;
10879
10880         return 0;
10881 }
10882
10883 static bool encoders_cloneable(const struct intel_encoder *a,
10884                                const struct intel_encoder *b)
10885 {
10886         /* masks could be asymmetric, so check both ways */
10887         return a == b || (a->cloneable & (1 << b->type) &&
10888                           b->cloneable & (1 << a->type));
10889 }
10890
10891 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10892                                          struct intel_crtc *crtc,
10893                                          struct intel_encoder *encoder)
10894 {
10895         struct intel_encoder *source_encoder;
10896         struct drm_connector *connector;
10897         struct drm_connector_state *connector_state;
10898         int i;
10899
10900         for_each_connector_in_state(state, connector, connector_state, i) {
10901                 if (connector_state->crtc != &crtc->base)
10902                         continue;
10903
10904                 source_encoder =
10905                         to_intel_encoder(connector_state->best_encoder);
10906                 if (!encoders_cloneable(encoder, source_encoder))
10907                         return false;
10908         }
10909
10910         return true;
10911 }
10912
10913 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10914                                    struct drm_crtc_state *crtc_state)
10915 {
10916         struct drm_device *dev = crtc->dev;
10917         struct drm_i915_private *dev_priv = to_i915(dev);
10918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10919         struct intel_crtc_state *pipe_config =
10920                 to_intel_crtc_state(crtc_state);
10921         struct drm_atomic_state *state = crtc_state->state;
10922         int ret;
10923         bool mode_changed = needs_modeset(crtc_state);
10924
10925         if (mode_changed && !crtc_state->active)
10926                 pipe_config->update_wm_post = true;
10927
10928         if (mode_changed && crtc_state->enable &&
10929             dev_priv->display.crtc_compute_clock &&
10930             !WARN_ON(pipe_config->shared_dpll)) {
10931                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10932                                                            pipe_config);
10933                 if (ret)
10934                         return ret;
10935         }
10936
10937         if (crtc_state->color_mgmt_changed) {
10938                 ret = intel_color_check(crtc, crtc_state);
10939                 if (ret)
10940                         return ret;
10941
10942                 /*
10943                  * Changing color management on Intel hardware is
10944                  * handled as part of planes update.
10945                  */
10946                 crtc_state->planes_changed = true;
10947         }
10948
10949         ret = 0;
10950         if (dev_priv->display.compute_pipe_wm) {
10951                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10952                 if (ret) {
10953                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10954                         return ret;
10955                 }
10956         }
10957
10958         if (dev_priv->display.compute_intermediate_wm &&
10959             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10960                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10961                         return 0;
10962
10963                 /*
10964                  * Calculate 'intermediate' watermarks that satisfy both the
10965                  * old state and the new state.  We can program these
10966                  * immediately.
10967                  */
10968                 ret = dev_priv->display.compute_intermediate_wm(dev,
10969                                                                 intel_crtc,
10970                                                                 pipe_config);
10971                 if (ret) {
10972                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10973                         return ret;
10974                 }
10975         } else if (dev_priv->display.compute_intermediate_wm) {
10976                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10977                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10978         }
10979
10980         if (INTEL_GEN(dev_priv) >= 9) {
10981                 if (mode_changed)
10982                         ret = skl_update_scaler_crtc(pipe_config);
10983
10984                 if (!ret)
10985                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10986                                                          pipe_config);
10987         }
10988
10989         return ret;
10990 }
10991
10992 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10993         .mode_set_base_atomic = intel_pipe_set_base_atomic,
10994         .atomic_begin = intel_begin_crtc_commit,
10995         .atomic_flush = intel_finish_crtc_commit,
10996         .atomic_check = intel_crtc_atomic_check,
10997 };
10998
10999 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11000 {
11001         struct intel_connector *connector;
11002
11003         for_each_intel_connector(dev, connector) {
11004                 if (connector->base.state->crtc)
11005                         drm_connector_unreference(&connector->base);
11006
11007                 if (connector->base.encoder) {
11008                         connector->base.state->best_encoder =
11009                                 connector->base.encoder;
11010                         connector->base.state->crtc =
11011                                 connector->base.encoder->crtc;
11012
11013                         drm_connector_reference(&connector->base);
11014                 } else {
11015                         connector->base.state->best_encoder = NULL;
11016                         connector->base.state->crtc = NULL;
11017                 }
11018         }
11019 }
11020
11021 static void
11022 connected_sink_compute_bpp(struct intel_connector *connector,
11023                            struct intel_crtc_state *pipe_config)
11024 {
11025         const struct drm_display_info *info = &connector->base.display_info;
11026         int bpp = pipe_config->pipe_bpp;
11027
11028         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11029                       connector->base.base.id,
11030                       connector->base.name);
11031
11032         /* Don't use an invalid EDID bpc value */
11033         if (info->bpc != 0 && info->bpc * 3 < bpp) {
11034                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11035                               bpp, info->bpc * 3);
11036                 pipe_config->pipe_bpp = info->bpc * 3;
11037         }
11038
11039         /* Clamp bpp to 8 on screens without EDID 1.4 */
11040         if (info->bpc == 0 && bpp > 24) {
11041                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11042                               bpp);
11043                 pipe_config->pipe_bpp = 24;
11044         }
11045 }
11046
11047 static int
11048 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11049                           struct intel_crtc_state *pipe_config)
11050 {
11051         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11052         struct drm_atomic_state *state;
11053         struct drm_connector *connector;
11054         struct drm_connector_state *connector_state;
11055         int bpp, i;
11056
11057         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11058             IS_CHERRYVIEW(dev_priv)))
11059                 bpp = 10*3;
11060         else if (INTEL_GEN(dev_priv) >= 5)
11061                 bpp = 12*3;
11062         else
11063                 bpp = 8*3;
11064
11065
11066         pipe_config->pipe_bpp = bpp;
11067
11068         state = pipe_config->base.state;
11069
11070         /* Clamp display bpp to EDID value */
11071         for_each_connector_in_state(state, connector, connector_state, i) {
11072                 if (connector_state->crtc != &crtc->base)
11073                         continue;
11074
11075                 connected_sink_compute_bpp(to_intel_connector(connector),
11076                                            pipe_config);
11077         }
11078
11079         return bpp;
11080 }
11081
11082 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11083 {
11084         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11085                         "type: 0x%x flags: 0x%x\n",
11086                 mode->crtc_clock,
11087                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11088                 mode->crtc_hsync_end, mode->crtc_htotal,
11089                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11090                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11091 }
11092
11093 static inline void
11094 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11095                       unsigned int lane_count, struct intel_link_m_n *m_n)
11096 {
11097         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11098                       id, lane_count,
11099                       m_n->gmch_m, m_n->gmch_n,
11100                       m_n->link_m, m_n->link_n, m_n->tu);
11101 }
11102
11103 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11104                                    struct intel_crtc_state *pipe_config,
11105                                    const char *context)
11106 {
11107         struct drm_device *dev = crtc->base.dev;
11108         struct drm_i915_private *dev_priv = to_i915(dev);
11109         struct drm_plane *plane;
11110         struct intel_plane *intel_plane;
11111         struct intel_plane_state *state;
11112         struct drm_framebuffer *fb;
11113
11114         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11115                       crtc->base.base.id, crtc->base.name, context);
11116
11117         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11118                       transcoder_name(pipe_config->cpu_transcoder),
11119                       pipe_config->pipe_bpp, pipe_config->dither);
11120
11121         if (pipe_config->has_pch_encoder)
11122                 intel_dump_m_n_config(pipe_config, "fdi",
11123                                       pipe_config->fdi_lanes,
11124                                       &pipe_config->fdi_m_n);
11125
11126         if (intel_crtc_has_dp_encoder(pipe_config)) {
11127                 intel_dump_m_n_config(pipe_config, "dp m_n",
11128                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11129                 if (pipe_config->has_drrs)
11130                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11131                                               pipe_config->lane_count,
11132                                               &pipe_config->dp_m2_n2);
11133         }
11134
11135         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11136                       pipe_config->has_audio, pipe_config->has_infoframe);
11137
11138         DRM_DEBUG_KMS("requested mode:\n");
11139         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11140         DRM_DEBUG_KMS("adjusted mode:\n");
11141         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11142         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11143         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11144                       pipe_config->port_clock,
11145                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11146                       pipe_config->pixel_rate);
11147
11148         if (INTEL_GEN(dev_priv) >= 9)
11149                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11150                               crtc->num_scalers,
11151                               pipe_config->scaler_state.scaler_users,
11152                               pipe_config->scaler_state.scaler_id);
11153
11154         if (HAS_GMCH_DISPLAY(dev_priv))
11155                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11156                               pipe_config->gmch_pfit.control,
11157                               pipe_config->gmch_pfit.pgm_ratios,
11158                               pipe_config->gmch_pfit.lvds_border_bits);
11159         else
11160                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11161                               pipe_config->pch_pfit.pos,
11162                               pipe_config->pch_pfit.size,
11163                               enableddisabled(pipe_config->pch_pfit.enabled));
11164
11165         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11166                       pipe_config->ips_enabled, pipe_config->double_wide);
11167
11168         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11169
11170         DRM_DEBUG_KMS("planes on this crtc\n");
11171         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11172                 struct drm_format_name_buf format_name;
11173                 intel_plane = to_intel_plane(plane);
11174                 if (intel_plane->pipe != crtc->pipe)
11175                         continue;
11176
11177                 state = to_intel_plane_state(plane->state);
11178                 fb = state->base.fb;
11179                 if (!fb) {
11180                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11181                                       plane->base.id, plane->name, state->scaler_id);
11182                         continue;
11183                 }
11184
11185                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11186                               plane->base.id, plane->name,
11187                               fb->base.id, fb->width, fb->height,
11188                               drm_get_format_name(fb->format->format, &format_name));
11189                 if (INTEL_GEN(dev_priv) >= 9)
11190                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11191                                       state->scaler_id,
11192                                       state->base.src.x1 >> 16,
11193                                       state->base.src.y1 >> 16,
11194                                       drm_rect_width(&state->base.src) >> 16,
11195                                       drm_rect_height(&state->base.src) >> 16,
11196                                       state->base.dst.x1, state->base.dst.y1,
11197                                       drm_rect_width(&state->base.dst),
11198                                       drm_rect_height(&state->base.dst));
11199         }
11200 }
11201
11202 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11203 {
11204         struct drm_device *dev = state->dev;
11205         struct drm_connector *connector;
11206         unsigned int used_ports = 0;
11207         unsigned int used_mst_ports = 0;
11208
11209         /*
11210          * Walk the connector list instead of the encoder
11211          * list to detect the problem on ddi platforms
11212          * where there's just one encoder per digital port.
11213          */
11214         drm_for_each_connector(connector, dev) {
11215                 struct drm_connector_state *connector_state;
11216                 struct intel_encoder *encoder;
11217
11218                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11219                 if (!connector_state)
11220                         connector_state = connector->state;
11221
11222                 if (!connector_state->best_encoder)
11223                         continue;
11224
11225                 encoder = to_intel_encoder(connector_state->best_encoder);
11226
11227                 WARN_ON(!connector_state->crtc);
11228
11229                 switch (encoder->type) {
11230                         unsigned int port_mask;
11231                 case INTEL_OUTPUT_UNKNOWN:
11232                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11233                                 break;
11234                 case INTEL_OUTPUT_DP:
11235                 case INTEL_OUTPUT_HDMI:
11236                 case INTEL_OUTPUT_EDP:
11237                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11238
11239                         /* the same port mustn't appear more than once */
11240                         if (used_ports & port_mask)
11241                                 return false;
11242
11243                         used_ports |= port_mask;
11244                         break;
11245                 case INTEL_OUTPUT_DP_MST:
11246                         used_mst_ports |=
11247                                 1 << enc_to_mst(&encoder->base)->primary->port;
11248                         break;
11249                 default:
11250                         break;
11251                 }
11252         }
11253
11254         /* can't mix MST and SST/HDMI on the same port */
11255         if (used_ports & used_mst_ports)
11256                 return false;
11257
11258         return true;
11259 }
11260
11261 static void
11262 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11263 {
11264         struct drm_i915_private *dev_priv =
11265                 to_i915(crtc_state->base.crtc->dev);
11266         struct intel_crtc_scaler_state scaler_state;
11267         struct intel_dpll_hw_state dpll_hw_state;
11268         struct intel_shared_dpll *shared_dpll;
11269         struct intel_crtc_wm_state wm_state;
11270         bool force_thru;
11271
11272         /* FIXME: before the switch to atomic started, a new pipe_config was
11273          * kzalloc'd. Code that depends on any field being zero should be
11274          * fixed, so that the crtc_state can be safely duplicated. For now,
11275          * only fields that are know to not cause problems are preserved. */
11276
11277         scaler_state = crtc_state->scaler_state;
11278         shared_dpll = crtc_state->shared_dpll;
11279         dpll_hw_state = crtc_state->dpll_hw_state;
11280         force_thru = crtc_state->pch_pfit.force_thru;
11281         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11282                 wm_state = crtc_state->wm;
11283
11284         /* Keep base drm_crtc_state intact, only clear our extended struct */
11285         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11286         memset(&crtc_state->base + 1, 0,
11287                sizeof(*crtc_state) - sizeof(crtc_state->base));
11288
11289         crtc_state->scaler_state = scaler_state;
11290         crtc_state->shared_dpll = shared_dpll;
11291         crtc_state->dpll_hw_state = dpll_hw_state;
11292         crtc_state->pch_pfit.force_thru = force_thru;
11293         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11294                 crtc_state->wm = wm_state;
11295 }
11296
11297 static int
11298 intel_modeset_pipe_config(struct drm_crtc *crtc,
11299                           struct intel_crtc_state *pipe_config)
11300 {
11301         struct drm_atomic_state *state = pipe_config->base.state;
11302         struct intel_encoder *encoder;
11303         struct drm_connector *connector;
11304         struct drm_connector_state *connector_state;
11305         int base_bpp, ret = -EINVAL;
11306         int i;
11307         bool retry = true;
11308
11309         clear_intel_crtc_state(pipe_config);
11310
11311         pipe_config->cpu_transcoder =
11312                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11313
11314         /*
11315          * Sanitize sync polarity flags based on requested ones. If neither
11316          * positive or negative polarity is requested, treat this as meaning
11317          * negative polarity.
11318          */
11319         if (!(pipe_config->base.adjusted_mode.flags &
11320               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11321                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11322
11323         if (!(pipe_config->base.adjusted_mode.flags &
11324               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11325                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11326
11327         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11328                                              pipe_config);
11329         if (base_bpp < 0)
11330                 goto fail;
11331
11332         /*
11333          * Determine the real pipe dimensions. Note that stereo modes can
11334          * increase the actual pipe size due to the frame doubling and
11335          * insertion of additional space for blanks between the frame. This
11336          * is stored in the crtc timings. We use the requested mode to do this
11337          * computation to clearly distinguish it from the adjusted mode, which
11338          * can be changed by the connectors in the below retry loop.
11339          */
11340         drm_mode_get_hv_timing(&pipe_config->base.mode,
11341                                &pipe_config->pipe_src_w,
11342                                &pipe_config->pipe_src_h);
11343
11344         for_each_connector_in_state(state, connector, connector_state, i) {
11345                 if (connector_state->crtc != crtc)
11346                         continue;
11347
11348                 encoder = to_intel_encoder(connector_state->best_encoder);
11349
11350                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11351                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11352                         goto fail;
11353                 }
11354
11355                 /*
11356                  * Determine output_types before calling the .compute_config()
11357                  * hooks so that the hooks can use this information safely.
11358                  */
11359                 pipe_config->output_types |= 1 << encoder->type;
11360         }
11361
11362 encoder_retry:
11363         /* Ensure the port clock defaults are reset when retrying. */
11364         pipe_config->port_clock = 0;
11365         pipe_config->pixel_multiplier = 1;
11366
11367         /* Fill in default crtc timings, allow encoders to overwrite them. */
11368         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11369                               CRTC_STEREO_DOUBLE);
11370
11371         /* Pass our mode to the connectors and the CRTC to give them a chance to
11372          * adjust it according to limitations or connector properties, and also
11373          * a chance to reject the mode entirely.
11374          */
11375         for_each_connector_in_state(state, connector, connector_state, i) {
11376                 if (connector_state->crtc != crtc)
11377                         continue;
11378
11379                 encoder = to_intel_encoder(connector_state->best_encoder);
11380
11381                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11382                         DRM_DEBUG_KMS("Encoder config failure\n");
11383                         goto fail;
11384                 }
11385         }
11386
11387         /* Set default port clock if not overwritten by the encoder. Needs to be
11388          * done afterwards in case the encoder adjusts the mode. */
11389         if (!pipe_config->port_clock)
11390                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11391                         * pipe_config->pixel_multiplier;
11392
11393         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11394         if (ret < 0) {
11395                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11396                 goto fail;
11397         }
11398
11399         if (ret == RETRY) {
11400                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11401                         ret = -EINVAL;
11402                         goto fail;
11403                 }
11404
11405                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11406                 retry = false;
11407                 goto encoder_retry;
11408         }
11409
11410         /* Dithering seems to not pass-through bits correctly when it should, so
11411          * only enable it on 6bpc panels and when its not a compliance
11412          * test requesting 6bpc video pattern.
11413          */
11414         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11415                 !pipe_config->dither_force_disable;
11416         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11417                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11418
11419 fail:
11420         return ret;
11421 }
11422
11423 static void
11424 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11425 {
11426         struct drm_crtc *crtc;
11427         struct drm_crtc_state *crtc_state;
11428         int i;
11429
11430         /* Double check state. */
11431         for_each_crtc_in_state(state, crtc, crtc_state, i) {
11432                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
11433
11434                 /* Update hwmode for vblank functions */
11435                 if (crtc->state->active)
11436                         crtc->hwmode = crtc->state->adjusted_mode;
11437                 else
11438                         crtc->hwmode.crtc_clock = 0;
11439
11440                 /*
11441                  * Update legacy state to satisfy fbc code. This can
11442                  * be removed when fbc uses the atomic state.
11443                  */
11444                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11445                         struct drm_plane_state *plane_state = crtc->primary->state;
11446
11447                         crtc->primary->fb = plane_state->fb;
11448                         crtc->x = plane_state->src_x >> 16;
11449                         crtc->y = plane_state->src_y >> 16;
11450                 }
11451         }
11452 }
11453
11454 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11455 {
11456         int diff;
11457
11458         if (clock1 == clock2)
11459                 return true;
11460
11461         if (!clock1 || !clock2)
11462                 return false;
11463
11464         diff = abs(clock1 - clock2);
11465
11466         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11467                 return true;
11468
11469         return false;
11470 }
11471
11472 static bool
11473 intel_compare_m_n(unsigned int m, unsigned int n,
11474                   unsigned int m2, unsigned int n2,
11475                   bool exact)
11476 {
11477         if (m == m2 && n == n2)
11478                 return true;
11479
11480         if (exact || !m || !n || !m2 || !n2)
11481                 return false;
11482
11483         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11484
11485         if (n > n2) {
11486                 while (n > n2) {
11487                         m2 <<= 1;
11488                         n2 <<= 1;
11489                 }
11490         } else if (n < n2) {
11491                 while (n < n2) {
11492                         m <<= 1;
11493                         n <<= 1;
11494                 }
11495         }
11496
11497         if (n != n2)
11498                 return false;
11499
11500         return intel_fuzzy_clock_check(m, m2);
11501 }
11502
11503 static bool
11504 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11505                        struct intel_link_m_n *m2_n2,
11506                        bool adjust)
11507 {
11508         if (m_n->tu == m2_n2->tu &&
11509             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11510                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11511             intel_compare_m_n(m_n->link_m, m_n->link_n,
11512                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11513                 if (adjust)
11514                         *m2_n2 = *m_n;
11515
11516                 return true;
11517         }
11518
11519         return false;
11520 }
11521
11522 static void __printf(3, 4)
11523 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11524 {
11525         char *level;
11526         unsigned int category;
11527         struct va_format vaf;
11528         va_list args;
11529
11530         if (adjust) {
11531                 level = KERN_DEBUG;
11532                 category = DRM_UT_KMS;
11533         } else {
11534                 level = KERN_ERR;
11535                 category = DRM_UT_NONE;
11536         }
11537
11538         va_start(args, format);
11539         vaf.fmt = format;
11540         vaf.va = &args;
11541
11542         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11543
11544         va_end(args);
11545 }
11546
11547 static bool
11548 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11549                           struct intel_crtc_state *current_config,
11550                           struct intel_crtc_state *pipe_config,
11551                           bool adjust)
11552 {
11553         bool ret = true;
11554
11555 #define PIPE_CONF_CHECK_X(name) \
11556         if (current_config->name != pipe_config->name) { \
11557                 pipe_config_err(adjust, __stringify(name), \
11558                           "(expected 0x%08x, found 0x%08x)\n", \
11559                           current_config->name, \
11560                           pipe_config->name); \
11561                 ret = false; \
11562         }
11563
11564 #define PIPE_CONF_CHECK_I(name) \
11565         if (current_config->name != pipe_config->name) { \
11566                 pipe_config_err(adjust, __stringify(name), \
11567                           "(expected %i, found %i)\n", \
11568                           current_config->name, \
11569                           pipe_config->name); \
11570                 ret = false; \
11571         }
11572
11573 #define PIPE_CONF_CHECK_P(name) \
11574         if (current_config->name != pipe_config->name) { \
11575                 pipe_config_err(adjust, __stringify(name), \
11576                           "(expected %p, found %p)\n", \
11577                           current_config->name, \
11578                           pipe_config->name); \
11579                 ret = false; \
11580         }
11581
11582 #define PIPE_CONF_CHECK_M_N(name) \
11583         if (!intel_compare_link_m_n(&current_config->name, \
11584                                     &pipe_config->name,\
11585                                     adjust)) { \
11586                 pipe_config_err(adjust, __stringify(name), \
11587                           "(expected tu %i gmch %i/%i link %i/%i, " \
11588                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11589                           current_config->name.tu, \
11590                           current_config->name.gmch_m, \
11591                           current_config->name.gmch_n, \
11592                           current_config->name.link_m, \
11593                           current_config->name.link_n, \
11594                           pipe_config->name.tu, \
11595                           pipe_config->name.gmch_m, \
11596                           pipe_config->name.gmch_n, \
11597                           pipe_config->name.link_m, \
11598                           pipe_config->name.link_n); \
11599                 ret = false; \
11600         }
11601
11602 /* This is required for BDW+ where there is only one set of registers for
11603  * switching between high and low RR.
11604  * This macro can be used whenever a comparison has to be made between one
11605  * hw state and multiple sw state variables.
11606  */
11607 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11608         if (!intel_compare_link_m_n(&current_config->name, \
11609                                     &pipe_config->name, adjust) && \
11610             !intel_compare_link_m_n(&current_config->alt_name, \
11611                                     &pipe_config->name, adjust)) { \
11612                 pipe_config_err(adjust, __stringify(name), \
11613                           "(expected tu %i gmch %i/%i link %i/%i, " \
11614                           "or tu %i gmch %i/%i link %i/%i, " \
11615                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11616                           current_config->name.tu, \
11617                           current_config->name.gmch_m, \
11618                           current_config->name.gmch_n, \
11619                           current_config->name.link_m, \
11620                           current_config->name.link_n, \
11621                           current_config->alt_name.tu, \
11622                           current_config->alt_name.gmch_m, \
11623                           current_config->alt_name.gmch_n, \
11624                           current_config->alt_name.link_m, \
11625                           current_config->alt_name.link_n, \
11626                           pipe_config->name.tu, \
11627                           pipe_config->name.gmch_m, \
11628                           pipe_config->name.gmch_n, \
11629                           pipe_config->name.link_m, \
11630                           pipe_config->name.link_n); \
11631                 ret = false; \
11632         }
11633
11634 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11635         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11636                 pipe_config_err(adjust, __stringify(name), \
11637                           "(%x) (expected %i, found %i)\n", \
11638                           (mask), \
11639                           current_config->name & (mask), \
11640                           pipe_config->name & (mask)); \
11641                 ret = false; \
11642         }
11643
11644 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11645         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11646                 pipe_config_err(adjust, __stringify(name), \
11647                           "(expected %i, found %i)\n", \
11648                           current_config->name, \
11649                           pipe_config->name); \
11650                 ret = false; \
11651         }
11652
11653 #define PIPE_CONF_QUIRK(quirk)  \
11654         ((current_config->quirks | pipe_config->quirks) & (quirk))
11655
11656         PIPE_CONF_CHECK_I(cpu_transcoder);
11657
11658         PIPE_CONF_CHECK_I(has_pch_encoder);
11659         PIPE_CONF_CHECK_I(fdi_lanes);
11660         PIPE_CONF_CHECK_M_N(fdi_m_n);
11661
11662         PIPE_CONF_CHECK_I(lane_count);
11663         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11664
11665         if (INTEL_GEN(dev_priv) < 8) {
11666                 PIPE_CONF_CHECK_M_N(dp_m_n);
11667
11668                 if (current_config->has_drrs)
11669                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11670         } else
11671                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11672
11673         PIPE_CONF_CHECK_X(output_types);
11674
11675         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11676         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11677         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11678         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11679         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11680         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11681
11682         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11683         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11684         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11685         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11686         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11687         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11688
11689         PIPE_CONF_CHECK_I(pixel_multiplier);
11690         PIPE_CONF_CHECK_I(has_hdmi_sink);
11691         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11692             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11693                 PIPE_CONF_CHECK_I(limited_color_range);
11694         PIPE_CONF_CHECK_I(has_infoframe);
11695
11696         PIPE_CONF_CHECK_I(has_audio);
11697
11698         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11699                               DRM_MODE_FLAG_INTERLACE);
11700
11701         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11702                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11703                                       DRM_MODE_FLAG_PHSYNC);
11704                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11705                                       DRM_MODE_FLAG_NHSYNC);
11706                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11707                                       DRM_MODE_FLAG_PVSYNC);
11708                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11709                                       DRM_MODE_FLAG_NVSYNC);
11710         }
11711
11712         PIPE_CONF_CHECK_X(gmch_pfit.control);
11713         /* pfit ratios are autocomputed by the hw on gen4+ */
11714         if (INTEL_GEN(dev_priv) < 4)
11715                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11716         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11717
11718         if (!adjust) {
11719                 PIPE_CONF_CHECK_I(pipe_src_w);
11720                 PIPE_CONF_CHECK_I(pipe_src_h);
11721
11722                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11723                 if (current_config->pch_pfit.enabled) {
11724                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11725                         PIPE_CONF_CHECK_X(pch_pfit.size);
11726                 }
11727
11728                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11729                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11730         }
11731
11732         /* BDW+ don't expose a synchronous way to read the state */
11733         if (IS_HASWELL(dev_priv))
11734                 PIPE_CONF_CHECK_I(ips_enabled);
11735
11736         PIPE_CONF_CHECK_I(double_wide);
11737
11738         PIPE_CONF_CHECK_P(shared_dpll);
11739         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11740         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11741         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11742         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11743         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11744         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11745         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11746         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11747         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11748
11749         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11750         PIPE_CONF_CHECK_X(dsi_pll.div);
11751
11752         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11753                 PIPE_CONF_CHECK_I(pipe_bpp);
11754
11755         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11756         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11757
11758 #undef PIPE_CONF_CHECK_X
11759 #undef PIPE_CONF_CHECK_I
11760 #undef PIPE_CONF_CHECK_P
11761 #undef PIPE_CONF_CHECK_FLAGS
11762 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11763 #undef PIPE_CONF_QUIRK
11764
11765         return ret;
11766 }
11767
11768 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11769                                            const struct intel_crtc_state *pipe_config)
11770 {
11771         if (pipe_config->has_pch_encoder) {
11772                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11773                                                             &pipe_config->fdi_m_n);
11774                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11775
11776                 /*
11777                  * FDI already provided one idea for the dotclock.
11778                  * Yell if the encoder disagrees.
11779                  */
11780                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11781                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11782                      fdi_dotclock, dotclock);
11783         }
11784 }
11785
11786 static void verify_wm_state(struct drm_crtc *crtc,
11787                             struct drm_crtc_state *new_state)
11788 {
11789         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11790         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11791         struct skl_pipe_wm hw_wm, *sw_wm;
11792         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11793         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11795         const enum pipe pipe = intel_crtc->pipe;
11796         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11797
11798         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11799                 return;
11800
11801         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11802         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11803
11804         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11805         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11806
11807         /* planes */
11808         for_each_universal_plane(dev_priv, pipe, plane) {
11809                 hw_plane_wm = &hw_wm.planes[plane];
11810                 sw_plane_wm = &sw_wm->planes[plane];
11811
11812                 /* Watermarks */
11813                 for (level = 0; level <= max_level; level++) {
11814                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11815                                                 &sw_plane_wm->wm[level]))
11816                                 continue;
11817
11818                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11819                                   pipe_name(pipe), plane + 1, level,
11820                                   sw_plane_wm->wm[level].plane_en,
11821                                   sw_plane_wm->wm[level].plane_res_b,
11822                                   sw_plane_wm->wm[level].plane_res_l,
11823                                   hw_plane_wm->wm[level].plane_en,
11824                                   hw_plane_wm->wm[level].plane_res_b,
11825                                   hw_plane_wm->wm[level].plane_res_l);
11826                 }
11827
11828                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11829                                          &sw_plane_wm->trans_wm)) {
11830                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11831                                   pipe_name(pipe), plane + 1,
11832                                   sw_plane_wm->trans_wm.plane_en,
11833                                   sw_plane_wm->trans_wm.plane_res_b,
11834                                   sw_plane_wm->trans_wm.plane_res_l,
11835                                   hw_plane_wm->trans_wm.plane_en,
11836                                   hw_plane_wm->trans_wm.plane_res_b,
11837                                   hw_plane_wm->trans_wm.plane_res_l);
11838                 }
11839
11840                 /* DDB */
11841                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11842                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11843
11844                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11845                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11846                                   pipe_name(pipe), plane + 1,
11847                                   sw_ddb_entry->start, sw_ddb_entry->end,
11848                                   hw_ddb_entry->start, hw_ddb_entry->end);
11849                 }
11850         }
11851
11852         /*
11853          * cursor
11854          * If the cursor plane isn't active, we may not have updated it's ddb
11855          * allocation. In that case since the ddb allocation will be updated
11856          * once the plane becomes visible, we can skip this check
11857          */
11858         if (intel_crtc->cursor_addr) {
11859                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11860                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11861
11862                 /* Watermarks */
11863                 for (level = 0; level <= max_level; level++) {
11864                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11865                                                 &sw_plane_wm->wm[level]))
11866                                 continue;
11867
11868                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11869                                   pipe_name(pipe), level,
11870                                   sw_plane_wm->wm[level].plane_en,
11871                                   sw_plane_wm->wm[level].plane_res_b,
11872                                   sw_plane_wm->wm[level].plane_res_l,
11873                                   hw_plane_wm->wm[level].plane_en,
11874                                   hw_plane_wm->wm[level].plane_res_b,
11875                                   hw_plane_wm->wm[level].plane_res_l);
11876                 }
11877
11878                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11879                                          &sw_plane_wm->trans_wm)) {
11880                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11881                                   pipe_name(pipe),
11882                                   sw_plane_wm->trans_wm.plane_en,
11883                                   sw_plane_wm->trans_wm.plane_res_b,
11884                                   sw_plane_wm->trans_wm.plane_res_l,
11885                                   hw_plane_wm->trans_wm.plane_en,
11886                                   hw_plane_wm->trans_wm.plane_res_b,
11887                                   hw_plane_wm->trans_wm.plane_res_l);
11888                 }
11889
11890                 /* DDB */
11891                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11892                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11893
11894                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11895                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11896                                   pipe_name(pipe),
11897                                   sw_ddb_entry->start, sw_ddb_entry->end,
11898                                   hw_ddb_entry->start, hw_ddb_entry->end);
11899                 }
11900         }
11901 }
11902
11903 static void
11904 verify_connector_state(struct drm_device *dev,
11905                        struct drm_atomic_state *state,
11906                        struct drm_crtc *crtc)
11907 {
11908         struct drm_connector *connector;
11909         struct drm_connector_state *old_conn_state;
11910         int i;
11911
11912         for_each_connector_in_state(state, connector, old_conn_state, i) {
11913                 struct drm_encoder *encoder = connector->encoder;
11914                 struct drm_connector_state *state = connector->state;
11915
11916                 if (state->crtc != crtc)
11917                         continue;
11918
11919                 intel_connector_verify_state(to_intel_connector(connector));
11920
11921                 I915_STATE_WARN(state->best_encoder != encoder,
11922                      "connector's atomic encoder doesn't match legacy encoder\n");
11923         }
11924 }
11925
11926 static void
11927 verify_encoder_state(struct drm_device *dev)
11928 {
11929         struct intel_encoder *encoder;
11930         struct intel_connector *connector;
11931
11932         for_each_intel_encoder(dev, encoder) {
11933                 bool enabled = false;
11934                 enum pipe pipe;
11935
11936                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11937                               encoder->base.base.id,
11938                               encoder->base.name);
11939
11940                 for_each_intel_connector(dev, connector) {
11941                         if (connector->base.state->best_encoder != &encoder->base)
11942                                 continue;
11943                         enabled = true;
11944
11945                         I915_STATE_WARN(connector->base.state->crtc !=
11946                                         encoder->base.crtc,
11947                              "connector's crtc doesn't match encoder crtc\n");
11948                 }
11949
11950                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11951                      "encoder's enabled state mismatch "
11952                      "(expected %i, found %i)\n",
11953                      !!encoder->base.crtc, enabled);
11954
11955                 if (!encoder->base.crtc) {
11956                         bool active;
11957
11958                         active = encoder->get_hw_state(encoder, &pipe);
11959                         I915_STATE_WARN(active,
11960                              "encoder detached but still enabled on pipe %c.\n",
11961                              pipe_name(pipe));
11962                 }
11963         }
11964 }
11965
11966 static void
11967 verify_crtc_state(struct drm_crtc *crtc,
11968                   struct drm_crtc_state *old_crtc_state,
11969                   struct drm_crtc_state *new_crtc_state)
11970 {
11971         struct drm_device *dev = crtc->dev;
11972         struct drm_i915_private *dev_priv = to_i915(dev);
11973         struct intel_encoder *encoder;
11974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11975         struct intel_crtc_state *pipe_config, *sw_config;
11976         struct drm_atomic_state *old_state;
11977         bool active;
11978
11979         old_state = old_crtc_state->state;
11980         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11981         pipe_config = to_intel_crtc_state(old_crtc_state);
11982         memset(pipe_config, 0, sizeof(*pipe_config));
11983         pipe_config->base.crtc = crtc;
11984         pipe_config->base.state = old_state;
11985
11986         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11987
11988         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11989
11990         /* hw state is inconsistent with the pipe quirk */
11991         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11992             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11993                 active = new_crtc_state->active;
11994
11995         I915_STATE_WARN(new_crtc_state->active != active,
11996              "crtc active state doesn't match with hw state "
11997              "(expected %i, found %i)\n", new_crtc_state->active, active);
11998
11999         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12000              "transitional active state does not match atomic hw state "
12001              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12002
12003         for_each_encoder_on_crtc(dev, crtc, encoder) {
12004                 enum pipe pipe;
12005
12006                 active = encoder->get_hw_state(encoder, &pipe);
12007                 I915_STATE_WARN(active != new_crtc_state->active,
12008                         "[ENCODER:%i] active %i with crtc active %i\n",
12009                         encoder->base.base.id, active, new_crtc_state->active);
12010
12011                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12012                                 "Encoder connected to wrong pipe %c\n",
12013                                 pipe_name(pipe));
12014
12015                 if (active) {
12016                         pipe_config->output_types |= 1 << encoder->type;
12017                         encoder->get_config(encoder, pipe_config);
12018                 }
12019         }
12020
12021         intel_crtc_compute_pixel_rate(pipe_config);
12022
12023         if (!new_crtc_state->active)
12024                 return;
12025
12026         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12027
12028         sw_config = to_intel_crtc_state(crtc->state);
12029         if (!intel_pipe_config_compare(dev_priv, sw_config,
12030                                        pipe_config, false)) {
12031                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12032                 intel_dump_pipe_config(intel_crtc, pipe_config,
12033                                        "[hw state]");
12034                 intel_dump_pipe_config(intel_crtc, sw_config,
12035                                        "[sw state]");
12036         }
12037 }
12038
12039 static void
12040 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12041                          struct intel_shared_dpll *pll,
12042                          struct drm_crtc *crtc,
12043                          struct drm_crtc_state *new_state)
12044 {
12045         struct intel_dpll_hw_state dpll_hw_state;
12046         unsigned crtc_mask;
12047         bool active;
12048
12049         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12050
12051         DRM_DEBUG_KMS("%s\n", pll->name);
12052
12053         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12054
12055         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12056                 I915_STATE_WARN(!pll->on && pll->active_mask,
12057                      "pll in active use but not on in sw tracking\n");
12058                 I915_STATE_WARN(pll->on && !pll->active_mask,
12059                      "pll is on but not used by any active crtc\n");
12060                 I915_STATE_WARN(pll->on != active,
12061                      "pll on state mismatch (expected %i, found %i)\n",
12062                      pll->on, active);
12063         }
12064
12065         if (!crtc) {
12066                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12067                                 "more active pll users than references: %x vs %x\n",
12068                                 pll->active_mask, pll->state.crtc_mask);
12069
12070                 return;
12071         }
12072
12073         crtc_mask = 1 << drm_crtc_index(crtc);
12074
12075         if (new_state->active)
12076                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12077                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12078                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12079         else
12080                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12081                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12082                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12083
12084         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12085                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12086                         crtc_mask, pll->state.crtc_mask);
12087
12088         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12089                                           &dpll_hw_state,
12090                                           sizeof(dpll_hw_state)),
12091                         "pll hw state mismatch\n");
12092 }
12093
12094 static void
12095 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12096                          struct drm_crtc_state *old_crtc_state,
12097                          struct drm_crtc_state *new_crtc_state)
12098 {
12099         struct drm_i915_private *dev_priv = to_i915(dev);
12100         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12101         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12102
12103         if (new_state->shared_dpll)
12104                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12105
12106         if (old_state->shared_dpll &&
12107             old_state->shared_dpll != new_state->shared_dpll) {
12108                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12109                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12110
12111                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12112                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12113                                 pipe_name(drm_crtc_index(crtc)));
12114                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12115                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12116                                 pipe_name(drm_crtc_index(crtc)));
12117         }
12118 }
12119
12120 static void
12121 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12122                           struct drm_atomic_state *state,
12123                           struct drm_crtc_state *old_state,
12124                           struct drm_crtc_state *new_state)
12125 {
12126         if (!needs_modeset(new_state) &&
12127             !to_intel_crtc_state(new_state)->update_pipe)
12128                 return;
12129
12130         verify_wm_state(crtc, new_state);
12131         verify_connector_state(crtc->dev, state, crtc);
12132         verify_crtc_state(crtc, old_state, new_state);
12133         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12134 }
12135
12136 static void
12137 verify_disabled_dpll_state(struct drm_device *dev)
12138 {
12139         struct drm_i915_private *dev_priv = to_i915(dev);
12140         int i;
12141
12142         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12143                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12144 }
12145
12146 static void
12147 intel_modeset_verify_disabled(struct drm_device *dev,
12148                               struct drm_atomic_state *state)
12149 {
12150         verify_encoder_state(dev);
12151         verify_connector_state(dev, state, NULL);
12152         verify_disabled_dpll_state(dev);
12153 }
12154
12155 static void update_scanline_offset(struct intel_crtc *crtc)
12156 {
12157         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12158
12159         /*
12160          * The scanline counter increments at the leading edge of hsync.
12161          *
12162          * On most platforms it starts counting from vtotal-1 on the
12163          * first active line. That means the scanline counter value is
12164          * always one less than what we would expect. Ie. just after
12165          * start of vblank, which also occurs at start of hsync (on the
12166          * last active line), the scanline counter will read vblank_start-1.
12167          *
12168          * On gen2 the scanline counter starts counting from 1 instead
12169          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12170          * to keep the value positive), instead of adding one.
12171          *
12172          * On HSW+ the behaviour of the scanline counter depends on the output
12173          * type. For DP ports it behaves like most other platforms, but on HDMI
12174          * there's an extra 1 line difference. So we need to add two instead of
12175          * one to the value.
12176          */
12177         if (IS_GEN2(dev_priv)) {
12178                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12179                 int vtotal;
12180
12181                 vtotal = adjusted_mode->crtc_vtotal;
12182                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12183                         vtotal /= 2;
12184
12185                 crtc->scanline_offset = vtotal - 1;
12186         } else if (HAS_DDI(dev_priv) &&
12187                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12188                 crtc->scanline_offset = 2;
12189         } else
12190                 crtc->scanline_offset = 1;
12191 }
12192
12193 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12194 {
12195         struct drm_device *dev = state->dev;
12196         struct drm_i915_private *dev_priv = to_i915(dev);
12197         struct drm_crtc *crtc;
12198         struct drm_crtc_state *crtc_state;
12199         int i;
12200
12201         if (!dev_priv->display.crtc_compute_clock)
12202                 return;
12203
12204         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12205                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12206                 struct intel_shared_dpll *old_dpll =
12207                         to_intel_crtc_state(crtc->state)->shared_dpll;
12208
12209                 if (!needs_modeset(crtc_state))
12210                         continue;
12211
12212                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
12213
12214                 if (!old_dpll)
12215                         continue;
12216
12217                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12218         }
12219 }
12220
12221 /*
12222  * This implements the workaround described in the "notes" section of the mode
12223  * set sequence documentation. When going from no pipes or single pipe to
12224  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12225  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12226  */
12227 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12228 {
12229         struct drm_crtc_state *crtc_state;
12230         struct intel_crtc *intel_crtc;
12231         struct drm_crtc *crtc;
12232         struct intel_crtc_state *first_crtc_state = NULL;
12233         struct intel_crtc_state *other_crtc_state = NULL;
12234         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12235         int i;
12236
12237         /* look at all crtc's that are going to be enabled in during modeset */
12238         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12239                 intel_crtc = to_intel_crtc(crtc);
12240
12241                 if (!crtc_state->active || !needs_modeset(crtc_state))
12242                         continue;
12243
12244                 if (first_crtc_state) {
12245                         other_crtc_state = to_intel_crtc_state(crtc_state);
12246                         break;
12247                 } else {
12248                         first_crtc_state = to_intel_crtc_state(crtc_state);
12249                         first_pipe = intel_crtc->pipe;
12250                 }
12251         }
12252
12253         /* No workaround needed? */
12254         if (!first_crtc_state)
12255                 return 0;
12256
12257         /* w/a possibly needed, check how many crtc's are already enabled. */
12258         for_each_intel_crtc(state->dev, intel_crtc) {
12259                 struct intel_crtc_state *pipe_config;
12260
12261                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12262                 if (IS_ERR(pipe_config))
12263                         return PTR_ERR(pipe_config);
12264
12265                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12266
12267                 if (!pipe_config->base.active ||
12268                     needs_modeset(&pipe_config->base))
12269                         continue;
12270
12271                 /* 2 or more enabled crtcs means no need for w/a */
12272                 if (enabled_pipe != INVALID_PIPE)
12273                         return 0;
12274
12275                 enabled_pipe = intel_crtc->pipe;
12276         }
12277
12278         if (enabled_pipe != INVALID_PIPE)
12279                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12280         else if (other_crtc_state)
12281                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12282
12283         return 0;
12284 }
12285
12286 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12287 {
12288         struct drm_crtc *crtc;
12289
12290         /* Add all pipes to the state */
12291         for_each_crtc(state->dev, crtc) {
12292                 struct drm_crtc_state *crtc_state;
12293
12294                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12295                 if (IS_ERR(crtc_state))
12296                         return PTR_ERR(crtc_state);
12297         }
12298
12299         return 0;
12300 }
12301
12302 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12303 {
12304         struct drm_crtc *crtc;
12305
12306         /*
12307          * Add all pipes to the state, and force
12308          * a modeset on all the active ones.
12309          */
12310         for_each_crtc(state->dev, crtc) {
12311                 struct drm_crtc_state *crtc_state;
12312                 int ret;
12313
12314                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12315                 if (IS_ERR(crtc_state))
12316                         return PTR_ERR(crtc_state);
12317
12318                 if (!crtc_state->active || needs_modeset(crtc_state))
12319                         continue;
12320
12321                 crtc_state->mode_changed = true;
12322
12323                 ret = drm_atomic_add_affected_connectors(state, crtc);
12324                 if (ret)
12325                         return ret;
12326
12327                 ret = drm_atomic_add_affected_planes(state, crtc);
12328                 if (ret)
12329                         return ret;
12330         }
12331
12332         return 0;
12333 }
12334
12335 static int intel_modeset_checks(struct drm_atomic_state *state)
12336 {
12337         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12338         struct drm_i915_private *dev_priv = to_i915(state->dev);
12339         struct drm_crtc *crtc;
12340         struct drm_crtc_state *crtc_state;
12341         int ret = 0, i;
12342
12343         if (!check_digital_port_conflicts(state)) {
12344                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12345                 return -EINVAL;
12346         }
12347
12348         intel_state->modeset = true;
12349         intel_state->active_crtcs = dev_priv->active_crtcs;
12350         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12351         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12352
12353         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12354                 if (crtc_state->active)
12355                         intel_state->active_crtcs |= 1 << i;
12356                 else
12357                         intel_state->active_crtcs &= ~(1 << i);
12358
12359                 if (crtc_state->active != crtc->state->active)
12360                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12361         }
12362
12363         /*
12364          * See if the config requires any additional preparation, e.g.
12365          * to adjust global state with pipes off.  We need to do this
12366          * here so we can get the modeset_pipe updated config for the new
12367          * mode set on this crtc.  For other crtcs we need to use the
12368          * adjusted_mode bits in the crtc directly.
12369          */
12370         if (dev_priv->display.modeset_calc_cdclk) {
12371                 ret = dev_priv->display.modeset_calc_cdclk(state);
12372                 if (ret < 0)
12373                         return ret;
12374
12375                 /*
12376                  * Writes to dev_priv->cdclk.logical must protected by
12377                  * holding all the crtc locks, even if we don't end up
12378                  * touching the hardware
12379                  */
12380                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12381                                                &intel_state->cdclk.logical)) {
12382                         ret = intel_lock_all_pipes(state);
12383                         if (ret < 0)
12384                                 return ret;
12385                 }
12386
12387                 /* All pipes must be switched off while we change the cdclk. */
12388                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12389                                                &intel_state->cdclk.actual)) {
12390                         ret = intel_modeset_all_pipes(state);
12391                         if (ret < 0)
12392                                 return ret;
12393                 }
12394
12395                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12396                               intel_state->cdclk.logical.cdclk,
12397                               intel_state->cdclk.actual.cdclk);
12398         } else {
12399                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12400         }
12401
12402         intel_modeset_clear_plls(state);
12403
12404         if (IS_HASWELL(dev_priv))
12405                 return haswell_mode_set_planes_workaround(state);
12406
12407         return 0;
12408 }
12409
12410 /*
12411  * Handle calculation of various watermark data at the end of the atomic check
12412  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12413  * handlers to ensure that all derived state has been updated.
12414  */
12415 static int calc_watermark_data(struct drm_atomic_state *state)
12416 {
12417         struct drm_device *dev = state->dev;
12418         struct drm_i915_private *dev_priv = to_i915(dev);
12419
12420         /* Is there platform-specific watermark information to calculate? */
12421         if (dev_priv->display.compute_global_watermarks)
12422                 return dev_priv->display.compute_global_watermarks(state);
12423
12424         return 0;
12425 }
12426
12427 /**
12428  * intel_atomic_check - validate state object
12429  * @dev: drm device
12430  * @state: state to validate
12431  */
12432 static int intel_atomic_check(struct drm_device *dev,
12433                               struct drm_atomic_state *state)
12434 {
12435         struct drm_i915_private *dev_priv = to_i915(dev);
12436         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12437         struct drm_crtc *crtc;
12438         struct drm_crtc_state *crtc_state;
12439         int ret, i;
12440         bool any_ms = false;
12441
12442         ret = drm_atomic_helper_check_modeset(dev, state);
12443         if (ret)
12444                 return ret;
12445
12446         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12447                 struct intel_crtc_state *pipe_config =
12448                         to_intel_crtc_state(crtc_state);
12449
12450                 /* Catch I915_MODE_FLAG_INHERITED */
12451                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12452                         crtc_state->mode_changed = true;
12453
12454                 if (!needs_modeset(crtc_state))
12455                         continue;
12456
12457                 if (!crtc_state->enable) {
12458                         any_ms = true;
12459                         continue;
12460                 }
12461
12462                 /* FIXME: For only active_changed we shouldn't need to do any
12463                  * state recomputation at all. */
12464
12465                 ret = drm_atomic_add_affected_connectors(state, crtc);
12466                 if (ret)
12467                         return ret;
12468
12469                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12470                 if (ret) {
12471                         intel_dump_pipe_config(to_intel_crtc(crtc),
12472                                                pipe_config, "[failed]");
12473                         return ret;
12474                 }
12475
12476                 if (i915.fastboot &&
12477                     intel_pipe_config_compare(dev_priv,
12478                                         to_intel_crtc_state(crtc->state),
12479                                         pipe_config, true)) {
12480                         crtc_state->mode_changed = false;
12481                         to_intel_crtc_state(crtc_state)->update_pipe = true;
12482                 }
12483
12484                 if (needs_modeset(crtc_state))
12485                         any_ms = true;
12486
12487                 ret = drm_atomic_add_affected_planes(state, crtc);
12488                 if (ret)
12489                         return ret;
12490
12491                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12492                                        needs_modeset(crtc_state) ?
12493                                        "[modeset]" : "[fastset]");
12494         }
12495
12496         if (any_ms) {
12497                 ret = intel_modeset_checks(state);
12498
12499                 if (ret)
12500                         return ret;
12501         } else {
12502                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12503         }
12504
12505         ret = drm_atomic_helper_check_planes(dev, state);
12506         if (ret)
12507                 return ret;
12508
12509         intel_fbc_choose_crtc(dev_priv, state);
12510         return calc_watermark_data(state);
12511 }
12512
12513 static int intel_atomic_prepare_commit(struct drm_device *dev,
12514                                        struct drm_atomic_state *state)
12515 {
12516         struct drm_i915_private *dev_priv = to_i915(dev);
12517         struct drm_crtc_state *crtc_state;
12518         struct drm_crtc *crtc;
12519         int i, ret;
12520
12521         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12522                 if (state->legacy_cursor_update)
12523                         continue;
12524
12525                 ret = intel_crtc_wait_for_pending_flips(crtc);
12526                 if (ret)
12527                         return ret;
12528
12529                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12530                         flush_workqueue(dev_priv->wq);
12531         }
12532
12533         ret = mutex_lock_interruptible(&dev->struct_mutex);
12534         if (ret)
12535                 return ret;
12536
12537         ret = drm_atomic_helper_prepare_planes(dev, state);
12538         mutex_unlock(&dev->struct_mutex);
12539
12540         return ret;
12541 }
12542
12543 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12544 {
12545         struct drm_device *dev = crtc->base.dev;
12546
12547         if (!dev->max_vblank_count)
12548                 return drm_accurate_vblank_count(&crtc->base);
12549
12550         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12551 }
12552
12553 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12554                                           struct drm_i915_private *dev_priv,
12555                                           unsigned crtc_mask)
12556 {
12557         unsigned last_vblank_count[I915_MAX_PIPES];
12558         enum pipe pipe;
12559         int ret;
12560
12561         if (!crtc_mask)
12562                 return;
12563
12564         for_each_pipe(dev_priv, pipe) {
12565                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12566                                                                   pipe);
12567
12568                 if (!((1 << pipe) & crtc_mask))
12569                         continue;
12570
12571                 ret = drm_crtc_vblank_get(&crtc->base);
12572                 if (WARN_ON(ret != 0)) {
12573                         crtc_mask &= ~(1 << pipe);
12574                         continue;
12575                 }
12576
12577                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12578         }
12579
12580         for_each_pipe(dev_priv, pipe) {
12581                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12582                                                                   pipe);
12583                 long lret;
12584
12585                 if (!((1 << pipe) & crtc_mask))
12586                         continue;
12587
12588                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12589                                 last_vblank_count[pipe] !=
12590                                         drm_crtc_vblank_count(&crtc->base),
12591                                 msecs_to_jiffies(50));
12592
12593                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12594
12595                 drm_crtc_vblank_put(&crtc->base);
12596         }
12597 }
12598
12599 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12600 {
12601         /* fb updated, need to unpin old fb */
12602         if (crtc_state->fb_changed)
12603                 return true;
12604
12605         /* wm changes, need vblank before final wm's */
12606         if (crtc_state->update_wm_post)
12607                 return true;
12608
12609         if (crtc_state->wm.need_postvbl_update)
12610                 return true;
12611
12612         return false;
12613 }
12614
12615 static void intel_update_crtc(struct drm_crtc *crtc,
12616                               struct drm_atomic_state *state,
12617                               struct drm_crtc_state *old_crtc_state,
12618                               unsigned int *crtc_vblank_mask)
12619 {
12620         struct drm_device *dev = crtc->dev;
12621         struct drm_i915_private *dev_priv = to_i915(dev);
12622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12623         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
12624         bool modeset = needs_modeset(crtc->state);
12625
12626         if (modeset) {
12627                 update_scanline_offset(intel_crtc);
12628                 dev_priv->display.crtc_enable(pipe_config, state);
12629         } else {
12630                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
12631         }
12632
12633         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12634                 intel_fbc_enable(
12635                     intel_crtc, pipe_config,
12636                     to_intel_plane_state(crtc->primary->state));
12637         }
12638
12639         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12640
12641         if (needs_vblank_wait(pipe_config))
12642                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12643 }
12644
12645 static void intel_update_crtcs(struct drm_atomic_state *state,
12646                                unsigned int *crtc_vblank_mask)
12647 {
12648         struct drm_crtc *crtc;
12649         struct drm_crtc_state *old_crtc_state;
12650         int i;
12651
12652         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12653                 if (!crtc->state->active)
12654                         continue;
12655
12656                 intel_update_crtc(crtc, state, old_crtc_state,
12657                                   crtc_vblank_mask);
12658         }
12659 }
12660
12661 static void skl_update_crtcs(struct drm_atomic_state *state,
12662                              unsigned int *crtc_vblank_mask)
12663 {
12664         struct drm_i915_private *dev_priv = to_i915(state->dev);
12665         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12666         struct drm_crtc *crtc;
12667         struct intel_crtc *intel_crtc;
12668         struct drm_crtc_state *old_crtc_state;
12669         struct intel_crtc_state *cstate;
12670         unsigned int updated = 0;
12671         bool progress;
12672         enum pipe pipe;
12673         int i;
12674
12675         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12676
12677         for_each_crtc_in_state(state, crtc, old_crtc_state, i)
12678                 /* ignore allocations for crtc's that have been turned off. */
12679                 if (crtc->state->active)
12680                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12681
12682         /*
12683          * Whenever the number of active pipes changes, we need to make sure we
12684          * update the pipes in the right order so that their ddb allocations
12685          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12686          * cause pipe underruns and other bad stuff.
12687          */
12688         do {
12689                 progress = false;
12690
12691                 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12692                         bool vbl_wait = false;
12693                         unsigned int cmask = drm_crtc_mask(crtc);
12694
12695                         intel_crtc = to_intel_crtc(crtc);
12696                         cstate = to_intel_crtc_state(crtc->state);
12697                         pipe = intel_crtc->pipe;
12698
12699                         if (updated & cmask || !cstate->base.active)
12700                                 continue;
12701
12702                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12703                                 continue;
12704
12705                         updated |= cmask;
12706                         entries[i] = &cstate->wm.skl.ddb;
12707
12708                         /*
12709                          * If this is an already active pipe, it's DDB changed,
12710                          * and this isn't the last pipe that needs updating
12711                          * then we need to wait for a vblank to pass for the
12712                          * new ddb allocation to take effect.
12713                          */
12714                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12715                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12716                             !crtc->state->active_changed &&
12717                             intel_state->wm_results.dirty_pipes != updated)
12718                                 vbl_wait = true;
12719
12720                         intel_update_crtc(crtc, state, old_crtc_state,
12721                                           crtc_vblank_mask);
12722
12723                         if (vbl_wait)
12724                                 intel_wait_for_vblank(dev_priv, pipe);
12725
12726                         progress = true;
12727                 }
12728         } while (progress);
12729 }
12730
12731 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12732 {
12733         struct intel_atomic_state *state, *next;
12734         struct llist_node *freed;
12735
12736         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12737         llist_for_each_entry_safe(state, next, freed, freed)
12738                 drm_atomic_state_put(&state->base);
12739 }
12740
12741 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12742 {
12743         struct drm_i915_private *dev_priv =
12744                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12745
12746         intel_atomic_helper_free_state(dev_priv);
12747 }
12748
12749 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12750 {
12751         struct drm_device *dev = state->dev;
12752         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12753         struct drm_i915_private *dev_priv = to_i915(dev);
12754         struct drm_crtc_state *old_crtc_state;
12755         struct drm_crtc *crtc;
12756         struct intel_crtc_state *intel_cstate;
12757         bool hw_check = intel_state->modeset;
12758         u64 put_domains[I915_MAX_PIPES] = {};
12759         unsigned crtc_vblank_mask = 0;
12760         int i;
12761
12762         drm_atomic_helper_wait_for_dependencies(state);
12763
12764         if (intel_state->modeset)
12765                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12766
12767         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12768                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12769
12770                 if (needs_modeset(crtc->state) ||
12771                     to_intel_crtc_state(crtc->state)->update_pipe) {
12772                         hw_check = true;
12773
12774                         put_domains[to_intel_crtc(crtc)->pipe] =
12775                                 modeset_get_crtc_power_domains(crtc,
12776                                         to_intel_crtc_state(crtc->state));
12777                 }
12778
12779                 if (!needs_modeset(crtc->state))
12780                         continue;
12781
12782                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
12783
12784                 if (old_crtc_state->active) {
12785                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12786                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12787                         intel_crtc->active = false;
12788                         intel_fbc_disable(intel_crtc);
12789                         intel_disable_shared_dpll(intel_crtc);
12790
12791                         /*
12792                          * Underruns don't always raise
12793                          * interrupts, so check manually.
12794                          */
12795                         intel_check_cpu_fifo_underruns(dev_priv);
12796                         intel_check_pch_fifo_underruns(dev_priv);
12797
12798                         if (!crtc->state->active) {
12799                                 /*
12800                                  * Make sure we don't call initial_watermarks
12801                                  * for ILK-style watermark updates.
12802                                  *
12803                                  * No clue what this is supposed to achieve.
12804                                  */
12805                                 if (INTEL_GEN(dev_priv) >= 9)
12806                                         dev_priv->display.initial_watermarks(intel_state,
12807                                                                              to_intel_crtc_state(crtc->state));
12808                         }
12809                 }
12810         }
12811
12812         /* Only after disabling all output pipelines that will be changed can we
12813          * update the the output configuration. */
12814         intel_modeset_update_crtc_state(state);
12815
12816         if (intel_state->modeset) {
12817                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12818
12819                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12820
12821                 /*
12822                  * SKL workaround: bspec recommends we disable the SAGV when we
12823                  * have more then one pipe enabled
12824                  */
12825                 if (!intel_can_enable_sagv(state))
12826                         intel_disable_sagv(dev_priv);
12827
12828                 intel_modeset_verify_disabled(dev, state);
12829         }
12830
12831         /* Complete the events for pipes that have now been disabled */
12832         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12833                 bool modeset = needs_modeset(crtc->state);
12834
12835                 /* Complete events for now disable pipes here. */
12836                 if (modeset && !crtc->state->active && crtc->state->event) {
12837                         spin_lock_irq(&dev->event_lock);
12838                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
12839                         spin_unlock_irq(&dev->event_lock);
12840
12841                         crtc->state->event = NULL;
12842                 }
12843         }
12844
12845         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12846         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12847
12848         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12849          * already, but still need the state for the delayed optimization. To
12850          * fix this:
12851          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12852          * - schedule that vblank worker _before_ calling hw_done
12853          * - at the start of commit_tail, cancel it _synchrously
12854          * - switch over to the vblank wait helper in the core after that since
12855          *   we don't need out special handling any more.
12856          */
12857         if (!state->legacy_cursor_update)
12858                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12859
12860         /*
12861          * Now that the vblank has passed, we can go ahead and program the
12862          * optimal watermarks on platforms that need two-step watermark
12863          * programming.
12864          *
12865          * TODO: Move this (and other cleanup) to an async worker eventually.
12866          */
12867         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12868                 intel_cstate = to_intel_crtc_state(crtc->state);
12869
12870                 if (dev_priv->display.optimize_watermarks)
12871                         dev_priv->display.optimize_watermarks(intel_state,
12872                                                               intel_cstate);
12873         }
12874
12875         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12876                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12877
12878                 if (put_domains[i])
12879                         modeset_put_power_domains(dev_priv, put_domains[i]);
12880
12881                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
12882         }
12883
12884         if (intel_state->modeset && intel_can_enable_sagv(state))
12885                 intel_enable_sagv(dev_priv);
12886
12887         drm_atomic_helper_commit_hw_done(state);
12888
12889         if (intel_state->modeset)
12890                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12891
12892         mutex_lock(&dev->struct_mutex);
12893         drm_atomic_helper_cleanup_planes(dev, state);
12894         mutex_unlock(&dev->struct_mutex);
12895
12896         drm_atomic_helper_commit_cleanup_done(state);
12897
12898         drm_atomic_state_put(state);
12899
12900         /* As one of the primary mmio accessors, KMS has a high likelihood
12901          * of triggering bugs in unclaimed access. After we finish
12902          * modesetting, see if an error has been flagged, and if so
12903          * enable debugging for the next modeset - and hope we catch
12904          * the culprit.
12905          *
12906          * XXX note that we assume display power is on at this point.
12907          * This might hold true now but we need to add pm helper to check
12908          * unclaimed only when the hardware is on, as atomic commits
12909          * can happen also when the device is completely off.
12910          */
12911         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12912
12913         intel_atomic_helper_free_state(dev_priv);
12914 }
12915
12916 static void intel_atomic_commit_work(struct work_struct *work)
12917 {
12918         struct drm_atomic_state *state =
12919                 container_of(work, struct drm_atomic_state, commit_work);
12920
12921         intel_atomic_commit_tail(state);
12922 }
12923
12924 static int __i915_sw_fence_call
12925 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12926                           enum i915_sw_fence_notify notify)
12927 {
12928         struct intel_atomic_state *state =
12929                 container_of(fence, struct intel_atomic_state, commit_ready);
12930
12931         switch (notify) {
12932         case FENCE_COMPLETE:
12933                 if (state->base.commit_work.func)
12934                         queue_work(system_unbound_wq, &state->base.commit_work);
12935                 break;
12936
12937         case FENCE_FREE:
12938                 {
12939                         struct intel_atomic_helper *helper =
12940                                 &to_i915(state->base.dev)->atomic_helper;
12941
12942                         if (llist_add(&state->freed, &helper->free_list))
12943                                 schedule_work(&helper->free_work);
12944                         break;
12945                 }
12946         }
12947
12948         return NOTIFY_DONE;
12949 }
12950
12951 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12952 {
12953         struct drm_plane_state *old_plane_state;
12954         struct drm_plane *plane;
12955         int i;
12956
12957         for_each_plane_in_state(state, plane, old_plane_state, i)
12958                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12959                                   intel_fb_obj(plane->state->fb),
12960                                   to_intel_plane(plane)->frontbuffer_bit);
12961 }
12962
12963 /**
12964  * intel_atomic_commit - commit validated state object
12965  * @dev: DRM device
12966  * @state: the top-level driver state object
12967  * @nonblock: nonblocking commit
12968  *
12969  * This function commits a top-level state object that has been validated
12970  * with drm_atomic_helper_check().
12971  *
12972  * RETURNS
12973  * Zero for success or -errno.
12974  */
12975 static int intel_atomic_commit(struct drm_device *dev,
12976                                struct drm_atomic_state *state,
12977                                bool nonblock)
12978 {
12979         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12980         struct drm_i915_private *dev_priv = to_i915(dev);
12981         int ret = 0;
12982
12983         /*
12984          * The intel_legacy_cursor_update() fast path takes care
12985          * of avoiding the vblank waits for simple cursor
12986          * movement and flips. For cursor on/off and size changes,
12987          * we want to perform the vblank waits so that watermark
12988          * updates happen during the correct frames. Gen9+ have
12989          * double buffered watermarks and so shouldn't need this.
12990          */
12991         if (INTEL_GEN(dev_priv) < 9)
12992                 state->legacy_cursor_update = false;
12993
12994         ret = drm_atomic_helper_setup_commit(state, nonblock);
12995         if (ret)
12996                 return ret;
12997
12998         drm_atomic_state_get(state);
12999         i915_sw_fence_init(&intel_state->commit_ready,
13000                            intel_atomic_commit_ready);
13001
13002         ret = intel_atomic_prepare_commit(dev, state);
13003         if (ret) {
13004                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13005                 i915_sw_fence_commit(&intel_state->commit_ready);
13006                 return ret;
13007         }
13008
13009         drm_atomic_helper_swap_state(state, true);
13010         dev_priv->wm.distrust_bios_wm = false;
13011         intel_shared_dpll_swap_state(state);
13012         intel_atomic_track_fbs(state);
13013
13014         if (intel_state->modeset) {
13015                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13016                        sizeof(intel_state->min_pixclk));
13017                 dev_priv->active_crtcs = intel_state->active_crtcs;
13018                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13019                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13020         }
13021
13022         drm_atomic_state_get(state);
13023         INIT_WORK(&state->commit_work,
13024                   nonblock ? intel_atomic_commit_work : NULL);
13025
13026         i915_sw_fence_commit(&intel_state->commit_ready);
13027         if (!nonblock) {
13028                 i915_sw_fence_wait(&intel_state->commit_ready);
13029                 intel_atomic_commit_tail(state);
13030         }
13031
13032         return 0;
13033 }
13034
13035 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13036 {
13037         struct drm_device *dev = crtc->dev;
13038         struct drm_atomic_state *state;
13039         struct drm_crtc_state *crtc_state;
13040         int ret;
13041
13042         state = drm_atomic_state_alloc(dev);
13043         if (!state) {
13044                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13045                               crtc->base.id, crtc->name);
13046                 return;
13047         }
13048
13049         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13050
13051 retry:
13052         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13053         ret = PTR_ERR_OR_ZERO(crtc_state);
13054         if (!ret) {
13055                 if (!crtc_state->active)
13056                         goto out;
13057
13058                 crtc_state->mode_changed = true;
13059                 ret = drm_atomic_commit(state);
13060         }
13061
13062         if (ret == -EDEADLK) {
13063                 drm_atomic_state_clear(state);
13064                 drm_modeset_backoff(state->acquire_ctx);
13065                 goto retry;
13066         }
13067
13068 out:
13069         drm_atomic_state_put(state);
13070 }
13071
13072 /*
13073  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13074  *        drm_atomic_helper_legacy_gamma_set() directly.
13075  */
13076 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13077                                          u16 *red, u16 *green, u16 *blue,
13078                                          uint32_t size)
13079 {
13080         struct drm_device *dev = crtc->dev;
13081         struct drm_mode_config *config = &dev->mode_config;
13082         struct drm_crtc_state *state;
13083         int ret;
13084
13085         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13086         if (ret)
13087                 return ret;
13088
13089         /*
13090          * Make sure we update the legacy properties so this works when
13091          * atomic is not enabled.
13092          */
13093
13094         state = crtc->state;
13095
13096         drm_object_property_set_value(&crtc->base,
13097                                       config->degamma_lut_property,
13098                                       (state->degamma_lut) ?
13099                                       state->degamma_lut->base.id : 0);
13100
13101         drm_object_property_set_value(&crtc->base,
13102                                       config->ctm_property,
13103                                       (state->ctm) ?
13104                                       state->ctm->base.id : 0);
13105
13106         drm_object_property_set_value(&crtc->base,
13107                                       config->gamma_lut_property,
13108                                       (state->gamma_lut) ?
13109                                       state->gamma_lut->base.id : 0);
13110
13111         return 0;
13112 }
13113
13114 static const struct drm_crtc_funcs intel_crtc_funcs = {
13115         .gamma_set = intel_atomic_legacy_gamma_set,
13116         .set_config = drm_atomic_helper_set_config,
13117         .set_property = drm_atomic_helper_crtc_set_property,
13118         .destroy = intel_crtc_destroy,
13119         .page_flip = drm_atomic_helper_page_flip,
13120         .atomic_duplicate_state = intel_crtc_duplicate_state,
13121         .atomic_destroy_state = intel_crtc_destroy_state,
13122         .set_crc_source = intel_crtc_set_crc_source,
13123 };
13124
13125 /**
13126  * intel_prepare_plane_fb - Prepare fb for usage on plane
13127  * @plane: drm plane to prepare for
13128  * @fb: framebuffer to prepare for presentation
13129  *
13130  * Prepares a framebuffer for usage on a display plane.  Generally this
13131  * involves pinning the underlying object and updating the frontbuffer tracking
13132  * bits.  Some older platforms need special physical address handling for
13133  * cursor planes.
13134  *
13135  * Must be called with struct_mutex held.
13136  *
13137  * Returns 0 on success, negative error code on failure.
13138  */
13139 int
13140 intel_prepare_plane_fb(struct drm_plane *plane,
13141                        struct drm_plane_state *new_state)
13142 {
13143         struct intel_atomic_state *intel_state =
13144                 to_intel_atomic_state(new_state->state);
13145         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13146         struct drm_framebuffer *fb = new_state->fb;
13147         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13148         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13149         int ret;
13150
13151         if (obj) {
13152                 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13153                     INTEL_INFO(dev_priv)->cursor_needs_physical) {
13154                         const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13155
13156                         ret = i915_gem_object_attach_phys(obj, align);
13157                         if (ret) {
13158                                 DRM_DEBUG_KMS("failed to attach phys object\n");
13159                                 return ret;
13160                         }
13161                 } else {
13162                         struct i915_vma *vma;
13163
13164                         vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13165                         if (IS_ERR(vma)) {
13166                                 DRM_DEBUG_KMS("failed to pin object\n");
13167                                 return PTR_ERR(vma);
13168                         }
13169
13170                         to_intel_plane_state(new_state)->vma = vma;
13171                 }
13172         }
13173
13174         if (!obj && !old_obj)
13175                 return 0;
13176
13177         if (old_obj) {
13178                 struct drm_crtc_state *crtc_state =
13179                         drm_atomic_get_existing_crtc_state(new_state->state,
13180                                                            plane->state->crtc);
13181
13182                 /* Big Hammer, we also need to ensure that any pending
13183                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13184                  * current scanout is retired before unpinning the old
13185                  * framebuffer. Note that we rely on userspace rendering
13186                  * into the buffer attached to the pipe they are waiting
13187                  * on. If not, userspace generates a GPU hang with IPEHR
13188                  * point to the MI_WAIT_FOR_EVENT.
13189                  *
13190                  * This should only fail upon a hung GPU, in which case we
13191                  * can safely continue.
13192                  */
13193                 if (needs_modeset(crtc_state)) {
13194                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13195                                                               old_obj->resv, NULL,
13196                                                               false, 0,
13197                                                               GFP_KERNEL);
13198                         if (ret < 0)
13199                                 return ret;
13200                 }
13201         }
13202
13203         if (new_state->fence) { /* explicit fencing */
13204                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13205                                                     new_state->fence,
13206                                                     I915_FENCE_TIMEOUT,
13207                                                     GFP_KERNEL);
13208                 if (ret < 0)
13209                         return ret;
13210         }
13211
13212         if (!obj)
13213                 return 0;
13214
13215         if (!new_state->fence) { /* implicit fencing */
13216                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13217                                                       obj->resv, NULL,
13218                                                       false, I915_FENCE_TIMEOUT,
13219                                                       GFP_KERNEL);
13220                 if (ret < 0)
13221                         return ret;
13222
13223                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13224         }
13225
13226         return 0;
13227 }
13228
13229 /**
13230  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13231  * @plane: drm plane to clean up for
13232  * @fb: old framebuffer that was on plane
13233  *
13234  * Cleans up a framebuffer that has just been removed from a plane.
13235  *
13236  * Must be called with struct_mutex held.
13237  */
13238 void
13239 intel_cleanup_plane_fb(struct drm_plane *plane,
13240                        struct drm_plane_state *old_state)
13241 {
13242         struct i915_vma *vma;
13243
13244         /* Should only be called after a successful intel_prepare_plane_fb()! */
13245         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13246         if (vma)
13247                 intel_unpin_fb_vma(vma);
13248 }
13249
13250 int
13251 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13252 {
13253         struct drm_i915_private *dev_priv;
13254         int max_scale;
13255         int crtc_clock, max_dotclk;
13256
13257         if (!intel_crtc || !crtc_state->base.enable)
13258                 return DRM_PLANE_HELPER_NO_SCALING;
13259
13260         dev_priv = to_i915(intel_crtc->base.dev);
13261
13262         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13263         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13264
13265         if (IS_GEMINILAKE(dev_priv))
13266                 max_dotclk *= 2;
13267
13268         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13269                 return DRM_PLANE_HELPER_NO_SCALING;
13270
13271         /*
13272          * skl max scale is lower of:
13273          *    close to 3 but not 3, -1 is for that purpose
13274          *            or
13275          *    cdclk/crtc_clock
13276          */
13277         max_scale = min((1 << 16) * 3 - 1,
13278                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13279
13280         return max_scale;
13281 }
13282
13283 static int
13284 intel_check_primary_plane(struct drm_plane *plane,
13285                           struct intel_crtc_state *crtc_state,
13286                           struct intel_plane_state *state)
13287 {
13288         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13289         struct drm_crtc *crtc = state->base.crtc;
13290         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13291         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13292         bool can_position = false;
13293         int ret;
13294
13295         if (INTEL_GEN(dev_priv) >= 9) {
13296                 /* use scaler when colorkey is not required */
13297                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13298                         min_scale = 1;
13299                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13300                 }
13301                 can_position = true;
13302         }
13303
13304         ret = drm_plane_helper_check_state(&state->base,
13305                                            &state->clip,
13306                                            min_scale, max_scale,
13307                                            can_position, true);
13308         if (ret)
13309                 return ret;
13310
13311         if (!state->base.fb)
13312                 return 0;
13313
13314         if (INTEL_GEN(dev_priv) >= 9) {
13315                 ret = skl_check_plane_surface(state);
13316                 if (ret)
13317                         return ret;
13318         }
13319
13320         return 0;
13321 }
13322
13323 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13324                                     struct drm_crtc_state *old_crtc_state)
13325 {
13326         struct drm_device *dev = crtc->dev;
13327         struct drm_i915_private *dev_priv = to_i915(dev);
13328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13329         struct intel_crtc_state *intel_cstate =
13330                 to_intel_crtc_state(crtc->state);
13331         struct intel_crtc_state *old_intel_cstate =
13332                 to_intel_crtc_state(old_crtc_state);
13333         struct intel_atomic_state *old_intel_state =
13334                 to_intel_atomic_state(old_crtc_state->state);
13335         bool modeset = needs_modeset(crtc->state);
13336
13337         if (!modeset &&
13338             (intel_cstate->base.color_mgmt_changed ||
13339              intel_cstate->update_pipe)) {
13340                 intel_color_set_csc(crtc->state);
13341                 intel_color_load_luts(crtc->state);
13342         }
13343
13344         /* Perform vblank evasion around commit operation */
13345         intel_pipe_update_start(intel_crtc);
13346
13347         if (modeset)
13348                 goto out;
13349
13350         if (intel_cstate->update_pipe)
13351                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13352         else if (INTEL_GEN(dev_priv) >= 9)
13353                 skl_detach_scalers(intel_crtc);
13354
13355 out:
13356         if (dev_priv->display.atomic_update_watermarks)
13357                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13358                                                            intel_cstate);
13359 }
13360
13361 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13362                                      struct drm_crtc_state *old_crtc_state)
13363 {
13364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13365
13366         intel_pipe_update_end(intel_crtc, NULL);
13367 }
13368
13369 /**
13370  * intel_plane_destroy - destroy a plane
13371  * @plane: plane to destroy
13372  *
13373  * Common destruction function for all types of planes (primary, cursor,
13374  * sprite).
13375  */
13376 void intel_plane_destroy(struct drm_plane *plane)
13377 {
13378         drm_plane_cleanup(plane);
13379         kfree(to_intel_plane(plane));
13380 }
13381
13382 const struct drm_plane_funcs intel_plane_funcs = {
13383         .update_plane = drm_atomic_helper_update_plane,
13384         .disable_plane = drm_atomic_helper_disable_plane,
13385         .destroy = intel_plane_destroy,
13386         .set_property = drm_atomic_helper_plane_set_property,
13387         .atomic_get_property = intel_plane_atomic_get_property,
13388         .atomic_set_property = intel_plane_atomic_set_property,
13389         .atomic_duplicate_state = intel_plane_duplicate_state,
13390         .atomic_destroy_state = intel_plane_destroy_state,
13391 };
13392
13393 static int
13394 intel_legacy_cursor_update(struct drm_plane *plane,
13395                            struct drm_crtc *crtc,
13396                            struct drm_framebuffer *fb,
13397                            int crtc_x, int crtc_y,
13398                            unsigned int crtc_w, unsigned int crtc_h,
13399                            uint32_t src_x, uint32_t src_y,
13400                            uint32_t src_w, uint32_t src_h)
13401 {
13402         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13403         int ret;
13404         struct drm_plane_state *old_plane_state, *new_plane_state;
13405         struct intel_plane *intel_plane = to_intel_plane(plane);
13406         struct drm_framebuffer *old_fb;
13407         struct drm_crtc_state *crtc_state = crtc->state;
13408         struct i915_vma *old_vma;
13409
13410         /*
13411          * When crtc is inactive or there is a modeset pending,
13412          * wait for it to complete in the slowpath
13413          */
13414         if (!crtc_state->active || needs_modeset(crtc_state) ||
13415             to_intel_crtc_state(crtc_state)->update_pipe)
13416                 goto slow;
13417
13418         old_plane_state = plane->state;
13419
13420         /*
13421          * If any parameters change that may affect watermarks,
13422          * take the slowpath. Only changing fb or position should be
13423          * in the fastpath.
13424          */
13425         if (old_plane_state->crtc != crtc ||
13426             old_plane_state->src_w != src_w ||
13427             old_plane_state->src_h != src_h ||
13428             old_plane_state->crtc_w != crtc_w ||
13429             old_plane_state->crtc_h != crtc_h ||
13430             !old_plane_state->fb != !fb)
13431                 goto slow;
13432
13433         new_plane_state = intel_plane_duplicate_state(plane);
13434         if (!new_plane_state)
13435                 return -ENOMEM;
13436
13437         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13438
13439         new_plane_state->src_x = src_x;
13440         new_plane_state->src_y = src_y;
13441         new_plane_state->src_w = src_w;
13442         new_plane_state->src_h = src_h;
13443         new_plane_state->crtc_x = crtc_x;
13444         new_plane_state->crtc_y = crtc_y;
13445         new_plane_state->crtc_w = crtc_w;
13446         new_plane_state->crtc_h = crtc_h;
13447
13448         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13449                                                   to_intel_plane_state(new_plane_state));
13450         if (ret)
13451                 goto out_free;
13452
13453         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13454         if (ret)
13455                 goto out_free;
13456
13457         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13458                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13459
13460                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13461                 if (ret) {
13462                         DRM_DEBUG_KMS("failed to attach phys object\n");
13463                         goto out_unlock;
13464                 }
13465         } else {
13466                 struct i915_vma *vma;
13467
13468                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13469                 if (IS_ERR(vma)) {
13470                         DRM_DEBUG_KMS("failed to pin object\n");
13471
13472                         ret = PTR_ERR(vma);
13473                         goto out_unlock;
13474                 }
13475
13476                 to_intel_plane_state(new_plane_state)->vma = vma;
13477         }
13478
13479         old_fb = old_plane_state->fb;
13480         old_vma = to_intel_plane_state(old_plane_state)->vma;
13481
13482         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13483                           intel_plane->frontbuffer_bit);
13484
13485         /* Swap plane state */
13486         new_plane_state->fence = old_plane_state->fence;
13487         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13488         new_plane_state->fence = NULL;
13489         new_plane_state->fb = old_fb;
13490         to_intel_plane_state(new_plane_state)->vma = old_vma;
13491
13492         if (plane->state->visible) {
13493                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13494                 intel_plane->update_plane(plane,
13495                                           to_intel_crtc_state(crtc->state),
13496                                           to_intel_plane_state(plane->state));
13497         } else {
13498                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13499                 intel_plane->disable_plane(plane, crtc);
13500         }
13501
13502         intel_cleanup_plane_fb(plane, new_plane_state);
13503
13504 out_unlock:
13505         mutex_unlock(&dev_priv->drm.struct_mutex);
13506 out_free:
13507         intel_plane_destroy_state(plane, new_plane_state);
13508         return ret;
13509
13510 slow:
13511         return drm_atomic_helper_update_plane(plane, crtc, fb,
13512                                               crtc_x, crtc_y, crtc_w, crtc_h,
13513                                               src_x, src_y, src_w, src_h);
13514 }
13515
13516 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13517         .update_plane = intel_legacy_cursor_update,
13518         .disable_plane = drm_atomic_helper_disable_plane,
13519         .destroy = intel_plane_destroy,
13520         .set_property = drm_atomic_helper_plane_set_property,
13521         .atomic_get_property = intel_plane_atomic_get_property,
13522         .atomic_set_property = intel_plane_atomic_set_property,
13523         .atomic_duplicate_state = intel_plane_duplicate_state,
13524         .atomic_destroy_state = intel_plane_destroy_state,
13525 };
13526
13527 static struct intel_plane *
13528 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13529 {
13530         struct intel_plane *primary = NULL;
13531         struct intel_plane_state *state = NULL;
13532         const uint32_t *intel_primary_formats;
13533         unsigned int supported_rotations;
13534         unsigned int num_formats;
13535         int ret;
13536
13537         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13538         if (!primary) {
13539                 ret = -ENOMEM;
13540                 goto fail;
13541         }
13542
13543         state = intel_create_plane_state(&primary->base);
13544         if (!state) {
13545                 ret = -ENOMEM;
13546                 goto fail;
13547         }
13548
13549         primary->base.state = &state->base;
13550
13551         primary->can_scale = false;
13552         primary->max_downscale = 1;
13553         if (INTEL_GEN(dev_priv) >= 9) {
13554                 primary->can_scale = true;
13555                 state->scaler_id = -1;
13556         }
13557         primary->pipe = pipe;
13558         /*
13559          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13560          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13561          */
13562         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13563                 primary->plane = (enum plane) !pipe;
13564         else
13565                 primary->plane = (enum plane) pipe;
13566         primary->id = PLANE_PRIMARY;
13567         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13568         primary->check_plane = intel_check_primary_plane;
13569
13570         if (INTEL_GEN(dev_priv) >= 9) {
13571                 intel_primary_formats = skl_primary_formats;
13572                 num_formats = ARRAY_SIZE(skl_primary_formats);
13573
13574                 primary->update_plane = skylake_update_primary_plane;
13575                 primary->disable_plane = skylake_disable_primary_plane;
13576         } else if (HAS_PCH_SPLIT(dev_priv)) {
13577                 intel_primary_formats = i965_primary_formats;
13578                 num_formats = ARRAY_SIZE(i965_primary_formats);
13579
13580                 primary->update_plane = ironlake_update_primary_plane;
13581                 primary->disable_plane = i9xx_disable_primary_plane;
13582         } else if (INTEL_GEN(dev_priv) >= 4) {
13583                 intel_primary_formats = i965_primary_formats;
13584                 num_formats = ARRAY_SIZE(i965_primary_formats);
13585
13586                 primary->update_plane = i9xx_update_primary_plane;
13587                 primary->disable_plane = i9xx_disable_primary_plane;
13588         } else {
13589                 intel_primary_formats = i8xx_primary_formats;
13590                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13591
13592                 primary->update_plane = i9xx_update_primary_plane;
13593                 primary->disable_plane = i9xx_disable_primary_plane;
13594         }
13595
13596         if (INTEL_GEN(dev_priv) >= 9)
13597                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13598                                                0, &intel_plane_funcs,
13599                                                intel_primary_formats, num_formats,
13600                                                DRM_PLANE_TYPE_PRIMARY,
13601                                                "plane 1%c", pipe_name(pipe));
13602         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13603                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13604                                                0, &intel_plane_funcs,
13605                                                intel_primary_formats, num_formats,
13606                                                DRM_PLANE_TYPE_PRIMARY,
13607                                                "primary %c", pipe_name(pipe));
13608         else
13609                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13610                                                0, &intel_plane_funcs,
13611                                                intel_primary_formats, num_formats,
13612                                                DRM_PLANE_TYPE_PRIMARY,
13613                                                "plane %c", plane_name(primary->plane));
13614         if (ret)
13615                 goto fail;
13616
13617         if (INTEL_GEN(dev_priv) >= 9) {
13618                 supported_rotations =
13619                         DRM_ROTATE_0 | DRM_ROTATE_90 |
13620                         DRM_ROTATE_180 | DRM_ROTATE_270;
13621         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13622                 supported_rotations =
13623                         DRM_ROTATE_0 | DRM_ROTATE_180 |
13624                         DRM_REFLECT_X;
13625         } else if (INTEL_GEN(dev_priv) >= 4) {
13626                 supported_rotations =
13627                         DRM_ROTATE_0 | DRM_ROTATE_180;
13628         } else {
13629                 supported_rotations = DRM_ROTATE_0;
13630         }
13631
13632         if (INTEL_GEN(dev_priv) >= 4)
13633                 drm_plane_create_rotation_property(&primary->base,
13634                                                    DRM_ROTATE_0,
13635                                                    supported_rotations);
13636
13637         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13638
13639         return primary;
13640
13641 fail:
13642         kfree(state);
13643         kfree(primary);
13644
13645         return ERR_PTR(ret);
13646 }
13647
13648 static int
13649 intel_check_cursor_plane(struct drm_plane *plane,
13650                          struct intel_crtc_state *crtc_state,
13651                          struct intel_plane_state *state)
13652 {
13653         struct drm_framebuffer *fb = state->base.fb;
13654         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13655         enum pipe pipe = to_intel_plane(plane)->pipe;
13656         unsigned stride;
13657         int ret;
13658
13659         ret = drm_plane_helper_check_state(&state->base,
13660                                            &state->clip,
13661                                            DRM_PLANE_HELPER_NO_SCALING,
13662                                            DRM_PLANE_HELPER_NO_SCALING,
13663                                            true, true);
13664         if (ret)
13665                 return ret;
13666
13667         /* if we want to turn off the cursor ignore width and height */
13668         if (!obj)
13669                 return 0;
13670
13671         /* Check for which cursor types we support */
13672         if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
13673                             state->base.crtc_h)) {
13674                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13675                           state->base.crtc_w, state->base.crtc_h);
13676                 return -EINVAL;
13677         }
13678
13679         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13680         if (obj->base.size < stride * state->base.crtc_h) {
13681                 DRM_DEBUG_KMS("buffer is too small\n");
13682                 return -ENOMEM;
13683         }
13684
13685         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
13686                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13687                 return -EINVAL;
13688         }
13689
13690         /*
13691          * There's something wrong with the cursor on CHV pipe C.
13692          * If it straddles the left edge of the screen then
13693          * moving it away from the edge or disabling it often
13694          * results in a pipe underrun, and often that can lead to
13695          * dead pipe (constant underrun reported, and it scans
13696          * out just a solid color). To recover from that, the
13697          * display power well must be turned off and on again.
13698          * Refuse the put the cursor into that compromised position.
13699          */
13700         if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
13701             state->base.visible && state->base.crtc_x < 0) {
13702                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13703                 return -EINVAL;
13704         }
13705
13706         return 0;
13707 }
13708
13709 static void
13710 intel_disable_cursor_plane(struct drm_plane *plane,
13711                            struct drm_crtc *crtc)
13712 {
13713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13714
13715         intel_crtc->cursor_addr = 0;
13716         intel_crtc_update_cursor(crtc, NULL);
13717 }
13718
13719 static void
13720 intel_update_cursor_plane(struct drm_plane *plane,
13721                           const struct intel_crtc_state *crtc_state,
13722                           const struct intel_plane_state *state)
13723 {
13724         struct drm_crtc *crtc = crtc_state->base.crtc;
13725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13726         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13727         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13728         uint32_t addr;
13729
13730         if (!obj)
13731                 addr = 0;
13732         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13733                 addr = intel_plane_ggtt_offset(state);
13734         else
13735                 addr = obj->phys_handle->busaddr;
13736
13737         intel_crtc->cursor_addr = addr;
13738         intel_crtc_update_cursor(crtc, state);
13739 }
13740
13741 static struct intel_plane *
13742 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13743 {
13744         struct intel_plane *cursor = NULL;
13745         struct intel_plane_state *state = NULL;
13746         int ret;
13747
13748         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13749         if (!cursor) {
13750                 ret = -ENOMEM;
13751                 goto fail;
13752         }
13753
13754         state = intel_create_plane_state(&cursor->base);
13755         if (!state) {
13756                 ret = -ENOMEM;
13757                 goto fail;
13758         }
13759
13760         cursor->base.state = &state->base;
13761
13762         cursor->can_scale = false;
13763         cursor->max_downscale = 1;
13764         cursor->pipe = pipe;
13765         cursor->plane = pipe;
13766         cursor->id = PLANE_CURSOR;
13767         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13768         cursor->check_plane = intel_check_cursor_plane;
13769         cursor->update_plane = intel_update_cursor_plane;
13770         cursor->disable_plane = intel_disable_cursor_plane;
13771
13772         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13773                                        0, &intel_cursor_plane_funcs,
13774                                        intel_cursor_formats,
13775                                        ARRAY_SIZE(intel_cursor_formats),
13776                                        DRM_PLANE_TYPE_CURSOR,
13777                                        "cursor %c", pipe_name(pipe));
13778         if (ret)
13779                 goto fail;
13780
13781         if (INTEL_GEN(dev_priv) >= 4)
13782                 drm_plane_create_rotation_property(&cursor->base,
13783                                                    DRM_ROTATE_0,
13784                                                    DRM_ROTATE_0 |
13785                                                    DRM_ROTATE_180);
13786
13787         if (INTEL_GEN(dev_priv) >= 9)
13788                 state->scaler_id = -1;
13789
13790         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13791
13792         return cursor;
13793
13794 fail:
13795         kfree(state);
13796         kfree(cursor);
13797
13798         return ERR_PTR(ret);
13799 }
13800
13801 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13802                                     struct intel_crtc_state *crtc_state)
13803 {
13804         struct intel_crtc_scaler_state *scaler_state =
13805                 &crtc_state->scaler_state;
13806         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13807         int i;
13808
13809         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13810         if (!crtc->num_scalers)
13811                 return;
13812
13813         for (i = 0; i < crtc->num_scalers; i++) {
13814                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13815
13816                 scaler->in_use = 0;
13817                 scaler->mode = PS_SCALER_MODE_DYN;
13818         }
13819
13820         scaler_state->scaler_id = -1;
13821 }
13822
13823 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13824 {
13825         struct intel_crtc *intel_crtc;
13826         struct intel_crtc_state *crtc_state = NULL;
13827         struct intel_plane *primary = NULL;
13828         struct intel_plane *cursor = NULL;
13829         int sprite, ret;
13830
13831         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13832         if (!intel_crtc)
13833                 return -ENOMEM;
13834
13835         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13836         if (!crtc_state) {
13837                 ret = -ENOMEM;
13838                 goto fail;
13839         }
13840         intel_crtc->config = crtc_state;
13841         intel_crtc->base.state = &crtc_state->base;
13842         crtc_state->base.crtc = &intel_crtc->base;
13843
13844         primary = intel_primary_plane_create(dev_priv, pipe);
13845         if (IS_ERR(primary)) {
13846                 ret = PTR_ERR(primary);
13847                 goto fail;
13848         }
13849         intel_crtc->plane_ids_mask |= BIT(primary->id);
13850
13851         for_each_sprite(dev_priv, pipe, sprite) {
13852                 struct intel_plane *plane;
13853
13854                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13855                 if (IS_ERR(plane)) {
13856                         ret = PTR_ERR(plane);
13857                         goto fail;
13858                 }
13859                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13860         }
13861
13862         cursor = intel_cursor_plane_create(dev_priv, pipe);
13863         if (IS_ERR(cursor)) {
13864                 ret = PTR_ERR(cursor);
13865                 goto fail;
13866         }
13867         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13868
13869         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13870                                         &primary->base, &cursor->base,
13871                                         &intel_crtc_funcs,
13872                                         "pipe %c", pipe_name(pipe));
13873         if (ret)
13874                 goto fail;
13875
13876         intel_crtc->pipe = pipe;
13877         intel_crtc->plane = primary->plane;
13878
13879         intel_crtc->cursor_base = ~0;
13880         intel_crtc->cursor_cntl = ~0;
13881         intel_crtc->cursor_size = ~0;
13882
13883         /* initialize shared scalers */
13884         intel_crtc_init_scalers(intel_crtc, crtc_state);
13885
13886         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13887                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13888         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13889         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13890
13891         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13892
13893         intel_color_init(&intel_crtc->base);
13894
13895         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13896
13897         return 0;
13898
13899 fail:
13900         /*
13901          * drm_mode_config_cleanup() will free up any
13902          * crtcs/planes already initialized.
13903          */
13904         kfree(crtc_state);
13905         kfree(intel_crtc);
13906
13907         return ret;
13908 }
13909
13910 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13911 {
13912         struct drm_encoder *encoder = connector->base.encoder;
13913         struct drm_device *dev = connector->base.dev;
13914
13915         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13916
13917         if (!encoder || WARN_ON(!encoder->crtc))
13918                 return INVALID_PIPE;
13919
13920         return to_intel_crtc(encoder->crtc)->pipe;
13921 }
13922
13923 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13924                                 struct drm_file *file)
13925 {
13926         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13927         struct drm_crtc *drmmode_crtc;
13928         struct intel_crtc *crtc;
13929
13930         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13931         if (!drmmode_crtc)
13932                 return -ENOENT;
13933
13934         crtc = to_intel_crtc(drmmode_crtc);
13935         pipe_from_crtc_id->pipe = crtc->pipe;
13936
13937         return 0;
13938 }
13939
13940 static int intel_encoder_clones(struct intel_encoder *encoder)
13941 {
13942         struct drm_device *dev = encoder->base.dev;
13943         struct intel_encoder *source_encoder;
13944         int index_mask = 0;
13945         int entry = 0;
13946
13947         for_each_intel_encoder(dev, source_encoder) {
13948                 if (encoders_cloneable(encoder, source_encoder))
13949                         index_mask |= (1 << entry);
13950
13951                 entry++;
13952         }
13953
13954         return index_mask;
13955 }
13956
13957 static bool has_edp_a(struct drm_i915_private *dev_priv)
13958 {
13959         if (!IS_MOBILE(dev_priv))
13960                 return false;
13961
13962         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13963                 return false;
13964
13965         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13966                 return false;
13967
13968         return true;
13969 }
13970
13971 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13972 {
13973         if (INTEL_GEN(dev_priv) >= 9)
13974                 return false;
13975
13976         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13977                 return false;
13978
13979         if (IS_CHERRYVIEW(dev_priv))
13980                 return false;
13981
13982         if (HAS_PCH_LPT_H(dev_priv) &&
13983             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13984                 return false;
13985
13986         /* DDI E can't be used if DDI A requires 4 lanes */
13987         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13988                 return false;
13989
13990         if (!dev_priv->vbt.int_crt_support)
13991                 return false;
13992
13993         return true;
13994 }
13995
13996 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13997 {
13998         int pps_num;
13999         int pps_idx;
14000
14001         if (HAS_DDI(dev_priv))
14002                 return;
14003         /*
14004          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14005          * everywhere where registers can be write protected.
14006          */
14007         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14008                 pps_num = 2;
14009         else
14010                 pps_num = 1;
14011
14012         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14013                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14014
14015                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14016                 I915_WRITE(PP_CONTROL(pps_idx), val);
14017         }
14018 }
14019
14020 static void intel_pps_init(struct drm_i915_private *dev_priv)
14021 {
14022         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14023                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14024         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14025                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14026         else
14027                 dev_priv->pps_mmio_base = PPS_BASE;
14028
14029         intel_pps_unlock_regs_wa(dev_priv);
14030 }
14031
14032 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14033 {
14034         struct intel_encoder *encoder;
14035         bool dpd_is_edp = false;
14036
14037         intel_pps_init(dev_priv);
14038
14039         /*
14040          * intel_edp_init_connector() depends on this completing first, to
14041          * prevent the registeration of both eDP and LVDS and the incorrect
14042          * sharing of the PPS.
14043          */
14044         intel_lvds_init(dev_priv);
14045
14046         if (intel_crt_present(dev_priv))
14047                 intel_crt_init(dev_priv);
14048
14049         if (IS_GEN9_LP(dev_priv)) {
14050                 /*
14051                  * FIXME: Broxton doesn't support port detection via the
14052                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14053                  * detect the ports.
14054                  */
14055                 intel_ddi_init(dev_priv, PORT_A);
14056                 intel_ddi_init(dev_priv, PORT_B);
14057                 intel_ddi_init(dev_priv, PORT_C);
14058
14059                 intel_dsi_init(dev_priv);
14060         } else if (HAS_DDI(dev_priv)) {
14061                 int found;
14062
14063                 /*
14064                  * Haswell uses DDI functions to detect digital outputs.
14065                  * On SKL pre-D0 the strap isn't connected, so we assume
14066                  * it's there.
14067                  */
14068                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14069                 /* WaIgnoreDDIAStrap: skl */
14070                 if (found || IS_GEN9_BC(dev_priv))
14071                         intel_ddi_init(dev_priv, PORT_A);
14072
14073                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14074                  * register */
14075                 found = I915_READ(SFUSE_STRAP);
14076
14077                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14078                         intel_ddi_init(dev_priv, PORT_B);
14079                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14080                         intel_ddi_init(dev_priv, PORT_C);
14081                 if (found & SFUSE_STRAP_DDID_DETECTED)
14082                         intel_ddi_init(dev_priv, PORT_D);
14083                 /*
14084                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14085                  */
14086                 if (IS_GEN9_BC(dev_priv) &&
14087                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14088                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14089                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14090                         intel_ddi_init(dev_priv, PORT_E);
14091
14092         } else if (HAS_PCH_SPLIT(dev_priv)) {
14093                 int found;
14094                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14095
14096                 if (has_edp_a(dev_priv))
14097                         intel_dp_init(dev_priv, DP_A, PORT_A);
14098
14099                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14100                         /* PCH SDVOB multiplex with HDMIB */
14101                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14102                         if (!found)
14103                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14104                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14105                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14106                 }
14107
14108                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14109                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14110
14111                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14112                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14113
14114                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14115                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14116
14117                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14118                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14119         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14120                 bool has_edp, has_port;
14121
14122                 /*
14123                  * The DP_DETECTED bit is the latched state of the DDC
14124                  * SDA pin at boot. However since eDP doesn't require DDC
14125                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14126                  * eDP ports may have been muxed to an alternate function.
14127                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14128                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14129                  * detect eDP ports.
14130                  *
14131                  * Sadly the straps seem to be missing sometimes even for HDMI
14132                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14133                  * and VBT for the presence of the port. Additionally we can't
14134                  * trust the port type the VBT declares as we've seen at least
14135                  * HDMI ports that the VBT claim are DP or eDP.
14136                  */
14137                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14138                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14139                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14140                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14141                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14142                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14143
14144                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14145                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14146                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14147                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14148                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14149                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14150
14151                 if (IS_CHERRYVIEW(dev_priv)) {
14152                         /*
14153                          * eDP not supported on port D,
14154                          * so no need to worry about it
14155                          */
14156                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14157                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14158                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14159                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14160                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14161                 }
14162
14163                 intel_dsi_init(dev_priv);
14164         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14165                 bool found = false;
14166
14167                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14168                         DRM_DEBUG_KMS("probing SDVOB\n");
14169                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14170                         if (!found && IS_G4X(dev_priv)) {
14171                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14172                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14173                         }
14174
14175                         if (!found && IS_G4X(dev_priv))
14176                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14177                 }
14178
14179                 /* Before G4X SDVOC doesn't have its own detect register */
14180
14181                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14182                         DRM_DEBUG_KMS("probing SDVOC\n");
14183                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14184                 }
14185
14186                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14187
14188                         if (IS_G4X(dev_priv)) {
14189                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14190                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14191                         }
14192                         if (IS_G4X(dev_priv))
14193                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14194                 }
14195
14196                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14197                         intel_dp_init(dev_priv, DP_D, PORT_D);
14198         } else if (IS_GEN2(dev_priv))
14199                 intel_dvo_init(dev_priv);
14200
14201         if (SUPPORTS_TV(dev_priv))
14202                 intel_tv_init(dev_priv);
14203
14204         intel_psr_init(dev_priv);
14205
14206         for_each_intel_encoder(&dev_priv->drm, encoder) {
14207                 encoder->base.possible_crtcs = encoder->crtc_mask;
14208                 encoder->base.possible_clones =
14209                         intel_encoder_clones(encoder);
14210         }
14211
14212         intel_init_pch_refclk(dev_priv);
14213
14214         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14215 }
14216
14217 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14218 {
14219         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14220
14221         drm_framebuffer_cleanup(fb);
14222
14223         i915_gem_object_lock(intel_fb->obj);
14224         WARN_ON(!intel_fb->obj->framebuffer_references--);
14225         i915_gem_object_unlock(intel_fb->obj);
14226
14227         i915_gem_object_put(intel_fb->obj);
14228
14229         kfree(intel_fb);
14230 }
14231
14232 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14233                                                 struct drm_file *file,
14234                                                 unsigned int *handle)
14235 {
14236         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14237         struct drm_i915_gem_object *obj = intel_fb->obj;
14238
14239         if (obj->userptr.mm) {
14240                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14241                 return -EINVAL;
14242         }
14243
14244         return drm_gem_handle_create(file, &obj->base, handle);
14245 }
14246
14247 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14248                                         struct drm_file *file,
14249                                         unsigned flags, unsigned color,
14250                                         struct drm_clip_rect *clips,
14251                                         unsigned num_clips)
14252 {
14253         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14254
14255         i915_gem_object_flush_if_display(obj);
14256         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14257
14258         return 0;
14259 }
14260
14261 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14262         .destroy = intel_user_framebuffer_destroy,
14263         .create_handle = intel_user_framebuffer_create_handle,
14264         .dirty = intel_user_framebuffer_dirty,
14265 };
14266
14267 static
14268 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14269                          uint64_t fb_modifier, uint32_t pixel_format)
14270 {
14271         u32 gen = INTEL_GEN(dev_priv);
14272
14273         if (gen >= 9) {
14274                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14275
14276                 /* "The stride in bytes must not exceed the of the size of 8K
14277                  *  pixels and 32K bytes."
14278                  */
14279                 return min(8192 * cpp, 32768);
14280         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14281                 return 32*1024;
14282         } else if (gen >= 4) {
14283                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14284                         return 16*1024;
14285                 else
14286                         return 32*1024;
14287         } else if (gen >= 3) {
14288                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14289                         return 8*1024;
14290                 else
14291                         return 16*1024;
14292         } else {
14293                 /* XXX DSPC is limited to 4k tiled */
14294                 return 8*1024;
14295         }
14296 }
14297
14298 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14299                                   struct drm_i915_gem_object *obj,
14300                                   struct drm_mode_fb_cmd2 *mode_cmd)
14301 {
14302         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14303         struct drm_format_name_buf format_name;
14304         u32 pitch_limit, stride_alignment;
14305         unsigned int tiling, stride;
14306         int ret = -EINVAL;
14307
14308         i915_gem_object_lock(obj);
14309         obj->framebuffer_references++;
14310         tiling = i915_gem_object_get_tiling(obj);
14311         stride = i915_gem_object_get_stride(obj);
14312         i915_gem_object_unlock(obj);
14313
14314         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14315                 /*
14316                  * If there's a fence, enforce that
14317                  * the fb modifier and tiling mode match.
14318                  */
14319                 if (tiling != I915_TILING_NONE &&
14320                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14321                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14322                         goto err;
14323                 }
14324         } else {
14325                 if (tiling == I915_TILING_X) {
14326                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14327                 } else if (tiling == I915_TILING_Y) {
14328                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14329                         goto err;
14330                 }
14331         }
14332
14333         /* Passed in modifier sanity checking. */
14334         switch (mode_cmd->modifier[0]) {
14335         case I915_FORMAT_MOD_Y_TILED:
14336         case I915_FORMAT_MOD_Yf_TILED:
14337                 if (INTEL_GEN(dev_priv) < 9) {
14338                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14339                                   mode_cmd->modifier[0]);
14340                         goto err;
14341                 }
14342         case DRM_FORMAT_MOD_NONE:
14343         case I915_FORMAT_MOD_X_TILED:
14344                 break;
14345         default:
14346                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14347                           mode_cmd->modifier[0]);
14348                 goto err;
14349         }
14350
14351         /*
14352          * gen2/3 display engine uses the fence if present,
14353          * so the tiling mode must match the fb modifier exactly.
14354          */
14355         if (INTEL_INFO(dev_priv)->gen < 4 &&
14356             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14357                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
14358                 goto err;
14359         }
14360
14361         stride_alignment = intel_fb_stride_alignment(dev_priv,
14362                                                      mode_cmd->modifier[0],
14363                                                      mode_cmd->pixel_format);
14364         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14365                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14366                           mode_cmd->pitches[0], stride_alignment);
14367                 goto err;
14368         }
14369
14370         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14371                                            mode_cmd->pixel_format);
14372         if (mode_cmd->pitches[0] > pitch_limit) {
14373                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14374                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14375                           "tiled" : "linear",
14376                           mode_cmd->pitches[0], pitch_limit);
14377                 goto err;
14378         }
14379
14380         /*
14381          * If there's a fence, enforce that
14382          * the fb pitch and fence stride match.
14383          */
14384         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] !=  stride) {
14385                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14386                           mode_cmd->pitches[0], stride);
14387                 goto err;
14388         }
14389
14390         /* Reject formats not supported by any plane early. */
14391         switch (mode_cmd->pixel_format) {
14392         case DRM_FORMAT_C8:
14393         case DRM_FORMAT_RGB565:
14394         case DRM_FORMAT_XRGB8888:
14395         case DRM_FORMAT_ARGB8888:
14396                 break;
14397         case DRM_FORMAT_XRGB1555:
14398                 if (INTEL_GEN(dev_priv) > 3) {
14399                         DRM_DEBUG("unsupported pixel format: %s\n",
14400                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
14401                         goto err;
14402                 }
14403                 break;
14404         case DRM_FORMAT_ABGR8888:
14405                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14406                     INTEL_GEN(dev_priv) < 9) {
14407                         DRM_DEBUG("unsupported pixel format: %s\n",
14408                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
14409                         goto err;
14410                 }
14411                 break;
14412         case DRM_FORMAT_XBGR8888:
14413         case DRM_FORMAT_XRGB2101010:
14414         case DRM_FORMAT_XBGR2101010:
14415                 if (INTEL_GEN(dev_priv) < 4) {
14416                         DRM_DEBUG("unsupported pixel format: %s\n",
14417                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
14418                         goto err;
14419                 }
14420                 break;
14421         case DRM_FORMAT_ABGR2101010:
14422                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14423                         DRM_DEBUG("unsupported pixel format: %s\n",
14424                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
14425                         goto err;
14426                 }
14427                 break;
14428         case DRM_FORMAT_YUYV:
14429         case DRM_FORMAT_UYVY:
14430         case DRM_FORMAT_YVYU:
14431         case DRM_FORMAT_VYUY:
14432                 if (INTEL_GEN(dev_priv) < 5) {
14433                         DRM_DEBUG("unsupported pixel format: %s\n",
14434                                   drm_get_format_name(mode_cmd->pixel_format, &format_name));
14435                         goto err;
14436                 }
14437                 break;
14438         default:
14439                 DRM_DEBUG("unsupported pixel format: %s\n",
14440                           drm_get_format_name(mode_cmd->pixel_format, &format_name));
14441                 goto err;
14442         }
14443
14444         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14445         if (mode_cmd->offsets[0] != 0)
14446                 goto err;
14447
14448         drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14449                                        &intel_fb->base, mode_cmd);
14450         intel_fb->obj = obj;
14451
14452         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14453         if (ret)
14454                 goto err;
14455
14456         ret = drm_framebuffer_init(obj->base.dev,
14457                                    &intel_fb->base,
14458                                    &intel_fb_funcs);
14459         if (ret) {
14460                 DRM_ERROR("framebuffer init failed %d\n", ret);
14461                 goto err;
14462         }
14463
14464         return 0;
14465
14466 err:
14467         i915_gem_object_lock(obj);
14468         obj->framebuffer_references--;
14469         i915_gem_object_unlock(obj);
14470         return ret;
14471 }
14472
14473 static struct drm_framebuffer *
14474 intel_user_framebuffer_create(struct drm_device *dev,
14475                               struct drm_file *filp,
14476                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14477 {
14478         struct drm_framebuffer *fb;
14479         struct drm_i915_gem_object *obj;
14480         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14481
14482         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14483         if (!obj)
14484                 return ERR_PTR(-ENOENT);
14485
14486         fb = intel_framebuffer_create(obj, &mode_cmd);
14487         if (IS_ERR(fb))
14488                 i915_gem_object_put(obj);
14489
14490         return fb;
14491 }
14492
14493 static void intel_atomic_state_free(struct drm_atomic_state *state)
14494 {
14495         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14496
14497         drm_atomic_state_default_release(state);
14498
14499         i915_sw_fence_fini(&intel_state->commit_ready);
14500
14501         kfree(state);
14502 }
14503
14504 static const struct drm_mode_config_funcs intel_mode_funcs = {
14505         .fb_create = intel_user_framebuffer_create,
14506         .output_poll_changed = intel_fbdev_output_poll_changed,
14507         .atomic_check = intel_atomic_check,
14508         .atomic_commit = intel_atomic_commit,
14509         .atomic_state_alloc = intel_atomic_state_alloc,
14510         .atomic_state_clear = intel_atomic_state_clear,
14511         .atomic_state_free = intel_atomic_state_free,
14512 };
14513
14514 /**
14515  * intel_init_display_hooks - initialize the display modesetting hooks
14516  * @dev_priv: device private
14517  */
14518 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14519 {
14520         intel_init_cdclk_hooks(dev_priv);
14521
14522         if (INTEL_INFO(dev_priv)->gen >= 9) {
14523                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14524                 dev_priv->display.get_initial_plane_config =
14525                         skylake_get_initial_plane_config;
14526                 dev_priv->display.crtc_compute_clock =
14527                         haswell_crtc_compute_clock;
14528                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14529                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14530         } else if (HAS_DDI(dev_priv)) {
14531                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14532                 dev_priv->display.get_initial_plane_config =
14533                         ironlake_get_initial_plane_config;
14534                 dev_priv->display.crtc_compute_clock =
14535                         haswell_crtc_compute_clock;
14536                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14537                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14538         } else if (HAS_PCH_SPLIT(dev_priv)) {
14539                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14540                 dev_priv->display.get_initial_plane_config =
14541                         ironlake_get_initial_plane_config;
14542                 dev_priv->display.crtc_compute_clock =
14543                         ironlake_crtc_compute_clock;
14544                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14545                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14546         } else if (IS_CHERRYVIEW(dev_priv)) {
14547                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14548                 dev_priv->display.get_initial_plane_config =
14549                         i9xx_get_initial_plane_config;
14550                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14551                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14552                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14553         } else if (IS_VALLEYVIEW(dev_priv)) {
14554                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14555                 dev_priv->display.get_initial_plane_config =
14556                         i9xx_get_initial_plane_config;
14557                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14558                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14559                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14560         } else if (IS_G4X(dev_priv)) {
14561                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14562                 dev_priv->display.get_initial_plane_config =
14563                         i9xx_get_initial_plane_config;
14564                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14565                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14566                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14567         } else if (IS_PINEVIEW(dev_priv)) {
14568                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14569                 dev_priv->display.get_initial_plane_config =
14570                         i9xx_get_initial_plane_config;
14571                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14572                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14573                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14574         } else if (!IS_GEN2(dev_priv)) {
14575                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14576                 dev_priv->display.get_initial_plane_config =
14577                         i9xx_get_initial_plane_config;
14578                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14579                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14580                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14581         } else {
14582                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14583                 dev_priv->display.get_initial_plane_config =
14584                         i9xx_get_initial_plane_config;
14585                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14586                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14587                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14588         }
14589
14590         if (IS_GEN5(dev_priv)) {
14591                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14592         } else if (IS_GEN6(dev_priv)) {
14593                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14594         } else if (IS_IVYBRIDGE(dev_priv)) {
14595                 /* FIXME: detect B0+ stepping and use auto training */
14596                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14597         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14598                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14599         }
14600
14601         if (dev_priv->info.gen >= 9)
14602                 dev_priv->display.update_crtcs = skl_update_crtcs;
14603         else
14604                 dev_priv->display.update_crtcs = intel_update_crtcs;
14605
14606         switch (INTEL_INFO(dev_priv)->gen) {
14607         case 2:
14608                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14609                 break;
14610
14611         case 3:
14612                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14613                 break;
14614
14615         case 4:
14616         case 5:
14617                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14618                 break;
14619
14620         case 6:
14621                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14622                 break;
14623         case 7:
14624         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14625                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14626                 break;
14627         case 9:
14628                 /* Drop through - unsupported since execlist only. */
14629         default:
14630                 /* Default just returns -ENODEV to indicate unsupported */
14631                 dev_priv->display.queue_flip = intel_default_queue_flip;
14632         }
14633 }
14634
14635 /*
14636  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14637  * resume, or other times.  This quirk makes sure that's the case for
14638  * affected systems.
14639  */
14640 static void quirk_pipea_force(struct drm_device *dev)
14641 {
14642         struct drm_i915_private *dev_priv = to_i915(dev);
14643
14644         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14645         DRM_INFO("applying pipe a force quirk\n");
14646 }
14647
14648 static void quirk_pipeb_force(struct drm_device *dev)
14649 {
14650         struct drm_i915_private *dev_priv = to_i915(dev);
14651
14652         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14653         DRM_INFO("applying pipe b force quirk\n");
14654 }
14655
14656 /*
14657  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14658  */
14659 static void quirk_ssc_force_disable(struct drm_device *dev)
14660 {
14661         struct drm_i915_private *dev_priv = to_i915(dev);
14662         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14663         DRM_INFO("applying lvds SSC disable quirk\n");
14664 }
14665
14666 /*
14667  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14668  * brightness value
14669  */
14670 static void quirk_invert_brightness(struct drm_device *dev)
14671 {
14672         struct drm_i915_private *dev_priv = to_i915(dev);
14673         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14674         DRM_INFO("applying inverted panel brightness quirk\n");
14675 }
14676
14677 /* Some VBT's incorrectly indicate no backlight is present */
14678 static void quirk_backlight_present(struct drm_device *dev)
14679 {
14680         struct drm_i915_private *dev_priv = to_i915(dev);
14681         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14682         DRM_INFO("applying backlight present quirk\n");
14683 }
14684
14685 struct intel_quirk {
14686         int device;
14687         int subsystem_vendor;
14688         int subsystem_device;
14689         void (*hook)(struct drm_device *dev);
14690 };
14691
14692 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14693 struct intel_dmi_quirk {
14694         void (*hook)(struct drm_device *dev);
14695         const struct dmi_system_id (*dmi_id_list)[];
14696 };
14697
14698 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14699 {
14700         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14701         return 1;
14702 }
14703
14704 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14705         {
14706                 .dmi_id_list = &(const struct dmi_system_id[]) {
14707                         {
14708                                 .callback = intel_dmi_reverse_brightness,
14709                                 .ident = "NCR Corporation",
14710                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14711                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14712                                 },
14713                         },
14714                         { }  /* terminating entry */
14715                 },
14716                 .hook = quirk_invert_brightness,
14717         },
14718 };
14719
14720 static struct intel_quirk intel_quirks[] = {
14721         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14722         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14723
14724         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14725         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14726
14727         /* 830 needs to leave pipe A & dpll A up */
14728         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14729
14730         /* 830 needs to leave pipe B & dpll B up */
14731         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14732
14733         /* Lenovo U160 cannot use SSC on LVDS */
14734         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14735
14736         /* Sony Vaio Y cannot use SSC on LVDS */
14737         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14738
14739         /* Acer Aspire 5734Z must invert backlight brightness */
14740         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14741
14742         /* Acer/eMachines G725 */
14743         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14744
14745         /* Acer/eMachines e725 */
14746         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14747
14748         /* Acer/Packard Bell NCL20 */
14749         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14750
14751         /* Acer Aspire 4736Z */
14752         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14753
14754         /* Acer Aspire 5336 */
14755         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14756
14757         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14758         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14759
14760         /* Acer C720 Chromebook (Core i3 4005U) */
14761         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14762
14763         /* Apple Macbook 2,1 (Core 2 T7400) */
14764         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14765
14766         /* Apple Macbook 4,1 */
14767         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14768
14769         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14770         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14771
14772         /* HP Chromebook 14 (Celeron 2955U) */
14773         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14774
14775         /* Dell Chromebook 11 */
14776         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14777
14778         /* Dell Chromebook 11 (2015 version) */
14779         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14780 };
14781
14782 static void intel_init_quirks(struct drm_device *dev)
14783 {
14784         struct pci_dev *d = dev->pdev;
14785         int i;
14786
14787         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14788                 struct intel_quirk *q = &intel_quirks[i];
14789
14790                 if (d->device == q->device &&
14791                     (d->subsystem_vendor == q->subsystem_vendor ||
14792                      q->subsystem_vendor == PCI_ANY_ID) &&
14793                     (d->subsystem_device == q->subsystem_device ||
14794                      q->subsystem_device == PCI_ANY_ID))
14795                         q->hook(dev);
14796         }
14797         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14798                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14799                         intel_dmi_quirks[i].hook(dev);
14800         }
14801 }
14802
14803 /* Disable the VGA plane that we never use */
14804 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14805 {
14806         struct pci_dev *pdev = dev_priv->drm.pdev;
14807         u8 sr1;
14808         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14809
14810         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14811         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14812         outb(SR01, VGA_SR_INDEX);
14813         sr1 = inb(VGA_SR_DATA);
14814         outb(sr1 | 1<<5, VGA_SR_DATA);
14815         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14816         udelay(300);
14817
14818         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14819         POSTING_READ(vga_reg);
14820 }
14821
14822 void intel_modeset_init_hw(struct drm_device *dev)
14823 {
14824         struct drm_i915_private *dev_priv = to_i915(dev);
14825
14826         intel_update_cdclk(dev_priv);
14827         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14828
14829         intel_init_clock_gating(dev_priv);
14830 }
14831
14832 /*
14833  * Calculate what we think the watermarks should be for the state we've read
14834  * out of the hardware and then immediately program those watermarks so that
14835  * we ensure the hardware settings match our internal state.
14836  *
14837  * We can calculate what we think WM's should be by creating a duplicate of the
14838  * current state (which was constructed during hardware readout) and running it
14839  * through the atomic check code to calculate new watermark values in the
14840  * state object.
14841  */
14842 static void sanitize_watermarks(struct drm_device *dev)
14843 {
14844         struct drm_i915_private *dev_priv = to_i915(dev);
14845         struct drm_atomic_state *state;
14846         struct intel_atomic_state *intel_state;
14847         struct drm_crtc *crtc;
14848         struct drm_crtc_state *cstate;
14849         struct drm_modeset_acquire_ctx ctx;
14850         int ret;
14851         int i;
14852
14853         /* Only supported on platforms that use atomic watermark design */
14854         if (!dev_priv->display.optimize_watermarks)
14855                 return;
14856
14857         /*
14858          * We need to hold connection_mutex before calling duplicate_state so
14859          * that the connector loop is protected.
14860          */
14861         drm_modeset_acquire_init(&ctx, 0);
14862 retry:
14863         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14864         if (ret == -EDEADLK) {
14865                 drm_modeset_backoff(&ctx);
14866                 goto retry;
14867         } else if (WARN_ON(ret)) {
14868                 goto fail;
14869         }
14870
14871         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14872         if (WARN_ON(IS_ERR(state)))
14873                 goto fail;
14874
14875         intel_state = to_intel_atomic_state(state);
14876
14877         /*
14878          * Hardware readout is the only time we don't want to calculate
14879          * intermediate watermarks (since we don't trust the current
14880          * watermarks).
14881          */
14882         if (!HAS_GMCH_DISPLAY(dev_priv))
14883                 intel_state->skip_intermediate_wm = true;
14884
14885         ret = intel_atomic_check(dev, state);
14886         if (ret) {
14887                 /*
14888                  * If we fail here, it means that the hardware appears to be
14889                  * programmed in a way that shouldn't be possible, given our
14890                  * understanding of watermark requirements.  This might mean a
14891                  * mistake in the hardware readout code or a mistake in the
14892                  * watermark calculations for a given platform.  Raise a WARN
14893                  * so that this is noticeable.
14894                  *
14895                  * If this actually happens, we'll have to just leave the
14896                  * BIOS-programmed watermarks untouched and hope for the best.
14897                  */
14898                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14899                 goto put_state;
14900         }
14901
14902         /* Write calculated watermark values back */
14903         for_each_crtc_in_state(state, crtc, cstate, i) {
14904                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14905
14906                 cs->wm.need_postvbl_update = true;
14907                 dev_priv->display.optimize_watermarks(intel_state, cs);
14908         }
14909
14910 put_state:
14911         drm_atomic_state_put(state);
14912 fail:
14913         drm_modeset_drop_locks(&ctx);
14914         drm_modeset_acquire_fini(&ctx);
14915 }
14916
14917 int intel_modeset_init(struct drm_device *dev)
14918 {
14919         struct drm_i915_private *dev_priv = to_i915(dev);
14920         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14921         enum pipe pipe;
14922         struct intel_crtc *crtc;
14923
14924         drm_mode_config_init(dev);
14925
14926         dev->mode_config.min_width = 0;
14927         dev->mode_config.min_height = 0;
14928
14929         dev->mode_config.preferred_depth = 24;
14930         dev->mode_config.prefer_shadow = 1;
14931
14932         dev->mode_config.allow_fb_modifiers = true;
14933
14934         dev->mode_config.funcs = &intel_mode_funcs;
14935
14936         INIT_WORK(&dev_priv->atomic_helper.free_work,
14937                   intel_atomic_helper_free_state_worker);
14938
14939         intel_init_quirks(dev);
14940
14941         intel_init_pm(dev_priv);
14942
14943         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14944                 return 0;
14945
14946         /*
14947          * There may be no VBT; and if the BIOS enabled SSC we can
14948          * just keep using it to avoid unnecessary flicker.  Whereas if the
14949          * BIOS isn't using it, don't assume it will work even if the VBT
14950          * indicates as much.
14951          */
14952         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14953                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14954                                             DREF_SSC1_ENABLE);
14955
14956                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14957                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14958                                      bios_lvds_use_ssc ? "en" : "dis",
14959                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14960                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14961                 }
14962         }
14963
14964         if (IS_GEN2(dev_priv)) {
14965                 dev->mode_config.max_width = 2048;
14966                 dev->mode_config.max_height = 2048;
14967         } else if (IS_GEN3(dev_priv)) {
14968                 dev->mode_config.max_width = 4096;
14969                 dev->mode_config.max_height = 4096;
14970         } else {
14971                 dev->mode_config.max_width = 8192;
14972                 dev->mode_config.max_height = 8192;
14973         }
14974
14975         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14976                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14977                 dev->mode_config.cursor_height = 1023;
14978         } else if (IS_GEN2(dev_priv)) {
14979                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14980                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14981         } else {
14982                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14983                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14984         }
14985
14986         dev->mode_config.fb_base = ggtt->mappable_base;
14987
14988         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14989                       INTEL_INFO(dev_priv)->num_pipes,
14990                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14991
14992         for_each_pipe(dev_priv, pipe) {
14993                 int ret;
14994
14995                 ret = intel_crtc_init(dev_priv, pipe);
14996                 if (ret) {
14997                         drm_mode_config_cleanup(dev);
14998                         return ret;
14999                 }
15000         }
15001
15002         intel_shared_dpll_init(dev);
15003
15004         intel_update_czclk(dev_priv);
15005         intel_modeset_init_hw(dev);
15006
15007         if (dev_priv->max_cdclk_freq == 0)
15008                 intel_update_max_cdclk(dev_priv);
15009
15010         /* Just disable it once at startup */
15011         i915_disable_vga(dev_priv);
15012         intel_setup_outputs(dev_priv);
15013
15014         drm_modeset_lock_all(dev);
15015         intel_modeset_setup_hw_state(dev);
15016         drm_modeset_unlock_all(dev);
15017
15018         for_each_intel_crtc(dev, crtc) {
15019                 struct intel_initial_plane_config plane_config = {};
15020
15021                 if (!crtc->active)
15022                         continue;
15023
15024                 /*
15025                  * Note that reserving the BIOS fb up front prevents us
15026                  * from stuffing other stolen allocations like the ring
15027                  * on top.  This prevents some ugliness at boot time, and
15028                  * can even allow for smooth boot transitions if the BIOS
15029                  * fb is large enough for the active pipe configuration.
15030                  */
15031                 dev_priv->display.get_initial_plane_config(crtc,
15032                                                            &plane_config);
15033
15034                 /*
15035                  * If the fb is shared between multiple heads, we'll
15036                  * just get the first one.
15037                  */
15038                 intel_find_initial_plane_obj(crtc, &plane_config);
15039         }
15040
15041         /*
15042          * Make sure hardware watermarks really match the state we read out.
15043          * Note that we need to do this after reconstructing the BIOS fb's
15044          * since the watermark calculation done here will use pstate->fb.
15045          */
15046         if (!HAS_GMCH_DISPLAY(dev_priv))
15047                 sanitize_watermarks(dev);
15048
15049         return 0;
15050 }
15051
15052 static void intel_enable_pipe_a(struct drm_device *dev)
15053 {
15054         struct intel_connector *connector;
15055         struct drm_connector *crt = NULL;
15056         struct intel_load_detect_pipe load_detect_temp;
15057         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15058
15059         /* We can't just switch on the pipe A, we need to set things up with a
15060          * proper mode and output configuration. As a gross hack, enable pipe A
15061          * by enabling the load detect pipe once. */
15062         for_each_intel_connector(dev, connector) {
15063                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15064                         crt = &connector->base;
15065                         break;
15066                 }
15067         }
15068
15069         if (!crt)
15070                 return;
15071
15072         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15073                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15074 }
15075
15076 static bool
15077 intel_check_plane_mapping(struct intel_crtc *crtc)
15078 {
15079         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15080         u32 val;
15081
15082         if (INTEL_INFO(dev_priv)->num_pipes == 1)
15083                 return true;
15084
15085         val = I915_READ(DSPCNTR(!crtc->plane));
15086
15087         if ((val & DISPLAY_PLANE_ENABLE) &&
15088             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15089                 return false;
15090
15091         return true;
15092 }
15093
15094 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15095 {
15096         struct drm_device *dev = crtc->base.dev;
15097         struct intel_encoder *encoder;
15098
15099         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15100                 return true;
15101
15102         return false;
15103 }
15104
15105 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15106 {
15107         struct drm_device *dev = encoder->base.dev;
15108         struct intel_connector *connector;
15109
15110         for_each_connector_on_encoder(dev, &encoder->base, connector)
15111                 return connector;
15112
15113         return NULL;
15114 }
15115
15116 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15117                               enum transcoder pch_transcoder)
15118 {
15119         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15120                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15121 }
15122
15123 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15124 {
15125         struct drm_device *dev = crtc->base.dev;
15126         struct drm_i915_private *dev_priv = to_i915(dev);
15127         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15128
15129         /* Clear any frame start delays used for debugging left by the BIOS */
15130         if (!transcoder_is_dsi(cpu_transcoder)) {
15131                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15132
15133                 I915_WRITE(reg,
15134                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15135         }
15136
15137         /* restore vblank interrupts to correct state */
15138         drm_crtc_vblank_reset(&crtc->base);
15139         if (crtc->active) {
15140                 struct intel_plane *plane;
15141
15142                 drm_crtc_vblank_on(&crtc->base);
15143
15144                 /* Disable everything but the primary plane */
15145                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15146                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15147                                 continue;
15148
15149                         trace_intel_disable_plane(&plane->base, crtc);
15150                         plane->disable_plane(&plane->base, &crtc->base);
15151                 }
15152         }
15153
15154         /* We need to sanitize the plane -> pipe mapping first because this will
15155          * disable the crtc (and hence change the state) if it is wrong. Note
15156          * that gen4+ has a fixed plane -> pipe mapping.  */
15157         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15158                 bool plane;
15159
15160                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15161                               crtc->base.base.id, crtc->base.name);
15162
15163                 /* Pipe has the wrong plane attached and the plane is active.
15164                  * Temporarily change the plane mapping and disable everything
15165                  * ...  */
15166                 plane = crtc->plane;
15167                 crtc->base.primary->state->visible = true;
15168                 crtc->plane = !plane;
15169                 intel_crtc_disable_noatomic(&crtc->base);
15170                 crtc->plane = plane;
15171         }
15172
15173         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15174             crtc->pipe == PIPE_A && !crtc->active) {
15175                 /* BIOS forgot to enable pipe A, this mostly happens after
15176                  * resume. Force-enable the pipe to fix this, the update_dpms
15177                  * call below we restore the pipe to the right state, but leave
15178                  * the required bits on. */
15179                 intel_enable_pipe_a(dev);
15180         }
15181
15182         /* Adjust the state of the output pipe according to whether we
15183          * have active connectors/encoders. */
15184         if (crtc->active && !intel_crtc_has_encoders(crtc))
15185                 intel_crtc_disable_noatomic(&crtc->base);
15186
15187         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15188                 /*
15189                  * We start out with underrun reporting disabled to avoid races.
15190                  * For correct bookkeeping mark this on active crtcs.
15191                  *
15192                  * Also on gmch platforms we dont have any hardware bits to
15193                  * disable the underrun reporting. Which means we need to start
15194                  * out with underrun reporting disabled also on inactive pipes,
15195                  * since otherwise we'll complain about the garbage we read when
15196                  * e.g. coming up after runtime pm.
15197                  *
15198                  * No protection against concurrent access is required - at
15199                  * worst a fifo underrun happens which also sets this to false.
15200                  */
15201                 crtc->cpu_fifo_underrun_disabled = true;
15202                 /*
15203                  * We track the PCH trancoder underrun reporting state
15204                  * within the crtc. With crtc for pipe A housing the underrun
15205                  * reporting state for PCH transcoder A, crtc for pipe B housing
15206                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15207                  * and marking underrun reporting as disabled for the non-existing
15208                  * PCH transcoders B and C would prevent enabling the south
15209                  * error interrupt (see cpt_can_enable_serr_int()).
15210                  */
15211                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15212                         crtc->pch_fifo_underrun_disabled = true;
15213         }
15214 }
15215
15216 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15217 {
15218         struct intel_connector *connector;
15219
15220         /* We need to check both for a crtc link (meaning that the
15221          * encoder is active and trying to read from a pipe) and the
15222          * pipe itself being active. */
15223         bool has_active_crtc = encoder->base.crtc &&
15224                 to_intel_crtc(encoder->base.crtc)->active;
15225
15226         connector = intel_encoder_find_connector(encoder);
15227         if (connector && !has_active_crtc) {
15228                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15229                               encoder->base.base.id,
15230                               encoder->base.name);
15231
15232                 /* Connector is active, but has no active pipe. This is
15233                  * fallout from our resume register restoring. Disable
15234                  * the encoder manually again. */
15235                 if (encoder->base.crtc) {
15236                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15237
15238                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15239                                       encoder->base.base.id,
15240                                       encoder->base.name);
15241                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15242                         if (encoder->post_disable)
15243                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15244                 }
15245                 encoder->base.crtc = NULL;
15246
15247                 /* Inconsistent output/port/pipe state happens presumably due to
15248                  * a bug in one of the get_hw_state functions. Or someplace else
15249                  * in our code, like the register restore mess on resume. Clamp
15250                  * things to off as a safer default. */
15251
15252                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15253                 connector->base.encoder = NULL;
15254         }
15255         /* Enabled encoders without active connectors will be fixed in
15256          * the crtc fixup. */
15257 }
15258
15259 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15260 {
15261         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15262
15263         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15264                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15265                 i915_disable_vga(dev_priv);
15266         }
15267 }
15268
15269 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15270 {
15271         /* This function can be called both from intel_modeset_setup_hw_state or
15272          * at a very early point in our resume sequence, where the power well
15273          * structures are not yet restored. Since this function is at a very
15274          * paranoid "someone might have enabled VGA while we were not looking"
15275          * level, just check if the power well is enabled instead of trying to
15276          * follow the "don't touch the power well if we don't need it" policy
15277          * the rest of the driver uses. */
15278         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15279                 return;
15280
15281         i915_redisable_vga_power_on(dev_priv);
15282
15283         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15284 }
15285
15286 static bool primary_get_hw_state(struct intel_plane *plane)
15287 {
15288         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15289
15290         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15291 }
15292
15293 /* FIXME read out full plane state for all planes */
15294 static void readout_plane_state(struct intel_crtc *crtc)
15295 {
15296         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15297         bool visible;
15298
15299         visible = crtc->active && primary_get_hw_state(primary);
15300
15301         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15302                                 to_intel_plane_state(primary->base.state),
15303                                 visible);
15304 }
15305
15306 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15307 {
15308         struct drm_i915_private *dev_priv = to_i915(dev);
15309         enum pipe pipe;
15310         struct intel_crtc *crtc;
15311         struct intel_encoder *encoder;
15312         struct intel_connector *connector;
15313         int i;
15314
15315         dev_priv->active_crtcs = 0;
15316
15317         for_each_intel_crtc(dev, crtc) {
15318                 struct intel_crtc_state *crtc_state =
15319                         to_intel_crtc_state(crtc->base.state);
15320
15321                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15322                 memset(crtc_state, 0, sizeof(*crtc_state));
15323                 crtc_state->base.crtc = &crtc->base;
15324
15325                 crtc_state->base.active = crtc_state->base.enable =
15326                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15327
15328                 crtc->base.enabled = crtc_state->base.enable;
15329                 crtc->active = crtc_state->base.active;
15330
15331                 if (crtc_state->base.active)
15332                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15333
15334                 readout_plane_state(crtc);
15335
15336                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15337                               crtc->base.base.id, crtc->base.name,
15338                               enableddisabled(crtc_state->base.active));
15339         }
15340
15341         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15342                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15343
15344                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15345                                                   &pll->state.hw_state);
15346                 pll->state.crtc_mask = 0;
15347                 for_each_intel_crtc(dev, crtc) {
15348                         struct intel_crtc_state *crtc_state =
15349                                 to_intel_crtc_state(crtc->base.state);
15350
15351                         if (crtc_state->base.active &&
15352                             crtc_state->shared_dpll == pll)
15353                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15354                 }
15355                 pll->active_mask = pll->state.crtc_mask;
15356
15357                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15358                               pll->name, pll->state.crtc_mask, pll->on);
15359         }
15360
15361         for_each_intel_encoder(dev, encoder) {
15362                 pipe = 0;
15363
15364                 if (encoder->get_hw_state(encoder, &pipe)) {
15365                         struct intel_crtc_state *crtc_state;
15366
15367                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15368                         crtc_state = to_intel_crtc_state(crtc->base.state);
15369
15370                         encoder->base.crtc = &crtc->base;
15371                         crtc_state->output_types |= 1 << encoder->type;
15372                         encoder->get_config(encoder, crtc_state);
15373                 } else {
15374                         encoder->base.crtc = NULL;
15375                 }
15376
15377                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15378                               encoder->base.base.id, encoder->base.name,
15379                               enableddisabled(encoder->base.crtc),
15380                               pipe_name(pipe));
15381         }
15382
15383         for_each_intel_connector(dev, connector) {
15384                 if (connector->get_hw_state(connector)) {
15385                         connector->base.dpms = DRM_MODE_DPMS_ON;
15386
15387                         encoder = connector->encoder;
15388                         connector->base.encoder = &encoder->base;
15389
15390                         if (encoder->base.crtc &&
15391                             encoder->base.crtc->state->active) {
15392                                 /*
15393                                  * This has to be done during hardware readout
15394                                  * because anything calling .crtc_disable may
15395                                  * rely on the connector_mask being accurate.
15396                                  */
15397                                 encoder->base.crtc->state->connector_mask |=
15398                                         1 << drm_connector_index(&connector->base);
15399                                 encoder->base.crtc->state->encoder_mask |=
15400                                         1 << drm_encoder_index(&encoder->base);
15401                         }
15402
15403                 } else {
15404                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15405                         connector->base.encoder = NULL;
15406                 }
15407                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15408                               connector->base.base.id, connector->base.name,
15409                               enableddisabled(connector->base.encoder));
15410         }
15411
15412         for_each_intel_crtc(dev, crtc) {
15413                 struct intel_crtc_state *crtc_state =
15414                         to_intel_crtc_state(crtc->base.state);
15415                 int pixclk = 0;
15416
15417                 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15418
15419                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15420                 if (crtc_state->base.active) {
15421                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15422                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15423                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15424
15425                         /*
15426                          * The initial mode needs to be set in order to keep
15427                          * the atomic core happy. It wants a valid mode if the
15428                          * crtc's enabled, so we do the above call.
15429                          *
15430                          * But we don't set all the derived state fully, hence
15431                          * set a flag to indicate that a full recalculation is
15432                          * needed on the next commit.
15433                          */
15434                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15435
15436                         intel_crtc_compute_pixel_rate(crtc_state);
15437
15438                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15439                             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15440                                 pixclk = crtc_state->pixel_rate;
15441                         else
15442                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15443
15444                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15445                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15446                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15447
15448                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15449                         update_scanline_offset(crtc);
15450                 }
15451
15452                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15453
15454                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15455         }
15456 }
15457
15458 static void
15459 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15460 {
15461         struct intel_encoder *encoder;
15462
15463         for_each_intel_encoder(&dev_priv->drm, encoder) {
15464                 u64 get_domains;
15465                 enum intel_display_power_domain domain;
15466
15467                 if (!encoder->get_power_domains)
15468                         continue;
15469
15470                 get_domains = encoder->get_power_domains(encoder);
15471                 for_each_power_domain(domain, get_domains)
15472                         intel_display_power_get(dev_priv, domain);
15473         }
15474 }
15475
15476 /* Scan out the current hw modeset state,
15477  * and sanitizes it to the current state
15478  */
15479 static void
15480 intel_modeset_setup_hw_state(struct drm_device *dev)
15481 {
15482         struct drm_i915_private *dev_priv = to_i915(dev);
15483         enum pipe pipe;
15484         struct intel_crtc *crtc;
15485         struct intel_encoder *encoder;
15486         int i;
15487
15488         intel_modeset_readout_hw_state(dev);
15489
15490         /* HW state is read out, now we need to sanitize this mess. */
15491         get_encoder_power_domains(dev_priv);
15492
15493         for_each_intel_encoder(dev, encoder) {
15494                 intel_sanitize_encoder(encoder);
15495         }
15496
15497         for_each_pipe(dev_priv, pipe) {
15498                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15499
15500                 intel_sanitize_crtc(crtc);
15501                 intel_dump_pipe_config(crtc, crtc->config,
15502                                        "[setup_hw_state]");
15503         }
15504
15505         intel_modeset_update_connector_atomic_state(dev);
15506
15507         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15508                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15509
15510                 if (!pll->on || pll->active_mask)
15511                         continue;
15512
15513                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15514
15515                 pll->funcs.disable(dev_priv, pll);
15516                 pll->on = false;
15517         }
15518
15519         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15520                 vlv_wm_get_hw_state(dev);
15521                 vlv_wm_sanitize(dev_priv);
15522         } else if (IS_GEN9(dev_priv)) {
15523                 skl_wm_get_hw_state(dev);
15524         } else if (HAS_PCH_SPLIT(dev_priv)) {
15525                 ilk_wm_get_hw_state(dev);
15526         }
15527
15528         for_each_intel_crtc(dev, crtc) {
15529                 u64 put_domains;
15530
15531                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15532                 if (WARN_ON(put_domains))
15533                         modeset_put_power_domains(dev_priv, put_domains);
15534         }
15535         intel_display_set_init_power(dev_priv, false);
15536
15537         intel_power_domains_verify_state(dev_priv);
15538
15539         intel_fbc_init_pipe_state(dev_priv);
15540 }
15541
15542 void intel_display_resume(struct drm_device *dev)
15543 {
15544         struct drm_i915_private *dev_priv = to_i915(dev);
15545         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15546         struct drm_modeset_acquire_ctx ctx;
15547         int ret;
15548
15549         dev_priv->modeset_restore_state = NULL;
15550         if (state)
15551                 state->acquire_ctx = &ctx;
15552
15553         /*
15554          * This is a cludge because with real atomic modeset mode_config.mutex
15555          * won't be taken. Unfortunately some probed state like
15556          * audio_codec_enable is still protected by mode_config.mutex, so lock
15557          * it here for now.
15558          */
15559         mutex_lock(&dev->mode_config.mutex);
15560         drm_modeset_acquire_init(&ctx, 0);
15561
15562         while (1) {
15563                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15564                 if (ret != -EDEADLK)
15565                         break;
15566
15567                 drm_modeset_backoff(&ctx);
15568         }
15569
15570         if (!ret)
15571                 ret = __intel_display_resume(dev, state, &ctx);
15572
15573         drm_modeset_drop_locks(&ctx);
15574         drm_modeset_acquire_fini(&ctx);
15575         mutex_unlock(&dev->mode_config.mutex);
15576
15577         if (ret)
15578                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15579         if (state)
15580                 drm_atomic_state_put(state);
15581 }
15582
15583 void intel_modeset_gem_init(struct drm_device *dev)
15584 {
15585         struct drm_i915_private *dev_priv = to_i915(dev);
15586
15587         intel_init_gt_powersave(dev_priv);
15588
15589         intel_setup_overlay(dev_priv);
15590 }
15591
15592 int intel_connector_register(struct drm_connector *connector)
15593 {
15594         struct intel_connector *intel_connector = to_intel_connector(connector);
15595         int ret;
15596
15597         ret = intel_backlight_device_register(intel_connector);
15598         if (ret)
15599                 goto err;
15600
15601         return 0;
15602
15603 err:
15604         return ret;
15605 }
15606
15607 void intel_connector_unregister(struct drm_connector *connector)
15608 {
15609         struct intel_connector *intel_connector = to_intel_connector(connector);
15610
15611         intel_backlight_device_unregister(intel_connector);
15612         intel_panel_destroy_backlight(connector);
15613 }
15614
15615 void intel_modeset_cleanup(struct drm_device *dev)
15616 {
15617         struct drm_i915_private *dev_priv = to_i915(dev);
15618
15619         flush_work(&dev_priv->atomic_helper.free_work);
15620         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15621
15622         intel_disable_gt_powersave(dev_priv);
15623
15624         /*
15625          * Interrupts and polling as the first thing to avoid creating havoc.
15626          * Too much stuff here (turning of connectors, ...) would
15627          * experience fancy races otherwise.
15628          */
15629         intel_irq_uninstall(dev_priv);
15630
15631         /*
15632          * Due to the hpd irq storm handling the hotplug work can re-arm the
15633          * poll handlers. Hence disable polling after hpd handling is shut down.
15634          */
15635         drm_kms_helper_poll_fini(dev);
15636
15637         intel_unregister_dsm_handler();
15638
15639         intel_fbc_global_disable(dev_priv);
15640
15641         /* flush any delayed tasks or pending work */
15642         flush_scheduled_work();
15643
15644         drm_mode_config_cleanup(dev);
15645
15646         intel_cleanup_overlay(dev_priv);
15647
15648         intel_cleanup_gt_powersave(dev_priv);
15649
15650         intel_teardown_gmbus(dev_priv);
15651 }
15652
15653 void intel_connector_attach_encoder(struct intel_connector *connector,
15654                                     struct intel_encoder *encoder)
15655 {
15656         connector->encoder = encoder;
15657         drm_mode_connector_attach_encoder(&connector->base,
15658                                           &encoder->base);
15659 }
15660
15661 /*
15662  * set vga decode state - true == enable VGA decode
15663  */
15664 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15665 {
15666         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15667         u16 gmch_ctrl;
15668
15669         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15670                 DRM_ERROR("failed to read control word\n");
15671                 return -EIO;
15672         }
15673
15674         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15675                 return 0;
15676
15677         if (state)
15678                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15679         else
15680                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15681
15682         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15683                 DRM_ERROR("failed to write control word\n");
15684                 return -EIO;
15685         }
15686
15687         return 0;
15688 }
15689
15690 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15691
15692 struct intel_display_error_state {
15693
15694         u32 power_well_driver;
15695
15696         int num_transcoders;
15697
15698         struct intel_cursor_error_state {
15699                 u32 control;
15700                 u32 position;
15701                 u32 base;
15702                 u32 size;
15703         } cursor[I915_MAX_PIPES];
15704
15705         struct intel_pipe_error_state {
15706                 bool power_domain_on;
15707                 u32 source;
15708                 u32 stat;
15709         } pipe[I915_MAX_PIPES];
15710
15711         struct intel_plane_error_state {
15712                 u32 control;
15713                 u32 stride;
15714                 u32 size;
15715                 u32 pos;
15716                 u32 addr;
15717                 u32 surface;
15718                 u32 tile_offset;
15719         } plane[I915_MAX_PIPES];
15720
15721         struct intel_transcoder_error_state {
15722                 bool power_domain_on;
15723                 enum transcoder cpu_transcoder;
15724
15725                 u32 conf;
15726
15727                 u32 htotal;
15728                 u32 hblank;
15729                 u32 hsync;
15730                 u32 vtotal;
15731                 u32 vblank;
15732                 u32 vsync;
15733         } transcoder[4];
15734 };
15735
15736 struct intel_display_error_state *
15737 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15738 {
15739         struct intel_display_error_state *error;
15740         int transcoders[] = {
15741                 TRANSCODER_A,
15742                 TRANSCODER_B,
15743                 TRANSCODER_C,
15744                 TRANSCODER_EDP,
15745         };
15746         int i;
15747
15748         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15749                 return NULL;
15750
15751         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15752         if (error == NULL)
15753                 return NULL;
15754
15755         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15756                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15757
15758         for_each_pipe(dev_priv, i) {
15759                 error->pipe[i].power_domain_on =
15760                         __intel_display_power_is_enabled(dev_priv,
15761                                                          POWER_DOMAIN_PIPE(i));
15762                 if (!error->pipe[i].power_domain_on)
15763                         continue;
15764
15765                 error->cursor[i].control = I915_READ(CURCNTR(i));
15766                 error->cursor[i].position = I915_READ(CURPOS(i));
15767                 error->cursor[i].base = I915_READ(CURBASE(i));
15768
15769                 error->plane[i].control = I915_READ(DSPCNTR(i));
15770                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15771                 if (INTEL_GEN(dev_priv) <= 3) {
15772                         error->plane[i].size = I915_READ(DSPSIZE(i));
15773                         error->plane[i].pos = I915_READ(DSPPOS(i));
15774                 }
15775                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15776                         error->plane[i].addr = I915_READ(DSPADDR(i));
15777                 if (INTEL_GEN(dev_priv) >= 4) {
15778                         error->plane[i].surface = I915_READ(DSPSURF(i));
15779                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15780                 }
15781
15782                 error->pipe[i].source = I915_READ(PIPESRC(i));
15783
15784                 if (HAS_GMCH_DISPLAY(dev_priv))
15785                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15786         }
15787
15788         /* Note: this does not include DSI transcoders. */
15789         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15790         if (HAS_DDI(dev_priv))
15791                 error->num_transcoders++; /* Account for eDP. */
15792
15793         for (i = 0; i < error->num_transcoders; i++) {
15794                 enum transcoder cpu_transcoder = transcoders[i];
15795
15796                 error->transcoder[i].power_domain_on =
15797                         __intel_display_power_is_enabled(dev_priv,
15798                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15799                 if (!error->transcoder[i].power_domain_on)
15800                         continue;
15801
15802                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15803
15804                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15805                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15806                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15807                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15808                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15809                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15810                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15811         }
15812
15813         return error;
15814 }
15815
15816 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15817
15818 void
15819 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15820                                 struct intel_display_error_state *error)
15821 {
15822         struct drm_i915_private *dev_priv = m->i915;
15823         int i;
15824
15825         if (!error)
15826                 return;
15827
15828         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15829         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15830                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15831                            error->power_well_driver);
15832         for_each_pipe(dev_priv, i) {
15833                 err_printf(m, "Pipe [%d]:\n", i);
15834                 err_printf(m, "  Power: %s\n",
15835                            onoff(error->pipe[i].power_domain_on));
15836                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15837                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15838
15839                 err_printf(m, "Plane [%d]:\n", i);
15840                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15841                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15842                 if (INTEL_GEN(dev_priv) <= 3) {
15843                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15844                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15845                 }
15846                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15847                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15848                 if (INTEL_GEN(dev_priv) >= 4) {
15849                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15850                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15851                 }
15852
15853                 err_printf(m, "Cursor [%d]:\n", i);
15854                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15855                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15856                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15857         }
15858
15859         for (i = 0; i < error->num_transcoders; i++) {
15860                 err_printf(m, "CPU transcoder: %s\n",
15861                            transcoder_name(error->transcoder[i].cpu_transcoder));
15862                 err_printf(m, "  Power: %s\n",
15863                            onoff(error->transcoder[i].power_domain_on));
15864                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15865                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15866                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15867                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15868                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15869                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15870                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15871         }
15872 }
15873
15874 #endif