drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 /* returns HPLL frequency in kHz */
 136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 137 {
 138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 139
 140         /* Obtain SKU information */
 141         mutex_lock(&dev_priv->sb_lock);
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144         mutex_unlock(&dev_priv->sb_lock);
 145
 146         return vco_freq[hpll_freq] * 1000;
 147 }
 148
 149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 150                                   const char *name, u32 reg)
 151 {
 152         u32 val;
 153         int divider;
 154
 155         if (dev_priv->hpll_freq == 0)
 156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 169 }
 170
 171 int
 172 intel_pch_rawclk(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175
 176         WARN_ON(!HAS_PCH_SPLIT(dev));
 177
 178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 int intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (!IS_VALLEYVIEW(dev_priv))
 217                 return;
 218
 219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 220                                                       CCK_CZ_CLOCK_CONTROL);
 221
 222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 223 }
 224
 225 static inline u32 /* units of 100MHz */
 226 intel_fdi_link_freq(struct drm_device *dev)
 227 {
 228         if (IS_GEN5(dev)) {
 229                 struct drm_i915_private *dev_priv = dev->dev_private;
 230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 231         } else
 232                 return 27;
 233 }
 234
 235 static const intel_limit_t intel_limits_i8xx_dac = {
 236         .dot = { .min = 25000, .max = 350000 },
 237         .vco = { .min = 908000, .max = 1512000 },
 238         .n = { .min = 2, .max = 16 },
 239         .m = { .min = 96, .max = 140 },
 240         .m1 = { .min = 18, .max = 26 },
 241         .m2 = { .min = 6, .max = 16 },
 242         .p = { .min = 4, .max = 128 },
 243         .p1 = { .min = 2, .max = 33 },
 244         .p2 = { .dot_limit = 165000,
 245                 .p2_slow = 4, .p2_fast = 2 },
 246 };
 247
 248 static const intel_limit_t intel_limits_i8xx_dvo = {
 249         .dot = { .min = 25000, .max = 350000 },
 250         .vco = { .min = 908000, .max = 1512000 },
 251         .n = { .min = 2, .max = 16 },
 252         .m = { .min = 96, .max = 140 },
 253         .m1 = { .min = 18, .max = 26 },
 254         .m2 = { .min = 6, .max = 16 },
 255         .p = { .min = 4, .max = 128 },
 256         .p1 = { .min = 2, .max = 33 },
 257         .p2 = { .dot_limit = 165000,
 258                 .p2_slow = 4, .p2_fast = 4 },
 259 };
 260
 261 static const intel_limit_t intel_limits_i8xx_lvds = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 908000, .max = 1512000 },
 264         .n = { .min = 2, .max = 16 },
 265         .m = { .min = 96, .max = 140 },
 266         .m1 = { .min = 18, .max = 26 },
 267         .m2 = { .min = 6, .max = 16 },
 268         .p = { .min = 4, .max = 128 },
 269         .p1 = { .min = 1, .max = 6 },
 270         .p2 = { .dot_limit = 165000,
 271                 .p2_slow = 14, .p2_fast = 7 },
 272 };
 273
 274 static const intel_limit_t intel_limits_i9xx_sdvo = {
 275         .dot = { .min = 20000, .max = 400000 },
 276         .vco = { .min = 1400000, .max = 2800000 },
 277         .n = { .min = 1, .max = 6 },
 278         .m = { .min = 70, .max = 120 },
 279         .m1 = { .min = 8, .max = 18 },
 280         .m2 = { .min = 3, .max = 7 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_i9xx_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1400000, .max = 2800000 },
 290         .n = { .min = 1, .max = 6 },
 291         .m = { .min = 70, .max = 120 },
 292         .m1 = { .min = 8, .max = 18 },
 293         .m2 = { .min = 3, .max = 7 },
 294         .p = { .min = 7, .max = 98 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 7 },
 298 };
 299
 300
 301 static const intel_limit_t intel_limits_g4x_sdvo = {
 302         .dot = { .min = 25000, .max = 270000 },
 303         .vco = { .min = 1750000, .max = 3500000},
 304         .n = { .min = 1, .max = 4 },
 305         .m = { .min = 104, .max = 138 },
 306         .m1 = { .min = 17, .max = 23 },
 307         .m2 = { .min = 5, .max = 11 },
 308         .p = { .min = 10, .max = 30 },
 309         .p1 = { .min = 1, .max = 3},
 310         .p2 = { .dot_limit = 270000,
 311                 .p2_slow = 10,
 312                 .p2_fast = 10
 313         },
 314 };
 315
 316 static const intel_limit_t intel_limits_g4x_hdmi = {
 317         .dot = { .min = 22000, .max = 400000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 16, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 5, .max = 80 },
 324         .p1 = { .min = 1, .max = 8},
 325         .p2 = { .dot_limit = 165000,
 326                 .p2_slow = 10, .p2_fast = 5 },
 327 };
 328
 329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 330         .dot = { .min = 20000, .max = 115000 },
 331         .vco = { .min = 1750000, .max = 3500000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 0,
 339                 .p2_slow = 14, .p2_fast = 14
 340         },
 341 };
 342
 343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 344         .dot = { .min = 80000, .max = 224000 },
 345         .vco = { .min = 1750000, .max = 3500000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 17, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 7, .p2_fast = 7
 354         },
 355 };
 356
 357 static const intel_limit_t intel_limits_pineview_sdvo = {
 358         .dot = { .min = 20000, .max = 400000},
 359         .vco = { .min = 1700000, .max = 3500000 },
 360         /* Pineview's Ncounter is a ring counter */
 361         .n = { .min = 3, .max = 6 },
 362         .m = { .min = 2, .max = 256 },
 363         /* Pineview only has one combined m divider, which we treat as m2. */
 364         .m1 = { .min = 0, .max = 0 },
 365         .m2 = { .min = 0, .max = 254 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 200000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const intel_limit_t intel_limits_pineview_lvds = {
 373         .dot = { .min = 20000, .max = 400000 },
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         .n = { .min = 3, .max = 6 },
 376         .m = { .min = 2, .max = 256 },
 377         .m1 = { .min = 0, .max = 0 },
 378         .m2 = { .min = 0, .max = 254 },
 379         .p = { .min = 7, .max = 112 },
 380         .p1 = { .min = 1, .max = 8 },
 381         .p2 = { .dot_limit = 112000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 /* Ironlake / Sandybridge
 386  *
 387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 388  * the range value for them is (actual_value - 2).
 389  */
 390 static const intel_limit_t intel_limits_ironlake_dac = {
 391         .dot = { .min = 25000, .max = 350000 },
 392         .vco = { .min = 1760000, .max = 3510000 },
 393         .n = { .min = 1, .max = 5 },
 394         .m = { .min = 79, .max = 127 },
 395         .m1 = { .min = 12, .max = 22 },
 396         .m2 = { .min = 5, .max = 9 },
 397         .p = { .min = 5, .max = 80 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 225000,
 400                 .p2_slow = 10, .p2_fast = 5 },
 401 };
 402
 403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 404         .dot = { .min = 25000, .max = 350000 },
 405         .vco = { .min = 1760000, .max = 3510000 },
 406         .n = { .min = 1, .max = 3 },
 407         .m = { .min = 79, .max = 118 },
 408         .m1 = { .min = 12, .max = 22 },
 409         .m2 = { .min = 5, .max = 9 },
 410         .p = { .min = 28, .max = 112 },
 411         .p1 = { .min = 2, .max = 8 },
 412         .p2 = { .dot_limit = 225000,
 413                 .p2_slow = 14, .p2_fast = 14 },
 414 };
 415
 416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 417         .dot = { .min = 25000, .max = 350000 },
 418         .vco = { .min = 1760000, .max = 3510000 },
 419         .n = { .min = 1, .max = 3 },
 420         .m = { .min = 79, .max = 127 },
 421         .m1 = { .min = 12, .max = 22 },
 422         .m2 = { .min = 5, .max = 9 },
 423         .p = { .min = 14, .max = 56 },
 424         .p1 = { .min = 2, .max = 8 },
 425         .p2 = { .dot_limit = 225000,
 426                 .p2_slow = 7, .p2_fast = 7 },
 427 };
 428
 429 /* LVDS 100mhz refclk limits. */
 430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 2 },
 434         .m = { .min = 79, .max = 126 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 126 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 42 },
 451         .p1 = { .min = 2, .max = 6 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 static const intel_limit_t intel_limits_vlv = {
 457          /*
 458           * These are the data rate limits (measured in fast clocks)
 459           * since those are the strictest limits we have. The fast
 460           * clock and actual rate limits are more relaxed, so checking
 461           * them would make no difference.
 462           */
 463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 464         .vco = { .min = 4000000, .max = 6000000 },
 465         .n = { .min = 1, .max = 7 },
 466         .m1 = { .min = 2, .max = 3 },
 467         .m2 = { .min = 11, .max = 156 },
 468         .p1 = { .min = 2, .max = 3 },
 469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 470 };
 471
 472 static const intel_limit_t intel_limits_chv = {
 473         /*
 474          * These are the data rate limits (measured in fast clocks)
 475          * since those are the strictest limits we have.  The fast
 476          * clock and actual rate limits are more relaxed, so checking
 477          * them would make no difference.
 478          */
 479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 480         .vco = { .min = 4800000, .max = 6480000 },
 481         .n = { .min = 1, .max = 1 },
 482         .m1 = { .min = 2, .max = 2 },
 483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 484         .p1 = { .min = 2, .max = 4 },
 485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 486 };
 487
 488 static const intel_limit_t intel_limits_bxt = {
 489         /* FIXME: find real dot limits */
 490         .dot = { .min = 0, .max = INT_MAX },
 491         .vco = { .min = 4800000, .max = 6700000 },
 492         .n = { .min = 1, .max = 1 },
 493         .m1 = { .min = 2, .max = 2 },
 494         /* FIXME: find real m2 limits */
 495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 496         .p1 = { .min = 2, .max = 4 },
 497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 498 };
 499
 500 static bool
 501 needs_modeset(struct drm_crtc_state *state)
 502 {
 503         return drm_atomic_crtc_needs_modeset(state);
 504 }
 505
 506 /**
 507  * Returns whether any output on the specified pipe is of the specified type
 508  */
 509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 510 {
 511         struct drm_device *dev = crtc->base.dev;
 512         struct intel_encoder *encoder;
 513
 514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 515                 if (encoder->type == type)
 516                         return true;
 517
 518         return false;
 519 }
 520
 521 /**
 522  * Returns whether any output on the specified pipe will have the specified
 523  * type after a staged modeset is complete, i.e., the same as
 524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 525  * encoder->crtc.
 526  */
 527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 528                                       int type)
 529 {
 530         struct drm_atomic_state *state = crtc_state->base.state;
 531         struct drm_connector *connector;
 532         struct drm_connector_state *connector_state;
 533         struct intel_encoder *encoder;
 534         int i, num_connectors = 0;
 535
 536         for_each_connector_in_state(state, connector, connector_state, i) {
 537                 if (connector_state->crtc != crtc_state->base.crtc)
 538                         continue;
 539
 540                 num_connectors++;
 541
 542                 encoder = to_intel_encoder(connector_state->best_encoder);
 543                 if (encoder->type == type)
 544                         return true;
 545         }
 546
 547         WARN_ON(num_connectors == 0);
 548
 549         return false;
 550 }
 551
 552 static const intel_limit_t *
 553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 554 {
 555         struct drm_device *dev = crtc_state->base.crtc->dev;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 559                 if (intel_is_dual_link_lvds(dev)) {
 560                         if (refclk == 100000)
 561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 562                         else
 563                                 limit = &intel_limits_ironlake_dual_lvds;
 564                 } else {
 565                         if (refclk == 100000)
 566                                 limit = &intel_limits_ironlake_single_lvds_100m;
 567                         else
 568                                 limit = &intel_limits_ironlake_single_lvds;
 569                 }
 570         } else
 571                 limit = &intel_limits_ironlake_dac;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *
 577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 578 {
 579         struct drm_device *dev = crtc_state->base.crtc->dev;
 580         const intel_limit_t *limit;
 581
 582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 583                 if (intel_is_dual_link_lvds(dev))
 584                         limit = &intel_limits_g4x_dual_channel_lvds;
 585                 else
 586                         limit = &intel_limits_g4x_single_channel_lvds;
 587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 589                 limit = &intel_limits_g4x_hdmi;
 590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 591                 limit = &intel_limits_g4x_sdvo;
 592         } else /* The option is for other outputs */
 593                 limit = &intel_limits_i9xx_sdvo;
 594
 595         return limit;
 596 }
 597
 598 static const intel_limit_t *
 599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 600 {
 601         struct drm_device *dev = crtc_state->base.crtc->dev;
 602         const intel_limit_t *limit;
 603
 604         if (IS_BROXTON(dev))
 605                 limit = &intel_limits_bxt;
 606         else if (HAS_PCH_SPLIT(dev))
 607                 limit = intel_ironlake_limit(crtc_state, refclk);
 608         else if (IS_G4X(dev)) {
 609                 limit = intel_g4x_limit(crtc_state);
 610         } else if (IS_PINEVIEW(dev)) {
 611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 612                         limit = &intel_limits_pineview_lvds;
 613                 else
 614                         limit = &intel_limits_pineview_sdvo;
 615         } else if (IS_CHERRYVIEW(dev)) {
 616                 limit = &intel_limits_chv;
 617         } else if (IS_VALLEYVIEW(dev)) {
 618                 limit = &intel_limits_vlv;
 619         } else if (!IS_GEN2(dev)) {
 620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 621                         limit = &intel_limits_i9xx_lvds;
 622                 else
 623                         limit = &intel_limits_i9xx_sdvo;
 624         } else {
 625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 626                         limit = &intel_limits_i8xx_lvds;
 627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 628                         limit = &intel_limits_i8xx_dvo;
 629                 else
 630                         limit = &intel_limits_i8xx_dac;
 631         }
 632         return limit;
 633 }
 634
 635 /*
 636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 639  * The helpers' return value is the rate of the clock that is fed to the
 640  * display engine's pipe which can be the above fast dot clock rate or a
 641  * divided-down version of it.
 642  */
 643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 645 {
 646         clock->m = clock->m2 + 2;
 647         clock->p = clock->p1 * clock->p2;
 648         if (WARN_ON(clock->n == 0 || clock->p == 0))
 649                 return 0;
 650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 652
 653         return clock->dot;
 654 }
 655
 656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 657 {
 658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 659 }
 660
 661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = i9xx_dpll_compute_m(clock);
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 674 {
 675         clock->m = clock->m1 * clock->m2;
 676         clock->p = clock->p1 * clock->p2;
 677         if (WARN_ON(clock->n == 0 || clock->p == 0))
 678                 return 0;
 679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 681
 682         return clock->dot / 5;
 683 }
 684
 685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 686 {
 687         clock->m = clock->m1 * clock->m2;
 688         clock->p = clock->p1 * clock->p2;
 689         if (WARN_ON(clock->n == 0 || clock->p == 0))
 690                 return 0;
 691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 692                         clock->n << 22);
 693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 694
 695         return clock->dot / 5;
 696 }
 697
 698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 699 /**
 700  * Returns whether the given set of divisors are valid for a given refclk with
 701  * the given connectors.
 702  */
 703
 704 static bool intel_PLL_is_valid(struct drm_device *dev,
 705                                const intel_limit_t *limit,
 706                                const intel_clock_t *clock)
 707 {
 708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 709                 INTELPllInvalid("n out of range\n");
 710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 711                 INTELPllInvalid("p1 out of range\n");
 712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 713                 INTELPllInvalid("m2 out of range\n");
 714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 715                 INTELPllInvalid("m1 out of range\n");
 716
 717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 718                 if (clock->m1 <= clock->m2)
 719                         INTELPllInvalid("m1 <= m2\n");
 720
 721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 723                         INTELPllInvalid("p out of range\n");
 724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 725                         INTELPllInvalid("m out of range\n");
 726         }
 727
 728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 729                 INTELPllInvalid("vco out of range\n");
 730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 731          * connector, etc., rather than just a single range.
 732          */
 733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 734                 INTELPllInvalid("dot out of range\n");
 735
 736         return true;
 737 }
 738
 739 static int
 740 i9xx_select_p2_div(const intel_limit_t *limit,
 741                    const struct intel_crtc_state *crtc_state,
 742                    int target)
 743 {
 744         struct drm_device *dev = crtc_state->base.crtc->dev;
 745
 746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 747                 /*
 748                  * For LVDS just rely on its current settings for dual-channel.
 749                  * We haven't figured out how to reliably set up different
 750                  * single/dual channel state, if we even can.
 751                  */
 752                 if (intel_is_dual_link_lvds(dev))
 753                         return limit->p2.p2_fast;
 754                 else
 755                         return limit->p2.p2_slow;
 756         } else {
 757                 if (target < limit->p2.dot_limit)
 758                         return limit->p2.p2_slow;
 759                 else
 760                         return limit->p2.p2_fast;
 761         }
 762 }
 763
 764 static bool
 765 i9xx_find_best_dpll(const intel_limit_t *limit,
 766                     struct intel_crtc_state *crtc_state,
 767                     int target, int refclk, intel_clock_t *match_clock,
 768                     intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         if (clock.m2 >= clock.m1)
 783                                 break;
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         i9xx_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794                                         if (match_clock &&
 795                                             clock.p != match_clock->p)
 796                                                 continue;
 797
 798                                         this_err = abs(clock.dot - target);
 799                                         if (this_err < err) {
 800                                                 *best_clock = clock;
 801                                                 err = this_err;
 802                                         }
 803                                 }
 804                         }
 805                 }
 806         }
 807
 808         return (err != target);
 809 }
 810
 811 static bool
 812 pnv_find_best_dpll(const intel_limit_t *limit,
 813                    struct intel_crtc_state *crtc_state,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc_state->base.crtc->dev;
 818         intel_clock_t clock;
 819         int err = target;
 820
 821         memset(best_clock, 0, sizeof(*best_clock));
 822
 823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         for (clock.n = limit->n.min;
 830                              clock.n <= limit->n.max; clock.n++) {
 831                                 for (clock.p1 = limit->p1.min;
 832                                         clock.p1 <= limit->p1.max; clock.p1++) {
 833                                         int this_err;
 834
 835                                         pnv_calc_dpll_params(refclk, &clock);
 836                                         if (!intel_PLL_is_valid(dev, limit,
 837                                                                 &clock))
 838                                                 continue;
 839                                         if (match_clock &&
 840                                             clock.p != match_clock->p)
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 g4x_find_best_dpll(const intel_limit_t *limit,
 858                    struct intel_crtc_state *crtc_state,
 859                    int target, int refclk, intel_clock_t *match_clock,
 860                    intel_clock_t *best_clock)
 861 {
 862         struct drm_device *dev = crtc_state->base.crtc->dev;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found = false;
 866         /* approximately equals target * 0.00585 */
 867         int err_most = (target >> 8) + (target >> 9);
 868
 869         memset(best_clock, 0, sizeof(*best_clock));
 870
 871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 872
 873         max_n = limit->n.max;
 874         /* based on hardware requirement, prefer smaller n to precision */
 875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 876                 /* based on hardware requirement, prefere larger m1,m2 */
 877                 for (clock.m1 = limit->m1.max;
 878                      clock.m1 >= limit->m1.min; clock.m1--) {
 879                         for (clock.m2 = limit->m2.max;
 880                              clock.m2 >= limit->m2.min; clock.m2--) {
 881                                 for (clock.p1 = limit->p1.max;
 882                                      clock.p1 >= limit->p1.min; clock.p1--) {
 883                                         int this_err;
 884
 885                                         i9xx_calc_dpll_params(refclk, &clock);
 886                                         if (!intel_PLL_is_valid(dev, limit,
 887                                                                 &clock))
 888                                                 continue;
 889
 890                                         this_err = abs(clock.dot - target);
 891                                         if (this_err < err_most) {
 892                                                 *best_clock = clock;
 893                                                 err_most = this_err;
 894                                                 max_n = clock.n;
 895                                                 found = true;
 896                                         }
 897                                 }
 898                         }
 899                 }
 900         }
 901         return found;
 902 }
 903
 904 /*
 905  * Check if the calculated PLL configuration is more optimal compared to the
 906  * best configuration and error found so far. Return the calculated error.
 907  */
 908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 909                                const intel_clock_t *calculated_clock,
 910                                const intel_clock_t *best_clock,
 911                                unsigned int best_error_ppm,
 912                                unsigned int *error_ppm)
 913 {
 914         /*
 915          * For CHV ignore the error and consider only the P value.
 916          * Prefer a bigger P value based on HW requirements.
 917          */
 918         if (IS_CHERRYVIEW(dev)) {
 919                 *error_ppm = 0;
 920
 921                 return calculated_clock->p > best_clock->p;
 922         }
 923
 924         if (WARN_ON_ONCE(!target_freq))
 925                 return false;
 926
 927         *error_ppm = div_u64(1000000ULL *
 928                                 abs(target_freq - calculated_clock->dot),
 929                              target_freq);
 930         /*
 931          * Prefer a better P value over a better (smaller) error if the error
 932          * is small. Ensure this preference for future configurations too by
 933          * setting the error to 0.
 934          */
 935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 936                 *error_ppm = 0;
 937
 938                 return true;
 939         }
 940
 941         return *error_ppm + 10 < best_error_ppm;
 942 }
 943
 944 static bool
 945 vlv_find_best_dpll(const intel_limit_t *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, intel_clock_t *match_clock,
 948                    intel_clock_t *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         intel_clock_t clock;
 953         unsigned int bestppm = 1000000;
 954         /* min update 19.2 MHz */
 955         int max_n = min(limit->n.max, refclk / 19200);
 956         bool found = false;
 957
 958         target *= 5; /* fast clock */
 959
 960         memset(best_clock, 0, sizeof(*best_clock));
 961
 962         /* based on hardware requirement, prefer smaller n to precision */
 963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 967                                 clock.p = clock.p1 * clock.p2;
 968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 970                                         unsigned int ppm;
 971
 972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 973                                                                      refclk * clock.m1);
 974
 975                                         vlv_calc_dpll_params(refclk, &clock);
 976
 977                                         if (!intel_PLL_is_valid(dev, limit,
 978                                                                 &clock))
 979                                                 continue;
 980
 981                                         if (!vlv_PLL_is_optimal(dev, target,
 982                                                                 &clock,
 983                                                                 best_clock,
 984                                                                 bestppm, &ppm))
 985                                                 continue;
 986
 987                                         *best_clock = clock;
 988                                         bestppm = ppm;
 989                                         found = true;
 990                                 }
 991                         }
 992                 }
 993         }
 994
 995         return found;
 996 }
 997
 998 static bool
 999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 int reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(DPLL(pipe));
1164         cur_state = !!(val & DPLL_VCO_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "PLL state assertion failure (expected %s, current %s)\n",
1167              state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173         u32 val;
1174         bool cur_state;
1175
1176         mutex_lock(&dev_priv->sb_lock);
1177         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178         mutex_unlock(&dev_priv->sb_lock);
1179
1180         cur_state = val & DSI_PLL_VCO_EN;
1181         I915_STATE_WARN(cur_state != state,
1182              "DSI PLL state assertion failure (expected %s, current %s)\n",
1183              state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193         if (crtc->config->shared_dpll < 0)
1194                 return NULL;
1195
1196         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201                         struct intel_shared_dpll *pll,
1202                         bool state)
1203 {
1204         bool cur_state;
1205         struct intel_dpll_hw_state hw_state;
1206
1207         if (WARN (!pll,
1208                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1209                 return;
1210
1211         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212         I915_STATE_WARN(cur_state != state,
1213              "%s assertion failure (expected %s, current %s)\n",
1214              pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218                           enum pipe pipe, bool state)
1219 {
1220         bool cur_state;
1221         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222                                                                       pipe);
1223
1224         if (HAS_DDI(dev_priv->dev)) {
1225                 /* DDI does not have a specific FDI_TX register */
1226                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228         } else {
1229                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230                 cur_state = !!(val & FDI_TX_ENABLE);
1231         }
1232         I915_STATE_WARN(cur_state != state,
1233              "FDI TX state assertion failure (expected %s, current %s)\n",
1234              state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240                           enum pipe pipe, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(FDI_RX_CTL(pipe));
1246         cur_state = !!(val & FDI_RX_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "FDI RX state assertion failure (expected %s, current %s)\n",
1249              state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255                                       enum pipe pipe)
1256 {
1257         u32 val;
1258
1259         /* ILK FDI PLL is always enabled */
1260         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261                 return;
1262
1263         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264         if (HAS_DDI(dev_priv->dev))
1265                 return;
1266
1267         val = I915_READ(FDI_TX_CTL(pipe));
1268         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272                        enum pipe pipe, bool state)
1273 {
1274         u32 val;
1275         bool cur_state;
1276
1277         val = I915_READ(FDI_RX_CTL(pipe));
1278         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279         I915_STATE_WARN(cur_state != state,
1280              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281              state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285                            enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         int pp_reg;
1289         u32 val;
1290         enum pipe panel_pipe = PIPE_A;
1291         bool locked = true;
1292
1293         if (WARN_ON(HAS_DDI(dev)))
1294                 return;
1295
1296         if (HAS_PCH_SPLIT(dev)) {
1297                 u32 port_sel;
1298
1299                 pp_reg = PCH_PP_CONTROL;
1300                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304                         panel_pipe = PIPE_B;
1305                 /* XXX: else fix for eDP */
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 /* presumably write lock depends on pipe, not port select */
1308                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309                 panel_pipe = pipe;
1310         } else {
1311                 pp_reg = PP_CONTROL;
1312                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313                         panel_pipe = PIPE_B;
1314         }
1315
1316         val = I915_READ(pp_reg);
1317         if (!(val & PANEL_POWER_ON) ||
1318             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319                 locked = false;
1320
1321         I915_STATE_WARN(panel_pipe == pipe && locked,
1322              "panel assertion failure, pipe %c regs locked\n",
1323              pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327                           enum pipe pipe, bool state)
1328 {
1329         struct drm_device *dev = dev_priv->dev;
1330         bool cur_state;
1331
1332         if (IS_845G(dev) || IS_I865G(dev))
1333                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334         else
1335                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345                  enum pipe pipe, bool state)
1346 {
1347         bool cur_state;
1348         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349                                                                       pipe);
1350
1351         /* if we need the pipe quirk it must be always on */
1352         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354                 state = true;
1355
1356         if (!intel_display_power_is_enabled(dev_priv,
1357                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358                 cur_state = false;
1359         } else {
1360                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361                 cur_state = !!(val & PIPECONF_ENABLE);
1362         }
1363
1364         I915_STATE_WARN(cur_state != state,
1365              "pipe %c assertion failure (expected %s, current %s)\n",
1366              pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370                          enum plane plane, bool state)
1371 {
1372         u32 val;
1373         bool cur_state;
1374
1375         val = I915_READ(DSPCNTR(plane));
1376         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377         I915_STATE_WARN(cur_state != state,
1378              "plane %c assertion failure (expected %s, current %s)\n",
1379              plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int i;
1390
1391         /* Primary planes are fixed to pipes on gen4+ */
1392         if (INTEL_INFO(dev)->gen >= 4) {
1393                 u32 val = I915_READ(DSPCNTR(pipe));
1394                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395                      "plane %c assertion failure, should be disabled but not\n",
1396                      plane_name(pipe));
1397                 return;
1398         }
1399
1400         /* Need to check both planes against the pipe */
1401         for_each_pipe(dev_priv, i) {
1402                 u32 val = I915_READ(DSPCNTR(i));
1403                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404                         DISPPLANE_SEL_PIPE_SHIFT;
1405                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407                      plane_name(i), pipe_name(pipe));
1408         }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412                                     enum pipe pipe)
1413 {
1414         struct drm_device *dev = dev_priv->dev;
1415         int sprite;
1416
1417         if (INTEL_INFO(dev)->gen >= 9) {
1418                 for_each_sprite(dev_priv, pipe, sprite) {
1419                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422                              sprite, pipe_name(pipe));
1423                 }
1424         } else if (IS_VALLEYVIEW(dev)) {
1425                 for_each_sprite(dev_priv, pipe, sprite) {
1426                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1427                         I915_STATE_WARN(val & SP_ENABLE,
1428                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429                              sprite_name(pipe, sprite), pipe_name(pipe));
1430                 }
1431         } else if (INTEL_INFO(dev)->gen >= 7) {
1432                 u32 val = I915_READ(SPRCTL(pipe));
1433                 I915_STATE_WARN(val & SPRITE_ENABLE,
1434                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435                      plane_name(pipe), pipe_name(pipe));
1436         } else if (INTEL_INFO(dev)->gen >= 5) {
1437                 u32 val = I915_READ(DVSCNTR(pipe));
1438                 I915_STATE_WARN(val & DVS_ENABLE,
1439                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440                      plane_name(pipe), pipe_name(pipe));
1441         }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447                 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452         u32 val;
1453         bool enabled;
1454
1455         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457         val = I915_READ(PCH_DREF_CONTROL);
1458         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459                             DREF_SUPERSPREAD_SOURCE_MASK));
1460         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464                                            enum pipe pipe)
1465 {
1466         u32 val;
1467         bool enabled;
1468
1469         val = I915_READ(PCH_TRANSCONF(pipe));
1470         enabled = !!(val & TRANS_ENABLE);
1471         I915_STATE_WARN(enabled,
1472              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473              pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477                             enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479         if ((val & DP_PORT_EN) == 0)
1480                 return false;
1481
1482         if (HAS_PCH_CPT(dev_priv->dev)) {
1483                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486                         return false;
1487         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489                         return false;
1490         } else {
1491                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492                         return false;
1493         }
1494         return true;
1495 }
1496
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498                               enum pipe pipe, u32 val)
1499 {
1500         if ((val & SDVO_ENABLE) == 0)
1501                 return false;
1502
1503         if (HAS_PCH_CPT(dev_priv->dev)) {
1504                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1505                         return false;
1506         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508                         return false;
1509         } else {
1510                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1511                         return false;
1512         }
1513         return true;
1514 }
1515
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517                               enum pipe pipe, u32 val)
1518 {
1519         if ((val & LVDS_PORT_EN) == 0)
1520                 return false;
1521
1522         if (HAS_PCH_CPT(dev_priv->dev)) {
1523                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524                         return false;
1525         } else {
1526                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527                         return false;
1528         }
1529         return true;
1530 }
1531
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533                               enum pipe pipe, u32 val)
1534 {
1535         if ((val & ADPA_DAC_ENABLE) == 0)
1536                 return false;
1537         if (HAS_PCH_CPT(dev_priv->dev)) {
1538                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539                         return false;
1540         } else {
1541                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542                         return false;
1543         }
1544         return true;
1545 }
1546
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548                                    enum pipe pipe, int reg, u32 port_sel)
1549 {
1550         u32 val = I915_READ(reg);
1551         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553              reg, pipe_name(pipe));
1554
1555         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556              && (val & DP_PIPEB_SELECT),
1557              "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561                                      enum pipe pipe, int reg)
1562 {
1563         u32 val = I915_READ(reg);
1564         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566              reg, pipe_name(pipe));
1567
1568         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569              && (val & SDVO_PIPE_B_SELECT),
1570              "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574                                       enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582         val = I915_READ(PCH_ADPA);
1583         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584              "PCH VGA enabled on transcoder %c, should be disabled\n",
1585              pipe_name(pipe));
1586
1587         val = I915_READ(PCH_LVDS);
1588         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590              pipe_name(pipe));
1591
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         int reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         int reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /*
1717          * Apparently we need to have VGA mode enabled prior to changing
1718          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719          * dividers, even though the register value does change.
1720          */
1721         I915_WRITE(reg, 0);
1722
1723         I915_WRITE(reg, dpll);
1724
1725         /* Wait for the clocks to stabilize. */
1726         POSTING_READ(reg);
1727         udelay(150);
1728
1729         if (INTEL_INFO(dev)->gen >= 4) {
1730                 I915_WRITE(DPLL_MD(crtc->pipe),
1731                            crtc->config->dpll_hw_state.dpll_md);
1732         } else {
1733                 /* The pixel multiplier can only be updated once the
1734                  * DPLL is enabled and the clocks are stable.
1735                  *
1736                  * So write it again.
1737                  */
1738                 I915_WRITE(reg, dpll);
1739         }
1740
1741         /* We do this three times for luck */
1742         I915_WRITE(reg, dpll);
1743         POSTING_READ(reg);
1744         udelay(150); /* wait for warmup */
1745         I915_WRITE(reg, dpll);
1746         POSTING_READ(reg);
1747         udelay(150); /* wait for warmup */
1748         I915_WRITE(reg, dpll);
1749         POSTING_READ(reg);
1750         udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754  * i9xx_disable_pll - disable a PLL
1755  * @dev_priv: i915 private structure
1756  * @pipe: pipe PLL to disable
1757  *
1758  * Disable the PLL for @pipe, making sure the pipe is off first.
1759  *
1760  * Note!  This is for pre-ILK only.
1761  */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764         struct drm_device *dev = crtc->base.dev;
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         enum pipe pipe = crtc->pipe;
1767
1768         /* Disable DVO 2x clock on both PLLs if necessary */
1769         if (IS_I830(dev) &&
1770             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771             !intel_num_dvo_pipes(dev)) {
1772                 I915_WRITE(DPLL(PIPE_B),
1773                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774                 I915_WRITE(DPLL(PIPE_A),
1775                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776         }
1777
1778         /* Don't disable pipe or pipe PLLs if needed */
1779         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781                 return;
1782
1783         /* Make sure the pipe isn't still relying on us */
1784         assert_pipe_disabled(dev_priv, pipe);
1785
1786         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787         POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792         u32 val;
1793
1794         /* Make sure the pipe isn't still relying on us */
1795         assert_pipe_disabled(dev_priv, pipe);
1796
1797         /*
1798          * Leave integrated clock source and reference clock enabled for pipe B.
1799          * The latter is needed for VGA hotplug / manual detection.
1800          */
1801         val = DPLL_VGA_MODE_DIS;
1802         if (pipe == PIPE_B)
1803                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804         I915_WRITE(DPLL(pipe), val);
1805         POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812         u32 val;
1813
1814         /* Make sure the pipe isn't still relying on us */
1815         assert_pipe_disabled(dev_priv, pipe);
1816
1817         /* Set PLL en = 0 */
1818         val = DPLL_SSC_REF_CLK_CHV |
1819                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820         if (pipe != PIPE_A)
1821                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822         I915_WRITE(DPLL(pipe), val);
1823         POSTING_READ(DPLL(pipe));
1824
1825         mutex_lock(&dev_priv->sb_lock);
1826
1827         /* Disable 10bit clock to display controller */
1828         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829         val &= ~DPIO_DCLKP_EN;
1830         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832         mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836                          struct intel_digital_port *dport,
1837                          unsigned int expected_mask)
1838 {
1839         u32 port_mask;
1840         int dpll_reg;
1841
1842         switch (dport->port) {
1843         case PORT_B:
1844                 port_mask = DPLL_PORTB_READY_MASK;
1845                 dpll_reg = DPLL(0);
1846                 break;
1847         case PORT_C:
1848                 port_mask = DPLL_PORTC_READY_MASK;
1849                 dpll_reg = DPLL(0);
1850                 expected_mask <<= 4;
1851                 break;
1852         case PORT_D:
1853                 port_mask = DPLL_PORTD_READY_MASK;
1854                 dpll_reg = DPIO_PHY_STATUS;
1855                 break;
1856         default:
1857                 BUG();
1858         }
1859
1860         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867         struct drm_device *dev = crtc->base.dev;
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871         if (WARN_ON(pll == NULL))
1872                 return;
1873
1874         WARN_ON(!pll->config.crtc_mask);
1875         if (pll->active == 0) {
1876                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877                 WARN_ON(pll->on);
1878                 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880                 pll->mode_set(dev_priv, pll);
1881         }
1882 }
1883
1884 /**
1885  * intel_enable_shared_dpll - enable PCH PLL
1886  * @dev_priv: i915 private structure
1887  * @pipe: pipe PLL to enable
1888  *
1889  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890  * drives the transcoder clock.
1891  */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894         struct drm_device *dev = crtc->base.dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898         if (WARN_ON(pll == NULL))
1899                 return;
1900
1901         if (WARN_ON(pll->config.crtc_mask == 0))
1902                 return;
1903
1904         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905                       pll->name, pll->active, pll->on,
1906                       crtc->base.base.id);
1907
1908         if (pll->active++) {
1909                 WARN_ON(!pll->on);
1910                 assert_shared_dpll_enabled(dev_priv, pll);
1911                 return;
1912         }
1913         WARN_ON(pll->on);
1914
1915         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918         pll->enable(dev_priv, pll);
1919         pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924         struct drm_device *dev = crtc->base.dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928         /* PCH only available on ILK+ */
1929         if (INTEL_INFO(dev)->gen < 5)
1930                 return;
1931
1932         if (pll == NULL)
1933                 return;
1934
1935         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936                 return;
1937
1938         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939                       pll->name, pll->active, pll->on,
1940                       crtc->base.base.id);
1941
1942         if (WARN_ON(pll->active == 0)) {
1943                 assert_shared_dpll_disabled(dev_priv, pll);
1944                 return;
1945         }
1946
1947         assert_shared_dpll_enabled(dev_priv, pll);
1948         WARN_ON(!pll->on);
1949         if (--pll->active)
1950                 return;
1951
1952         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953         pll->disable(dev_priv, pll);
1954         pll->on = false;
1955
1956         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960                                            enum pipe pipe)
1961 {
1962         struct drm_device *dev = dev_priv->dev;
1963         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965         uint32_t reg, val, pipeconf_val;
1966
1967         /* PCH only available on ILK+ */
1968         BUG_ON(!HAS_PCH_SPLIT(dev));
1969
1970         /* Make sure PCH DPLL is enabled */
1971         assert_shared_dpll_enabled(dev_priv,
1972                                    intel_crtc_to_shared_dpll(intel_crtc));
1973
1974         /* FDI must be feeding us bits for PCH ports */
1975         assert_fdi_tx_enabled(dev_priv, pipe);
1976         assert_fdi_rx_enabled(dev_priv, pipe);
1977
1978         if (HAS_PCH_CPT(dev)) {
1979                 /* Workaround: Set the timing override bit before enabling the
1980                  * pch transcoder. */
1981                 reg = TRANS_CHICKEN2(pipe);
1982                 val = I915_READ(reg);
1983                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984                 I915_WRITE(reg, val);
1985         }
1986
1987         reg = PCH_TRANSCONF(pipe);
1988         val = I915_READ(reg);
1989         pipeconf_val = I915_READ(PIPECONF(pipe));
1990
1991         if (HAS_PCH_IBX(dev_priv->dev)) {
1992                 /*
1993                  * Make the BPC in transcoder be consistent with
1994                  * that in pipeconf reg. For HDMI we must use 8bpc
1995                  * here for both 8bpc and 12bpc.
1996                  */
1997                 val &= ~PIPECONF_BPC_MASK;
1998                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1999                         val |= PIPECONF_8BPC;
2000                 else
2001                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2002         }
2003
2004         val &= ~TRANS_INTERLACE_MASK;
2005         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2006                 if (HAS_PCH_IBX(dev_priv->dev) &&
2007                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2008                         val |= TRANS_LEGACY_INTERLACED_ILK;
2009                 else
2010                         val |= TRANS_INTERLACED;
2011         else
2012                 val |= TRANS_PROGRESSIVE;
2013
2014         I915_WRITE(reg, val | TRANS_ENABLE);
2015         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2016                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2017 }
2018
2019 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2020                                       enum transcoder cpu_transcoder)
2021 {
2022         u32 val, pipeconf_val;
2023
2024         /* PCH only available on ILK+ */
2025         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2026
2027         /* FDI must be feeding us bits for PCH ports */
2028         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2029         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2030
2031         /* Workaround: set timing override bit. */
2032         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2033         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2034         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2035
2036         val = TRANS_ENABLE;
2037         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2038
2039         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2040             PIPECONF_INTERLACED_ILK)
2041                 val |= TRANS_INTERLACED;
2042         else
2043                 val |= TRANS_PROGRESSIVE;
2044
2045         I915_WRITE(LPT_TRANSCONF, val);
2046         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2047                 DRM_ERROR("Failed to enable PCH transcoder\n");
2048 }
2049
2050 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2051                                             enum pipe pipe)
2052 {
2053         struct drm_device *dev = dev_priv->dev;
2054         uint32_t reg, val;
2055
2056         /* FDI relies on the transcoder */
2057         assert_fdi_tx_disabled(dev_priv, pipe);
2058         assert_fdi_rx_disabled(dev_priv, pipe);
2059
2060         /* Ports must be off as well */
2061         assert_pch_ports_disabled(dev_priv, pipe);
2062
2063         reg = PCH_TRANSCONF(pipe);
2064         val = I915_READ(reg);
2065         val &= ~TRANS_ENABLE;
2066         I915_WRITE(reg, val);
2067         /* wait for PCH transcoder off, transcoder state */
2068         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2069                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2070
2071         if (!HAS_PCH_IBX(dev)) {
2072                 /* Workaround: Clear the timing override chicken bit again. */
2073                 reg = TRANS_CHICKEN2(pipe);
2074                 val = I915_READ(reg);
2075                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2076                 I915_WRITE(reg, val);
2077         }
2078 }
2079
2080 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2081 {
2082         u32 val;
2083
2084         val = I915_READ(LPT_TRANSCONF);
2085         val &= ~TRANS_ENABLE;
2086         I915_WRITE(LPT_TRANSCONF, val);
2087         /* wait for PCH transcoder off, transcoder state */
2088         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2089                 DRM_ERROR("Failed to disable PCH transcoder\n");
2090
2091         /* Workaround: clear timing override bit. */
2092         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2093         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2095 }
2096
2097 /**
2098  * intel_enable_pipe - enable a pipe, asserting requirements
2099  * @crtc: crtc responsible for the pipe
2100  *
2101  * Enable @crtc's pipe, making sure that various hardware specific requirements
2102  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2103  */
2104 static void intel_enable_pipe(struct intel_crtc *crtc)
2105 {
2106         struct drm_device *dev = crtc->base.dev;
2107         struct drm_i915_private *dev_priv = dev->dev_private;
2108         enum pipe pipe = crtc->pipe;
2109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2110                                                                       pipe);
2111         enum pipe pch_transcoder;
2112         int reg;
2113         u32 val;
2114
2115         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2116
2117         assert_planes_disabled(dev_priv, pipe);
2118         assert_cursor_disabled(dev_priv, pipe);
2119         assert_sprites_disabled(dev_priv, pipe);
2120
2121         if (HAS_PCH_LPT(dev_priv->dev))
2122                 pch_transcoder = TRANSCODER_A;
2123         else
2124                 pch_transcoder = pipe;
2125
2126         /*
2127          * A pipe without a PLL won't actually be able to drive bits from
2128          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2129          * need the check.
2130          */
2131         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2132                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2133                         assert_dsi_pll_enabled(dev_priv);
2134                 else
2135                         assert_pll_enabled(dev_priv, pipe);
2136         else {
2137                 if (crtc->config->has_pch_encoder) {
2138                         /* if driving the PCH, we need FDI enabled */
2139                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2140                         assert_fdi_tx_pll_enabled(dev_priv,
2141                                                   (enum pipe) cpu_transcoder);
2142                 }
2143                 /* FIXME: assert CPU port conditions for SNB+ */
2144         }
2145
2146         reg = PIPECONF(cpu_transcoder);
2147         val = I915_READ(reg);
2148         if (val & PIPECONF_ENABLE) {
2149                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2150                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2151                 return;
2152         }
2153
2154         I915_WRITE(reg, val | PIPECONF_ENABLE);
2155         POSTING_READ(reg);
2156 }
2157
2158 /**
2159  * intel_disable_pipe - disable a pipe, asserting requirements
2160  * @crtc: crtc whose pipes is to be disabled
2161  *
2162  * Disable the pipe of @crtc, making sure that various hardware
2163  * specific requirements are met, if applicable, e.g. plane
2164  * disabled, panel fitter off, etc.
2165  *
2166  * Will wait until the pipe has shut down before returning.
2167  */
2168 static void intel_disable_pipe(struct intel_crtc *crtc)
2169 {
2170         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2171         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2172         enum pipe pipe = crtc->pipe;
2173         int reg;
2174         u32 val;
2175
2176         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2177
2178         /*
2179          * Make sure planes won't keep trying to pump pixels to us,
2180          * or we might hang the display.
2181          */
2182         assert_planes_disabled(dev_priv, pipe);
2183         assert_cursor_disabled(dev_priv, pipe);
2184         assert_sprites_disabled(dev_priv, pipe);
2185
2186         reg = PIPECONF(cpu_transcoder);
2187         val = I915_READ(reg);
2188         if ((val & PIPECONF_ENABLE) == 0)
2189                 return;
2190
2191         /*
2192          * Double wide has implications for planes
2193          * so best keep it disabled when not needed.
2194          */
2195         if (crtc->config->double_wide)
2196                 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198         /* Don't disable pipe or pipe PLLs if needed */
2199         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2201                 val &= ~PIPECONF_ENABLE;
2202
2203         I915_WRITE(reg, val);
2204         if ((val & PIPECONF_ENABLE) == 0)
2205                 intel_wait_for_pipe_off(crtc);
2206 }
2207
2208 static bool need_vtd_wa(struct drm_device *dev)
2209 {
2210 #ifdef CONFIG_INTEL_IOMMU
2211         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2212                 return true;
2213 #endif
2214         return false;
2215 }
2216
2217 unsigned int
2218 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2219                   uint64_t fb_format_modifier, unsigned int plane)
2220 {
2221         unsigned int tile_height;
2222         uint32_t pixel_bytes;
2223
2224         switch (fb_format_modifier) {
2225         case DRM_FORMAT_MOD_NONE:
2226                 tile_height = 1;
2227                 break;
2228         case I915_FORMAT_MOD_X_TILED:
2229                 tile_height = IS_GEN2(dev) ? 16 : 8;
2230                 break;
2231         case I915_FORMAT_MOD_Y_TILED:
2232                 tile_height = 32;
2233                 break;
2234         case I915_FORMAT_MOD_Yf_TILED:
2235                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2236                 switch (pixel_bytes) {
2237                 default:
2238                 case 1:
2239                         tile_height = 64;
2240                         break;
2241                 case 2:
2242                 case 4:
2243                         tile_height = 32;
2244                         break;
2245                 case 8:
2246                         tile_height = 16;
2247                         break;
2248                 case 16:
2249                         WARN_ONCE(1,
2250                                   "128-bit pixels are not supported for display!");
2251                         tile_height = 16;
2252                         break;
2253                 }
2254                 break;
2255         default:
2256                 MISSING_CASE(fb_format_modifier);
2257                 tile_height = 1;
2258                 break;
2259         }
2260
2261         return tile_height;
2262 }
2263
2264 unsigned int
2265 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2266                       uint32_t pixel_format, uint64_t fb_format_modifier)
2267 {
2268         return ALIGN(height, intel_tile_height(dev, pixel_format,
2269                                                fb_format_modifier, 0));
2270 }
2271
2272 static int
2273 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2274                         const struct drm_plane_state *plane_state)
2275 {
2276         struct intel_rotation_info *info = &view->rotation_info;
2277         unsigned int tile_height, tile_pitch;
2278
2279         *view = i915_ggtt_view_normal;
2280
2281         if (!plane_state)
2282                 return 0;
2283
2284         if (!intel_rotation_90_or_270(plane_state->rotation))
2285                 return 0;
2286
2287         *view = i915_ggtt_view_rotated;
2288
2289         info->height = fb->height;
2290         info->pixel_format = fb->pixel_format;
2291         info->pitch = fb->pitches[0];
2292         info->uv_offset = fb->offsets[1];
2293         info->fb_modifier = fb->modifier[0];
2294
2295         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2296                                         fb->modifier[0], 0);
2297         tile_pitch = PAGE_SIZE / tile_height;
2298         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2300         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2301
2302         if (info->pixel_format == DRM_FORMAT_NV12) {
2303                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304                                                 fb->modifier[0], 1);
2305                 tile_pitch = PAGE_SIZE / tile_height;
2306                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2307                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2308                                                      tile_height);
2309                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2310                                 PAGE_SIZE;
2311         }
2312
2313         return 0;
2314 }
2315
2316 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2317 {
2318         if (INTEL_INFO(dev_priv)->gen >= 9)
2319                 return 256 * 1024;
2320         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2321                  IS_VALLEYVIEW(dev_priv))
2322                 return 128 * 1024;
2323         else if (INTEL_INFO(dev_priv)->gen >= 4)
2324                 return 4 * 1024;
2325         else
2326                 return 0;
2327 }
2328
2329 int
2330 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2331                            struct drm_framebuffer *fb,
2332                            const struct drm_plane_state *plane_state,
2333                            struct intel_engine_cs *pipelined,
2334                            struct drm_i915_gem_request **pipelined_request)
2335 {
2336         struct drm_device *dev = fb->dev;
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2339         struct i915_ggtt_view view;
2340         u32 alignment;
2341         int ret;
2342
2343         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2344
2345         switch (fb->modifier[0]) {
2346         case DRM_FORMAT_MOD_NONE:
2347                 alignment = intel_linear_alignment(dev_priv);
2348                 break;
2349         case I915_FORMAT_MOD_X_TILED:
2350                 if (INTEL_INFO(dev)->gen >= 9)
2351                         alignment = 256 * 1024;
2352                 else {
2353                         /* pin() will align the object as required by fence */
2354                         alignment = 0;
2355                 }
2356                 break;
2357         case I915_FORMAT_MOD_Y_TILED:
2358         case I915_FORMAT_MOD_Yf_TILED:
2359                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360                           "Y tiling bo slipped through, driver bug!\n"))
2361                         return -EINVAL;
2362                 alignment = 1 * 1024 * 1024;
2363                 break;
2364         default:
2365                 MISSING_CASE(fb->modifier[0]);
2366                 return -EINVAL;
2367         }
2368
2369         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370         if (ret)
2371                 return ret;
2372
2373         /* Note that the w/a also requires 64 PTE of padding following the
2374          * bo. We currently fill all unused PTE with the shadow page and so
2375          * we should always have valid PTE following the scanout preventing
2376          * the VT-d warning.
2377          */
2378         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379                 alignment = 256 * 1024;
2380
2381         /*
2382          * Global gtt pte registers are special registers which actually forward
2383          * writes to a chunk of system memory. Which means that there is no risk
2384          * that the register values disappear as soon as we call
2385          * intel_runtime_pm_put(), so it is correct to wrap only the
2386          * pin/unpin/fence and not more.
2387          */
2388         intel_runtime_pm_get(dev_priv);
2389
2390         dev_priv->mm.interruptible = false;
2391         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2392                                                    pipelined_request, &view);
2393         if (ret)
2394                 goto err_interruptible;
2395
2396         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397          * fence, whereas 965+ only requires a fence if using
2398          * framebuffer compression.  For simplicity, we always install
2399          * a fence as the cost is not that onerous.
2400          */
2401         if (view.type == I915_GGTT_VIEW_NORMAL) {
2402                 ret = i915_gem_object_get_fence(obj);
2403                 if (ret == -EDEADLK) {
2404                         /*
2405                          * -EDEADLK means there are no free fences
2406                          * no pending flips.
2407                          *
2408                          * This is propagated to atomic, but it uses
2409                          * -EDEADLK to force a locking recovery, so
2410                          * change the returned error to -EBUSY.
2411                          */
2412                         ret = -EBUSY;
2413                         goto err_unpin;
2414                 } else if (ret)
2415                         goto err_unpin;
2416
2417                 i915_gem_object_pin_fence(obj);
2418         }
2419
2420         dev_priv->mm.interruptible = true;
2421         intel_runtime_pm_put(dev_priv);
2422         return 0;
2423
2424 err_unpin:
2425         i915_gem_object_unpin_from_display_plane(obj, &view);
2426 err_interruptible:
2427         dev_priv->mm.interruptible = true;
2428         intel_runtime_pm_put(dev_priv);
2429         return ret;
2430 }
2431
2432 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2433                                const struct drm_plane_state *plane_state)
2434 {
2435         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2436         struct i915_ggtt_view view;
2437         int ret;
2438
2439         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2440
2441         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2442         WARN_ONCE(ret, "Couldn't get view from plane state!");
2443
2444         if (view.type == I915_GGTT_VIEW_NORMAL)
2445                 i915_gem_object_unpin_fence(obj);
2446
2447         i915_gem_object_unpin_from_display_plane(obj, &view);
2448 }
2449
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451  * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2453                                              int *x, int *y,
2454                                              unsigned int tiling_mode,
2455                                              unsigned int cpp,
2456                                              unsigned int pitch)
2457 {
2458         if (tiling_mode != I915_TILING_NONE) {
2459                 unsigned int tile_rows, tiles;
2460
2461                 tile_rows = *y / 8;
2462                 *y %= 8;
2463
2464                 tiles = *x / (512/cpp);
2465                 *x %= 512/cpp;
2466
2467                 return tile_rows * pitch * 8 + tiles * 4096;
2468         } else {
2469                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2470                 unsigned int offset;
2471
2472                 offset = *y * pitch + *x * cpp;
2473                 *y = (offset & alignment) / pitch;
2474                 *x = ((offset & alignment) - *y * pitch) / cpp;
2475                 return offset & ~alignment;
2476         }
2477 }
2478
2479 static int i9xx_format_to_fourcc(int format)
2480 {
2481         switch (format) {
2482         case DISPPLANE_8BPP:
2483                 return DRM_FORMAT_C8;
2484         case DISPPLANE_BGRX555:
2485                 return DRM_FORMAT_XRGB1555;
2486         case DISPPLANE_BGRX565:
2487                 return DRM_FORMAT_RGB565;
2488         default:
2489         case DISPPLANE_BGRX888:
2490                 return DRM_FORMAT_XRGB8888;
2491         case DISPPLANE_RGBX888:
2492                 return DRM_FORMAT_XBGR8888;
2493         case DISPPLANE_BGRX101010:
2494                 return DRM_FORMAT_XRGB2101010;
2495         case DISPPLANE_RGBX101010:
2496                 return DRM_FORMAT_XBGR2101010;
2497         }
2498 }
2499
2500 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2501 {
2502         switch (format) {
2503         case PLANE_CTL_FORMAT_RGB_565:
2504                 return DRM_FORMAT_RGB565;
2505         default:
2506         case PLANE_CTL_FORMAT_XRGB_8888:
2507                 if (rgb_order) {
2508                         if (alpha)
2509                                 return DRM_FORMAT_ABGR8888;
2510                         else
2511                                 return DRM_FORMAT_XBGR8888;
2512                 } else {
2513                         if (alpha)
2514                                 return DRM_FORMAT_ARGB8888;
2515                         else
2516                                 return DRM_FORMAT_XRGB8888;
2517                 }
2518         case PLANE_CTL_FORMAT_XRGB_2101010:
2519                 if (rgb_order)
2520                         return DRM_FORMAT_XBGR2101010;
2521                 else
2522                         return DRM_FORMAT_XRGB2101010;
2523         }
2524 }
2525
2526 static bool
2527 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528                               struct intel_initial_plane_config *plane_config)
2529 {
2530         struct drm_device *dev = crtc->base.dev;
2531         struct drm_i915_private *dev_priv = to_i915(dev);
2532         struct drm_i915_gem_object *obj = NULL;
2533         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2534         struct drm_framebuffer *fb = &plane_config->fb->base;
2535         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2536         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2537                                     PAGE_SIZE);
2538
2539         size_aligned -= base_aligned;
2540
2541         if (plane_config->size == 0)
2542                 return false;
2543
2544         /* If the FB is too big, just don't use it since fbdev is not very
2545          * important and we should probably use that space with FBC or other
2546          * features. */
2547         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2548                 return false;
2549
2550         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2551                                                              base_aligned,
2552                                                              base_aligned,
2553                                                              size_aligned);
2554         if (!obj)
2555                 return false;
2556
2557         obj->tiling_mode = plane_config->tiling;
2558         if (obj->tiling_mode == I915_TILING_X)
2559                 obj->stride = fb->pitches[0];
2560
2561         mode_cmd.pixel_format = fb->pixel_format;
2562         mode_cmd.width = fb->width;
2563         mode_cmd.height = fb->height;
2564         mode_cmd.pitches[0] = fb->pitches[0];
2565         mode_cmd.modifier[0] = fb->modifier[0];
2566         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2567
2568         mutex_lock(&dev->struct_mutex);
2569         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2570                                    &mode_cmd, obj)) {
2571                 DRM_DEBUG_KMS("intel fb init failed\n");
2572                 goto out_unref_obj;
2573         }
2574         mutex_unlock(&dev->struct_mutex);
2575
2576         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2577         return true;
2578
2579 out_unref_obj:
2580         drm_gem_object_unreference(&obj->base);
2581         mutex_unlock(&dev->struct_mutex);
2582         return false;
2583 }
2584
2585 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2586 static void
2587 update_state_fb(struct drm_plane *plane)
2588 {
2589         if (plane->fb == plane->state->fb)
2590                 return;
2591
2592         if (plane->state->fb)
2593                 drm_framebuffer_unreference(plane->state->fb);
2594         plane->state->fb = plane->fb;
2595         if (plane->state->fb)
2596                 drm_framebuffer_reference(plane->state->fb);
2597 }
2598
2599 static void
2600 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2601                              struct intel_initial_plane_config *plane_config)
2602 {
2603         struct drm_device *dev = intel_crtc->base.dev;
2604         struct drm_i915_private *dev_priv = dev->dev_private;
2605         struct drm_crtc *c;
2606         struct intel_crtc *i;
2607         struct drm_i915_gem_object *obj;
2608         struct drm_plane *primary = intel_crtc->base.primary;
2609         struct drm_plane_state *plane_state = primary->state;
2610         struct drm_framebuffer *fb;
2611
2612         if (!plane_config->fb)
2613                 return;
2614
2615         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2616                 fb = &plane_config->fb->base;
2617                 goto valid_fb;
2618         }
2619
2620         kfree(plane_config->fb);
2621
2622         /*
2623          * Failed to alloc the obj, check to see if we should share
2624          * an fb with another CRTC instead
2625          */
2626         for_each_crtc(dev, c) {
2627                 i = to_intel_crtc(c);
2628
2629                 if (c == &intel_crtc->base)
2630                         continue;
2631
2632                 if (!i->active)
2633                         continue;
2634
2635                 fb = c->primary->fb;
2636                 if (!fb)
2637                         continue;
2638
2639                 obj = intel_fb_obj(fb);
2640                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2641                         drm_framebuffer_reference(fb);
2642                         goto valid_fb;
2643                 }
2644         }
2645
2646         return;
2647
2648 valid_fb:
2649         plane_state->src_x = 0;
2650         plane_state->src_y = 0;
2651         plane_state->src_w = fb->width << 16;
2652         plane_state->src_h = fb->height << 16;
2653
2654         plane_state->crtc_x = 0;
2655         plane_state->crtc_y = 0;
2656         plane_state->crtc_w = fb->width;
2657         plane_state->crtc_h = fb->height;
2658
2659         obj = intel_fb_obj(fb);
2660         if (obj->tiling_mode != I915_TILING_NONE)
2661                 dev_priv->preserve_bios_swizzle = true;
2662
2663         drm_framebuffer_reference(fb);
2664         primary->fb = primary->state->fb = fb;
2665         primary->crtc = primary->state->crtc = &intel_crtc->base;
2666         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2667         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2668 }
2669
2670 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2671                                       struct drm_framebuffer *fb,
2672                                       int x, int y)
2673 {
2674         struct drm_device *dev = crtc->dev;
2675         struct drm_i915_private *dev_priv = dev->dev_private;
2676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2677         struct drm_plane *primary = crtc->primary;
2678         bool visible = to_intel_plane_state(primary->state)->visible;
2679         struct drm_i915_gem_object *obj;
2680         int plane = intel_crtc->plane;
2681         unsigned long linear_offset;
2682         u32 dspcntr;
2683         u32 reg = DSPCNTR(plane);
2684         int pixel_size;
2685
2686         if (!visible || !fb) {
2687                 I915_WRITE(reg, 0);
2688                 if (INTEL_INFO(dev)->gen >= 4)
2689                         I915_WRITE(DSPSURF(plane), 0);
2690                 else
2691                         I915_WRITE(DSPADDR(plane), 0);
2692                 POSTING_READ(reg);
2693                 return;
2694         }
2695
2696         obj = intel_fb_obj(fb);
2697         if (WARN_ON(obj == NULL))
2698                 return;
2699
2700         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2701
2702         dspcntr = DISPPLANE_GAMMA_ENABLE;
2703
2704         dspcntr |= DISPLAY_PLANE_ENABLE;
2705
2706         if (INTEL_INFO(dev)->gen < 4) {
2707                 if (intel_crtc->pipe == PIPE_B)
2708                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2709
2710                 /* pipesrc and dspsize control the size that is scaled from,
2711                  * which should always be the user's requested size.
2712                  */
2713                 I915_WRITE(DSPSIZE(plane),
2714                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2715                            (intel_crtc->config->pipe_src_w - 1));
2716                 I915_WRITE(DSPPOS(plane), 0);
2717         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2718                 I915_WRITE(PRIMSIZE(plane),
2719                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2720                            (intel_crtc->config->pipe_src_w - 1));
2721                 I915_WRITE(PRIMPOS(plane), 0);
2722                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2723         }
2724
2725         switch (fb->pixel_format) {
2726         case DRM_FORMAT_C8:
2727                 dspcntr |= DISPPLANE_8BPP;
2728                 break;
2729         case DRM_FORMAT_XRGB1555:
2730                 dspcntr |= DISPPLANE_BGRX555;
2731                 break;
2732         case DRM_FORMAT_RGB565:
2733                 dspcntr |= DISPPLANE_BGRX565;
2734                 break;
2735         case DRM_FORMAT_XRGB8888:
2736                 dspcntr |= DISPPLANE_BGRX888;
2737                 break;
2738         case DRM_FORMAT_XBGR8888:
2739                 dspcntr |= DISPPLANE_RGBX888;
2740                 break;
2741         case DRM_FORMAT_XRGB2101010:
2742                 dspcntr |= DISPPLANE_BGRX101010;
2743                 break;
2744         case DRM_FORMAT_XBGR2101010:
2745                 dspcntr |= DISPPLANE_RGBX101010;
2746                 break;
2747         default:
2748                 BUG();
2749         }
2750
2751         if (INTEL_INFO(dev)->gen >= 4 &&
2752             obj->tiling_mode != I915_TILING_NONE)
2753                 dspcntr |= DISPPLANE_TILED;
2754
2755         if (IS_G4X(dev))
2756                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2757
2758         linear_offset = y * fb->pitches[0] + x * pixel_size;
2759
2760         if (INTEL_INFO(dev)->gen >= 4) {
2761                 intel_crtc->dspaddr_offset =
2762                         intel_gen4_compute_page_offset(dev_priv,
2763                                                        &x, &y, obj->tiling_mode,
2764                                                        pixel_size,
2765                                                        fb->pitches[0]);
2766                 linear_offset -= intel_crtc->dspaddr_offset;
2767         } else {
2768                 intel_crtc->dspaddr_offset = linear_offset;
2769         }
2770
2771         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2772                 dspcntr |= DISPPLANE_ROTATE_180;
2773
2774                 x += (intel_crtc->config->pipe_src_w - 1);
2775                 y += (intel_crtc->config->pipe_src_h - 1);
2776
2777                 /* Finding the last pixel of the last line of the display
2778                 data and adding to linear_offset*/
2779                 linear_offset +=
2780                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2781                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2782         }
2783
2784         intel_crtc->adjusted_x = x;
2785         intel_crtc->adjusted_y = y;
2786
2787         I915_WRITE(reg, dspcntr);
2788
2789         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2790         if (INTEL_INFO(dev)->gen >= 4) {
2791                 I915_WRITE(DSPSURF(plane),
2792                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2793                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2794                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2795         } else
2796                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2797         POSTING_READ(reg);
2798 }
2799
2800 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2801                                           struct drm_framebuffer *fb,
2802                                           int x, int y)
2803 {
2804         struct drm_device *dev = crtc->dev;
2805         struct drm_i915_private *dev_priv = dev->dev_private;
2806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807         struct drm_plane *primary = crtc->primary;
2808         bool visible = to_intel_plane_state(primary->state)->visible;
2809         struct drm_i915_gem_object *obj;
2810         int plane = intel_crtc->plane;
2811         unsigned long linear_offset;
2812         u32 dspcntr;
2813         u32 reg = DSPCNTR(plane);
2814         int pixel_size;
2815
2816         if (!visible || !fb) {
2817                 I915_WRITE(reg, 0);
2818                 I915_WRITE(DSPSURF(plane), 0);
2819                 POSTING_READ(reg);
2820                 return;
2821         }
2822
2823         obj = intel_fb_obj(fb);
2824         if (WARN_ON(obj == NULL))
2825                 return;
2826
2827         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2828
2829         dspcntr = DISPPLANE_GAMMA_ENABLE;
2830
2831         dspcntr |= DISPLAY_PLANE_ENABLE;
2832
2833         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2834                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2835
2836         switch (fb->pixel_format) {
2837         case DRM_FORMAT_C8:
2838                 dspcntr |= DISPPLANE_8BPP;
2839                 break;
2840         case DRM_FORMAT_RGB565:
2841                 dspcntr |= DISPPLANE_BGRX565;
2842                 break;
2843         case DRM_FORMAT_XRGB8888:
2844                 dspcntr |= DISPPLANE_BGRX888;
2845                 break;
2846         case DRM_FORMAT_XBGR8888:
2847                 dspcntr |= DISPPLANE_RGBX888;
2848                 break;
2849         case DRM_FORMAT_XRGB2101010:
2850                 dspcntr |= DISPPLANE_BGRX101010;
2851                 break;
2852         case DRM_FORMAT_XBGR2101010:
2853                 dspcntr |= DISPPLANE_RGBX101010;
2854                 break;
2855         default:
2856                 BUG();
2857         }
2858
2859         if (obj->tiling_mode != I915_TILING_NONE)
2860                 dspcntr |= DISPPLANE_TILED;
2861
2862         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2863                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2864
2865         linear_offset = y * fb->pitches[0] + x * pixel_size;
2866         intel_crtc->dspaddr_offset =
2867                 intel_gen4_compute_page_offset(dev_priv,
2868                                                &x, &y, obj->tiling_mode,
2869                                                pixel_size,
2870                                                fb->pitches[0]);
2871         linear_offset -= intel_crtc->dspaddr_offset;
2872         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2873                 dspcntr |= DISPPLANE_ROTATE_180;
2874
2875                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2876                         x += (intel_crtc->config->pipe_src_w - 1);
2877                         y += (intel_crtc->config->pipe_src_h - 1);
2878
2879                         /* Finding the last pixel of the last line of the display
2880                         data and adding to linear_offset*/
2881                         linear_offset +=
2882                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2883                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2884                 }
2885         }
2886
2887         intel_crtc->adjusted_x = x;
2888         intel_crtc->adjusted_y = y;
2889
2890         I915_WRITE(reg, dspcntr);
2891
2892         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2893         I915_WRITE(DSPSURF(plane),
2894                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2895         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2896                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2897         } else {
2898                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2899                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2900         }
2901         POSTING_READ(reg);
2902 }
2903
2904 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2905                               uint32_t pixel_format)
2906 {
2907         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2908
2909         /*
2910          * The stride is either expressed as a multiple of 64 bytes
2911          * chunks for linear buffers or in number of tiles for tiled
2912          * buffers.
2913          */
2914         switch (fb_modifier) {
2915         case DRM_FORMAT_MOD_NONE:
2916                 return 64;
2917         case I915_FORMAT_MOD_X_TILED:
2918                 if (INTEL_INFO(dev)->gen == 2)
2919                         return 128;
2920                 return 512;
2921         case I915_FORMAT_MOD_Y_TILED:
2922                 /* No need to check for old gens and Y tiling since this is
2923                  * about the display engine and those will be blocked before
2924                  * we get here.
2925                  */
2926                 return 128;
2927         case I915_FORMAT_MOD_Yf_TILED:
2928                 if (bits_per_pixel == 8)
2929                         return 64;
2930                 else
2931                         return 128;
2932         default:
2933                 MISSING_CASE(fb_modifier);
2934                 return 64;
2935         }
2936 }
2937
2938 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2939                                      struct drm_i915_gem_object *obj,
2940                                      unsigned int plane)
2941 {
2942         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2943         struct i915_vma *vma;
2944         unsigned char *offset;
2945
2946         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2947                 view = &i915_ggtt_view_rotated;
2948
2949         vma = i915_gem_obj_to_ggtt_view(obj, view);
2950         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2951                 view->type))
2952                 return -1;
2953
2954         offset = (unsigned char *)vma->node.start;
2955
2956         if (plane == 1) {
2957                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2958                           PAGE_SIZE;
2959         }
2960
2961         return (unsigned long)offset;
2962 }
2963
2964 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2965 {
2966         struct drm_device *dev = intel_crtc->base.dev;
2967         struct drm_i915_private *dev_priv = dev->dev_private;
2968
2969         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2970         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2971         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2972 }
2973
2974 /*
2975  * This function detaches (aka. unbinds) unused scalers in hardware
2976  */
2977 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2978 {
2979         struct intel_crtc_scaler_state *scaler_state;
2980         int i;
2981
2982         scaler_state = &intel_crtc->config->scaler_state;
2983
2984         /* loop through and disable scalers that aren't in use */
2985         for (i = 0; i < intel_crtc->num_scalers; i++) {
2986                 if (!scaler_state->scalers[i].in_use)
2987                         skl_detach_scaler(intel_crtc, i);
2988         }
2989 }
2990
2991 u32 skl_plane_ctl_format(uint32_t pixel_format)
2992 {
2993         switch (pixel_format) {
2994         case DRM_FORMAT_C8:
2995                 return PLANE_CTL_FORMAT_INDEXED;
2996         case DRM_FORMAT_RGB565:
2997                 return PLANE_CTL_FORMAT_RGB_565;
2998         case DRM_FORMAT_XBGR8888:
2999                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3000         case DRM_FORMAT_XRGB8888:
3001                 return PLANE_CTL_FORMAT_XRGB_8888;
3002         /*
3003          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3004          * to be already pre-multiplied. We need to add a knob (or a different
3005          * DRM_FORMAT) for user-space to configure that.
3006          */
3007         case DRM_FORMAT_ABGR8888:
3008                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3009                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3010         case DRM_FORMAT_ARGB8888:
3011                 return PLANE_CTL_FORMAT_XRGB_8888 |
3012                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3013         case DRM_FORMAT_XRGB2101010:
3014                 return PLANE_CTL_FORMAT_XRGB_2101010;
3015         case DRM_FORMAT_XBGR2101010:
3016                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3017         case DRM_FORMAT_YUYV:
3018                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3019         case DRM_FORMAT_YVYU:
3020                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3021         case DRM_FORMAT_UYVY:
3022                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3023         case DRM_FORMAT_VYUY:
3024                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3025         default:
3026                 MISSING_CASE(pixel_format);
3027         }
3028
3029         return 0;
3030 }
3031
3032 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3033 {
3034         switch (fb_modifier) {
3035         case DRM_FORMAT_MOD_NONE:
3036                 break;
3037         case I915_FORMAT_MOD_X_TILED:
3038                 return PLANE_CTL_TILED_X;
3039         case I915_FORMAT_MOD_Y_TILED:
3040                 return PLANE_CTL_TILED_Y;
3041         case I915_FORMAT_MOD_Yf_TILED:
3042                 return PLANE_CTL_TILED_YF;
3043         default:
3044                 MISSING_CASE(fb_modifier);
3045         }
3046
3047         return 0;
3048 }
3049
3050 u32 skl_plane_ctl_rotation(unsigned int rotation)
3051 {
3052         switch (rotation) {
3053         case BIT(DRM_ROTATE_0):
3054                 break;
3055         /*
3056          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3057          * while i915 HW rotation is clockwise, thats why this swapping.
3058          */
3059         case BIT(DRM_ROTATE_90):
3060                 return PLANE_CTL_ROTATE_270;
3061         case BIT(DRM_ROTATE_180):
3062                 return PLANE_CTL_ROTATE_180;
3063         case BIT(DRM_ROTATE_270):
3064                 return PLANE_CTL_ROTATE_90;
3065         default:
3066                 MISSING_CASE(rotation);
3067         }
3068
3069         return 0;
3070 }
3071
3072 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3073                                          struct drm_framebuffer *fb,
3074                                          int x, int y)
3075 {
3076         struct drm_device *dev = crtc->dev;
3077         struct drm_i915_private *dev_priv = dev->dev_private;
3078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3079         struct drm_plane *plane = crtc->primary;
3080         bool visible = to_intel_plane_state(plane->state)->visible;
3081         struct drm_i915_gem_object *obj;
3082         int pipe = intel_crtc->pipe;
3083         u32 plane_ctl, stride_div, stride;
3084         u32 tile_height, plane_offset, plane_size;
3085         unsigned int rotation;
3086         int x_offset, y_offset;
3087         unsigned long surf_addr;
3088         struct intel_crtc_state *crtc_state = intel_crtc->config;
3089         struct intel_plane_state *plane_state;
3090         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3091         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3092         int scaler_id = -1;
3093
3094         plane_state = to_intel_plane_state(plane->state);
3095
3096         if (!visible || !fb) {
3097                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3098                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3099                 POSTING_READ(PLANE_CTL(pipe, 0));
3100                 return;
3101         }
3102
3103         plane_ctl = PLANE_CTL_ENABLE |
3104                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3105                     PLANE_CTL_PIPE_CSC_ENABLE;
3106
3107         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3108         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3109         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3110
3111         rotation = plane->state->rotation;
3112         plane_ctl |= skl_plane_ctl_rotation(rotation);
3113
3114         obj = intel_fb_obj(fb);
3115         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3116                                                fb->pixel_format);
3117         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3118
3119         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3120
3121         scaler_id = plane_state->scaler_id;
3122         src_x = plane_state->src.x1 >> 16;
3123         src_y = plane_state->src.y1 >> 16;
3124         src_w = drm_rect_width(&plane_state->src) >> 16;
3125         src_h = drm_rect_height(&plane_state->src) >> 16;
3126         dst_x = plane_state->dst.x1;
3127         dst_y = plane_state->dst.y1;
3128         dst_w = drm_rect_width(&plane_state->dst);
3129         dst_h = drm_rect_height(&plane_state->dst);
3130
3131         WARN_ON(x != src_x || y != src_y);
3132
3133         if (intel_rotation_90_or_270(rotation)) {
3134                 /* stride = Surface height in tiles */
3135                 tile_height = intel_tile_height(dev, fb->pixel_format,
3136                                                 fb->modifier[0], 0);
3137                 stride = DIV_ROUND_UP(fb->height, tile_height);
3138                 x_offset = stride * tile_height - y - src_h;
3139                 y_offset = x;
3140                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3141         } else {
3142                 stride = fb->pitches[0] / stride_div;
3143                 x_offset = x;
3144                 y_offset = y;
3145                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3146         }
3147         plane_offset = y_offset << 16 | x_offset;
3148
3149         intel_crtc->adjusted_x = x_offset;
3150         intel_crtc->adjusted_y = y_offset;
3151
3152         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3153         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3154         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3155         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3156
3157         if (scaler_id >= 0) {
3158                 uint32_t ps_ctrl = 0;
3159
3160                 WARN_ON(!dst_w || !dst_h);
3161                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3162                         crtc_state->scaler_state.scalers[scaler_id].mode;
3163                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3164                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3165                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3166                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3167                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3168         } else {
3169                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3170         }
3171
3172         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3173
3174         POSTING_READ(PLANE_SURF(pipe, 0));
3175 }
3176
3177 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3178 static int
3179 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3180                            int x, int y, enum mode_set_atomic state)
3181 {
3182         struct drm_device *dev = crtc->dev;
3183         struct drm_i915_private *dev_priv = dev->dev_private;
3184
3185         if (dev_priv->fbc.disable_fbc)
3186                 dev_priv->fbc.disable_fbc(dev_priv);
3187
3188         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3189
3190         return 0;
3191 }
3192
3193 static void intel_complete_page_flips(struct drm_device *dev)
3194 {
3195         struct drm_crtc *crtc;
3196
3197         for_each_crtc(dev, crtc) {
3198                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3199                 enum plane plane = intel_crtc->plane;
3200
3201                 intel_prepare_page_flip(dev, plane);
3202                 intel_finish_page_flip_plane(dev, plane);
3203         }
3204 }
3205
3206 static void intel_update_primary_planes(struct drm_device *dev)
3207 {
3208         struct drm_crtc *crtc;
3209
3210         for_each_crtc(dev, crtc) {
3211                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3212                 struct intel_plane_state *plane_state;
3213
3214                 drm_modeset_lock_crtc(crtc, &plane->base);
3215
3216                 plane_state = to_intel_plane_state(plane->base.state);
3217
3218                 if (plane_state->base.fb)
3219                         plane->commit_plane(&plane->base, plane_state);
3220
3221                 drm_modeset_unlock_crtc(crtc);
3222         }
3223 }
3224
3225 void intel_prepare_reset(struct drm_device *dev)
3226 {
3227         /* no reset support for gen2 */
3228         if (IS_GEN2(dev))
3229                 return;
3230
3231         /* reset doesn't touch the display */
3232         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3233                 return;
3234
3235         drm_modeset_lock_all(dev);
3236         /*
3237          * Disabling the crtcs gracefully seems nicer. Also the
3238          * g33 docs say we should at least disable all the planes.
3239          */
3240         intel_display_suspend(dev);
3241 }
3242
3243 void intel_finish_reset(struct drm_device *dev)
3244 {
3245         struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247         /*
3248          * Flips in the rings will be nuked by the reset,
3249          * so complete all pending flips so that user space
3250          * will get its events and not get stuck.
3251          */
3252         intel_complete_page_flips(dev);
3253
3254         /* no reset support for gen2 */
3255         if (IS_GEN2(dev))
3256                 return;
3257
3258         /* reset doesn't touch the display */
3259         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3260                 /*
3261                  * Flips in the rings have been nuked by the reset,
3262                  * so update the base address of all primary
3263                  * planes to the the last fb to make sure we're
3264                  * showing the correct fb after a reset.
3265                  *
3266                  * FIXME: Atomic will make this obsolete since we won't schedule
3267                  * CS-based flips (which might get lost in gpu resets) any more.
3268                  */
3269                 intel_update_primary_planes(dev);
3270                 return;
3271         }
3272
3273         /*
3274          * The display has been reset as well,
3275          * so need a full re-initialization.
3276          */
3277         intel_runtime_pm_disable_interrupts(dev_priv);
3278         intel_runtime_pm_enable_interrupts(dev_priv);
3279
3280         intel_modeset_init_hw(dev);
3281
3282         spin_lock_irq(&dev_priv->irq_lock);
3283         if (dev_priv->display.hpd_irq_setup)
3284                 dev_priv->display.hpd_irq_setup(dev);
3285         spin_unlock_irq(&dev_priv->irq_lock);
3286
3287         intel_display_resume(dev);
3288
3289         intel_hpd_init(dev_priv);
3290
3291         drm_modeset_unlock_all(dev);
3292 }
3293
3294 static void
3295 intel_finish_fb(struct drm_framebuffer *old_fb)
3296 {
3297         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3298         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3299         bool was_interruptible = dev_priv->mm.interruptible;
3300         int ret;
3301
3302         /* Big Hammer, we also need to ensure that any pending
3303          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3304          * current scanout is retired before unpinning the old
3305          * framebuffer. Note that we rely on userspace rendering
3306          * into the buffer attached to the pipe they are waiting
3307          * on. If not, userspace generates a GPU hang with IPEHR
3308          * point to the MI_WAIT_FOR_EVENT.
3309          *
3310          * This should only fail upon a hung GPU, in which case we
3311          * can safely continue.
3312          */
3313         dev_priv->mm.interruptible = false;
3314         ret = i915_gem_object_wait_rendering(obj, true);
3315         dev_priv->mm.interruptible = was_interruptible;
3316
3317         WARN_ON(ret);
3318 }
3319
3320 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3321 {
3322         struct drm_device *dev = crtc->dev;
3323         struct drm_i915_private *dev_priv = dev->dev_private;
3324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3325         bool pending;
3326
3327         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3328             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3329                 return false;
3330
3331         spin_lock_irq(&dev->event_lock);
3332         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3333         spin_unlock_irq(&dev->event_lock);
3334
3335         return pending;
3336 }
3337
3338 static void intel_update_pipe_config(struct intel_crtc *crtc,
3339                                      struct intel_crtc_state *old_crtc_state)
3340 {
3341         struct drm_device *dev = crtc->base.dev;
3342         struct drm_i915_private *dev_priv = dev->dev_private;
3343         struct intel_crtc_state *pipe_config =
3344                 to_intel_crtc_state(crtc->base.state);
3345
3346         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3347         crtc->base.mode = crtc->base.state->mode;
3348
3349         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3350                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3351                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3352
3353         if (HAS_DDI(dev))
3354                 intel_set_pipe_csc(&crtc->base);
3355
3356         /*
3357          * Update pipe size and adjust fitter if needed: the reason for this is
3358          * that in compute_mode_changes we check the native mode (not the pfit
3359          * mode) to see if we can flip rather than do a full mode set. In the
3360          * fastboot case, we'll flip, but if we don't update the pipesrc and
3361          * pfit state, we'll end up with a big fb scanned out into the wrong
3362          * sized surface.
3363          */
3364
3365         I915_WRITE(PIPESRC(crtc->pipe),
3366                    ((pipe_config->pipe_src_w - 1) << 16) |
3367                    (pipe_config->pipe_src_h - 1));
3368
3369         /* on skylake this is done by detaching scalers */
3370         if (INTEL_INFO(dev)->gen >= 9) {
3371                 skl_detach_scalers(crtc);
3372
3373                 if (pipe_config->pch_pfit.enabled)
3374                         skylake_pfit_enable(crtc);
3375         } else if (HAS_PCH_SPLIT(dev)) {
3376                 if (pipe_config->pch_pfit.enabled)
3377                         ironlake_pfit_enable(crtc);
3378                 else if (old_crtc_state->pch_pfit.enabled)
3379                         ironlake_pfit_disable(crtc, true);
3380         }
3381 }
3382
3383 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3384 {
3385         struct drm_device *dev = crtc->dev;
3386         struct drm_i915_private *dev_priv = dev->dev_private;
3387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3388         int pipe = intel_crtc->pipe;
3389         u32 reg, temp;
3390
3391         /* enable normal train */
3392         reg = FDI_TX_CTL(pipe);
3393         temp = I915_READ(reg);
3394         if (IS_IVYBRIDGE(dev)) {
3395                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3396                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3397         } else {
3398                 temp &= ~FDI_LINK_TRAIN_NONE;
3399                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3400         }
3401         I915_WRITE(reg, temp);
3402
3403         reg = FDI_RX_CTL(pipe);
3404         temp = I915_READ(reg);
3405         if (HAS_PCH_CPT(dev)) {
3406                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3407                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3408         } else {
3409                 temp &= ~FDI_LINK_TRAIN_NONE;
3410                 temp |= FDI_LINK_TRAIN_NONE;
3411         }
3412         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3413
3414         /* wait one idle pattern time */
3415         POSTING_READ(reg);
3416         udelay(1000);
3417
3418         /* IVB wants error correction enabled */
3419         if (IS_IVYBRIDGE(dev))
3420                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3421                            FDI_FE_ERRC_ENABLE);
3422 }
3423
3424 /* The FDI link training functions for ILK/Ibexpeak. */
3425 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3426 {
3427         struct drm_device *dev = crtc->dev;
3428         struct drm_i915_private *dev_priv = dev->dev_private;
3429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3430         int pipe = intel_crtc->pipe;
3431         u32 reg, temp, tries;
3432
3433         /* FDI needs bits from pipe first */
3434         assert_pipe_enabled(dev_priv, pipe);
3435
3436         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3437            for train result */
3438         reg = FDI_RX_IMR(pipe);
3439         temp = I915_READ(reg);
3440         temp &= ~FDI_RX_SYMBOL_LOCK;
3441         temp &= ~FDI_RX_BIT_LOCK;
3442         I915_WRITE(reg, temp);
3443         I915_READ(reg);
3444         udelay(150);
3445
3446         /* enable CPU FDI TX and PCH FDI RX */
3447         reg = FDI_TX_CTL(pipe);
3448         temp = I915_READ(reg);
3449         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3450         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3451         temp &= ~FDI_LINK_TRAIN_NONE;
3452         temp |= FDI_LINK_TRAIN_PATTERN_1;
3453         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3454
3455         reg = FDI_RX_CTL(pipe);
3456         temp = I915_READ(reg);
3457         temp &= ~FDI_LINK_TRAIN_NONE;
3458         temp |= FDI_LINK_TRAIN_PATTERN_1;
3459         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3460
3461         POSTING_READ(reg);
3462         udelay(150);
3463
3464         /* Ironlake workaround, enable clock pointer after FDI enable*/
3465         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3466         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3467                    FDI_RX_PHASE_SYNC_POINTER_EN);
3468
3469         reg = FDI_RX_IIR(pipe);
3470         for (tries = 0; tries < 5; tries++) {
3471                 temp = I915_READ(reg);
3472                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3473
3474                 if ((temp & FDI_RX_BIT_LOCK)) {
3475                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3476                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3477                         break;
3478                 }
3479         }
3480         if (tries == 5)
3481                 DRM_ERROR("FDI train 1 fail!\n");
3482
3483         /* Train 2 */
3484         reg = FDI_TX_CTL(pipe);
3485         temp = I915_READ(reg);
3486         temp &= ~FDI_LINK_TRAIN_NONE;
3487         temp |= FDI_LINK_TRAIN_PATTERN_2;
3488         I915_WRITE(reg, temp);
3489
3490         reg = FDI_RX_CTL(pipe);
3491         temp = I915_READ(reg);
3492         temp &= ~FDI_LINK_TRAIN_NONE;
3493         temp |= FDI_LINK_TRAIN_PATTERN_2;
3494         I915_WRITE(reg, temp);
3495
3496         POSTING_READ(reg);
3497         udelay(150);
3498
3499         reg = FDI_RX_IIR(pipe);
3500         for (tries = 0; tries < 5; tries++) {
3501                 temp = I915_READ(reg);
3502                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3503
3504                 if (temp & FDI_RX_SYMBOL_LOCK) {
3505                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3506                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3507                         break;
3508                 }
3509         }
3510         if (tries == 5)
3511                 DRM_ERROR("FDI train 2 fail!\n");
3512
3513         DRM_DEBUG_KMS("FDI train done\n");
3514
3515 }
3516
3517 static const int snb_b_fdi_train_param[] = {
3518         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3519         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3520         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3521         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3522 };
3523
3524 /* The FDI link training functions for SNB/Cougarpoint. */
3525 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3526 {
3527         struct drm_device *dev = crtc->dev;
3528         struct drm_i915_private *dev_priv = dev->dev_private;
3529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3530         int pipe = intel_crtc->pipe;
3531         u32 reg, temp, i, retry;
3532
3533         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3534            for train result */
3535         reg = FDI_RX_IMR(pipe);
3536         temp = I915_READ(reg);
3537         temp &= ~FDI_RX_SYMBOL_LOCK;
3538         temp &= ~FDI_RX_BIT_LOCK;
3539         I915_WRITE(reg, temp);
3540
3541         POSTING_READ(reg);
3542         udelay(150);
3543
3544         /* enable CPU FDI TX and PCH FDI RX */
3545         reg = FDI_TX_CTL(pipe);
3546         temp = I915_READ(reg);
3547         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3548         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3549         temp &= ~FDI_LINK_TRAIN_NONE;
3550         temp |= FDI_LINK_TRAIN_PATTERN_1;
3551         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3552         /* SNB-B */
3553         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3554         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3555
3556         I915_WRITE(FDI_RX_MISC(pipe),
3557                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3558
3559         reg = FDI_RX_CTL(pipe);
3560         temp = I915_READ(reg);
3561         if (HAS_PCH_CPT(dev)) {
3562                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3563                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3564         } else {
3565                 temp &= ~FDI_LINK_TRAIN_NONE;
3566                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3567         }
3568         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3569
3570         POSTING_READ(reg);
3571         udelay(150);
3572
3573         for (i = 0; i < 4; i++) {
3574                 reg = FDI_TX_CTL(pipe);
3575                 temp = I915_READ(reg);
3576                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577                 temp |= snb_b_fdi_train_param[i];
3578                 I915_WRITE(reg, temp);
3579
3580                 POSTING_READ(reg);
3581                 udelay(500);
3582
3583                 for (retry = 0; retry < 5; retry++) {
3584                         reg = FDI_RX_IIR(pipe);
3585                         temp = I915_READ(reg);
3586                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3587                         if (temp & FDI_RX_BIT_LOCK) {
3588                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3589                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3590                                 break;
3591                         }
3592                         udelay(50);
3593                 }
3594                 if (retry < 5)
3595                         break;
3596         }
3597         if (i == 4)
3598                 DRM_ERROR("FDI train 1 fail!\n");
3599
3600         /* Train 2 */
3601         reg = FDI_TX_CTL(pipe);
3602         temp = I915_READ(reg);
3603         temp &= ~FDI_LINK_TRAIN_NONE;
3604         temp |= FDI_LINK_TRAIN_PATTERN_2;
3605         if (IS_GEN6(dev)) {
3606                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3607                 /* SNB-B */
3608                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3609         }
3610         I915_WRITE(reg, temp);
3611
3612         reg = FDI_RX_CTL(pipe);
3613         temp = I915_READ(reg);
3614         if (HAS_PCH_CPT(dev)) {
3615                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3616                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3617         } else {
3618                 temp &= ~FDI_LINK_TRAIN_NONE;
3619                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3620         }
3621         I915_WRITE(reg, temp);
3622
3623         POSTING_READ(reg);
3624         udelay(150);
3625
3626         for (i = 0; i < 4; i++) {
3627                 reg = FDI_TX_CTL(pipe);
3628                 temp = I915_READ(reg);
3629                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3630                 temp |= snb_b_fdi_train_param[i];
3631                 I915_WRITE(reg, temp);
3632
3633                 POSTING_READ(reg);
3634                 udelay(500);
3635
3636                 for (retry = 0; retry < 5; retry++) {
3637                         reg = FDI_RX_IIR(pipe);
3638                         temp = I915_READ(reg);
3639                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3640                         if (temp & FDI_RX_SYMBOL_LOCK) {
3641                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3642                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3643                                 break;
3644                         }
3645                         udelay(50);
3646                 }
3647                 if (retry < 5)
3648                         break;
3649         }
3650         if (i == 4)
3651                 DRM_ERROR("FDI train 2 fail!\n");
3652
3653         DRM_DEBUG_KMS("FDI train done.\n");
3654 }
3655
3656 /* Manual link training for Ivy Bridge A0 parts */
3657 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3658 {
3659         struct drm_device *dev = crtc->dev;
3660         struct drm_i915_private *dev_priv = dev->dev_private;
3661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3662         int pipe = intel_crtc->pipe;
3663         u32 reg, temp, i, j;
3664
3665         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3666            for train result */
3667         reg = FDI_RX_IMR(pipe);
3668         temp = I915_READ(reg);
3669         temp &= ~FDI_RX_SYMBOL_LOCK;
3670         temp &= ~FDI_RX_BIT_LOCK;
3671         I915_WRITE(reg, temp);
3672
3673         POSTING_READ(reg);
3674         udelay(150);
3675
3676         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3677                       I915_READ(FDI_RX_IIR(pipe)));
3678
3679         /* Try each vswing and preemphasis setting twice before moving on */
3680         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3681                 /* disable first in case we need to retry */
3682                 reg = FDI_TX_CTL(pipe);
3683                 temp = I915_READ(reg);
3684                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3685                 temp &= ~FDI_TX_ENABLE;
3686                 I915_WRITE(reg, temp);
3687
3688                 reg = FDI_RX_CTL(pipe);
3689                 temp = I915_READ(reg);
3690                 temp &= ~FDI_LINK_TRAIN_AUTO;
3691                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3692                 temp &= ~FDI_RX_ENABLE;
3693                 I915_WRITE(reg, temp);
3694
3695                 /* enable CPU FDI TX and PCH FDI RX */
3696                 reg = FDI_TX_CTL(pipe);
3697                 temp = I915_READ(reg);
3698                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3699                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3700                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3701                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3702                 temp |= snb_b_fdi_train_param[j/2];
3703                 temp |= FDI_COMPOSITE_SYNC;
3704                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3705
3706                 I915_WRITE(FDI_RX_MISC(pipe),
3707                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3708
3709                 reg = FDI_RX_CTL(pipe);
3710                 temp = I915_READ(reg);
3711                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3712                 temp |= FDI_COMPOSITE_SYNC;
3713                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3714
3715                 POSTING_READ(reg);
3716                 udelay(1); /* should be 0.5us */
3717
3718                 for (i = 0; i < 4; i++) {
3719                         reg = FDI_RX_IIR(pipe);
3720                         temp = I915_READ(reg);
3721                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3722
3723                         if (temp & FDI_RX_BIT_LOCK ||
3724                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3725                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3726                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3727                                               i);
3728                                 break;
3729                         }
3730                         udelay(1); /* should be 0.5us */
3731                 }
3732                 if (i == 4) {
3733                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3734                         continue;
3735                 }
3736
3737                 /* Train 2 */
3738                 reg = FDI_TX_CTL(pipe);
3739                 temp = I915_READ(reg);
3740                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3741                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3742                 I915_WRITE(reg, temp);
3743
3744                 reg = FDI_RX_CTL(pipe);
3745                 temp = I915_READ(reg);
3746                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3747                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3748                 I915_WRITE(reg, temp);
3749
3750                 POSTING_READ(reg);
3751                 udelay(2); /* should be 1.5us */
3752
3753                 for (i = 0; i < 4; i++) {
3754                         reg = FDI_RX_IIR(pipe);
3755                         temp = I915_READ(reg);
3756                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3757
3758                         if (temp & FDI_RX_SYMBOL_LOCK ||
3759                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3760                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3761                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3762                                               i);
3763                                 goto train_done;
3764                         }
3765                         udelay(2); /* should be 1.5us */
3766                 }
3767                 if (i == 4)
3768                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3769         }
3770
3771 train_done:
3772         DRM_DEBUG_KMS("FDI train done.\n");
3773 }
3774
3775 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3776 {
3777         struct drm_device *dev = intel_crtc->base.dev;
3778         struct drm_i915_private *dev_priv = dev->dev_private;
3779         int pipe = intel_crtc->pipe;
3780         u32 reg, temp;
3781
3782
3783         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3784         reg = FDI_RX_CTL(pipe);
3785         temp = I915_READ(reg);
3786         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3787         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3788         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3789         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3790
3791         POSTING_READ(reg);
3792         udelay(200);
3793
3794         /* Switch from Rawclk to PCDclk */
3795         temp = I915_READ(reg);
3796         I915_WRITE(reg, temp | FDI_PCDCLK);
3797
3798         POSTING_READ(reg);
3799         udelay(200);
3800
3801         /* Enable CPU FDI TX PLL, always on for Ironlake */
3802         reg = FDI_TX_CTL(pipe);
3803         temp = I915_READ(reg);
3804         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3805                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3806
3807                 POSTING_READ(reg);
3808                 udelay(100);
3809         }
3810 }
3811
3812 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3813 {
3814         struct drm_device *dev = intel_crtc->base.dev;
3815         struct drm_i915_private *dev_priv = dev->dev_private;
3816         int pipe = intel_crtc->pipe;
3817         u32 reg, temp;
3818
3819         /* Switch from PCDclk to Rawclk */
3820         reg = FDI_RX_CTL(pipe);
3821         temp = I915_READ(reg);
3822         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3823
3824         /* Disable CPU FDI TX PLL */
3825         reg = FDI_TX_CTL(pipe);
3826         temp = I915_READ(reg);
3827         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3828
3829         POSTING_READ(reg);
3830         udelay(100);
3831
3832         reg = FDI_RX_CTL(pipe);
3833         temp = I915_READ(reg);
3834         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3835
3836         /* Wait for the clocks to turn off. */
3837         POSTING_READ(reg);
3838         udelay(100);
3839 }
3840
3841 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_i915_private *dev_priv = dev->dev_private;
3845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846         int pipe = intel_crtc->pipe;
3847         u32 reg, temp;
3848
3849         /* disable CPU FDI tx and PCH FDI rx */
3850         reg = FDI_TX_CTL(pipe);
3851         temp = I915_READ(reg);
3852         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3853         POSTING_READ(reg);
3854
3855         reg = FDI_RX_CTL(pipe);
3856         temp = I915_READ(reg);
3857         temp &= ~(0x7 << 16);
3858         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3859         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3860
3861         POSTING_READ(reg);
3862         udelay(100);
3863
3864         /* Ironlake workaround, disable clock pointer after downing FDI */
3865         if (HAS_PCH_IBX(dev))
3866                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3867
3868         /* still set train pattern 1 */
3869         reg = FDI_TX_CTL(pipe);
3870         temp = I915_READ(reg);
3871         temp &= ~FDI_LINK_TRAIN_NONE;
3872         temp |= FDI_LINK_TRAIN_PATTERN_1;
3873         I915_WRITE(reg, temp);
3874
3875         reg = FDI_RX_CTL(pipe);
3876         temp = I915_READ(reg);
3877         if (HAS_PCH_CPT(dev)) {
3878                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3879                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3880         } else {
3881                 temp &= ~FDI_LINK_TRAIN_NONE;
3882                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3883         }
3884         /* BPC in FDI rx is consistent with that in PIPECONF */
3885         temp &= ~(0x07 << 16);
3886         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3887         I915_WRITE(reg, temp);
3888
3889         POSTING_READ(reg);
3890         udelay(100);
3891 }
3892
3893 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3894 {
3895         struct intel_crtc *crtc;
3896
3897         /* Note that we don't need to be called with mode_config.lock here
3898          * as our list of CRTC objects is static for the lifetime of the
3899          * device and so cannot disappear as we iterate. Similarly, we can
3900          * happily treat the predicates as racy, atomic checks as userspace
3901          * cannot claim and pin a new fb without at least acquring the
3902          * struct_mutex and so serialising with us.
3903          */
3904         for_each_intel_crtc(dev, crtc) {
3905                 if (atomic_read(&crtc->unpin_work_count) == 0)
3906                         continue;
3907
3908                 if (crtc->unpin_work)
3909                         intel_wait_for_vblank(dev, crtc->pipe);
3910
3911                 return true;
3912         }
3913
3914         return false;
3915 }
3916
3917 static void page_flip_completed(struct intel_crtc *intel_crtc)
3918 {
3919         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3920         struct intel_unpin_work *work = intel_crtc->unpin_work;
3921
3922         /* ensure that the unpin work is consistent wrt ->pending. */
3923         smp_rmb();
3924         intel_crtc->unpin_work = NULL;
3925
3926         if (work->event)
3927                 drm_send_vblank_event(intel_crtc->base.dev,
3928                                       intel_crtc->pipe,
3929                                       work->event);
3930
3931         drm_crtc_vblank_put(&intel_crtc->base);
3932
3933         wake_up_all(&dev_priv->pending_flip_queue);
3934         queue_work(dev_priv->wq, &work->work);
3935
3936         trace_i915_flip_complete(intel_crtc->plane,
3937                                  work->pending_flip_obj);
3938 }
3939
3940 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3941 {
3942         struct drm_device *dev = crtc->dev;
3943         struct drm_i915_private *dev_priv = dev->dev_private;
3944
3945         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3946         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3947                                        !intel_crtc_has_pending_flip(crtc),
3948                                        60*HZ) == 0)) {
3949                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3950
3951                 spin_lock_irq(&dev->event_lock);
3952                 if (intel_crtc->unpin_work) {
3953                         WARN_ONCE(1, "Removing stuck page flip\n");
3954                         page_flip_completed(intel_crtc);
3955                 }
3956                 spin_unlock_irq(&dev->event_lock);
3957         }
3958
3959         if (crtc->primary->fb) {
3960                 mutex_lock(&dev->struct_mutex);
3961                 intel_finish_fb(crtc->primary->fb);
3962                 mutex_unlock(&dev->struct_mutex);
3963         }
3964 }
3965
3966 /* Program iCLKIP clock to the desired frequency */
3967 static void lpt_program_iclkip(struct drm_crtc *crtc)
3968 {
3969         struct drm_device *dev = crtc->dev;
3970         struct drm_i915_private *dev_priv = dev->dev_private;
3971         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3972         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3973         u32 temp;
3974
3975         mutex_lock(&dev_priv->sb_lock);
3976
3977         /* It is necessary to ungate the pixclk gate prior to programming
3978          * the divisors, and gate it back when it is done.
3979          */
3980         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3981
3982         /* Disable SSCCTL */
3983         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3984                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3985                                 SBI_SSCCTL_DISABLE,
3986                         SBI_ICLK);
3987
3988         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3989         if (clock == 20000) {
3990                 auxdiv = 1;
3991                 divsel = 0x41;
3992                 phaseinc = 0x20;
3993         } else {
3994                 /* The iCLK virtual clock root frequency is in MHz,
3995                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3996                  * divisors, it is necessary to divide one by another, so we
3997                  * convert the virtual clock precision to KHz here for higher
3998                  * precision.
3999                  */
4000                 u32 iclk_virtual_root_freq = 172800 * 1000;
4001                 u32 iclk_pi_range = 64;
4002                 u32 desired_divisor, msb_divisor_value, pi_value;
4003
4004                 desired_divisor = (iclk_virtual_root_freq / clock);
4005                 msb_divisor_value = desired_divisor / iclk_pi_range;
4006                 pi_value = desired_divisor % iclk_pi_range;
4007
4008                 auxdiv = 0;
4009                 divsel = msb_divisor_value - 2;
4010                 phaseinc = pi_value;
4011         }
4012
4013         /* This should not happen with any sane values */
4014         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4015                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4016         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4017                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4018
4019         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4020                         clock,
4021                         auxdiv,
4022                         divsel,
4023                         phasedir,
4024                         phaseinc);
4025
4026         /* Program SSCDIVINTPHASE6 */
4027         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4028         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4029         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4030         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4031         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4032         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4033         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4034         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4035
4036         /* Program SSCAUXDIV */
4037         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4038         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4039         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4040         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4041
4042         /* Enable modulator and associated divider */
4043         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4044         temp &= ~SBI_SSCCTL_DISABLE;
4045         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4046
4047         /* Wait for initialization time */
4048         udelay(24);
4049
4050         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4051
4052         mutex_unlock(&dev_priv->sb_lock);
4053 }
4054
4055 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4056                                                 enum pipe pch_transcoder)
4057 {
4058         struct drm_device *dev = crtc->base.dev;
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4061
4062         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4063                    I915_READ(HTOTAL(cpu_transcoder)));
4064         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4065                    I915_READ(HBLANK(cpu_transcoder)));
4066         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4067                    I915_READ(HSYNC(cpu_transcoder)));
4068
4069         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4070                    I915_READ(VTOTAL(cpu_transcoder)));
4071         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4072                    I915_READ(VBLANK(cpu_transcoder)));
4073         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4074                    I915_READ(VSYNC(cpu_transcoder)));
4075         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4076                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4077 }
4078
4079 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4080 {
4081         struct drm_i915_private *dev_priv = dev->dev_private;
4082         uint32_t temp;
4083
4084         temp = I915_READ(SOUTH_CHICKEN1);
4085         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4086                 return;
4087
4088         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4089         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4090
4091         temp &= ~FDI_BC_BIFURCATION_SELECT;
4092         if (enable)
4093                 temp |= FDI_BC_BIFURCATION_SELECT;
4094
4095         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4096         I915_WRITE(SOUTH_CHICKEN1, temp);
4097         POSTING_READ(SOUTH_CHICKEN1);
4098 }
4099
4100 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4101 {
4102         struct drm_device *dev = intel_crtc->base.dev;
4103
4104         switch (intel_crtc->pipe) {
4105         case PIPE_A:
4106                 break;
4107         case PIPE_B:
4108                 if (intel_crtc->config->fdi_lanes > 2)
4109                         cpt_set_fdi_bc_bifurcation(dev, false);
4110                 else
4111                         cpt_set_fdi_bc_bifurcation(dev, true);
4112
4113                 break;
4114         case PIPE_C:
4115                 cpt_set_fdi_bc_bifurcation(dev, true);
4116
4117                 break;
4118         default:
4119                 BUG();
4120         }
4121 }
4122
4123 /*
4124  * Enable PCH resources required for PCH ports:
4125  *   - PCH PLLs
4126  *   - FDI training & RX/TX
4127  *   - update transcoder timings
4128  *   - DP transcoding bits
4129  *   - transcoder
4130  */
4131 static void ironlake_pch_enable(struct drm_crtc *crtc)
4132 {
4133         struct drm_device *dev = crtc->dev;
4134         struct drm_i915_private *dev_priv = dev->dev_private;
4135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4136         int pipe = intel_crtc->pipe;
4137         u32 reg, temp;
4138
4139         assert_pch_transcoder_disabled(dev_priv, pipe);
4140
4141         if (IS_IVYBRIDGE(dev))
4142                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4143
4144         /* Write the TU size bits before fdi link training, so that error
4145          * detection works. */
4146         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4147                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4148
4149         /* For PCH output, training FDI link */
4150         dev_priv->display.fdi_link_train(crtc);
4151
4152         /* We need to program the right clock selection before writing the pixel
4153          * mutliplier into the DPLL. */
4154         if (HAS_PCH_CPT(dev)) {
4155                 u32 sel;
4156
4157                 temp = I915_READ(PCH_DPLL_SEL);
4158                 temp |= TRANS_DPLL_ENABLE(pipe);
4159                 sel = TRANS_DPLLB_SEL(pipe);
4160                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4161                         temp |= sel;
4162                 else
4163                         temp &= ~sel;
4164                 I915_WRITE(PCH_DPLL_SEL, temp);
4165         }
4166
4167         /* XXX: pch pll's can be enabled any time before we enable the PCH
4168          * transcoder, and we actually should do this to not upset any PCH
4169          * transcoder that already use the clock when we share it.
4170          *
4171          * Note that enable_shared_dpll tries to do the right thing, but
4172          * get_shared_dpll unconditionally resets the pll - we need that to have
4173          * the right LVDS enable sequence. */
4174         intel_enable_shared_dpll(intel_crtc);
4175
4176         /* set transcoder timing, panel must allow it */
4177         assert_panel_unlocked(dev_priv, pipe);
4178         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4179
4180         intel_fdi_normal_train(crtc);
4181
4182         /* For PCH DP, enable TRANS_DP_CTL */
4183         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4184                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4185                 reg = TRANS_DP_CTL(pipe);
4186                 temp = I915_READ(reg);
4187                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4188                           TRANS_DP_SYNC_MASK |
4189                           TRANS_DP_BPC_MASK);
4190                 temp |= TRANS_DP_OUTPUT_ENABLE;
4191                 temp |= bpc << 9; /* same format but at 11:9 */
4192
4193                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4194                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4195                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4196                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4197
4198                 switch (intel_trans_dp_port_sel(crtc)) {
4199                 case PCH_DP_B:
4200                         temp |= TRANS_DP_PORT_SEL_B;
4201                         break;
4202                 case PCH_DP_C:
4203                         temp |= TRANS_DP_PORT_SEL_C;
4204                         break;
4205                 case PCH_DP_D:
4206                         temp |= TRANS_DP_PORT_SEL_D;
4207                         break;
4208                 default:
4209                         BUG();
4210                 }
4211
4212                 I915_WRITE(reg, temp);
4213         }
4214
4215         ironlake_enable_pch_transcoder(dev_priv, pipe);
4216 }
4217
4218 static void lpt_pch_enable(struct drm_crtc *crtc)
4219 {
4220         struct drm_device *dev = crtc->dev;
4221         struct drm_i915_private *dev_priv = dev->dev_private;
4222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4223         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4224
4225         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4226
4227         lpt_program_iclkip(crtc);
4228
4229         /* Set transcoder timing. */
4230         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4231
4232         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4233 }
4234
4235 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4236                                                 struct intel_crtc_state *crtc_state)
4237 {
4238         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4239         struct intel_shared_dpll *pll;
4240         struct intel_shared_dpll_config *shared_dpll;
4241         enum intel_dpll_id i;
4242
4243         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4244
4245         if (HAS_PCH_IBX(dev_priv->dev)) {
4246                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4247                 i = (enum intel_dpll_id) crtc->pipe;
4248                 pll = &dev_priv->shared_dplls[i];
4249
4250                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4251                               crtc->base.base.id, pll->name);
4252
4253                 WARN_ON(shared_dpll[i].crtc_mask);
4254
4255                 goto found;
4256         }
4257
4258         if (IS_BROXTON(dev_priv->dev)) {
4259                 /* PLL is attached to port in bxt */
4260                 struct intel_encoder *encoder;
4261                 struct intel_digital_port *intel_dig_port;
4262
4263                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4264                 if (WARN_ON(!encoder))
4265                         return NULL;
4266
4267                 intel_dig_port = enc_to_dig_port(&encoder->base);
4268                 /* 1:1 mapping between ports and PLLs */
4269                 i = (enum intel_dpll_id)intel_dig_port->port;
4270                 pll = &dev_priv->shared_dplls[i];
4271                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272                         crtc->base.base.id, pll->name);
4273                 WARN_ON(shared_dpll[i].crtc_mask);
4274
4275                 goto found;
4276         }
4277
4278         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4279                 pll = &dev_priv->shared_dplls[i];
4280
4281                 /* Only want to check enabled timings first */
4282                 if (shared_dpll[i].crtc_mask == 0)
4283                         continue;
4284
4285                 if (memcmp(&crtc_state->dpll_hw_state,
4286                            &shared_dpll[i].hw_state,
4287                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4288                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4289                                       crtc->base.base.id, pll->name,
4290                                       shared_dpll[i].crtc_mask,
4291                                       pll->active);
4292                         goto found;
4293                 }
4294         }
4295
4296         /* Ok no matching timings, maybe there's a free one? */
4297         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4298                 pll = &dev_priv->shared_dplls[i];
4299                 if (shared_dpll[i].crtc_mask == 0) {
4300                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4301                                       crtc->base.base.id, pll->name);
4302                         goto found;
4303                 }
4304         }
4305
4306         return NULL;
4307
4308 found:
4309         if (shared_dpll[i].crtc_mask == 0)
4310                 shared_dpll[i].hw_state =
4311                         crtc_state->dpll_hw_state;
4312
4313         crtc_state->shared_dpll = i;
4314         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4315                          pipe_name(crtc->pipe));
4316
4317         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4318
4319         return pll;
4320 }
4321
4322 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4323 {
4324         struct drm_i915_private *dev_priv = to_i915(state->dev);
4325         struct intel_shared_dpll_config *shared_dpll;
4326         struct intel_shared_dpll *pll;
4327         enum intel_dpll_id i;
4328
4329         if (!to_intel_atomic_state(state)->dpll_set)
4330                 return;
4331
4332         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4333         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4334                 pll = &dev_priv->shared_dplls[i];
4335                 pll->config = shared_dpll[i];
4336         }
4337 }
4338
4339 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4340 {
4341         struct drm_i915_private *dev_priv = dev->dev_private;
4342         int dslreg = PIPEDSL(pipe);
4343         u32 temp;
4344
4345         temp = I915_READ(dslreg);
4346         udelay(500);
4347         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4348                 if (wait_for(I915_READ(dslreg) != temp, 5))
4349                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4350         }
4351 }
4352
4353 static int
4354 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4355                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4356                   int src_w, int src_h, int dst_w, int dst_h)
4357 {
4358         struct intel_crtc_scaler_state *scaler_state =
4359                 &crtc_state->scaler_state;
4360         struct intel_crtc *intel_crtc =
4361                 to_intel_crtc(crtc_state->base.crtc);
4362         int need_scaling;
4363
4364         need_scaling = intel_rotation_90_or_270(rotation) ?
4365                 (src_h != dst_w || src_w != dst_h):
4366                 (src_w != dst_w || src_h != dst_h);
4367
4368         /*
4369          * if plane is being disabled or scaler is no more required or force detach
4370          *  - free scaler binded to this plane/crtc
4371          *  - in order to do this, update crtc->scaler_usage
4372          *
4373          * Here scaler state in crtc_state is set free so that
4374          * scaler can be assigned to other user. Actual register
4375          * update to free the scaler is done in plane/panel-fit programming.
4376          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4377          */
4378         if (force_detach || !need_scaling) {
4379                 if (*scaler_id >= 0) {
4380                         scaler_state->scaler_users &= ~(1 << scaler_user);
4381                         scaler_state->scalers[*scaler_id].in_use = 0;
4382
4383                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4384                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4385                                 intel_crtc->pipe, scaler_user, *scaler_id,
4386                                 scaler_state->scaler_users);
4387                         *scaler_id = -1;
4388                 }
4389                 return 0;
4390         }
4391
4392         /* range checks */
4393         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4394                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4395
4396                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4397                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4398                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4399                         "size is out of scaler range\n",
4400                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4401                 return -EINVAL;
4402         }
4403
4404         /* mark this plane as a scaler user in crtc_state */
4405         scaler_state->scaler_users |= (1 << scaler_user);
4406         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4407                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4408                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4409                 scaler_state->scaler_users);
4410
4411         return 0;
4412 }
4413
4414 /**
4415  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4416  *
4417  * @state: crtc's scaler state
4418  *
4419  * Return
4420  *     0 - scaler_usage updated successfully
4421  *    error - requested scaling cannot be supported or other error condition
4422  */
4423 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4424 {
4425         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4426         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4427
4428         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4429                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4430
4431         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4432                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4433                 state->pipe_src_w, state->pipe_src_h,
4434                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4435 }
4436
4437 /**
4438  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4439  *
4440  * @state: crtc's scaler state
4441  * @plane_state: atomic plane state to update
4442  *
4443  * Return
4444  *     0 - scaler_usage updated successfully
4445  *    error - requested scaling cannot be supported or other error condition
4446  */
4447 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4448                                    struct intel_plane_state *plane_state)
4449 {
4450
4451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4452         struct intel_plane *intel_plane =
4453                 to_intel_plane(plane_state->base.plane);
4454         struct drm_framebuffer *fb = plane_state->base.fb;
4455         int ret;
4456
4457         bool force_detach = !fb || !plane_state->visible;
4458
4459         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4460                       intel_plane->base.base.id, intel_crtc->pipe,
4461                       drm_plane_index(&intel_plane->base));
4462
4463         ret = skl_update_scaler(crtc_state, force_detach,
4464                                 drm_plane_index(&intel_plane->base),
4465                                 &plane_state->scaler_id,
4466                                 plane_state->base.rotation,
4467                                 drm_rect_width(&plane_state->src) >> 16,
4468                                 drm_rect_height(&plane_state->src) >> 16,
4469                                 drm_rect_width(&plane_state->dst),
4470                                 drm_rect_height(&plane_state->dst));
4471
4472         if (ret || plane_state->scaler_id < 0)
4473                 return ret;
4474
4475         /* check colorkey */
4476         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4477                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4478                               intel_plane->base.base.id);
4479                 return -EINVAL;
4480         }
4481
4482         /* Check src format */
4483         switch (fb->pixel_format) {
4484         case DRM_FORMAT_RGB565:
4485         case DRM_FORMAT_XBGR8888:
4486         case DRM_FORMAT_XRGB8888:
4487         case DRM_FORMAT_ABGR8888:
4488         case DRM_FORMAT_ARGB8888:
4489         case DRM_FORMAT_XRGB2101010:
4490         case DRM_FORMAT_XBGR2101010:
4491         case DRM_FORMAT_YUYV:
4492         case DRM_FORMAT_YVYU:
4493         case DRM_FORMAT_UYVY:
4494         case DRM_FORMAT_VYUY:
4495                 break;
4496         default:
4497                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4498                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4499                 return -EINVAL;
4500         }
4501
4502         return 0;
4503 }
4504
4505 static void skylake_scaler_disable(struct intel_crtc *crtc)
4506 {
4507         int i;
4508
4509         for (i = 0; i < crtc->num_scalers; i++)
4510                 skl_detach_scaler(crtc, i);
4511 }
4512
4513 static void skylake_pfit_enable(struct intel_crtc *crtc)
4514 {
4515         struct drm_device *dev = crtc->base.dev;
4516         struct drm_i915_private *dev_priv = dev->dev_private;
4517         int pipe = crtc->pipe;
4518         struct intel_crtc_scaler_state *scaler_state =
4519                 &crtc->config->scaler_state;
4520
4521         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4522
4523         if (crtc->config->pch_pfit.enabled) {
4524                 int id;
4525
4526                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4527                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4528                         return;
4529                 }
4530
4531                 id = scaler_state->scaler_id;
4532                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4533                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4534                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4535                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4536
4537                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4538         }
4539 }
4540
4541 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4542 {
4543         struct drm_device *dev = crtc->base.dev;
4544         struct drm_i915_private *dev_priv = dev->dev_private;
4545         int pipe = crtc->pipe;
4546
4547         if (crtc->config->pch_pfit.enabled) {
4548                 /* Force use of hard-coded filter coefficients
4549                  * as some pre-programmed values are broken,
4550                  * e.g. x201.
4551                  */
4552                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4553                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4554                                                  PF_PIPE_SEL_IVB(pipe));
4555                 else
4556                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4557                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4558                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4559         }
4560 }
4561
4562 void hsw_enable_ips(struct intel_crtc *crtc)
4563 {
4564         struct drm_device *dev = crtc->base.dev;
4565         struct drm_i915_private *dev_priv = dev->dev_private;
4566
4567         if (!crtc->config->ips_enabled)
4568                 return;
4569
4570         /* We can only enable IPS after we enable a plane and wait for a vblank */
4571         intel_wait_for_vblank(dev, crtc->pipe);
4572
4573         assert_plane_enabled(dev_priv, crtc->plane);
4574         if (IS_BROADWELL(dev)) {
4575                 mutex_lock(&dev_priv->rps.hw_lock);
4576                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4577                 mutex_unlock(&dev_priv->rps.hw_lock);
4578                 /* Quoting Art Runyan: "its not safe to expect any particular
4579                  * value in IPS_CTL bit 31 after enabling IPS through the
4580                  * mailbox." Moreover, the mailbox may return a bogus state,
4581                  * so we need to just enable it and continue on.
4582                  */
4583         } else {
4584                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4585                 /* The bit only becomes 1 in the next vblank, so this wait here
4586                  * is essentially intel_wait_for_vblank. If we don't have this
4587                  * and don't wait for vblanks until the end of crtc_enable, then
4588                  * the HW state readout code will complain that the expected
4589                  * IPS_CTL value is not the one we read. */
4590                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4591                         DRM_ERROR("Timed out waiting for IPS enable\n");
4592         }
4593 }
4594
4595 void hsw_disable_ips(struct intel_crtc *crtc)
4596 {
4597         struct drm_device *dev = crtc->base.dev;
4598         struct drm_i915_private *dev_priv = dev->dev_private;
4599
4600         if (!crtc->config->ips_enabled)
4601                 return;
4602
4603         assert_plane_enabled(dev_priv, crtc->plane);
4604         if (IS_BROADWELL(dev)) {
4605                 mutex_lock(&dev_priv->rps.hw_lock);
4606                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4607                 mutex_unlock(&dev_priv->rps.hw_lock);
4608                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4609                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4610                         DRM_ERROR("Timed out waiting for IPS disable\n");
4611         } else {
4612                 I915_WRITE(IPS_CTL, 0);
4613                 POSTING_READ(IPS_CTL);
4614         }
4615
4616         /* We need to wait for a vblank before we can disable the plane. */
4617         intel_wait_for_vblank(dev, crtc->pipe);
4618 }
4619
4620 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4621 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4622 {
4623         struct drm_device *dev = crtc->dev;
4624         struct drm_i915_private *dev_priv = dev->dev_private;
4625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626         enum pipe pipe = intel_crtc->pipe;
4627         int i;
4628         bool reenable_ips = false;
4629
4630         /* The clocks have to be on to load the palette. */
4631         if (!crtc->state->active)
4632                 return;
4633
4634         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4635                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4636                         assert_dsi_pll_enabled(dev_priv);
4637                 else
4638                         assert_pll_enabled(dev_priv, pipe);
4639         }
4640
4641         /* Workaround : Do not read or write the pipe palette/gamma data while
4642          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4643          */
4644         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4645             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4646              GAMMA_MODE_MODE_SPLIT)) {
4647                 hsw_disable_ips(intel_crtc);
4648                 reenable_ips = true;
4649         }
4650
4651         for (i = 0; i < 256; i++) {
4652                 u32 palreg;
4653
4654                 if (HAS_GMCH_DISPLAY(dev))
4655                         palreg = PALETTE(pipe, i);
4656                 else
4657                         palreg = LGC_PALETTE(pipe, i);
4658
4659                 I915_WRITE(palreg,
4660                            (intel_crtc->lut_r[i] << 16) |
4661                            (intel_crtc->lut_g[i] << 8) |
4662                            intel_crtc->lut_b[i]);
4663         }
4664
4665         if (reenable_ips)
4666                 hsw_enable_ips(intel_crtc);
4667 }
4668
4669 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4670 {
4671         if (intel_crtc->overlay) {
4672                 struct drm_device *dev = intel_crtc->base.dev;
4673                 struct drm_i915_private *dev_priv = dev->dev_private;
4674
4675                 mutex_lock(&dev->struct_mutex);
4676                 dev_priv->mm.interruptible = false;
4677                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4678                 dev_priv->mm.interruptible = true;
4679                 mutex_unlock(&dev->struct_mutex);
4680         }
4681
4682         /* Let userspace switch the overlay on again. In most cases userspace
4683          * has to recompute where to put it anyway.
4684          */
4685 }
4686
4687 /**
4688  * intel_post_enable_primary - Perform operations after enabling primary plane
4689  * @crtc: the CRTC whose primary plane was just enabled
4690  *
4691  * Performs potentially sleeping operations that must be done after the primary
4692  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4693  * called due to an explicit primary plane update, or due to an implicit
4694  * re-enable that is caused when a sprite plane is updated to no longer
4695  * completely hide the primary plane.
4696  */
4697 static void
4698 intel_post_enable_primary(struct drm_crtc *crtc)
4699 {
4700         struct drm_device *dev = crtc->dev;
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703         int pipe = intel_crtc->pipe;
4704
4705         /*
4706          * BDW signals flip done immediately if the plane
4707          * is disabled, even if the plane enable is already
4708          * armed to occur at the next vblank :(
4709          */
4710         if (IS_BROADWELL(dev))
4711                 intel_wait_for_vblank(dev, pipe);
4712
4713         /*
4714          * FIXME IPS should be fine as long as one plane is
4715          * enabled, but in practice it seems to have problems
4716          * when going from primary only to sprite only and vice
4717          * versa.
4718          */
4719         hsw_enable_ips(intel_crtc);
4720
4721         /*
4722          * Gen2 reports pipe underruns whenever all planes are disabled.
4723          * So don't enable underrun reporting before at least some planes
4724          * are enabled.
4725          * FIXME: Need to fix the logic to work when we turn off all planes
4726          * but leave the pipe running.
4727          */
4728         if (IS_GEN2(dev))
4729                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4730
4731         /* Underruns don't raise interrupts, so check manually. */
4732         if (HAS_GMCH_DISPLAY(dev))
4733                 i9xx_check_fifo_underruns(dev_priv);
4734 }
4735
4736 /**
4737  * intel_pre_disable_primary - Perform operations before disabling primary plane
4738  * @crtc: the CRTC whose primary plane is to be disabled
4739  *
4740  * Performs potentially sleeping operations that must be done before the
4741  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4742  * be called due to an explicit primary plane update, or due to an implicit
4743  * disable that is caused when a sprite plane completely hides the primary
4744  * plane.
4745  */
4746 static void
4747 intel_pre_disable_primary(struct drm_crtc *crtc)
4748 {
4749         struct drm_device *dev = crtc->dev;
4750         struct drm_i915_private *dev_priv = dev->dev_private;
4751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4752         int pipe = intel_crtc->pipe;
4753
4754         /*
4755          * Gen2 reports pipe underruns whenever all planes are disabled.
4756          * So diasble underrun reporting before all the planes get disabled.
4757          * FIXME: Need to fix the logic to work when we turn off all planes
4758          * but leave the pipe running.
4759          */
4760         if (IS_GEN2(dev))
4761                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4762
4763         /*
4764          * Vblank time updates from the shadow to live plane control register
4765          * are blocked if the memory self-refresh mode is active at that
4766          * moment. So to make sure the plane gets truly disabled, disable
4767          * first the self-refresh mode. The self-refresh enable bit in turn
4768          * will be checked/applied by the HW only at the next frame start
4769          * event which is after the vblank start event, so we need to have a
4770          * wait-for-vblank between disabling the plane and the pipe.
4771          */
4772         if (HAS_GMCH_DISPLAY(dev)) {
4773                 intel_set_memory_cxsr(dev_priv, false);
4774                 dev_priv->wm.vlv.cxsr = false;
4775                 intel_wait_for_vblank(dev, pipe);
4776         }
4777
4778         /*
4779          * FIXME IPS should be fine as long as one plane is
4780          * enabled, but in practice it seems to have problems
4781          * when going from primary only to sprite only and vice
4782          * versa.
4783          */
4784         hsw_disable_ips(intel_crtc);
4785 }
4786
4787 static void intel_post_plane_update(struct intel_crtc *crtc)
4788 {
4789         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4790         struct drm_device *dev = crtc->base.dev;
4791         struct drm_i915_private *dev_priv = dev->dev_private;
4792         struct drm_plane *plane;
4793
4794         if (atomic->wait_vblank)
4795                 intel_wait_for_vblank(dev, crtc->pipe);
4796
4797         intel_frontbuffer_flip(dev, atomic->fb_bits);
4798
4799         if (atomic->disable_cxsr)
4800                 crtc->wm.cxsr_allowed = true;
4801
4802         if (crtc->atomic.update_wm_post)
4803                 intel_update_watermarks(&crtc->base);
4804
4805         if (atomic->update_fbc)
4806                 intel_fbc_update(dev_priv);
4807
4808         if (atomic->post_enable_primary)
4809                 intel_post_enable_primary(&crtc->base);
4810
4811         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4812                 intel_update_sprite_watermarks(plane, &crtc->base,
4813                                                0, 0, 0, false, false);
4814
4815         memset(atomic, 0, sizeof(*atomic));
4816 }
4817
4818 static void intel_pre_plane_update(struct intel_crtc *crtc)
4819 {
4820         struct drm_device *dev = crtc->base.dev;
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4823         struct drm_plane *p;
4824
4825         /* Track fb's for any planes being disabled */
4826         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4827                 struct intel_plane *plane = to_intel_plane(p);
4828
4829                 mutex_lock(&dev->struct_mutex);
4830                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4831                                   plane->frontbuffer_bit);
4832                 mutex_unlock(&dev->struct_mutex);
4833         }
4834
4835         if (atomic->wait_for_flips)
4836                 intel_crtc_wait_for_pending_flips(&crtc->base);
4837
4838         if (atomic->disable_fbc)
4839                 intel_fbc_disable_crtc(crtc);
4840
4841         if (crtc->atomic.disable_ips)
4842                 hsw_disable_ips(crtc);
4843
4844         if (atomic->pre_disable_primary)
4845                 intel_pre_disable_primary(&crtc->base);
4846
4847         if (atomic->disable_cxsr) {
4848                 crtc->wm.cxsr_allowed = false;
4849                 intel_set_memory_cxsr(dev_priv, false);
4850         }
4851 }
4852
4853 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4854 {
4855         struct drm_device *dev = crtc->dev;
4856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4857         struct drm_plane *p;
4858         int pipe = intel_crtc->pipe;
4859
4860         intel_crtc_dpms_overlay_disable(intel_crtc);
4861
4862         drm_for_each_plane_mask(p, dev, plane_mask)
4863                 to_intel_plane(p)->disable_plane(p, crtc);
4864
4865         /*
4866          * FIXME: Once we grow proper nuclear flip support out of this we need
4867          * to compute the mask of flip planes precisely. For the time being
4868          * consider this a flip to a NULL plane.
4869          */
4870         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4871 }
4872
4873 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4874 {
4875         struct drm_device *dev = crtc->dev;
4876         struct drm_i915_private *dev_priv = dev->dev_private;
4877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4878         struct intel_encoder *encoder;
4879         int pipe = intel_crtc->pipe;
4880
4881         if (WARN_ON(intel_crtc->active))
4882                 return;
4883
4884         if (intel_crtc->config->has_pch_encoder)
4885                 intel_prepare_shared_dpll(intel_crtc);
4886
4887         if (intel_crtc->config->has_dp_encoder)
4888                 intel_dp_set_m_n(intel_crtc, M1_N1);
4889
4890         intel_set_pipe_timings(intel_crtc);
4891
4892         if (intel_crtc->config->has_pch_encoder) {
4893                 intel_cpu_transcoder_set_m_n(intel_crtc,
4894                                      &intel_crtc->config->fdi_m_n, NULL);
4895         }
4896
4897         ironlake_set_pipeconf(crtc);
4898
4899         intel_crtc->active = true;
4900
4901         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4902         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4903
4904         for_each_encoder_on_crtc(dev, crtc, encoder)
4905                 if (encoder->pre_enable)
4906                         encoder->pre_enable(encoder);
4907
4908         if (intel_crtc->config->has_pch_encoder) {
4909                 /* Note: FDI PLL enabling _must_ be done before we enable the
4910                  * cpu pipes, hence this is separate from all the other fdi/pch
4911                  * enabling. */
4912                 ironlake_fdi_pll_enable(intel_crtc);
4913         } else {
4914                 assert_fdi_tx_disabled(dev_priv, pipe);
4915                 assert_fdi_rx_disabled(dev_priv, pipe);
4916         }
4917
4918         ironlake_pfit_enable(intel_crtc);
4919
4920         /*
4921          * On ILK+ LUT must be loaded before the pipe is running but with
4922          * clocks enabled
4923          */
4924         intel_crtc_load_lut(crtc);
4925
4926         intel_update_watermarks(crtc);
4927         intel_enable_pipe(intel_crtc);
4928
4929         if (intel_crtc->config->has_pch_encoder)
4930                 ironlake_pch_enable(crtc);
4931
4932         assert_vblank_disabled(crtc);
4933         drm_crtc_vblank_on(crtc);
4934
4935         for_each_encoder_on_crtc(dev, crtc, encoder)
4936                 encoder->enable(encoder);
4937
4938         if (HAS_PCH_CPT(dev))
4939                 cpt_verify_modeset(dev, intel_crtc->pipe);
4940 }
4941
4942 /* IPS only exists on ULT machines and is tied to pipe A. */
4943 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4944 {
4945         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4946 }
4947
4948 static void haswell_crtc_enable(struct drm_crtc *crtc)
4949 {
4950         struct drm_device *dev = crtc->dev;
4951         struct drm_i915_private *dev_priv = dev->dev_private;
4952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4953         struct intel_encoder *encoder;
4954         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4955         struct intel_crtc_state *pipe_config =
4956                 to_intel_crtc_state(crtc->state);
4957         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4958
4959         if (WARN_ON(intel_crtc->active))
4960                 return;
4961
4962         if (intel_crtc_to_shared_dpll(intel_crtc))
4963                 intel_enable_shared_dpll(intel_crtc);
4964
4965         if (intel_crtc->config->has_dp_encoder)
4966                 intel_dp_set_m_n(intel_crtc, M1_N1);
4967
4968         intel_set_pipe_timings(intel_crtc);
4969
4970         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4971                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4972                            intel_crtc->config->pixel_multiplier - 1);
4973         }
4974
4975         if (intel_crtc->config->has_pch_encoder) {
4976                 intel_cpu_transcoder_set_m_n(intel_crtc,
4977                                      &intel_crtc->config->fdi_m_n, NULL);
4978         }
4979
4980         haswell_set_pipeconf(crtc);
4981
4982         intel_set_pipe_csc(crtc);
4983
4984         intel_crtc->active = true;
4985
4986         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4987         for_each_encoder_on_crtc(dev, crtc, encoder) {
4988                 if (encoder->pre_pll_enable)
4989                         encoder->pre_pll_enable(encoder);
4990                 if (encoder->pre_enable)
4991                         encoder->pre_enable(encoder);
4992         }
4993
4994         if (intel_crtc->config->has_pch_encoder) {
4995                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4996                                                       true);
4997                 dev_priv->display.fdi_link_train(crtc);
4998         }
4999
5000         if (!is_dsi)
5001                 intel_ddi_enable_pipe_clock(intel_crtc);
5002
5003         if (INTEL_INFO(dev)->gen >= 9)
5004                 skylake_pfit_enable(intel_crtc);
5005         else
5006                 ironlake_pfit_enable(intel_crtc);
5007
5008         /*
5009          * On ILK+ LUT must be loaded before the pipe is running but with
5010          * clocks enabled
5011          */
5012         intel_crtc_load_lut(crtc);
5013
5014         intel_ddi_set_pipe_settings(crtc);
5015         if (!is_dsi)
5016                 intel_ddi_enable_transcoder_func(crtc);
5017
5018         intel_update_watermarks(crtc);
5019         intel_enable_pipe(intel_crtc);
5020
5021         if (intel_crtc->config->has_pch_encoder)
5022                 lpt_pch_enable(crtc);
5023
5024         if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5025                 intel_ddi_set_vc_payload_alloc(crtc, true);
5026
5027         assert_vblank_disabled(crtc);
5028         drm_crtc_vblank_on(crtc);
5029
5030         for_each_encoder_on_crtc(dev, crtc, encoder) {
5031                 encoder->enable(encoder);
5032                 intel_opregion_notify_encoder(encoder, true);
5033         }
5034
5035         /* If we change the relative order between pipe/planes enabling, we need
5036          * to change the workaround. */
5037         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5038         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5039                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5040                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5041         }
5042 }
5043
5044 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5045 {
5046         struct drm_device *dev = crtc->base.dev;
5047         struct drm_i915_private *dev_priv = dev->dev_private;
5048         int pipe = crtc->pipe;
5049
5050         /* To avoid upsetting the power well on haswell only disable the pfit if
5051          * it's in use. The hw state code will make sure we get this right. */
5052         if (force || crtc->config->pch_pfit.enabled) {
5053                 I915_WRITE(PF_CTL(pipe), 0);
5054                 I915_WRITE(PF_WIN_POS(pipe), 0);
5055                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5056         }
5057 }
5058
5059 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5060 {
5061         struct drm_device *dev = crtc->dev;
5062         struct drm_i915_private *dev_priv = dev->dev_private;
5063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5064         struct intel_encoder *encoder;
5065         int pipe = intel_crtc->pipe;
5066         u32 reg, temp;
5067
5068         for_each_encoder_on_crtc(dev, crtc, encoder)
5069                 encoder->disable(encoder);
5070
5071         drm_crtc_vblank_off(crtc);
5072         assert_vblank_disabled(crtc);
5073
5074         if (intel_crtc->config->has_pch_encoder)
5075                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5076
5077         intel_disable_pipe(intel_crtc);
5078
5079         ironlake_pfit_disable(intel_crtc, false);
5080
5081         if (intel_crtc->config->has_pch_encoder)
5082                 ironlake_fdi_disable(crtc);
5083
5084         for_each_encoder_on_crtc(dev, crtc, encoder)
5085                 if (encoder->post_disable)
5086                         encoder->post_disable(encoder);
5087
5088         if (intel_crtc->config->has_pch_encoder) {
5089                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5090
5091                 if (HAS_PCH_CPT(dev)) {
5092                         /* disable TRANS_DP_CTL */
5093                         reg = TRANS_DP_CTL(pipe);
5094                         temp = I915_READ(reg);
5095                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5096                                   TRANS_DP_PORT_SEL_MASK);
5097                         temp |= TRANS_DP_PORT_SEL_NONE;
5098                         I915_WRITE(reg, temp);
5099
5100                         /* disable DPLL_SEL */
5101                         temp = I915_READ(PCH_DPLL_SEL);
5102                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5103                         I915_WRITE(PCH_DPLL_SEL, temp);
5104                 }
5105
5106                 ironlake_fdi_pll_disable(intel_crtc);
5107         }
5108 }
5109
5110 static void haswell_crtc_disable(struct drm_crtc *crtc)
5111 {
5112         struct drm_device *dev = crtc->dev;
5113         struct drm_i915_private *dev_priv = dev->dev_private;
5114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115         struct intel_encoder *encoder;
5116         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5117         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5118
5119         for_each_encoder_on_crtc(dev, crtc, encoder) {
5120                 intel_opregion_notify_encoder(encoder, false);
5121                 encoder->disable(encoder);
5122         }
5123
5124         drm_crtc_vblank_off(crtc);
5125         assert_vblank_disabled(crtc);
5126
5127         if (intel_crtc->config->has_pch_encoder)
5128                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5129                                                       false);
5130         intel_disable_pipe(intel_crtc);
5131
5132         if (intel_crtc->config->dp_encoder_is_mst)
5133                 intel_ddi_set_vc_payload_alloc(crtc, false);
5134
5135         if (!is_dsi)
5136                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5137
5138         if (INTEL_INFO(dev)->gen >= 9)
5139                 skylake_scaler_disable(intel_crtc);
5140         else
5141                 ironlake_pfit_disable(intel_crtc, false);
5142
5143         if (!is_dsi)
5144                 intel_ddi_disable_pipe_clock(intel_crtc);
5145
5146         if (intel_crtc->config->has_pch_encoder) {
5147                 lpt_disable_pch_transcoder(dev_priv);
5148                 intel_ddi_fdi_disable(crtc);
5149         }
5150
5151         for_each_encoder_on_crtc(dev, crtc, encoder)
5152                 if (encoder->post_disable)
5153                         encoder->post_disable(encoder);
5154 }
5155
5156 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5157 {
5158         struct drm_device *dev = crtc->base.dev;
5159         struct drm_i915_private *dev_priv = dev->dev_private;
5160         struct intel_crtc_state *pipe_config = crtc->config;
5161
5162         if (!pipe_config->gmch_pfit.control)
5163                 return;
5164
5165         /*
5166          * The panel fitter should only be adjusted whilst the pipe is disabled,
5167          * according to register description and PRM.
5168          */
5169         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5170         assert_pipe_disabled(dev_priv, crtc->pipe);
5171
5172         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5173         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5174
5175         /* Border color in case we don't scale up to the full screen. Black by
5176          * default, change to something else for debugging. */
5177         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5178 }
5179
5180 static enum intel_display_power_domain port_to_power_domain(enum port port)
5181 {
5182         switch (port) {
5183         case PORT_A:
5184                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5185         case PORT_B:
5186                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5187         case PORT_C:
5188                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5189         case PORT_D:
5190                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5191         case PORT_E:
5192                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5193         default:
5194                 WARN_ON_ONCE(1);
5195                 return POWER_DOMAIN_PORT_OTHER;
5196         }
5197 }
5198
5199 #define for_each_power_domain(domain, mask)                             \
5200         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5201                 if ((1 << (domain)) & (mask))
5202
5203 enum intel_display_power_domain
5204 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5205 {
5206         struct drm_device *dev = intel_encoder->base.dev;
5207         struct intel_digital_port *intel_dig_port;
5208
5209         switch (intel_encoder->type) {
5210         case INTEL_OUTPUT_UNKNOWN:
5211                 /* Only DDI platforms should ever use this output type */
5212                 WARN_ON_ONCE(!HAS_DDI(dev));
5213         case INTEL_OUTPUT_DISPLAYPORT:
5214         case INTEL_OUTPUT_HDMI:
5215         case INTEL_OUTPUT_EDP:
5216                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5217                 return port_to_power_domain(intel_dig_port->port);
5218         case INTEL_OUTPUT_DP_MST:
5219                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5220                 return port_to_power_domain(intel_dig_port->port);
5221         case INTEL_OUTPUT_ANALOG:
5222                 return POWER_DOMAIN_PORT_CRT;
5223         case INTEL_OUTPUT_DSI:
5224                 return POWER_DOMAIN_PORT_DSI;
5225         default:
5226                 return POWER_DOMAIN_PORT_OTHER;
5227         }
5228 }
5229
5230 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5231 {
5232         struct drm_device *dev = crtc->dev;
5233         struct intel_encoder *intel_encoder;
5234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5235         enum pipe pipe = intel_crtc->pipe;
5236         unsigned long mask;
5237         enum transcoder transcoder;
5238
5239         if (!crtc->state->active)
5240                 return 0;
5241
5242         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5243
5244         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5245         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5246         if (intel_crtc->config->pch_pfit.enabled ||
5247             intel_crtc->config->pch_pfit.force_thru)
5248                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5249
5250         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5251                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5252
5253         return mask;
5254 }
5255
5256 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5257 {
5258         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5260         enum intel_display_power_domain domain;
5261         unsigned long domains, new_domains, old_domains;
5262
5263         old_domains = intel_crtc->enabled_power_domains;
5264         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5265
5266         domains = new_domains & ~old_domains;
5267
5268         for_each_power_domain(domain, domains)
5269                 intel_display_power_get(dev_priv, domain);
5270
5271         return old_domains & ~new_domains;
5272 }
5273
5274 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5275                                       unsigned long domains)
5276 {
5277         enum intel_display_power_domain domain;
5278
5279         for_each_power_domain(domain, domains)
5280                 intel_display_power_put(dev_priv, domain);
5281 }
5282
5283 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5284 {
5285         struct drm_device *dev = state->dev;
5286         struct drm_i915_private *dev_priv = dev->dev_private;
5287         unsigned long put_domains[I915_MAX_PIPES] = {};
5288         struct drm_crtc_state *crtc_state;
5289         struct drm_crtc *crtc;
5290         int i;
5291
5292         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5293                 if (needs_modeset(crtc->state))
5294                         put_domains[to_intel_crtc(crtc)->pipe] =
5295                                 modeset_get_crtc_power_domains(crtc);
5296         }
5297
5298         if (dev_priv->display.modeset_commit_cdclk) {
5299                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5300
5301                 if (cdclk != dev_priv->cdclk_freq &&
5302                     !WARN_ON(!state->allow_modeset))
5303                         dev_priv->display.modeset_commit_cdclk(state);
5304         }
5305
5306         for (i = 0; i < I915_MAX_PIPES; i++)
5307                 if (put_domains[i])
5308                         modeset_put_power_domains(dev_priv, put_domains[i]);
5309 }
5310
5311 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5312 {
5313         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5314
5315         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5316             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5317                 return max_cdclk_freq;
5318         else if (IS_CHERRYVIEW(dev_priv))
5319                 return max_cdclk_freq*95/100;
5320         else if (INTEL_INFO(dev_priv)->gen < 4)
5321                 return 2*max_cdclk_freq*90/100;
5322         else
5323                 return max_cdclk_freq*90/100;
5324 }
5325
5326 static void intel_update_max_cdclk(struct drm_device *dev)
5327 {
5328         struct drm_i915_private *dev_priv = dev->dev_private;
5329
5330         if (IS_SKYLAKE(dev)) {
5331                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5332
5333                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5334                         dev_priv->max_cdclk_freq = 675000;
5335                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5336                         dev_priv->max_cdclk_freq = 540000;
5337                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5338                         dev_priv->max_cdclk_freq = 450000;
5339                 else
5340                         dev_priv->max_cdclk_freq = 337500;
5341         } else if (IS_BROADWELL(dev))  {
5342                 /*
5343                  * FIXME with extra cooling we can allow
5344                  * 540 MHz for ULX and 675 Mhz for ULT.
5345                  * How can we know if extra cooling is
5346                  * available? PCI ID, VTB, something else?
5347                  */
5348                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5349                         dev_priv->max_cdclk_freq = 450000;
5350                 else if (IS_BDW_ULX(dev))
5351                         dev_priv->max_cdclk_freq = 450000;
5352                 else if (IS_BDW_ULT(dev))
5353                         dev_priv->max_cdclk_freq = 540000;
5354                 else
5355                         dev_priv->max_cdclk_freq = 675000;
5356         } else if (IS_CHERRYVIEW(dev)) {
5357                 dev_priv->max_cdclk_freq = 320000;
5358         } else if (IS_VALLEYVIEW(dev)) {
5359                 dev_priv->max_cdclk_freq = 400000;
5360         } else {
5361                 /* otherwise assume cdclk is fixed */
5362                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5363         }
5364
5365         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5366
5367         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5368                          dev_priv->max_cdclk_freq);
5369
5370         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5371                          dev_priv->max_dotclk_freq);
5372 }
5373
5374 static void intel_update_cdclk(struct drm_device *dev)
5375 {
5376         struct drm_i915_private *dev_priv = dev->dev_private;
5377
5378         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5379         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5380                          dev_priv->cdclk_freq);
5381
5382         /*
5383          * Program the gmbus_freq based on the cdclk frequency.
5384          * BSpec erroneously claims we should aim for 4MHz, but
5385          * in fact 1MHz is the correct frequency.
5386          */
5387         if (IS_VALLEYVIEW(dev)) {
5388                 /*
5389                  * Program the gmbus_freq based on the cdclk frequency.
5390                  * BSpec erroneously claims we should aim for 4MHz, but
5391                  * in fact 1MHz is the correct frequency.
5392                  */
5393                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5394         }
5395
5396         if (dev_priv->max_cdclk_freq == 0)
5397                 intel_update_max_cdclk(dev);
5398 }
5399
5400 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5401 {
5402         struct drm_i915_private *dev_priv = dev->dev_private;
5403         uint32_t divider;
5404         uint32_t ratio;
5405         uint32_t current_freq;
5406         int ret;
5407
5408         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5409         switch (frequency) {
5410         case 144000:
5411                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5412                 ratio = BXT_DE_PLL_RATIO(60);
5413                 break;
5414         case 288000:
5415                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5416                 ratio = BXT_DE_PLL_RATIO(60);
5417                 break;
5418         case 384000:
5419                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5420                 ratio = BXT_DE_PLL_RATIO(60);
5421                 break;
5422         case 576000:
5423                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5424                 ratio = BXT_DE_PLL_RATIO(60);
5425                 break;
5426         case 624000:
5427                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5428                 ratio = BXT_DE_PLL_RATIO(65);
5429                 break;
5430         case 19200:
5431                 /*
5432                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5433                  * to suppress GCC warning.
5434                  */
5435                 ratio = 0;
5436                 divider = 0;
5437                 break;
5438         default:
5439                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5440
5441                 return;
5442         }
5443
5444         mutex_lock(&dev_priv->rps.hw_lock);
5445         /* Inform power controller of upcoming frequency change */
5446         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5447                                       0x80000000);
5448         mutex_unlock(&dev_priv->rps.hw_lock);
5449
5450         if (ret) {
5451                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5452                           ret, frequency);
5453                 return;
5454         }
5455
5456         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5457         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5458         current_freq = current_freq * 500 + 1000;
5459
5460         /*
5461          * DE PLL has to be disabled when
5462          * - setting to 19.2MHz (bypass, PLL isn't used)
5463          * - before setting to 624MHz (PLL needs toggling)
5464          * - before setting to any frequency from 624MHz (PLL needs toggling)
5465          */
5466         if (frequency == 19200 || frequency == 624000 ||
5467             current_freq == 624000) {
5468                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5469                 /* Timeout 200us */
5470                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5471                              1))
5472                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5473         }
5474
5475         if (frequency != 19200) {
5476                 uint32_t val;
5477
5478                 val = I915_READ(BXT_DE_PLL_CTL);
5479                 val &= ~BXT_DE_PLL_RATIO_MASK;
5480                 val |= ratio;
5481                 I915_WRITE(BXT_DE_PLL_CTL, val);
5482
5483                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5484                 /* Timeout 200us */
5485                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5486                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5487
5488                 val = I915_READ(CDCLK_CTL);
5489                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5490                 val |= divider;
5491                 /*
5492                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5493                  * enable otherwise.
5494                  */
5495                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5496                 if (frequency >= 500000)
5497                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5498
5499                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5500                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5501                 val |= (frequency - 1000) / 500;
5502                 I915_WRITE(CDCLK_CTL, val);
5503         }
5504
5505         mutex_lock(&dev_priv->rps.hw_lock);
5506         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5507                                       DIV_ROUND_UP(frequency, 25000));
5508         mutex_unlock(&dev_priv->rps.hw_lock);
5509
5510         if (ret) {
5511                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5512                           ret, frequency);
5513                 return;
5514         }
5515
5516         intel_update_cdclk(dev);
5517 }
5518
5519 void broxton_init_cdclk(struct drm_device *dev)
5520 {
5521         struct drm_i915_private *dev_priv = dev->dev_private;
5522         uint32_t val;
5523
5524         /*
5525          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5526          * or else the reset will hang because there is no PCH to respond.
5527          * Move the handshake programming to initialization sequence.
5528          * Previously was left up to BIOS.
5529          */
5530         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5531         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5532         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5533
5534         /* Enable PG1 for cdclk */
5535         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5536
5537         /* check if cd clock is enabled */
5538         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5539                 DRM_DEBUG_KMS("Display already initialized\n");
5540                 return;
5541         }
5542
5543         /*
5544          * FIXME:
5545          * - The initial CDCLK needs to be read from VBT.
5546          *   Need to make this change after VBT has changes for BXT.
5547          * - check if setting the max (or any) cdclk freq is really necessary
5548          *   here, it belongs to modeset time
5549          */
5550         broxton_set_cdclk(dev, 624000);
5551
5552         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5553         POSTING_READ(DBUF_CTL);
5554
5555         udelay(10);
5556
5557         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5558                 DRM_ERROR("DBuf power enable timeout!\n");
5559 }
5560
5561 void broxton_uninit_cdclk(struct drm_device *dev)
5562 {
5563         struct drm_i915_private *dev_priv = dev->dev_private;
5564
5565         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5566         POSTING_READ(DBUF_CTL);
5567
5568         udelay(10);
5569
5570         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5571                 DRM_ERROR("DBuf power disable timeout!\n");
5572
5573         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5574         broxton_set_cdclk(dev, 19200);
5575
5576         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5577 }
5578
5579 static const struct skl_cdclk_entry {
5580         unsigned int freq;
5581         unsigned int vco;
5582 } skl_cdclk_frequencies[] = {
5583         { .freq = 308570, .vco = 8640 },
5584         { .freq = 337500, .vco = 8100 },
5585         { .freq = 432000, .vco = 8640 },
5586         { .freq = 450000, .vco = 8100 },
5587         { .freq = 540000, .vco = 8100 },
5588         { .freq = 617140, .vco = 8640 },
5589         { .freq = 675000, .vco = 8100 },
5590 };
5591
5592 static unsigned int skl_cdclk_decimal(unsigned int freq)
5593 {
5594         return (freq - 1000) / 500;
5595 }
5596
5597 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5598 {
5599         unsigned int i;
5600
5601         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5602                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5603
5604                 if (e->freq == freq)
5605                         return e->vco;
5606         }
5607
5608         return 8100;
5609 }
5610
5611 static void
5612 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5613 {
5614         unsigned int min_freq;
5615         u32 val;
5616
5617         /* select the minimum CDCLK before enabling DPLL 0 */
5618         val = I915_READ(CDCLK_CTL);
5619         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5620         val |= CDCLK_FREQ_337_308;
5621
5622         if (required_vco == 8640)
5623                 min_freq = 308570;
5624         else
5625                 min_freq = 337500;
5626
5627         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5628
5629         I915_WRITE(CDCLK_CTL, val);
5630         POSTING_READ(CDCLK_CTL);
5631
5632         /*
5633          * We always enable DPLL0 with the lowest link rate possible, but still
5634          * taking into account the VCO required to operate the eDP panel at the
5635          * desired frequency. The usual DP link rates operate with a VCO of
5636          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5637          * The modeset code is responsible for the selection of the exact link
5638          * rate later on, with the constraint of choosing a frequency that
5639          * works with required_vco.
5640          */
5641         val = I915_READ(DPLL_CTRL1);
5642
5643         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5644                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5645         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5646         if (required_vco == 8640)
5647                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5648                                             SKL_DPLL0);
5649         else
5650                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5651                                             SKL_DPLL0);
5652
5653         I915_WRITE(DPLL_CTRL1, val);
5654         POSTING_READ(DPLL_CTRL1);
5655
5656         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5657
5658         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5659                 DRM_ERROR("DPLL0 not locked\n");
5660 }
5661
5662 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5663 {
5664         int ret;
5665         u32 val;
5666
5667         /* inform PCU we want to change CDCLK */
5668         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5669         mutex_lock(&dev_priv->rps.hw_lock);
5670         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5671         mutex_unlock(&dev_priv->rps.hw_lock);
5672
5673         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5674 }
5675
5676 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5677 {
5678         unsigned int i;
5679
5680         for (i = 0; i < 15; i++) {
5681                 if (skl_cdclk_pcu_ready(dev_priv))
5682                         return true;
5683                 udelay(10);
5684         }
5685
5686         return false;
5687 }
5688
5689 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5690 {
5691         struct drm_device *dev = dev_priv->dev;
5692         u32 freq_select, pcu_ack;
5693
5694         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5695
5696         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5697                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5698                 return;
5699         }
5700
5701         /* set CDCLK_CTL */
5702         switch(freq) {
5703         case 450000:
5704         case 432000:
5705                 freq_select = CDCLK_FREQ_450_432;
5706                 pcu_ack = 1;
5707                 break;
5708         case 540000:
5709                 freq_select = CDCLK_FREQ_540;
5710                 pcu_ack = 2;
5711                 break;
5712         case 308570:
5713         case 337500:
5714         default:
5715                 freq_select = CDCLK_FREQ_337_308;
5716                 pcu_ack = 0;
5717                 break;
5718         case 617140:
5719         case 675000:
5720                 freq_select = CDCLK_FREQ_675_617;
5721                 pcu_ack = 3;
5722                 break;
5723         }
5724
5725         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5726         POSTING_READ(CDCLK_CTL);
5727
5728         /* inform PCU of the change */
5729         mutex_lock(&dev_priv->rps.hw_lock);
5730         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5731         mutex_unlock(&dev_priv->rps.hw_lock);
5732
5733         intel_update_cdclk(dev);
5734 }
5735
5736 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5737 {
5738         /* disable DBUF power */
5739         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5740         POSTING_READ(DBUF_CTL);
5741
5742         udelay(10);
5743
5744         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5745                 DRM_ERROR("DBuf power disable timeout\n");
5746
5747         /*
5748          * DMC assumes ownership of LCPLL and will get confused if we touch it.
5749          */
5750         if (dev_priv->csr.dmc_payload) {
5751                 /* disable DPLL0 */
5752                 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5753                                         ~LCPLL_PLL_ENABLE);
5754                 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5755                         DRM_ERROR("Couldn't disable DPLL0\n");
5756         }
5757
5758         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5759 }
5760
5761 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5762 {
5763         u32 val;
5764         unsigned int required_vco;
5765
5766         /* enable PCH reset handshake */
5767         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5768         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5769
5770         /* enable PG1 and Misc I/O */
5771         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5772
5773         /* DPLL0 not enabled (happens on early BIOS versions) */
5774         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5775                 /* enable DPLL0 */
5776                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5777                 skl_dpll0_enable(dev_priv, required_vco);
5778         }
5779
5780         /* set CDCLK to the frequency the BIOS chose */
5781         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5782
5783         /* enable DBUF power */
5784         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5785         POSTING_READ(DBUF_CTL);
5786
5787         udelay(10);
5788
5789         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5790                 DRM_ERROR("DBuf power enable timeout\n");
5791 }
5792
5793 /* Adjust CDclk dividers to allow high res or save power if possible */
5794 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5795 {
5796         struct drm_i915_private *dev_priv = dev->dev_private;
5797         u32 val, cmd;
5798
5799         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5800                                         != dev_priv->cdclk_freq);
5801
5802         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5803                 cmd = 2;
5804         else if (cdclk == 266667)
5805                 cmd = 1;
5806         else
5807                 cmd = 0;
5808
5809         mutex_lock(&dev_priv->rps.hw_lock);
5810         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5811         val &= ~DSPFREQGUAR_MASK;
5812         val |= (cmd << DSPFREQGUAR_SHIFT);
5813         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5814         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5815                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5816                      50)) {
5817                 DRM_ERROR("timed out waiting for CDclk change\n");
5818         }
5819         mutex_unlock(&dev_priv->rps.hw_lock);
5820
5821         mutex_lock(&dev_priv->sb_lock);
5822
5823         if (cdclk == 400000) {
5824                 u32 divider;
5825
5826                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5827
5828                 /* adjust cdclk divider */
5829                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5830                 val &= ~CCK_FREQUENCY_VALUES;
5831                 val |= divider;
5832                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5833
5834                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5835                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5836                              50))
5837                         DRM_ERROR("timed out waiting for CDclk change\n");
5838         }
5839
5840         /* adjust self-refresh exit latency value */
5841         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5842         val &= ~0x7f;
5843
5844         /*
5845          * For high bandwidth configs, we set a higher latency in the bunit
5846          * so that the core display fetch happens in time to avoid underruns.
5847          */
5848         if (cdclk == 400000)
5849                 val |= 4500 / 250; /* 4.5 usec */
5850         else
5851                 val |= 3000 / 250; /* 3.0 usec */
5852         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5853
5854         mutex_unlock(&dev_priv->sb_lock);
5855
5856         intel_update_cdclk(dev);
5857 }
5858
5859 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5860 {
5861         struct drm_i915_private *dev_priv = dev->dev_private;
5862         u32 val, cmd;
5863
5864         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5865                                                 != dev_priv->cdclk_freq);
5866
5867         switch (cdclk) {
5868         case 333333:
5869         case 320000:
5870         case 266667:
5871         case 200000:
5872                 break;
5873         default:
5874                 MISSING_CASE(cdclk);
5875                 return;
5876         }
5877
5878         /*
5879          * Specs are full of misinformation, but testing on actual
5880          * hardware has shown that we just need to write the desired
5881          * CCK divider into the Punit register.
5882          */
5883         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5884
5885         mutex_lock(&dev_priv->rps.hw_lock);
5886         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5887         val &= ~DSPFREQGUAR_MASK_CHV;
5888         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5889         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5890         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5891                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5892                      50)) {
5893                 DRM_ERROR("timed out waiting for CDclk change\n");
5894         }
5895         mutex_unlock(&dev_priv->rps.hw_lock);
5896
5897         intel_update_cdclk(dev);
5898 }
5899
5900 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5901                                  int max_pixclk)
5902 {
5903         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5904         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5905
5906         /*
5907          * Really only a few cases to deal with, as only 4 CDclks are supported:
5908          *   200MHz
5909          *   267MHz
5910          *   320/333MHz (depends on HPLL freq)
5911          *   400MHz (VLV only)
5912          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5913          * of the lower bin and adjust if needed.
5914          *
5915          * We seem to get an unstable or solid color picture at 200MHz.
5916          * Not sure what's wrong. For now use 200MHz only when all pipes
5917          * are off.
5918          */
5919         if (!IS_CHERRYVIEW(dev_priv) &&
5920             max_pixclk > freq_320*limit/100)
5921                 return 400000;
5922         else if (max_pixclk > 266667*limit/100)
5923                 return freq_320;
5924         else if (max_pixclk > 0)
5925                 return 266667;
5926         else
5927                 return 200000;
5928 }
5929
5930 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5931                               int max_pixclk)
5932 {
5933         /*
5934          * FIXME:
5935          * - remove the guardband, it's not needed on BXT
5936          * - set 19.2MHz bypass frequency if there are no active pipes
5937          */
5938         if (max_pixclk > 576000*9/10)
5939                 return 624000;
5940         else if (max_pixclk > 384000*9/10)
5941                 return 576000;
5942         else if (max_pixclk > 288000*9/10)
5943                 return 384000;
5944         else if (max_pixclk > 144000*9/10)
5945                 return 288000;
5946         else
5947                 return 144000;
5948 }
5949
5950 /* Compute the max pixel clock for new configuration. Uses atomic state if
5951  * that's non-NULL, look at current state otherwise. */
5952 static int intel_mode_max_pixclk(struct drm_device *dev,
5953                                  struct drm_atomic_state *state)
5954 {
5955         struct intel_crtc *intel_crtc;
5956         struct intel_crtc_state *crtc_state;
5957         int max_pixclk = 0;
5958
5959         for_each_intel_crtc(dev, intel_crtc) {
5960                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5961                 if (IS_ERR(crtc_state))
5962                         return PTR_ERR(crtc_state);
5963
5964                 if (!crtc_state->base.enable)
5965                         continue;
5966
5967                 max_pixclk = max(max_pixclk,
5968                                  crtc_state->base.adjusted_mode.crtc_clock);
5969         }
5970
5971         return max_pixclk;
5972 }
5973
5974 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5975 {
5976         struct drm_device *dev = state->dev;
5977         struct drm_i915_private *dev_priv = dev->dev_private;
5978         int max_pixclk = intel_mode_max_pixclk(dev, state);
5979
5980         if (max_pixclk < 0)
5981                 return max_pixclk;
5982
5983         to_intel_atomic_state(state)->cdclk =
5984                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5985
5986         return 0;
5987 }
5988
5989 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5990 {
5991         struct drm_device *dev = state->dev;
5992         struct drm_i915_private *dev_priv = dev->dev_private;
5993         int max_pixclk = intel_mode_max_pixclk(dev, state);
5994
5995         if (max_pixclk < 0)
5996                 return max_pixclk;
5997
5998         to_intel_atomic_state(state)->cdclk =
5999                 broxton_calc_cdclk(dev_priv, max_pixclk);
6000
6001         return 0;
6002 }
6003
6004 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6005 {
6006         unsigned int credits, default_credits;
6007
6008         if (IS_CHERRYVIEW(dev_priv))
6009                 default_credits = PFI_CREDIT(12);
6010         else
6011                 default_credits = PFI_CREDIT(8);
6012
6013         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6014                 /* CHV suggested value is 31 or 63 */
6015                 if (IS_CHERRYVIEW(dev_priv))
6016                         credits = PFI_CREDIT_63;
6017                 else
6018                         credits = PFI_CREDIT(15);
6019         } else {
6020                 credits = default_credits;
6021         }
6022
6023         /*
6024          * WA - write default credits before re-programming
6025          * FIXME: should we also set the resend bit here?
6026          */
6027         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6028                    default_credits);
6029
6030         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6031                    credits | PFI_CREDIT_RESEND);
6032
6033         /*
6034          * FIXME is this guaranteed to clear
6035          * immediately or should we poll for it?
6036          */
6037         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6038 }
6039
6040 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6041 {
6042         struct drm_device *dev = old_state->dev;
6043         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6044         struct drm_i915_private *dev_priv = dev->dev_private;
6045
6046         /*
6047          * FIXME: We can end up here with all power domains off, yet
6048          * with a CDCLK frequency other than the minimum. To account
6049          * for this take the PIPE-A power domain, which covers the HW
6050          * blocks needed for the following programming. This can be
6051          * removed once it's guaranteed that we get here either with
6052          * the minimum CDCLK set, or the required power domains
6053          * enabled.
6054          */
6055         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6056
6057         if (IS_CHERRYVIEW(dev))
6058                 cherryview_set_cdclk(dev, req_cdclk);
6059         else
6060                 valleyview_set_cdclk(dev, req_cdclk);
6061
6062         vlv_program_pfi_credits(dev_priv);
6063
6064         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6065 }
6066
6067 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6068 {
6069         struct drm_device *dev = crtc->dev;
6070         struct drm_i915_private *dev_priv = to_i915(dev);
6071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6072         struct intel_encoder *encoder;
6073         int pipe = intel_crtc->pipe;
6074         bool is_dsi;
6075
6076         if (WARN_ON(intel_crtc->active))
6077                 return;
6078
6079         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6080
6081         if (intel_crtc->config->has_dp_encoder)
6082                 intel_dp_set_m_n(intel_crtc, M1_N1);
6083
6084         intel_set_pipe_timings(intel_crtc);
6085
6086         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6087                 struct drm_i915_private *dev_priv = dev->dev_private;
6088
6089                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6090                 I915_WRITE(CHV_CANVAS(pipe), 0);
6091         }
6092
6093         i9xx_set_pipeconf(intel_crtc);
6094
6095         intel_crtc->active = true;
6096
6097         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6098
6099         for_each_encoder_on_crtc(dev, crtc, encoder)
6100                 if (encoder->pre_pll_enable)
6101                         encoder->pre_pll_enable(encoder);
6102
6103         if (!is_dsi) {
6104                 if (IS_CHERRYVIEW(dev)) {
6105                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6106                         chv_enable_pll(intel_crtc, intel_crtc->config);
6107                 } else {
6108                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6109                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6110                 }
6111         }
6112
6113         for_each_encoder_on_crtc(dev, crtc, encoder)
6114                 if (encoder->pre_enable)
6115                         encoder->pre_enable(encoder);
6116
6117         i9xx_pfit_enable(intel_crtc);
6118
6119         intel_crtc_load_lut(crtc);
6120
6121         intel_enable_pipe(intel_crtc);
6122
6123         assert_vblank_disabled(crtc);
6124         drm_crtc_vblank_on(crtc);
6125
6126         for_each_encoder_on_crtc(dev, crtc, encoder)
6127                 encoder->enable(encoder);
6128 }
6129
6130 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6131 {
6132         struct drm_device *dev = crtc->base.dev;
6133         struct drm_i915_private *dev_priv = dev->dev_private;
6134
6135         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6136         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6137 }
6138
6139 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6140 {
6141         struct drm_device *dev = crtc->dev;
6142         struct drm_i915_private *dev_priv = to_i915(dev);
6143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6144         struct intel_encoder *encoder;
6145         int pipe = intel_crtc->pipe;
6146
6147         if (WARN_ON(intel_crtc->active))
6148                 return;
6149
6150         i9xx_set_pll_dividers(intel_crtc);
6151
6152         if (intel_crtc->config->has_dp_encoder)
6153                 intel_dp_set_m_n(intel_crtc, M1_N1);
6154
6155         intel_set_pipe_timings(intel_crtc);
6156
6157         i9xx_set_pipeconf(intel_crtc);
6158
6159         intel_crtc->active = true;
6160
6161         if (!IS_GEN2(dev))
6162                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6163
6164         for_each_encoder_on_crtc(dev, crtc, encoder)
6165                 if (encoder->pre_enable)
6166                         encoder->pre_enable(encoder);
6167
6168         i9xx_enable_pll(intel_crtc);
6169
6170         i9xx_pfit_enable(intel_crtc);
6171
6172         intel_crtc_load_lut(crtc);
6173
6174         intel_update_watermarks(crtc);
6175         intel_enable_pipe(intel_crtc);
6176
6177         assert_vblank_disabled(crtc);
6178         drm_crtc_vblank_on(crtc);
6179
6180         for_each_encoder_on_crtc(dev, crtc, encoder)
6181                 encoder->enable(encoder);
6182 }
6183
6184 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6185 {
6186         struct drm_device *dev = crtc->base.dev;
6187         struct drm_i915_private *dev_priv = dev->dev_private;
6188
6189         if (!crtc->config->gmch_pfit.control)
6190                 return;
6191
6192         assert_pipe_disabled(dev_priv, crtc->pipe);
6193
6194         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6195                          I915_READ(PFIT_CONTROL));
6196         I915_WRITE(PFIT_CONTROL, 0);
6197 }
6198
6199 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6200 {
6201         struct drm_device *dev = crtc->dev;
6202         struct drm_i915_private *dev_priv = dev->dev_private;
6203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6204         struct intel_encoder *encoder;
6205         int pipe = intel_crtc->pipe;
6206
6207         /*
6208          * On gen2 planes are double buffered but the pipe isn't, so we must
6209          * wait for planes to fully turn off before disabling the pipe.
6210          * We also need to wait on all gmch platforms because of the
6211          * self-refresh mode constraint explained above.
6212          */
6213         intel_wait_for_vblank(dev, pipe);
6214
6215         for_each_encoder_on_crtc(dev, crtc, encoder)
6216                 encoder->disable(encoder);
6217
6218         drm_crtc_vblank_off(crtc);
6219         assert_vblank_disabled(crtc);
6220
6221         intel_disable_pipe(intel_crtc);
6222
6223         i9xx_pfit_disable(intel_crtc);
6224
6225         for_each_encoder_on_crtc(dev, crtc, encoder)
6226                 if (encoder->post_disable)
6227                         encoder->post_disable(encoder);
6228
6229         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6230                 if (IS_CHERRYVIEW(dev))
6231                         chv_disable_pll(dev_priv, pipe);
6232                 else if (IS_VALLEYVIEW(dev))
6233                         vlv_disable_pll(dev_priv, pipe);
6234                 else
6235                         i9xx_disable_pll(intel_crtc);
6236         }
6237
6238         for_each_encoder_on_crtc(dev, crtc, encoder)
6239                 if (encoder->post_pll_disable)
6240                         encoder->post_pll_disable(encoder);
6241
6242         if (!IS_GEN2(dev))
6243                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6244 }
6245
6246 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6247 {
6248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6249         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6250         enum intel_display_power_domain domain;
6251         unsigned long domains;
6252
6253         if (!intel_crtc->active)
6254                 return;
6255
6256         if (to_intel_plane_state(crtc->primary->state)->visible) {
6257                 intel_crtc_wait_for_pending_flips(crtc);
6258                 intel_pre_disable_primary(crtc);
6259         }
6260
6261         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6262         dev_priv->display.crtc_disable(crtc);
6263         intel_crtc->active = false;
6264         intel_update_watermarks(crtc);
6265         intel_disable_shared_dpll(intel_crtc);
6266
6267         domains = intel_crtc->enabled_power_domains;
6268         for_each_power_domain(domain, domains)
6269                 intel_display_power_put(dev_priv, domain);
6270         intel_crtc->enabled_power_domains = 0;
6271 }
6272
6273 /*
6274  * turn all crtc's off, but do not adjust state
6275  * This has to be paired with a call to intel_modeset_setup_hw_state.
6276  */
6277 int intel_display_suspend(struct drm_device *dev)
6278 {
6279         struct drm_mode_config *config = &dev->mode_config;
6280         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6281         struct drm_atomic_state *state;
6282         struct drm_crtc *crtc;
6283         unsigned crtc_mask = 0;
6284         int ret = 0;
6285
6286         if (WARN_ON(!ctx))
6287                 return 0;
6288
6289         lockdep_assert_held(&ctx->ww_ctx);
6290         state = drm_atomic_state_alloc(dev);
6291         if (WARN_ON(!state))
6292                 return -ENOMEM;
6293
6294         state->acquire_ctx = ctx;
6295         state->allow_modeset = true;
6296
6297         for_each_crtc(dev, crtc) {
6298                 struct drm_crtc_state *crtc_state =
6299                         drm_atomic_get_crtc_state(state, crtc);
6300
6301                 ret = PTR_ERR_OR_ZERO(crtc_state);
6302                 if (ret)
6303                         goto free;
6304
6305                 if (!crtc_state->active)
6306                         continue;
6307
6308                 crtc_state->active = false;
6309                 crtc_mask |= 1 << drm_crtc_index(crtc);
6310         }
6311
6312         if (crtc_mask) {
6313                 ret = drm_atomic_commit(state);
6314
6315                 if (!ret) {
6316                         for_each_crtc(dev, crtc)
6317                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6318                                         crtc->state->active = true;
6319
6320                         return ret;
6321                 }
6322         }
6323
6324 free:
6325         if (ret)
6326                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6327         drm_atomic_state_free(state);
6328         return ret;
6329 }
6330
6331 void intel_encoder_destroy(struct drm_encoder *encoder)
6332 {
6333         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6334
6335         drm_encoder_cleanup(encoder);
6336         kfree(intel_encoder);
6337 }
6338
6339 /* Cross check the actual hw state with our own modeset state tracking (and it's
6340  * internal consistency). */
6341 static void intel_connector_check_state(struct intel_connector *connector)
6342 {
6343         struct drm_crtc *crtc = connector->base.state->crtc;
6344
6345         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6346                       connector->base.base.id,
6347                       connector->base.name);
6348
6349         if (connector->get_hw_state(connector)) {
6350                 struct intel_encoder *encoder = connector->encoder;
6351                 struct drm_connector_state *conn_state = connector->base.state;
6352
6353                 I915_STATE_WARN(!crtc,
6354                          "connector enabled without attached crtc\n");
6355
6356                 if (!crtc)
6357                         return;
6358
6359                 I915_STATE_WARN(!crtc->state->active,
6360                       "connector is active, but attached crtc isn't\n");
6361
6362                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6363                         return;
6364
6365                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6366                         "atomic encoder doesn't match attached encoder\n");
6367
6368                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6369                         "attached encoder crtc differs from connector crtc\n");
6370         } else {
6371                 I915_STATE_WARN(crtc && crtc->state->active,
6372                         "attached crtc is active, but connector isn't\n");
6373                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6374                         "best encoder set without crtc!\n");
6375         }
6376 }
6377
6378 int intel_connector_init(struct intel_connector *connector)
6379 {
6380         struct drm_connector_state *connector_state;
6381
6382         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6383         if (!connector_state)
6384                 return -ENOMEM;
6385
6386         connector->base.state = connector_state;
6387         return 0;
6388 }
6389
6390 struct intel_connector *intel_connector_alloc(void)
6391 {
6392         struct intel_connector *connector;
6393
6394         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6395         if (!connector)
6396                 return NULL;
6397
6398         if (intel_connector_init(connector) < 0) {
6399                 kfree(connector);
6400                 return NULL;
6401         }
6402
6403         return connector;
6404 }
6405
6406 /* Simple connector->get_hw_state implementation for encoders that support only
6407  * one connector and no cloning and hence the encoder state determines the state
6408  * of the connector. */
6409 bool intel_connector_get_hw_state(struct intel_connector *connector)
6410 {
6411         enum pipe pipe = 0;
6412         struct intel_encoder *encoder = connector->encoder;
6413
6414         return encoder->get_hw_state(encoder, &pipe);
6415 }
6416
6417 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6418 {
6419         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6420                 return crtc_state->fdi_lanes;
6421
6422         return 0;
6423 }
6424
6425 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6426                                      struct intel_crtc_state *pipe_config)
6427 {
6428         struct drm_atomic_state *state = pipe_config->base.state;
6429         struct intel_crtc *other_crtc;
6430         struct intel_crtc_state *other_crtc_state;
6431
6432         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6433                       pipe_name(pipe), pipe_config->fdi_lanes);
6434         if (pipe_config->fdi_lanes > 4) {
6435                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6436                               pipe_name(pipe), pipe_config->fdi_lanes);
6437                 return -EINVAL;
6438         }
6439
6440         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6441                 if (pipe_config->fdi_lanes > 2) {
6442                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6443                                       pipe_config->fdi_lanes);
6444                         return -EINVAL;
6445                 } else {
6446                         return 0;
6447                 }
6448         }
6449
6450         if (INTEL_INFO(dev)->num_pipes == 2)
6451                 return 0;
6452
6453         /* Ivybridge 3 pipe is really complicated */
6454         switch (pipe) {
6455         case PIPE_A:
6456                 return 0;
6457         case PIPE_B:
6458                 if (pipe_config->fdi_lanes <= 2)
6459                         return 0;
6460
6461                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6462                 other_crtc_state =
6463                         intel_atomic_get_crtc_state(state, other_crtc);
6464                 if (IS_ERR(other_crtc_state))
6465                         return PTR_ERR(other_crtc_state);
6466
6467                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6468                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6469                                       pipe_name(pipe), pipe_config->fdi_lanes);
6470                         return -EINVAL;
6471                 }
6472                 return 0;
6473         case PIPE_C:
6474                 if (pipe_config->fdi_lanes > 2) {
6475                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6476                                       pipe_name(pipe), pipe_config->fdi_lanes);
6477                         return -EINVAL;
6478                 }
6479
6480                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6481                 other_crtc_state =
6482                         intel_atomic_get_crtc_state(state, other_crtc);
6483                 if (IS_ERR(other_crtc_state))
6484                         return PTR_ERR(other_crtc_state);
6485
6486                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6487                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6488                         return -EINVAL;
6489                 }
6490                 return 0;
6491         default:
6492                 BUG();
6493         }
6494 }
6495
6496 #define RETRY 1
6497 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6498                                        struct intel_crtc_state *pipe_config)
6499 {
6500         struct drm_device *dev = intel_crtc->base.dev;
6501         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6502         int lane, link_bw, fdi_dotclock, ret;
6503         bool needs_recompute = false;
6504
6505 retry:
6506         /* FDI is a binary signal running at ~2.7GHz, encoding
6507          * each output octet as 10 bits. The actual frequency
6508          * is stored as a divider into a 100MHz clock, and the
6509          * mode pixel clock is stored in units of 1KHz.
6510          * Hence the bw of each lane in terms of the mode signal
6511          * is:
6512          */
6513         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6514
6515         fdi_dotclock = adjusted_mode->crtc_clock;
6516
6517         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6518                                            pipe_config->pipe_bpp);
6519
6520         pipe_config->fdi_lanes = lane;
6521
6522         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6523                                link_bw, &pipe_config->fdi_m_n);
6524
6525         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6526                                        intel_crtc->pipe, pipe_config);
6527         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6528                 pipe_config->pipe_bpp -= 2*3;
6529                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6530                               pipe_config->pipe_bpp);
6531                 needs_recompute = true;
6532                 pipe_config->bw_constrained = true;
6533
6534                 goto retry;
6535         }
6536
6537         if (needs_recompute)
6538                 return RETRY;
6539
6540         return ret;
6541 }
6542
6543 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6544                                      struct intel_crtc_state *pipe_config)
6545 {
6546         if (pipe_config->pipe_bpp > 24)
6547                 return false;
6548
6549         /* HSW can handle pixel rate up to cdclk? */
6550         if (IS_HASWELL(dev_priv->dev))
6551                 return true;
6552
6553         /*
6554          * We compare against max which means we must take
6555          * the increased cdclk requirement into account when
6556          * calculating the new cdclk.
6557          *
6558          * Should measure whether using a lower cdclk w/o IPS
6559          */
6560         return ilk_pipe_pixel_rate(pipe_config) <=
6561                 dev_priv->max_cdclk_freq * 95 / 100;
6562 }
6563
6564 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6565                                    struct intel_crtc_state *pipe_config)
6566 {
6567         struct drm_device *dev = crtc->base.dev;
6568         struct drm_i915_private *dev_priv = dev->dev_private;
6569
6570         pipe_config->ips_enabled = i915.enable_ips &&
6571                 hsw_crtc_supports_ips(crtc) &&
6572                 pipe_config_supports_ips(dev_priv, pipe_config);
6573 }
6574
6575 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6576                                      struct intel_crtc_state *pipe_config)
6577 {
6578         struct drm_device *dev = crtc->base.dev;
6579         struct drm_i915_private *dev_priv = dev->dev_private;
6580         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6581
6582         /* FIXME should check pixel clock limits on all platforms */
6583         if (INTEL_INFO(dev)->gen < 4) {
6584                 int clock_limit = dev_priv->max_cdclk_freq;
6585
6586                 /*
6587                  * Enable pixel doubling when the dot clock
6588                  * is > 90% of the (display) core speed.
6589                  *
6590                  * GDG double wide on either pipe,
6591                  * otherwise pipe A only.
6592                  */
6593                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6594                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6595                         clock_limit *= 2;
6596                         pipe_config->double_wide = true;
6597                 }
6598
6599                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6600                         return -EINVAL;
6601         }
6602
6603         /*
6604          * Pipe horizontal size must be even in:
6605          * - DVO ganged mode
6606          * - LVDS dual channel mode
6607          * - Double wide pipe
6608          */
6609         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6610              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6611                 pipe_config->pipe_src_w &= ~1;
6612
6613         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6614          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6615          */
6616         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6617                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6618                 return -EINVAL;
6619
6620         if (HAS_IPS(dev))
6621                 hsw_compute_ips_config(crtc, pipe_config);
6622
6623         if (pipe_config->has_pch_encoder)
6624                 return ironlake_fdi_compute_config(crtc, pipe_config);
6625
6626         return 0;
6627 }
6628
6629 static int skylake_get_display_clock_speed(struct drm_device *dev)
6630 {
6631         struct drm_i915_private *dev_priv = to_i915(dev);
6632         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6633         uint32_t cdctl = I915_READ(CDCLK_CTL);
6634         uint32_t linkrate;
6635
6636         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6637                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6638
6639         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6640                 return 540000;
6641
6642         linkrate = (I915_READ(DPLL_CTRL1) &
6643                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6644
6645         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6646             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6647                 /* vco 8640 */
6648                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6649                 case CDCLK_FREQ_450_432:
6650                         return 432000;
6651                 case CDCLK_FREQ_337_308:
6652                         return 308570;
6653                 case CDCLK_FREQ_675_617:
6654                         return 617140;
6655                 default:
6656                         WARN(1, "Unknown cd freq selection\n");
6657                 }
6658         } else {
6659                 /* vco 8100 */
6660                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6661                 case CDCLK_FREQ_450_432:
6662                         return 450000;
6663                 case CDCLK_FREQ_337_308:
6664                         return 337500;
6665                 case CDCLK_FREQ_675_617:
6666                         return 675000;
6667                 default:
6668                         WARN(1, "Unknown cd freq selection\n");
6669                 }
6670         }
6671
6672         /* error case, do as if DPLL0 isn't enabled */
6673         return 24000;
6674 }
6675
6676 static int broxton_get_display_clock_speed(struct drm_device *dev)
6677 {
6678         struct drm_i915_private *dev_priv = to_i915(dev);
6679         uint32_t cdctl = I915_READ(CDCLK_CTL);
6680         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6681         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6682         int cdclk;
6683
6684         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6685                 return 19200;
6686
6687         cdclk = 19200 * pll_ratio / 2;
6688
6689         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6690         case BXT_CDCLK_CD2X_DIV_SEL_1:
6691                 return cdclk;  /* 576MHz or 624MHz */
6692         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6693                 return cdclk * 2 / 3; /* 384MHz */
6694         case BXT_CDCLK_CD2X_DIV_SEL_2:
6695                 return cdclk / 2; /* 288MHz */
6696         case BXT_CDCLK_CD2X_DIV_SEL_4:
6697                 return cdclk / 4; /* 144MHz */
6698         }
6699
6700         /* error case, do as if DE PLL isn't enabled */
6701         return 19200;
6702 }
6703
6704 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6705 {
6706         struct drm_i915_private *dev_priv = dev->dev_private;
6707         uint32_t lcpll = I915_READ(LCPLL_CTL);
6708         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6709
6710         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6711                 return 800000;
6712         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6713                 return 450000;
6714         else if (freq == LCPLL_CLK_FREQ_450)
6715                 return 450000;
6716         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6717                 return 540000;
6718         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6719                 return 337500;
6720         else
6721                 return 675000;
6722 }
6723
6724 static int haswell_get_display_clock_speed(struct drm_device *dev)
6725 {
6726         struct drm_i915_private *dev_priv = dev->dev_private;
6727         uint32_t lcpll = I915_READ(LCPLL_CTL);
6728         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6729
6730         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6731                 return 800000;
6732         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6733                 return 450000;
6734         else if (freq == LCPLL_CLK_FREQ_450)
6735                 return 450000;
6736         else if (IS_HSW_ULT(dev))
6737                 return 337500;
6738         else
6739                 return 540000;
6740 }
6741
6742 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6743 {
6744         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6745                                       CCK_DISPLAY_CLOCK_CONTROL);
6746 }
6747
6748 static int ilk_get_display_clock_speed(struct drm_device *dev)
6749 {
6750         return 450000;
6751 }
6752
6753 static int i945_get_display_clock_speed(struct drm_device *dev)
6754 {
6755         return 400000;
6756 }
6757
6758 static int i915_get_display_clock_speed(struct drm_device *dev)
6759 {
6760         return 333333;
6761 }
6762
6763 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6764 {
6765         return 200000;
6766 }
6767
6768 static int pnv_get_display_clock_speed(struct drm_device *dev)
6769 {
6770         u16 gcfgc = 0;
6771
6772         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6773
6774         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6775         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6776                 return 266667;
6777         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6778                 return 333333;
6779         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6780                 return 444444;
6781         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6782                 return 200000;
6783         default:
6784                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6785         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6786                 return 133333;
6787         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6788                 return 166667;
6789         }
6790 }
6791
6792 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6793 {
6794         u16 gcfgc = 0;
6795
6796         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6797
6798         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6799                 return 133333;
6800         else {
6801                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6802                 case GC_DISPLAY_CLOCK_333_MHZ:
6803                         return 333333;
6804                 default:
6805                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6806                         return 190000;
6807                 }
6808         }
6809 }
6810
6811 static int i865_get_display_clock_speed(struct drm_device *dev)
6812 {
6813         return 266667;
6814 }
6815
6816 static int i85x_get_display_clock_speed(struct drm_device *dev)
6817 {
6818         u16 hpllcc = 0;
6819
6820         /*
6821          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6822          * encoding is different :(
6823          * FIXME is this the right way to detect 852GM/852GMV?
6824          */
6825         if (dev->pdev->revision == 0x1)
6826                 return 133333;
6827
6828         pci_bus_read_config_word(dev->pdev->bus,
6829                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6830
6831         /* Assume that the hardware is in the high speed state.  This
6832          * should be the default.
6833          */
6834         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6835         case GC_CLOCK_133_200:
6836         case GC_CLOCK_133_200_2:
6837         case GC_CLOCK_100_200:
6838                 return 200000;
6839         case GC_CLOCK_166_250:
6840                 return 250000;
6841         case GC_CLOCK_100_133:
6842                 return 133333;
6843         case GC_CLOCK_133_266:
6844         case GC_CLOCK_133_266_2:
6845         case GC_CLOCK_166_266:
6846                 return 266667;
6847         }
6848
6849         /* Shouldn't happen */
6850         return 0;
6851 }
6852
6853 static int i830_get_display_clock_speed(struct drm_device *dev)
6854 {
6855         return 133333;
6856 }
6857
6858 static unsigned int intel_hpll_vco(struct drm_device *dev)
6859 {
6860         struct drm_i915_private *dev_priv = dev->dev_private;
6861         static const unsigned int blb_vco[8] = {
6862                 [0] = 3200000,
6863                 [1] = 4000000,
6864                 [2] = 5333333,
6865                 [3] = 4800000,
6866                 [4] = 6400000,
6867         };
6868         static const unsigned int pnv_vco[8] = {
6869                 [0] = 3200000,
6870                 [1] = 4000000,
6871                 [2] = 5333333,
6872                 [3] = 4800000,
6873                 [4] = 2666667,
6874         };
6875         static const unsigned int cl_vco[8] = {
6876                 [0] = 3200000,
6877                 [1] = 4000000,
6878                 [2] = 5333333,
6879                 [3] = 6400000,
6880                 [4] = 3333333,
6881                 [5] = 3566667,
6882                 [6] = 4266667,
6883         };
6884         static const unsigned int elk_vco[8] = {
6885                 [0] = 3200000,
6886                 [1] = 4000000,
6887                 [2] = 5333333,
6888                 [3] = 4800000,
6889         };
6890         static const unsigned int ctg_vco[8] = {
6891                 [0] = 3200000,
6892                 [1] = 4000000,
6893                 [2] = 5333333,
6894                 [3] = 6400000,
6895                 [4] = 2666667,
6896                 [5] = 4266667,
6897         };
6898         const unsigned int *vco_table;
6899         unsigned int vco;
6900         uint8_t tmp = 0;
6901
6902         /* FIXME other chipsets? */
6903         if (IS_GM45(dev))
6904                 vco_table = ctg_vco;
6905         else if (IS_G4X(dev))
6906                 vco_table = elk_vco;
6907         else if (IS_CRESTLINE(dev))
6908                 vco_table = cl_vco;
6909         else if (IS_PINEVIEW(dev))
6910                 vco_table = pnv_vco;
6911         else if (IS_G33(dev))
6912                 vco_table = blb_vco;
6913         else
6914                 return 0;
6915
6916         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6917
6918         vco = vco_table[tmp & 0x7];
6919         if (vco == 0)
6920                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6921         else
6922                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6923
6924         return vco;
6925 }
6926
6927 static int gm45_get_display_clock_speed(struct drm_device *dev)
6928 {
6929         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6930         uint16_t tmp = 0;
6931
6932         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6933
6934         cdclk_sel = (tmp >> 12) & 0x1;
6935
6936         switch (vco) {
6937         case 2666667:
6938         case 4000000:
6939         case 5333333:
6940                 return cdclk_sel ? 333333 : 222222;
6941         case 3200000:
6942                 return cdclk_sel ? 320000 : 228571;
6943         default:
6944                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6945                 return 222222;
6946         }
6947 }
6948
6949 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6950 {
6951         static const uint8_t div_3200[] = { 16, 10,  8 };
6952         static const uint8_t div_4000[] = { 20, 12, 10 };
6953         static const uint8_t div_5333[] = { 24, 16, 14 };
6954         const uint8_t *div_table;
6955         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6956         uint16_t tmp = 0;
6957
6958         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6959
6960         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6961
6962         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6963                 goto fail;
6964
6965         switch (vco) {
6966         case 3200000:
6967                 div_table = div_3200;
6968                 break;
6969         case 4000000:
6970                 div_table = div_4000;
6971                 break;
6972         case 5333333:
6973                 div_table = div_5333;
6974                 break;
6975         default:
6976                 goto fail;
6977         }
6978
6979         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6980
6981 fail:
6982         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6983         return 200000;
6984 }
6985
6986 static int g33_get_display_clock_speed(struct drm_device *dev)
6987 {
6988         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6989         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6990         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6991         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6992         const uint8_t *div_table;
6993         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6994         uint16_t tmp = 0;
6995
6996         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6997
6998         cdclk_sel = (tmp >> 4) & 0x7;
6999
7000         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7001                 goto fail;
7002
7003         switch (vco) {
7004         case 3200000:
7005                 div_table = div_3200;
7006                 break;
7007         case 4000000:
7008                 div_table = div_4000;
7009                 break;
7010         case 4800000:
7011                 div_table = div_4800;
7012                 break;
7013         case 5333333:
7014                 div_table = div_5333;
7015                 break;
7016         default:
7017                 goto fail;
7018         }
7019
7020         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7021
7022 fail:
7023         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7024         return 190476;
7025 }
7026
7027 static void
7028 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7029 {
7030         while (*num > DATA_LINK_M_N_MASK ||
7031                *den > DATA_LINK_M_N_MASK) {
7032                 *num >>= 1;
7033                 *den >>= 1;
7034         }
7035 }
7036
7037 static void compute_m_n(unsigned int m, unsigned int n,
7038                         uint32_t *ret_m, uint32_t *ret_n)
7039 {
7040         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7041         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7042         intel_reduce_m_n_ratio(ret_m, ret_n);
7043 }
7044
7045 void
7046 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7047                        int pixel_clock, int link_clock,
7048                        struct intel_link_m_n *m_n)
7049 {
7050         m_n->tu = 64;
7051
7052         compute_m_n(bits_per_pixel * pixel_clock,
7053                     link_clock * nlanes * 8,
7054                     &m_n->gmch_m, &m_n->gmch_n);
7055
7056         compute_m_n(pixel_clock, link_clock,
7057                     &m_n->link_m, &m_n->link_n);
7058 }
7059
7060 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7061 {
7062         if (i915.panel_use_ssc >= 0)
7063                 return i915.panel_use_ssc != 0;
7064         return dev_priv->vbt.lvds_use_ssc
7065                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7066 }
7067
7068 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7069                            int num_connectors)
7070 {
7071         struct drm_device *dev = crtc_state->base.crtc->dev;
7072         struct drm_i915_private *dev_priv = dev->dev_private;
7073         int refclk;
7074
7075         WARN_ON(!crtc_state->base.state);
7076
7077         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7078                 refclk = 100000;
7079         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7080             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7081                 refclk = dev_priv->vbt.lvds_ssc_freq;
7082                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7083         } else if (!IS_GEN2(dev)) {
7084                 refclk = 96000;
7085         } else {
7086                 refclk = 48000;
7087         }
7088
7089         return refclk;
7090 }
7091
7092 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7093 {
7094         return (1 << dpll->n) << 16 | dpll->m2;
7095 }
7096
7097 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7098 {
7099         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7100 }
7101
7102 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7103                                      struct intel_crtc_state *crtc_state,
7104                                      intel_clock_t *reduced_clock)
7105 {
7106         struct drm_device *dev = crtc->base.dev;
7107         u32 fp, fp2 = 0;
7108
7109         if (IS_PINEVIEW(dev)) {
7110                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7111                 if (reduced_clock)
7112                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7113         } else {
7114                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7115                 if (reduced_clock)
7116                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7117         }
7118
7119         crtc_state->dpll_hw_state.fp0 = fp;
7120
7121         crtc->lowfreq_avail = false;
7122         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7123             reduced_clock) {
7124                 crtc_state->dpll_hw_state.fp1 = fp2;
7125                 crtc->lowfreq_avail = true;
7126         } else {
7127                 crtc_state->dpll_hw_state.fp1 = fp;
7128         }
7129 }
7130
7131 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7132                 pipe)
7133 {
7134         u32 reg_val;
7135
7136         /*
7137          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7138          * and set it to a reasonable value instead.
7139          */
7140         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7141         reg_val &= 0xffffff00;
7142         reg_val |= 0x00000030;
7143         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7144
7145         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7146         reg_val &= 0x8cffffff;
7147         reg_val = 0x8c000000;
7148         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7149
7150         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7151         reg_val &= 0xffffff00;
7152         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7153
7154         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7155         reg_val &= 0x00ffffff;
7156         reg_val |= 0xb0000000;
7157         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7158 }
7159
7160 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7161                                          struct intel_link_m_n *m_n)
7162 {
7163         struct drm_device *dev = crtc->base.dev;
7164         struct drm_i915_private *dev_priv = dev->dev_private;
7165         int pipe = crtc->pipe;
7166
7167         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7168         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7169         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7170         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7171 }
7172
7173 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7174                                          struct intel_link_m_n *m_n,
7175                                          struct intel_link_m_n *m2_n2)
7176 {
7177         struct drm_device *dev = crtc->base.dev;
7178         struct drm_i915_private *dev_priv = dev->dev_private;
7179         int pipe = crtc->pipe;
7180         enum transcoder transcoder = crtc->config->cpu_transcoder;
7181
7182         if (INTEL_INFO(dev)->gen >= 5) {
7183                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7184                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7185                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7186                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7187                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7188                  * for gen < 8) and if DRRS is supported (to make sure the
7189                  * registers are not unnecessarily accessed).
7190                  */
7191                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7192                         crtc->config->has_drrs) {
7193                         I915_WRITE(PIPE_DATA_M2(transcoder),
7194                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7195                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7196                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7197                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7198                 }
7199         } else {
7200                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7201                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7202                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7203                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7204         }
7205 }
7206
7207 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7208 {
7209         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7210
7211         if (m_n == M1_N1) {
7212                 dp_m_n = &crtc->config->dp_m_n;
7213                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7214         } else if (m_n == M2_N2) {
7215
7216                 /*
7217                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7218                  * needs to be programmed into M1_N1.
7219                  */
7220                 dp_m_n = &crtc->config->dp_m2_n2;
7221         } else {
7222                 DRM_ERROR("Unsupported divider value\n");
7223                 return;
7224         }
7225
7226         if (crtc->config->has_pch_encoder)
7227                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7228         else
7229                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7230 }
7231
7232 static void vlv_compute_dpll(struct intel_crtc *crtc,
7233                              struct intel_crtc_state *pipe_config)
7234 {
7235         u32 dpll, dpll_md;
7236
7237         /*
7238          * Enable DPIO clock input. We should never disable the reference
7239          * clock for pipe B, since VGA hotplug / manual detection depends
7240          * on it.
7241          */
7242         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7243                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7244         /* We should never disable this, set it here for state tracking */
7245         if (crtc->pipe == PIPE_B)
7246                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7247         dpll |= DPLL_VCO_ENABLE;
7248         pipe_config->dpll_hw_state.dpll = dpll;
7249
7250         dpll_md = (pipe_config->pixel_multiplier - 1)
7251                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7252         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7253 }
7254
7255 static void vlv_prepare_pll(struct intel_crtc *crtc,
7256                             const struct intel_crtc_state *pipe_config)
7257 {
7258         struct drm_device *dev = crtc->base.dev;
7259         struct drm_i915_private *dev_priv = dev->dev_private;
7260         int pipe = crtc->pipe;
7261         u32 mdiv;
7262         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7263         u32 coreclk, reg_val;
7264
7265         mutex_lock(&dev_priv->sb_lock);
7266
7267         bestn = pipe_config->dpll.n;
7268         bestm1 = pipe_config->dpll.m1;
7269         bestm2 = pipe_config->dpll.m2;
7270         bestp1 = pipe_config->dpll.p1;
7271         bestp2 = pipe_config->dpll.p2;
7272
7273         /* See eDP HDMI DPIO driver vbios notes doc */
7274
7275         /* PLL B needs special handling */
7276         if (pipe == PIPE_B)
7277                 vlv_pllb_recal_opamp(dev_priv, pipe);
7278
7279         /* Set up Tx target for periodic Rcomp update */
7280         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7281
7282         /* Disable target IRef on PLL */
7283         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7284         reg_val &= 0x00ffffff;
7285         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7286
7287         /* Disable fast lock */
7288         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7289
7290         /* Set idtafcrecal before PLL is enabled */
7291         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7292         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7293         mdiv |= ((bestn << DPIO_N_SHIFT));
7294         mdiv |= (1 << DPIO_K_SHIFT);
7295
7296         /*
7297          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7298          * but we don't support that).
7299          * Note: don't use the DAC post divider as it seems unstable.
7300          */
7301         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7302         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7303
7304         mdiv |= DPIO_ENABLE_CALIBRATION;
7305         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7306
7307         /* Set HBR and RBR LPF coefficients */
7308         if (pipe_config->port_clock == 162000 ||
7309             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7310             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7311                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7312                                  0x009f0003);
7313         else
7314                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7315                                  0x00d0000f);
7316
7317         if (pipe_config->has_dp_encoder) {
7318                 /* Use SSC source */
7319                 if (pipe == PIPE_A)
7320                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7321                                          0x0df40000);
7322                 else
7323                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7324                                          0x0df70000);
7325         } else { /* HDMI or VGA */
7326                 /* Use bend source */
7327                 if (pipe == PIPE_A)
7328                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7329                                          0x0df70000);
7330                 else
7331                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7332                                          0x0df40000);
7333         }
7334
7335         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7336         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7337         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7338             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7339                 coreclk |= 0x01000000;
7340         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7341
7342         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7343         mutex_unlock(&dev_priv->sb_lock);
7344 }
7345
7346 static void chv_compute_dpll(struct intel_crtc *crtc,
7347                              struct intel_crtc_state *pipe_config)
7348 {
7349         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7350                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7351                 DPLL_VCO_ENABLE;
7352         if (crtc->pipe != PIPE_A)
7353                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7354
7355         pipe_config->dpll_hw_state.dpll_md =
7356                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7357 }
7358
7359 static void chv_prepare_pll(struct intel_crtc *crtc,
7360                             const struct intel_crtc_state *pipe_config)
7361 {
7362         struct drm_device *dev = crtc->base.dev;
7363         struct drm_i915_private *dev_priv = dev->dev_private;
7364         int pipe = crtc->pipe;
7365         int dpll_reg = DPLL(crtc->pipe);
7366         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7367         u32 loopfilter, tribuf_calcntr;
7368         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7369         u32 dpio_val;
7370         int vco;
7371
7372         bestn = pipe_config->dpll.n;
7373         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7374         bestm1 = pipe_config->dpll.m1;
7375         bestm2 = pipe_config->dpll.m2 >> 22;
7376         bestp1 = pipe_config->dpll.p1;
7377         bestp2 = pipe_config->dpll.p2;
7378         vco = pipe_config->dpll.vco;
7379         dpio_val = 0;
7380         loopfilter = 0;
7381
7382         /*
7383          * Enable Refclk and SSC
7384          */
7385         I915_WRITE(dpll_reg,
7386                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7387
7388         mutex_lock(&dev_priv->sb_lock);
7389
7390         /* p1 and p2 divider */
7391         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7392                         5 << DPIO_CHV_S1_DIV_SHIFT |
7393                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7394                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7395                         1 << DPIO_CHV_K_DIV_SHIFT);
7396
7397         /* Feedback post-divider - m2 */
7398         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7399
7400         /* Feedback refclk divider - n and m1 */
7401         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7402                         DPIO_CHV_M1_DIV_BY_2 |
7403                         1 << DPIO_CHV_N_DIV_SHIFT);
7404
7405         /* M2 fraction division */
7406         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7407
7408         /* M2 fraction division enable */
7409         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7410         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7411         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7412         if (bestm2_frac)
7413                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7414         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7415
7416         /* Program digital lock detect threshold */
7417         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7418         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7419                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7420         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7421         if (!bestm2_frac)
7422                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7423         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7424
7425         /* Loop filter */
7426         if (vco == 5400000) {
7427                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7428                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7429                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7430                 tribuf_calcntr = 0x9;
7431         } else if (vco <= 6200000) {
7432                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7433                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7434                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7435                 tribuf_calcntr = 0x9;
7436         } else if (vco <= 6480000) {
7437                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7438                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7439                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7440                 tribuf_calcntr = 0x8;
7441         } else {
7442                 /* Not supported. Apply the same limits as in the max case */
7443                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7444                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7445                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7446                 tribuf_calcntr = 0;
7447         }
7448         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7449
7450         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7451         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7452         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7453         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7454
7455         /* AFC Recal */
7456         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7457                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7458                         DPIO_AFC_RECAL);
7459
7460         mutex_unlock(&dev_priv->sb_lock);
7461 }
7462
7463 /**
7464  * vlv_force_pll_on - forcibly enable just the PLL
7465  * @dev_priv: i915 private structure
7466  * @pipe: pipe PLL to enable
7467  * @dpll: PLL configuration
7468  *
7469  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7470  * in cases where we need the PLL enabled even when @pipe is not going to
7471  * be enabled.
7472  */
7473 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7474                       const struct dpll *dpll)
7475 {
7476         struct intel_crtc *crtc =
7477                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7478         struct intel_crtc_state pipe_config = {
7479                 .base.crtc = &crtc->base,
7480                 .pixel_multiplier = 1,
7481                 .dpll = *dpll,
7482         };
7483
7484         if (IS_CHERRYVIEW(dev)) {
7485                 chv_compute_dpll(crtc, &pipe_config);
7486                 chv_prepare_pll(crtc, &pipe_config);
7487                 chv_enable_pll(crtc, &pipe_config);
7488         } else {
7489                 vlv_compute_dpll(crtc, &pipe_config);
7490                 vlv_prepare_pll(crtc, &pipe_config);
7491                 vlv_enable_pll(crtc, &pipe_config);
7492         }
7493 }
7494
7495 /**
7496  * vlv_force_pll_off - forcibly disable just the PLL
7497  * @dev_priv: i915 private structure
7498  * @pipe: pipe PLL to disable
7499  *
7500  * Disable the PLL for @pipe. To be used in cases where we need
7501  * the PLL enabled even when @pipe is not going to be enabled.
7502  */
7503 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7504 {
7505         if (IS_CHERRYVIEW(dev))
7506                 chv_disable_pll(to_i915(dev), pipe);
7507         else
7508                 vlv_disable_pll(to_i915(dev), pipe);
7509 }
7510
7511 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7512                               struct intel_crtc_state *crtc_state,
7513                               intel_clock_t *reduced_clock,
7514                               int num_connectors)
7515 {
7516         struct drm_device *dev = crtc->base.dev;
7517         struct drm_i915_private *dev_priv = dev->dev_private;
7518         u32 dpll;
7519         bool is_sdvo;
7520         struct dpll *clock = &crtc_state->dpll;
7521
7522         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7523
7524         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7525                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7526
7527         dpll = DPLL_VGA_MODE_DIS;
7528
7529         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7530                 dpll |= DPLLB_MODE_LVDS;
7531         else
7532                 dpll |= DPLLB_MODE_DAC_SERIAL;
7533
7534         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7535                 dpll |= (crtc_state->pixel_multiplier - 1)
7536                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7537         }
7538
7539         if (is_sdvo)
7540                 dpll |= DPLL_SDVO_HIGH_SPEED;
7541
7542         if (crtc_state->has_dp_encoder)
7543                 dpll |= DPLL_SDVO_HIGH_SPEED;
7544
7545         /* compute bitmask from p1 value */
7546         if (IS_PINEVIEW(dev))
7547                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7548         else {
7549                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7550                 if (IS_G4X(dev) && reduced_clock)
7551                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7552         }
7553         switch (clock->p2) {
7554         case 5:
7555                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7556                 break;
7557         case 7:
7558                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7559                 break;
7560         case 10:
7561                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7562                 break;
7563         case 14:
7564                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7565                 break;
7566         }
7567         if (INTEL_INFO(dev)->gen >= 4)
7568                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7569
7570         if (crtc_state->sdvo_tv_clock)
7571                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7572         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7573                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7574                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7575         else
7576                 dpll |= PLL_REF_INPUT_DREFCLK;
7577
7578         dpll |= DPLL_VCO_ENABLE;
7579         crtc_state->dpll_hw_state.dpll = dpll;
7580
7581         if (INTEL_INFO(dev)->gen >= 4) {
7582                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7583                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7584                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7585         }
7586 }
7587
7588 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7589                               struct intel_crtc_state *crtc_state,
7590                               intel_clock_t *reduced_clock,
7591                               int num_connectors)
7592 {
7593         struct drm_device *dev = crtc->base.dev;
7594         struct drm_i915_private *dev_priv = dev->dev_private;
7595         u32 dpll;
7596         struct dpll *clock = &crtc_state->dpll;
7597
7598         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7599
7600         dpll = DPLL_VGA_MODE_DIS;
7601
7602         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7603                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7604         } else {
7605                 if (clock->p1 == 2)
7606                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7607                 else
7608                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7609                 if (clock->p2 == 4)
7610                         dpll |= PLL_P2_DIVIDE_BY_4;
7611         }
7612
7613         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7614                 dpll |= DPLL_DVO_2X_MODE;
7615
7616         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7617                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7618                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7619         else
7620                 dpll |= PLL_REF_INPUT_DREFCLK;
7621
7622         dpll |= DPLL_VCO_ENABLE;
7623         crtc_state->dpll_hw_state.dpll = dpll;
7624 }
7625
7626 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7627 {
7628         struct drm_device *dev = intel_crtc->base.dev;
7629         struct drm_i915_private *dev_priv = dev->dev_private;
7630         enum pipe pipe = intel_crtc->pipe;
7631         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7632         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7633         uint32_t crtc_vtotal, crtc_vblank_end;
7634         int vsyncshift = 0;
7635
7636         /* We need to be careful not to changed the adjusted mode, for otherwise
7637          * the hw state checker will get angry at the mismatch. */
7638         crtc_vtotal = adjusted_mode->crtc_vtotal;
7639         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7640
7641         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7642                 /* the chip adds 2 halflines automatically */
7643                 crtc_vtotal -= 1;
7644                 crtc_vblank_end -= 1;
7645
7646                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7647                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7648                 else
7649                         vsyncshift = adjusted_mode->crtc_hsync_start -
7650                                 adjusted_mode->crtc_htotal / 2;
7651                 if (vsyncshift < 0)
7652                         vsyncshift += adjusted_mode->crtc_htotal;
7653         }
7654
7655         if (INTEL_INFO(dev)->gen > 3)
7656                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7657
7658         I915_WRITE(HTOTAL(cpu_transcoder),
7659                    (adjusted_mode->crtc_hdisplay - 1) |
7660                    ((adjusted_mode->crtc_htotal - 1) << 16));
7661         I915_WRITE(HBLANK(cpu_transcoder),
7662                    (adjusted_mode->crtc_hblank_start - 1) |
7663                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7664         I915_WRITE(HSYNC(cpu_transcoder),
7665                    (adjusted_mode->crtc_hsync_start - 1) |
7666                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7667
7668         I915_WRITE(VTOTAL(cpu_transcoder),
7669                    (adjusted_mode->crtc_vdisplay - 1) |
7670                    ((crtc_vtotal - 1) << 16));
7671         I915_WRITE(VBLANK(cpu_transcoder),
7672                    (adjusted_mode->crtc_vblank_start - 1) |
7673                    ((crtc_vblank_end - 1) << 16));
7674         I915_WRITE(VSYNC(cpu_transcoder),
7675                    (adjusted_mode->crtc_vsync_start - 1) |
7676                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7677
7678         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7679          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7680          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7681          * bits. */
7682         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7683             (pipe == PIPE_B || pipe == PIPE_C))
7684                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7685
7686         /* pipesrc controls the size that is scaled from, which should
7687          * always be the user's requested size.
7688          */
7689         I915_WRITE(PIPESRC(pipe),
7690                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7691                    (intel_crtc->config->pipe_src_h - 1));
7692 }
7693
7694 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7695                                    struct intel_crtc_state *pipe_config)
7696 {
7697         struct drm_device *dev = crtc->base.dev;
7698         struct drm_i915_private *dev_priv = dev->dev_private;
7699         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7700         uint32_t tmp;
7701
7702         tmp = I915_READ(HTOTAL(cpu_transcoder));
7703         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7704         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7705         tmp = I915_READ(HBLANK(cpu_transcoder));
7706         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7707         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7708         tmp = I915_READ(HSYNC(cpu_transcoder));
7709         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7710         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7711
7712         tmp = I915_READ(VTOTAL(cpu_transcoder));
7713         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7714         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7715         tmp = I915_READ(VBLANK(cpu_transcoder));
7716         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7717         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7718         tmp = I915_READ(VSYNC(cpu_transcoder));
7719         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7720         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7721
7722         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7723                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7724                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7725                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7726         }
7727
7728         tmp = I915_READ(PIPESRC(crtc->pipe));
7729         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7730         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7731
7732         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7733         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7734 }
7735
7736 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7737                                  struct intel_crtc_state *pipe_config)
7738 {
7739         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7740         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7741         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7742         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7743
7744         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7745         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7746         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7747         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7748
7749         mode->flags = pipe_config->base.adjusted_mode.flags;
7750         mode->type = DRM_MODE_TYPE_DRIVER;
7751
7752         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7753         mode->flags |= pipe_config->base.adjusted_mode.flags;
7754
7755         mode->hsync = drm_mode_hsync(mode);
7756         mode->vrefresh = drm_mode_vrefresh(mode);
7757         drm_mode_set_name(mode);
7758 }
7759
7760 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7761 {
7762         struct drm_device *dev = intel_crtc->base.dev;
7763         struct drm_i915_private *dev_priv = dev->dev_private;
7764         uint32_t pipeconf;
7765
7766         pipeconf = 0;
7767
7768         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7769             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7770                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7771
7772         if (intel_crtc->config->double_wide)
7773                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7774
7775         /* only g4x and later have fancy bpc/dither controls */
7776         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7777                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7778                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7779                         pipeconf |= PIPECONF_DITHER_EN |
7780                                     PIPECONF_DITHER_TYPE_SP;
7781
7782                 switch (intel_crtc->config->pipe_bpp) {
7783                 case 18:
7784                         pipeconf |= PIPECONF_6BPC;
7785                         break;
7786                 case 24:
7787                         pipeconf |= PIPECONF_8BPC;
7788                         break;
7789                 case 30:
7790                         pipeconf |= PIPECONF_10BPC;
7791                         break;
7792                 default:
7793                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7794                         BUG();
7795                 }
7796         }
7797
7798         if (HAS_PIPE_CXSR(dev)) {
7799                 if (intel_crtc->lowfreq_avail) {
7800                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7801                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7802                 } else {
7803                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7804                 }
7805         }
7806
7807         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7808                 if (INTEL_INFO(dev)->gen < 4 ||
7809                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7810                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7811                 else
7812                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7813         } else
7814                 pipeconf |= PIPECONF_PROGRESSIVE;
7815
7816         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7817                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7818
7819         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7820         POSTING_READ(PIPECONF(intel_crtc->pipe));
7821 }
7822
7823 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7824                                    struct intel_crtc_state *crtc_state)
7825 {
7826         struct drm_device *dev = crtc->base.dev;
7827         struct drm_i915_private *dev_priv = dev->dev_private;
7828         int refclk, num_connectors = 0;
7829         intel_clock_t clock;
7830         bool ok;
7831         bool is_dsi = false;
7832         struct intel_encoder *encoder;
7833         const intel_limit_t *limit;
7834         struct drm_atomic_state *state = crtc_state->base.state;
7835         struct drm_connector *connector;
7836         struct drm_connector_state *connector_state;
7837         int i;
7838
7839         memset(&crtc_state->dpll_hw_state, 0,
7840                sizeof(crtc_state->dpll_hw_state));
7841
7842         for_each_connector_in_state(state, connector, connector_state, i) {
7843                 if (connector_state->crtc != &crtc->base)
7844                         continue;
7845
7846                 encoder = to_intel_encoder(connector_state->best_encoder);
7847
7848                 switch (encoder->type) {
7849                 case INTEL_OUTPUT_DSI:
7850                         is_dsi = true;
7851                         break;
7852                 default:
7853                         break;
7854                 }
7855
7856                 num_connectors++;
7857         }
7858
7859         if (is_dsi)
7860                 return 0;
7861
7862         if (!crtc_state->clock_set) {
7863                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7864
7865                 /*
7866                  * Returns a set of divisors for the desired target clock with
7867                  * the given refclk, or FALSE.  The returned values represent
7868                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7869                  * 2) / p1 / p2.
7870                  */
7871                 limit = intel_limit(crtc_state, refclk);
7872                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7873                                                  crtc_state->port_clock,
7874                                                  refclk, NULL, &clock);
7875                 if (!ok) {
7876                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7877                         return -EINVAL;
7878                 }
7879
7880                 /* Compat-code for transition, will disappear. */
7881                 crtc_state->dpll.n = clock.n;
7882                 crtc_state->dpll.m1 = clock.m1;
7883                 crtc_state->dpll.m2 = clock.m2;
7884                 crtc_state->dpll.p1 = clock.p1;
7885                 crtc_state->dpll.p2 = clock.p2;
7886         }
7887
7888         if (IS_GEN2(dev)) {
7889                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7890                                   num_connectors);
7891         } else if (IS_CHERRYVIEW(dev)) {
7892                 chv_compute_dpll(crtc, crtc_state);
7893         } else if (IS_VALLEYVIEW(dev)) {
7894                 vlv_compute_dpll(crtc, crtc_state);
7895         } else {
7896                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7897                                   num_connectors);
7898         }
7899
7900         return 0;
7901 }
7902
7903 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7904                                  struct intel_crtc_state *pipe_config)
7905 {
7906         struct drm_device *dev = crtc->base.dev;
7907         struct drm_i915_private *dev_priv = dev->dev_private;
7908         uint32_t tmp;
7909
7910         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7911                 return;
7912
7913         tmp = I915_READ(PFIT_CONTROL);
7914         if (!(tmp & PFIT_ENABLE))
7915                 return;
7916
7917         /* Check whether the pfit is attached to our pipe. */
7918         if (INTEL_INFO(dev)->gen < 4) {
7919                 if (crtc->pipe != PIPE_B)
7920                         return;
7921         } else {
7922                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7923                         return;
7924         }
7925
7926         pipe_config->gmch_pfit.control = tmp;
7927         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7928         if (INTEL_INFO(dev)->gen < 5)
7929                 pipe_config->gmch_pfit.lvds_border_bits =
7930                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7931 }
7932
7933 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7934                                struct intel_crtc_state *pipe_config)
7935 {
7936         struct drm_device *dev = crtc->base.dev;
7937         struct drm_i915_private *dev_priv = dev->dev_private;
7938         int pipe = pipe_config->cpu_transcoder;
7939         intel_clock_t clock;
7940         u32 mdiv;
7941         int refclk = 100000;
7942
7943         /* In case of MIPI DPLL will not even be used */
7944         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7945                 return;
7946
7947         mutex_lock(&dev_priv->sb_lock);
7948         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7949         mutex_unlock(&dev_priv->sb_lock);
7950
7951         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7952         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7953         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7954         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7955         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7956
7957         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7958 }
7959
7960 static void
7961 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7962                               struct intel_initial_plane_config *plane_config)
7963 {
7964         struct drm_device *dev = crtc->base.dev;
7965         struct drm_i915_private *dev_priv = dev->dev_private;
7966         u32 val, base, offset;
7967         int pipe = crtc->pipe, plane = crtc->plane;
7968         int fourcc, pixel_format;
7969         unsigned int aligned_height;
7970         struct drm_framebuffer *fb;
7971         struct intel_framebuffer *intel_fb;
7972
7973         val = I915_READ(DSPCNTR(plane));
7974         if (!(val & DISPLAY_PLANE_ENABLE))
7975                 return;
7976
7977         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7978         if (!intel_fb) {
7979                 DRM_DEBUG_KMS("failed to alloc fb\n");
7980                 return;
7981         }
7982
7983         fb = &intel_fb->base;
7984
7985         if (INTEL_INFO(dev)->gen >= 4) {
7986                 if (val & DISPPLANE_TILED) {
7987                         plane_config->tiling = I915_TILING_X;
7988                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7989                 }
7990         }
7991
7992         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7993         fourcc = i9xx_format_to_fourcc(pixel_format);
7994         fb->pixel_format = fourcc;
7995         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7996
7997         if (INTEL_INFO(dev)->gen >= 4) {
7998                 if (plane_config->tiling)
7999                         offset = I915_READ(DSPTILEOFF(plane));
8000                 else
8001                         offset = I915_READ(DSPLINOFF(plane));
8002                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8003         } else {
8004                 base = I915_READ(DSPADDR(plane));
8005         }
8006         plane_config->base = base;
8007
8008         val = I915_READ(PIPESRC(pipe));
8009         fb->width = ((val >> 16) & 0xfff) + 1;
8010         fb->height = ((val >> 0) & 0xfff) + 1;
8011
8012         val = I915_READ(DSPSTRIDE(pipe));
8013         fb->pitches[0] = val & 0xffffffc0;
8014
8015         aligned_height = intel_fb_align_height(dev, fb->height,
8016                                                fb->pixel_format,
8017                                                fb->modifier[0]);
8018
8019         plane_config->size = fb->pitches[0] * aligned_height;
8020
8021         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8022                       pipe_name(pipe), plane, fb->width, fb->height,
8023                       fb->bits_per_pixel, base, fb->pitches[0],
8024                       plane_config->size);
8025
8026         plane_config->fb = intel_fb;
8027 }
8028
8029 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8030                                struct intel_crtc_state *pipe_config)
8031 {
8032         struct drm_device *dev = crtc->base.dev;
8033         struct drm_i915_private *dev_priv = dev->dev_private;
8034         int pipe = pipe_config->cpu_transcoder;
8035         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8036         intel_clock_t clock;
8037         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8038         int refclk = 100000;
8039
8040         mutex_lock(&dev_priv->sb_lock);
8041         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8042         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8043         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8044         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8045         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8046         mutex_unlock(&dev_priv->sb_lock);
8047
8048         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8049         clock.m2 = (pll_dw0 & 0xff) << 22;
8050         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8051                 clock.m2 |= pll_dw2 & 0x3fffff;
8052         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8053         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8054         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8055
8056         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8057 }
8058
8059 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8060                                  struct intel_crtc_state *pipe_config)
8061 {
8062         struct drm_device *dev = crtc->base.dev;
8063         struct drm_i915_private *dev_priv = dev->dev_private;
8064         uint32_t tmp;
8065
8066         if (!intel_display_power_is_enabled(dev_priv,
8067                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8068                 return false;
8069
8070         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8071         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8072
8073         tmp = I915_READ(PIPECONF(crtc->pipe));
8074         if (!(tmp & PIPECONF_ENABLE))
8075                 return false;
8076
8077         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8078                 switch (tmp & PIPECONF_BPC_MASK) {
8079                 case PIPECONF_6BPC:
8080                         pipe_config->pipe_bpp = 18;
8081                         break;
8082                 case PIPECONF_8BPC:
8083                         pipe_config->pipe_bpp = 24;
8084                         break;
8085                 case PIPECONF_10BPC:
8086                         pipe_config->pipe_bpp = 30;
8087                         break;
8088                 default:
8089                         break;
8090                 }
8091         }
8092
8093         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8094                 pipe_config->limited_color_range = true;
8095
8096         if (INTEL_INFO(dev)->gen < 4)
8097                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8098
8099         intel_get_pipe_timings(crtc, pipe_config);
8100
8101         i9xx_get_pfit_config(crtc, pipe_config);
8102
8103         if (INTEL_INFO(dev)->gen >= 4) {
8104                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8105                 pipe_config->pixel_multiplier =
8106                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8107                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8108                 pipe_config->dpll_hw_state.dpll_md = tmp;
8109         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8110                 tmp = I915_READ(DPLL(crtc->pipe));
8111                 pipe_config->pixel_multiplier =
8112                         ((tmp & SDVO_MULTIPLIER_MASK)
8113                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8114         } else {
8115                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8116                  * port and will be fixed up in the encoder->get_config
8117                  * function. */
8118                 pipe_config->pixel_multiplier = 1;
8119         }
8120         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8121         if (!IS_VALLEYVIEW(dev)) {
8122                 /*
8123                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8124                  * on 830. Filter it out here so that we don't
8125                  * report errors due to that.
8126                  */
8127                 if (IS_I830(dev))
8128                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8129
8130                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8131                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8132         } else {
8133                 /* Mask out read-only status bits. */
8134                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8135                                                      DPLL_PORTC_READY_MASK |
8136                                                      DPLL_PORTB_READY_MASK);
8137         }
8138
8139         if (IS_CHERRYVIEW(dev))
8140                 chv_crtc_clock_get(crtc, pipe_config);
8141         else if (IS_VALLEYVIEW(dev))
8142                 vlv_crtc_clock_get(crtc, pipe_config);
8143         else
8144                 i9xx_crtc_clock_get(crtc, pipe_config);
8145
8146         /*
8147          * Normally the dotclock is filled in by the encoder .get_config()
8148          * but in case the pipe is enabled w/o any ports we need a sane
8149          * default.
8150          */
8151         pipe_config->base.adjusted_mode.crtc_clock =
8152                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8153
8154         return true;
8155 }
8156
8157 static void ironlake_init_pch_refclk(struct drm_device *dev)
8158 {
8159         struct drm_i915_private *dev_priv = dev->dev_private;
8160         struct intel_encoder *encoder;
8161         u32 val, final;
8162         bool has_lvds = false;
8163         bool has_cpu_edp = false;
8164         bool has_panel = false;
8165         bool has_ck505 = false;
8166         bool can_ssc = false;
8167
8168         /* We need to take the global config into account */
8169         for_each_intel_encoder(dev, encoder) {
8170                 switch (encoder->type) {
8171                 case INTEL_OUTPUT_LVDS:
8172                         has_panel = true;
8173                         has_lvds = true;
8174                         break;
8175                 case INTEL_OUTPUT_EDP:
8176                         has_panel = true;
8177                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8178                                 has_cpu_edp = true;
8179                         break;
8180                 default:
8181                         break;
8182                 }
8183         }
8184
8185         if (HAS_PCH_IBX(dev)) {
8186                 has_ck505 = dev_priv->vbt.display_clock_mode;
8187                 can_ssc = has_ck505;
8188         } else {
8189                 has_ck505 = false;
8190                 can_ssc = true;
8191         }
8192
8193         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8194                       has_panel, has_lvds, has_ck505);
8195
8196         /* Ironlake: try to setup display ref clock before DPLL
8197          * enabling. This is only under driver's control after
8198          * PCH B stepping, previous chipset stepping should be
8199          * ignoring this setting.
8200          */
8201         val = I915_READ(PCH_DREF_CONTROL);
8202
8203         /* As we must carefully and slowly disable/enable each source in turn,
8204          * compute the final state we want first and check if we need to
8205          * make any changes at all.
8206          */
8207         final = val;
8208         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8209         if (has_ck505)
8210                 final |= DREF_NONSPREAD_CK505_ENABLE;
8211         else
8212                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8213
8214         final &= ~DREF_SSC_SOURCE_MASK;
8215         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8216         final &= ~DREF_SSC1_ENABLE;
8217
8218         if (has_panel) {
8219                 final |= DREF_SSC_SOURCE_ENABLE;
8220
8221                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8222                         final |= DREF_SSC1_ENABLE;
8223
8224                 if (has_cpu_edp) {
8225                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8226                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8227                         else
8228                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8229                 } else
8230                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8231         } else {
8232                 final |= DREF_SSC_SOURCE_DISABLE;
8233                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8234         }
8235
8236         if (final == val)
8237                 return;
8238
8239         /* Always enable nonspread source */
8240         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8241
8242         if (has_ck505)
8243                 val |= DREF_NONSPREAD_CK505_ENABLE;
8244         else
8245                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8246
8247         if (has_panel) {
8248                 val &= ~DREF_SSC_SOURCE_MASK;
8249                 val |= DREF_SSC_SOURCE_ENABLE;
8250
8251                 /* SSC must be turned on before enabling the CPU output  */
8252                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8253                         DRM_DEBUG_KMS("Using SSC on panel\n");
8254                         val |= DREF_SSC1_ENABLE;
8255                 } else
8256                         val &= ~DREF_SSC1_ENABLE;
8257
8258                 /* Get SSC going before enabling the outputs */
8259                 I915_WRITE(PCH_DREF_CONTROL, val);
8260                 POSTING_READ(PCH_DREF_CONTROL);
8261                 udelay(200);
8262
8263                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8264
8265                 /* Enable CPU source on CPU attached eDP */
8266                 if (has_cpu_edp) {
8267                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8268                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8269                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8270                         } else
8271                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8272                 } else
8273                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8274
8275                 I915_WRITE(PCH_DREF_CONTROL, val);
8276                 POSTING_READ(PCH_DREF_CONTROL);
8277                 udelay(200);
8278         } else {
8279                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8280
8281                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8282
8283                 /* Turn off CPU output */
8284                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8285
8286                 I915_WRITE(PCH_DREF_CONTROL, val);
8287                 POSTING_READ(PCH_DREF_CONTROL);
8288                 udelay(200);
8289
8290                 /* Turn off the SSC source */
8291                 val &= ~DREF_SSC_SOURCE_MASK;
8292                 val |= DREF_SSC_SOURCE_DISABLE;
8293
8294                 /* Turn off SSC1 */
8295                 val &= ~DREF_SSC1_ENABLE;
8296
8297                 I915_WRITE(PCH_DREF_CONTROL, val);
8298                 POSTING_READ(PCH_DREF_CONTROL);
8299                 udelay(200);
8300         }
8301
8302         BUG_ON(val != final);
8303 }
8304
8305 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8306 {
8307         uint32_t tmp;
8308
8309         tmp = I915_READ(SOUTH_CHICKEN2);
8310         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8311         I915_WRITE(SOUTH_CHICKEN2, tmp);
8312
8313         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8314                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8315                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8316
8317         tmp = I915_READ(SOUTH_CHICKEN2);
8318         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8319         I915_WRITE(SOUTH_CHICKEN2, tmp);
8320
8321         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8322                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8323                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8324 }
8325
8326 /* WaMPhyProgramming:hsw */
8327 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8328 {
8329         uint32_t tmp;
8330
8331         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8332         tmp &= ~(0xFF << 24);
8333         tmp |= (0x12 << 24);
8334         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8335
8336         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8337         tmp |= (1 << 11);
8338         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8339
8340         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8341         tmp |= (1 << 11);
8342         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8343
8344         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8345         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8346         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8347
8348         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8349         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8350         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8351
8352         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8353         tmp &= ~(7 << 13);
8354         tmp |= (5 << 13);
8355         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8356
8357         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8358         tmp &= ~(7 << 13);
8359         tmp |= (5 << 13);
8360         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8361
8362         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8363         tmp &= ~0xFF;
8364         tmp |= 0x1C;
8365         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8366
8367         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8368         tmp &= ~0xFF;
8369         tmp |= 0x1C;
8370         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8371
8372         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8373         tmp &= ~(0xFF << 16);
8374         tmp |= (0x1C << 16);
8375         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8376
8377         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8378         tmp &= ~(0xFF << 16);
8379         tmp |= (0x1C << 16);
8380         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8381
8382         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8383         tmp |= (1 << 27);
8384         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8385
8386         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8387         tmp |= (1 << 27);
8388         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8389
8390         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8391         tmp &= ~(0xF << 28);
8392         tmp |= (4 << 28);
8393         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8394
8395         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8396         tmp &= ~(0xF << 28);
8397         tmp |= (4 << 28);
8398         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8399 }
8400
8401 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8402  * Programming" based on the parameters passed:
8403  * - Sequence to enable CLKOUT_DP
8404  * - Sequence to enable CLKOUT_DP without spread
8405  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8406  */
8407 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8408                                  bool with_fdi)
8409 {
8410         struct drm_i915_private *dev_priv = dev->dev_private;
8411         uint32_t reg, tmp;
8412
8413         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8414                 with_spread = true;
8415         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8416                 with_fdi = false;
8417
8418         mutex_lock(&dev_priv->sb_lock);
8419
8420         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8421         tmp &= ~SBI_SSCCTL_DISABLE;
8422         tmp |= SBI_SSCCTL_PATHALT;
8423         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8424
8425         udelay(24);
8426
8427         if (with_spread) {
8428                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8429                 tmp &= ~SBI_SSCCTL_PATHALT;
8430                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8431
8432                 if (with_fdi) {
8433                         lpt_reset_fdi_mphy(dev_priv);
8434                         lpt_program_fdi_mphy(dev_priv);
8435                 }
8436         }
8437
8438         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8439         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8440         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8441         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8442
8443         mutex_unlock(&dev_priv->sb_lock);
8444 }
8445
8446 /* Sequence to disable CLKOUT_DP */
8447 static void lpt_disable_clkout_dp(struct drm_device *dev)
8448 {
8449         struct drm_i915_private *dev_priv = dev->dev_private;
8450         uint32_t reg, tmp;
8451
8452         mutex_lock(&dev_priv->sb_lock);
8453
8454         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8455         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8456         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8457         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8458
8459         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8460         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8461                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8462                         tmp |= SBI_SSCCTL_PATHALT;
8463                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8464                         udelay(32);
8465                 }
8466                 tmp |= SBI_SSCCTL_DISABLE;
8467                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8468         }
8469
8470         mutex_unlock(&dev_priv->sb_lock);
8471 }
8472
8473 static void lpt_init_pch_refclk(struct drm_device *dev)
8474 {
8475         struct intel_encoder *encoder;
8476         bool has_vga = false;
8477
8478         for_each_intel_encoder(dev, encoder) {
8479                 switch (encoder->type) {
8480                 case INTEL_OUTPUT_ANALOG:
8481                         has_vga = true;
8482                         break;
8483                 default:
8484                         break;
8485                 }
8486         }
8487
8488         if (has_vga)
8489                 lpt_enable_clkout_dp(dev, true, true);
8490         else
8491                 lpt_disable_clkout_dp(dev);
8492 }
8493
8494 /*
8495  * Initialize reference clocks when the driver loads
8496  */
8497 void intel_init_pch_refclk(struct drm_device *dev)
8498 {
8499         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8500                 ironlake_init_pch_refclk(dev);
8501         else if (HAS_PCH_LPT(dev))
8502                 lpt_init_pch_refclk(dev);
8503 }
8504
8505 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8506 {
8507         struct drm_device *dev = crtc_state->base.crtc->dev;
8508         struct drm_i915_private *dev_priv = dev->dev_private;
8509         struct drm_atomic_state *state = crtc_state->base.state;
8510         struct drm_connector *connector;
8511         struct drm_connector_state *connector_state;
8512         struct intel_encoder *encoder;
8513         int num_connectors = 0, i;
8514         bool is_lvds = false;
8515
8516         for_each_connector_in_state(state, connector, connector_state, i) {
8517                 if (connector_state->crtc != crtc_state->base.crtc)
8518                         continue;
8519
8520                 encoder = to_intel_encoder(connector_state->best_encoder);
8521
8522                 switch (encoder->type) {
8523                 case INTEL_OUTPUT_LVDS:
8524                         is_lvds = true;
8525                         break;
8526                 default:
8527                         break;
8528                 }
8529                 num_connectors++;
8530         }
8531
8532         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8533                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8534                               dev_priv->vbt.lvds_ssc_freq);
8535                 return dev_priv->vbt.lvds_ssc_freq;
8536         }
8537
8538         return 120000;
8539 }
8540
8541 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8542 {
8543         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8545         int pipe = intel_crtc->pipe;
8546         uint32_t val;
8547
8548         val = 0;
8549
8550         switch (intel_crtc->config->pipe_bpp) {
8551         case 18:
8552                 val |= PIPECONF_6BPC;
8553                 break;
8554         case 24:
8555                 val |= PIPECONF_8BPC;
8556                 break;
8557         case 30:
8558                 val |= PIPECONF_10BPC;
8559                 break;
8560         case 36:
8561                 val |= PIPECONF_12BPC;
8562                 break;
8563         default:
8564                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8565                 BUG();
8566         }
8567
8568         if (intel_crtc->config->dither)
8569                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8570
8571         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8572                 val |= PIPECONF_INTERLACED_ILK;
8573         else
8574                 val |= PIPECONF_PROGRESSIVE;
8575
8576         if (intel_crtc->config->limited_color_range)
8577                 val |= PIPECONF_COLOR_RANGE_SELECT;
8578
8579         I915_WRITE(PIPECONF(pipe), val);
8580         POSTING_READ(PIPECONF(pipe));
8581 }
8582
8583 /*
8584  * Set up the pipe CSC unit.
8585  *
8586  * Currently only full range RGB to limited range RGB conversion
8587  * is supported, but eventually this should handle various
8588  * RGB<->YCbCr scenarios as well.
8589  */
8590 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8591 {
8592         struct drm_device *dev = crtc->dev;
8593         struct drm_i915_private *dev_priv = dev->dev_private;
8594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8595         int pipe = intel_crtc->pipe;
8596         uint16_t coeff = 0x7800; /* 1.0 */
8597
8598         /*
8599          * TODO: Check what kind of values actually come out of the pipe
8600          * with these coeff/postoff values and adjust to get the best
8601          * accuracy. Perhaps we even need to take the bpc value into
8602          * consideration.
8603          */
8604
8605         if (intel_crtc->config->limited_color_range)
8606                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8607
8608         /*
8609          * GY/GU and RY/RU should be the other way around according
8610          * to BSpec, but reality doesn't agree. Just set them up in
8611          * a way that results in the correct picture.
8612          */
8613         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8614         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8615
8616         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8617         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8618
8619         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8620         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8621
8622         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8623         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8624         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8625
8626         if (INTEL_INFO(dev)->gen > 6) {
8627                 uint16_t postoff = 0;
8628
8629                 if (intel_crtc->config->limited_color_range)
8630                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8631
8632                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8633                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8634                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8635
8636                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8637         } else {
8638                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8639
8640                 if (intel_crtc->config->limited_color_range)
8641                         mode |= CSC_BLACK_SCREEN_OFFSET;
8642
8643                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8644         }
8645 }
8646
8647 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8648 {
8649         struct drm_device *dev = crtc->dev;
8650         struct drm_i915_private *dev_priv = dev->dev_private;
8651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8652         enum pipe pipe = intel_crtc->pipe;
8653         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8654         uint32_t val;
8655
8656         val = 0;
8657
8658         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8659                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8660
8661         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8662                 val |= PIPECONF_INTERLACED_ILK;
8663         else
8664                 val |= PIPECONF_PROGRESSIVE;
8665
8666         I915_WRITE(PIPECONF(cpu_transcoder), val);
8667         POSTING_READ(PIPECONF(cpu_transcoder));
8668
8669         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8670         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8671
8672         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8673                 val = 0;
8674
8675                 switch (intel_crtc->config->pipe_bpp) {
8676                 case 18:
8677                         val |= PIPEMISC_DITHER_6_BPC;
8678                         break;
8679                 case 24:
8680                         val |= PIPEMISC_DITHER_8_BPC;
8681                         break;
8682                 case 30:
8683                         val |= PIPEMISC_DITHER_10_BPC;
8684                         break;
8685                 case 36:
8686                         val |= PIPEMISC_DITHER_12_BPC;
8687                         break;
8688                 default:
8689                         /* Case prevented by pipe_config_set_bpp. */
8690                         BUG();
8691                 }
8692
8693                 if (intel_crtc->config->dither)
8694                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8695
8696                 I915_WRITE(PIPEMISC(pipe), val);
8697         }
8698 }
8699
8700 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8701                                     struct intel_crtc_state *crtc_state,
8702                                     intel_clock_t *clock,
8703                                     bool *has_reduced_clock,
8704                                     intel_clock_t *reduced_clock)
8705 {
8706         struct drm_device *dev = crtc->dev;
8707         struct drm_i915_private *dev_priv = dev->dev_private;
8708         int refclk;
8709         const intel_limit_t *limit;
8710         bool ret;
8711
8712         refclk = ironlake_get_refclk(crtc_state);
8713
8714         /*
8715          * Returns a set of divisors for the desired target clock with the given
8716          * refclk, or FALSE.  The returned values represent the clock equation:
8717          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8718          */
8719         limit = intel_limit(crtc_state, refclk);
8720         ret = dev_priv->display.find_dpll(limit, crtc_state,
8721                                           crtc_state->port_clock,
8722                                           refclk, NULL, clock);
8723         if (!ret)
8724                 return false;
8725
8726         return true;
8727 }
8728
8729 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8730 {
8731         /*
8732          * Account for spread spectrum to avoid
8733          * oversubscribing the link. Max center spread
8734          * is 2.5%; use 5% for safety's sake.
8735          */
8736         u32 bps = target_clock * bpp * 21 / 20;
8737         return DIV_ROUND_UP(bps, link_bw * 8);
8738 }
8739
8740 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8741 {
8742         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8743 }
8744
8745 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8746                                       struct intel_crtc_state *crtc_state,
8747                                       u32 *fp,
8748                                       intel_clock_t *reduced_clock, u32 *fp2)
8749 {
8750         struct drm_crtc *crtc = &intel_crtc->base;
8751         struct drm_device *dev = crtc->dev;
8752         struct drm_i915_private *dev_priv = dev->dev_private;
8753         struct drm_atomic_state *state = crtc_state->base.state;
8754         struct drm_connector *connector;
8755         struct drm_connector_state *connector_state;
8756         struct intel_encoder *encoder;
8757         uint32_t dpll;
8758         int factor, num_connectors = 0, i;
8759         bool is_lvds = false, is_sdvo = false;
8760
8761         for_each_connector_in_state(state, connector, connector_state, i) {
8762                 if (connector_state->crtc != crtc_state->base.crtc)
8763                         continue;
8764
8765                 encoder = to_intel_encoder(connector_state->best_encoder);
8766
8767                 switch (encoder->type) {
8768                 case INTEL_OUTPUT_LVDS:
8769                         is_lvds = true;
8770                         break;
8771                 case INTEL_OUTPUT_SDVO:
8772                 case INTEL_OUTPUT_HDMI:
8773                         is_sdvo = true;
8774                         break;
8775                 default:
8776                         break;
8777                 }
8778
8779                 num_connectors++;
8780         }
8781
8782         /* Enable autotuning of the PLL clock (if permissible) */
8783         factor = 21;
8784         if (is_lvds) {
8785                 if ((intel_panel_use_ssc(dev_priv) &&
8786                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8787                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8788                         factor = 25;
8789         } else if (crtc_state->sdvo_tv_clock)
8790                 factor = 20;
8791
8792         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8793                 *fp |= FP_CB_TUNE;
8794
8795         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8796                 *fp2 |= FP_CB_TUNE;
8797
8798         dpll = 0;
8799
8800         if (is_lvds)
8801                 dpll |= DPLLB_MODE_LVDS;
8802         else
8803                 dpll |= DPLLB_MODE_DAC_SERIAL;
8804
8805         dpll |= (crtc_state->pixel_multiplier - 1)
8806                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8807
8808         if (is_sdvo)
8809                 dpll |= DPLL_SDVO_HIGH_SPEED;
8810         if (crtc_state->has_dp_encoder)
8811                 dpll |= DPLL_SDVO_HIGH_SPEED;
8812
8813         /* compute bitmask from p1 value */
8814         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8815         /* also FPA1 */
8816         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8817
8818         switch (crtc_state->dpll.p2) {
8819         case 5:
8820                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8821                 break;
8822         case 7:
8823                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8824                 break;
8825         case 10:
8826                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8827                 break;
8828         case 14:
8829                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8830                 break;
8831         }
8832
8833         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8834                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8835         else
8836                 dpll |= PLL_REF_INPUT_DREFCLK;
8837
8838         return dpll | DPLL_VCO_ENABLE;
8839 }
8840
8841 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8842                                        struct intel_crtc_state *crtc_state)
8843 {
8844         struct drm_device *dev = crtc->base.dev;
8845         intel_clock_t clock, reduced_clock;
8846         u32 dpll = 0, fp = 0, fp2 = 0;
8847         bool ok, has_reduced_clock = false;
8848         bool is_lvds = false;
8849         struct intel_shared_dpll *pll;
8850
8851         memset(&crtc_state->dpll_hw_state, 0,
8852                sizeof(crtc_state->dpll_hw_state));
8853
8854         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8855
8856         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8857              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8858
8859         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8860                                      &has_reduced_clock, &reduced_clock);
8861         if (!ok && !crtc_state->clock_set) {
8862                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8863                 return -EINVAL;
8864         }
8865         /* Compat-code for transition, will disappear. */
8866         if (!crtc_state->clock_set) {
8867                 crtc_state->dpll.n = clock.n;
8868                 crtc_state->dpll.m1 = clock.m1;
8869                 crtc_state->dpll.m2 = clock.m2;
8870                 crtc_state->dpll.p1 = clock.p1;
8871                 crtc_state->dpll.p2 = clock.p2;
8872         }
8873
8874         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8875         if (crtc_state->has_pch_encoder) {
8876                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8877                 if (has_reduced_clock)
8878                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8879
8880                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8881                                              &fp, &reduced_clock,
8882                                              has_reduced_clock ? &fp2 : NULL);
8883
8884                 crtc_state->dpll_hw_state.dpll = dpll;
8885                 crtc_state->dpll_hw_state.fp0 = fp;
8886                 if (has_reduced_clock)
8887                         crtc_state->dpll_hw_state.fp1 = fp2;
8888                 else
8889                         crtc_state->dpll_hw_state.fp1 = fp;
8890
8891                 pll = intel_get_shared_dpll(crtc, crtc_state);
8892                 if (pll == NULL) {
8893                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8894                                          pipe_name(crtc->pipe));
8895                         return -EINVAL;
8896                 }
8897         }
8898
8899         if (is_lvds && has_reduced_clock)
8900                 crtc->lowfreq_avail = true;
8901         else
8902                 crtc->lowfreq_avail = false;
8903
8904         return 0;
8905 }
8906
8907 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8908                                          struct intel_link_m_n *m_n)
8909 {
8910         struct drm_device *dev = crtc->base.dev;
8911         struct drm_i915_private *dev_priv = dev->dev_private;
8912         enum pipe pipe = crtc->pipe;
8913
8914         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8915         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8916         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8917                 & ~TU_SIZE_MASK;
8918         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8919         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8920                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8921 }
8922
8923 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8924                                          enum transcoder transcoder,
8925                                          struct intel_link_m_n *m_n,
8926                                          struct intel_link_m_n *m2_n2)
8927 {
8928         struct drm_device *dev = crtc->base.dev;
8929         struct drm_i915_private *dev_priv = dev->dev_private;
8930         enum pipe pipe = crtc->pipe;
8931
8932         if (INTEL_INFO(dev)->gen >= 5) {
8933                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8934                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8935                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8936                         & ~TU_SIZE_MASK;
8937                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8938                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8939                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8940                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8941                  * gen < 8) and if DRRS is supported (to make sure the
8942                  * registers are not unnecessarily read).
8943                  */
8944                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8945                         crtc->config->has_drrs) {
8946                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8947                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8948                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8949                                         & ~TU_SIZE_MASK;
8950                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8951                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8952                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8953                 }
8954         } else {
8955                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8956                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8957                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8958                         & ~TU_SIZE_MASK;
8959                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8960                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8961                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8962         }
8963 }
8964
8965 void intel_dp_get_m_n(struct intel_crtc *crtc,
8966                       struct intel_crtc_state *pipe_config)
8967 {
8968         if (pipe_config->has_pch_encoder)
8969                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8970         else
8971                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8972                                              &pipe_config->dp_m_n,
8973                                              &pipe_config->dp_m2_n2);
8974 }
8975
8976 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8977                                         struct intel_crtc_state *pipe_config)
8978 {
8979         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8980                                      &pipe_config->fdi_m_n, NULL);
8981 }
8982
8983 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8984                                     struct intel_crtc_state *pipe_config)
8985 {
8986         struct drm_device *dev = crtc->base.dev;
8987         struct drm_i915_private *dev_priv = dev->dev_private;
8988         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8989         uint32_t ps_ctrl = 0;
8990         int id = -1;
8991         int i;
8992
8993         /* find scaler attached to this pipe */
8994         for (i = 0; i < crtc->num_scalers; i++) {
8995                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8996                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8997                         id = i;
8998                         pipe_config->pch_pfit.enabled = true;
8999                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9000                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9001                         break;
9002                 }
9003         }
9004
9005         scaler_state->scaler_id = id;
9006         if (id >= 0) {
9007                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9008         } else {
9009                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9010         }
9011 }
9012
9013 static void
9014 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9015                                  struct intel_initial_plane_config *plane_config)
9016 {
9017         struct drm_device *dev = crtc->base.dev;
9018         struct drm_i915_private *dev_priv = dev->dev_private;
9019         u32 val, base, offset, stride_mult, tiling;
9020         int pipe = crtc->pipe;
9021         int fourcc, pixel_format;
9022         unsigned int aligned_height;
9023         struct drm_framebuffer *fb;
9024         struct intel_framebuffer *intel_fb;
9025
9026         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9027         if (!intel_fb) {
9028                 DRM_DEBUG_KMS("failed to alloc fb\n");
9029                 return;
9030         }
9031
9032         fb = &intel_fb->base;
9033
9034         val = I915_READ(PLANE_CTL(pipe, 0));
9035         if (!(val & PLANE_CTL_ENABLE))
9036                 goto error;
9037
9038         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9039         fourcc = skl_format_to_fourcc(pixel_format,
9040                                       val & PLANE_CTL_ORDER_RGBX,
9041                                       val & PLANE_CTL_ALPHA_MASK);
9042         fb->pixel_format = fourcc;
9043         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9044
9045         tiling = val & PLANE_CTL_TILED_MASK;
9046         switch (tiling) {
9047         case PLANE_CTL_TILED_LINEAR:
9048                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9049                 break;
9050         case PLANE_CTL_TILED_X:
9051                 plane_config->tiling = I915_TILING_X;
9052                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9053                 break;
9054         case PLANE_CTL_TILED_Y:
9055                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9056                 break;
9057         case PLANE_CTL_TILED_YF:
9058                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9059                 break;
9060         default:
9061                 MISSING_CASE(tiling);
9062                 goto error;
9063         }
9064
9065         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9066         plane_config->base = base;
9067
9068         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9069
9070         val = I915_READ(PLANE_SIZE(pipe, 0));
9071         fb->height = ((val >> 16) & 0xfff) + 1;
9072         fb->width = ((val >> 0) & 0x1fff) + 1;
9073
9074         val = I915_READ(PLANE_STRIDE(pipe, 0));
9075         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9076                                                 fb->pixel_format);
9077         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9078
9079         aligned_height = intel_fb_align_height(dev, fb->height,
9080                                                fb->pixel_format,
9081                                                fb->modifier[0]);
9082
9083         plane_config->size = fb->pitches[0] * aligned_height;
9084
9085         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9086                       pipe_name(pipe), fb->width, fb->height,
9087                       fb->bits_per_pixel, base, fb->pitches[0],
9088                       plane_config->size);
9089
9090         plane_config->fb = intel_fb;
9091         return;
9092
9093 error:
9094         kfree(fb);
9095 }
9096
9097 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9098                                      struct intel_crtc_state *pipe_config)
9099 {
9100         struct drm_device *dev = crtc->base.dev;
9101         struct drm_i915_private *dev_priv = dev->dev_private;
9102         uint32_t tmp;
9103
9104         tmp = I915_READ(PF_CTL(crtc->pipe));
9105
9106         if (tmp & PF_ENABLE) {
9107                 pipe_config->pch_pfit.enabled = true;
9108                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9109                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9110
9111                 /* We currently do not free assignements of panel fitters on
9112                  * ivb/hsw (since we don't use the higher upscaling modes which
9113                  * differentiates them) so just WARN about this case for now. */
9114                 if (IS_GEN7(dev)) {
9115                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9116                                 PF_PIPE_SEL_IVB(crtc->pipe));
9117                 }
9118         }
9119 }
9120
9121 static void
9122 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9123                                   struct intel_initial_plane_config *plane_config)
9124 {
9125         struct drm_device *dev = crtc->base.dev;
9126         struct drm_i915_private *dev_priv = dev->dev_private;
9127         u32 val, base, offset;
9128         int pipe = crtc->pipe;
9129         int fourcc, pixel_format;
9130         unsigned int aligned_height;
9131         struct drm_framebuffer *fb;
9132         struct intel_framebuffer *intel_fb;
9133
9134         val = I915_READ(DSPCNTR(pipe));
9135         if (!(val & DISPLAY_PLANE_ENABLE))
9136                 return;
9137
9138         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9139         if (!intel_fb) {
9140                 DRM_DEBUG_KMS("failed to alloc fb\n");
9141                 return;
9142         }
9143
9144         fb = &intel_fb->base;
9145
9146         if (INTEL_INFO(dev)->gen >= 4) {
9147                 if (val & DISPPLANE_TILED) {
9148                         plane_config->tiling = I915_TILING_X;
9149                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9150                 }
9151         }
9152
9153         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9154         fourcc = i9xx_format_to_fourcc(pixel_format);
9155         fb->pixel_format = fourcc;
9156         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9157
9158         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9159         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9160                 offset = I915_READ(DSPOFFSET(pipe));
9161         } else {
9162                 if (plane_config->tiling)
9163                         offset = I915_READ(DSPTILEOFF(pipe));
9164                 else
9165                         offset = I915_READ(DSPLINOFF(pipe));
9166         }
9167         plane_config->base = base;
9168
9169         val = I915_READ(PIPESRC(pipe));
9170         fb->width = ((val >> 16) & 0xfff) + 1;
9171         fb->height = ((val >> 0) & 0xfff) + 1;
9172
9173         val = I915_READ(DSPSTRIDE(pipe));
9174         fb->pitches[0] = val & 0xffffffc0;
9175
9176         aligned_height = intel_fb_align_height(dev, fb->height,
9177                                                fb->pixel_format,
9178                                                fb->modifier[0]);
9179
9180         plane_config->size = fb->pitches[0] * aligned_height;
9181
9182         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9183                       pipe_name(pipe), fb->width, fb->height,
9184                       fb->bits_per_pixel, base, fb->pitches[0],
9185                       plane_config->size);
9186
9187         plane_config->fb = intel_fb;
9188 }
9189
9190 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9191                                      struct intel_crtc_state *pipe_config)
9192 {
9193         struct drm_device *dev = crtc->base.dev;
9194         struct drm_i915_private *dev_priv = dev->dev_private;
9195         uint32_t tmp;
9196
9197         if (!intel_display_power_is_enabled(dev_priv,
9198                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9199                 return false;
9200
9201         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9202         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9203
9204         tmp = I915_READ(PIPECONF(crtc->pipe));
9205         if (!(tmp & PIPECONF_ENABLE))
9206                 return false;
9207
9208         switch (tmp & PIPECONF_BPC_MASK) {
9209         case PIPECONF_6BPC:
9210                 pipe_config->pipe_bpp = 18;
9211                 break;
9212         case PIPECONF_8BPC:
9213                 pipe_config->pipe_bpp = 24;
9214                 break;
9215         case PIPECONF_10BPC:
9216                 pipe_config->pipe_bpp = 30;
9217                 break;
9218         case PIPECONF_12BPC:
9219                 pipe_config->pipe_bpp = 36;
9220                 break;
9221         default:
9222                 break;
9223         }
9224
9225         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9226                 pipe_config->limited_color_range = true;
9227
9228         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9229                 struct intel_shared_dpll *pll;
9230
9231                 pipe_config->has_pch_encoder = true;
9232
9233                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9234                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9235                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9236
9237                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9238
9239                 if (HAS_PCH_IBX(dev_priv->dev)) {
9240                         pipe_config->shared_dpll =
9241                                 (enum intel_dpll_id) crtc->pipe;
9242                 } else {
9243                         tmp = I915_READ(PCH_DPLL_SEL);
9244                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9245                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9246                         else
9247                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9248                 }
9249
9250                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9251
9252                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9253                                            &pipe_config->dpll_hw_state));
9254
9255                 tmp = pipe_config->dpll_hw_state.dpll;
9256                 pipe_config->pixel_multiplier =
9257                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9258                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9259
9260                 ironlake_pch_clock_get(crtc, pipe_config);
9261         } else {
9262                 pipe_config->pixel_multiplier = 1;
9263         }
9264
9265         intel_get_pipe_timings(crtc, pipe_config);
9266
9267         ironlake_get_pfit_config(crtc, pipe_config);
9268
9269         return true;
9270 }
9271
9272 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9273 {
9274         struct drm_device *dev = dev_priv->dev;
9275         struct intel_crtc *crtc;
9276
9277         for_each_intel_crtc(dev, crtc)
9278                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9279                      pipe_name(crtc->pipe));
9280
9281         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9282         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9283         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9284         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9285         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9286         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9287              "CPU PWM1 enabled\n");
9288         if (IS_HASWELL(dev))
9289                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9290                      "CPU PWM2 enabled\n");
9291         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9292              "PCH PWM1 enabled\n");
9293         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9294              "Utility pin enabled\n");
9295         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9296
9297         /*
9298          * In theory we can still leave IRQs enabled, as long as only the HPD
9299          * interrupts remain enabled. We used to check for that, but since it's
9300          * gen-specific and since we only disable LCPLL after we fully disable
9301          * the interrupts, the check below should be enough.
9302          */
9303         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9304 }
9305
9306 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9307 {
9308         struct drm_device *dev = dev_priv->dev;
9309
9310         if (IS_HASWELL(dev))
9311                 return I915_READ(D_COMP_HSW);
9312         else
9313                 return I915_READ(D_COMP_BDW);
9314 }
9315
9316 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9317 {
9318         struct drm_device *dev = dev_priv->dev;
9319
9320         if (IS_HASWELL(dev)) {
9321                 mutex_lock(&dev_priv->rps.hw_lock);
9322                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9323                                             val))
9324                         DRM_ERROR("Failed to write to D_COMP\n");
9325                 mutex_unlock(&dev_priv->rps.hw_lock);
9326         } else {
9327                 I915_WRITE(D_COMP_BDW, val);
9328                 POSTING_READ(D_COMP_BDW);
9329         }
9330 }
9331
9332 /*
9333  * This function implements pieces of two sequences from BSpec:
9334  * - Sequence for display software to disable LCPLL
9335  * - Sequence for display software to allow package C8+
9336  * The steps implemented here are just the steps that actually touch the LCPLL
9337  * register. Callers should take care of disabling all the display engine
9338  * functions, doing the mode unset, fixing interrupts, etc.
9339  */
9340 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9341                               bool switch_to_fclk, bool allow_power_down)
9342 {
9343         uint32_t val;
9344
9345         assert_can_disable_lcpll(dev_priv);
9346
9347         val = I915_READ(LCPLL_CTL);
9348
9349         if (switch_to_fclk) {
9350                 val |= LCPLL_CD_SOURCE_FCLK;
9351                 I915_WRITE(LCPLL_CTL, val);
9352
9353                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9354                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9355                         DRM_ERROR("Switching to FCLK failed\n");
9356
9357                 val = I915_READ(LCPLL_CTL);
9358         }
9359
9360         val |= LCPLL_PLL_DISABLE;
9361         I915_WRITE(LCPLL_CTL, val);
9362         POSTING_READ(LCPLL_CTL);
9363
9364         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9365                 DRM_ERROR("LCPLL still locked\n");
9366
9367         val = hsw_read_dcomp(dev_priv);
9368         val |= D_COMP_COMP_DISABLE;
9369         hsw_write_dcomp(dev_priv, val);
9370         ndelay(100);
9371
9372         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9373                      1))
9374                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9375
9376         if (allow_power_down) {
9377                 val = I915_READ(LCPLL_CTL);
9378                 val |= LCPLL_POWER_DOWN_ALLOW;
9379                 I915_WRITE(LCPLL_CTL, val);
9380                 POSTING_READ(LCPLL_CTL);
9381         }
9382 }
9383
9384 /*
9385  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9386  * source.
9387  */
9388 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9389 {
9390         uint32_t val;
9391
9392         val = I915_READ(LCPLL_CTL);
9393
9394         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9395                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9396                 return;
9397
9398         /*
9399          * Make sure we're not on PC8 state before disabling PC8, otherwise
9400          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9401          */
9402         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9403
9404         if (val & LCPLL_POWER_DOWN_ALLOW) {
9405                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9406                 I915_WRITE(LCPLL_CTL, val);
9407                 POSTING_READ(LCPLL_CTL);
9408         }
9409
9410         val = hsw_read_dcomp(dev_priv);
9411         val |= D_COMP_COMP_FORCE;
9412         val &= ~D_COMP_COMP_DISABLE;
9413         hsw_write_dcomp(dev_priv, val);
9414
9415         val = I915_READ(LCPLL_CTL);
9416         val &= ~LCPLL_PLL_DISABLE;
9417         I915_WRITE(LCPLL_CTL, val);
9418
9419         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9420                 DRM_ERROR("LCPLL not locked yet\n");
9421
9422         if (val & LCPLL_CD_SOURCE_FCLK) {
9423                 val = I915_READ(LCPLL_CTL);
9424                 val &= ~LCPLL_CD_SOURCE_FCLK;
9425                 I915_WRITE(LCPLL_CTL, val);
9426
9427                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9428                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9429                         DRM_ERROR("Switching back to LCPLL failed\n");
9430         }
9431
9432         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9433         intel_update_cdclk(dev_priv->dev);
9434 }
9435
9436 /*
9437  * Package states C8 and deeper are really deep PC states that can only be
9438  * reached when all the devices on the system allow it, so even if the graphics
9439  * device allows PC8+, it doesn't mean the system will actually get to these
9440  * states. Our driver only allows PC8+ when going into runtime PM.
9441  *
9442  * The requirements for PC8+ are that all the outputs are disabled, the power
9443  * well is disabled and most interrupts are disabled, and these are also
9444  * requirements for runtime PM. When these conditions are met, we manually do
9445  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9446  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9447  * hang the machine.
9448  *
9449  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9450  * the state of some registers, so when we come back from PC8+ we need to
9451  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9452  * need to take care of the registers kept by RC6. Notice that this happens even
9453  * if we don't put the device in PCI D3 state (which is what currently happens
9454  * because of the runtime PM support).
9455  *
9456  * For more, read "Display Sequences for Package C8" on the hardware
9457  * documentation.
9458  */
9459 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9460 {
9461         struct drm_device *dev = dev_priv->dev;
9462         uint32_t val;
9463
9464         DRM_DEBUG_KMS("Enabling package C8+\n");
9465
9466         if (HAS_PCH_LPT_LP(dev)) {
9467                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9468                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9469                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9470         }
9471
9472         lpt_disable_clkout_dp(dev);
9473         hsw_disable_lcpll(dev_priv, true, true);
9474 }
9475
9476 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9477 {
9478         struct drm_device *dev = dev_priv->dev;
9479         uint32_t val;
9480
9481         DRM_DEBUG_KMS("Disabling package C8+\n");
9482
9483         hsw_restore_lcpll(dev_priv);
9484         lpt_init_pch_refclk(dev);
9485
9486         if (HAS_PCH_LPT_LP(dev)) {
9487                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9488                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9489                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9490         }
9491
9492         intel_prepare_ddi(dev);
9493 }
9494
9495 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9496 {
9497         struct drm_device *dev = old_state->dev;
9498         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9499
9500         broxton_set_cdclk(dev, req_cdclk);
9501 }
9502
9503 /* compute the max rate for new configuration */
9504 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9505 {
9506         struct intel_crtc *intel_crtc;
9507         struct intel_crtc_state *crtc_state;
9508         int max_pixel_rate = 0;
9509
9510         for_each_intel_crtc(state->dev, intel_crtc) {
9511                 int pixel_rate;
9512
9513                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9514                 if (IS_ERR(crtc_state))
9515                         return PTR_ERR(crtc_state);
9516
9517                 if (!crtc_state->base.enable)
9518                         continue;
9519
9520                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9521
9522                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9523                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9524                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9525
9526                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9527         }
9528
9529         return max_pixel_rate;
9530 }
9531
9532 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9533 {
9534         struct drm_i915_private *dev_priv = dev->dev_private;
9535         uint32_t val, data;
9536         int ret;
9537
9538         if (WARN((I915_READ(LCPLL_CTL) &
9539                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9540                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9541                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9542                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9543                  "trying to change cdclk frequency with cdclk not enabled\n"))
9544                 return;
9545
9546         mutex_lock(&dev_priv->rps.hw_lock);
9547         ret = sandybridge_pcode_write(dev_priv,
9548                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9549         mutex_unlock(&dev_priv->rps.hw_lock);
9550         if (ret) {
9551                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9552                 return;
9553         }
9554
9555         val = I915_READ(LCPLL_CTL);
9556         val |= LCPLL_CD_SOURCE_FCLK;
9557         I915_WRITE(LCPLL_CTL, val);
9558
9559         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9560                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9561                 DRM_ERROR("Switching to FCLK failed\n");
9562
9563         val = I915_READ(LCPLL_CTL);
9564         val &= ~LCPLL_CLK_FREQ_MASK;
9565
9566         switch (cdclk) {
9567         case 450000:
9568                 val |= LCPLL_CLK_FREQ_450;
9569                 data = 0;
9570                 break;
9571         case 540000:
9572                 val |= LCPLL_CLK_FREQ_54O_BDW;
9573                 data = 1;
9574                 break;
9575         case 337500:
9576                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9577                 data = 2;
9578                 break;
9579         case 675000:
9580                 val |= LCPLL_CLK_FREQ_675_BDW;
9581                 data = 3;
9582                 break;
9583         default:
9584                 WARN(1, "invalid cdclk frequency\n");
9585                 return;
9586         }
9587
9588         I915_WRITE(LCPLL_CTL, val);
9589
9590         val = I915_READ(LCPLL_CTL);
9591         val &= ~LCPLL_CD_SOURCE_FCLK;
9592         I915_WRITE(LCPLL_CTL, val);
9593
9594         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9595                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9596                 DRM_ERROR("Switching back to LCPLL failed\n");
9597
9598         mutex_lock(&dev_priv->rps.hw_lock);
9599         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9600         mutex_unlock(&dev_priv->rps.hw_lock);
9601
9602         intel_update_cdclk(dev);
9603
9604         WARN(cdclk != dev_priv->cdclk_freq,
9605              "cdclk requested %d kHz but got %d kHz\n",
9606              cdclk, dev_priv->cdclk_freq);
9607 }
9608
9609 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9610 {
9611         struct drm_i915_private *dev_priv = to_i915(state->dev);
9612         int max_pixclk = ilk_max_pixel_rate(state);
9613         int cdclk;
9614
9615         /*
9616          * FIXME should also account for plane ratio
9617          * once 64bpp pixel formats are supported.
9618          */
9619         if (max_pixclk > 540000)
9620                 cdclk = 675000;
9621         else if (max_pixclk > 450000)
9622                 cdclk = 540000;
9623         else if (max_pixclk > 337500)
9624                 cdclk = 450000;
9625         else
9626                 cdclk = 337500;
9627
9628         /*
9629          * FIXME move the cdclk caclulation to
9630          * compute_config() so we can fail gracegully.
9631          */
9632         if (cdclk > dev_priv->max_cdclk_freq) {
9633                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9634                           cdclk, dev_priv->max_cdclk_freq);
9635                 cdclk = dev_priv->max_cdclk_freq;
9636         }
9637
9638         to_intel_atomic_state(state)->cdclk = cdclk;
9639
9640         return 0;
9641 }
9642
9643 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9644 {
9645         struct drm_device *dev = old_state->dev;
9646         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9647
9648         broadwell_set_cdclk(dev, req_cdclk);
9649 }
9650
9651 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9652                                       struct intel_crtc_state *crtc_state)
9653 {
9654         if (!intel_ddi_pll_select(crtc, crtc_state))
9655                 return -EINVAL;
9656
9657         crtc->lowfreq_avail = false;
9658
9659         return 0;
9660 }
9661
9662 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9663                                 enum port port,
9664                                 struct intel_crtc_state *pipe_config)
9665 {
9666         switch (port) {
9667         case PORT_A:
9668                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9669                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9670                 break;
9671         case PORT_B:
9672                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9673                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9674                 break;
9675         case PORT_C:
9676                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9677                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9678                 break;
9679         default:
9680                 DRM_ERROR("Incorrect port type\n");
9681         }
9682 }
9683
9684 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9685                                 enum port port,
9686                                 struct intel_crtc_state *pipe_config)
9687 {
9688         u32 temp, dpll_ctl1;
9689
9690         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9691         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9692
9693         switch (pipe_config->ddi_pll_sel) {
9694         case SKL_DPLL0:
9695                 /*
9696                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9697                  * of the shared DPLL framework and thus needs to be read out
9698                  * separately
9699                  */
9700                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9701                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9702                 break;
9703         case SKL_DPLL1:
9704                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9705                 break;
9706         case SKL_DPLL2:
9707                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9708                 break;
9709         case SKL_DPLL3:
9710                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9711                 break;
9712         }
9713 }
9714
9715 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9716                                 enum port port,
9717                                 struct intel_crtc_state *pipe_config)
9718 {
9719         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9720
9721         switch (pipe_config->ddi_pll_sel) {
9722         case PORT_CLK_SEL_WRPLL1:
9723                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9724                 break;
9725         case PORT_CLK_SEL_WRPLL2:
9726                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9727                 break;
9728         }
9729 }
9730
9731 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9732                                        struct intel_crtc_state *pipe_config)
9733 {
9734         struct drm_device *dev = crtc->base.dev;
9735         struct drm_i915_private *dev_priv = dev->dev_private;
9736         struct intel_shared_dpll *pll;
9737         enum port port;
9738         uint32_t tmp;
9739
9740         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9741
9742         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9743
9744         if (IS_SKYLAKE(dev))
9745                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9746         else if (IS_BROXTON(dev))
9747                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9748         else
9749                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9750
9751         if (pipe_config->shared_dpll >= 0) {
9752                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9753
9754                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9755                                            &pipe_config->dpll_hw_state));
9756         }
9757
9758         /*
9759          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9760          * DDI E. So just check whether this pipe is wired to DDI E and whether
9761          * the PCH transcoder is on.
9762          */
9763         if (INTEL_INFO(dev)->gen < 9 &&
9764             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9765                 pipe_config->has_pch_encoder = true;
9766
9767                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9768                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9769                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9770
9771                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9772         }
9773 }
9774
9775 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9776                                     struct intel_crtc_state *pipe_config)
9777 {
9778         struct drm_device *dev = crtc->base.dev;
9779         struct drm_i915_private *dev_priv = dev->dev_private;
9780         enum intel_display_power_domain pfit_domain;
9781         uint32_t tmp;
9782
9783         if (!intel_display_power_is_enabled(dev_priv,
9784                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9785                 return false;
9786
9787         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9788         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9789
9790         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9791         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9792                 enum pipe trans_edp_pipe;
9793                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9794                 default:
9795                         WARN(1, "unknown pipe linked to edp transcoder\n");
9796                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9797                 case TRANS_DDI_EDP_INPUT_A_ON:
9798                         trans_edp_pipe = PIPE_A;
9799                         break;
9800                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9801                         trans_edp_pipe = PIPE_B;
9802                         break;
9803                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9804                         trans_edp_pipe = PIPE_C;
9805                         break;
9806                 }
9807
9808                 if (trans_edp_pipe == crtc->pipe)
9809                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9810         }
9811
9812         if (!intel_display_power_is_enabled(dev_priv,
9813                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9814                 return false;
9815
9816         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9817         if (!(tmp & PIPECONF_ENABLE))
9818                 return false;
9819
9820         haswell_get_ddi_port_state(crtc, pipe_config);
9821
9822         intel_get_pipe_timings(crtc, pipe_config);
9823
9824         if (INTEL_INFO(dev)->gen >= 9) {
9825                 skl_init_scalers(dev, crtc, pipe_config);
9826         }
9827
9828         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9829
9830         if (INTEL_INFO(dev)->gen >= 9) {
9831                 pipe_config->scaler_state.scaler_id = -1;
9832                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9833         }
9834
9835         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9836                 if (INTEL_INFO(dev)->gen >= 9)
9837                         skylake_get_pfit_config(crtc, pipe_config);
9838                 else
9839                         ironlake_get_pfit_config(crtc, pipe_config);
9840         }
9841
9842         if (IS_HASWELL(dev))
9843                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9844                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9845
9846         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9847                 pipe_config->pixel_multiplier =
9848                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9849         } else {
9850                 pipe_config->pixel_multiplier = 1;
9851         }
9852
9853         return true;
9854 }
9855
9856 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9857 {
9858         struct drm_device *dev = crtc->dev;
9859         struct drm_i915_private *dev_priv = dev->dev_private;
9860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9861         uint32_t cntl = 0, size = 0;
9862
9863         if (base) {
9864                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9865                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9866                 unsigned int stride = roundup_pow_of_two(width) * 4;
9867
9868                 switch (stride) {
9869                 default:
9870                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9871                                   width, stride);
9872                         stride = 256;
9873                         /* fallthrough */
9874                 case 256:
9875                 case 512:
9876                 case 1024:
9877                 case 2048:
9878                         break;
9879                 }
9880
9881                 cntl |= CURSOR_ENABLE |
9882                         CURSOR_GAMMA_ENABLE |
9883                         CURSOR_FORMAT_ARGB |
9884                         CURSOR_STRIDE(stride);
9885
9886                 size = (height << 12) | width;
9887         }
9888
9889         if (intel_crtc->cursor_cntl != 0 &&
9890             (intel_crtc->cursor_base != base ||
9891              intel_crtc->cursor_size != size ||
9892              intel_crtc->cursor_cntl != cntl)) {
9893                 /* On these chipsets we can only modify the base/size/stride
9894                  * whilst the cursor is disabled.
9895                  */
9896                 I915_WRITE(CURCNTR(PIPE_A), 0);
9897                 POSTING_READ(CURCNTR(PIPE_A));
9898                 intel_crtc->cursor_cntl = 0;
9899         }
9900
9901         if (intel_crtc->cursor_base != base) {
9902                 I915_WRITE(CURBASE(PIPE_A), base);
9903                 intel_crtc->cursor_base = base;
9904         }
9905
9906         if (intel_crtc->cursor_size != size) {
9907                 I915_WRITE(CURSIZE, size);
9908                 intel_crtc->cursor_size = size;
9909         }
9910
9911         if (intel_crtc->cursor_cntl != cntl) {
9912                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9913                 POSTING_READ(CURCNTR(PIPE_A));
9914                 intel_crtc->cursor_cntl = cntl;
9915         }
9916 }
9917
9918 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9919 {
9920         struct drm_device *dev = crtc->dev;
9921         struct drm_i915_private *dev_priv = dev->dev_private;
9922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9923         int pipe = intel_crtc->pipe;
9924         uint32_t cntl;
9925
9926         cntl = 0;
9927         if (base) {
9928                 cntl = MCURSOR_GAMMA_ENABLE;
9929                 switch (intel_crtc->base.cursor->state->crtc_w) {
9930                         case 64:
9931                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9932                                 break;
9933                         case 128:
9934                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9935                                 break;
9936                         case 256:
9937                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9938                                 break;
9939                         default:
9940                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9941                                 return;
9942                 }
9943                 cntl |= pipe << 28; /* Connect to correct pipe */
9944
9945                 if (HAS_DDI(dev))
9946                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9947         }
9948
9949         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9950                 cntl |= CURSOR_ROTATE_180;
9951
9952         if (intel_crtc->cursor_cntl != cntl) {
9953                 I915_WRITE(CURCNTR(pipe), cntl);
9954                 POSTING_READ(CURCNTR(pipe));
9955                 intel_crtc->cursor_cntl = cntl;
9956         }
9957
9958         /* and commit changes on next vblank */
9959         I915_WRITE(CURBASE(pipe), base);
9960         POSTING_READ(CURBASE(pipe));
9961
9962         intel_crtc->cursor_base = base;
9963 }
9964
9965 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9966 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9967                                      bool on)
9968 {
9969         struct drm_device *dev = crtc->dev;
9970         struct drm_i915_private *dev_priv = dev->dev_private;
9971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9972         int pipe = intel_crtc->pipe;
9973         struct drm_plane_state *cursor_state = crtc->cursor->state;
9974         int x = cursor_state->crtc_x;
9975         int y = cursor_state->crtc_y;
9976         u32 base = 0, pos = 0;
9977
9978         if (on)
9979                 base = intel_crtc->cursor_addr;
9980
9981         if (x >= intel_crtc->config->pipe_src_w)
9982                 base = 0;
9983
9984         if (y >= intel_crtc->config->pipe_src_h)
9985                 base = 0;
9986
9987         if (x < 0) {
9988                 if (x + cursor_state->crtc_w <= 0)
9989                         base = 0;
9990
9991                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9992                 x = -x;
9993         }
9994         pos |= x << CURSOR_X_SHIFT;
9995
9996         if (y < 0) {
9997                 if (y + cursor_state->crtc_h <= 0)
9998                         base = 0;
9999
10000                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10001                 y = -y;
10002         }
10003         pos |= y << CURSOR_Y_SHIFT;
10004
10005         if (base == 0 && intel_crtc->cursor_base == 0)
10006                 return;
10007
10008         I915_WRITE(CURPOS(pipe), pos);
10009
10010         /* ILK+ do this automagically */
10011         if (HAS_GMCH_DISPLAY(dev) &&
10012             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10013                 base += (cursor_state->crtc_h *
10014                          cursor_state->crtc_w - 1) * 4;
10015         }
10016
10017         if (IS_845G(dev) || IS_I865G(dev))
10018                 i845_update_cursor(crtc, base);
10019         else
10020                 i9xx_update_cursor(crtc, base);
10021 }
10022
10023 static bool cursor_size_ok(struct drm_device *dev,
10024                            uint32_t width, uint32_t height)
10025 {
10026         if (width == 0 || height == 0)
10027                 return false;
10028
10029         /*
10030          * 845g/865g are special in that they are only limited by
10031          * the width of their cursors, the height is arbitrary up to
10032          * the precision of the register. Everything else requires
10033          * square cursors, limited to a few power-of-two sizes.
10034          */
10035         if (IS_845G(dev) || IS_I865G(dev)) {
10036                 if ((width & 63) != 0)
10037                         return false;
10038
10039                 if (width > (IS_845G(dev) ? 64 : 512))
10040                         return false;
10041
10042                 if (height > 1023)
10043                         return false;
10044         } else {
10045                 switch (width | height) {
10046                 case 256:
10047                 case 128:
10048                         if (IS_GEN2(dev))
10049                                 return false;
10050                 case 64:
10051                         break;
10052                 default:
10053                         return false;
10054                 }
10055         }
10056
10057         return true;
10058 }
10059
10060 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10061                                  u16 *blue, uint32_t start, uint32_t size)
10062 {
10063         int end = (start + size > 256) ? 256 : start + size, i;
10064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10065
10066         for (i = start; i < end; i++) {
10067                 intel_crtc->lut_r[i] = red[i] >> 8;
10068                 intel_crtc->lut_g[i] = green[i] >> 8;
10069                 intel_crtc->lut_b[i] = blue[i] >> 8;
10070         }
10071
10072         intel_crtc_load_lut(crtc);
10073 }
10074
10075 /* VESA 640x480x72Hz mode to set on the pipe */
10076 static struct drm_display_mode load_detect_mode = {
10077         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10078                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10079 };
10080
10081 struct drm_framebuffer *
10082 __intel_framebuffer_create(struct drm_device *dev,
10083                            struct drm_mode_fb_cmd2 *mode_cmd,
10084                            struct drm_i915_gem_object *obj)
10085 {
10086         struct intel_framebuffer *intel_fb;
10087         int ret;
10088
10089         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10090         if (!intel_fb) {
10091                 drm_gem_object_unreference(&obj->base);
10092                 return ERR_PTR(-ENOMEM);
10093         }
10094
10095         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10096         if (ret)
10097                 goto err;
10098
10099         return &intel_fb->base;
10100 err:
10101         drm_gem_object_unreference(&obj->base);
10102         kfree(intel_fb);
10103
10104         return ERR_PTR(ret);
10105 }
10106
10107 static struct drm_framebuffer *
10108 intel_framebuffer_create(struct drm_device *dev,
10109                          struct drm_mode_fb_cmd2 *mode_cmd,
10110                          struct drm_i915_gem_object *obj)
10111 {
10112         struct drm_framebuffer *fb;
10113         int ret;
10114
10115         ret = i915_mutex_lock_interruptible(dev);
10116         if (ret)
10117                 return ERR_PTR(ret);
10118         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10119         mutex_unlock(&dev->struct_mutex);
10120
10121         return fb;
10122 }
10123
10124 static u32
10125 intel_framebuffer_pitch_for_width(int width, int bpp)
10126 {
10127         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10128         return ALIGN(pitch, 64);
10129 }
10130
10131 static u32
10132 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10133 {
10134         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10135         return PAGE_ALIGN(pitch * mode->vdisplay);
10136 }
10137
10138 static struct drm_framebuffer *
10139 intel_framebuffer_create_for_mode(struct drm_device *dev,
10140                                   struct drm_display_mode *mode,
10141                                   int depth, int bpp)
10142 {
10143         struct drm_i915_gem_object *obj;
10144         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10145
10146         obj = i915_gem_alloc_object(dev,
10147                                     intel_framebuffer_size_for_mode(mode, bpp));
10148         if (obj == NULL)
10149                 return ERR_PTR(-ENOMEM);
10150
10151         mode_cmd.width = mode->hdisplay;
10152         mode_cmd.height = mode->vdisplay;
10153         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10154                                                                 bpp);
10155         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10156
10157         return intel_framebuffer_create(dev, &mode_cmd, obj);
10158 }
10159
10160 static struct drm_framebuffer *
10161 mode_fits_in_fbdev(struct drm_device *dev,
10162                    struct drm_display_mode *mode)
10163 {
10164 #ifdef CONFIG_DRM_FBDEV_EMULATION
10165         struct drm_i915_private *dev_priv = dev->dev_private;
10166         struct drm_i915_gem_object *obj;
10167         struct drm_framebuffer *fb;
10168
10169         if (!dev_priv->fbdev)
10170                 return NULL;
10171
10172         if (!dev_priv->fbdev->fb)
10173                 return NULL;
10174
10175         obj = dev_priv->fbdev->fb->obj;
10176         BUG_ON(!obj);
10177
10178         fb = &dev_priv->fbdev->fb->base;
10179         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10180                                                                fb->bits_per_pixel))
10181                 return NULL;
10182
10183         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10184                 return NULL;
10185
10186         return fb;
10187 #else
10188         return NULL;
10189 #endif
10190 }
10191
10192 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10193                                            struct drm_crtc *crtc,
10194                                            struct drm_display_mode *mode,
10195                                            struct drm_framebuffer *fb,
10196                                            int x, int y)
10197 {
10198         struct drm_plane_state *plane_state;
10199         int hdisplay, vdisplay;
10200         int ret;
10201
10202         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10203         if (IS_ERR(plane_state))
10204                 return PTR_ERR(plane_state);
10205
10206         if (mode)
10207                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10208         else
10209                 hdisplay = vdisplay = 0;
10210
10211         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10212         if (ret)
10213                 return ret;
10214         drm_atomic_set_fb_for_plane(plane_state, fb);
10215         plane_state->crtc_x = 0;
10216         plane_state->crtc_y = 0;
10217         plane_state->crtc_w = hdisplay;
10218         plane_state->crtc_h = vdisplay;
10219         plane_state->src_x = x << 16;
10220         plane_state->src_y = y << 16;
10221         plane_state->src_w = hdisplay << 16;
10222         plane_state->src_h = vdisplay << 16;
10223
10224         return 0;
10225 }
10226
10227 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10228                                 struct drm_display_mode *mode,
10229                                 struct intel_load_detect_pipe *old,
10230                                 struct drm_modeset_acquire_ctx *ctx)
10231 {
10232         struct intel_crtc *intel_crtc;
10233         struct intel_encoder *intel_encoder =
10234                 intel_attached_encoder(connector);
10235         struct drm_crtc *possible_crtc;
10236         struct drm_encoder *encoder = &intel_encoder->base;
10237         struct drm_crtc *crtc = NULL;
10238         struct drm_device *dev = encoder->dev;
10239         struct drm_framebuffer *fb;
10240         struct drm_mode_config *config = &dev->mode_config;
10241         struct drm_atomic_state *state = NULL;
10242         struct drm_connector_state *connector_state;
10243         struct intel_crtc_state *crtc_state;
10244         int ret, i = -1;
10245
10246         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10247                       connector->base.id, connector->name,
10248                       encoder->base.id, encoder->name);
10249
10250 retry:
10251         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10252         if (ret)
10253                 goto fail;
10254
10255         /*
10256          * Algorithm gets a little messy:
10257          *
10258          *   - if the connector already has an assigned crtc, use it (but make
10259          *     sure it's on first)
10260          *
10261          *   - try to find the first unused crtc that can drive this connector,
10262          *     and use that if we find one
10263          */
10264
10265         /* See if we already have a CRTC for this connector */
10266         if (encoder->crtc) {
10267                 crtc = encoder->crtc;
10268
10269                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10270                 if (ret)
10271                         goto fail;
10272                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10273                 if (ret)
10274                         goto fail;
10275
10276                 old->dpms_mode = connector->dpms;
10277                 old->load_detect_temp = false;
10278
10279                 /* Make sure the crtc and connector are running */
10280                 if (connector->dpms != DRM_MODE_DPMS_ON)
10281                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10282
10283                 return true;
10284         }
10285
10286         /* Find an unused one (if possible) */
10287         for_each_crtc(dev, possible_crtc) {
10288                 i++;
10289                 if (!(encoder->possible_crtcs & (1 << i)))
10290                         continue;
10291                 if (possible_crtc->state->enable)
10292                         continue;
10293
10294                 crtc = possible_crtc;
10295                 break;
10296         }
10297
10298         /*
10299          * If we didn't find an unused CRTC, don't use any.
10300          */
10301         if (!crtc) {
10302                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10303                 goto fail;
10304         }
10305
10306         ret = drm_modeset_lock(&crtc->mutex, ctx);
10307         if (ret)
10308                 goto fail;
10309         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10310         if (ret)
10311                 goto fail;
10312
10313         intel_crtc = to_intel_crtc(crtc);
10314         old->dpms_mode = connector->dpms;
10315         old->load_detect_temp = true;
10316         old->release_fb = NULL;
10317
10318         state = drm_atomic_state_alloc(dev);
10319         if (!state)
10320                 return false;
10321
10322         state->acquire_ctx = ctx;
10323
10324         connector_state = drm_atomic_get_connector_state(state, connector);
10325         if (IS_ERR(connector_state)) {
10326                 ret = PTR_ERR(connector_state);
10327                 goto fail;
10328         }
10329
10330         connector_state->crtc = crtc;
10331         connector_state->best_encoder = &intel_encoder->base;
10332
10333         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10334         if (IS_ERR(crtc_state)) {
10335                 ret = PTR_ERR(crtc_state);
10336                 goto fail;
10337         }
10338
10339         crtc_state->base.active = crtc_state->base.enable = true;
10340
10341         if (!mode)
10342                 mode = &load_detect_mode;
10343
10344         /* We need a framebuffer large enough to accommodate all accesses
10345          * that the plane may generate whilst we perform load detection.
10346          * We can not rely on the fbcon either being present (we get called
10347          * during its initialisation to detect all boot displays, or it may
10348          * not even exist) or that it is large enough to satisfy the
10349          * requested mode.
10350          */
10351         fb = mode_fits_in_fbdev(dev, mode);
10352         if (fb == NULL) {
10353                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10354                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10355                 old->release_fb = fb;
10356         } else
10357                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10358         if (IS_ERR(fb)) {
10359                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10360                 goto fail;
10361         }
10362
10363         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10364         if (ret)
10365                 goto fail;
10366
10367         drm_mode_copy(&crtc_state->base.mode, mode);
10368
10369         if (drm_atomic_commit(state)) {
10370                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10371                 if (old->release_fb)
10372                         old->release_fb->funcs->destroy(old->release_fb);
10373                 goto fail;
10374         }
10375         crtc->primary->crtc = crtc;
10376
10377         /* let the connector get through one full cycle before testing */
10378         intel_wait_for_vblank(dev, intel_crtc->pipe);
10379         return true;
10380
10381 fail:
10382         drm_atomic_state_free(state);
10383         state = NULL;
10384
10385         if (ret == -EDEADLK) {
10386                 drm_modeset_backoff(ctx);
10387                 goto retry;
10388         }
10389
10390         return false;
10391 }
10392
10393 void intel_release_load_detect_pipe(struct drm_connector *connector,
10394                                     struct intel_load_detect_pipe *old,
10395                                     struct drm_modeset_acquire_ctx *ctx)
10396 {
10397         struct drm_device *dev = connector->dev;
10398         struct intel_encoder *intel_encoder =
10399                 intel_attached_encoder(connector);
10400         struct drm_encoder *encoder = &intel_encoder->base;
10401         struct drm_crtc *crtc = encoder->crtc;
10402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10403         struct drm_atomic_state *state;
10404         struct drm_connector_state *connector_state;
10405         struct intel_crtc_state *crtc_state;
10406         int ret;
10407
10408         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10409                       connector->base.id, connector->name,
10410                       encoder->base.id, encoder->name);
10411
10412         if (old->load_detect_temp) {
10413                 state = drm_atomic_state_alloc(dev);
10414                 if (!state)
10415                         goto fail;
10416
10417                 state->acquire_ctx = ctx;
10418
10419                 connector_state = drm_atomic_get_connector_state(state, connector);
10420                 if (IS_ERR(connector_state))
10421                         goto fail;
10422
10423                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10424                 if (IS_ERR(crtc_state))
10425                         goto fail;
10426
10427                 connector_state->best_encoder = NULL;
10428                 connector_state->crtc = NULL;
10429
10430                 crtc_state->base.enable = crtc_state->base.active = false;
10431
10432                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10433                                                       0, 0);
10434                 if (ret)
10435                         goto fail;
10436
10437                 ret = drm_atomic_commit(state);
10438                 if (ret)
10439                         goto fail;
10440
10441                 if (old->release_fb) {
10442                         drm_framebuffer_unregister_private(old->release_fb);
10443                         drm_framebuffer_unreference(old->release_fb);
10444                 }
10445
10446                 return;
10447         }
10448
10449         /* Switch crtc and encoder back off if necessary */
10450         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10451                 connector->funcs->dpms(connector, old->dpms_mode);
10452
10453         return;
10454 fail:
10455         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10456         drm_atomic_state_free(state);
10457 }
10458
10459 static int i9xx_pll_refclk(struct drm_device *dev,
10460                            const struct intel_crtc_state *pipe_config)
10461 {
10462         struct drm_i915_private *dev_priv = dev->dev_private;
10463         u32 dpll = pipe_config->dpll_hw_state.dpll;
10464
10465         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10466                 return dev_priv->vbt.lvds_ssc_freq;
10467         else if (HAS_PCH_SPLIT(dev))
10468                 return 120000;
10469         else if (!IS_GEN2(dev))
10470                 return 96000;
10471         else
10472                 return 48000;
10473 }
10474
10475 /* Returns the clock of the currently programmed mode of the given pipe. */
10476 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10477                                 struct intel_crtc_state *pipe_config)
10478 {
10479         struct drm_device *dev = crtc->base.dev;
10480         struct drm_i915_private *dev_priv = dev->dev_private;
10481         int pipe = pipe_config->cpu_transcoder;
10482         u32 dpll = pipe_config->dpll_hw_state.dpll;
10483         u32 fp;
10484         intel_clock_t clock;
10485         int port_clock;
10486         int refclk = i9xx_pll_refclk(dev, pipe_config);
10487
10488         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10489                 fp = pipe_config->dpll_hw_state.fp0;
10490         else
10491                 fp = pipe_config->dpll_hw_state.fp1;
10492
10493         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10494         if (IS_PINEVIEW(dev)) {
10495                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10496                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10497         } else {
10498                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10499                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10500         }
10501
10502         if (!IS_GEN2(dev)) {
10503                 if (IS_PINEVIEW(dev))
10504                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10505                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10506                 else
10507                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10508                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10509
10510                 switch (dpll & DPLL_MODE_MASK) {
10511                 case DPLLB_MODE_DAC_SERIAL:
10512                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10513                                 5 : 10;
10514                         break;
10515                 case DPLLB_MODE_LVDS:
10516                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10517                                 7 : 14;
10518                         break;
10519                 default:
10520                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10521                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10522                         return;
10523                 }
10524
10525                 if (IS_PINEVIEW(dev))
10526                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10527                 else
10528                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10529         } else {
10530                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10531                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10532
10533                 if (is_lvds) {
10534                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10535                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10536
10537                         if (lvds & LVDS_CLKB_POWER_UP)
10538                                 clock.p2 = 7;
10539                         else
10540                                 clock.p2 = 14;
10541                 } else {
10542                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10543                                 clock.p1 = 2;
10544                         else {
10545                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10546                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10547                         }
10548                         if (dpll & PLL_P2_DIVIDE_BY_4)
10549                                 clock.p2 = 4;
10550                         else
10551                                 clock.p2 = 2;
10552                 }
10553
10554                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10555         }
10556
10557         /*
10558          * This value includes pixel_multiplier. We will use
10559          * port_clock to compute adjusted_mode.crtc_clock in the
10560          * encoder's get_config() function.
10561          */
10562         pipe_config->port_clock = port_clock;
10563 }
10564
10565 int intel_dotclock_calculate(int link_freq,
10566                              const struct intel_link_m_n *m_n)
10567 {
10568         /*
10569          * The calculation for the data clock is:
10570          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10571          * But we want to avoid losing precison if possible, so:
10572          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10573          *
10574          * and the link clock is simpler:
10575          * link_clock = (m * link_clock) / n
10576          */
10577
10578         if (!m_n->link_n)
10579                 return 0;
10580
10581         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10582 }
10583
10584 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10585                                    struct intel_crtc_state *pipe_config)
10586 {
10587         struct drm_device *dev = crtc->base.dev;
10588
10589         /* read out port_clock from the DPLL */
10590         i9xx_crtc_clock_get(crtc, pipe_config);
10591
10592         /*
10593          * This value does not include pixel_multiplier.
10594          * We will check that port_clock and adjusted_mode.crtc_clock
10595          * agree once we know their relationship in the encoder's
10596          * get_config() function.
10597          */
10598         pipe_config->base.adjusted_mode.crtc_clock =
10599                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10600                                          &pipe_config->fdi_m_n);
10601 }
10602
10603 /** Returns the currently programmed mode of the given pipe. */
10604 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10605                                              struct drm_crtc *crtc)
10606 {
10607         struct drm_i915_private *dev_priv = dev->dev_private;
10608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10609         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10610         struct drm_display_mode *mode;
10611         struct intel_crtc_state pipe_config;
10612         int htot = I915_READ(HTOTAL(cpu_transcoder));
10613         int hsync = I915_READ(HSYNC(cpu_transcoder));
10614         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10615         int vsync = I915_READ(VSYNC(cpu_transcoder));
10616         enum pipe pipe = intel_crtc->pipe;
10617
10618         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10619         if (!mode)
10620                 return NULL;
10621
10622         /*
10623          * Construct a pipe_config sufficient for getting the clock info
10624          * back out of crtc_clock_get.
10625          *
10626          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10627          * to use a real value here instead.
10628          */
10629         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10630         pipe_config.pixel_multiplier = 1;
10631         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10632         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10633         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10634         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10635
10636         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10637         mode->hdisplay = (htot & 0xffff) + 1;
10638         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10639         mode->hsync_start = (hsync & 0xffff) + 1;
10640         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10641         mode->vdisplay = (vtot & 0xffff) + 1;
10642         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10643         mode->vsync_start = (vsync & 0xffff) + 1;
10644         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10645
10646         drm_mode_set_name(mode);
10647
10648         return mode;
10649 }
10650
10651 void intel_mark_busy(struct drm_device *dev)
10652 {
10653         struct drm_i915_private *dev_priv = dev->dev_private;
10654
10655         if (dev_priv->mm.busy)
10656                 return;
10657
10658         intel_runtime_pm_get(dev_priv);
10659         i915_update_gfx_val(dev_priv);
10660         if (INTEL_INFO(dev)->gen >= 6)
10661                 gen6_rps_busy(dev_priv);
10662         dev_priv->mm.busy = true;
10663 }
10664
10665 void intel_mark_idle(struct drm_device *dev)
10666 {
10667         struct drm_i915_private *dev_priv = dev->dev_private;
10668
10669         if (!dev_priv->mm.busy)
10670                 return;
10671
10672         dev_priv->mm.busy = false;
10673
10674         if (INTEL_INFO(dev)->gen >= 6)
10675                 gen6_rps_idle(dev->dev_private);
10676
10677         intel_runtime_pm_put(dev_priv);
10678 }
10679
10680 static void intel_crtc_destroy(struct drm_crtc *crtc)
10681 {
10682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10683         struct drm_device *dev = crtc->dev;
10684         struct intel_unpin_work *work;
10685
10686         spin_lock_irq(&dev->event_lock);
10687         work = intel_crtc->unpin_work;
10688         intel_crtc->unpin_work = NULL;
10689         spin_unlock_irq(&dev->event_lock);
10690
10691         if (work) {
10692                 cancel_work_sync(&work->work);
10693                 kfree(work);
10694         }
10695
10696         drm_crtc_cleanup(crtc);
10697
10698         kfree(intel_crtc);
10699 }
10700
10701 static void intel_unpin_work_fn(struct work_struct *__work)
10702 {
10703         struct intel_unpin_work *work =
10704                 container_of(__work, struct intel_unpin_work, work);
10705         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10706         struct drm_device *dev = crtc->base.dev;
10707         struct drm_plane *primary = crtc->base.primary;
10708
10709         mutex_lock(&dev->struct_mutex);
10710         intel_unpin_fb_obj(work->old_fb, primary->state);
10711         drm_gem_object_unreference(&work->pending_flip_obj->base);
10712
10713         if (work->flip_queued_req)
10714                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10715         mutex_unlock(&dev->struct_mutex);
10716
10717         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10718         drm_framebuffer_unreference(work->old_fb);
10719
10720         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10721         atomic_dec(&crtc->unpin_work_count);
10722
10723         kfree(work);
10724 }
10725
10726 static void do_intel_finish_page_flip(struct drm_device *dev,
10727                                       struct drm_crtc *crtc)
10728 {
10729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10730         struct intel_unpin_work *work;
10731         unsigned long flags;
10732
10733         /* Ignore early vblank irqs */
10734         if (intel_crtc == NULL)
10735                 return;
10736
10737         /*
10738          * This is called both by irq handlers and the reset code (to complete
10739          * lost pageflips) so needs the full irqsave spinlocks.
10740          */
10741         spin_lock_irqsave(&dev->event_lock, flags);
10742         work = intel_crtc->unpin_work;
10743
10744         /* Ensure we don't miss a work->pending update ... */
10745         smp_rmb();
10746
10747         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10748                 spin_unlock_irqrestore(&dev->event_lock, flags);
10749                 return;
10750         }
10751
10752         page_flip_completed(intel_crtc);
10753
10754         spin_unlock_irqrestore(&dev->event_lock, flags);
10755 }
10756
10757 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10758 {
10759         struct drm_i915_private *dev_priv = dev->dev_private;
10760         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10761
10762         do_intel_finish_page_flip(dev, crtc);
10763 }
10764
10765 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10766 {
10767         struct drm_i915_private *dev_priv = dev->dev_private;
10768         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10769
10770         do_intel_finish_page_flip(dev, crtc);
10771 }
10772
10773 /* Is 'a' after or equal to 'b'? */
10774 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10775 {
10776         return !((a - b) & 0x80000000);
10777 }
10778
10779 static bool page_flip_finished(struct intel_crtc *crtc)
10780 {
10781         struct drm_device *dev = crtc->base.dev;
10782         struct drm_i915_private *dev_priv = dev->dev_private;
10783
10784         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10785             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10786                 return true;
10787
10788         /*
10789          * The relevant registers doen't exist on pre-ctg.
10790          * As the flip done interrupt doesn't trigger for mmio
10791          * flips on gmch platforms, a flip count check isn't
10792          * really needed there. But since ctg has the registers,
10793          * include it in the check anyway.
10794          */
10795         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10796                 return true;
10797
10798         /*
10799          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10800          * used the same base address. In that case the mmio flip might
10801          * have completed, but the CS hasn't even executed the flip yet.
10802          *
10803          * A flip count check isn't enough as the CS might have updated
10804          * the base address just after start of vblank, but before we
10805          * managed to process the interrupt. This means we'd complete the
10806          * CS flip too soon.
10807          *
10808          * Combining both checks should get us a good enough result. It may
10809          * still happen that the CS flip has been executed, but has not
10810          * yet actually completed. But in case the base address is the same
10811          * anyway, we don't really care.
10812          */
10813         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10814                 crtc->unpin_work->gtt_offset &&
10815                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10816                                     crtc->unpin_work->flip_count);
10817 }
10818
10819 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10820 {
10821         struct drm_i915_private *dev_priv = dev->dev_private;
10822         struct intel_crtc *intel_crtc =
10823                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10824         unsigned long flags;
10825
10826
10827         /*
10828          * This is called both by irq handlers and the reset code (to complete
10829          * lost pageflips) so needs the full irqsave spinlocks.
10830          *
10831          * NB: An MMIO update of the plane base pointer will also
10832          * generate a page-flip completion irq, i.e. every modeset
10833          * is also accompanied by a spurious intel_prepare_page_flip().
10834          */
10835         spin_lock_irqsave(&dev->event_lock, flags);
10836         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10837                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10838         spin_unlock_irqrestore(&dev->event_lock, flags);
10839 }
10840
10841 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10842 {
10843         /* Ensure that the work item is consistent when activating it ... */
10844         smp_wmb();
10845         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10846         /* and that it is marked active as soon as the irq could fire. */
10847         smp_wmb();
10848 }
10849
10850 static int intel_gen2_queue_flip(struct drm_device *dev,
10851                                  struct drm_crtc *crtc,
10852                                  struct drm_framebuffer *fb,
10853                                  struct drm_i915_gem_object *obj,
10854                                  struct drm_i915_gem_request *req,
10855                                  uint32_t flags)
10856 {
10857         struct intel_engine_cs *ring = req->ring;
10858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10859         u32 flip_mask;
10860         int ret;
10861
10862         ret = intel_ring_begin(req, 6);
10863         if (ret)
10864                 return ret;
10865
10866         /* Can't queue multiple flips, so wait for the previous
10867          * one to finish before executing the next.
10868          */
10869         if (intel_crtc->plane)
10870                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10871         else
10872                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10873         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10874         intel_ring_emit(ring, MI_NOOP);
10875         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10876                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10877         intel_ring_emit(ring, fb->pitches[0]);
10878         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10879         intel_ring_emit(ring, 0); /* aux display base address, unused */
10880
10881         intel_mark_page_flip_active(intel_crtc->unpin_work);
10882         return 0;
10883 }
10884
10885 static int intel_gen3_queue_flip(struct drm_device *dev,
10886                                  struct drm_crtc *crtc,
10887                                  struct drm_framebuffer *fb,
10888                                  struct drm_i915_gem_object *obj,
10889                                  struct drm_i915_gem_request *req,
10890                                  uint32_t flags)
10891 {
10892         struct intel_engine_cs *ring = req->ring;
10893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10894         u32 flip_mask;
10895         int ret;
10896
10897         ret = intel_ring_begin(req, 6);
10898         if (ret)
10899                 return ret;
10900
10901         if (intel_crtc->plane)
10902                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10903         else
10904                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10905         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10906         intel_ring_emit(ring, MI_NOOP);
10907         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10908                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10909         intel_ring_emit(ring, fb->pitches[0]);
10910         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10911         intel_ring_emit(ring, MI_NOOP);
10912
10913         intel_mark_page_flip_active(intel_crtc->unpin_work);
10914         return 0;
10915 }
10916
10917 static int intel_gen4_queue_flip(struct drm_device *dev,
10918                                  struct drm_crtc *crtc,
10919                                  struct drm_framebuffer *fb,
10920                                  struct drm_i915_gem_object *obj,
10921                                  struct drm_i915_gem_request *req,
10922                                  uint32_t flags)
10923 {
10924         struct intel_engine_cs *ring = req->ring;
10925         struct drm_i915_private *dev_priv = dev->dev_private;
10926         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10927         uint32_t pf, pipesrc;
10928         int ret;
10929
10930         ret = intel_ring_begin(req, 4);
10931         if (ret)
10932                 return ret;
10933
10934         /* i965+ uses the linear or tiled offsets from the
10935          * Display Registers (which do not change across a page-flip)
10936          * so we need only reprogram the base address.
10937          */
10938         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10939                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10940         intel_ring_emit(ring, fb->pitches[0]);
10941         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10942                         obj->tiling_mode);
10943
10944         /* XXX Enabling the panel-fitter across page-flip is so far
10945          * untested on non-native modes, so ignore it for now.
10946          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10947          */
10948         pf = 0;
10949         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10950         intel_ring_emit(ring, pf | pipesrc);
10951
10952         intel_mark_page_flip_active(intel_crtc->unpin_work);
10953         return 0;
10954 }
10955
10956 static int intel_gen6_queue_flip(struct drm_device *dev,
10957                                  struct drm_crtc *crtc,
10958                                  struct drm_framebuffer *fb,
10959                                  struct drm_i915_gem_object *obj,
10960                                  struct drm_i915_gem_request *req,
10961                                  uint32_t flags)
10962 {
10963         struct intel_engine_cs *ring = req->ring;
10964         struct drm_i915_private *dev_priv = dev->dev_private;
10965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10966         uint32_t pf, pipesrc;
10967         int ret;
10968
10969         ret = intel_ring_begin(req, 4);
10970         if (ret)
10971                 return ret;
10972
10973         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10974                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10975         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10976         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10977
10978         /* Contrary to the suggestions in the documentation,
10979          * "Enable Panel Fitter" does not seem to be required when page
10980          * flipping with a non-native mode, and worse causes a normal
10981          * modeset to fail.
10982          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10983          */
10984         pf = 0;
10985         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10986         intel_ring_emit(ring, pf | pipesrc);
10987
10988         intel_mark_page_flip_active(intel_crtc->unpin_work);
10989         return 0;
10990 }
10991
10992 static int intel_gen7_queue_flip(struct drm_device *dev,
10993                                  struct drm_crtc *crtc,
10994                                  struct drm_framebuffer *fb,
10995                                  struct drm_i915_gem_object *obj,
10996                                  struct drm_i915_gem_request *req,
10997                                  uint32_t flags)
10998 {
10999         struct intel_engine_cs *ring = req->ring;
11000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11001         uint32_t plane_bit = 0;
11002         int len, ret;
11003
11004         switch (intel_crtc->plane) {
11005         case PLANE_A:
11006                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11007                 break;
11008         case PLANE_B:
11009                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11010                 break;
11011         case PLANE_C:
11012                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11013                 break;
11014         default:
11015                 WARN_ONCE(1, "unknown plane in flip command\n");
11016                 return -ENODEV;
11017         }
11018
11019         len = 4;
11020         if (ring->id == RCS) {
11021                 len += 6;
11022                 /*
11023                  * On Gen 8, SRM is now taking an extra dword to accommodate
11024                  * 48bits addresses, and we need a NOOP for the batch size to
11025                  * stay even.
11026                  */
11027                 if (IS_GEN8(dev))
11028                         len += 2;
11029         }
11030
11031         /*
11032          * BSpec MI_DISPLAY_FLIP for IVB:
11033          * "The full packet must be contained within the same cache line."
11034          *
11035          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11036          * cacheline, if we ever start emitting more commands before
11037          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11038          * then do the cacheline alignment, and finally emit the
11039          * MI_DISPLAY_FLIP.
11040          */
11041         ret = intel_ring_cacheline_align(req);
11042         if (ret)
11043                 return ret;
11044
11045         ret = intel_ring_begin(req, len);
11046         if (ret)
11047                 return ret;
11048
11049         /* Unmask the flip-done completion message. Note that the bspec says that
11050          * we should do this for both the BCS and RCS, and that we must not unmask
11051          * more than one flip event at any time (or ensure that one flip message
11052          * can be sent by waiting for flip-done prior to queueing new flips).
11053          * Experimentation says that BCS works despite DERRMR masking all
11054          * flip-done completion events and that unmasking all planes at once
11055          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11056          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11057          */
11058         if (ring->id == RCS) {
11059                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11060                 intel_ring_emit(ring, DERRMR);
11061                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11062                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11063                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11064                 if (IS_GEN8(dev))
11065                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11066                                               MI_SRM_LRM_GLOBAL_GTT);
11067                 else
11068                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11069                                               MI_SRM_LRM_GLOBAL_GTT);
11070                 intel_ring_emit(ring, DERRMR);
11071                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11072                 if (IS_GEN8(dev)) {
11073                         intel_ring_emit(ring, 0);
11074                         intel_ring_emit(ring, MI_NOOP);
11075                 }
11076         }
11077
11078         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11079         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11080         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11081         intel_ring_emit(ring, (MI_NOOP));
11082
11083         intel_mark_page_flip_active(intel_crtc->unpin_work);
11084         return 0;
11085 }
11086
11087 static bool use_mmio_flip(struct intel_engine_cs *ring,
11088                           struct drm_i915_gem_object *obj)
11089 {
11090         /*
11091          * This is not being used for older platforms, because
11092          * non-availability of flip done interrupt forces us to use
11093          * CS flips. Older platforms derive flip done using some clever
11094          * tricks involving the flip_pending status bits and vblank irqs.
11095          * So using MMIO flips there would disrupt this mechanism.
11096          */
11097
11098         if (ring == NULL)
11099                 return true;
11100
11101         if (INTEL_INFO(ring->dev)->gen < 5)
11102                 return false;
11103
11104         if (i915.use_mmio_flip < 0)
11105                 return false;
11106         else if (i915.use_mmio_flip > 0)
11107                 return true;
11108         else if (i915.enable_execlists)
11109                 return true;
11110         else
11111                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11112 }
11113
11114 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11115                              struct intel_unpin_work *work)
11116 {
11117         struct drm_device *dev = intel_crtc->base.dev;
11118         struct drm_i915_private *dev_priv = dev->dev_private;
11119         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11120         const enum pipe pipe = intel_crtc->pipe;
11121         u32 ctl, stride;
11122
11123         ctl = I915_READ(PLANE_CTL(pipe, 0));
11124         ctl &= ~PLANE_CTL_TILED_MASK;
11125         switch (fb->modifier[0]) {
11126         case DRM_FORMAT_MOD_NONE:
11127                 break;
11128         case I915_FORMAT_MOD_X_TILED:
11129                 ctl |= PLANE_CTL_TILED_X;
11130                 break;
11131         case I915_FORMAT_MOD_Y_TILED:
11132                 ctl |= PLANE_CTL_TILED_Y;
11133                 break;
11134         case I915_FORMAT_MOD_Yf_TILED:
11135                 ctl |= PLANE_CTL_TILED_YF;
11136                 break;
11137         default:
11138                 MISSING_CASE(fb->modifier[0]);
11139         }
11140
11141         /*
11142          * The stride is either expressed as a multiple of 64 bytes chunks for
11143          * linear buffers or in number of tiles for tiled buffers.
11144          */
11145         stride = fb->pitches[0] /
11146                  intel_fb_stride_alignment(dev, fb->modifier[0],
11147                                            fb->pixel_format);
11148
11149         /*
11150          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11151          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11152          */
11153         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11154         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11155
11156         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11157         POSTING_READ(PLANE_SURF(pipe, 0));
11158 }
11159
11160 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11161                              struct intel_unpin_work *work)
11162 {
11163         struct drm_device *dev = intel_crtc->base.dev;
11164         struct drm_i915_private *dev_priv = dev->dev_private;
11165         struct intel_framebuffer *intel_fb =
11166                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11167         struct drm_i915_gem_object *obj = intel_fb->obj;
11168         u32 dspcntr;
11169         u32 reg;
11170
11171         reg = DSPCNTR(intel_crtc->plane);
11172         dspcntr = I915_READ(reg);
11173
11174         if (obj->tiling_mode != I915_TILING_NONE)
11175                 dspcntr |= DISPPLANE_TILED;
11176         else
11177                 dspcntr &= ~DISPPLANE_TILED;
11178
11179         I915_WRITE(reg, dspcntr);
11180
11181         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11182         POSTING_READ(DSPSURF(intel_crtc->plane));
11183 }
11184
11185 /*
11186  * XXX: This is the temporary way to update the plane registers until we get
11187  * around to using the usual plane update functions for MMIO flips
11188  */
11189 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11190 {
11191         struct intel_crtc *crtc = mmio_flip->crtc;
11192         struct intel_unpin_work *work;
11193
11194         spin_lock_irq(&crtc->base.dev->event_lock);
11195         work = crtc->unpin_work;
11196         spin_unlock_irq(&crtc->base.dev->event_lock);
11197         if (work == NULL)
11198                 return;
11199
11200         intel_mark_page_flip_active(work);
11201
11202         intel_pipe_update_start(crtc);
11203
11204         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11205                 skl_do_mmio_flip(crtc, work);
11206         else
11207                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11208                 ilk_do_mmio_flip(crtc, work);
11209
11210         intel_pipe_update_end(crtc);
11211 }
11212
11213 static void intel_mmio_flip_work_func(struct work_struct *work)
11214 {
11215         struct intel_mmio_flip *mmio_flip =
11216                 container_of(work, struct intel_mmio_flip, work);
11217
11218         if (mmio_flip->req) {
11219                 WARN_ON(__i915_wait_request(mmio_flip->req,
11220                                             mmio_flip->crtc->reset_counter,
11221                                             false, NULL,
11222                                             &mmio_flip->i915->rps.mmioflips));
11223                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11224         }
11225
11226         intel_do_mmio_flip(mmio_flip);
11227         kfree(mmio_flip);
11228 }
11229
11230 static int intel_queue_mmio_flip(struct drm_device *dev,
11231                                  struct drm_crtc *crtc,
11232                                  struct drm_framebuffer *fb,
11233                                  struct drm_i915_gem_object *obj,
11234                                  struct intel_engine_cs *ring,
11235                                  uint32_t flags)
11236 {
11237         struct intel_mmio_flip *mmio_flip;
11238
11239         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11240         if (mmio_flip == NULL)
11241                 return -ENOMEM;
11242
11243         mmio_flip->i915 = to_i915(dev);
11244         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11245         mmio_flip->crtc = to_intel_crtc(crtc);
11246
11247         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11248         schedule_work(&mmio_flip->work);
11249
11250         return 0;
11251 }
11252
11253 static int intel_default_queue_flip(struct drm_device *dev,
11254                                     struct drm_crtc *crtc,
11255                                     struct drm_framebuffer *fb,
11256                                     struct drm_i915_gem_object *obj,
11257                                     struct drm_i915_gem_request *req,
11258                                     uint32_t flags)
11259 {
11260         return -ENODEV;
11261 }
11262
11263 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11264                                          struct drm_crtc *crtc)
11265 {
11266         struct drm_i915_private *dev_priv = dev->dev_private;
11267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11268         struct intel_unpin_work *work = intel_crtc->unpin_work;
11269         u32 addr;
11270
11271         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11272                 return true;
11273
11274         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11275                 return false;
11276
11277         if (!work->enable_stall_check)
11278                 return false;
11279
11280         if (work->flip_ready_vblank == 0) {
11281                 if (work->flip_queued_req &&
11282                     !i915_gem_request_completed(work->flip_queued_req, true))
11283                         return false;
11284
11285                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11286         }
11287
11288         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11289                 return false;
11290
11291         /* Potential stall - if we see that the flip has happened,
11292          * assume a missed interrupt. */
11293         if (INTEL_INFO(dev)->gen >= 4)
11294                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11295         else
11296                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11297
11298         /* There is a potential issue here with a false positive after a flip
11299          * to the same address. We could address this by checking for a
11300          * non-incrementing frame counter.
11301          */
11302         return addr == work->gtt_offset;
11303 }
11304
11305 void intel_check_page_flip(struct drm_device *dev, int pipe)
11306 {
11307         struct drm_i915_private *dev_priv = dev->dev_private;
11308         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11310         struct intel_unpin_work *work;
11311
11312         WARN_ON(!in_interrupt());
11313
11314         if (crtc == NULL)
11315                 return;
11316
11317         spin_lock(&dev->event_lock);
11318         work = intel_crtc->unpin_work;
11319         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11320                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11321                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11322                 page_flip_completed(intel_crtc);
11323                 work = NULL;
11324         }
11325         if (work != NULL &&
11326             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11327                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11328         spin_unlock(&dev->event_lock);
11329 }
11330
11331 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11332                                 struct drm_framebuffer *fb,
11333                                 struct drm_pending_vblank_event *event,
11334                                 uint32_t page_flip_flags)
11335 {
11336         struct drm_device *dev = crtc->dev;
11337         struct drm_i915_private *dev_priv = dev->dev_private;
11338         struct drm_framebuffer *old_fb = crtc->primary->fb;
11339         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11341         struct drm_plane *primary = crtc->primary;
11342         enum pipe pipe = intel_crtc->pipe;
11343         struct intel_unpin_work *work;
11344         struct intel_engine_cs *ring;
11345         bool mmio_flip;
11346         struct drm_i915_gem_request *request = NULL;
11347         int ret;
11348
11349         /*
11350          * drm_mode_page_flip_ioctl() should already catch this, but double
11351          * check to be safe.  In the future we may enable pageflipping from
11352          * a disabled primary plane.
11353          */
11354         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11355                 return -EBUSY;
11356
11357         /* Can't change pixel format via MI display flips. */
11358         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11359                 return -EINVAL;
11360
11361         /*
11362          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11363          * Note that pitch changes could also affect these register.
11364          */
11365         if (INTEL_INFO(dev)->gen > 3 &&
11366             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11367              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11368                 return -EINVAL;
11369
11370         if (i915_terminally_wedged(&dev_priv->gpu_error))
11371                 goto out_hang;
11372
11373         work = kzalloc(sizeof(*work), GFP_KERNEL);
11374         if (work == NULL)
11375                 return -ENOMEM;
11376
11377         work->event = event;
11378         work->crtc = crtc;
11379         work->old_fb = old_fb;
11380         INIT_WORK(&work->work, intel_unpin_work_fn);
11381
11382         ret = drm_crtc_vblank_get(crtc);
11383         if (ret)
11384                 goto free_work;
11385
11386         /* We borrow the event spin lock for protecting unpin_work */
11387         spin_lock_irq(&dev->event_lock);
11388         if (intel_crtc->unpin_work) {
11389                 /* Before declaring the flip queue wedged, check if
11390                  * the hardware completed the operation behind our backs.
11391                  */
11392                 if (__intel_pageflip_stall_check(dev, crtc)) {
11393                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11394                         page_flip_completed(intel_crtc);
11395                 } else {
11396                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11397                         spin_unlock_irq(&dev->event_lock);
11398
11399                         drm_crtc_vblank_put(crtc);
11400                         kfree(work);
11401                         return -EBUSY;
11402                 }
11403         }
11404         intel_crtc->unpin_work = work;
11405         spin_unlock_irq(&dev->event_lock);
11406
11407         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11408                 flush_workqueue(dev_priv->wq);
11409
11410         /* Reference the objects for the scheduled work. */
11411         drm_framebuffer_reference(work->old_fb);
11412         drm_gem_object_reference(&obj->base);
11413
11414         crtc->primary->fb = fb;
11415         update_state_fb(crtc->primary);
11416
11417         work->pending_flip_obj = obj;
11418
11419         ret = i915_mutex_lock_interruptible(dev);
11420         if (ret)
11421                 goto cleanup;
11422
11423         atomic_inc(&intel_crtc->unpin_work_count);
11424         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11425
11426         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11427                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11428
11429         if (IS_VALLEYVIEW(dev)) {
11430                 ring = &dev_priv->ring[BCS];
11431                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11432                         /* vlv: DISPLAY_FLIP fails to change tiling */
11433                         ring = NULL;
11434         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11435                 ring = &dev_priv->ring[BCS];
11436         } else if (INTEL_INFO(dev)->gen >= 7) {
11437                 ring = i915_gem_request_get_ring(obj->last_write_req);
11438                 if (ring == NULL || ring->id != RCS)
11439                         ring = &dev_priv->ring[BCS];
11440         } else {
11441                 ring = &dev_priv->ring[RCS];
11442         }
11443
11444         mmio_flip = use_mmio_flip(ring, obj);
11445
11446         /* When using CS flips, we want to emit semaphores between rings.
11447          * However, when using mmio flips we will create a task to do the
11448          * synchronisation, so all we want here is to pin the framebuffer
11449          * into the display plane and skip any waits.
11450          */
11451         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11452                                          crtc->primary->state,
11453                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11454         if (ret)
11455                 goto cleanup_pending;
11456
11457         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11458                                                   obj, 0);
11459         work->gtt_offset += intel_crtc->dspaddr_offset;
11460
11461         if (mmio_flip) {
11462                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11463                                             page_flip_flags);
11464                 if (ret)
11465                         goto cleanup_unpin;
11466
11467                 i915_gem_request_assign(&work->flip_queued_req,
11468                                         obj->last_write_req);
11469         } else {
11470                 if (!request) {
11471                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11472                         if (ret)
11473                                 goto cleanup_unpin;
11474                 }
11475
11476                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11477                                                    page_flip_flags);
11478                 if (ret)
11479                         goto cleanup_unpin;
11480
11481                 i915_gem_request_assign(&work->flip_queued_req, request);
11482         }
11483
11484         if (request)
11485                 i915_add_request_no_flush(request);
11486
11487         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11488         work->enable_stall_check = true;
11489
11490         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11491                           to_intel_plane(primary)->frontbuffer_bit);
11492         mutex_unlock(&dev->struct_mutex);
11493
11494         intel_fbc_disable_crtc(intel_crtc);
11495         intel_frontbuffer_flip_prepare(dev,
11496                                        to_intel_plane(primary)->frontbuffer_bit);
11497
11498         trace_i915_flip_request(intel_crtc->plane, obj);
11499
11500         return 0;
11501
11502 cleanup_unpin:
11503         intel_unpin_fb_obj(fb, crtc->primary->state);
11504 cleanup_pending:
11505         if (request)
11506                 i915_gem_request_cancel(request);
11507         atomic_dec(&intel_crtc->unpin_work_count);
11508         mutex_unlock(&dev->struct_mutex);
11509 cleanup:
11510         crtc->primary->fb = old_fb;
11511         update_state_fb(crtc->primary);
11512
11513         drm_gem_object_unreference_unlocked(&obj->base);
11514         drm_framebuffer_unreference(work->old_fb);
11515
11516         spin_lock_irq(&dev->event_lock);
11517         intel_crtc->unpin_work = NULL;
11518         spin_unlock_irq(&dev->event_lock);
11519
11520         drm_crtc_vblank_put(crtc);
11521 free_work:
11522         kfree(work);
11523
11524         if (ret == -EIO) {
11525                 struct drm_atomic_state *state;
11526                 struct drm_plane_state *plane_state;
11527
11528 out_hang:
11529                 state = drm_atomic_state_alloc(dev);
11530                 if (!state)
11531                         return -ENOMEM;
11532                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11533
11534 retry:
11535                 plane_state = drm_atomic_get_plane_state(state, primary);
11536                 ret = PTR_ERR_OR_ZERO(plane_state);
11537                 if (!ret) {
11538                         drm_atomic_set_fb_for_plane(plane_state, fb);
11539
11540                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11541                         if (!ret)
11542                                 ret = drm_atomic_commit(state);
11543                 }
11544
11545                 if (ret == -EDEADLK) {
11546                         drm_modeset_backoff(state->acquire_ctx);
11547                         drm_atomic_state_clear(state);
11548                         goto retry;
11549                 }
11550
11551                 if (ret)
11552                         drm_atomic_state_free(state);
11553
11554                 if (ret == 0 && event) {
11555                         spin_lock_irq(&dev->event_lock);
11556                         drm_send_vblank_event(dev, pipe, event);
11557                         spin_unlock_irq(&dev->event_lock);
11558                 }
11559         }
11560         return ret;
11561 }
11562
11563
11564 /**
11565  * intel_wm_need_update - Check whether watermarks need updating
11566  * @plane: drm plane
11567  * @state: new plane state
11568  *
11569  * Check current plane state versus the new one to determine whether
11570  * watermarks need to be recalculated.
11571  *
11572  * Returns true or false.
11573  */
11574 static bool intel_wm_need_update(struct drm_plane *plane,
11575                                  struct drm_plane_state *state)
11576 {
11577         /* Update watermarks on tiling changes. */
11578         if (!plane->state->fb || !state->fb ||
11579             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11580             plane->state->rotation != state->rotation)
11581                 return true;
11582
11583         if (plane->state->crtc_w != state->crtc_w)
11584                 return true;
11585
11586         return false;
11587 }
11588
11589 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11590                                     struct drm_plane_state *plane_state)
11591 {
11592         struct drm_crtc *crtc = crtc_state->crtc;
11593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11594         struct drm_plane *plane = plane_state->plane;
11595         struct drm_device *dev = crtc->dev;
11596         struct drm_i915_private *dev_priv = dev->dev_private;
11597         struct intel_plane_state *old_plane_state =
11598                 to_intel_plane_state(plane->state);
11599         int idx = intel_crtc->base.base.id, ret;
11600         int i = drm_plane_index(plane);
11601         bool mode_changed = needs_modeset(crtc_state);
11602         bool was_crtc_enabled = crtc->state->active;
11603         bool is_crtc_enabled = crtc_state->active;
11604
11605         bool turn_off, turn_on, visible, was_visible;
11606         struct drm_framebuffer *fb = plane_state->fb;
11607
11608         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11609             plane->type != DRM_PLANE_TYPE_CURSOR) {
11610                 ret = skl_update_scaler_plane(
11611                         to_intel_crtc_state(crtc_state),
11612                         to_intel_plane_state(plane_state));
11613                 if (ret)
11614                         return ret;
11615         }
11616
11617         /*
11618          * Disabling a plane is always okay; we just need to update
11619          * fb tracking in a special way since cleanup_fb() won't
11620          * get called by the plane helpers.
11621          */
11622         if (old_plane_state->base.fb && !fb)
11623                 intel_crtc->atomic.disabled_planes |= 1 << i;
11624
11625         was_visible = old_plane_state->visible;
11626         visible = to_intel_plane_state(plane_state)->visible;
11627
11628         if (!was_crtc_enabled && WARN_ON(was_visible))
11629                 was_visible = false;
11630
11631         if (!is_crtc_enabled && WARN_ON(visible))
11632                 visible = false;
11633
11634         if (!was_visible && !visible)
11635                 return 0;
11636
11637         turn_off = was_visible && (!visible || mode_changed);
11638         turn_on = visible && (!was_visible || mode_changed);
11639
11640         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11641                          plane->base.id, fb ? fb->base.id : -1);
11642
11643         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11644                          plane->base.id, was_visible, visible,
11645                          turn_off, turn_on, mode_changed);
11646
11647         if (turn_on) {
11648                 intel_crtc->atomic.update_wm_pre = true;
11649                 /* must disable cxsr around plane enable/disable */
11650                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11651                         intel_crtc->atomic.disable_cxsr = true;
11652                         /* to potentially re-enable cxsr */
11653                         intel_crtc->atomic.wait_vblank = true;
11654                         intel_crtc->atomic.update_wm_post = true;
11655                 }
11656         } else if (turn_off) {
11657                 intel_crtc->atomic.update_wm_post = true;
11658                 /* must disable cxsr around plane enable/disable */
11659                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11660                         if (is_crtc_enabled)
11661                                 intel_crtc->atomic.wait_vblank = true;
11662                         intel_crtc->atomic.disable_cxsr = true;
11663                 }
11664         } else if (intel_wm_need_update(plane, plane_state)) {
11665                 intel_crtc->atomic.update_wm_pre = true;
11666         }
11667
11668         if (visible || was_visible)
11669                 intel_crtc->atomic.fb_bits |=
11670                         to_intel_plane(plane)->frontbuffer_bit;
11671
11672         switch (plane->type) {
11673         case DRM_PLANE_TYPE_PRIMARY:
11674                 intel_crtc->atomic.wait_for_flips = true;
11675                 intel_crtc->atomic.pre_disable_primary = turn_off;
11676                 intel_crtc->atomic.post_enable_primary = turn_on;
11677
11678                 if (turn_off) {
11679                         /*
11680                          * FIXME: Actually if we will still have any other
11681                          * plane enabled on the pipe we could let IPS enabled
11682                          * still, but for now lets consider that when we make
11683                          * primary invisible by setting DSPCNTR to 0 on
11684                          * update_primary_plane function IPS needs to be
11685                          * disable.
11686                          */
11687                         intel_crtc->atomic.disable_ips = true;
11688
11689                         intel_crtc->atomic.disable_fbc = true;
11690                 }
11691
11692                 /*
11693                  * FBC does not work on some platforms for rotated
11694                  * planes, so disable it when rotation is not 0 and
11695                  * update it when rotation is set back to 0.
11696                  *
11697                  * FIXME: This is redundant with the fbc update done in
11698                  * the primary plane enable function except that that
11699                  * one is done too late. We eventually need to unify
11700                  * this.
11701                  */
11702
11703                 if (visible &&
11704                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11705                     dev_priv->fbc.crtc == intel_crtc &&
11706                     plane_state->rotation != BIT(DRM_ROTATE_0))
11707                         intel_crtc->atomic.disable_fbc = true;
11708
11709                 /*
11710                  * BDW signals flip done immediately if the plane
11711                  * is disabled, even if the plane enable is already
11712                  * armed to occur at the next vblank :(
11713                  */
11714                 if (turn_on && IS_BROADWELL(dev))
11715                         intel_crtc->atomic.wait_vblank = true;
11716
11717                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11718                 break;
11719         case DRM_PLANE_TYPE_CURSOR:
11720                 break;
11721         case DRM_PLANE_TYPE_OVERLAY:
11722                 if (turn_off && !mode_changed) {
11723                         intel_crtc->atomic.wait_vblank = true;
11724                         intel_crtc->atomic.update_sprite_watermarks |=
11725                                 1 << i;
11726                 }
11727         }
11728         return 0;
11729 }
11730
11731 static bool encoders_cloneable(const struct intel_encoder *a,
11732                                const struct intel_encoder *b)
11733 {
11734         /* masks could be asymmetric, so check both ways */
11735         return a == b || (a->cloneable & (1 << b->type) &&
11736                           b->cloneable & (1 << a->type));
11737 }
11738
11739 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11740                                          struct intel_crtc *crtc,
11741                                          struct intel_encoder *encoder)
11742 {
11743         struct intel_encoder *source_encoder;
11744         struct drm_connector *connector;
11745         struct drm_connector_state *connector_state;
11746         int i;
11747
11748         for_each_connector_in_state(state, connector, connector_state, i) {
11749                 if (connector_state->crtc != &crtc->base)
11750                         continue;
11751
11752                 source_encoder =
11753                         to_intel_encoder(connector_state->best_encoder);
11754                 if (!encoders_cloneable(encoder, source_encoder))
11755                         return false;
11756         }
11757
11758         return true;
11759 }
11760
11761 static bool check_encoder_cloning(struct drm_atomic_state *state,
11762                                   struct intel_crtc *crtc)
11763 {
11764         struct intel_encoder *encoder;
11765         struct drm_connector *connector;
11766         struct drm_connector_state *connector_state;
11767         int i;
11768
11769         for_each_connector_in_state(state, connector, connector_state, i) {
11770                 if (connector_state->crtc != &crtc->base)
11771                         continue;
11772
11773                 encoder = to_intel_encoder(connector_state->best_encoder);
11774                 if (!check_single_encoder_cloning(state, crtc, encoder))
11775                         return false;
11776         }
11777
11778         return true;
11779 }
11780
11781 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11782                                    struct drm_crtc_state *crtc_state)
11783 {
11784         struct drm_device *dev = crtc->dev;
11785         struct drm_i915_private *dev_priv = dev->dev_private;
11786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11787         struct intel_crtc_state *pipe_config =
11788                 to_intel_crtc_state(crtc_state);
11789         struct drm_atomic_state *state = crtc_state->state;
11790         int ret;
11791         bool mode_changed = needs_modeset(crtc_state);
11792
11793         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11794                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11795                 return -EINVAL;
11796         }
11797
11798         if (mode_changed && !crtc_state->active)
11799                 intel_crtc->atomic.update_wm_post = true;
11800
11801         if (mode_changed && crtc_state->enable &&
11802             dev_priv->display.crtc_compute_clock &&
11803             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11804                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11805                                                            pipe_config);
11806                 if (ret)
11807                         return ret;
11808         }
11809
11810         ret = 0;
11811         if (INTEL_INFO(dev)->gen >= 9) {
11812                 if (mode_changed)
11813                         ret = skl_update_scaler_crtc(pipe_config);
11814
11815                 if (!ret)
11816                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11817                                                          pipe_config);
11818         }
11819
11820         return ret;
11821 }
11822
11823 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11824         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11825         .load_lut = intel_crtc_load_lut,
11826         .atomic_begin = intel_begin_crtc_commit,
11827         .atomic_flush = intel_finish_crtc_commit,
11828         .atomic_check = intel_crtc_atomic_check,
11829 };
11830
11831 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11832 {
11833         struct intel_connector *connector;
11834
11835         for_each_intel_connector(dev, connector) {
11836                 if (connector->base.encoder) {
11837                         connector->base.state->best_encoder =
11838                                 connector->base.encoder;
11839                         connector->base.state->crtc =
11840                                 connector->base.encoder->crtc;
11841                 } else {
11842                         connector->base.state->best_encoder = NULL;
11843                         connector->base.state->crtc = NULL;
11844                 }
11845         }
11846 }
11847
11848 static void
11849 connected_sink_compute_bpp(struct intel_connector *connector,
11850                            struct intel_crtc_state *pipe_config)
11851 {
11852         int bpp = pipe_config->pipe_bpp;
11853
11854         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11855                 connector->base.base.id,
11856                 connector->base.name);
11857
11858         /* Don't use an invalid EDID bpc value */
11859         if (connector->base.display_info.bpc &&
11860             connector->base.display_info.bpc * 3 < bpp) {
11861                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11862                               bpp, connector->base.display_info.bpc*3);
11863                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11864         }
11865
11866         /* Clamp bpp to 8 on screens without EDID 1.4 */
11867         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11868                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11869                               bpp);
11870                 pipe_config->pipe_bpp = 24;
11871         }
11872 }
11873
11874 static int
11875 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11876                           struct intel_crtc_state *pipe_config)
11877 {
11878         struct drm_device *dev = crtc->base.dev;
11879         struct drm_atomic_state *state;
11880         struct drm_connector *connector;
11881         struct drm_connector_state *connector_state;
11882         int bpp, i;
11883
11884         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11885                 bpp = 10*3;
11886         else if (INTEL_INFO(dev)->gen >= 5)
11887                 bpp = 12*3;
11888         else
11889                 bpp = 8*3;
11890
11891
11892         pipe_config->pipe_bpp = bpp;
11893
11894         state = pipe_config->base.state;
11895
11896         /* Clamp display bpp to EDID value */
11897         for_each_connector_in_state(state, connector, connector_state, i) {
11898                 if (connector_state->crtc != &crtc->base)
11899                         continue;
11900
11901                 connected_sink_compute_bpp(to_intel_connector(connector),
11902                                            pipe_config);
11903         }
11904
11905         return bpp;
11906 }
11907
11908 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11909 {
11910         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11911                         "type: 0x%x flags: 0x%x\n",
11912                 mode->crtc_clock,
11913                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11914                 mode->crtc_hsync_end, mode->crtc_htotal,
11915                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11916                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11917 }
11918
11919 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11920                                    struct intel_crtc_state *pipe_config,
11921                                    const char *context)
11922 {
11923         struct drm_device *dev = crtc->base.dev;
11924         struct drm_plane *plane;
11925         struct intel_plane *intel_plane;
11926         struct intel_plane_state *state;
11927         struct drm_framebuffer *fb;
11928
11929         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11930                       context, pipe_config, pipe_name(crtc->pipe));
11931
11932         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11933         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11934                       pipe_config->pipe_bpp, pipe_config->dither);
11935         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11936                       pipe_config->has_pch_encoder,
11937                       pipe_config->fdi_lanes,
11938                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11939                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11940                       pipe_config->fdi_m_n.tu);
11941         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11942                       pipe_config->has_dp_encoder,
11943                       pipe_config->lane_count,
11944                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11945                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11946                       pipe_config->dp_m_n.tu);
11947
11948         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11949                       pipe_config->has_dp_encoder,
11950                       pipe_config->lane_count,
11951                       pipe_config->dp_m2_n2.gmch_m,
11952                       pipe_config->dp_m2_n2.gmch_n,
11953                       pipe_config->dp_m2_n2.link_m,
11954                       pipe_config->dp_m2_n2.link_n,
11955                       pipe_config->dp_m2_n2.tu);
11956
11957         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11958                       pipe_config->has_audio,
11959                       pipe_config->has_infoframe);
11960
11961         DRM_DEBUG_KMS("requested mode:\n");
11962         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11963         DRM_DEBUG_KMS("adjusted mode:\n");
11964         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11965         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11966         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11967         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11968                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11969         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11970                       crtc->num_scalers,
11971                       pipe_config->scaler_state.scaler_users,
11972                       pipe_config->scaler_state.scaler_id);
11973         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11974                       pipe_config->gmch_pfit.control,
11975                       pipe_config->gmch_pfit.pgm_ratios,
11976                       pipe_config->gmch_pfit.lvds_border_bits);
11977         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11978                       pipe_config->pch_pfit.pos,
11979                       pipe_config->pch_pfit.size,
11980                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11981         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11982         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11983
11984         if (IS_BROXTON(dev)) {
11985                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11986                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11987                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11988                               pipe_config->ddi_pll_sel,
11989                               pipe_config->dpll_hw_state.ebb0,
11990                               pipe_config->dpll_hw_state.ebb4,
11991                               pipe_config->dpll_hw_state.pll0,
11992                               pipe_config->dpll_hw_state.pll1,
11993                               pipe_config->dpll_hw_state.pll2,
11994                               pipe_config->dpll_hw_state.pll3,
11995                               pipe_config->dpll_hw_state.pll6,
11996                               pipe_config->dpll_hw_state.pll8,
11997                               pipe_config->dpll_hw_state.pll9,
11998                               pipe_config->dpll_hw_state.pll10,
11999                               pipe_config->dpll_hw_state.pcsdw12);
12000         } else if (IS_SKYLAKE(dev)) {
12001                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12002                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12003                               pipe_config->ddi_pll_sel,
12004                               pipe_config->dpll_hw_state.ctrl1,
12005                               pipe_config->dpll_hw_state.cfgcr1,
12006                               pipe_config->dpll_hw_state.cfgcr2);
12007         } else if (HAS_DDI(dev)) {
12008                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12009                               pipe_config->ddi_pll_sel,
12010                               pipe_config->dpll_hw_state.wrpll);
12011         } else {
12012                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12013                               "fp0: 0x%x, fp1: 0x%x\n",
12014                               pipe_config->dpll_hw_state.dpll,
12015                               pipe_config->dpll_hw_state.dpll_md,
12016                               pipe_config->dpll_hw_state.fp0,
12017                               pipe_config->dpll_hw_state.fp1);
12018         }
12019
12020         DRM_DEBUG_KMS("planes on this crtc\n");
12021         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12022                 intel_plane = to_intel_plane(plane);
12023                 if (intel_plane->pipe != crtc->pipe)
12024                         continue;
12025
12026                 state = to_intel_plane_state(plane->state);
12027                 fb = state->base.fb;
12028                 if (!fb) {
12029                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12030                                 "disabled, scaler_id = %d\n",
12031                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12032                                 plane->base.id, intel_plane->pipe,
12033                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12034                                 drm_plane_index(plane), state->scaler_id);
12035                         continue;
12036                 }
12037
12038                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12039                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12040                         plane->base.id, intel_plane->pipe,
12041                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12042                         drm_plane_index(plane));
12043                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12044                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12045                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12046                         state->scaler_id,
12047                         state->src.x1 >> 16, state->src.y1 >> 16,
12048                         drm_rect_width(&state->src) >> 16,
12049                         drm_rect_height(&state->src) >> 16,
12050                         state->dst.x1, state->dst.y1,
12051                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12052         }
12053 }
12054
12055 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12056 {
12057         struct drm_device *dev = state->dev;
12058         struct intel_encoder *encoder;
12059         struct drm_connector *connector;
12060         struct drm_connector_state *connector_state;
12061         unsigned int used_ports = 0;
12062         int i;
12063
12064         /*
12065          * Walk the connector list instead of the encoder
12066          * list to detect the problem on ddi platforms
12067          * where there's just one encoder per digital port.
12068          */
12069         for_each_connector_in_state(state, connector, connector_state, i) {
12070                 if (!connector_state->best_encoder)
12071                         continue;
12072
12073                 encoder = to_intel_encoder(connector_state->best_encoder);
12074
12075                 WARN_ON(!connector_state->crtc);
12076
12077                 switch (encoder->type) {
12078                         unsigned int port_mask;
12079                 case INTEL_OUTPUT_UNKNOWN:
12080                         if (WARN_ON(!HAS_DDI(dev)))
12081                                 break;
12082                 case INTEL_OUTPUT_DISPLAYPORT:
12083                 case INTEL_OUTPUT_HDMI:
12084                 case INTEL_OUTPUT_EDP:
12085                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12086
12087                         /* the same port mustn't appear more than once */
12088                         if (used_ports & port_mask)
12089                                 return false;
12090
12091                         used_ports |= port_mask;
12092                 default:
12093                         break;
12094                 }
12095         }
12096
12097         return true;
12098 }
12099
12100 static void
12101 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12102 {
12103         struct drm_crtc_state tmp_state;
12104         struct intel_crtc_scaler_state scaler_state;
12105         struct intel_dpll_hw_state dpll_hw_state;
12106         enum intel_dpll_id shared_dpll;
12107         uint32_t ddi_pll_sel;
12108         bool force_thru;
12109
12110         /* FIXME: before the switch to atomic started, a new pipe_config was
12111          * kzalloc'd. Code that depends on any field being zero should be
12112          * fixed, so that the crtc_state can be safely duplicated. For now,
12113          * only fields that are know to not cause problems are preserved. */
12114
12115         tmp_state = crtc_state->base;
12116         scaler_state = crtc_state->scaler_state;
12117         shared_dpll = crtc_state->shared_dpll;
12118         dpll_hw_state = crtc_state->dpll_hw_state;
12119         ddi_pll_sel = crtc_state->ddi_pll_sel;
12120         force_thru = crtc_state->pch_pfit.force_thru;
12121
12122         memset(crtc_state, 0, sizeof *crtc_state);
12123
12124         crtc_state->base = tmp_state;
12125         crtc_state->scaler_state = scaler_state;
12126         crtc_state->shared_dpll = shared_dpll;
12127         crtc_state->dpll_hw_state = dpll_hw_state;
12128         crtc_state->ddi_pll_sel = ddi_pll_sel;
12129         crtc_state->pch_pfit.force_thru = force_thru;
12130 }
12131
12132 static int
12133 intel_modeset_pipe_config(struct drm_crtc *crtc,
12134                           struct intel_crtc_state *pipe_config)
12135 {
12136         struct drm_atomic_state *state = pipe_config->base.state;
12137         struct intel_encoder *encoder;
12138         struct drm_connector *connector;
12139         struct drm_connector_state *connector_state;
12140         int base_bpp, ret = -EINVAL;
12141         int i;
12142         bool retry = true;
12143
12144         clear_intel_crtc_state(pipe_config);
12145
12146         pipe_config->cpu_transcoder =
12147                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12148
12149         /*
12150          * Sanitize sync polarity flags based on requested ones. If neither
12151          * positive or negative polarity is requested, treat this as meaning
12152          * negative polarity.
12153          */
12154         if (!(pipe_config->base.adjusted_mode.flags &
12155               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12156                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12157
12158         if (!(pipe_config->base.adjusted_mode.flags &
12159               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12160                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12161
12162         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12163                                              pipe_config);
12164         if (base_bpp < 0)
12165                 goto fail;
12166
12167         /*
12168          * Determine the real pipe dimensions. Note that stereo modes can
12169          * increase the actual pipe size due to the frame doubling and
12170          * insertion of additional space for blanks between the frame. This
12171          * is stored in the crtc timings. We use the requested mode to do this
12172          * computation to clearly distinguish it from the adjusted mode, which
12173          * can be changed by the connectors in the below retry loop.
12174          */
12175         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12176                                &pipe_config->pipe_src_w,
12177                                &pipe_config->pipe_src_h);
12178
12179 encoder_retry:
12180         /* Ensure the port clock defaults are reset when retrying. */
12181         pipe_config->port_clock = 0;
12182         pipe_config->pixel_multiplier = 1;
12183
12184         /* Fill in default crtc timings, allow encoders to overwrite them. */
12185         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12186                               CRTC_STEREO_DOUBLE);
12187
12188         /* Pass our mode to the connectors and the CRTC to give them a chance to
12189          * adjust it according to limitations or connector properties, and also
12190          * a chance to reject the mode entirely.
12191          */
12192         for_each_connector_in_state(state, connector, connector_state, i) {
12193                 if (connector_state->crtc != crtc)
12194                         continue;
12195
12196                 encoder = to_intel_encoder(connector_state->best_encoder);
12197
12198                 if (!(encoder->compute_config(encoder, pipe_config))) {
12199                         DRM_DEBUG_KMS("Encoder config failure\n");
12200                         goto fail;
12201                 }
12202         }
12203
12204         /* Set default port clock if not overwritten by the encoder. Needs to be
12205          * done afterwards in case the encoder adjusts the mode. */
12206         if (!pipe_config->port_clock)
12207                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12208                         * pipe_config->pixel_multiplier;
12209
12210         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12211         if (ret < 0) {
12212                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12213                 goto fail;
12214         }
12215
12216         if (ret == RETRY) {
12217                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12218                         ret = -EINVAL;
12219                         goto fail;
12220                 }
12221
12222                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12223                 retry = false;
12224                 goto encoder_retry;
12225         }
12226
12227         /* Dithering seems to not pass-through bits correctly when it should, so
12228          * only enable it on 6bpc panels. */
12229         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12230         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12231                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12232
12233 fail:
12234         return ret;
12235 }
12236
12237 static void
12238 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12239 {
12240         struct drm_crtc *crtc;
12241         struct drm_crtc_state *crtc_state;
12242         int i;
12243
12244         /* Double check state. */
12245         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12246                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12247
12248                 /* Update hwmode for vblank functions */
12249                 if (crtc->state->active)
12250                         crtc->hwmode = crtc->state->adjusted_mode;
12251                 else
12252                         crtc->hwmode.crtc_clock = 0;
12253         }
12254 }
12255
12256 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12257 {
12258         int diff;
12259
12260         if (clock1 == clock2)
12261                 return true;
12262
12263         if (!clock1 || !clock2)
12264                 return false;
12265
12266         diff = abs(clock1 - clock2);
12267
12268         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12269                 return true;
12270
12271         return false;
12272 }
12273
12274 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12275         list_for_each_entry((intel_crtc), \
12276                             &(dev)->mode_config.crtc_list, \
12277                             base.head) \
12278                 if (mask & (1 <<(intel_crtc)->pipe))
12279
12280 static bool
12281 intel_compare_m_n(unsigned int m, unsigned int n,
12282                   unsigned int m2, unsigned int n2,
12283                   bool exact)
12284 {
12285         if (m == m2 && n == n2)
12286                 return true;
12287
12288         if (exact || !m || !n || !m2 || !n2)
12289                 return false;
12290
12291         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12292
12293         if (m > m2) {
12294                 while (m > m2) {
12295                         m2 <<= 1;
12296                         n2 <<= 1;
12297                 }
12298         } else if (m < m2) {
12299                 while (m < m2) {
12300                         m <<= 1;
12301                         n <<= 1;
12302                 }
12303         }
12304
12305         return m == m2 && n == n2;
12306 }
12307
12308 static bool
12309 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12310                        struct intel_link_m_n *m2_n2,
12311                        bool adjust)
12312 {
12313         if (m_n->tu == m2_n2->tu &&
12314             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12315                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12316             intel_compare_m_n(m_n->link_m, m_n->link_n,
12317                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12318                 if (adjust)
12319                         *m2_n2 = *m_n;
12320
12321                 return true;
12322         }
12323
12324         return false;
12325 }
12326
12327 static bool
12328 intel_pipe_config_compare(struct drm_device *dev,
12329                           struct intel_crtc_state *current_config,
12330                           struct intel_crtc_state *pipe_config,
12331                           bool adjust)
12332 {
12333         bool ret = true;
12334
12335 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12336         do { \
12337                 if (!adjust) \
12338                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12339                 else \
12340                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12341         } while (0)
12342
12343 #define PIPE_CONF_CHECK_X(name) \
12344         if (current_config->name != pipe_config->name) { \
12345                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12346                           "(expected 0x%08x, found 0x%08x)\n", \
12347                           current_config->name, \
12348                           pipe_config->name); \
12349                 ret = false; \
12350         }
12351
12352 #define PIPE_CONF_CHECK_I(name) \
12353         if (current_config->name != pipe_config->name) { \
12354                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12355                           "(expected %i, found %i)\n", \
12356                           current_config->name, \
12357                           pipe_config->name); \
12358                 ret = false; \
12359         }
12360
12361 #define PIPE_CONF_CHECK_M_N(name) \
12362         if (!intel_compare_link_m_n(&current_config->name, \
12363                                     &pipe_config->name,\
12364                                     adjust)) { \
12365                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12366                           "(expected tu %i gmch %i/%i link %i/%i, " \
12367                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12368                           current_config->name.tu, \
12369                           current_config->name.gmch_m, \
12370                           current_config->name.gmch_n, \
12371                           current_config->name.link_m, \
12372                           current_config->name.link_n, \
12373                           pipe_config->name.tu, \
12374                           pipe_config->name.gmch_m, \
12375                           pipe_config->name.gmch_n, \
12376                           pipe_config->name.link_m, \
12377                           pipe_config->name.link_n); \
12378                 ret = false; \
12379         }
12380
12381 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12382         if (!intel_compare_link_m_n(&current_config->name, \
12383                                     &pipe_config->name, adjust) && \
12384             !intel_compare_link_m_n(&current_config->alt_name, \
12385                                     &pipe_config->name, adjust)) { \
12386                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12387                           "(expected tu %i gmch %i/%i link %i/%i, " \
12388                           "or tu %i gmch %i/%i link %i/%i, " \
12389                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12390                           current_config->name.tu, \
12391                           current_config->name.gmch_m, \
12392                           current_config->name.gmch_n, \
12393                           current_config->name.link_m, \
12394                           current_config->name.link_n, \
12395                           current_config->alt_name.tu, \
12396                           current_config->alt_name.gmch_m, \
12397                           current_config->alt_name.gmch_n, \
12398                           current_config->alt_name.link_m, \
12399                           current_config->alt_name.link_n, \
12400                           pipe_config->name.tu, \
12401                           pipe_config->name.gmch_m, \
12402                           pipe_config->name.gmch_n, \
12403                           pipe_config->name.link_m, \
12404                           pipe_config->name.link_n); \
12405                 ret = false; \
12406         }
12407
12408 /* This is required for BDW+ where there is only one set of registers for
12409  * switching between high and low RR.
12410  * This macro can be used whenever a comparison has to be made between one
12411  * hw state and multiple sw state variables.
12412  */
12413 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12414         if ((current_config->name != pipe_config->name) && \
12415                 (current_config->alt_name != pipe_config->name)) { \
12416                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12417                                   "(expected %i or %i, found %i)\n", \
12418                                   current_config->name, \
12419                                   current_config->alt_name, \
12420                                   pipe_config->name); \
12421                         ret = false; \
12422         }
12423
12424 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12425         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12426                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12427                           "(expected %i, found %i)\n", \
12428                           current_config->name & (mask), \
12429                           pipe_config->name & (mask)); \
12430                 ret = false; \
12431         }
12432
12433 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12434         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12435                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12436                           "(expected %i, found %i)\n", \
12437                           current_config->name, \
12438                           pipe_config->name); \
12439                 ret = false; \
12440         }
12441
12442 #define PIPE_CONF_QUIRK(quirk)  \
12443         ((current_config->quirks | pipe_config->quirks) & (quirk))
12444
12445         PIPE_CONF_CHECK_I(cpu_transcoder);
12446
12447         PIPE_CONF_CHECK_I(has_pch_encoder);
12448         PIPE_CONF_CHECK_I(fdi_lanes);
12449         PIPE_CONF_CHECK_M_N(fdi_m_n);
12450
12451         PIPE_CONF_CHECK_I(has_dp_encoder);
12452         PIPE_CONF_CHECK_I(lane_count);
12453
12454         if (INTEL_INFO(dev)->gen < 8) {
12455                 PIPE_CONF_CHECK_M_N(dp_m_n);
12456
12457                 PIPE_CONF_CHECK_I(has_drrs);
12458                 if (current_config->has_drrs)
12459                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12460         } else
12461                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12462
12463         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12464         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12465         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12466         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12467         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12468         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12469
12470         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12471         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12472         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12473         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12474         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12475         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12476
12477         PIPE_CONF_CHECK_I(pixel_multiplier);
12478         PIPE_CONF_CHECK_I(has_hdmi_sink);
12479         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12480             IS_VALLEYVIEW(dev))
12481                 PIPE_CONF_CHECK_I(limited_color_range);
12482         PIPE_CONF_CHECK_I(has_infoframe);
12483
12484         PIPE_CONF_CHECK_I(has_audio);
12485
12486         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12487                               DRM_MODE_FLAG_INTERLACE);
12488
12489         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12490                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12491                                       DRM_MODE_FLAG_PHSYNC);
12492                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12493                                       DRM_MODE_FLAG_NHSYNC);
12494                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12495                                       DRM_MODE_FLAG_PVSYNC);
12496                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12497                                       DRM_MODE_FLAG_NVSYNC);
12498         }
12499
12500         PIPE_CONF_CHECK_X(gmch_pfit.control);
12501         /* pfit ratios are autocomputed by the hw on gen4+ */
12502         if (INTEL_INFO(dev)->gen < 4)
12503                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12504         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12505
12506         if (!adjust) {
12507                 PIPE_CONF_CHECK_I(pipe_src_w);
12508                 PIPE_CONF_CHECK_I(pipe_src_h);
12509
12510                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12511                 if (current_config->pch_pfit.enabled) {
12512                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12513                         PIPE_CONF_CHECK_X(pch_pfit.size);
12514                 }
12515
12516                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12517         }
12518
12519         /* BDW+ don't expose a synchronous way to read the state */
12520         if (IS_HASWELL(dev))
12521                 PIPE_CONF_CHECK_I(ips_enabled);
12522
12523         PIPE_CONF_CHECK_I(double_wide);
12524
12525         PIPE_CONF_CHECK_X(ddi_pll_sel);
12526
12527         PIPE_CONF_CHECK_I(shared_dpll);
12528         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12529         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12530         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12531         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12532         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12533         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12534         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12535         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12536
12537         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12538                 PIPE_CONF_CHECK_I(pipe_bpp);
12539
12540         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12541         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12542
12543 #undef PIPE_CONF_CHECK_X
12544 #undef PIPE_CONF_CHECK_I
12545 #undef PIPE_CONF_CHECK_I_ALT
12546 #undef PIPE_CONF_CHECK_FLAGS
12547 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12548 #undef PIPE_CONF_QUIRK
12549 #undef INTEL_ERR_OR_DBG_KMS
12550
12551         return ret;
12552 }
12553
12554 static void check_wm_state(struct drm_device *dev)
12555 {
12556         struct drm_i915_private *dev_priv = dev->dev_private;
12557         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12558         struct intel_crtc *intel_crtc;
12559         int plane;
12560
12561         if (INTEL_INFO(dev)->gen < 9)
12562                 return;
12563
12564         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12565         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12566
12567         for_each_intel_crtc(dev, intel_crtc) {
12568                 struct skl_ddb_entry *hw_entry, *sw_entry;
12569                 const enum pipe pipe = intel_crtc->pipe;
12570
12571                 if (!intel_crtc->active)
12572                         continue;
12573
12574                 /* planes */
12575                 for_each_plane(dev_priv, pipe, plane) {
12576                         hw_entry = &hw_ddb.plane[pipe][plane];
12577                         sw_entry = &sw_ddb->plane[pipe][plane];
12578
12579                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12580                                 continue;
12581
12582                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12583                                   "(expected (%u,%u), found (%u,%u))\n",
12584                                   pipe_name(pipe), plane + 1,
12585                                   sw_entry->start, sw_entry->end,
12586                                   hw_entry->start, hw_entry->end);
12587                 }
12588
12589                 /* cursor */
12590                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12591                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12592
12593                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12594                         continue;
12595
12596                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12597                           "(expected (%u,%u), found (%u,%u))\n",
12598                           pipe_name(pipe),
12599                           sw_entry->start, sw_entry->end,
12600                           hw_entry->start, hw_entry->end);
12601         }
12602 }
12603
12604 static void
12605 check_connector_state(struct drm_device *dev,
12606                       struct drm_atomic_state *old_state)
12607 {
12608         struct drm_connector_state *old_conn_state;
12609         struct drm_connector *connector;
12610         int i;
12611
12612         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12613                 struct drm_encoder *encoder = connector->encoder;
12614                 struct drm_connector_state *state = connector->state;
12615
12616                 /* This also checks the encoder/connector hw state with the
12617                  * ->get_hw_state callbacks. */
12618                 intel_connector_check_state(to_intel_connector(connector));
12619
12620                 I915_STATE_WARN(state->best_encoder != encoder,
12621                      "connector's atomic encoder doesn't match legacy encoder\n");
12622         }
12623 }
12624
12625 static void
12626 check_encoder_state(struct drm_device *dev)
12627 {
12628         struct intel_encoder *encoder;
12629         struct intel_connector *connector;
12630
12631         for_each_intel_encoder(dev, encoder) {
12632                 bool enabled = false;
12633                 enum pipe pipe;
12634
12635                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12636                               encoder->base.base.id,
12637                               encoder->base.name);
12638
12639                 for_each_intel_connector(dev, connector) {
12640                         if (connector->base.state->best_encoder != &encoder->base)
12641                                 continue;
12642                         enabled = true;
12643
12644                         I915_STATE_WARN(connector->base.state->crtc !=
12645                                         encoder->base.crtc,
12646                              "connector's crtc doesn't match encoder crtc\n");
12647                 }
12648
12649                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12650                      "encoder's enabled state mismatch "
12651                      "(expected %i, found %i)\n",
12652                      !!encoder->base.crtc, enabled);
12653
12654                 if (!encoder->base.crtc) {
12655                         bool active;
12656
12657                         active = encoder->get_hw_state(encoder, &pipe);
12658                         I915_STATE_WARN(active,
12659                              "encoder detached but still enabled on pipe %c.\n",
12660                              pipe_name(pipe));
12661                 }
12662         }
12663 }
12664
12665 static void
12666 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12667 {
12668         struct drm_i915_private *dev_priv = dev->dev_private;
12669         struct intel_encoder *encoder;
12670         struct drm_crtc_state *old_crtc_state;
12671         struct drm_crtc *crtc;
12672         int i;
12673
12674         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12675                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12676                 struct intel_crtc_state *pipe_config, *sw_config;
12677                 bool active;
12678
12679                 if (!needs_modeset(crtc->state) &&
12680                     !to_intel_crtc_state(crtc->state)->update_pipe)
12681                         continue;
12682
12683                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12684                 pipe_config = to_intel_crtc_state(old_crtc_state);
12685                 memset(pipe_config, 0, sizeof(*pipe_config));
12686                 pipe_config->base.crtc = crtc;
12687                 pipe_config->base.state = old_state;
12688
12689                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12690                               crtc->base.id);
12691
12692                 active = dev_priv->display.get_pipe_config(intel_crtc,
12693                                                            pipe_config);
12694
12695                 /* hw state is inconsistent with the pipe quirk */
12696                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12697                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12698                         active = crtc->state->active;
12699
12700                 I915_STATE_WARN(crtc->state->active != active,
12701                      "crtc active state doesn't match with hw state "
12702                      "(expected %i, found %i)\n", crtc->state->active, active);
12703
12704                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12705                      "transitional active state does not match atomic hw state "
12706                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12707
12708                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12709                         enum pipe pipe;
12710
12711                         active = encoder->get_hw_state(encoder, &pipe);
12712                         I915_STATE_WARN(active != crtc->state->active,
12713                                 "[ENCODER:%i] active %i with crtc active %i\n",
12714                                 encoder->base.base.id, active, crtc->state->active);
12715
12716                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12717                                         "Encoder connected to wrong pipe %c\n",
12718                                         pipe_name(pipe));
12719
12720                         if (active)
12721                                 encoder->get_config(encoder, pipe_config);
12722                 }
12723
12724                 if (!crtc->state->active)
12725                         continue;
12726
12727                 sw_config = to_intel_crtc_state(crtc->state);
12728                 if (!intel_pipe_config_compare(dev, sw_config,
12729                                                pipe_config, false)) {
12730                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12731                         intel_dump_pipe_config(intel_crtc, pipe_config,
12732                                                "[hw state]");
12733                         intel_dump_pipe_config(intel_crtc, sw_config,
12734                                                "[sw state]");
12735                 }
12736         }
12737 }
12738
12739 static void
12740 check_shared_dpll_state(struct drm_device *dev)
12741 {
12742         struct drm_i915_private *dev_priv = dev->dev_private;
12743         struct intel_crtc *crtc;
12744         struct intel_dpll_hw_state dpll_hw_state;
12745         int i;
12746
12747         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12748                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12749                 int enabled_crtcs = 0, active_crtcs = 0;
12750                 bool active;
12751
12752                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12753
12754                 DRM_DEBUG_KMS("%s\n", pll->name);
12755
12756                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12757
12758                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12759                      "more active pll users than references: %i vs %i\n",
12760                      pll->active, hweight32(pll->config.crtc_mask));
12761                 I915_STATE_WARN(pll->active && !pll->on,
12762                      "pll in active use but not on in sw tracking\n");
12763                 I915_STATE_WARN(pll->on && !pll->active,
12764                      "pll in on but not on in use in sw tracking\n");
12765                 I915_STATE_WARN(pll->on != active,
12766                      "pll on state mismatch (expected %i, found %i)\n",
12767                      pll->on, active);
12768
12769                 for_each_intel_crtc(dev, crtc) {
12770                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12771                                 enabled_crtcs++;
12772                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12773                                 active_crtcs++;
12774                 }
12775                 I915_STATE_WARN(pll->active != active_crtcs,
12776                      "pll active crtcs mismatch (expected %i, found %i)\n",
12777                      pll->active, active_crtcs);
12778                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12779                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12780                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12781
12782                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12783                                        sizeof(dpll_hw_state)),
12784                      "pll hw state mismatch\n");
12785         }
12786 }
12787
12788 static void
12789 intel_modeset_check_state(struct drm_device *dev,
12790                           struct drm_atomic_state *old_state)
12791 {
12792         check_wm_state(dev);
12793         check_connector_state(dev, old_state);
12794         check_encoder_state(dev);
12795         check_crtc_state(dev, old_state);
12796         check_shared_dpll_state(dev);
12797 }
12798
12799 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12800                                      int dotclock)
12801 {
12802         /*
12803          * FDI already provided one idea for the dotclock.
12804          * Yell if the encoder disagrees.
12805          */
12806         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12807              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12808              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12809 }
12810
12811 static void update_scanline_offset(struct intel_crtc *crtc)
12812 {
12813         struct drm_device *dev = crtc->base.dev;
12814
12815         /*
12816          * The scanline counter increments at the leading edge of hsync.
12817          *
12818          * On most platforms it starts counting from vtotal-1 on the
12819          * first active line. That means the scanline counter value is
12820          * always one less than what we would expect. Ie. just after
12821          * start of vblank, which also occurs at start of hsync (on the
12822          * last active line), the scanline counter will read vblank_start-1.
12823          *
12824          * On gen2 the scanline counter starts counting from 1 instead
12825          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12826          * to keep the value positive), instead of adding one.
12827          *
12828          * On HSW+ the behaviour of the scanline counter depends on the output
12829          * type. For DP ports it behaves like most other platforms, but on HDMI
12830          * there's an extra 1 line difference. So we need to add two instead of
12831          * one to the value.
12832          */
12833         if (IS_GEN2(dev)) {
12834                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12835                 int vtotal;
12836
12837                 vtotal = adjusted_mode->crtc_vtotal;
12838                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12839                         vtotal /= 2;
12840
12841                 crtc->scanline_offset = vtotal - 1;
12842         } else if (HAS_DDI(dev) &&
12843                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12844                 crtc->scanline_offset = 2;
12845         } else
12846                 crtc->scanline_offset = 1;
12847 }
12848
12849 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12850 {
12851         struct drm_device *dev = state->dev;
12852         struct drm_i915_private *dev_priv = to_i915(dev);
12853         struct intel_shared_dpll_config *shared_dpll = NULL;
12854         struct intel_crtc *intel_crtc;
12855         struct intel_crtc_state *intel_crtc_state;
12856         struct drm_crtc *crtc;
12857         struct drm_crtc_state *crtc_state;
12858         int i;
12859
12860         if (!dev_priv->display.crtc_compute_clock)
12861                 return;
12862
12863         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12864                 int dpll;
12865
12866                 intel_crtc = to_intel_crtc(crtc);
12867                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12868                 dpll = intel_crtc_state->shared_dpll;
12869
12870                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12871                         continue;
12872
12873                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12874
12875                 if (!shared_dpll)
12876                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12877
12878                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12879         }
12880 }
12881
12882 /*
12883  * This implements the workaround described in the "notes" section of the mode
12884  * set sequence documentation. When going from no pipes or single pipe to
12885  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12886  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12887  */
12888 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12889 {
12890         struct drm_crtc_state *crtc_state;
12891         struct intel_crtc *intel_crtc;
12892         struct drm_crtc *crtc;
12893         struct intel_crtc_state *first_crtc_state = NULL;
12894         struct intel_crtc_state *other_crtc_state = NULL;
12895         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12896         int i;
12897
12898         /* look at all crtc's that are going to be enabled in during modeset */
12899         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12900                 intel_crtc = to_intel_crtc(crtc);
12901
12902                 if (!crtc_state->active || !needs_modeset(crtc_state))
12903                         continue;
12904
12905                 if (first_crtc_state) {
12906                         other_crtc_state = to_intel_crtc_state(crtc_state);
12907                         break;
12908                 } else {
12909                         first_crtc_state = to_intel_crtc_state(crtc_state);
12910                         first_pipe = intel_crtc->pipe;
12911                 }
12912         }
12913
12914         /* No workaround needed? */
12915         if (!first_crtc_state)
12916                 return 0;
12917
12918         /* w/a possibly needed, check how many crtc's are already enabled. */
12919         for_each_intel_crtc(state->dev, intel_crtc) {
12920                 struct intel_crtc_state *pipe_config;
12921
12922                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12923                 if (IS_ERR(pipe_config))
12924                         return PTR_ERR(pipe_config);
12925
12926                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12927
12928                 if (!pipe_config->base.active ||
12929                     needs_modeset(&pipe_config->base))
12930                         continue;
12931
12932                 /* 2 or more enabled crtcs means no need for w/a */
12933                 if (enabled_pipe != INVALID_PIPE)
12934                         return 0;
12935
12936                 enabled_pipe = intel_crtc->pipe;
12937         }
12938
12939         if (enabled_pipe != INVALID_PIPE)
12940                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12941         else if (other_crtc_state)
12942                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12943
12944         return 0;
12945 }
12946
12947 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12948 {
12949         struct drm_crtc *crtc;
12950         struct drm_crtc_state *crtc_state;
12951         int ret = 0;
12952
12953         /* add all active pipes to the state */
12954         for_each_crtc(state->dev, crtc) {
12955                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12956                 if (IS_ERR(crtc_state))
12957                         return PTR_ERR(crtc_state);
12958
12959                 if (!crtc_state->active || needs_modeset(crtc_state))
12960                         continue;
12961
12962                 crtc_state->mode_changed = true;
12963
12964                 ret = drm_atomic_add_affected_connectors(state, crtc);
12965                 if (ret)
12966                         break;
12967
12968                 ret = drm_atomic_add_affected_planes(state, crtc);
12969                 if (ret)
12970                         break;
12971         }
12972
12973         return ret;
12974 }
12975
12976 static int intel_modeset_checks(struct drm_atomic_state *state)
12977 {
12978         struct drm_device *dev = state->dev;
12979         struct drm_i915_private *dev_priv = dev->dev_private;
12980         int ret;
12981
12982         if (!check_digital_port_conflicts(state)) {
12983                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12984                 return -EINVAL;
12985         }
12986
12987         /*
12988          * See if the config requires any additional preparation, e.g.
12989          * to adjust global state with pipes off.  We need to do this
12990          * here so we can get the modeset_pipe updated config for the new
12991          * mode set on this crtc.  For other crtcs we need to use the
12992          * adjusted_mode bits in the crtc directly.
12993          */
12994         if (dev_priv->display.modeset_calc_cdclk) {
12995                 unsigned int cdclk;
12996
12997                 ret = dev_priv->display.modeset_calc_cdclk(state);
12998
12999                 cdclk = to_intel_atomic_state(state)->cdclk;
13000                 if (!ret && cdclk != dev_priv->cdclk_freq)
13001                         ret = intel_modeset_all_pipes(state);
13002
13003                 if (ret < 0)
13004                         return ret;
13005         } else
13006                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13007
13008         intel_modeset_clear_plls(state);
13009
13010         if (IS_HASWELL(dev))
13011                 return haswell_mode_set_planes_workaround(state);
13012
13013         return 0;
13014 }
13015
13016 /**
13017  * intel_atomic_check - validate state object
13018  * @dev: drm device
13019  * @state: state to validate
13020  */
13021 static int intel_atomic_check(struct drm_device *dev,
13022                               struct drm_atomic_state *state)
13023 {
13024         struct drm_crtc *crtc;
13025         struct drm_crtc_state *crtc_state;
13026         int ret, i;
13027         bool any_ms = false;
13028
13029         ret = drm_atomic_helper_check_modeset(dev, state);
13030         if (ret)
13031                 return ret;
13032
13033         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13034                 struct intel_crtc_state *pipe_config =
13035                         to_intel_crtc_state(crtc_state);
13036
13037                 memset(&to_intel_crtc(crtc)->atomic, 0,
13038                        sizeof(struct intel_crtc_atomic_commit));
13039
13040                 /* Catch I915_MODE_FLAG_INHERITED */
13041                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13042                         crtc_state->mode_changed = true;
13043
13044                 if (!crtc_state->enable) {
13045                         if (needs_modeset(crtc_state))
13046                                 any_ms = true;
13047                         continue;
13048                 }
13049
13050                 if (!needs_modeset(crtc_state))
13051                         continue;
13052
13053                 /* FIXME: For only active_changed we shouldn't need to do any
13054                  * state recomputation at all. */
13055
13056                 ret = drm_atomic_add_affected_connectors(state, crtc);
13057                 if (ret)
13058                         return ret;
13059
13060                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13061                 if (ret)
13062                         return ret;
13063
13064                 if (intel_pipe_config_compare(state->dev,
13065                                         to_intel_crtc_state(crtc->state),
13066                                         pipe_config, true)) {
13067                         crtc_state->mode_changed = false;
13068                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13069                 }
13070
13071                 if (needs_modeset(crtc_state)) {
13072                         any_ms = true;
13073
13074                         ret = drm_atomic_add_affected_planes(state, crtc);
13075                         if (ret)
13076                                 return ret;
13077                 }
13078
13079                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13080                                        needs_modeset(crtc_state) ?
13081                                        "[modeset]" : "[fastset]");
13082         }
13083
13084         if (any_ms) {
13085                 ret = intel_modeset_checks(state);
13086
13087                 if (ret)
13088                         return ret;
13089         } else
13090                 to_intel_atomic_state(state)->cdclk =
13091                         to_i915(state->dev)->cdclk_freq;
13092
13093         return drm_atomic_helper_check_planes(state->dev, state);
13094 }
13095
13096 /**
13097  * intel_atomic_commit - commit validated state object
13098  * @dev: DRM device
13099  * @state: the top-level driver state object
13100  * @async: asynchronous commit
13101  *
13102  * This function commits a top-level state object that has been validated
13103  * with drm_atomic_helper_check().
13104  *
13105  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13106  * we can only handle plane-related operations and do not yet support
13107  * asynchronous commit.
13108  *
13109  * RETURNS
13110  * Zero for success or -errno.
13111  */
13112 static int intel_atomic_commit(struct drm_device *dev,
13113                                struct drm_atomic_state *state,
13114                                bool async)
13115 {
13116         struct drm_i915_private *dev_priv = dev->dev_private;
13117         struct drm_crtc *crtc;
13118         struct drm_crtc_state *crtc_state;
13119         int ret = 0;
13120         int i;
13121         bool any_ms = false;
13122
13123         if (async) {
13124                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13125                 return -EINVAL;
13126         }
13127
13128         ret = drm_atomic_helper_prepare_planes(dev, state);
13129         if (ret)
13130                 return ret;
13131
13132         drm_atomic_helper_swap_state(dev, state);
13133
13134         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13135                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13136
13137                 if (!needs_modeset(crtc->state))
13138                         continue;
13139
13140                 any_ms = true;
13141                 intel_pre_plane_update(intel_crtc);
13142
13143                 if (crtc_state->active) {
13144                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13145                         dev_priv->display.crtc_disable(crtc);
13146                         intel_crtc->active = false;
13147                         intel_disable_shared_dpll(intel_crtc);
13148                 }
13149         }
13150
13151         /* Only after disabling all output pipelines that will be changed can we
13152          * update the the output configuration. */
13153         intel_modeset_update_crtc_state(state);
13154
13155         if (any_ms) {
13156                 intel_shared_dpll_commit(state);
13157
13158                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13159                 modeset_update_crtc_power_domains(state);
13160         }
13161
13162         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13163         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13164                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13165                 bool modeset = needs_modeset(crtc->state);
13166                 bool update_pipe = !modeset &&
13167                         to_intel_crtc_state(crtc->state)->update_pipe;
13168                 unsigned long put_domains = 0;
13169
13170                 if (modeset && crtc->state->active) {
13171                         update_scanline_offset(to_intel_crtc(crtc));
13172                         dev_priv->display.crtc_enable(crtc);
13173                 }
13174
13175                 if (update_pipe) {
13176                         put_domains = modeset_get_crtc_power_domains(crtc);
13177
13178                         /* make sure intel_modeset_check_state runs */
13179                         any_ms = true;
13180                 }
13181
13182                 if (!modeset)
13183                         intel_pre_plane_update(intel_crtc);
13184
13185                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13186
13187                 if (put_domains)
13188                         modeset_put_power_domains(dev_priv, put_domains);
13189
13190                 intel_post_plane_update(intel_crtc);
13191         }
13192
13193         /* FIXME: add subpixel order */
13194
13195         drm_atomic_helper_wait_for_vblanks(dev, state);
13196         drm_atomic_helper_cleanup_planes(dev, state);
13197
13198         if (any_ms)
13199                 intel_modeset_check_state(dev, state);
13200
13201         drm_atomic_state_free(state);
13202
13203         return 0;
13204 }
13205
13206 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13207 {
13208         struct drm_device *dev = crtc->dev;
13209         struct drm_atomic_state *state;
13210         struct drm_crtc_state *crtc_state;
13211         int ret;
13212
13213         state = drm_atomic_state_alloc(dev);
13214         if (!state) {
13215                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13216                               crtc->base.id);
13217                 return;
13218         }
13219
13220         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13221
13222 retry:
13223         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13224         ret = PTR_ERR_OR_ZERO(crtc_state);
13225         if (!ret) {
13226                 if (!crtc_state->active)
13227                         goto out;
13228
13229                 crtc_state->mode_changed = true;
13230                 ret = drm_atomic_commit(state);
13231         }
13232
13233         if (ret == -EDEADLK) {
13234                 drm_atomic_state_clear(state);
13235                 drm_modeset_backoff(state->acquire_ctx);
13236                 goto retry;
13237         }
13238
13239         if (ret)
13240 out:
13241                 drm_atomic_state_free(state);
13242 }
13243
13244 #undef for_each_intel_crtc_masked
13245
13246 static const struct drm_crtc_funcs intel_crtc_funcs = {
13247         .gamma_set = intel_crtc_gamma_set,
13248         .set_config = drm_atomic_helper_set_config,
13249         .destroy = intel_crtc_destroy,
13250         .page_flip = intel_crtc_page_flip,
13251         .atomic_duplicate_state = intel_crtc_duplicate_state,
13252         .atomic_destroy_state = intel_crtc_destroy_state,
13253 };
13254
13255 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13256                                       struct intel_shared_dpll *pll,
13257                                       struct intel_dpll_hw_state *hw_state)
13258 {
13259         uint32_t val;
13260
13261         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13262                 return false;
13263
13264         val = I915_READ(PCH_DPLL(pll->id));
13265         hw_state->dpll = val;
13266         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13267         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13268
13269         return val & DPLL_VCO_ENABLE;
13270 }
13271
13272 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13273                                   struct intel_shared_dpll *pll)
13274 {
13275         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13276         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13277 }
13278
13279 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13280                                 struct intel_shared_dpll *pll)
13281 {
13282         /* PCH refclock must be enabled first */
13283         ibx_assert_pch_refclk_enabled(dev_priv);
13284
13285         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13286
13287         /* Wait for the clocks to stabilize. */
13288         POSTING_READ(PCH_DPLL(pll->id));
13289         udelay(150);
13290
13291         /* The pixel multiplier can only be updated once the
13292          * DPLL is enabled and the clocks are stable.
13293          *
13294          * So write it again.
13295          */
13296         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13297         POSTING_READ(PCH_DPLL(pll->id));
13298         udelay(200);
13299 }
13300
13301 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13302                                  struct intel_shared_dpll *pll)
13303 {
13304         struct drm_device *dev = dev_priv->dev;
13305         struct intel_crtc *crtc;
13306
13307         /* Make sure no transcoder isn't still depending on us. */
13308         for_each_intel_crtc(dev, crtc) {
13309                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13310                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13311         }
13312
13313         I915_WRITE(PCH_DPLL(pll->id), 0);
13314         POSTING_READ(PCH_DPLL(pll->id));
13315         udelay(200);
13316 }
13317
13318 static char *ibx_pch_dpll_names[] = {
13319         "PCH DPLL A",
13320         "PCH DPLL B",
13321 };
13322
13323 static void ibx_pch_dpll_init(struct drm_device *dev)
13324 {
13325         struct drm_i915_private *dev_priv = dev->dev_private;
13326         int i;
13327
13328         dev_priv->num_shared_dpll = 2;
13329
13330         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13331                 dev_priv->shared_dplls[i].id = i;
13332                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13333                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13334                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13335                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13336                 dev_priv->shared_dplls[i].get_hw_state =
13337                         ibx_pch_dpll_get_hw_state;
13338         }
13339 }
13340
13341 static void intel_shared_dpll_init(struct drm_device *dev)
13342 {
13343         struct drm_i915_private *dev_priv = dev->dev_private;
13344
13345         if (HAS_DDI(dev))
13346                 intel_ddi_pll_init(dev);
13347         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13348                 ibx_pch_dpll_init(dev);
13349         else
13350                 dev_priv->num_shared_dpll = 0;
13351
13352         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13353 }
13354
13355 /**
13356  * intel_prepare_plane_fb - Prepare fb for usage on plane
13357  * @plane: drm plane to prepare for
13358  * @fb: framebuffer to prepare for presentation
13359  *
13360  * Prepares a framebuffer for usage on a display plane.  Generally this
13361  * involves pinning the underlying object and updating the frontbuffer tracking
13362  * bits.  Some older platforms need special physical address handling for
13363  * cursor planes.
13364  *
13365  * Returns 0 on success, negative error code on failure.
13366  */
13367 int
13368 intel_prepare_plane_fb(struct drm_plane *plane,
13369                        const struct drm_plane_state *new_state)
13370 {
13371         struct drm_device *dev = plane->dev;
13372         struct drm_framebuffer *fb = new_state->fb;
13373         struct intel_plane *intel_plane = to_intel_plane(plane);
13374         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13375         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13376         int ret = 0;
13377
13378         if (!obj)
13379                 return 0;
13380
13381         mutex_lock(&dev->struct_mutex);
13382
13383         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13384             INTEL_INFO(dev)->cursor_needs_physical) {
13385                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13386                 ret = i915_gem_object_attach_phys(obj, align);
13387                 if (ret)
13388                         DRM_DEBUG_KMS("failed to attach phys object\n");
13389         } else {
13390                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13391         }
13392
13393         if (ret == 0)
13394                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13395
13396         mutex_unlock(&dev->struct_mutex);
13397
13398         return ret;
13399 }
13400
13401 /**
13402  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13403  * @plane: drm plane to clean up for
13404  * @fb: old framebuffer that was on plane
13405  *
13406  * Cleans up a framebuffer that has just been removed from a plane.
13407  */
13408 void
13409 intel_cleanup_plane_fb(struct drm_plane *plane,
13410                        const struct drm_plane_state *old_state)
13411 {
13412         struct drm_device *dev = plane->dev;
13413         struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13414
13415         if (!obj)
13416                 return;
13417
13418         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13419             !INTEL_INFO(dev)->cursor_needs_physical) {
13420                 mutex_lock(&dev->struct_mutex);
13421                 intel_unpin_fb_obj(old_state->fb, old_state);
13422                 mutex_unlock(&dev->struct_mutex);
13423         }
13424 }
13425
13426 int
13427 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13428 {
13429         int max_scale;
13430         struct drm_device *dev;
13431         struct drm_i915_private *dev_priv;
13432         int crtc_clock, cdclk;
13433
13434         if (!intel_crtc || !crtc_state)
13435                 return DRM_PLANE_HELPER_NO_SCALING;
13436
13437         dev = intel_crtc->base.dev;
13438         dev_priv = dev->dev_private;
13439         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13440         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13441
13442         if (!crtc_clock || !cdclk)
13443                 return DRM_PLANE_HELPER_NO_SCALING;
13444
13445         /*
13446          * skl max scale is lower of:
13447          *    close to 3 but not 3, -1 is for that purpose
13448          *            or
13449          *    cdclk/crtc_clock
13450          */
13451         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13452
13453         return max_scale;
13454 }
13455
13456 static int
13457 intel_check_primary_plane(struct drm_plane *plane,
13458                           struct intel_crtc_state *crtc_state,
13459                           struct intel_plane_state *state)
13460 {
13461         struct drm_crtc *crtc = state->base.crtc;
13462         struct drm_framebuffer *fb = state->base.fb;
13463         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13464         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13465         bool can_position = false;
13466
13467         /* use scaler when colorkey is not required */
13468         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13469             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13470                 min_scale = 1;
13471                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13472                 can_position = true;
13473         }
13474
13475         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13476                                              &state->dst, &state->clip,
13477                                              min_scale, max_scale,
13478                                              can_position, true,
13479                                              &state->visible);
13480 }
13481
13482 static void
13483 intel_commit_primary_plane(struct drm_plane *plane,
13484                            struct intel_plane_state *state)
13485 {
13486         struct drm_crtc *crtc = state->base.crtc;
13487         struct drm_framebuffer *fb = state->base.fb;
13488         struct drm_device *dev = plane->dev;
13489         struct drm_i915_private *dev_priv = dev->dev_private;
13490         struct intel_crtc *intel_crtc;
13491         struct drm_rect *src = &state->src;
13492
13493         crtc = crtc ? crtc : plane->crtc;
13494         intel_crtc = to_intel_crtc(crtc);
13495
13496         plane->fb = fb;
13497         crtc->x = src->x1 >> 16;
13498         crtc->y = src->y1 >> 16;
13499
13500         if (!crtc->state->active)
13501                 return;
13502
13503         dev_priv->display.update_primary_plane(crtc, fb,
13504                                                state->src.x1 >> 16,
13505                                                state->src.y1 >> 16);
13506 }
13507
13508 static void
13509 intel_disable_primary_plane(struct drm_plane *plane,
13510                             struct drm_crtc *crtc)
13511 {
13512         struct drm_device *dev = plane->dev;
13513         struct drm_i915_private *dev_priv = dev->dev_private;
13514
13515         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13516 }
13517
13518 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13519                                     struct drm_crtc_state *old_crtc_state)
13520 {
13521         struct drm_device *dev = crtc->dev;
13522         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13523         struct intel_crtc_state *old_intel_state =
13524                 to_intel_crtc_state(old_crtc_state);
13525         bool modeset = needs_modeset(crtc->state);
13526
13527         if (intel_crtc->atomic.update_wm_pre)
13528                 intel_update_watermarks(crtc);
13529
13530         /* Perform vblank evasion around commit operation */
13531         if (crtc->state->active)
13532                 intel_pipe_update_start(intel_crtc);
13533
13534         if (modeset)
13535                 return;
13536
13537         if (to_intel_crtc_state(crtc->state)->update_pipe)
13538                 intel_update_pipe_config(intel_crtc, old_intel_state);
13539         else if (INTEL_INFO(dev)->gen >= 9)
13540                 skl_detach_scalers(intel_crtc);
13541 }
13542
13543 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13544                                      struct drm_crtc_state *old_crtc_state)
13545 {
13546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13547
13548         if (crtc->state->active)
13549                 intel_pipe_update_end(intel_crtc);
13550 }
13551
13552 /**
13553  * intel_plane_destroy - destroy a plane
13554  * @plane: plane to destroy
13555  *
13556  * Common destruction function for all types of planes (primary, cursor,
13557  * sprite).
13558  */
13559 void intel_plane_destroy(struct drm_plane *plane)
13560 {
13561         struct intel_plane *intel_plane = to_intel_plane(plane);
13562         drm_plane_cleanup(plane);
13563         kfree(intel_plane);
13564 }
13565
13566 const struct drm_plane_funcs intel_plane_funcs = {
13567         .update_plane = drm_atomic_helper_update_plane,
13568         .disable_plane = drm_atomic_helper_disable_plane,
13569         .destroy = intel_plane_destroy,
13570         .set_property = drm_atomic_helper_plane_set_property,
13571         .atomic_get_property = intel_plane_atomic_get_property,
13572         .atomic_set_property = intel_plane_atomic_set_property,
13573         .atomic_duplicate_state = intel_plane_duplicate_state,
13574         .atomic_destroy_state = intel_plane_destroy_state,
13575
13576 };
13577
13578 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13579                                                     int pipe)
13580 {
13581         struct intel_plane *primary;
13582         struct intel_plane_state *state;
13583         const uint32_t *intel_primary_formats;
13584         unsigned int num_formats;
13585
13586         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13587         if (primary == NULL)
13588                 return NULL;
13589
13590         state = intel_create_plane_state(&primary->base);
13591         if (!state) {
13592                 kfree(primary);
13593                 return NULL;
13594         }
13595         primary->base.state = &state->base;
13596
13597         primary->can_scale = false;
13598         primary->max_downscale = 1;
13599         if (INTEL_INFO(dev)->gen >= 9) {
13600                 primary->can_scale = true;
13601                 state->scaler_id = -1;
13602         }
13603         primary->pipe = pipe;
13604         primary->plane = pipe;
13605         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13606         primary->check_plane = intel_check_primary_plane;
13607         primary->commit_plane = intel_commit_primary_plane;
13608         primary->disable_plane = intel_disable_primary_plane;
13609         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13610                 primary->plane = !pipe;
13611
13612         if (INTEL_INFO(dev)->gen >= 9) {
13613                 intel_primary_formats = skl_primary_formats;
13614                 num_formats = ARRAY_SIZE(skl_primary_formats);
13615         } else if (INTEL_INFO(dev)->gen >= 4) {
13616                 intel_primary_formats = i965_primary_formats;
13617                 num_formats = ARRAY_SIZE(i965_primary_formats);
13618         } else {
13619                 intel_primary_formats = i8xx_primary_formats;
13620                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13621         }
13622
13623         drm_universal_plane_init(dev, &primary->base, 0,
13624                                  &intel_plane_funcs,
13625                                  intel_primary_formats, num_formats,
13626                                  DRM_PLANE_TYPE_PRIMARY);
13627
13628         if (INTEL_INFO(dev)->gen >= 4)
13629                 intel_create_rotation_property(dev, primary);
13630
13631         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13632
13633         return &primary->base;
13634 }
13635
13636 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13637 {
13638         if (!dev->mode_config.rotation_property) {
13639                 unsigned long flags = BIT(DRM_ROTATE_0) |
13640                         BIT(DRM_ROTATE_180);
13641
13642                 if (INTEL_INFO(dev)->gen >= 9)
13643                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13644
13645                 dev->mode_config.rotation_property =
13646                         drm_mode_create_rotation_property(dev, flags);
13647         }
13648         if (dev->mode_config.rotation_property)
13649                 drm_object_attach_property(&plane->base.base,
13650                                 dev->mode_config.rotation_property,
13651                                 plane->base.state->rotation);
13652 }
13653
13654 static int
13655 intel_check_cursor_plane(struct drm_plane *plane,
13656                          struct intel_crtc_state *crtc_state,
13657                          struct intel_plane_state *state)
13658 {
13659         struct drm_crtc *crtc = crtc_state->base.crtc;
13660         struct drm_framebuffer *fb = state->base.fb;
13661         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13662         unsigned stride;
13663         int ret;
13664
13665         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13666                                             &state->dst, &state->clip,
13667                                             DRM_PLANE_HELPER_NO_SCALING,
13668                                             DRM_PLANE_HELPER_NO_SCALING,
13669                                             true, true, &state->visible);
13670         if (ret)
13671                 return ret;
13672
13673         /* if we want to turn off the cursor ignore width and height */
13674         if (!obj)
13675                 return 0;
13676
13677         /* Check for which cursor types we support */
13678         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13679                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13680                           state->base.crtc_w, state->base.crtc_h);
13681                 return -EINVAL;
13682         }
13683
13684         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13685         if (obj->base.size < stride * state->base.crtc_h) {
13686                 DRM_DEBUG_KMS("buffer is too small\n");
13687                 return -ENOMEM;
13688         }
13689
13690         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13691                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13692                 return -EINVAL;
13693         }
13694
13695         return 0;
13696 }
13697
13698 static void
13699 intel_disable_cursor_plane(struct drm_plane *plane,
13700                            struct drm_crtc *crtc)
13701 {
13702         intel_crtc_update_cursor(crtc, false);
13703 }
13704
13705 static void
13706 intel_commit_cursor_plane(struct drm_plane *plane,
13707                           struct intel_plane_state *state)
13708 {
13709         struct drm_crtc *crtc = state->base.crtc;
13710         struct drm_device *dev = plane->dev;
13711         struct intel_crtc *intel_crtc;
13712         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13713         uint32_t addr;
13714
13715         crtc = crtc ? crtc : plane->crtc;
13716         intel_crtc = to_intel_crtc(crtc);
13717
13718         if (intel_crtc->cursor_bo == obj)
13719                 goto update;
13720
13721         if (!obj)
13722                 addr = 0;
13723         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13724                 addr = i915_gem_obj_ggtt_offset(obj);
13725         else
13726                 addr = obj->phys_handle->busaddr;
13727
13728         intel_crtc->cursor_addr = addr;
13729         intel_crtc->cursor_bo = obj;
13730
13731 update:
13732         if (crtc->state->active)
13733                 intel_crtc_update_cursor(crtc, state->visible);
13734 }
13735
13736 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13737                                                    int pipe)
13738 {
13739         struct intel_plane *cursor;
13740         struct intel_plane_state *state;
13741
13742         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13743         if (cursor == NULL)
13744                 return NULL;
13745
13746         state = intel_create_plane_state(&cursor->base);
13747         if (!state) {
13748                 kfree(cursor);
13749                 return NULL;
13750         }
13751         cursor->base.state = &state->base;
13752
13753         cursor->can_scale = false;
13754         cursor->max_downscale = 1;
13755         cursor->pipe = pipe;
13756         cursor->plane = pipe;
13757         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13758         cursor->check_plane = intel_check_cursor_plane;
13759         cursor->commit_plane = intel_commit_cursor_plane;
13760         cursor->disable_plane = intel_disable_cursor_plane;
13761
13762         drm_universal_plane_init(dev, &cursor->base, 0,
13763                                  &intel_plane_funcs,
13764                                  intel_cursor_formats,
13765                                  ARRAY_SIZE(intel_cursor_formats),
13766                                  DRM_PLANE_TYPE_CURSOR);
13767
13768         if (INTEL_INFO(dev)->gen >= 4) {
13769                 if (!dev->mode_config.rotation_property)
13770                         dev->mode_config.rotation_property =
13771                                 drm_mode_create_rotation_property(dev,
13772                                                         BIT(DRM_ROTATE_0) |
13773                                                         BIT(DRM_ROTATE_180));
13774                 if (dev->mode_config.rotation_property)
13775                         drm_object_attach_property(&cursor->base.base,
13776                                 dev->mode_config.rotation_property,
13777                                 state->base.rotation);
13778         }
13779
13780         if (INTEL_INFO(dev)->gen >=9)
13781                 state->scaler_id = -1;
13782
13783         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13784
13785         return &cursor->base;
13786 }
13787
13788 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13789         struct intel_crtc_state *crtc_state)
13790 {
13791         int i;
13792         struct intel_scaler *intel_scaler;
13793         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13794
13795         for (i = 0; i < intel_crtc->num_scalers; i++) {
13796                 intel_scaler = &scaler_state->scalers[i];
13797                 intel_scaler->in_use = 0;
13798                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13799         }
13800
13801         scaler_state->scaler_id = -1;
13802 }
13803
13804 static void intel_crtc_init(struct drm_device *dev, int pipe)
13805 {
13806         struct drm_i915_private *dev_priv = dev->dev_private;
13807         struct intel_crtc *intel_crtc;
13808         struct intel_crtc_state *crtc_state = NULL;
13809         struct drm_plane *primary = NULL;
13810         struct drm_plane *cursor = NULL;
13811         int i, ret;
13812
13813         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13814         if (intel_crtc == NULL)
13815                 return;
13816
13817         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13818         if (!crtc_state)
13819                 goto fail;
13820         intel_crtc->config = crtc_state;
13821         intel_crtc->base.state = &crtc_state->base;
13822         crtc_state->base.crtc = &intel_crtc->base;
13823
13824         /* initialize shared scalers */
13825         if (INTEL_INFO(dev)->gen >= 9) {
13826                 if (pipe == PIPE_C)
13827                         intel_crtc->num_scalers = 1;
13828                 else
13829                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13830
13831                 skl_init_scalers(dev, intel_crtc, crtc_state);
13832         }
13833
13834         primary = intel_primary_plane_create(dev, pipe);
13835         if (!primary)
13836                 goto fail;
13837
13838         cursor = intel_cursor_plane_create(dev, pipe);
13839         if (!cursor)
13840                 goto fail;
13841
13842         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13843                                         cursor, &intel_crtc_funcs);
13844         if (ret)
13845                 goto fail;
13846
13847         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13848         for (i = 0; i < 256; i++) {
13849                 intel_crtc->lut_r[i] = i;
13850                 intel_crtc->lut_g[i] = i;
13851                 intel_crtc->lut_b[i] = i;
13852         }
13853
13854         /*
13855          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13856          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13857          */
13858         intel_crtc->pipe = pipe;
13859         intel_crtc->plane = pipe;
13860         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13861                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13862                 intel_crtc->plane = !pipe;
13863         }
13864
13865         intel_crtc->cursor_base = ~0;
13866         intel_crtc->cursor_cntl = ~0;
13867         intel_crtc->cursor_size = ~0;
13868
13869         intel_crtc->wm.cxsr_allowed = true;
13870
13871         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13872                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13873         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13874         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13875
13876         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13877
13878         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13879         return;
13880
13881 fail:
13882         if (primary)
13883                 drm_plane_cleanup(primary);
13884         if (cursor)
13885                 drm_plane_cleanup(cursor);
13886         kfree(crtc_state);
13887         kfree(intel_crtc);
13888 }
13889
13890 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13891 {
13892         struct drm_encoder *encoder = connector->base.encoder;
13893         struct drm_device *dev = connector->base.dev;
13894
13895         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13896
13897         if (!encoder || WARN_ON(!encoder->crtc))
13898                 return INVALID_PIPE;
13899
13900         return to_intel_crtc(encoder->crtc)->pipe;
13901 }
13902
13903 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13904                                 struct drm_file *file)
13905 {
13906         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13907         struct drm_crtc *drmmode_crtc;
13908         struct intel_crtc *crtc;
13909
13910         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13911
13912         if (!drmmode_crtc) {
13913                 DRM_ERROR("no such CRTC id\n");
13914                 return -ENOENT;
13915         }
13916
13917         crtc = to_intel_crtc(drmmode_crtc);
13918         pipe_from_crtc_id->pipe = crtc->pipe;
13919
13920         return 0;
13921 }
13922
13923 static int intel_encoder_clones(struct intel_encoder *encoder)
13924 {
13925         struct drm_device *dev = encoder->base.dev;
13926         struct intel_encoder *source_encoder;
13927         int index_mask = 0;
13928         int entry = 0;
13929
13930         for_each_intel_encoder(dev, source_encoder) {
13931                 if (encoders_cloneable(encoder, source_encoder))
13932                         index_mask |= (1 << entry);
13933
13934                 entry++;
13935         }
13936
13937         return index_mask;
13938 }
13939
13940 static bool has_edp_a(struct drm_device *dev)
13941 {
13942         struct drm_i915_private *dev_priv = dev->dev_private;
13943
13944         if (!IS_MOBILE(dev))
13945                 return false;
13946
13947         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13948                 return false;
13949
13950         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13951                 return false;
13952
13953         return true;
13954 }
13955
13956 static bool intel_crt_present(struct drm_device *dev)
13957 {
13958         struct drm_i915_private *dev_priv = dev->dev_private;
13959
13960         if (INTEL_INFO(dev)->gen >= 9)
13961                 return false;
13962
13963         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13964                 return false;
13965
13966         if (IS_CHERRYVIEW(dev))
13967                 return false;
13968
13969         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13970                 return false;
13971
13972         return true;
13973 }
13974
13975 static void intel_setup_outputs(struct drm_device *dev)
13976 {
13977         struct drm_i915_private *dev_priv = dev->dev_private;
13978         struct intel_encoder *encoder;
13979         bool dpd_is_edp = false;
13980
13981         intel_lvds_init(dev);
13982
13983         if (intel_crt_present(dev))
13984                 intel_crt_init(dev);
13985
13986         if (IS_BROXTON(dev)) {
13987                 /*
13988                  * FIXME: Broxton doesn't support port detection via the
13989                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13990                  * detect the ports.
13991                  */
13992                 intel_ddi_init(dev, PORT_A);
13993                 intel_ddi_init(dev, PORT_B);
13994                 intel_ddi_init(dev, PORT_C);
13995         } else if (HAS_DDI(dev)) {
13996                 int found;
13997
13998                 /*
13999                  * Haswell uses DDI functions to detect digital outputs.
14000                  * On SKL pre-D0 the strap isn't connected, so we assume
14001                  * it's there.
14002                  */
14003                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14004                 /* WaIgnoreDDIAStrap: skl */
14005                 if (found || IS_SKYLAKE(dev))
14006                         intel_ddi_init(dev, PORT_A);
14007
14008                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14009                  * register */
14010                 found = I915_READ(SFUSE_STRAP);
14011
14012                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14013                         intel_ddi_init(dev, PORT_B);
14014                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14015                         intel_ddi_init(dev, PORT_C);
14016                 if (found & SFUSE_STRAP_DDID_DETECTED)
14017                         intel_ddi_init(dev, PORT_D);
14018                 /*
14019                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14020                  */
14021                 if (IS_SKYLAKE(dev) &&
14022                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14023                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14024                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14025                         intel_ddi_init(dev, PORT_E);
14026
14027         } else if (HAS_PCH_SPLIT(dev)) {
14028                 int found;
14029                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14030
14031                 if (has_edp_a(dev))
14032                         intel_dp_init(dev, DP_A, PORT_A);
14033
14034                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14035                         /* PCH SDVOB multiplex with HDMIB */
14036                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14037                         if (!found)
14038                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14039                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14040                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14041                 }
14042
14043                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14044                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14045
14046                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14047                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14048
14049                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14050                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14051
14052                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14053                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14054         } else if (IS_VALLEYVIEW(dev)) {
14055                 /*
14056                  * The DP_DETECTED bit is the latched state of the DDC
14057                  * SDA pin at boot. However since eDP doesn't require DDC
14058                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14059                  * eDP ports may have been muxed to an alternate function.
14060                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14061                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14062                  * detect eDP ports.
14063                  */
14064                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14065                     !intel_dp_is_edp(dev, PORT_B))
14066                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14067                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14068                     intel_dp_is_edp(dev, PORT_B))
14069                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14070
14071                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14072                     !intel_dp_is_edp(dev, PORT_C))
14073                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14074                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14075                     intel_dp_is_edp(dev, PORT_C))
14076                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14077
14078                 if (IS_CHERRYVIEW(dev)) {
14079                         /* eDP not supported on port D, so don't check VBT */
14080                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14081                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14082                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14083                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14084                 }
14085
14086                 intel_dsi_init(dev);
14087         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14088                 bool found = false;
14089
14090                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14091                         DRM_DEBUG_KMS("probing SDVOB\n");
14092                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14093                         if (!found && IS_G4X(dev)) {
14094                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14095                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14096                         }
14097
14098                         if (!found && IS_G4X(dev))
14099                                 intel_dp_init(dev, DP_B, PORT_B);
14100                 }
14101
14102                 /* Before G4X SDVOC doesn't have its own detect register */
14103
14104                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14105                         DRM_DEBUG_KMS("probing SDVOC\n");
14106                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14107                 }
14108
14109                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14110
14111                         if (IS_G4X(dev)) {
14112                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14113                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14114                         }
14115                         if (IS_G4X(dev))
14116                                 intel_dp_init(dev, DP_C, PORT_C);
14117                 }
14118
14119                 if (IS_G4X(dev) &&
14120                     (I915_READ(DP_D) & DP_DETECTED))
14121                         intel_dp_init(dev, DP_D, PORT_D);
14122         } else if (IS_GEN2(dev))
14123                 intel_dvo_init(dev);
14124
14125         if (SUPPORTS_TV(dev))
14126                 intel_tv_init(dev);
14127
14128         intel_psr_init(dev);
14129
14130         for_each_intel_encoder(dev, encoder) {
14131                 encoder->base.possible_crtcs = encoder->crtc_mask;
14132                 encoder->base.possible_clones =
14133                         intel_encoder_clones(encoder);
14134         }
14135
14136         intel_init_pch_refclk(dev);
14137
14138         drm_helper_move_panel_connectors_to_head(dev);
14139 }
14140
14141 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14142 {
14143         struct drm_device *dev = fb->dev;
14144         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14145
14146         drm_framebuffer_cleanup(fb);
14147         mutex_lock(&dev->struct_mutex);
14148         WARN_ON(!intel_fb->obj->framebuffer_references--);
14149         drm_gem_object_unreference(&intel_fb->obj->base);
14150         mutex_unlock(&dev->struct_mutex);
14151         kfree(intel_fb);
14152 }
14153
14154 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14155                                                 struct drm_file *file,
14156                                                 unsigned int *handle)
14157 {
14158         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14159         struct drm_i915_gem_object *obj = intel_fb->obj;
14160
14161         if (obj->userptr.mm) {
14162                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14163                 return -EINVAL;
14164         }
14165
14166         return drm_gem_handle_create(file, &obj->base, handle);
14167 }
14168
14169 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14170                                         struct drm_file *file,
14171                                         unsigned flags, unsigned color,
14172                                         struct drm_clip_rect *clips,
14173                                         unsigned num_clips)
14174 {
14175         struct drm_device *dev = fb->dev;
14176         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14177         struct drm_i915_gem_object *obj = intel_fb->obj;
14178
14179         mutex_lock(&dev->struct_mutex);
14180         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14181         mutex_unlock(&dev->struct_mutex);
14182
14183         return 0;
14184 }
14185
14186 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14187         .destroy = intel_user_framebuffer_destroy,
14188         .create_handle = intel_user_framebuffer_create_handle,
14189         .dirty = intel_user_framebuffer_dirty,
14190 };
14191
14192 static
14193 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14194                          uint32_t pixel_format)
14195 {
14196         u32 gen = INTEL_INFO(dev)->gen;
14197
14198         if (gen >= 9) {
14199                 /* "The stride in bytes must not exceed the of the size of 8K
14200                  *  pixels and 32K bytes."
14201                  */
14202                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14203         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14204                 return 32*1024;
14205         } else if (gen >= 4) {
14206                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14207                         return 16*1024;
14208                 else
14209                         return 32*1024;
14210         } else if (gen >= 3) {
14211                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14212                         return 8*1024;
14213                 else
14214                         return 16*1024;
14215         } else {
14216                 /* XXX DSPC is limited to 4k tiled */
14217                 return 8*1024;
14218         }
14219 }
14220
14221 static int intel_framebuffer_init(struct drm_device *dev,
14222                                   struct intel_framebuffer *intel_fb,
14223                                   struct drm_mode_fb_cmd2 *mode_cmd,
14224                                   struct drm_i915_gem_object *obj)
14225 {
14226         unsigned int aligned_height;
14227         int ret;
14228         u32 pitch_limit, stride_alignment;
14229
14230         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14231
14232         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14233                 /* Enforce that fb modifier and tiling mode match, but only for
14234                  * X-tiled. This is needed for FBC. */
14235                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14236                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14237                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14238                         return -EINVAL;
14239                 }
14240         } else {
14241                 if (obj->tiling_mode == I915_TILING_X)
14242                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14243                 else if (obj->tiling_mode == I915_TILING_Y) {
14244                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14245                         return -EINVAL;
14246                 }
14247         }
14248
14249         /* Passed in modifier sanity checking. */
14250         switch (mode_cmd->modifier[0]) {
14251         case I915_FORMAT_MOD_Y_TILED:
14252         case I915_FORMAT_MOD_Yf_TILED:
14253                 if (INTEL_INFO(dev)->gen < 9) {
14254                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14255                                   mode_cmd->modifier[0]);
14256                         return -EINVAL;
14257                 }
14258         case DRM_FORMAT_MOD_NONE:
14259         case I915_FORMAT_MOD_X_TILED:
14260                 break;
14261         default:
14262                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14263                           mode_cmd->modifier[0]);
14264                 return -EINVAL;
14265         }
14266
14267         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14268                                                      mode_cmd->pixel_format);
14269         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14270                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14271                           mode_cmd->pitches[0], stride_alignment);
14272                 return -EINVAL;
14273         }
14274
14275         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14276                                            mode_cmd->pixel_format);
14277         if (mode_cmd->pitches[0] > pitch_limit) {
14278                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14279                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14280                           "tiled" : "linear",
14281                           mode_cmd->pitches[0], pitch_limit);
14282                 return -EINVAL;
14283         }
14284
14285         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14286             mode_cmd->pitches[0] != obj->stride) {
14287                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14288                           mode_cmd->pitches[0], obj->stride);
14289                 return -EINVAL;
14290         }
14291
14292         /* Reject formats not supported by any plane early. */
14293         switch (mode_cmd->pixel_format) {
14294         case DRM_FORMAT_C8:
14295         case DRM_FORMAT_RGB565:
14296         case DRM_FORMAT_XRGB8888:
14297         case DRM_FORMAT_ARGB8888:
14298                 break;
14299         case DRM_FORMAT_XRGB1555:
14300                 if (INTEL_INFO(dev)->gen > 3) {
14301                         DRM_DEBUG("unsupported pixel format: %s\n",
14302                                   drm_get_format_name(mode_cmd->pixel_format));
14303                         return -EINVAL;
14304                 }
14305                 break;
14306         case DRM_FORMAT_ABGR8888:
14307                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14308                         DRM_DEBUG("unsupported pixel format: %s\n",
14309                                   drm_get_format_name(mode_cmd->pixel_format));
14310                         return -EINVAL;
14311                 }
14312                 break;
14313         case DRM_FORMAT_XBGR8888:
14314         case DRM_FORMAT_XRGB2101010:
14315         case DRM_FORMAT_XBGR2101010:
14316                 if (INTEL_INFO(dev)->gen < 4) {
14317                         DRM_DEBUG("unsupported pixel format: %s\n",
14318                                   drm_get_format_name(mode_cmd->pixel_format));
14319                         return -EINVAL;
14320                 }
14321                 break;
14322         case DRM_FORMAT_ABGR2101010:
14323                 if (!IS_VALLEYVIEW(dev)) {
14324                         DRM_DEBUG("unsupported pixel format: %s\n",
14325                                   drm_get_format_name(mode_cmd->pixel_format));
14326                         return -EINVAL;
14327                 }
14328                 break;
14329         case DRM_FORMAT_YUYV:
14330         case DRM_FORMAT_UYVY:
14331         case DRM_FORMAT_YVYU:
14332         case DRM_FORMAT_VYUY:
14333                 if (INTEL_INFO(dev)->gen < 5) {
14334                         DRM_DEBUG("unsupported pixel format: %s\n",
14335                                   drm_get_format_name(mode_cmd->pixel_format));
14336                         return -EINVAL;
14337                 }
14338                 break;
14339         default:
14340                 DRM_DEBUG("unsupported pixel format: %s\n",
14341                           drm_get_format_name(mode_cmd->pixel_format));
14342                 return -EINVAL;
14343         }
14344
14345         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14346         if (mode_cmd->offsets[0] != 0)
14347                 return -EINVAL;
14348
14349         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14350                                                mode_cmd->pixel_format,
14351                                                mode_cmd->modifier[0]);
14352         /* FIXME drm helper for size checks (especially planar formats)? */
14353         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14354                 return -EINVAL;
14355
14356         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14357         intel_fb->obj = obj;
14358         intel_fb->obj->framebuffer_references++;
14359
14360         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14361         if (ret) {
14362                 DRM_ERROR("framebuffer init failed %d\n", ret);
14363                 return ret;
14364         }
14365
14366         return 0;
14367 }
14368
14369 static struct drm_framebuffer *
14370 intel_user_framebuffer_create(struct drm_device *dev,
14371                               struct drm_file *filp,
14372                               struct drm_mode_fb_cmd2 *mode_cmd)
14373 {
14374         struct drm_i915_gem_object *obj;
14375
14376         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14377                                                 mode_cmd->handles[0]));
14378         if (&obj->base == NULL)
14379                 return ERR_PTR(-ENOENT);
14380
14381         return intel_framebuffer_create(dev, mode_cmd, obj);
14382 }
14383
14384 #ifndef CONFIG_DRM_FBDEV_EMULATION
14385 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14386 {
14387 }
14388 #endif
14389
14390 static const struct drm_mode_config_funcs intel_mode_funcs = {
14391         .fb_create = intel_user_framebuffer_create,
14392         .output_poll_changed = intel_fbdev_output_poll_changed,
14393         .atomic_check = intel_atomic_check,
14394         .atomic_commit = intel_atomic_commit,
14395         .atomic_state_alloc = intel_atomic_state_alloc,
14396         .atomic_state_clear = intel_atomic_state_clear,
14397 };
14398
14399 /* Set up chip specific display functions */
14400 static void intel_init_display(struct drm_device *dev)
14401 {
14402         struct drm_i915_private *dev_priv = dev->dev_private;
14403
14404         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14405                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14406         else if (IS_CHERRYVIEW(dev))
14407                 dev_priv->display.find_dpll = chv_find_best_dpll;
14408         else if (IS_VALLEYVIEW(dev))
14409                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14410         else if (IS_PINEVIEW(dev))
14411                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14412         else
14413                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14414
14415         if (INTEL_INFO(dev)->gen >= 9) {
14416                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14417                 dev_priv->display.get_initial_plane_config =
14418                         skylake_get_initial_plane_config;
14419                 dev_priv->display.crtc_compute_clock =
14420                         haswell_crtc_compute_clock;
14421                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14422                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14423                 dev_priv->display.update_primary_plane =
14424                         skylake_update_primary_plane;
14425         } else if (HAS_DDI(dev)) {
14426                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14427                 dev_priv->display.get_initial_plane_config =
14428                         ironlake_get_initial_plane_config;
14429                 dev_priv->display.crtc_compute_clock =
14430                         haswell_crtc_compute_clock;
14431                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14432                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14433                 dev_priv->display.update_primary_plane =
14434                         ironlake_update_primary_plane;
14435         } else if (HAS_PCH_SPLIT(dev)) {
14436                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14437                 dev_priv->display.get_initial_plane_config =
14438                         ironlake_get_initial_plane_config;
14439                 dev_priv->display.crtc_compute_clock =
14440                         ironlake_crtc_compute_clock;
14441                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14442                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14443                 dev_priv->display.update_primary_plane =
14444                         ironlake_update_primary_plane;
14445         } else if (IS_VALLEYVIEW(dev)) {
14446                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14447                 dev_priv->display.get_initial_plane_config =
14448                         i9xx_get_initial_plane_config;
14449                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14450                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14451                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14452                 dev_priv->display.update_primary_plane =
14453                         i9xx_update_primary_plane;
14454         } else {
14455                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14456                 dev_priv->display.get_initial_plane_config =
14457                         i9xx_get_initial_plane_config;
14458                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14459                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14460                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14461                 dev_priv->display.update_primary_plane =
14462                         i9xx_update_primary_plane;
14463         }
14464
14465         /* Returns the core display clock speed */
14466         if (IS_SKYLAKE(dev))
14467                 dev_priv->display.get_display_clock_speed =
14468                         skylake_get_display_clock_speed;
14469         else if (IS_BROXTON(dev))
14470                 dev_priv->display.get_display_clock_speed =
14471                         broxton_get_display_clock_speed;
14472         else if (IS_BROADWELL(dev))
14473                 dev_priv->display.get_display_clock_speed =
14474                         broadwell_get_display_clock_speed;
14475         else if (IS_HASWELL(dev))
14476                 dev_priv->display.get_display_clock_speed =
14477                         haswell_get_display_clock_speed;
14478         else if (IS_VALLEYVIEW(dev))
14479                 dev_priv->display.get_display_clock_speed =
14480                         valleyview_get_display_clock_speed;
14481         else if (IS_GEN5(dev))
14482                 dev_priv->display.get_display_clock_speed =
14483                         ilk_get_display_clock_speed;
14484         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14485                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14486                 dev_priv->display.get_display_clock_speed =
14487                         i945_get_display_clock_speed;
14488         else if (IS_GM45(dev))
14489                 dev_priv->display.get_display_clock_speed =
14490                         gm45_get_display_clock_speed;
14491         else if (IS_CRESTLINE(dev))
14492                 dev_priv->display.get_display_clock_speed =
14493                         i965gm_get_display_clock_speed;
14494         else if (IS_PINEVIEW(dev))
14495                 dev_priv->display.get_display_clock_speed =
14496                         pnv_get_display_clock_speed;
14497         else if (IS_G33(dev) || IS_G4X(dev))
14498                 dev_priv->display.get_display_clock_speed =
14499                         g33_get_display_clock_speed;
14500         else if (IS_I915G(dev))
14501                 dev_priv->display.get_display_clock_speed =
14502                         i915_get_display_clock_speed;
14503         else if (IS_I945GM(dev) || IS_845G(dev))
14504                 dev_priv->display.get_display_clock_speed =
14505                         i9xx_misc_get_display_clock_speed;
14506         else if (IS_PINEVIEW(dev))
14507                 dev_priv->display.get_display_clock_speed =
14508                         pnv_get_display_clock_speed;
14509         else if (IS_I915GM(dev))
14510                 dev_priv->display.get_display_clock_speed =
14511                         i915gm_get_display_clock_speed;
14512         else if (IS_I865G(dev))
14513                 dev_priv->display.get_display_clock_speed =
14514                         i865_get_display_clock_speed;
14515         else if (IS_I85X(dev))
14516                 dev_priv->display.get_display_clock_speed =
14517                         i85x_get_display_clock_speed;
14518         else { /* 830 */
14519                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14520                 dev_priv->display.get_display_clock_speed =
14521                         i830_get_display_clock_speed;
14522         }
14523
14524         if (IS_GEN5(dev)) {
14525                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14526         } else if (IS_GEN6(dev)) {
14527                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14528         } else if (IS_IVYBRIDGE(dev)) {
14529                 /* FIXME: detect B0+ stepping and use auto training */
14530                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14531         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14532                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14533                 if (IS_BROADWELL(dev)) {
14534                         dev_priv->display.modeset_commit_cdclk =
14535                                 broadwell_modeset_commit_cdclk;
14536                         dev_priv->display.modeset_calc_cdclk =
14537                                 broadwell_modeset_calc_cdclk;
14538                 }
14539         } else if (IS_VALLEYVIEW(dev)) {
14540                 dev_priv->display.modeset_commit_cdclk =
14541                         valleyview_modeset_commit_cdclk;
14542                 dev_priv->display.modeset_calc_cdclk =
14543                         valleyview_modeset_calc_cdclk;
14544         } else if (IS_BROXTON(dev)) {
14545                 dev_priv->display.modeset_commit_cdclk =
14546                         broxton_modeset_commit_cdclk;
14547                 dev_priv->display.modeset_calc_cdclk =
14548                         broxton_modeset_calc_cdclk;
14549         }
14550
14551         switch (INTEL_INFO(dev)->gen) {
14552         case 2:
14553                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14554                 break;
14555
14556         case 3:
14557                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14558                 break;
14559
14560         case 4:
14561         case 5:
14562                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14563                 break;
14564
14565         case 6:
14566                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14567                 break;
14568         case 7:
14569         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14570                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14571                 break;
14572         case 9:
14573                 /* Drop through - unsupported since execlist only. */
14574         default:
14575                 /* Default just returns -ENODEV to indicate unsupported */
14576                 dev_priv->display.queue_flip = intel_default_queue_flip;
14577         }
14578
14579         mutex_init(&dev_priv->pps_mutex);
14580 }
14581
14582 /*
14583  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14584  * resume, or other times.  This quirk makes sure that's the case for
14585  * affected systems.
14586  */
14587 static void quirk_pipea_force(struct drm_device *dev)
14588 {
14589         struct drm_i915_private *dev_priv = dev->dev_private;
14590
14591         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14592         DRM_INFO("applying pipe a force quirk\n");
14593 }
14594
14595 static void quirk_pipeb_force(struct drm_device *dev)
14596 {
14597         struct drm_i915_private *dev_priv = dev->dev_private;
14598
14599         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14600         DRM_INFO("applying pipe b force quirk\n");
14601 }
14602
14603 /*
14604  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14605  */
14606 static void quirk_ssc_force_disable(struct drm_device *dev)
14607 {
14608         struct drm_i915_private *dev_priv = dev->dev_private;
14609         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14610         DRM_INFO("applying lvds SSC disable quirk\n");
14611 }
14612
14613 /*
14614  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14615  * brightness value
14616  */
14617 static void quirk_invert_brightness(struct drm_device *dev)
14618 {
14619         struct drm_i915_private *dev_priv = dev->dev_private;
14620         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14621         DRM_INFO("applying inverted panel brightness quirk\n");
14622 }
14623
14624 /* Some VBT's incorrectly indicate no backlight is present */
14625 static void quirk_backlight_present(struct drm_device *dev)
14626 {
14627         struct drm_i915_private *dev_priv = dev->dev_private;
14628         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14629         DRM_INFO("applying backlight present quirk\n");
14630 }
14631
14632 struct intel_quirk {
14633         int device;
14634         int subsystem_vendor;
14635         int subsystem_device;
14636         void (*hook)(struct drm_device *dev);
14637 };
14638
14639 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14640 struct intel_dmi_quirk {
14641         void (*hook)(struct drm_device *dev);
14642         const struct dmi_system_id (*dmi_id_list)[];
14643 };
14644
14645 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14646 {
14647         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14648         return 1;
14649 }
14650
14651 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14652         {
14653                 .dmi_id_list = &(const struct dmi_system_id[]) {
14654                         {
14655                                 .callback = intel_dmi_reverse_brightness,
14656                                 .ident = "NCR Corporation",
14657                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14658                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14659                                 },
14660                         },
14661                         { }  /* terminating entry */
14662                 },
14663                 .hook = quirk_invert_brightness,
14664         },
14665 };
14666
14667 static struct intel_quirk intel_quirks[] = {
14668         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14669         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14670
14671         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14672         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14673
14674         /* 830 needs to leave pipe A & dpll A up */
14675         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14676
14677         /* 830 needs to leave pipe B & dpll B up */
14678         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14679
14680         /* Lenovo U160 cannot use SSC on LVDS */
14681         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14682
14683         /* Sony Vaio Y cannot use SSC on LVDS */
14684         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14685
14686         /* Acer Aspire 5734Z must invert backlight brightness */
14687         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14688
14689         /* Acer/eMachines G725 */
14690         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14691
14692         /* Acer/eMachines e725 */
14693         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14694
14695         /* Acer/Packard Bell NCL20 */
14696         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14697
14698         /* Acer Aspire 4736Z */
14699         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14700
14701         /* Acer Aspire 5336 */
14702         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14703
14704         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14705         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14706
14707         /* Acer C720 Chromebook (Core i3 4005U) */
14708         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14709
14710         /* Apple Macbook 2,1 (Core 2 T7400) */
14711         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14712
14713         /* Apple Macbook 4,1 */
14714         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14715
14716         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14717         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14718
14719         /* HP Chromebook 14 (Celeron 2955U) */
14720         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14721
14722         /* Dell Chromebook 11 */
14723         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14724
14725         /* Dell Chromebook 11 (2015 version) */
14726         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14727 };
14728
14729 static void intel_init_quirks(struct drm_device *dev)
14730 {
14731         struct pci_dev *d = dev->pdev;
14732         int i;
14733
14734         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14735                 struct intel_quirk *q = &intel_quirks[i];
14736
14737                 if (d->device == q->device &&
14738                     (d->subsystem_vendor == q->subsystem_vendor ||
14739                      q->subsystem_vendor == PCI_ANY_ID) &&
14740                     (d->subsystem_device == q->subsystem_device ||
14741                      q->subsystem_device == PCI_ANY_ID))
14742                         q->hook(dev);
14743         }
14744         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14745                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14746                         intel_dmi_quirks[i].hook(dev);
14747         }
14748 }
14749
14750 /* Disable the VGA plane that we never use */
14751 static void i915_disable_vga(struct drm_device *dev)
14752 {
14753         struct drm_i915_private *dev_priv = dev->dev_private;
14754         u8 sr1;
14755         u32 vga_reg = i915_vgacntrl_reg(dev);
14756
14757         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14758         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14759         outb(SR01, VGA_SR_INDEX);
14760         sr1 = inb(VGA_SR_DATA);
14761         outb(sr1 | 1<<5, VGA_SR_DATA);
14762         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14763         udelay(300);
14764
14765         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14766         POSTING_READ(vga_reg);
14767 }
14768
14769 void intel_modeset_init_hw(struct drm_device *dev)
14770 {
14771         intel_update_cdclk(dev);
14772         intel_prepare_ddi(dev);
14773         intel_init_clock_gating(dev);
14774         intel_enable_gt_powersave(dev);
14775 }
14776
14777 void intel_modeset_init(struct drm_device *dev)
14778 {
14779         struct drm_i915_private *dev_priv = dev->dev_private;
14780         int sprite, ret;
14781         enum pipe pipe;
14782         struct intel_crtc *crtc;
14783
14784         drm_mode_config_init(dev);
14785
14786         dev->mode_config.min_width = 0;
14787         dev->mode_config.min_height = 0;
14788
14789         dev->mode_config.preferred_depth = 24;
14790         dev->mode_config.prefer_shadow = 1;
14791
14792         dev->mode_config.allow_fb_modifiers = true;
14793
14794         dev->mode_config.funcs = &intel_mode_funcs;
14795
14796         intel_init_quirks(dev);
14797
14798         intel_init_pm(dev);
14799
14800         if (INTEL_INFO(dev)->num_pipes == 0)
14801                 return;
14802
14803         /*
14804          * There may be no VBT; and if the BIOS enabled SSC we can
14805          * just keep using it to avoid unnecessary flicker.  Whereas if the
14806          * BIOS isn't using it, don't assume it will work even if the VBT
14807          * indicates as much.
14808          */
14809         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14810                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14811                                             DREF_SSC1_ENABLE);
14812
14813                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14814                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14815                                      bios_lvds_use_ssc ? "en" : "dis",
14816                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14817                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14818                 }
14819         }
14820
14821         intel_init_display(dev);
14822         intel_init_audio(dev);
14823
14824         if (IS_GEN2(dev)) {
14825                 dev->mode_config.max_width = 2048;
14826                 dev->mode_config.max_height = 2048;
14827         } else if (IS_GEN3(dev)) {
14828                 dev->mode_config.max_width = 4096;
14829                 dev->mode_config.max_height = 4096;
14830         } else {
14831                 dev->mode_config.max_width = 8192;
14832                 dev->mode_config.max_height = 8192;
14833         }
14834
14835         if (IS_845G(dev) || IS_I865G(dev)) {
14836                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14837                 dev->mode_config.cursor_height = 1023;
14838         } else if (IS_GEN2(dev)) {
14839                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14840                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14841         } else {
14842                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14843                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14844         }
14845
14846         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14847
14848         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14849                       INTEL_INFO(dev)->num_pipes,
14850                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14851
14852         for_each_pipe(dev_priv, pipe) {
14853                 intel_crtc_init(dev, pipe);
14854                 for_each_sprite(dev_priv, pipe, sprite) {
14855                         ret = intel_plane_init(dev, pipe, sprite);
14856                         if (ret)
14857                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14858                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14859                 }
14860         }
14861
14862         intel_update_czclk(dev_priv);
14863         intel_update_cdclk(dev);
14864
14865         intel_shared_dpll_init(dev);
14866
14867         /* Just disable it once at startup */
14868         i915_disable_vga(dev);
14869         intel_setup_outputs(dev);
14870
14871         /* Just in case the BIOS is doing something questionable. */
14872         intel_fbc_disable(dev_priv);
14873
14874         drm_modeset_lock_all(dev);
14875         intel_modeset_setup_hw_state(dev);
14876         drm_modeset_unlock_all(dev);
14877
14878         for_each_intel_crtc(dev, crtc) {
14879                 struct intel_initial_plane_config plane_config = {};
14880
14881                 if (!crtc->active)
14882                         continue;
14883
14884                 /*
14885                  * Note that reserving the BIOS fb up front prevents us
14886                  * from stuffing other stolen allocations like the ring
14887                  * on top.  This prevents some ugliness at boot time, and
14888                  * can even allow for smooth boot transitions if the BIOS
14889                  * fb is large enough for the active pipe configuration.
14890                  */
14891                 dev_priv->display.get_initial_plane_config(crtc,
14892                                                            &plane_config);
14893
14894                 /*
14895                  * If the fb is shared between multiple heads, we'll
14896                  * just get the first one.
14897                  */
14898                 intel_find_initial_plane_obj(crtc, &plane_config);
14899         }
14900 }
14901
14902 static void intel_enable_pipe_a(struct drm_device *dev)
14903 {
14904         struct intel_connector *connector;
14905         struct drm_connector *crt = NULL;
14906         struct intel_load_detect_pipe load_detect_temp;
14907         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14908
14909         /* We can't just switch on the pipe A, we need to set things up with a
14910          * proper mode and output configuration. As a gross hack, enable pipe A
14911          * by enabling the load detect pipe once. */
14912         for_each_intel_connector(dev, connector) {
14913                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14914                         crt = &connector->base;
14915                         break;
14916                 }
14917         }
14918
14919         if (!crt)
14920                 return;
14921
14922         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14923                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14924 }
14925
14926 static bool
14927 intel_check_plane_mapping(struct intel_crtc *crtc)
14928 {
14929         struct drm_device *dev = crtc->base.dev;
14930         struct drm_i915_private *dev_priv = dev->dev_private;
14931         u32 val;
14932
14933         if (INTEL_INFO(dev)->num_pipes == 1)
14934                 return true;
14935
14936         val = I915_READ(DSPCNTR(!crtc->plane));
14937
14938         if ((val & DISPLAY_PLANE_ENABLE) &&
14939             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14940                 return false;
14941
14942         return true;
14943 }
14944
14945 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14946 {
14947         struct drm_device *dev = crtc->base.dev;
14948         struct intel_encoder *encoder;
14949
14950         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14951                 return true;
14952
14953         return false;
14954 }
14955
14956 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14957 {
14958         struct drm_device *dev = crtc->base.dev;
14959         struct drm_i915_private *dev_priv = dev->dev_private;
14960         u32 reg;
14961
14962         /* Clear any frame start delays used for debugging left by the BIOS */
14963         reg = PIPECONF(crtc->config->cpu_transcoder);
14964         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14965
14966         /* restore vblank interrupts to correct state */
14967         drm_crtc_vblank_reset(&crtc->base);
14968         if (crtc->active) {
14969                 struct intel_plane *plane;
14970
14971                 drm_crtc_vblank_on(&crtc->base);
14972
14973                 /* Disable everything but the primary plane */
14974                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14975                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14976                                 continue;
14977
14978                         plane->disable_plane(&plane->base, &crtc->base);
14979                 }
14980         }
14981
14982         /* We need to sanitize the plane -> pipe mapping first because this will
14983          * disable the crtc (and hence change the state) if it is wrong. Note
14984          * that gen4+ has a fixed plane -> pipe mapping.  */
14985         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14986                 bool plane;
14987
14988                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14989                               crtc->base.base.id);
14990
14991                 /* Pipe has the wrong plane attached and the plane is active.
14992                  * Temporarily change the plane mapping and disable everything
14993                  * ...  */
14994                 plane = crtc->plane;
14995                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14996                 crtc->plane = !plane;
14997                 intel_crtc_disable_noatomic(&crtc->base);
14998                 crtc->plane = plane;
14999         }
15000
15001         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15002             crtc->pipe == PIPE_A && !crtc->active) {
15003                 /* BIOS forgot to enable pipe A, this mostly happens after
15004                  * resume. Force-enable the pipe to fix this, the update_dpms
15005                  * call below we restore the pipe to the right state, but leave
15006                  * the required bits on. */
15007                 intel_enable_pipe_a(dev);
15008         }
15009
15010         /* Adjust the state of the output pipe according to whether we
15011          * have active connectors/encoders. */
15012         if (!intel_crtc_has_encoders(crtc))
15013                 intel_crtc_disable_noatomic(&crtc->base);
15014
15015         if (crtc->active != crtc->base.state->active) {
15016                 struct intel_encoder *encoder;
15017
15018                 /* This can happen either due to bugs in the get_hw_state
15019                  * functions or because of calls to intel_crtc_disable_noatomic,
15020                  * or because the pipe is force-enabled due to the
15021                  * pipe A quirk. */
15022                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15023                               crtc->base.base.id,
15024                               crtc->base.state->enable ? "enabled" : "disabled",
15025                               crtc->active ? "enabled" : "disabled");
15026
15027                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15028                 crtc->base.state->active = crtc->active;
15029                 crtc->base.enabled = crtc->active;
15030
15031                 /* Because we only establish the connector -> encoder ->
15032                  * crtc links if something is active, this means the
15033                  * crtc is now deactivated. Break the links. connector
15034                  * -> encoder links are only establish when things are
15035                  *  actually up, hence no need to break them. */
15036                 WARN_ON(crtc->active);
15037
15038                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15039                         encoder->base.crtc = NULL;
15040         }
15041
15042         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15043                 /*
15044                  * We start out with underrun reporting disabled to avoid races.
15045                  * For correct bookkeeping mark this on active crtcs.
15046                  *
15047                  * Also on gmch platforms we dont have any hardware bits to
15048                  * disable the underrun reporting. Which means we need to start
15049                  * out with underrun reporting disabled also on inactive pipes,
15050                  * since otherwise we'll complain about the garbage we read when
15051                  * e.g. coming up after runtime pm.
15052                  *
15053                  * No protection against concurrent access is required - at
15054                  * worst a fifo underrun happens which also sets this to false.
15055                  */
15056                 crtc->cpu_fifo_underrun_disabled = true;
15057                 crtc->pch_fifo_underrun_disabled = true;
15058         }
15059 }
15060
15061 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15062 {
15063         struct intel_connector *connector;
15064         struct drm_device *dev = encoder->base.dev;
15065         bool active = false;
15066
15067         /* We need to check both for a crtc link (meaning that the
15068          * encoder is active and trying to read from a pipe) and the
15069          * pipe itself being active. */
15070         bool has_active_crtc = encoder->base.crtc &&
15071                 to_intel_crtc(encoder->base.crtc)->active;
15072
15073         for_each_intel_connector(dev, connector) {
15074                 if (connector->base.encoder != &encoder->base)
15075                         continue;
15076
15077                 active = true;
15078                 break;
15079         }
15080
15081         if (active && !has_active_crtc) {
15082                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15083                               encoder->base.base.id,
15084                               encoder->base.name);
15085
15086                 /* Connector is active, but has no active pipe. This is
15087                  * fallout from our resume register restoring. Disable
15088                  * the encoder manually again. */
15089                 if (encoder->base.crtc) {
15090                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15091                                       encoder->base.base.id,
15092                                       encoder->base.name);
15093                         encoder->disable(encoder);
15094                         if (encoder->post_disable)
15095                                 encoder->post_disable(encoder);
15096                 }
15097                 encoder->base.crtc = NULL;
15098
15099                 /* Inconsistent output/port/pipe state happens presumably due to
15100                  * a bug in one of the get_hw_state functions. Or someplace else
15101                  * in our code, like the register restore mess on resume. Clamp
15102                  * things to off as a safer default. */
15103                 for_each_intel_connector(dev, connector) {
15104                         if (connector->encoder != encoder)
15105                                 continue;
15106                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15107                         connector->base.encoder = NULL;
15108                 }
15109         }
15110         /* Enabled encoders without active connectors will be fixed in
15111          * the crtc fixup. */
15112 }
15113
15114 void i915_redisable_vga_power_on(struct drm_device *dev)
15115 {
15116         struct drm_i915_private *dev_priv = dev->dev_private;
15117         u32 vga_reg = i915_vgacntrl_reg(dev);
15118
15119         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15120                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15121                 i915_disable_vga(dev);
15122         }
15123 }
15124
15125 void i915_redisable_vga(struct drm_device *dev)
15126 {
15127         struct drm_i915_private *dev_priv = dev->dev_private;
15128
15129         /* This function can be called both from intel_modeset_setup_hw_state or
15130          * at a very early point in our resume sequence, where the power well
15131          * structures are not yet restored. Since this function is at a very
15132          * paranoid "someone might have enabled VGA while we were not looking"
15133          * level, just check if the power well is enabled instead of trying to
15134          * follow the "don't touch the power well if we don't need it" policy
15135          * the rest of the driver uses. */
15136         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15137                 return;
15138
15139         i915_redisable_vga_power_on(dev);
15140 }
15141
15142 static bool primary_get_hw_state(struct intel_plane *plane)
15143 {
15144         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15145
15146         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15147 }
15148
15149 /* FIXME read out full plane state for all planes */
15150 static void readout_plane_state(struct intel_crtc *crtc)
15151 {
15152         struct drm_plane *primary = crtc->base.primary;
15153         struct intel_plane_state *plane_state =
15154                 to_intel_plane_state(primary->state);
15155
15156         plane_state->visible =
15157                 primary_get_hw_state(to_intel_plane(primary));
15158
15159         if (plane_state->visible)
15160                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15161 }
15162
15163 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15164 {
15165         struct drm_i915_private *dev_priv = dev->dev_private;
15166         enum pipe pipe;
15167         struct intel_crtc *crtc;
15168         struct intel_encoder *encoder;
15169         struct intel_connector *connector;
15170         int i;
15171
15172         for_each_intel_crtc(dev, crtc) {
15173                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15174                 memset(crtc->config, 0, sizeof(*crtc->config));
15175                 crtc->config->base.crtc = &crtc->base;
15176
15177                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15178                                                                  crtc->config);
15179
15180                 crtc->base.state->active = crtc->active;
15181                 crtc->base.enabled = crtc->active;
15182
15183                 readout_plane_state(crtc);
15184
15185                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15186                               crtc->base.base.id,
15187                               crtc->active ? "enabled" : "disabled");
15188         }
15189
15190         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15191                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15192
15193                 pll->on = pll->get_hw_state(dev_priv, pll,
15194                                             &pll->config.hw_state);
15195                 pll->active = 0;
15196                 pll->config.crtc_mask = 0;
15197                 for_each_intel_crtc(dev, crtc) {
15198                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15199                                 pll->active++;
15200                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15201                         }
15202                 }
15203
15204                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15205                               pll->name, pll->config.crtc_mask, pll->on);
15206
15207                 if (pll->config.crtc_mask)
15208                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15209         }
15210
15211         for_each_intel_encoder(dev, encoder) {
15212                 pipe = 0;
15213
15214                 if (encoder->get_hw_state(encoder, &pipe)) {
15215                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15216                         encoder->base.crtc = &crtc->base;
15217                         encoder->get_config(encoder, crtc->config);
15218                 } else {
15219                         encoder->base.crtc = NULL;
15220                 }
15221
15222                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15223                               encoder->base.base.id,
15224                               encoder->base.name,
15225                               encoder->base.crtc ? "enabled" : "disabled",
15226                               pipe_name(pipe));
15227         }
15228
15229         for_each_intel_connector(dev, connector) {
15230                 if (connector->get_hw_state(connector)) {
15231                         connector->base.dpms = DRM_MODE_DPMS_ON;
15232                         connector->base.encoder = &connector->encoder->base;
15233                 } else {
15234                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15235                         connector->base.encoder = NULL;
15236                 }
15237                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15238                               connector->base.base.id,
15239                               connector->base.name,
15240                               connector->base.encoder ? "enabled" : "disabled");
15241         }
15242
15243         for_each_intel_crtc(dev, crtc) {
15244                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15245
15246                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15247                 if (crtc->base.state->active) {
15248                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15249                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15250                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15251
15252                         /*
15253                          * The initial mode needs to be set in order to keep
15254                          * the atomic core happy. It wants a valid mode if the
15255                          * crtc's enabled, so we do the above call.
15256                          *
15257                          * At this point some state updated by the connectors
15258                          * in their ->detect() callback has not run yet, so
15259                          * no recalculation can be done yet.
15260                          *
15261                          * Even if we could do a recalculation and modeset
15262                          * right now it would cause a double modeset if
15263                          * fbdev or userspace chooses a different initial mode.
15264                          *
15265                          * If that happens, someone indicated they wanted a
15266                          * mode change, which means it's safe to do a full
15267                          * recalculation.
15268                          */
15269                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15270
15271                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15272                         update_scanline_offset(crtc);
15273                 }
15274         }
15275 }
15276
15277 /* Scan out the current hw modeset state,
15278  * and sanitizes it to the current state
15279  */
15280 static void
15281 intel_modeset_setup_hw_state(struct drm_device *dev)
15282 {
15283         struct drm_i915_private *dev_priv = dev->dev_private;
15284         enum pipe pipe;
15285         struct intel_crtc *crtc;
15286         struct intel_encoder *encoder;
15287         int i;
15288
15289         intel_modeset_readout_hw_state(dev);
15290
15291         /* HW state is read out, now we need to sanitize this mess. */
15292         for_each_intel_encoder(dev, encoder) {
15293                 intel_sanitize_encoder(encoder);
15294         }
15295
15296         for_each_pipe(dev_priv, pipe) {
15297                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15298                 intel_sanitize_crtc(crtc);
15299                 intel_dump_pipe_config(crtc, crtc->config,
15300                                        "[setup_hw_state]");
15301         }
15302
15303         intel_modeset_update_connector_atomic_state(dev);
15304
15305         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15306                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15307
15308                 if (!pll->on || pll->active)
15309                         continue;
15310
15311                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15312
15313                 pll->disable(dev_priv, pll);
15314                 pll->on = false;
15315         }
15316
15317         if (IS_VALLEYVIEW(dev))
15318                 vlv_wm_get_hw_state(dev);
15319         else if (IS_GEN9(dev))
15320                 skl_wm_get_hw_state(dev);
15321         else if (HAS_PCH_SPLIT(dev))
15322                 ilk_wm_get_hw_state(dev);
15323
15324         for_each_intel_crtc(dev, crtc) {
15325                 unsigned long put_domains;
15326
15327                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15328                 if (WARN_ON(put_domains))
15329                         modeset_put_power_domains(dev_priv, put_domains);
15330         }
15331         intel_display_set_init_power(dev_priv, false);
15332 }
15333
15334 void intel_display_resume(struct drm_device *dev)
15335 {
15336         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15337         struct intel_connector *conn;
15338         struct intel_plane *plane;
15339         struct drm_crtc *crtc;
15340         int ret;
15341
15342         if (!state)
15343                 return;
15344
15345         state->acquire_ctx = dev->mode_config.acquire_ctx;
15346
15347         /* preserve complete old state, including dpll */
15348         intel_atomic_get_shared_dpll_state(state);
15349
15350         for_each_crtc(dev, crtc) {
15351                 struct drm_crtc_state *crtc_state =
15352                         drm_atomic_get_crtc_state(state, crtc);
15353
15354                 ret = PTR_ERR_OR_ZERO(crtc_state);
15355                 if (ret)
15356                         goto err;
15357
15358                 /* force a restore */
15359                 crtc_state->mode_changed = true;
15360         }
15361
15362         for_each_intel_plane(dev, plane) {
15363                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15364                 if (ret)
15365                         goto err;
15366         }
15367
15368         for_each_intel_connector(dev, conn) {
15369                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15370                 if (ret)
15371                         goto err;
15372         }
15373
15374         intel_modeset_setup_hw_state(dev);
15375
15376         i915_redisable_vga(dev);
15377         ret = drm_atomic_commit(state);
15378         if (!ret)
15379                 return;
15380
15381 err:
15382         DRM_ERROR("Restoring old state failed with %i\n", ret);
15383         drm_atomic_state_free(state);
15384 }
15385
15386 void intel_modeset_gem_init(struct drm_device *dev)
15387 {
15388         struct drm_crtc *c;
15389         struct drm_i915_gem_object *obj;
15390         int ret;
15391
15392         mutex_lock(&dev->struct_mutex);
15393         intel_init_gt_powersave(dev);
15394         mutex_unlock(&dev->struct_mutex);
15395
15396         intel_modeset_init_hw(dev);
15397
15398         intel_setup_overlay(dev);
15399
15400         /*
15401          * Make sure any fbs we allocated at startup are properly
15402          * pinned & fenced.  When we do the allocation it's too early
15403          * for this.
15404          */
15405         for_each_crtc(dev, c) {
15406                 obj = intel_fb_obj(c->primary->fb);
15407                 if (obj == NULL)
15408                         continue;
15409
15410                 mutex_lock(&dev->struct_mutex);
15411                 ret = intel_pin_and_fence_fb_obj(c->primary,
15412                                                  c->primary->fb,
15413                                                  c->primary->state,
15414                                                  NULL, NULL);
15415                 mutex_unlock(&dev->struct_mutex);
15416                 if (ret) {
15417                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15418                                   to_intel_crtc(c)->pipe);
15419                         drm_framebuffer_unreference(c->primary->fb);
15420                         c->primary->fb = NULL;
15421                         c->primary->crtc = c->primary->state->crtc = NULL;
15422                         update_state_fb(c->primary);
15423                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15424                 }
15425         }
15426
15427         intel_backlight_register(dev);
15428 }
15429
15430 void intel_connector_unregister(struct intel_connector *intel_connector)
15431 {
15432         struct drm_connector *connector = &intel_connector->base;
15433
15434         intel_panel_destroy_backlight(connector);
15435         drm_connector_unregister(connector);
15436 }
15437
15438 void intel_modeset_cleanup(struct drm_device *dev)
15439 {
15440         struct drm_i915_private *dev_priv = dev->dev_private;
15441         struct drm_connector *connector;
15442
15443         intel_disable_gt_powersave(dev);
15444
15445         intel_backlight_unregister(dev);
15446
15447         /*
15448          * Interrupts and polling as the first thing to avoid creating havoc.
15449          * Too much stuff here (turning of connectors, ...) would
15450          * experience fancy races otherwise.
15451          */
15452         intel_irq_uninstall(dev_priv);
15453
15454         /*
15455          * Due to the hpd irq storm handling the hotplug work can re-arm the
15456          * poll handlers. Hence disable polling after hpd handling is shut down.
15457          */
15458         drm_kms_helper_poll_fini(dev);
15459
15460         intel_unregister_dsm_handler();
15461
15462         intel_fbc_disable(dev_priv);
15463
15464         /* flush any delayed tasks or pending work */
15465         flush_scheduled_work();
15466
15467         /* destroy the backlight and sysfs files before encoders/connectors */
15468         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15469                 struct intel_connector *intel_connector;
15470
15471                 intel_connector = to_intel_connector(connector);
15472                 intel_connector->unregister(intel_connector);
15473         }
15474
15475         drm_mode_config_cleanup(dev);
15476
15477         intel_cleanup_overlay(dev);
15478
15479         mutex_lock(&dev->struct_mutex);
15480         intel_cleanup_gt_powersave(dev);
15481         mutex_unlock(&dev->struct_mutex);
15482 }
15483
15484 /*
15485  * Return which encoder is currently attached for connector.
15486  */
15487 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15488 {
15489         return &intel_attached_encoder(connector)->base;
15490 }
15491
15492 void intel_connector_attach_encoder(struct intel_connector *connector,
15493                                     struct intel_encoder *encoder)
15494 {
15495         connector->encoder = encoder;
15496         drm_mode_connector_attach_encoder(&connector->base,
15497                                           &encoder->base);
15498 }
15499
15500 /*
15501  * set vga decode state - true == enable VGA decode
15502  */
15503 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15504 {
15505         struct drm_i915_private *dev_priv = dev->dev_private;
15506         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15507         u16 gmch_ctrl;
15508
15509         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15510                 DRM_ERROR("failed to read control word\n");
15511                 return -EIO;
15512         }
15513
15514         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15515                 return 0;
15516
15517         if (state)
15518                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15519         else
15520                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15521
15522         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15523                 DRM_ERROR("failed to write control word\n");
15524                 return -EIO;
15525         }
15526
15527         return 0;
15528 }
15529
15530 struct intel_display_error_state {
15531
15532         u32 power_well_driver;
15533
15534         int num_transcoders;
15535
15536         struct intel_cursor_error_state {
15537                 u32 control;
15538                 u32 position;
15539                 u32 base;
15540                 u32 size;
15541         } cursor[I915_MAX_PIPES];
15542
15543         struct intel_pipe_error_state {
15544                 bool power_domain_on;
15545                 u32 source;
15546                 u32 stat;
15547         } pipe[I915_MAX_PIPES];
15548
15549         struct intel_plane_error_state {
15550                 u32 control;
15551                 u32 stride;
15552                 u32 size;
15553                 u32 pos;
15554                 u32 addr;
15555                 u32 surface;
15556                 u32 tile_offset;
15557         } plane[I915_MAX_PIPES];
15558
15559         struct intel_transcoder_error_state {
15560                 bool power_domain_on;
15561                 enum transcoder cpu_transcoder;
15562
15563                 u32 conf;
15564
15565                 u32 htotal;
15566                 u32 hblank;
15567                 u32 hsync;
15568                 u32 vtotal;
15569                 u32 vblank;
15570                 u32 vsync;
15571         } transcoder[4];
15572 };
15573
15574 struct intel_display_error_state *
15575 intel_display_capture_error_state(struct drm_device *dev)
15576 {
15577         struct drm_i915_private *dev_priv = dev->dev_private;
15578         struct intel_display_error_state *error;
15579         int transcoders[] = {
15580                 TRANSCODER_A,
15581                 TRANSCODER_B,
15582                 TRANSCODER_C,
15583                 TRANSCODER_EDP,
15584         };
15585         int i;
15586
15587         if (INTEL_INFO(dev)->num_pipes == 0)
15588                 return NULL;
15589
15590         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15591         if (error == NULL)
15592                 return NULL;
15593
15594         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15595                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15596
15597         for_each_pipe(dev_priv, i) {
15598                 error->pipe[i].power_domain_on =
15599                         __intel_display_power_is_enabled(dev_priv,
15600                                                          POWER_DOMAIN_PIPE(i));
15601                 if (!error->pipe[i].power_domain_on)
15602                         continue;
15603
15604                 error->cursor[i].control = I915_READ(CURCNTR(i));
15605                 error->cursor[i].position = I915_READ(CURPOS(i));
15606                 error->cursor[i].base = I915_READ(CURBASE(i));
15607
15608                 error->plane[i].control = I915_READ(DSPCNTR(i));
15609                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15610                 if (INTEL_INFO(dev)->gen <= 3) {
15611                         error->plane[i].size = I915_READ(DSPSIZE(i));
15612                         error->plane[i].pos = I915_READ(DSPPOS(i));
15613                 }
15614                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15615                         error->plane[i].addr = I915_READ(DSPADDR(i));
15616                 if (INTEL_INFO(dev)->gen >= 4) {
15617                         error->plane[i].surface = I915_READ(DSPSURF(i));
15618                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15619                 }
15620
15621                 error->pipe[i].source = I915_READ(PIPESRC(i));
15622
15623                 if (HAS_GMCH_DISPLAY(dev))
15624                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15625         }
15626
15627         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15628         if (HAS_DDI(dev_priv->dev))
15629                 error->num_transcoders++; /* Account for eDP. */
15630
15631         for (i = 0; i < error->num_transcoders; i++) {
15632                 enum transcoder cpu_transcoder = transcoders[i];
15633
15634                 error->transcoder[i].power_domain_on =
15635                         __intel_display_power_is_enabled(dev_priv,
15636                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15637                 if (!error->transcoder[i].power_domain_on)
15638                         continue;
15639
15640                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15641
15642                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15643                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15644                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15645                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15646                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15647                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15648                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15649         }
15650
15651         return error;
15652 }
15653
15654 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15655
15656 void
15657 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15658                                 struct drm_device *dev,
15659                                 struct intel_display_error_state *error)
15660 {
15661         struct drm_i915_private *dev_priv = dev->dev_private;
15662         int i;
15663
15664         if (!error)
15665                 return;
15666
15667         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15668         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15669                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15670                            error->power_well_driver);
15671         for_each_pipe(dev_priv, i) {
15672                 err_printf(m, "Pipe [%d]:\n", i);
15673                 err_printf(m, "  Power: %s\n",
15674                            error->pipe[i].power_domain_on ? "on" : "off");
15675                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15676                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15677
15678                 err_printf(m, "Plane [%d]:\n", i);
15679                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15680                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15681                 if (INTEL_INFO(dev)->gen <= 3) {
15682                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15683                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15684                 }
15685                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15686                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15687                 if (INTEL_INFO(dev)->gen >= 4) {
15688                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15689                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15690                 }
15691
15692                 err_printf(m, "Cursor [%d]:\n", i);
15693                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15694                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15695                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15696         }
15697
15698         for (i = 0; i < error->num_transcoders; i++) {
15699                 err_printf(m, "CPU transcoder: %c\n",
15700                            transcoder_name(error->transcoder[i].cpu_transcoder));
15701                 err_printf(m, "  Power: %s\n",
15702                            error->transcoder[i].power_domain_on ? "on" : "off");
15703                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15704                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15705                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15706                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15707                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15708                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15709                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15710         }
15711 }
15712
15713 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15714 {
15715         struct intel_crtc *crtc;
15716
15717         for_each_intel_crtc(dev, crtc) {
15718                 struct intel_unpin_work *work;
15719
15720                 spin_lock_irq(&dev->event_lock);
15721
15722                 work = crtc->unpin_work;
15723
15724                 if (work && work->event &&
15725                     work->event->base.file_priv == file) {
15726                         kfree(work->event);
15727                         work->event = NULL;
15728                 }
15729
15730                 spin_unlock_irq(&dev->event_lock);
15731         }
15732 }