drivers/gpu/drm/i915/intel_display.h

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29 #include <drm/i915_drm.h>
  30
  31 struct drm_i915_private;
  32 struct intel_plane_state;
  33
  34 enum i915_gpio {
  35         GPIOA,
  36         GPIOB,
  37         GPIOC,
  38         GPIOD,
  39         GPIOE,
  40         GPIOF,
  41         GPIOG,
  42         GPIOH,
  43         __GPIOI_UNUSED,
  44         GPIOJ,
  45         GPIOK,
  46         GPIOL,
  47         GPIOM,
  48 };
  49
  50 /*
  51  * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
  52  * rest have consecutive values and match the enum values of transcoders
  53  * with a 1:1 transcoder -> pipe mapping.
  54  */
  55 enum pipe {
  56         INVALID_PIPE = -1,
  57
  58         PIPE_A = 0,
  59         PIPE_B,
  60         PIPE_C,
  61         _PIPE_EDP,
  62
  63         I915_MAX_PIPES = _PIPE_EDP
  64 };
  65
  66 #define pipe_name(p) ((p) + 'A')
  67
  68 enum transcoder {
  69         /*
  70          * The following transcoders have a 1:1 transcoder -> pipe mapping,
  71          * keep their values fixed: the code assumes that TRANSCODER_A=0, the
  72          * rest have consecutive values and match the enum values of the pipes
  73          * they map to.
  74          */
  75         TRANSCODER_A = PIPE_A,
  76         TRANSCODER_B = PIPE_B,
  77         TRANSCODER_C = PIPE_C,
  78
  79         /*
  80          * The following transcoders can map to any pipe, their enum value
  81          * doesn't need to stay fixed.
  82          */
  83         TRANSCODER_EDP,
  84         TRANSCODER_DSI_0,
  85         TRANSCODER_DSI_1,
  86         TRANSCODER_DSI_A = TRANSCODER_DSI_0,    /* legacy DSI */
  87         TRANSCODER_DSI_C = TRANSCODER_DSI_1,    /* legacy DSI */
  88
  89         I915_MAX_TRANSCODERS
  90 };
  91
  92 static inline const char *transcoder_name(enum transcoder transcoder)
  93 {
  94         switch (transcoder) {
  95         case TRANSCODER_A:
  96                 return "A";
  97         case TRANSCODER_B:
  98                 return "B";
  99         case TRANSCODER_C:
 100                 return "C";
 101         case TRANSCODER_EDP:
 102                 return "EDP";
 103         case TRANSCODER_DSI_A:
 104                 return "DSI A";
 105         case TRANSCODER_DSI_C:
 106                 return "DSI C";
 107         default:
 108                 return "<invalid>";
 109         }
 110 }
 111
 112 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 113 {
 114         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 115 }
 116
 117 /*
 118  * Global legacy plane identifier. Valid only for primary/sprite
 119  * planes on pre-g4x, and only for primary planes on g4x-bdw.
 120  */
 121 enum i9xx_plane_id {
 122         PLANE_A,
 123         PLANE_B,
 124         PLANE_C,
 125 };
 126
 127 #define plane_name(p) ((p) + 'A')
 128 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 129
 130 /*
 131  * Per-pipe plane identifier.
 132  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 133  * number of planes per CRTC.  Not all platforms really have this many planes,
 134  * which means some arrays of size I915_MAX_PLANES may have unused entries
 135  * between the topmost sprite plane and the cursor plane.
 136  *
 137  * This is expected to be passed to various register macros
 138  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 139  */
 140 enum plane_id {
 141         PLANE_PRIMARY,
 142         PLANE_SPRITE0,
 143         PLANE_SPRITE1,
 144         PLANE_SPRITE2,
 145         PLANE_SPRITE3,
 146         PLANE_SPRITE4,
 147         PLANE_SPRITE5,
 148         PLANE_CURSOR,
 149
 150         I915_MAX_PLANES,
 151 };
 152
 153 #define for_each_plane_id_on_crtc(__crtc, __p) \
 154         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 155                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 156
 157 /*
 158  * Ports identifier referenced from other drivers.
 159  * Expected to remain stable over time
 160  */
 161 static inline const char *port_identifier(enum port port)
 162 {
 163         switch (port) {
 164         case PORT_A:
 165                 return "Port A";
 166         case PORT_B:
 167                 return "Port B";
 168         case PORT_C:
 169                 return "Port C";
 170         case PORT_D:
 171                 return "Port D";
 172         case PORT_E:
 173                 return "Port E";
 174         case PORT_F:
 175                 return "Port F";
 176         default:
 177                 return "<invalid>";
 178         }
 179 }
 180
 181 enum tc_port {
 182         PORT_TC_NONE = -1,
 183
 184         PORT_TC1 = 0,
 185         PORT_TC2,
 186         PORT_TC3,
 187         PORT_TC4,
 188
 189         I915_MAX_TC_PORTS
 190 };
 191
 192 enum tc_port_type {
 193         TC_PORT_UNKNOWN = 0,
 194         TC_PORT_TYPEC,
 195         TC_PORT_TBT,
 196         TC_PORT_LEGACY,
 197 };
 198
 199 enum dpio_channel {
 200         DPIO_CH0,
 201         DPIO_CH1
 202 };
 203
 204 enum dpio_phy {
 205         DPIO_PHY0,
 206         DPIO_PHY1,
 207         DPIO_PHY2,
 208 };
 209
 210 #define I915_NUM_PHYS_VLV 2
 211
 212 enum aux_ch {
 213         AUX_CH_A,
 214         AUX_CH_B,
 215         AUX_CH_C,
 216         AUX_CH_D,
 217         AUX_CH_E, /* ICL+ */
 218         AUX_CH_F,
 219 };
 220
 221 #define aux_ch_name(a) ((a) + 'A')
 222
 223 enum intel_display_power_domain {
 224         POWER_DOMAIN_DISPLAY_CORE,
 225         POWER_DOMAIN_PIPE_A,
 226         POWER_DOMAIN_PIPE_B,
 227         POWER_DOMAIN_PIPE_C,
 228         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 229         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 230         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 231         POWER_DOMAIN_TRANSCODER_A,
 232         POWER_DOMAIN_TRANSCODER_B,
 233         POWER_DOMAIN_TRANSCODER_C,
 234         POWER_DOMAIN_TRANSCODER_EDP,
 235         POWER_DOMAIN_TRANSCODER_EDP_VDSC,
 236         POWER_DOMAIN_TRANSCODER_DSI_A,
 237         POWER_DOMAIN_TRANSCODER_DSI_C,
 238         POWER_DOMAIN_PORT_DDI_A_LANES,
 239         POWER_DOMAIN_PORT_DDI_B_LANES,
 240         POWER_DOMAIN_PORT_DDI_C_LANES,
 241         POWER_DOMAIN_PORT_DDI_D_LANES,
 242         POWER_DOMAIN_PORT_DDI_E_LANES,
 243         POWER_DOMAIN_PORT_DDI_F_LANES,
 244         POWER_DOMAIN_PORT_DDI_A_IO,
 245         POWER_DOMAIN_PORT_DDI_B_IO,
 246         POWER_DOMAIN_PORT_DDI_C_IO,
 247         POWER_DOMAIN_PORT_DDI_D_IO,
 248         POWER_DOMAIN_PORT_DDI_E_IO,
 249         POWER_DOMAIN_PORT_DDI_F_IO,
 250         POWER_DOMAIN_PORT_DSI,
 251         POWER_DOMAIN_PORT_CRT,
 252         POWER_DOMAIN_PORT_OTHER,
 253         POWER_DOMAIN_VGA,
 254         POWER_DOMAIN_AUDIO,
 255         POWER_DOMAIN_AUX_A,
 256         POWER_DOMAIN_AUX_B,
 257         POWER_DOMAIN_AUX_C,
 258         POWER_DOMAIN_AUX_D,
 259         POWER_DOMAIN_AUX_E,
 260         POWER_DOMAIN_AUX_F,
 261         POWER_DOMAIN_AUX_IO_A,
 262         POWER_DOMAIN_AUX_TBT1,
 263         POWER_DOMAIN_AUX_TBT2,
 264         POWER_DOMAIN_AUX_TBT3,
 265         POWER_DOMAIN_AUX_TBT4,
 266         POWER_DOMAIN_GMBUS,
 267         POWER_DOMAIN_MODESET,
 268         POWER_DOMAIN_GT_IRQ,
 269         POWER_DOMAIN_INIT,
 270
 271         POWER_DOMAIN_NUM,
 272 };
 273
 274 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 275 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 276                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 277 #define POWER_DOMAIN_TRANSCODER(tran) \
 278         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 279          (tran) + POWER_DOMAIN_TRANSCODER_A)
 280
 281 /* Used by dp and fdi links */
 282 struct intel_link_m_n {
 283         u32 tu;
 284         u32 gmch_m;
 285         u32 gmch_n;
 286         u32 link_m;
 287         u32 link_n;
 288 };
 289
 290 #define for_each_pipe(__dev_priv, __p) \
 291         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 292
 293 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 294         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
 295                 for_each_if((__mask) & BIT(__p))
 296
 297 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 298         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 299                 for_each_if ((__mask) & (1 << (__t)))
 300
 301 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 302         for ((__p) = 0;                                                 \
 303              (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;       \
 304              (__p)++)
 305
 306 #define for_each_sprite(__dev_priv, __p, __s)                           \
 307         for ((__s) = 0;                                                 \
 308              (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];      \
 309              (__s)++)
 310
 311 #define for_each_port_masked(__port, __ports_mask) \
 312         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
 313                 for_each_if((__ports_mask) & BIT(__port))
 314
 315 #define for_each_crtc(dev, crtc) \
 316         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 317
 318 #define for_each_intel_plane(dev, intel_plane) \
 319         list_for_each_entry(intel_plane,                        \
 320                             &(dev)->mode_config.plane_list,     \
 321                             base.head)
 322
 323 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 324         list_for_each_entry(intel_plane,                                \
 325                             &(dev)->mode_config.plane_list,             \
 326                             base.head)                                  \
 327                 for_each_if((plane_mask) &                              \
 328                             drm_plane_mask(&intel_plane->base)))
 329
 330 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 331         list_for_each_entry(intel_plane,                                \
 332                             &(dev)->mode_config.plane_list,             \
 333                             base.head)                                  \
 334                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 335
 336 #define for_each_intel_crtc(dev, intel_crtc)                            \
 337         list_for_each_entry(intel_crtc,                                 \
 338                             &(dev)->mode_config.crtc_list,              \
 339                             base.head)
 340
 341 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 342         list_for_each_entry(intel_crtc,                                 \
 343                             &(dev)->mode_config.crtc_list,              \
 344                             base.head)                                  \
 345                 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
 346
 347 #define for_each_intel_encoder(dev, intel_encoder)              \
 348         list_for_each_entry(intel_encoder,                      \
 349                             &(dev)->mode_config.encoder_list,   \
 350                             base.head)
 351
 352 #define for_each_intel_dp(dev, intel_encoder)                   \
 353         for_each_intel_encoder(dev, intel_encoder)              \
 354                 for_each_if(intel_encoder_is_dp(intel_encoder))
 355
 356 #define for_each_intel_connector_iter(intel_connector, iter) \
 357         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 358
 359 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 360         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 361                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 362
 363 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 364         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 365                 for_each_if((intel_connector)->base.encoder == (__encoder))
 366
 367 #define for_each_power_domain(domain, mask)                             \
 368         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 369                 for_each_if(BIT_ULL(domain) & (mask))
 370
 371 #define for_each_power_well(__dev_priv, __power_well)                           \
 372         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
 373              (__power_well) - (__dev_priv)->power_domains.power_wells < \
 374                 (__dev_priv)->power_domains.power_well_count;           \
 375              (__power_well)++)
 376
 377 #define for_each_power_well_reverse(__dev_priv, __power_well)                   \
 378         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
 379                               (__dev_priv)->power_domains.power_well_count - 1; \
 380              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
 381              (__power_well)--)
 382
 383 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
 384         for_each_power_well(__dev_priv, __power_well)                           \
 385                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 386
 387 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
 388         for_each_power_well_reverse(__dev_priv, __power_well)                   \
 389                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 390
 391 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
 392         for ((__i) = 0; \
 393              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 394                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 395                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
 396              (__i)++) \
 397                 for_each_if(plane)
 398
 399 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 400         for ((__i) = 0; \
 401              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 402                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 403                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 404              (__i)++) \
 405                 for_each_if(plane)
 406
 407 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 408         for ((__i) = 0; \
 409              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 410                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 411                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 412              (__i)++) \
 413                 for_each_if(crtc)
 414
 415 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 416         for ((__i) = 0; \
 417              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 418                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 419                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 420                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 421              (__i)++) \
 422                 for_each_if(plane)
 423
 424 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 425         for ((__i) = 0; \
 426              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 427                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 428                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 429                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 430              (__i)++) \
 431                 for_each_if(crtc)
 432
 433 void intel_link_compute_m_n(u16 bpp, int nlanes,
 434                             int pixel_clock, int link_clock,
 435                             struct intel_link_m_n *m_n,
 436                             bool constant_n);
 437 bool is_ccs_modifier(u64 modifier);
 438 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 439 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 440                               u32 pixel_format, u64 modifier);
 441 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
 442
 443 #endif