drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include "intel_drv.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  45
  46 /* Compliance test status bits  */
  47 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  48 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  50 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51
  52 struct dp_link_dpll {
  53         int clock;
  54         struct dpll dpll;
  55 };
  56
  57 static const struct dp_link_dpll gen4_dpll[] = {
  58         { 162000,
  59                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  60         { 270000,
  61                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  62 };
  63
  64 static const struct dp_link_dpll pch_dpll[] = {
  65         { 162000,
  66                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  67         { 270000,
  68                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  69 };
  70
  71 static const struct dp_link_dpll vlv_dpll[] = {
  72         { 162000,
  73                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  74         { 270000,
  75                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  76 };
  77
  78 /*
  79  * CHV supports eDP 1.4 that have  more link rates.
  80  * Below only provides the fixed rate but exclude variable rate.
  81  */
  82 static const struct dp_link_dpll chv_dpll[] = {
  83         /*
  84          * CHV requires to program fractional division for m2.
  85          * m2 is stored in fixed point format using formula below
  86          * (m2_int << 22) | m2_fraction
  87          */
  88         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  89                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  90         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  92         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  94 };
  95
  96 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int skl_rates[] = { 162000, 216000, 270000,
  99                                   324000, 432000, 540000 };
 100 static const int default_rates[] = { 162000, 270000, 540000 };
 101
 102 /**
 103  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 104  * @intel_dp: DP struct
 105  *
 106  * If a CPU or PCH DP output is attached to an eDP panel, this function
 107  * will return true, and false otherwise.
 108  */
 109 static bool is_edp(struct intel_dp *intel_dp)
 110 {
 111         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 112
 113         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 114 }
 115
 116 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 117 {
 118         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 119
 120         return intel_dig_port->base.base.dev;
 121 }
 122
 123 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 124 {
 125         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 126 }
 127
 128 static void intel_dp_link_down(struct intel_dp *intel_dp);
 129 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 130 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 131 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 132 static void vlv_steal_power_sequencer(struct drm_device *dev,
 133                                       enum pipe pipe);
 134 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 135
 136 static int intel_dp_num_rates(u8 link_bw_code)
 137 {
 138         switch (link_bw_code) {
 139         default:
 140                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 141                      link_bw_code);
 142         case DP_LINK_BW_1_62:
 143                 return 1;
 144         case DP_LINK_BW_2_7:
 145                 return 2;
 146         case DP_LINK_BW_5_4:
 147                 return 3;
 148         }
 149 }
 150
 151 /* update sink rates from dpcd */
 152 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 153 {
 154         int i, num_rates;
 155
 156         num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 157
 158         for (i = 0; i < num_rates; i++)
 159                 intel_dp->sink_rates[i] = default_rates[i];
 160
 161         intel_dp->num_sink_rates = num_rates;
 162 }
 163
 164 /* Theoretical max between source and sink */
 165 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 166 {
 167         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 168 }
 169
 170 /* Theoretical max between source and sink */
 171 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 172 {
 173         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 174         int source_max = intel_dig_port->max_lanes;
 175         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 176
 177         return min(source_max, sink_max);
 178 }
 179
 180 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 181 {
 182         return intel_dp->max_link_lane_count;
 183 }
 184
 185 int
 186 intel_dp_link_required(int pixel_clock, int bpp)
 187 {
 188         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 189         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 190 }
 191
 192 int
 193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 194 {
 195         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 196          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 197          * is transmitted every LS_Clk per lane, there is no need to account for
 198          * the channel encoding that is done in the PHY layer here.
 199          */
 200
 201         return max_link_clock * max_lanes;
 202 }
 203
 204 static int
 205 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 206 {
 207         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 208         struct intel_encoder *encoder = &intel_dig_port->base;
 209         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 210         int max_dotclk = dev_priv->max_dotclk_freq;
 211         int ds_max_dotclk;
 212
 213         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 214
 215         if (type != DP_DS_PORT_TYPE_VGA)
 216                 return max_dotclk;
 217
 218         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 219                                                     intel_dp->downstream_ports);
 220
 221         if (ds_max_dotclk != 0)
 222                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 223
 224         return max_dotclk;
 225 }
 226
 227 static void
 228 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 229 {
 230         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 231         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 232         const int *source_rates;
 233         int size;
 234
 235         /* This should only be done once */
 236         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 237
 238         if (IS_GEN9_LP(dev_priv)) {
 239                 source_rates = bxt_rates;
 240                 size = ARRAY_SIZE(bxt_rates);
 241         } else if (IS_GEN9_BC(dev_priv)) {
 242                 source_rates = skl_rates;
 243                 size = ARRAY_SIZE(skl_rates);
 244         } else {
 245                 source_rates = default_rates;
 246                 size = ARRAY_SIZE(default_rates);
 247         }
 248
 249         /* This depends on the fact that 5.4 is last value in the array */
 250         if (!intel_dp_source_supports_hbr2(intel_dp))
 251                 size--;
 252
 253         intel_dp->source_rates = source_rates;
 254         intel_dp->num_source_rates = size;
 255 }
 256
 257 static int intersect_rates(const int *source_rates, int source_len,
 258                            const int *sink_rates, int sink_len,
 259                            int *common_rates)
 260 {
 261         int i = 0, j = 0, k = 0;
 262
 263         while (i < source_len && j < sink_len) {
 264                 if (source_rates[i] == sink_rates[j]) {
 265                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 266                                 return k;
 267                         common_rates[k] = source_rates[i];
 268                         ++k;
 269                         ++i;
 270                         ++j;
 271                 } else if (source_rates[i] < sink_rates[j]) {
 272                         ++i;
 273                 } else {
 274                         ++j;
 275                 }
 276         }
 277         return k;
 278 }
 279
 280 /* return index of rate in rates array, or -1 if not found */
 281 static int intel_dp_rate_index(const int *rates, int len, int rate)
 282 {
 283         int i;
 284
 285         for (i = 0; i < len; i++)
 286                 if (rate == rates[i])
 287                         return i;
 288
 289         return -1;
 290 }
 291
 292 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 293 {
 294         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 295
 296         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 297                                                      intel_dp->num_source_rates,
 298                                                      intel_dp->sink_rates,
 299                                                      intel_dp->num_sink_rates,
 300                                                      intel_dp->common_rates);
 301
 302         /* Paranoia, there should always be something in common. */
 303         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 304                 intel_dp->common_rates[0] = default_rates[0];
 305                 intel_dp->num_common_rates = 1;
 306         }
 307 }
 308
 309 /* get length of common rates potentially limited by max_rate */
 310 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 311                                           int max_rate)
 312 {
 313         const int *common_rates = intel_dp->common_rates;
 314         int i, common_len = intel_dp->num_common_rates;
 315
 316         /* Limit results by potentially reduced max rate */
 317         for (i = 0; i < common_len; i++) {
 318                 if (common_rates[common_len - i - 1] <= max_rate)
 319                         return common_len - i;
 320         }
 321
 322         return 0;
 323 }
 324
 325 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp)
 326 {
 327         /*
 328          * FIXME: we need to synchronize the current link parameters with
 329          * hardware readout. Currently fast link training doesn't work on
 330          * boot-up.
 331          */
 332         if (intel_dp->link_rate == 0 ||
 333             intel_dp->link_rate > intel_dp->max_link_rate)
 334                 return false;
 335
 336         if (intel_dp->lane_count == 0 ||
 337             intel_dp->lane_count > intel_dp_max_lane_count(intel_dp))
 338                 return false;
 339
 340         return true;
 341 }
 342
 343 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 344                                             int link_rate, uint8_t lane_count)
 345 {
 346         int index;
 347
 348         index = intel_dp_rate_index(intel_dp->common_rates,
 349                                     intel_dp->num_common_rates,
 350                                     link_rate);
 351         if (index > 0) {
 352                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 353                 intel_dp->max_link_lane_count = lane_count;
 354         } else if (lane_count > 1) {
 355                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 356                 intel_dp->max_link_lane_count = lane_count >> 1;
 357         } else {
 358                 DRM_ERROR("Link Training Unsuccessful\n");
 359                 return -1;
 360         }
 361
 362         return 0;
 363 }
 364
 365 static enum drm_mode_status
 366 intel_dp_mode_valid(struct drm_connector *connector,
 367                     struct drm_display_mode *mode)
 368 {
 369         struct intel_dp *intel_dp = intel_attached_dp(connector);
 370         struct intel_connector *intel_connector = to_intel_connector(connector);
 371         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 372         int target_clock = mode->clock;
 373         int max_rate, mode_rate, max_lanes, max_link_clock;
 374         int max_dotclk;
 375
 376         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 377
 378         if (is_edp(intel_dp) && fixed_mode) {
 379                 if (mode->hdisplay > fixed_mode->hdisplay)
 380                         return MODE_PANEL;
 381
 382                 if (mode->vdisplay > fixed_mode->vdisplay)
 383                         return MODE_PANEL;
 384
 385                 target_clock = fixed_mode->clock;
 386         }
 387
 388         max_link_clock = intel_dp_max_link_rate(intel_dp);
 389         max_lanes = intel_dp_max_lane_count(intel_dp);
 390
 391         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 392         mode_rate = intel_dp_link_required(target_clock, 18);
 393
 394         if (mode_rate > max_rate || target_clock > max_dotclk)
 395                 return MODE_CLOCK_HIGH;
 396
 397         if (mode->clock < 10000)
 398                 return MODE_CLOCK_LOW;
 399
 400         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 401                 return MODE_H_ILLEGAL;
 402
 403         return MODE_OK;
 404 }
 405
 406 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 407 {
 408         int     i;
 409         uint32_t v = 0;
 410
 411         if (src_bytes > 4)
 412                 src_bytes = 4;
 413         for (i = 0; i < src_bytes; i++)
 414                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 415         return v;
 416 }
 417
 418 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 419 {
 420         int i;
 421         if (dst_bytes > 4)
 422                 dst_bytes = 4;
 423         for (i = 0; i < dst_bytes; i++)
 424                 dst[i] = src >> ((3-i) * 8);
 425 }
 426
 427 static void
 428 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 429                                     struct intel_dp *intel_dp);
 430 static void
 431 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 432                                               struct intel_dp *intel_dp,
 433                                               bool force_disable_vdd);
 434 static void
 435 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 436
 437 static void pps_lock(struct intel_dp *intel_dp)
 438 {
 439         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 440         struct intel_encoder *encoder = &intel_dig_port->base;
 441         struct drm_device *dev = encoder->base.dev;
 442         struct drm_i915_private *dev_priv = to_i915(dev);
 443
 444         /*
 445          * See vlv_power_sequencer_reset() why we need
 446          * a power domain reference here.
 447          */
 448         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 449
 450         mutex_lock(&dev_priv->pps_mutex);
 451 }
 452
 453 static void pps_unlock(struct intel_dp *intel_dp)
 454 {
 455         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 456         struct intel_encoder *encoder = &intel_dig_port->base;
 457         struct drm_device *dev = encoder->base.dev;
 458         struct drm_i915_private *dev_priv = to_i915(dev);
 459
 460         mutex_unlock(&dev_priv->pps_mutex);
 461
 462         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 463 }
 464
 465 static void
 466 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 467 {
 468         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 469         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 470         enum pipe pipe = intel_dp->pps_pipe;
 471         bool pll_enabled, release_cl_override = false;
 472         enum dpio_phy phy = DPIO_PHY(pipe);
 473         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 474         uint32_t DP;
 475
 476         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 477                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 478                  pipe_name(pipe), port_name(intel_dig_port->port)))
 479                 return;
 480
 481         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 482                       pipe_name(pipe), port_name(intel_dig_port->port));
 483
 484         /* Preserve the BIOS-computed detected bit. This is
 485          * supposed to be read-only.
 486          */
 487         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 488         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 489         DP |= DP_PORT_WIDTH(1);
 490         DP |= DP_LINK_TRAIN_PAT_1;
 491
 492         if (IS_CHERRYVIEW(dev_priv))
 493                 DP |= DP_PIPE_SELECT_CHV(pipe);
 494         else if (pipe == PIPE_B)
 495                 DP |= DP_PIPEB_SELECT;
 496
 497         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 498
 499         /*
 500          * The DPLL for the pipe must be enabled for this to work.
 501          * So enable temporarily it if it's not already enabled.
 502          */
 503         if (!pll_enabled) {
 504                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 505                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 506
 507                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 508                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 509                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 510                                   pipe_name(pipe));
 511                         return;
 512                 }
 513         }
 514
 515         /*
 516          * Similar magic as in intel_dp_enable_port().
 517          * We _must_ do this port enable + disable trick
 518          * to make this power seqeuencer lock onto the port.
 519          * Otherwise even VDD force bit won't work.
 520          */
 521         I915_WRITE(intel_dp->output_reg, DP);
 522         POSTING_READ(intel_dp->output_reg);
 523
 524         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 525         POSTING_READ(intel_dp->output_reg);
 526
 527         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 528         POSTING_READ(intel_dp->output_reg);
 529
 530         if (!pll_enabled) {
 531                 vlv_force_pll_off(dev_priv, pipe);
 532
 533                 if (release_cl_override)
 534                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 535         }
 536 }
 537
 538 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 539 {
 540         struct intel_encoder *encoder;
 541         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 542
 543         /*
 544          * We don't have power sequencer currently.
 545          * Pick one that's not used by other ports.
 546          */
 547         for_each_intel_encoder(&dev_priv->drm, encoder) {
 548                 struct intel_dp *intel_dp;
 549
 550                 if (encoder->type != INTEL_OUTPUT_DP &&
 551                     encoder->type != INTEL_OUTPUT_EDP)
 552                         continue;
 553
 554                 intel_dp = enc_to_intel_dp(&encoder->base);
 555
 556                 if (encoder->type == INTEL_OUTPUT_EDP) {
 557                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 558                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 559
 560                         if (intel_dp->pps_pipe != INVALID_PIPE)
 561                                 pipes &= ~(1 << intel_dp->pps_pipe);
 562                 } else {
 563                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 564
 565                         if (intel_dp->active_pipe != INVALID_PIPE)
 566                                 pipes &= ~(1 << intel_dp->active_pipe);
 567                 }
 568         }
 569
 570         if (pipes == 0)
 571                 return INVALID_PIPE;
 572
 573         return ffs(pipes) - 1;
 574 }
 575
 576 static enum pipe
 577 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 578 {
 579         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 580         struct drm_device *dev = intel_dig_port->base.base.dev;
 581         struct drm_i915_private *dev_priv = to_i915(dev);
 582         enum pipe pipe;
 583
 584         lockdep_assert_held(&dev_priv->pps_mutex);
 585
 586         /* We should never land here with regular DP ports */
 587         WARN_ON(!is_edp(intel_dp));
 588
 589         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 590                 intel_dp->active_pipe != intel_dp->pps_pipe);
 591
 592         if (intel_dp->pps_pipe != INVALID_PIPE)
 593                 return intel_dp->pps_pipe;
 594
 595         pipe = vlv_find_free_pps(dev_priv);
 596
 597         /*
 598          * Didn't find one. This should not happen since there
 599          * are two power sequencers and up to two eDP ports.
 600          */
 601         if (WARN_ON(pipe == INVALID_PIPE))
 602                 pipe = PIPE_A;
 603
 604         vlv_steal_power_sequencer(dev, pipe);
 605         intel_dp->pps_pipe = pipe;
 606
 607         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 608                       pipe_name(intel_dp->pps_pipe),
 609                       port_name(intel_dig_port->port));
 610
 611         /* init power sequencer on this pipe and port */
 612         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 613         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
 614
 615         /*
 616          * Even vdd force doesn't work until we've made
 617          * the power sequencer lock in on the port.
 618          */
 619         vlv_power_sequencer_kick(intel_dp);
 620
 621         return intel_dp->pps_pipe;
 622 }
 623
 624 static int
 625 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 626 {
 627         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 628         struct drm_device *dev = intel_dig_port->base.base.dev;
 629         struct drm_i915_private *dev_priv = to_i915(dev);
 630
 631         lockdep_assert_held(&dev_priv->pps_mutex);
 632
 633         /* We should never land here with regular DP ports */
 634         WARN_ON(!is_edp(intel_dp));
 635
 636         /*
 637          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 638          * mapping needs to be retrieved from VBT, for now just hard-code to
 639          * use instance #0 always.
 640          */
 641         if (!intel_dp->pps_reset)
 642                 return 0;
 643
 644         intel_dp->pps_reset = false;
 645
 646         /*
 647          * Only the HW needs to be reprogrammed, the SW state is fixed and
 648          * has been setup during connector init.
 649          */
 650         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 651
 652         return 0;
 653 }
 654
 655 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 656                                enum pipe pipe);
 657
 658 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 659                                enum pipe pipe)
 660 {
 661         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 662 }
 663
 664 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 665                                 enum pipe pipe)
 666 {
 667         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 668 }
 669
 670 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 671                          enum pipe pipe)
 672 {
 673         return true;
 674 }
 675
 676 static enum pipe
 677 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 678                      enum port port,
 679                      vlv_pipe_check pipe_check)
 680 {
 681         enum pipe pipe;
 682
 683         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 684                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 685                         PANEL_PORT_SELECT_MASK;
 686
 687                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 688                         continue;
 689
 690                 if (!pipe_check(dev_priv, pipe))
 691                         continue;
 692
 693                 return pipe;
 694         }
 695
 696         return INVALID_PIPE;
 697 }
 698
 699 static void
 700 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 701 {
 702         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 703         struct drm_device *dev = intel_dig_port->base.base.dev;
 704         struct drm_i915_private *dev_priv = to_i915(dev);
 705         enum port port = intel_dig_port->port;
 706
 707         lockdep_assert_held(&dev_priv->pps_mutex);
 708
 709         /* try to find a pipe with this port selected */
 710         /* first pick one where the panel is on */
 711         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 712                                                   vlv_pipe_has_pp_on);
 713         /* didn't find one? pick one where vdd is on */
 714         if (intel_dp->pps_pipe == INVALID_PIPE)
 715                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 716                                                           vlv_pipe_has_vdd_on);
 717         /* didn't find one? pick one with just the correct port */
 718         if (intel_dp->pps_pipe == INVALID_PIPE)
 719                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 720                                                           vlv_pipe_any);
 721
 722         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 723         if (intel_dp->pps_pipe == INVALID_PIPE) {
 724                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 725                               port_name(port));
 726                 return;
 727         }
 728
 729         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 730                       port_name(port), pipe_name(intel_dp->pps_pipe));
 731
 732         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 733         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 734 }
 735
 736 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 737 {
 738         struct drm_device *dev = &dev_priv->drm;
 739         struct intel_encoder *encoder;
 740
 741         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 742                     !IS_GEN9_LP(dev_priv)))
 743                 return;
 744
 745         /*
 746          * We can't grab pps_mutex here due to deadlock with power_domain
 747          * mutex when power_domain functions are called while holding pps_mutex.
 748          * That also means that in order to use pps_pipe the code needs to
 749          * hold both a power domain reference and pps_mutex, and the power domain
 750          * reference get/put must be done while _not_ holding pps_mutex.
 751          * pps_{lock,unlock}() do these steps in the correct order, so one
 752          * should use them always.
 753          */
 754
 755         for_each_intel_encoder(dev, encoder) {
 756                 struct intel_dp *intel_dp;
 757
 758                 if (encoder->type != INTEL_OUTPUT_DP &&
 759                     encoder->type != INTEL_OUTPUT_EDP)
 760                         continue;
 761
 762                 intel_dp = enc_to_intel_dp(&encoder->base);
 763
 764                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 765
 766                 if (encoder->type != INTEL_OUTPUT_EDP)
 767                         continue;
 768
 769                 if (IS_GEN9_LP(dev_priv))
 770                         intel_dp->pps_reset = true;
 771                 else
 772                         intel_dp->pps_pipe = INVALID_PIPE;
 773         }
 774 }
 775
 776 struct pps_registers {
 777         i915_reg_t pp_ctrl;
 778         i915_reg_t pp_stat;
 779         i915_reg_t pp_on;
 780         i915_reg_t pp_off;
 781         i915_reg_t pp_div;
 782 };
 783
 784 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 785                                     struct intel_dp *intel_dp,
 786                                     struct pps_registers *regs)
 787 {
 788         int pps_idx = 0;
 789
 790         memset(regs, 0, sizeof(*regs));
 791
 792         if (IS_GEN9_LP(dev_priv))
 793                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 794         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 795                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 796
 797         regs->pp_ctrl = PP_CONTROL(pps_idx);
 798         regs->pp_stat = PP_STATUS(pps_idx);
 799         regs->pp_on = PP_ON_DELAYS(pps_idx);
 800         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 801         if (!IS_GEN9_LP(dev_priv))
 802                 regs->pp_div = PP_DIVISOR(pps_idx);
 803 }
 804
 805 static i915_reg_t
 806 _pp_ctrl_reg(struct intel_dp *intel_dp)
 807 {
 808         struct pps_registers regs;
 809
 810         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 811                                 &regs);
 812
 813         return regs.pp_ctrl;
 814 }
 815
 816 static i915_reg_t
 817 _pp_stat_reg(struct intel_dp *intel_dp)
 818 {
 819         struct pps_registers regs;
 820
 821         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 822                                 &regs);
 823
 824         return regs.pp_stat;
 825 }
 826
 827 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 828    This function only applicable when panel PM state is not to be tracked */
 829 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 830                               void *unused)
 831 {
 832         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 833                                                  edp_notifier);
 834         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 835         struct drm_i915_private *dev_priv = to_i915(dev);
 836
 837         if (!is_edp(intel_dp) || code != SYS_RESTART)
 838                 return 0;
 839
 840         pps_lock(intel_dp);
 841
 842         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 843                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 844                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 845                 u32 pp_div;
 846
 847                 pp_ctrl_reg = PP_CONTROL(pipe);
 848                 pp_div_reg  = PP_DIVISOR(pipe);
 849                 pp_div = I915_READ(pp_div_reg);
 850                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 851
 852                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 853                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 854                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 855                 msleep(intel_dp->panel_power_cycle_delay);
 856         }
 857
 858         pps_unlock(intel_dp);
 859
 860         return 0;
 861 }
 862
 863 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 864 {
 865         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 866         struct drm_i915_private *dev_priv = to_i915(dev);
 867
 868         lockdep_assert_held(&dev_priv->pps_mutex);
 869
 870         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 871             intel_dp->pps_pipe == INVALID_PIPE)
 872                 return false;
 873
 874         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 875 }
 876
 877 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 878 {
 879         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 880         struct drm_i915_private *dev_priv = to_i915(dev);
 881
 882         lockdep_assert_held(&dev_priv->pps_mutex);
 883
 884         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 885             intel_dp->pps_pipe == INVALID_PIPE)
 886                 return false;
 887
 888         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 889 }
 890
 891 static void
 892 intel_dp_check_edp(struct intel_dp *intel_dp)
 893 {
 894         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 895         struct drm_i915_private *dev_priv = to_i915(dev);
 896
 897         if (!is_edp(intel_dp))
 898                 return;
 899
 900         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 901                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 902                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 903                               I915_READ(_pp_stat_reg(intel_dp)),
 904                               I915_READ(_pp_ctrl_reg(intel_dp)));
 905         }
 906 }
 907
 908 static uint32_t
 909 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 910 {
 911         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 912         struct drm_device *dev = intel_dig_port->base.base.dev;
 913         struct drm_i915_private *dev_priv = to_i915(dev);
 914         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 915         uint32_t status;
 916         bool done;
 917
 918 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 919         if (has_aux_irq)
 920                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 921                                           msecs_to_jiffies_timeout(10));
 922         else
 923                 done = wait_for(C, 10) == 0;
 924         if (!done)
 925                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 926                           has_aux_irq);
 927 #undef C
 928
 929         return status;
 930 }
 931
 932 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 933 {
 934         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 935         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 936
 937         if (index)
 938                 return 0;
 939
 940         /*
 941          * The clock divider is based off the hrawclk, and would like to run at
 942          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 943          */
 944         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 945 }
 946
 947 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 948 {
 949         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 950         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 951
 952         if (index)
 953                 return 0;
 954
 955         /*
 956          * The clock divider is based off the cdclk or PCH rawclk, and would
 957          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 958          * divide by 2000 and use that
 959          */
 960         if (intel_dig_port->port == PORT_A)
 961                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 962         else
 963                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 964 }
 965
 966 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 967 {
 968         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 969         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 970
 971         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 972                 /* Workaround for non-ULT HSW */
 973                 switch (index) {
 974                 case 0: return 63;
 975                 case 1: return 72;
 976                 default: return 0;
 977                 }
 978         }
 979
 980         return ilk_get_aux_clock_divider(intel_dp, index);
 981 }
 982
 983 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 984 {
 985         /*
 986          * SKL doesn't need us to program the AUX clock divider (Hardware will
 987          * derive the clock from CDCLK automatically). We still implement the
 988          * get_aux_clock_divider vfunc to plug-in into the existing code.
 989          */
 990         return index ? 0 : 1;
 991 }
 992
 993 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 994                                      bool has_aux_irq,
 995                                      int send_bytes,
 996                                      uint32_t aux_clock_divider)
 997 {
 998         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 999         struct drm_i915_private *dev_priv =
1000                         to_i915(intel_dig_port->base.base.dev);
1001         uint32_t precharge, timeout;
1002
1003         if (IS_GEN6(dev_priv))
1004                 precharge = 3;
1005         else
1006                 precharge = 5;
1007
1008         if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
1009                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1010         else
1011                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1012
1013         return DP_AUX_CH_CTL_SEND_BUSY |
1014                DP_AUX_CH_CTL_DONE |
1015                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1016                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1017                timeout |
1018                DP_AUX_CH_CTL_RECEIVE_ERROR |
1019                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1020                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1021                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1022 }
1023
1024 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1025                                       bool has_aux_irq,
1026                                       int send_bytes,
1027                                       uint32_t unused)
1028 {
1029         return DP_AUX_CH_CTL_SEND_BUSY |
1030                DP_AUX_CH_CTL_DONE |
1031                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1032                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1033                DP_AUX_CH_CTL_TIME_OUT_1600us |
1034                DP_AUX_CH_CTL_RECEIVE_ERROR |
1035                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1036                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1037                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1038 }
1039
1040 static int
1041 intel_dp_aux_ch(struct intel_dp *intel_dp,
1042                 const uint8_t *send, int send_bytes,
1043                 uint8_t *recv, int recv_size)
1044 {
1045         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1046         struct drm_i915_private *dev_priv =
1047                         to_i915(intel_dig_port->base.base.dev);
1048         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1049         uint32_t aux_clock_divider;
1050         int i, ret, recv_bytes;
1051         uint32_t status;
1052         int try, clock = 0;
1053         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1054         bool vdd;
1055
1056         pps_lock(intel_dp);
1057
1058         /*
1059          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1060          * In such cases we want to leave VDD enabled and it's up to upper layers
1061          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1062          * ourselves.
1063          */
1064         vdd = edp_panel_vdd_on(intel_dp);
1065
1066         /* dp aux is extremely sensitive to irq latency, hence request the
1067          * lowest possible wakeup latency and so prevent the cpu from going into
1068          * deep sleep states.
1069          */
1070         pm_qos_update_request(&dev_priv->pm_qos, 0);
1071
1072         intel_dp_check_edp(intel_dp);
1073
1074         /* Try to wait for any previous AUX channel activity */
1075         for (try = 0; try < 3; try++) {
1076                 status = I915_READ_NOTRACE(ch_ctl);
1077                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1078                         break;
1079                 msleep(1);
1080         }
1081
1082         if (try == 3) {
1083                 static u32 last_status = -1;
1084                 const u32 status = I915_READ(ch_ctl);
1085
1086                 if (status != last_status) {
1087                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1088                              status);
1089                         last_status = status;
1090                 }
1091
1092                 ret = -EBUSY;
1093                 goto out;
1094         }
1095
1096         /* Only 5 data registers! */
1097         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1098                 ret = -E2BIG;
1099                 goto out;
1100         }
1101
1102         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1103                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1104                                                           has_aux_irq,
1105                                                           send_bytes,
1106                                                           aux_clock_divider);
1107
1108                 /* Must try at least 3 times according to DP spec */
1109                 for (try = 0; try < 5; try++) {
1110                         /* Load the send data into the aux channel data registers */
1111                         for (i = 0; i < send_bytes; i += 4)
1112                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1113                                            intel_dp_pack_aux(send + i,
1114                                                              send_bytes - i));
1115
1116                         /* Send the command and wait for it to complete */
1117                         I915_WRITE(ch_ctl, send_ctl);
1118
1119                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1120
1121                         /* Clear done status and any errors */
1122                         I915_WRITE(ch_ctl,
1123                                    status |
1124                                    DP_AUX_CH_CTL_DONE |
1125                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1126                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1127
1128                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1129                                 continue;
1130
1131                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1132                          *   400us delay required for errors and timeouts
1133                          *   Timeout errors from the HW already meet this
1134                          *   requirement so skip to next iteration
1135                          */
1136                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1137                                 usleep_range(400, 500);
1138                                 continue;
1139                         }
1140                         if (status & DP_AUX_CH_CTL_DONE)
1141                                 goto done;
1142                 }
1143         }
1144
1145         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1146                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1147                 ret = -EBUSY;
1148                 goto out;
1149         }
1150
1151 done:
1152         /* Check for timeout or receive error.
1153          * Timeouts occur when the sink is not connected
1154          */
1155         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1156                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1157                 ret = -EIO;
1158                 goto out;
1159         }
1160
1161         /* Timeouts occur when the device isn't connected, so they're
1162          * "normal" -- don't fill the kernel log with these */
1163         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1164                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1165                 ret = -ETIMEDOUT;
1166                 goto out;
1167         }
1168
1169         /* Unload any bytes sent back from the other side */
1170         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1171                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1172
1173         /*
1174          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1175          * We have no idea of what happened so we return -EBUSY so
1176          * drm layer takes care for the necessary retries.
1177          */
1178         if (recv_bytes == 0 || recv_bytes > 20) {
1179                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1180                               recv_bytes);
1181                 /*
1182                  * FIXME: This patch was created on top of a series that
1183                  * organize the retries at drm level. There EBUSY should
1184                  * also take care for 1ms wait before retrying.
1185                  * That aux retries re-org is still needed and after that is
1186                  * merged we remove this sleep from here.
1187                  */
1188                 usleep_range(1000, 1500);
1189                 ret = -EBUSY;
1190                 goto out;
1191         }
1192
1193         if (recv_bytes > recv_size)
1194                 recv_bytes = recv_size;
1195
1196         for (i = 0; i < recv_bytes; i += 4)
1197                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1198                                     recv + i, recv_bytes - i);
1199
1200         ret = recv_bytes;
1201 out:
1202         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1203
1204         if (vdd)
1205                 edp_panel_vdd_off(intel_dp, false);
1206
1207         pps_unlock(intel_dp);
1208
1209         return ret;
1210 }
1211
1212 #define BARE_ADDRESS_SIZE       3
1213 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1214 static ssize_t
1215 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1216 {
1217         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1218         uint8_t txbuf[20], rxbuf[20];
1219         size_t txsize, rxsize;
1220         int ret;
1221
1222         txbuf[0] = (msg->request << 4) |
1223                 ((msg->address >> 16) & 0xf);
1224         txbuf[1] = (msg->address >> 8) & 0xff;
1225         txbuf[2] = msg->address & 0xff;
1226         txbuf[3] = msg->size - 1;
1227
1228         switch (msg->request & ~DP_AUX_I2C_MOT) {
1229         case DP_AUX_NATIVE_WRITE:
1230         case DP_AUX_I2C_WRITE:
1231         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1232                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1233                 rxsize = 2; /* 0 or 1 data bytes */
1234
1235                 if (WARN_ON(txsize > 20))
1236                         return -E2BIG;
1237
1238                 WARN_ON(!msg->buffer != !msg->size);
1239
1240                 if (msg->buffer)
1241                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1242
1243                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1244                 if (ret > 0) {
1245                         msg->reply = rxbuf[0] >> 4;
1246
1247                         if (ret > 1) {
1248                                 /* Number of bytes written in a short write. */
1249                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1250                         } else {
1251                                 /* Return payload size. */
1252                                 ret = msg->size;
1253                         }
1254                 }
1255                 break;
1256
1257         case DP_AUX_NATIVE_READ:
1258         case DP_AUX_I2C_READ:
1259                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1260                 rxsize = msg->size + 1;
1261
1262                 if (WARN_ON(rxsize > 20))
1263                         return -E2BIG;
1264
1265                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1266                 if (ret > 0) {
1267                         msg->reply = rxbuf[0] >> 4;
1268                         /*
1269                          * Assume happy day, and copy the data. The caller is
1270                          * expected to check msg->reply before touching it.
1271                          *
1272                          * Return payload size.
1273                          */
1274                         ret--;
1275                         memcpy(msg->buffer, rxbuf + 1, ret);
1276                 }
1277                 break;
1278
1279         default:
1280                 ret = -EINVAL;
1281                 break;
1282         }
1283
1284         return ret;
1285 }
1286
1287 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1288                                 enum port port)
1289 {
1290         const struct ddi_vbt_port_info *info =
1291                 &dev_priv->vbt.ddi_port_info[port];
1292         enum port aux_port;
1293
1294         if (!info->alternate_aux_channel) {
1295                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1296                               port_name(port), port_name(port));
1297                 return port;
1298         }
1299
1300         switch (info->alternate_aux_channel) {
1301         case DP_AUX_A:
1302                 aux_port = PORT_A;
1303                 break;
1304         case DP_AUX_B:
1305                 aux_port = PORT_B;
1306                 break;
1307         case DP_AUX_C:
1308                 aux_port = PORT_C;
1309                 break;
1310         case DP_AUX_D:
1311                 aux_port = PORT_D;
1312                 break;
1313         default:
1314                 MISSING_CASE(info->alternate_aux_channel);
1315                 aux_port = PORT_A;
1316                 break;
1317         }
1318
1319         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1320                       port_name(aux_port), port_name(port));
1321
1322         return aux_port;
1323 }
1324
1325 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1326                                   enum port port)
1327 {
1328         switch (port) {
1329         case PORT_B:
1330         case PORT_C:
1331         case PORT_D:
1332                 return DP_AUX_CH_CTL(port);
1333         default:
1334                 MISSING_CASE(port);
1335                 return DP_AUX_CH_CTL(PORT_B);
1336         }
1337 }
1338
1339 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1340                                    enum port port, int index)
1341 {
1342         switch (port) {
1343         case PORT_B:
1344         case PORT_C:
1345         case PORT_D:
1346                 return DP_AUX_CH_DATA(port, index);
1347         default:
1348                 MISSING_CASE(port);
1349                 return DP_AUX_CH_DATA(PORT_B, index);
1350         }
1351 }
1352
1353 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1354                                   enum port port)
1355 {
1356         switch (port) {
1357         case PORT_A:
1358                 return DP_AUX_CH_CTL(port);
1359         case PORT_B:
1360         case PORT_C:
1361         case PORT_D:
1362                 return PCH_DP_AUX_CH_CTL(port);
1363         default:
1364                 MISSING_CASE(port);
1365                 return DP_AUX_CH_CTL(PORT_A);
1366         }
1367 }
1368
1369 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1370                                    enum port port, int index)
1371 {
1372         switch (port) {
1373         case PORT_A:
1374                 return DP_AUX_CH_DATA(port, index);
1375         case PORT_B:
1376         case PORT_C:
1377         case PORT_D:
1378                 return PCH_DP_AUX_CH_DATA(port, index);
1379         default:
1380                 MISSING_CASE(port);
1381                 return DP_AUX_CH_DATA(PORT_A, index);
1382         }
1383 }
1384
1385 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1386                                   enum port port)
1387 {
1388         switch (port) {
1389         case PORT_A:
1390         case PORT_B:
1391         case PORT_C:
1392         case PORT_D:
1393                 return DP_AUX_CH_CTL(port);
1394         default:
1395                 MISSING_CASE(port);
1396                 return DP_AUX_CH_CTL(PORT_A);
1397         }
1398 }
1399
1400 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1401                                    enum port port, int index)
1402 {
1403         switch (port) {
1404         case PORT_A:
1405         case PORT_B:
1406         case PORT_C:
1407         case PORT_D:
1408                 return DP_AUX_CH_DATA(port, index);
1409         default:
1410                 MISSING_CASE(port);
1411                 return DP_AUX_CH_DATA(PORT_A, index);
1412         }
1413 }
1414
1415 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1416                                     enum port port)
1417 {
1418         if (INTEL_INFO(dev_priv)->gen >= 9)
1419                 return skl_aux_ctl_reg(dev_priv, port);
1420         else if (HAS_PCH_SPLIT(dev_priv))
1421                 return ilk_aux_ctl_reg(dev_priv, port);
1422         else
1423                 return g4x_aux_ctl_reg(dev_priv, port);
1424 }
1425
1426 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1427                                      enum port port, int index)
1428 {
1429         if (INTEL_INFO(dev_priv)->gen >= 9)
1430                 return skl_aux_data_reg(dev_priv, port, index);
1431         else if (HAS_PCH_SPLIT(dev_priv))
1432                 return ilk_aux_data_reg(dev_priv, port, index);
1433         else
1434                 return g4x_aux_data_reg(dev_priv, port, index);
1435 }
1436
1437 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1438 {
1439         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1440         enum port port = intel_aux_port(dev_priv,
1441                                         dp_to_dig_port(intel_dp)->port);
1442         int i;
1443
1444         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1445         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1446                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1447 }
1448
1449 static void
1450 intel_dp_aux_fini(struct intel_dp *intel_dp)
1451 {
1452         kfree(intel_dp->aux.name);
1453 }
1454
1455 static void
1456 intel_dp_aux_init(struct intel_dp *intel_dp)
1457 {
1458         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1459         enum port port = intel_dig_port->port;
1460
1461         intel_aux_reg_init(intel_dp);
1462         drm_dp_aux_init(&intel_dp->aux);
1463
1464         /* Failure to allocate our preferred name is not critical */
1465         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1466         intel_dp->aux.transfer = intel_dp_aux_transfer;
1467 }
1468
1469 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1470 {
1471         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1472         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1473
1474         if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1475             IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1476                 return true;
1477         else
1478                 return false;
1479 }
1480
1481 static void
1482 intel_dp_set_clock(struct intel_encoder *encoder,
1483                    struct intel_crtc_state *pipe_config)
1484 {
1485         struct drm_device *dev = encoder->base.dev;
1486         struct drm_i915_private *dev_priv = to_i915(dev);
1487         const struct dp_link_dpll *divisor = NULL;
1488         int i, count = 0;
1489
1490         if (IS_G4X(dev_priv)) {
1491                 divisor = gen4_dpll;
1492                 count = ARRAY_SIZE(gen4_dpll);
1493         } else if (HAS_PCH_SPLIT(dev_priv)) {
1494                 divisor = pch_dpll;
1495                 count = ARRAY_SIZE(pch_dpll);
1496         } else if (IS_CHERRYVIEW(dev_priv)) {
1497                 divisor = chv_dpll;
1498                 count = ARRAY_SIZE(chv_dpll);
1499         } else if (IS_VALLEYVIEW(dev_priv)) {
1500                 divisor = vlv_dpll;
1501                 count = ARRAY_SIZE(vlv_dpll);
1502         }
1503
1504         if (divisor && count) {
1505                 for (i = 0; i < count; i++) {
1506                         if (pipe_config->port_clock == divisor[i].clock) {
1507                                 pipe_config->dpll = divisor[i].dpll;
1508                                 pipe_config->clock_set = true;
1509                                 break;
1510                         }
1511                 }
1512         }
1513 }
1514
1515 static void snprintf_int_array(char *str, size_t len,
1516                                const int *array, int nelem)
1517 {
1518         int i;
1519
1520         str[0] = '\0';
1521
1522         for (i = 0; i < nelem; i++) {
1523                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1524                 if (r >= len)
1525                         return;
1526                 str += r;
1527                 len -= r;
1528         }
1529 }
1530
1531 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1532 {
1533         char str[128]; /* FIXME: too big for stack? */
1534
1535         if ((drm_debug & DRM_UT_KMS) == 0)
1536                 return;
1537
1538         snprintf_int_array(str, sizeof(str),
1539                            intel_dp->source_rates, intel_dp->num_source_rates);
1540         DRM_DEBUG_KMS("source rates: %s\n", str);
1541
1542         snprintf_int_array(str, sizeof(str),
1543                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1544         DRM_DEBUG_KMS("sink rates: %s\n", str);
1545
1546         snprintf_int_array(str, sizeof(str),
1547                            intel_dp->common_rates, intel_dp->num_common_rates);
1548         DRM_DEBUG_KMS("common rates: %s\n", str);
1549 }
1550
1551 bool
1552 __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
1553 {
1554         u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1555                                                       DP_SINK_OUI;
1556
1557         return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1558                sizeof(*desc);
1559 }
1560
1561 bool intel_dp_read_desc(struct intel_dp *intel_dp)
1562 {
1563         struct intel_dp_desc *desc = &intel_dp->desc;
1564         bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1565                        DP_OUI_SUPPORT;
1566         int dev_id_len;
1567
1568         if (!__intel_dp_read_desc(intel_dp, desc))
1569                 return false;
1570
1571         dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1572         DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1573                       drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1574                       (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1575                       dev_id_len, desc->device_id,
1576                       desc->hw_rev >> 4, desc->hw_rev & 0xf,
1577                       desc->sw_major_rev, desc->sw_minor_rev);
1578
1579         return true;
1580 }
1581
1582 int
1583 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1584 {
1585         int len;
1586
1587         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1588         if (WARN_ON(len <= 0))
1589                 return 162000;
1590
1591         return intel_dp->common_rates[len - 1];
1592 }
1593
1594 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1595 {
1596         int i = intel_dp_rate_index(intel_dp->sink_rates,
1597                                     intel_dp->num_sink_rates, rate);
1598
1599         if (WARN_ON(i < 0))
1600                 i = 0;
1601
1602         return i;
1603 }
1604
1605 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1606                            uint8_t *link_bw, uint8_t *rate_select)
1607 {
1608         /* eDP 1.4 rate select method. */
1609         if (intel_dp->use_rate_select) {
1610                 *link_bw = 0;
1611                 *rate_select =
1612                         intel_dp_rate_select(intel_dp, port_clock);
1613         } else {
1614                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1615                 *rate_select = 0;
1616         }
1617 }
1618
1619 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1620                                 struct intel_crtc_state *pipe_config)
1621 {
1622         int bpp, bpc;
1623
1624         bpp = pipe_config->pipe_bpp;
1625         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1626
1627         if (bpc > 0)
1628                 bpp = min(bpp, 3*bpc);
1629
1630         /* For DP Compliance we override the computed bpp for the pipe */
1631         if (intel_dp->compliance.test_data.bpc != 0) {
1632                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1633                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1634                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1635                               pipe_config->pipe_bpp);
1636         }
1637         return bpp;
1638 }
1639
1640 bool
1641 intel_dp_compute_config(struct intel_encoder *encoder,
1642                         struct intel_crtc_state *pipe_config,
1643                         struct drm_connector_state *conn_state)
1644 {
1645         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1646         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1647         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1648         enum port port = dp_to_dig_port(intel_dp)->port;
1649         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1650         struct intel_connector *intel_connector = intel_dp->attached_connector;
1651         int lane_count, clock;
1652         int min_lane_count = 1;
1653         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1654         /* Conveniently, the link BW constants become indices with a shift...*/
1655         int min_clock = 0;
1656         int max_clock;
1657         int bpp, mode_rate;
1658         int link_avail, link_clock;
1659         int common_len;
1660         uint8_t link_bw, rate_select;
1661
1662         common_len = intel_dp_common_len_rate_limit(intel_dp,
1663                                                     intel_dp->max_link_rate);
1664
1665         /* No common link rates between source and sink */
1666         WARN_ON(common_len <= 0);
1667
1668         max_clock = common_len - 1;
1669
1670         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1671                 pipe_config->has_pch_encoder = true;
1672
1673         pipe_config->has_drrs = false;
1674         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1675
1676         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1677                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1678                                        adjusted_mode);
1679
1680                 if (INTEL_GEN(dev_priv) >= 9) {
1681                         int ret;
1682                         ret = skl_update_scaler_crtc(pipe_config);
1683                         if (ret)
1684                                 return ret;
1685                 }
1686
1687                 if (HAS_GMCH_DISPLAY(dev_priv))
1688                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1689                                                  intel_connector->panel.fitting_mode);
1690                 else
1691                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1692                                                 intel_connector->panel.fitting_mode);
1693         }
1694
1695         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1696                 return false;
1697
1698         /* Use values requested by Compliance Test Request */
1699         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1700                 int index;
1701
1702                 index = intel_dp_rate_index(intel_dp->common_rates,
1703                                             intel_dp->num_common_rates,
1704                                             intel_dp->compliance.test_link_rate);
1705                 if (index >= 0)
1706                         min_clock = max_clock = index;
1707                 min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1708         }
1709         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1710                       "max bw %d pixel clock %iKHz\n",
1711                       max_lane_count, intel_dp->common_rates[max_clock],
1712                       adjusted_mode->crtc_clock);
1713
1714         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1715          * bpc in between. */
1716         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1717         if (is_edp(intel_dp)) {
1718
1719                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1720                 if (intel_connector->base.display_info.bpc == 0 &&
1721                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1722                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1723                                       dev_priv->vbt.edp.bpp);
1724                         bpp = dev_priv->vbt.edp.bpp;
1725                 }
1726
1727                 /*
1728                  * Use the maximum clock and number of lanes the eDP panel
1729                  * advertizes being capable of. The panels are generally
1730                  * designed to support only a single clock and lane
1731                  * configuration, and typically these values correspond to the
1732                  * native resolution of the panel.
1733                  */
1734                 min_lane_count = max_lane_count;
1735                 min_clock = max_clock;
1736         }
1737
1738         for (; bpp >= 6*3; bpp -= 2*3) {
1739                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1740                                                    bpp);
1741
1742                 for (clock = min_clock; clock <= max_clock; clock++) {
1743                         for (lane_count = min_lane_count;
1744                                 lane_count <= max_lane_count;
1745                                 lane_count <<= 1) {
1746
1747                                 link_clock = intel_dp->common_rates[clock];
1748                                 link_avail = intel_dp_max_data_rate(link_clock,
1749                                                                     lane_count);
1750
1751                                 if (mode_rate <= link_avail) {
1752                                         goto found;
1753                                 }
1754                         }
1755                 }
1756         }
1757
1758         return false;
1759
1760 found:
1761         if (intel_dp->color_range_auto) {
1762                 /*
1763                  * See:
1764                  * CEA-861-E - 5.1 Default Encoding Parameters
1765                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1766                  */
1767                 pipe_config->limited_color_range =
1768                         bpp != 18 &&
1769                         drm_default_rgb_quant_range(adjusted_mode) ==
1770                         HDMI_QUANTIZATION_RANGE_LIMITED;
1771         } else {
1772                 pipe_config->limited_color_range =
1773                         intel_dp->limited_color_range;
1774         }
1775
1776         pipe_config->lane_count = lane_count;
1777
1778         pipe_config->pipe_bpp = bpp;
1779         pipe_config->port_clock = intel_dp->common_rates[clock];
1780
1781         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1782                               &link_bw, &rate_select);
1783
1784         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1785                       link_bw, rate_select, pipe_config->lane_count,
1786                       pipe_config->port_clock, bpp);
1787         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1788                       mode_rate, link_avail);
1789
1790         intel_link_compute_m_n(bpp, lane_count,
1791                                adjusted_mode->crtc_clock,
1792                                pipe_config->port_clock,
1793                                &pipe_config->dp_m_n);
1794
1795         if (intel_connector->panel.downclock_mode != NULL &&
1796                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1797                         pipe_config->has_drrs = true;
1798                         intel_link_compute_m_n(bpp, lane_count,
1799                                 intel_connector->panel.downclock_mode->clock,
1800                                 pipe_config->port_clock,
1801                                 &pipe_config->dp_m2_n2);
1802         }
1803
1804         /*
1805          * DPLL0 VCO may need to be adjusted to get the correct
1806          * clock for eDP. This will affect cdclk as well.
1807          */
1808         if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1809                 int vco;
1810
1811                 switch (pipe_config->port_clock / 2) {
1812                 case 108000:
1813                 case 216000:
1814                         vco = 8640000;
1815                         break;
1816                 default:
1817                         vco = 8100000;
1818                         break;
1819                 }
1820
1821                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1822         }
1823
1824         if (!HAS_DDI(dev_priv))
1825                 intel_dp_set_clock(encoder, pipe_config);
1826
1827         return true;
1828 }
1829
1830 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1831                               int link_rate, uint8_t lane_count,
1832                               bool link_mst)
1833 {
1834         intel_dp->link_rate = link_rate;
1835         intel_dp->lane_count = lane_count;
1836         intel_dp->link_mst = link_mst;
1837 }
1838
1839 static void intel_dp_prepare(struct intel_encoder *encoder,
1840                              struct intel_crtc_state *pipe_config)
1841 {
1842         struct drm_device *dev = encoder->base.dev;
1843         struct drm_i915_private *dev_priv = to_i915(dev);
1844         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1845         enum port port = dp_to_dig_port(intel_dp)->port;
1846         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1847         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1848
1849         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1850                                  pipe_config->lane_count,
1851                                  intel_crtc_has_type(pipe_config,
1852                                                      INTEL_OUTPUT_DP_MST));
1853
1854         /*
1855          * There are four kinds of DP registers:
1856          *
1857          *      IBX PCH
1858          *      SNB CPU
1859          *      IVB CPU
1860          *      CPT PCH
1861          *
1862          * IBX PCH and CPU are the same for almost everything,
1863          * except that the CPU DP PLL is configured in this
1864          * register
1865          *
1866          * CPT PCH is quite different, having many bits moved
1867          * to the TRANS_DP_CTL register instead. That
1868          * configuration happens (oddly) in ironlake_pch_enable
1869          */
1870
1871         /* Preserve the BIOS-computed detected bit. This is
1872          * supposed to be read-only.
1873          */
1874         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1875
1876         /* Handle DP bits in common between all three register formats */
1877         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1878         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1879
1880         /* Split out the IBX/CPU vs CPT settings */
1881
1882         if (IS_GEN7(dev_priv) && port == PORT_A) {
1883                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1884                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1885                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1886                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1887                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1888
1889                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1890                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1891
1892                 intel_dp->DP |= crtc->pipe << 29;
1893         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1894                 u32 trans_dp;
1895
1896                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1897
1898                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1899                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1900                         trans_dp |= TRANS_DP_ENH_FRAMING;
1901                 else
1902                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1903                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1904         } else {
1905                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1906                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1907
1908                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1909                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1910                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1911                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1912                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1913
1914                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1915                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1916
1917                 if (IS_CHERRYVIEW(dev_priv))
1918                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1919                 else if (crtc->pipe == PIPE_B)
1920                         intel_dp->DP |= DP_PIPEB_SELECT;
1921         }
1922 }
1923
1924 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1925 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1926
1927 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1928 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1929
1930 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1931 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1932
1933 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1934                                    struct intel_dp *intel_dp);
1935
1936 static void wait_panel_status(struct intel_dp *intel_dp,
1937                                        u32 mask,
1938                                        u32 value)
1939 {
1940         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1941         struct drm_i915_private *dev_priv = to_i915(dev);
1942         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1943
1944         lockdep_assert_held(&dev_priv->pps_mutex);
1945
1946         intel_pps_verify_state(dev_priv, intel_dp);
1947
1948         pp_stat_reg = _pp_stat_reg(intel_dp);
1949         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1950
1951         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1952                         mask, value,
1953                         I915_READ(pp_stat_reg),
1954                         I915_READ(pp_ctrl_reg));
1955
1956         if (intel_wait_for_register(dev_priv,
1957                                     pp_stat_reg, mask, value,
1958                                     5000))
1959                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1960                                 I915_READ(pp_stat_reg),
1961                                 I915_READ(pp_ctrl_reg));
1962
1963         DRM_DEBUG_KMS("Wait complete\n");
1964 }
1965
1966 static void wait_panel_on(struct intel_dp *intel_dp)
1967 {
1968         DRM_DEBUG_KMS("Wait for panel power on\n");
1969         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1970 }
1971
1972 static void wait_panel_off(struct intel_dp *intel_dp)
1973 {
1974         DRM_DEBUG_KMS("Wait for panel power off time\n");
1975         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1976 }
1977
1978 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1979 {
1980         ktime_t panel_power_on_time;
1981         s64 panel_power_off_duration;
1982
1983         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1984
1985         /* take the difference of currrent time and panel power off time
1986          * and then make panel wait for t11_t12 if needed. */
1987         panel_power_on_time = ktime_get_boottime();
1988         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1989
1990         /* When we disable the VDD override bit last we have to do the manual
1991          * wait. */
1992         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1993                 wait_remaining_ms_from_jiffies(jiffies,
1994                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1995
1996         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1997 }
1998
1999 static void wait_backlight_on(struct intel_dp *intel_dp)
2000 {
2001         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2002                                        intel_dp->backlight_on_delay);
2003 }
2004
2005 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2006 {
2007         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2008                                        intel_dp->backlight_off_delay);
2009 }
2010
2011 /* Read the current pp_control value, unlocking the register if it
2012  * is locked
2013  */
2014
2015 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2016 {
2017         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2018         struct drm_i915_private *dev_priv = to_i915(dev);
2019         u32 control;
2020
2021         lockdep_assert_held(&dev_priv->pps_mutex);
2022
2023         control = I915_READ(_pp_ctrl_reg(intel_dp));
2024         if (WARN_ON(!HAS_DDI(dev_priv) &&
2025                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2026                 control &= ~PANEL_UNLOCK_MASK;
2027                 control |= PANEL_UNLOCK_REGS;
2028         }
2029         return control;
2030 }
2031
2032 /*
2033  * Must be paired with edp_panel_vdd_off().
2034  * Must hold pps_mutex around the whole on/off sequence.
2035  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2036  */
2037 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2038 {
2039         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2040         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2041         struct drm_i915_private *dev_priv = to_i915(dev);
2042         u32 pp;
2043         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2044         bool need_to_disable = !intel_dp->want_panel_vdd;
2045
2046         lockdep_assert_held(&dev_priv->pps_mutex);
2047
2048         if (!is_edp(intel_dp))
2049                 return false;
2050
2051         cancel_delayed_work(&intel_dp->panel_vdd_work);
2052         intel_dp->want_panel_vdd = true;
2053
2054         if (edp_have_panel_vdd(intel_dp))
2055                 return need_to_disable;
2056
2057         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2058
2059         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2060                       port_name(intel_dig_port->port));
2061
2062         if (!edp_have_panel_power(intel_dp))
2063                 wait_panel_power_cycle(intel_dp);
2064
2065         pp = ironlake_get_pp_control(intel_dp);
2066         pp |= EDP_FORCE_VDD;
2067
2068         pp_stat_reg = _pp_stat_reg(intel_dp);
2069         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2070
2071         I915_WRITE(pp_ctrl_reg, pp);
2072         POSTING_READ(pp_ctrl_reg);
2073         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2074                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2075         /*
2076          * If the panel wasn't on, delay before accessing aux channel
2077          */
2078         if (!edp_have_panel_power(intel_dp)) {
2079                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2080                               port_name(intel_dig_port->port));
2081                 msleep(intel_dp->panel_power_up_delay);
2082         }
2083
2084         return need_to_disable;
2085 }
2086
2087 /*
2088  * Must be paired with intel_edp_panel_vdd_off() or
2089  * intel_edp_panel_off().
2090  * Nested calls to these functions are not allowed since
2091  * we drop the lock. Caller must use some higher level
2092  * locking to prevent nested calls from other threads.
2093  */
2094 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2095 {
2096         bool vdd;
2097
2098         if (!is_edp(intel_dp))
2099                 return;
2100
2101         pps_lock(intel_dp);
2102         vdd = edp_panel_vdd_on(intel_dp);
2103         pps_unlock(intel_dp);
2104
2105         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2106              port_name(dp_to_dig_port(intel_dp)->port));
2107 }
2108
2109 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2110 {
2111         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2112         struct drm_i915_private *dev_priv = to_i915(dev);
2113         struct intel_digital_port *intel_dig_port =
2114                 dp_to_dig_port(intel_dp);
2115         u32 pp;
2116         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2117
2118         lockdep_assert_held(&dev_priv->pps_mutex);
2119
2120         WARN_ON(intel_dp->want_panel_vdd);
2121
2122         if (!edp_have_panel_vdd(intel_dp))
2123                 return;
2124
2125         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2126                       port_name(intel_dig_port->port));
2127
2128         pp = ironlake_get_pp_control(intel_dp);
2129         pp &= ~EDP_FORCE_VDD;
2130
2131         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2132         pp_stat_reg = _pp_stat_reg(intel_dp);
2133
2134         I915_WRITE(pp_ctrl_reg, pp);
2135         POSTING_READ(pp_ctrl_reg);
2136
2137         /* Make sure sequencer is idle before allowing subsequent activity */
2138         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2139         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2140
2141         if ((pp & PANEL_POWER_ON) == 0)
2142                 intel_dp->panel_power_off_time = ktime_get_boottime();
2143
2144         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2145 }
2146
2147 static void edp_panel_vdd_work(struct work_struct *__work)
2148 {
2149         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2150                                                  struct intel_dp, panel_vdd_work);
2151
2152         pps_lock(intel_dp);
2153         if (!intel_dp->want_panel_vdd)
2154                 edp_panel_vdd_off_sync(intel_dp);
2155         pps_unlock(intel_dp);
2156 }
2157
2158 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2159 {
2160         unsigned long delay;
2161
2162         /*
2163          * Queue the timer to fire a long time from now (relative to the power
2164          * down delay) to keep the panel power up across a sequence of
2165          * operations.
2166          */
2167         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2168         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2169 }
2170
2171 /*
2172  * Must be paired with edp_panel_vdd_on().
2173  * Must hold pps_mutex around the whole on/off sequence.
2174  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2175  */
2176 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2177 {
2178         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2179
2180         lockdep_assert_held(&dev_priv->pps_mutex);
2181
2182         if (!is_edp(intel_dp))
2183                 return;
2184
2185         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2186              port_name(dp_to_dig_port(intel_dp)->port));
2187
2188         intel_dp->want_panel_vdd = false;
2189
2190         if (sync)
2191                 edp_panel_vdd_off_sync(intel_dp);
2192         else
2193                 edp_panel_vdd_schedule_off(intel_dp);
2194 }
2195
2196 static void edp_panel_on(struct intel_dp *intel_dp)
2197 {
2198         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2199         struct drm_i915_private *dev_priv = to_i915(dev);
2200         u32 pp;
2201         i915_reg_t pp_ctrl_reg;
2202
2203         lockdep_assert_held(&dev_priv->pps_mutex);
2204
2205         if (!is_edp(intel_dp))
2206                 return;
2207
2208         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2209                       port_name(dp_to_dig_port(intel_dp)->port));
2210
2211         if (WARN(edp_have_panel_power(intel_dp),
2212                  "eDP port %c panel power already on\n",
2213                  port_name(dp_to_dig_port(intel_dp)->port)))
2214                 return;
2215
2216         wait_panel_power_cycle(intel_dp);
2217
2218         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2219         pp = ironlake_get_pp_control(intel_dp);
2220         if (IS_GEN5(dev_priv)) {
2221                 /* ILK workaround: disable reset around power sequence */
2222                 pp &= ~PANEL_POWER_RESET;
2223                 I915_WRITE(pp_ctrl_reg, pp);
2224                 POSTING_READ(pp_ctrl_reg);
2225         }
2226
2227         pp |= PANEL_POWER_ON;
2228         if (!IS_GEN5(dev_priv))
2229                 pp |= PANEL_POWER_RESET;
2230
2231         I915_WRITE(pp_ctrl_reg, pp);
2232         POSTING_READ(pp_ctrl_reg);
2233
2234         wait_panel_on(intel_dp);
2235         intel_dp->last_power_on = jiffies;
2236
2237         if (IS_GEN5(dev_priv)) {
2238                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2239                 I915_WRITE(pp_ctrl_reg, pp);
2240                 POSTING_READ(pp_ctrl_reg);
2241         }
2242 }
2243
2244 void intel_edp_panel_on(struct intel_dp *intel_dp)
2245 {
2246         if (!is_edp(intel_dp))
2247                 return;
2248
2249         pps_lock(intel_dp);
2250         edp_panel_on(intel_dp);
2251         pps_unlock(intel_dp);
2252 }
2253
2254
2255 static void edp_panel_off(struct intel_dp *intel_dp)
2256 {
2257         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2258         struct drm_i915_private *dev_priv = to_i915(dev);
2259         u32 pp;
2260         i915_reg_t pp_ctrl_reg;
2261
2262         lockdep_assert_held(&dev_priv->pps_mutex);
2263
2264         if (!is_edp(intel_dp))
2265                 return;
2266
2267         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2268                       port_name(dp_to_dig_port(intel_dp)->port));
2269
2270         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2271              port_name(dp_to_dig_port(intel_dp)->port));
2272
2273         pp = ironlake_get_pp_control(intel_dp);
2274         /* We need to switch off panel power _and_ force vdd, for otherwise some
2275          * panels get very unhappy and cease to work. */
2276         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2277                 EDP_BLC_ENABLE);
2278
2279         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2280
2281         intel_dp->want_panel_vdd = false;
2282
2283         I915_WRITE(pp_ctrl_reg, pp);
2284         POSTING_READ(pp_ctrl_reg);
2285
2286         intel_dp->panel_power_off_time = ktime_get_boottime();
2287         wait_panel_off(intel_dp);
2288
2289         /* We got a reference when we enabled the VDD. */
2290         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2291 }
2292
2293 void intel_edp_panel_off(struct intel_dp *intel_dp)
2294 {
2295         if (!is_edp(intel_dp))
2296                 return;
2297
2298         pps_lock(intel_dp);
2299         edp_panel_off(intel_dp);
2300         pps_unlock(intel_dp);
2301 }
2302
2303 /* Enable backlight in the panel power control. */
2304 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2305 {
2306         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2307         struct drm_device *dev = intel_dig_port->base.base.dev;
2308         struct drm_i915_private *dev_priv = to_i915(dev);
2309         u32 pp;
2310         i915_reg_t pp_ctrl_reg;
2311
2312         /*
2313          * If we enable the backlight right away following a panel power
2314          * on, we may see slight flicker as the panel syncs with the eDP
2315          * link.  So delay a bit to make sure the image is solid before
2316          * allowing it to appear.
2317          */
2318         wait_backlight_on(intel_dp);
2319
2320         pps_lock(intel_dp);
2321
2322         pp = ironlake_get_pp_control(intel_dp);
2323         pp |= EDP_BLC_ENABLE;
2324
2325         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2326
2327         I915_WRITE(pp_ctrl_reg, pp);
2328         POSTING_READ(pp_ctrl_reg);
2329
2330         pps_unlock(intel_dp);
2331 }
2332
2333 /* Enable backlight PWM and backlight PP control. */
2334 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2335 {
2336         if (!is_edp(intel_dp))
2337                 return;
2338
2339         DRM_DEBUG_KMS("\n");
2340
2341         intel_panel_enable_backlight(intel_dp->attached_connector);
2342         _intel_edp_backlight_on(intel_dp);
2343 }
2344
2345 /* Disable backlight in the panel power control. */
2346 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2347 {
2348         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2349         struct drm_i915_private *dev_priv = to_i915(dev);
2350         u32 pp;
2351         i915_reg_t pp_ctrl_reg;
2352
2353         if (!is_edp(intel_dp))
2354                 return;
2355
2356         pps_lock(intel_dp);
2357
2358         pp = ironlake_get_pp_control(intel_dp);
2359         pp &= ~EDP_BLC_ENABLE;
2360
2361         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2362
2363         I915_WRITE(pp_ctrl_reg, pp);
2364         POSTING_READ(pp_ctrl_reg);
2365
2366         pps_unlock(intel_dp);
2367
2368         intel_dp->last_backlight_off = jiffies;
2369         edp_wait_backlight_off(intel_dp);
2370 }
2371
2372 /* Disable backlight PP control and backlight PWM. */
2373 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2374 {
2375         if (!is_edp(intel_dp))
2376                 return;
2377
2378         DRM_DEBUG_KMS("\n");
2379
2380         _intel_edp_backlight_off(intel_dp);
2381         intel_panel_disable_backlight(intel_dp->attached_connector);
2382 }
2383
2384 /*
2385  * Hook for controlling the panel power control backlight through the bl_power
2386  * sysfs attribute. Take care to handle multiple calls.
2387  */
2388 static void intel_edp_backlight_power(struct intel_connector *connector,
2389                                       bool enable)
2390 {
2391         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2392         bool is_enabled;
2393
2394         pps_lock(intel_dp);
2395         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2396         pps_unlock(intel_dp);
2397
2398         if (is_enabled == enable)
2399                 return;
2400
2401         DRM_DEBUG_KMS("panel power control backlight %s\n",
2402                       enable ? "enable" : "disable");
2403
2404         if (enable)
2405                 _intel_edp_backlight_on(intel_dp);
2406         else
2407                 _intel_edp_backlight_off(intel_dp);
2408 }
2409
2410 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2411 {
2412         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2413         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2414         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2415
2416         I915_STATE_WARN(cur_state != state,
2417                         "DP port %c state assertion failure (expected %s, current %s)\n",
2418                         port_name(dig_port->port),
2419                         onoff(state), onoff(cur_state));
2420 }
2421 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2422
2423 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2424 {
2425         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2426
2427         I915_STATE_WARN(cur_state != state,
2428                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2429                         onoff(state), onoff(cur_state));
2430 }
2431 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2432 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2433
2434 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2435                                 struct intel_crtc_state *pipe_config)
2436 {
2437         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2438         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2439
2440         assert_pipe_disabled(dev_priv, crtc->pipe);
2441         assert_dp_port_disabled(intel_dp);
2442         assert_edp_pll_disabled(dev_priv);
2443
2444         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2445                       pipe_config->port_clock);
2446
2447         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2448
2449         if (pipe_config->port_clock == 162000)
2450                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2451         else
2452                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2453
2454         I915_WRITE(DP_A, intel_dp->DP);
2455         POSTING_READ(DP_A);
2456         udelay(500);
2457
2458         /*
2459          * [DevILK] Work around required when enabling DP PLL
2460          * while a pipe is enabled going to FDI:
2461          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2462          * 2. Program DP PLL enable
2463          */
2464         if (IS_GEN5(dev_priv))
2465                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2466
2467         intel_dp->DP |= DP_PLL_ENABLE;
2468
2469         I915_WRITE(DP_A, intel_dp->DP);
2470         POSTING_READ(DP_A);
2471         udelay(200);
2472 }
2473
2474 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2475 {
2476         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2477         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2478         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2479
2480         assert_pipe_disabled(dev_priv, crtc->pipe);
2481         assert_dp_port_disabled(intel_dp);
2482         assert_edp_pll_enabled(dev_priv);
2483
2484         DRM_DEBUG_KMS("disabling eDP PLL\n");
2485
2486         intel_dp->DP &= ~DP_PLL_ENABLE;
2487
2488         I915_WRITE(DP_A, intel_dp->DP);
2489         POSTING_READ(DP_A);
2490         udelay(200);
2491 }
2492
2493 /* If the sink supports it, try to set the power state appropriately */
2494 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2495 {
2496         int ret, i;
2497
2498         /* Should have a valid DPCD by this point */
2499         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2500                 return;
2501
2502         if (mode != DRM_MODE_DPMS_ON) {
2503                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2504                                          DP_SET_POWER_D3);
2505         } else {
2506                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2507
2508                 /*
2509                  * When turning on, we need to retry for 1ms to give the sink
2510                  * time to wake up.
2511                  */
2512                 for (i = 0; i < 3; i++) {
2513                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2514                                                  DP_SET_POWER_D0);
2515                         if (ret == 1)
2516                                 break;
2517                         msleep(1);
2518                 }
2519
2520                 if (ret == 1 && lspcon->active)
2521                         lspcon_wait_pcon_mode(lspcon);
2522         }
2523
2524         if (ret != 1)
2525                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2526                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2527 }
2528
2529 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2530                                   enum pipe *pipe)
2531 {
2532         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2533         enum port port = dp_to_dig_port(intel_dp)->port;
2534         struct drm_device *dev = encoder->base.dev;
2535         struct drm_i915_private *dev_priv = to_i915(dev);
2536         u32 tmp;
2537         bool ret;
2538
2539         if (!intel_display_power_get_if_enabled(dev_priv,
2540                                                 encoder->power_domain))
2541                 return false;
2542
2543         ret = false;
2544
2545         tmp = I915_READ(intel_dp->output_reg);
2546
2547         if (!(tmp & DP_PORT_EN))
2548                 goto out;
2549
2550         if (IS_GEN7(dev_priv) && port == PORT_A) {
2551                 *pipe = PORT_TO_PIPE_CPT(tmp);
2552         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2553                 enum pipe p;
2554
2555                 for_each_pipe(dev_priv, p) {
2556                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2557                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2558                                 *pipe = p;
2559                                 ret = true;
2560
2561                                 goto out;
2562                         }
2563                 }
2564
2565                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2566                               i915_mmio_reg_offset(intel_dp->output_reg));
2567         } else if (IS_CHERRYVIEW(dev_priv)) {
2568                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2569         } else {
2570                 *pipe = PORT_TO_PIPE(tmp);
2571         }
2572
2573         ret = true;
2574
2575 out:
2576         intel_display_power_put(dev_priv, encoder->power_domain);
2577
2578         return ret;
2579 }
2580
2581 static void intel_dp_get_config(struct intel_encoder *encoder,
2582                                 struct intel_crtc_state *pipe_config)
2583 {
2584         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2585         u32 tmp, flags = 0;
2586         struct drm_device *dev = encoder->base.dev;
2587         struct drm_i915_private *dev_priv = to_i915(dev);
2588         enum port port = dp_to_dig_port(intel_dp)->port;
2589         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2590
2591         tmp = I915_READ(intel_dp->output_reg);
2592
2593         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2594
2595         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2596                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2597
2598                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2599                         flags |= DRM_MODE_FLAG_PHSYNC;
2600                 else
2601                         flags |= DRM_MODE_FLAG_NHSYNC;
2602
2603                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2604                         flags |= DRM_MODE_FLAG_PVSYNC;
2605                 else
2606                         flags |= DRM_MODE_FLAG_NVSYNC;
2607         } else {
2608                 if (tmp & DP_SYNC_HS_HIGH)
2609                         flags |= DRM_MODE_FLAG_PHSYNC;
2610                 else
2611                         flags |= DRM_MODE_FLAG_NHSYNC;
2612
2613                 if (tmp & DP_SYNC_VS_HIGH)
2614                         flags |= DRM_MODE_FLAG_PVSYNC;
2615                 else
2616                         flags |= DRM_MODE_FLAG_NVSYNC;
2617         }
2618
2619         pipe_config->base.adjusted_mode.flags |= flags;
2620
2621         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2622                 pipe_config->limited_color_range = true;
2623
2624         pipe_config->lane_count =
2625                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2626
2627         intel_dp_get_m_n(crtc, pipe_config);
2628
2629         if (port == PORT_A) {
2630                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2631                         pipe_config->port_clock = 162000;
2632                 else
2633                         pipe_config->port_clock = 270000;
2634         }
2635
2636         pipe_config->base.adjusted_mode.crtc_clock =
2637                 intel_dotclock_calculate(pipe_config->port_clock,
2638                                          &pipe_config->dp_m_n);
2639
2640         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2641             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2642                 /*
2643                  * This is a big fat ugly hack.
2644                  *
2645                  * Some machines in UEFI boot mode provide us a VBT that has 18
2646                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2647                  * unknown we fail to light up. Yet the same BIOS boots up with
2648                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2649                  * max, not what it tells us to use.
2650                  *
2651                  * Note: This will still be broken if the eDP panel is not lit
2652                  * up by the BIOS, and thus we can't get the mode at module
2653                  * load.
2654                  */
2655                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2656                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2657                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2658         }
2659 }
2660
2661 static void intel_disable_dp(struct intel_encoder *encoder,
2662                              struct intel_crtc_state *old_crtc_state,
2663                              struct drm_connector_state *old_conn_state)
2664 {
2665         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2666         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2667
2668         if (old_crtc_state->has_audio)
2669                 intel_audio_codec_disable(encoder);
2670
2671         if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2672                 intel_psr_disable(intel_dp);
2673
2674         /* Make sure the panel is off before trying to change the mode. But also
2675          * ensure that we have vdd while we switch off the panel. */
2676         intel_edp_panel_vdd_on(intel_dp);
2677         intel_edp_backlight_off(intel_dp);
2678         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2679         intel_edp_panel_off(intel_dp);
2680
2681         /* disable the port before the pipe on g4x */
2682         if (INTEL_GEN(dev_priv) < 5)
2683                 intel_dp_link_down(intel_dp);
2684 }
2685
2686 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2687                                 struct intel_crtc_state *old_crtc_state,
2688                                 struct drm_connector_state *old_conn_state)
2689 {
2690         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2691         enum port port = dp_to_dig_port(intel_dp)->port;
2692
2693         intel_dp_link_down(intel_dp);
2694
2695         /* Only ilk+ has port A */
2696         if (port == PORT_A)
2697                 ironlake_edp_pll_off(intel_dp);
2698 }
2699
2700 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2701                                 struct intel_crtc_state *old_crtc_state,
2702                                 struct drm_connector_state *old_conn_state)
2703 {
2704         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2705
2706         intel_dp_link_down(intel_dp);
2707 }
2708
2709 static void chv_post_disable_dp(struct intel_encoder *encoder,
2710                                 struct intel_crtc_state *old_crtc_state,
2711                                 struct drm_connector_state *old_conn_state)
2712 {
2713         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2714         struct drm_device *dev = encoder->base.dev;
2715         struct drm_i915_private *dev_priv = to_i915(dev);
2716
2717         intel_dp_link_down(intel_dp);
2718
2719         mutex_lock(&dev_priv->sb_lock);
2720
2721         /* Assert data lane reset */
2722         chv_data_lane_soft_reset(encoder, true);
2723
2724         mutex_unlock(&dev_priv->sb_lock);
2725 }
2726
2727 static void
2728 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2729                          uint32_t *DP,
2730                          uint8_t dp_train_pat)
2731 {
2732         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2733         struct drm_device *dev = intel_dig_port->base.base.dev;
2734         struct drm_i915_private *dev_priv = to_i915(dev);
2735         enum port port = intel_dig_port->port;
2736
2737         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2738                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2739                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2740
2741         if (HAS_DDI(dev_priv)) {
2742                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2743
2744                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2745                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2746                 else
2747                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2748
2749                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2750                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2751                 case DP_TRAINING_PATTERN_DISABLE:
2752                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2753
2754                         break;
2755                 case DP_TRAINING_PATTERN_1:
2756                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2757                         break;
2758                 case DP_TRAINING_PATTERN_2:
2759                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2760                         break;
2761                 case DP_TRAINING_PATTERN_3:
2762                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2763                         break;
2764                 }
2765                 I915_WRITE(DP_TP_CTL(port), temp);
2766
2767         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2768                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2769                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2770
2771                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2772                 case DP_TRAINING_PATTERN_DISABLE:
2773                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2774                         break;
2775                 case DP_TRAINING_PATTERN_1:
2776                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2777                         break;
2778                 case DP_TRAINING_PATTERN_2:
2779                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2780                         break;
2781                 case DP_TRAINING_PATTERN_3:
2782                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2783                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2784                         break;
2785                 }
2786
2787         } else {
2788                 if (IS_CHERRYVIEW(dev_priv))
2789                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2790                 else
2791                         *DP &= ~DP_LINK_TRAIN_MASK;
2792
2793                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2794                 case DP_TRAINING_PATTERN_DISABLE:
2795                         *DP |= DP_LINK_TRAIN_OFF;
2796                         break;
2797                 case DP_TRAINING_PATTERN_1:
2798                         *DP |= DP_LINK_TRAIN_PAT_1;
2799                         break;
2800                 case DP_TRAINING_PATTERN_2:
2801                         *DP |= DP_LINK_TRAIN_PAT_2;
2802                         break;
2803                 case DP_TRAINING_PATTERN_3:
2804                         if (IS_CHERRYVIEW(dev_priv)) {
2805                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2806                         } else {
2807                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2808                                 *DP |= DP_LINK_TRAIN_PAT_2;
2809                         }
2810                         break;
2811                 }
2812         }
2813 }
2814
2815 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2816                                  struct intel_crtc_state *old_crtc_state)
2817 {
2818         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2819         struct drm_i915_private *dev_priv = to_i915(dev);
2820
2821         /* enable with pattern 1 (as per spec) */
2822
2823         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2824
2825         /*
2826          * Magic for VLV/CHV. We _must_ first set up the register
2827          * without actually enabling the port, and then do another
2828          * write to enable the port. Otherwise link training will
2829          * fail when the power sequencer is freshly used for this port.
2830          */
2831         intel_dp->DP |= DP_PORT_EN;
2832         if (old_crtc_state->has_audio)
2833                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2834
2835         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2836         POSTING_READ(intel_dp->output_reg);
2837 }
2838
2839 static void intel_enable_dp(struct intel_encoder *encoder,
2840                             struct intel_crtc_state *pipe_config,
2841                             struct drm_connector_state *conn_state)
2842 {
2843         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2844         struct drm_device *dev = encoder->base.dev;
2845         struct drm_i915_private *dev_priv = to_i915(dev);
2846         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2847         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2848         enum pipe pipe = crtc->pipe;
2849
2850         if (WARN_ON(dp_reg & DP_PORT_EN))
2851                 return;
2852
2853         pps_lock(intel_dp);
2854
2855         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2856                 vlv_init_panel_power_sequencer(intel_dp);
2857
2858         intel_dp_enable_port(intel_dp, pipe_config);
2859
2860         edp_panel_vdd_on(intel_dp);
2861         edp_panel_on(intel_dp);
2862         edp_panel_vdd_off(intel_dp, true);
2863
2864         pps_unlock(intel_dp);
2865
2866         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2867                 unsigned int lane_mask = 0x0;
2868
2869                 if (IS_CHERRYVIEW(dev_priv))
2870                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2871
2872                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2873                                     lane_mask);
2874         }
2875
2876         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2877         intel_dp_start_link_train(intel_dp);
2878         intel_dp_stop_link_train(intel_dp);
2879
2880         if (pipe_config->has_audio) {
2881                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2882                                  pipe_name(pipe));
2883                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2884         }
2885 }
2886
2887 static void g4x_enable_dp(struct intel_encoder *encoder,
2888                           struct intel_crtc_state *pipe_config,
2889                           struct drm_connector_state *conn_state)
2890 {
2891         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2892
2893         intel_enable_dp(encoder, pipe_config, conn_state);
2894         intel_edp_backlight_on(intel_dp);
2895 }
2896
2897 static void vlv_enable_dp(struct intel_encoder *encoder,
2898                           struct intel_crtc_state *pipe_config,
2899                           struct drm_connector_state *conn_state)
2900 {
2901         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2902
2903         intel_edp_backlight_on(intel_dp);
2904         intel_psr_enable(intel_dp);
2905 }
2906
2907 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2908                               struct intel_crtc_state *pipe_config,
2909                               struct drm_connector_state *conn_state)
2910 {
2911         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2912         enum port port = dp_to_dig_port(intel_dp)->port;
2913
2914         intel_dp_prepare(encoder, pipe_config);
2915
2916         /* Only ilk+ has port A */
2917         if (port == PORT_A)
2918                 ironlake_edp_pll_on(intel_dp, pipe_config);
2919 }
2920
2921 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2922 {
2923         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2924         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2925         enum pipe pipe = intel_dp->pps_pipe;
2926         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2927
2928         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2929
2930         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2931                 return;
2932
2933         edp_panel_vdd_off_sync(intel_dp);
2934
2935         /*
2936          * VLV seems to get confused when multiple power seqeuencers
2937          * have the same port selected (even if only one has power/vdd
2938          * enabled). The failure manifests as vlv_wait_port_ready() failing
2939          * CHV on the other hand doesn't seem to mind having the same port
2940          * selected in multiple power seqeuencers, but let's clear the
2941          * port select always when logically disconnecting a power sequencer
2942          * from a port.
2943          */
2944         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2945                       pipe_name(pipe), port_name(intel_dig_port->port));
2946         I915_WRITE(pp_on_reg, 0);
2947         POSTING_READ(pp_on_reg);
2948
2949         intel_dp->pps_pipe = INVALID_PIPE;
2950 }
2951
2952 static void vlv_steal_power_sequencer(struct drm_device *dev,
2953                                       enum pipe pipe)
2954 {
2955         struct drm_i915_private *dev_priv = to_i915(dev);
2956         struct intel_encoder *encoder;
2957
2958         lockdep_assert_held(&dev_priv->pps_mutex);
2959
2960         for_each_intel_encoder(dev, encoder) {
2961                 struct intel_dp *intel_dp;
2962                 enum port port;
2963
2964                 if (encoder->type != INTEL_OUTPUT_DP &&
2965                     encoder->type != INTEL_OUTPUT_EDP)
2966                         continue;
2967
2968                 intel_dp = enc_to_intel_dp(&encoder->base);
2969                 port = dp_to_dig_port(intel_dp)->port;
2970
2971                 WARN(intel_dp->active_pipe == pipe,
2972                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
2973                      pipe_name(pipe), port_name(port));
2974
2975                 if (intel_dp->pps_pipe != pipe)
2976                         continue;
2977
2978                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2979                               pipe_name(pipe), port_name(port));
2980
2981                 /* make sure vdd is off before we steal it */
2982                 vlv_detach_power_sequencer(intel_dp);
2983         }
2984 }
2985
2986 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2987 {
2988         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2989         struct intel_encoder *encoder = &intel_dig_port->base;
2990         struct drm_device *dev = encoder->base.dev;
2991         struct drm_i915_private *dev_priv = to_i915(dev);
2992         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2993
2994         lockdep_assert_held(&dev_priv->pps_mutex);
2995
2996         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2997
2998         if (intel_dp->pps_pipe != INVALID_PIPE &&
2999             intel_dp->pps_pipe != crtc->pipe) {
3000                 /*
3001                  * If another power sequencer was being used on this
3002                  * port previously make sure to turn off vdd there while
3003                  * we still have control of it.
3004                  */
3005                 vlv_detach_power_sequencer(intel_dp);
3006         }
3007
3008         /*
3009          * We may be stealing the power
3010          * sequencer from another port.
3011          */
3012         vlv_steal_power_sequencer(dev, crtc->pipe);
3013
3014         intel_dp->active_pipe = crtc->pipe;
3015
3016         if (!is_edp(intel_dp))
3017                 return;
3018
3019         /* now it's all ours */
3020         intel_dp->pps_pipe = crtc->pipe;
3021
3022         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3023                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
3024
3025         /* init power sequencer on this pipe and port */
3026         intel_dp_init_panel_power_sequencer(dev, intel_dp);
3027         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
3028 }
3029
3030 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3031                               struct intel_crtc_state *pipe_config,
3032                               struct drm_connector_state *conn_state)
3033 {
3034         vlv_phy_pre_encoder_enable(encoder);
3035
3036         intel_enable_dp(encoder, pipe_config, conn_state);
3037 }
3038
3039 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3040                                   struct intel_crtc_state *pipe_config,
3041                                   struct drm_connector_state *conn_state)
3042 {
3043         intel_dp_prepare(encoder, pipe_config);
3044
3045         vlv_phy_pre_pll_enable(encoder);
3046 }
3047
3048 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3049                               struct intel_crtc_state *pipe_config,
3050                               struct drm_connector_state *conn_state)
3051 {
3052         chv_phy_pre_encoder_enable(encoder);
3053
3054         intel_enable_dp(encoder, pipe_config, conn_state);
3055
3056         /* Second common lane will stay alive on its own now */
3057         chv_phy_release_cl2_override(encoder);
3058 }
3059
3060 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3061                                   struct intel_crtc_state *pipe_config,
3062                                   struct drm_connector_state *conn_state)
3063 {
3064         intel_dp_prepare(encoder, pipe_config);
3065
3066         chv_phy_pre_pll_enable(encoder);
3067 }
3068
3069 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3070                                     struct intel_crtc_state *pipe_config,
3071                                     struct drm_connector_state *conn_state)
3072 {
3073         chv_phy_post_pll_disable(encoder);
3074 }
3075
3076 /*
3077  * Fetch AUX CH registers 0x202 - 0x207 which contain
3078  * link status information
3079  */
3080 bool
3081 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3082 {
3083         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3084                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3085 }
3086
3087 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3088 {
3089         uint8_t psr_caps = 0;
3090
3091         drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
3092         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3093 }
3094
3095 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3096 {
3097         uint8_t dprx = 0;
3098
3099         drm_dp_dpcd_readb(&intel_dp->aux,
3100                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3101                         &dprx);
3102         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3103 }
3104
3105 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3106 {
3107         uint8_t alpm_caps = 0;
3108
3109         drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
3110         return alpm_caps & DP_ALPM_CAP;
3111 }
3112
3113 /* These are source-specific values. */
3114 uint8_t
3115 intel_dp_voltage_max(struct intel_dp *intel_dp)
3116 {
3117         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3118         enum port port = dp_to_dig_port(intel_dp)->port;
3119
3120         if (IS_GEN9_LP(dev_priv))
3121                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3122         else if (INTEL_GEN(dev_priv) >= 9) {
3123                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3124                 return intel_ddi_dp_voltage_max(encoder);
3125         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3126                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3127         else if (IS_GEN7(dev_priv) && port == PORT_A)
3128                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3129         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3130                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3131         else
3132                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3133 }
3134
3135 uint8_t
3136 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3137 {
3138         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3139         enum port port = dp_to_dig_port(intel_dp)->port;
3140
3141         if (INTEL_GEN(dev_priv) >= 9) {
3142                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3143                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3144                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3145                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3146                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3147                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3148                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3149                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3150                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3151                 default:
3152                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3153                 }
3154         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3155                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3156                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3157                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3158                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3159                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3160                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3161                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3162                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3163                 default:
3164                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3165                 }
3166         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3167                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3168                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3169                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3170                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3171                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3172                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3173                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3174                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3175                 default:
3176                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3177                 }
3178         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3179                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3180                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3181                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3182                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3183                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3184                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3185                 default:
3186                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3187                 }
3188         } else {
3189                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3190                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3191                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3192                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3193                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3194                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3195                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3196                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3197                 default:
3198                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3199                 }
3200         }
3201 }
3202
3203 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3204 {
3205         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3206         unsigned long demph_reg_value, preemph_reg_value,
3207                 uniqtranscale_reg_value;
3208         uint8_t train_set = intel_dp->train_set[0];
3209
3210         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3211         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3212                 preemph_reg_value = 0x0004000;
3213                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3214                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3215                         demph_reg_value = 0x2B405555;
3216                         uniqtranscale_reg_value = 0x552AB83A;
3217                         break;
3218                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3219                         demph_reg_value = 0x2B404040;
3220                         uniqtranscale_reg_value = 0x5548B83A;
3221                         break;
3222                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3223                         demph_reg_value = 0x2B245555;
3224                         uniqtranscale_reg_value = 0x5560B83A;
3225                         break;
3226                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3227                         demph_reg_value = 0x2B405555;
3228                         uniqtranscale_reg_value = 0x5598DA3A;
3229                         break;
3230                 default:
3231                         return 0;
3232                 }
3233                 break;
3234         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3235                 preemph_reg_value = 0x0002000;
3236                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3237                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3238                         demph_reg_value = 0x2B404040;
3239                         uniqtranscale_reg_value = 0x5552B83A;
3240                         break;
3241                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3242                         demph_reg_value = 0x2B404848;
3243                         uniqtranscale_reg_value = 0x5580B83A;
3244                         break;
3245                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3246                         demph_reg_value = 0x2B404040;
3247                         uniqtranscale_reg_value = 0x55ADDA3A;
3248                         break;
3249                 default:
3250                         return 0;
3251                 }
3252                 break;
3253         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3254                 preemph_reg_value = 0x0000000;
3255                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3256                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3257                         demph_reg_value = 0x2B305555;
3258                         uniqtranscale_reg_value = 0x5570B83A;
3259                         break;
3260                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3261                         demph_reg_value = 0x2B2B4040;
3262                         uniqtranscale_reg_value = 0x55ADDA3A;
3263                         break;
3264                 default:
3265                         return 0;
3266                 }
3267                 break;
3268         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3269                 preemph_reg_value = 0x0006000;
3270                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3271                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3272                         demph_reg_value = 0x1B405555;
3273                         uniqtranscale_reg_value = 0x55ADDA3A;
3274                         break;
3275                 default:
3276                         return 0;
3277                 }
3278                 break;
3279         default:
3280                 return 0;
3281         }
3282
3283         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3284                                  uniqtranscale_reg_value, 0);
3285
3286         return 0;
3287 }
3288
3289 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3290 {
3291         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3292         u32 deemph_reg_value, margin_reg_value;
3293         bool uniq_trans_scale = false;
3294         uint8_t train_set = intel_dp->train_set[0];
3295
3296         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3297         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3298                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3299                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3300                         deemph_reg_value = 128;
3301                         margin_reg_value = 52;
3302                         break;
3303                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3304                         deemph_reg_value = 128;
3305                         margin_reg_value = 77;
3306                         break;
3307                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3308                         deemph_reg_value = 128;
3309                         margin_reg_value = 102;
3310                         break;
3311                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3312                         deemph_reg_value = 128;
3313                         margin_reg_value = 154;
3314                         uniq_trans_scale = true;
3315                         break;
3316                 default:
3317                         return 0;
3318                 }
3319                 break;
3320         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3321                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3322                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3323                         deemph_reg_value = 85;
3324                         margin_reg_value = 78;
3325                         break;
3326                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3327                         deemph_reg_value = 85;
3328                         margin_reg_value = 116;
3329                         break;
3330                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3331                         deemph_reg_value = 85;
3332                         margin_reg_value = 154;
3333                         break;
3334                 default:
3335                         return 0;
3336                 }
3337                 break;
3338         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3339                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3340                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3341                         deemph_reg_value = 64;
3342                         margin_reg_value = 104;
3343                         break;
3344                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3345                         deemph_reg_value = 64;
3346                         margin_reg_value = 154;
3347                         break;
3348                 default:
3349                         return 0;
3350                 }
3351                 break;
3352         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3353                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3354                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3355                         deemph_reg_value = 43;
3356                         margin_reg_value = 154;
3357                         break;
3358                 default:
3359                         return 0;
3360                 }
3361                 break;
3362         default:
3363                 return 0;
3364         }
3365
3366         chv_set_phy_signal_level(encoder, deemph_reg_value,
3367                                  margin_reg_value, uniq_trans_scale);
3368
3369         return 0;
3370 }
3371
3372 static uint32_t
3373 gen4_signal_levels(uint8_t train_set)
3374 {
3375         uint32_t        signal_levels = 0;
3376
3377         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3378         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3379         default:
3380                 signal_levels |= DP_VOLTAGE_0_4;
3381                 break;
3382         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3383                 signal_levels |= DP_VOLTAGE_0_6;
3384                 break;
3385         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3386                 signal_levels |= DP_VOLTAGE_0_8;
3387                 break;
3388         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3389                 signal_levels |= DP_VOLTAGE_1_2;
3390                 break;
3391         }
3392         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3393         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3394         default:
3395                 signal_levels |= DP_PRE_EMPHASIS_0;
3396                 break;
3397         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3398                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3399                 break;
3400         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3401                 signal_levels |= DP_PRE_EMPHASIS_6;
3402                 break;
3403         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3404                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3405                 break;
3406         }
3407         return signal_levels;
3408 }
3409
3410 /* Gen6's DP voltage swing and pre-emphasis control */
3411 static uint32_t
3412 gen6_edp_signal_levels(uint8_t train_set)
3413 {
3414         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3415                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3416         switch (signal_levels) {
3417         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3418         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3419                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3420         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3421                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3422         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3423         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3424                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3425         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3426         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3427                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3428         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3429         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3430                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3431         default:
3432                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3433                               "0x%x\n", signal_levels);
3434                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3435         }
3436 }
3437
3438 /* Gen7's DP voltage swing and pre-emphasis control */
3439 static uint32_t
3440 gen7_edp_signal_levels(uint8_t train_set)
3441 {
3442         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3443                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3444         switch (signal_levels) {
3445         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3446                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3447         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3448                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3449         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3450                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3451
3452         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3453                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3454         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3455                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3456
3457         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3458                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3459         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3460                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3461
3462         default:
3463                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3464                               "0x%x\n", signal_levels);
3465                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3466         }
3467 }
3468
3469 void
3470 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3471 {
3472         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3473         enum port port = intel_dig_port->port;
3474         struct drm_device *dev = intel_dig_port->base.base.dev;
3475         struct drm_i915_private *dev_priv = to_i915(dev);
3476         uint32_t signal_levels, mask = 0;
3477         uint8_t train_set = intel_dp->train_set[0];
3478
3479         if (HAS_DDI(dev_priv)) {
3480                 signal_levels = ddi_signal_levels(intel_dp);
3481
3482                 if (IS_GEN9_LP(dev_priv))
3483                         signal_levels = 0;
3484                 else
3485                         mask = DDI_BUF_EMP_MASK;
3486         } else if (IS_CHERRYVIEW(dev_priv)) {
3487                 signal_levels = chv_signal_levels(intel_dp);
3488         } else if (IS_VALLEYVIEW(dev_priv)) {
3489                 signal_levels = vlv_signal_levels(intel_dp);
3490         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3491                 signal_levels = gen7_edp_signal_levels(train_set);
3492                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3493         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3494                 signal_levels = gen6_edp_signal_levels(train_set);
3495                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3496         } else {
3497                 signal_levels = gen4_signal_levels(train_set);
3498                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3499         }
3500
3501         if (mask)
3502                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3503
3504         DRM_DEBUG_KMS("Using vswing level %d\n",
3505                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3506         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3507                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3508                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3509
3510         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3511
3512         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3513         POSTING_READ(intel_dp->output_reg);
3514 }
3515
3516 void
3517 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3518                                        uint8_t dp_train_pat)
3519 {
3520         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3521         struct drm_i915_private *dev_priv =
3522                 to_i915(intel_dig_port->base.base.dev);
3523
3524         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3525
3526         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3527         POSTING_READ(intel_dp->output_reg);
3528 }
3529
3530 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3531 {
3532         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3533         struct drm_device *dev = intel_dig_port->base.base.dev;
3534         struct drm_i915_private *dev_priv = to_i915(dev);
3535         enum port port = intel_dig_port->port;
3536         uint32_t val;
3537
3538         if (!HAS_DDI(dev_priv))
3539                 return;
3540
3541         val = I915_READ(DP_TP_CTL(port));
3542         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3543         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3544         I915_WRITE(DP_TP_CTL(port), val);
3545
3546         /*
3547          * On PORT_A we can have only eDP in SST mode. There the only reason
3548          * we need to set idle transmission mode is to work around a HW issue
3549          * where we enable the pipe while not in idle link-training mode.
3550          * In this case there is requirement to wait for a minimum number of
3551          * idle patterns to be sent.
3552          */
3553         if (port == PORT_A)
3554                 return;
3555
3556         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3557                                     DP_TP_STATUS_IDLE_DONE,
3558                                     DP_TP_STATUS_IDLE_DONE,
3559                                     1))
3560                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3561 }
3562
3563 static void
3564 intel_dp_link_down(struct intel_dp *intel_dp)
3565 {
3566         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3567         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3568         enum port port = intel_dig_port->port;
3569         struct drm_device *dev = intel_dig_port->base.base.dev;
3570         struct drm_i915_private *dev_priv = to_i915(dev);
3571         uint32_t DP = intel_dp->DP;
3572
3573         if (WARN_ON(HAS_DDI(dev_priv)))
3574                 return;
3575
3576         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3577                 return;
3578
3579         DRM_DEBUG_KMS("\n");
3580
3581         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3582             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3583                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3584                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3585         } else {
3586                 if (IS_CHERRYVIEW(dev_priv))
3587                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3588                 else
3589                         DP &= ~DP_LINK_TRAIN_MASK;
3590                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3591         }
3592         I915_WRITE(intel_dp->output_reg, DP);
3593         POSTING_READ(intel_dp->output_reg);
3594
3595         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3596         I915_WRITE(intel_dp->output_reg, DP);
3597         POSTING_READ(intel_dp->output_reg);
3598
3599         /*
3600          * HW workaround for IBX, we need to move the port
3601          * to transcoder A after disabling it to allow the
3602          * matching HDMI port to be enabled on transcoder A.
3603          */
3604         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3605                 /*
3606                  * We get CPU/PCH FIFO underruns on the other pipe when
3607                  * doing the workaround. Sweep them under the rug.
3608                  */
3609                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3610                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3611
3612                 /* always enable with pattern 1 (as per spec) */
3613                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3614                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3615                 I915_WRITE(intel_dp->output_reg, DP);
3616                 POSTING_READ(intel_dp->output_reg);
3617
3618                 DP &= ~DP_PORT_EN;
3619                 I915_WRITE(intel_dp->output_reg, DP);
3620                 POSTING_READ(intel_dp->output_reg);
3621
3622                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3623                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3624                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3625         }
3626
3627         msleep(intel_dp->panel_power_down_delay);
3628
3629         intel_dp->DP = DP;
3630
3631         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3632                 pps_lock(intel_dp);
3633                 intel_dp->active_pipe = INVALID_PIPE;
3634                 pps_unlock(intel_dp);
3635         }
3636 }
3637
3638 bool
3639 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3640 {
3641         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3642                              sizeof(intel_dp->dpcd)) < 0)
3643                 return false; /* aux transfer failed */
3644
3645         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3646
3647         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3648 }
3649
3650 static bool
3651 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3652 {
3653         struct drm_i915_private *dev_priv =
3654                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3655
3656         /* this function is meant to be called only once */
3657         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3658
3659         if (!intel_dp_read_dpcd(intel_dp))
3660                 return false;
3661
3662         intel_dp_read_desc(intel_dp);
3663
3664         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3665                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3666                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3667
3668         /* Check if the panel supports PSR */
3669         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3670                          intel_dp->psr_dpcd,
3671                          sizeof(intel_dp->psr_dpcd));
3672         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3673                 dev_priv->psr.sink_support = true;
3674                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3675         }
3676
3677         if (INTEL_GEN(dev_priv) >= 9 &&
3678             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3679                 uint8_t frame_sync_cap;
3680
3681                 dev_priv->psr.sink_support = true;
3682                 drm_dp_dpcd_readb(&intel_dp->aux,
3683                                   DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3684                                   &frame_sync_cap);
3685                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3686                 /* PSR2 needs frame sync as well */
3687                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3688                 DRM_DEBUG_KMS("PSR2 %s on sink",
3689                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3690
3691                 if (dev_priv->psr.psr2_support) {
3692                         dev_priv->psr.y_cord_support =
3693                                 intel_dp_get_y_cord_status(intel_dp);
3694                         dev_priv->psr.colorimetry_support =
3695                                 intel_dp_get_colorimetry_status(intel_dp);
3696                         dev_priv->psr.alpm =
3697                                 intel_dp_get_alpm_status(intel_dp);
3698                 }
3699
3700         }
3701
3702         /* Read the eDP Display control capabilities registers */
3703         if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3704             drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3705                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3706                              sizeof(intel_dp->edp_dpcd))
3707                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3708                               intel_dp->edp_dpcd);
3709
3710         /* Intermediate frequency support */
3711         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3712                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3713                 int i;
3714
3715                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3716                                 sink_rates, sizeof(sink_rates));
3717
3718                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3719                         int val = le16_to_cpu(sink_rates[i]);
3720
3721                         if (val == 0)
3722                                 break;
3723
3724                         /* Value read multiplied by 200kHz gives the per-lane
3725                          * link rate in kHz. The source rates are, however,
3726                          * stored in terms of LS_Clk kHz. The full conversion
3727                          * back to symbols is
3728                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3729                          */
3730                         intel_dp->sink_rates[i] = (val * 200) / 10;
3731                 }
3732                 intel_dp->num_sink_rates = i;
3733         }
3734
3735         if (intel_dp->num_sink_rates)
3736                 intel_dp->use_rate_select = true;
3737         else
3738                 intel_dp_set_sink_rates(intel_dp);
3739
3740         intel_dp_set_common_rates(intel_dp);
3741
3742         return true;
3743 }
3744
3745
3746 static bool
3747 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3748 {
3749         u8 sink_count;
3750
3751         if (!intel_dp_read_dpcd(intel_dp))
3752                 return false;
3753
3754         /* Don't clobber cached eDP rates. */
3755         if (!is_edp(intel_dp)) {
3756                 intel_dp_set_sink_rates(intel_dp);
3757                 intel_dp_set_common_rates(intel_dp);
3758         }
3759
3760         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3761                 return false;
3762
3763         /*
3764          * Sink count can change between short pulse hpd hence
3765          * a member variable in intel_dp will track any changes
3766          * between short pulse interrupts.
3767          */
3768         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3769
3770         /*
3771          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3772          * a dongle is present but no display. Unless we require to know
3773          * if a dongle is present or not, we don't need to update
3774          * downstream port information. So, an early return here saves
3775          * time from performing other operations which are not required.
3776          */
3777         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3778                 return false;
3779
3780         if (!drm_dp_is_branch(intel_dp->dpcd))
3781                 return true; /* native DP sink */
3782
3783         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3784                 return true; /* no per-port downstream info */
3785
3786         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3787                              intel_dp->downstream_ports,
3788                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3789                 return false; /* downstream port status fetch failed */
3790
3791         return true;
3792 }
3793
3794 static bool
3795 intel_dp_can_mst(struct intel_dp *intel_dp)
3796 {
3797         u8 mstm_cap;
3798
3799         if (!i915.enable_dp_mst)
3800                 return false;
3801
3802         if (!intel_dp->can_mst)
3803                 return false;
3804
3805         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3806                 return false;
3807
3808         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3809                 return false;
3810
3811         return mstm_cap & DP_MST_CAP;
3812 }
3813
3814 static void
3815 intel_dp_configure_mst(struct intel_dp *intel_dp)
3816 {
3817         if (!i915.enable_dp_mst)
3818                 return;
3819
3820         if (!intel_dp->can_mst)
3821                 return;
3822
3823         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3824
3825         if (intel_dp->is_mst)
3826                 DRM_DEBUG_KMS("Sink is MST capable\n");
3827         else
3828                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3829
3830         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3831                                         intel_dp->is_mst);
3832 }
3833
3834 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3835 {
3836         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3837         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3838         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3839         u8 buf;
3840         int ret = 0;
3841         int count = 0;
3842         int attempts = 10;
3843
3844         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3845                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3846                 ret = -EIO;
3847                 goto out;
3848         }
3849
3850         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3851                                buf & ~DP_TEST_SINK_START) < 0) {
3852                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3853                 ret = -EIO;
3854                 goto out;
3855         }
3856
3857         do {
3858                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3859
3860                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3861                                       DP_TEST_SINK_MISC, &buf) < 0) {
3862                         ret = -EIO;
3863                         goto out;
3864                 }
3865                 count = buf & DP_TEST_COUNT_MASK;
3866         } while (--attempts && count);
3867
3868         if (attempts == 0) {
3869                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3870                 ret = -ETIMEDOUT;
3871         }
3872
3873  out:
3874         hsw_enable_ips(intel_crtc);
3875         return ret;
3876 }
3877
3878 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3879 {
3880         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3881         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3882         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3883         u8 buf;
3884         int ret;
3885
3886         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3887                 return -EIO;
3888
3889         if (!(buf & DP_TEST_CRC_SUPPORTED))
3890                 return -ENOTTY;
3891
3892         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3893                 return -EIO;
3894
3895         if (buf & DP_TEST_SINK_START) {
3896                 ret = intel_dp_sink_crc_stop(intel_dp);
3897                 if (ret)
3898                         return ret;
3899         }
3900
3901         hsw_disable_ips(intel_crtc);
3902
3903         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3904                                buf | DP_TEST_SINK_START) < 0) {
3905                 hsw_enable_ips(intel_crtc);
3906                 return -EIO;
3907         }
3908
3909         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3910         return 0;
3911 }
3912
3913 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3914 {
3915         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3916         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3917         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3918         u8 buf;
3919         int count, ret;
3920         int attempts = 6;
3921
3922         ret = intel_dp_sink_crc_start(intel_dp);
3923         if (ret)
3924                 return ret;
3925
3926         do {
3927                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3928
3929                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3930                                       DP_TEST_SINK_MISC, &buf) < 0) {
3931                         ret = -EIO;
3932                         goto stop;
3933                 }
3934                 count = buf & DP_TEST_COUNT_MASK;
3935
3936         } while (--attempts && count == 0);
3937
3938         if (attempts == 0) {
3939                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3940                 ret = -ETIMEDOUT;
3941                 goto stop;
3942         }
3943
3944         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3945                 ret = -EIO;
3946                 goto stop;
3947         }
3948
3949 stop:
3950         intel_dp_sink_crc_stop(intel_dp);
3951         return ret;
3952 }
3953
3954 static bool
3955 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3956 {
3957         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3958                                  sink_irq_vector) == 1;
3959 }
3960
3961 static bool
3962 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3963 {
3964         int ret;
3965
3966         ret = drm_dp_dpcd_read(&intel_dp->aux,
3967                                              DP_SINK_COUNT_ESI,
3968                                              sink_irq_vector, 14);
3969         if (ret != 14)
3970                 return false;
3971
3972         return true;
3973 }
3974
3975 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3976 {
3977         int status = 0;
3978         int min_lane_count = 1;
3979         int link_rate_index, test_link_rate;
3980         uint8_t test_lane_count, test_link_bw;
3981         /* (DP CTS 1.2)
3982          * 4.3.1.11
3983          */
3984         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3985         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3986                                    &test_lane_count);
3987
3988         if (status <= 0) {
3989                 DRM_DEBUG_KMS("Lane count read failed\n");
3990                 return DP_TEST_NAK;
3991         }
3992         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3993         /* Validate the requested lane count */
3994         if (test_lane_count < min_lane_count ||
3995             test_lane_count > intel_dp->max_link_lane_count)
3996                 return DP_TEST_NAK;
3997
3998         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3999                                    &test_link_bw);
4000         if (status <= 0) {
4001                 DRM_DEBUG_KMS("Link Rate read failed\n");
4002                 return DP_TEST_NAK;
4003         }
4004         /* Validate the requested link rate */
4005         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4006         link_rate_index = intel_dp_rate_index(intel_dp->common_rates,
4007                                               intel_dp->num_common_rates,
4008                                               test_link_rate);
4009         if (link_rate_index < 0)
4010                 return DP_TEST_NAK;
4011
4012         intel_dp->compliance.test_lane_count = test_lane_count;
4013         intel_dp->compliance.test_link_rate = test_link_rate;
4014
4015         return DP_TEST_ACK;
4016 }
4017
4018 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4019 {
4020         uint8_t test_pattern;
4021         uint8_t test_misc;
4022         __be16 h_width, v_height;
4023         int status = 0;
4024
4025         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4026         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4027                                    &test_pattern);
4028         if (status <= 0) {
4029                 DRM_DEBUG_KMS("Test pattern read failed\n");
4030                 return DP_TEST_NAK;
4031         }
4032         if (test_pattern != DP_COLOR_RAMP)
4033                 return DP_TEST_NAK;
4034
4035         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4036                                   &h_width, 2);
4037         if (status <= 0) {
4038                 DRM_DEBUG_KMS("H Width read failed\n");
4039                 return DP_TEST_NAK;
4040         }
4041
4042         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4043                                   &v_height, 2);
4044         if (status <= 0) {
4045                 DRM_DEBUG_KMS("V Height read failed\n");
4046                 return DP_TEST_NAK;
4047         }
4048
4049         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4050                                    &test_misc);
4051         if (status <= 0) {
4052                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4053                 return DP_TEST_NAK;
4054         }
4055         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4056                 return DP_TEST_NAK;
4057         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4058                 return DP_TEST_NAK;
4059         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4060         case DP_TEST_BIT_DEPTH_6:
4061                 intel_dp->compliance.test_data.bpc = 6;
4062                 break;
4063         case DP_TEST_BIT_DEPTH_8:
4064                 intel_dp->compliance.test_data.bpc = 8;
4065                 break;
4066         default:
4067                 return DP_TEST_NAK;
4068         }
4069
4070         intel_dp->compliance.test_data.video_pattern = test_pattern;
4071         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4072         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4073         /* Set test active flag here so userspace doesn't interrupt things */
4074         intel_dp->compliance.test_active = 1;
4075
4076         return DP_TEST_ACK;
4077 }
4078
4079 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4080 {
4081         uint8_t test_result = DP_TEST_ACK;
4082         struct intel_connector *intel_connector = intel_dp->attached_connector;
4083         struct drm_connector *connector = &intel_connector->base;
4084
4085         if (intel_connector->detect_edid == NULL ||
4086             connector->edid_corrupt ||
4087             intel_dp->aux.i2c_defer_count > 6) {
4088                 /* Check EDID read for NACKs, DEFERs and corruption
4089                  * (DP CTS 1.2 Core r1.1)
4090                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4091                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4092                  *    4.2.2.6 : EDID corruption detected
4093                  * Use failsafe mode for all cases
4094                  */
4095                 if (intel_dp->aux.i2c_nack_count > 0 ||
4096                         intel_dp->aux.i2c_defer_count > 0)
4097                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4098                                       intel_dp->aux.i2c_nack_count,
4099                                       intel_dp->aux.i2c_defer_count);
4100                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4101         } else {
4102                 struct edid *block = intel_connector->detect_edid;
4103
4104                 /* We have to write the checksum
4105                  * of the last block read
4106                  */
4107                 block += intel_connector->detect_edid->extensions;
4108
4109                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4110                                        block->checksum) <= 0)
4111                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4112
4113                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4114                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4115         }
4116
4117         /* Set test active flag here so userspace doesn't interrupt things */
4118         intel_dp->compliance.test_active = 1;
4119
4120         return test_result;
4121 }
4122
4123 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4124 {
4125         uint8_t test_result = DP_TEST_NAK;
4126         return test_result;
4127 }
4128
4129 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4130 {
4131         uint8_t response = DP_TEST_NAK;
4132         uint8_t request = 0;
4133         int status;
4134
4135         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4136         if (status <= 0) {
4137                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4138                 goto update_status;
4139         }
4140
4141         switch (request) {
4142         case DP_TEST_LINK_TRAINING:
4143                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4144                 response = intel_dp_autotest_link_training(intel_dp);
4145                 break;
4146         case DP_TEST_LINK_VIDEO_PATTERN:
4147                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4148                 response = intel_dp_autotest_video_pattern(intel_dp);
4149                 break;
4150         case DP_TEST_LINK_EDID_READ:
4151                 DRM_DEBUG_KMS("EDID test requested\n");
4152                 response = intel_dp_autotest_edid(intel_dp);
4153                 break;
4154         case DP_TEST_LINK_PHY_TEST_PATTERN:
4155                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4156                 response = intel_dp_autotest_phy_pattern(intel_dp);
4157                 break;
4158         default:
4159                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4160                 break;
4161         }
4162
4163         if (response & DP_TEST_ACK)
4164                 intel_dp->compliance.test_type = request;
4165
4166 update_status:
4167         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4168         if (status <= 0)
4169                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4170 }
4171
4172 static int
4173 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4174 {
4175         bool bret;
4176
4177         if (intel_dp->is_mst) {
4178                 u8 esi[16] = { 0 };
4179                 int ret = 0;
4180                 int retry;
4181                 bool handled;
4182                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4183 go_again:
4184                 if (bret == true) {
4185
4186                         /* check link status - esi[10] = 0x200c */
4187                         if (intel_dp->active_mst_links &&
4188                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4189                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4190                                 intel_dp_start_link_train(intel_dp);
4191                                 intel_dp_stop_link_train(intel_dp);
4192                         }
4193
4194                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4195                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4196
4197                         if (handled) {
4198                                 for (retry = 0; retry < 3; retry++) {
4199                                         int wret;
4200                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4201                                                                  DP_SINK_COUNT_ESI+1,
4202                                                                  &esi[1], 3);
4203                                         if (wret == 3) {
4204                                                 break;
4205                                         }
4206                                 }
4207
4208                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4209                                 if (bret == true) {
4210                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4211                                         goto go_again;
4212                                 }
4213                         } else
4214                                 ret = 0;
4215
4216                         return ret;
4217                 } else {
4218                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4219                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4220                         intel_dp->is_mst = false;
4221                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4222                         /* send a hotplug event */
4223                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4224                 }
4225         }
4226         return -EINVAL;
4227 }
4228
4229 static void
4230 intel_dp_retrain_link(struct intel_dp *intel_dp)
4231 {
4232         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4234         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4235
4236         /* Suppress underruns caused by re-training */
4237         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4238         if (crtc->config->has_pch_encoder)
4239                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4240                                                       intel_crtc_pch_transcoder(crtc), false);
4241
4242         intel_dp_start_link_train(intel_dp);
4243         intel_dp_stop_link_train(intel_dp);
4244
4245         /* Keep underrun reporting disabled until things are stable */
4246         intel_wait_for_vblank(dev_priv, crtc->pipe);
4247
4248         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4249         if (crtc->config->has_pch_encoder)
4250                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4251                                                       intel_crtc_pch_transcoder(crtc), true);
4252 }
4253
4254 static void
4255 intel_dp_check_link_status(struct intel_dp *intel_dp)
4256 {
4257         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4258         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4259         u8 link_status[DP_LINK_STATUS_SIZE];
4260
4261         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4262
4263         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4264                 DRM_ERROR("Failed to get link status\n");
4265                 return;
4266         }
4267
4268         if (!intel_encoder->base.crtc)
4269                 return;
4270
4271         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4272                 return;
4273
4274         /*
4275          * Validate the cached values of intel_dp->link_rate and
4276          * intel_dp->lane_count before attempting to retrain.
4277          */
4278         if (!intel_dp_link_params_valid(intel_dp))
4279                 return;
4280
4281         /* Retrain if Channel EQ or CR not ok */
4282         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4283                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4284                               intel_encoder->base.name);
4285
4286                 intel_dp_retrain_link(intel_dp);
4287         }
4288 }
4289
4290 /*
4291  * According to DP spec
4292  * 5.1.2:
4293  *  1. Read DPCD
4294  *  2. Configure link according to Receiver Capabilities
4295  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4296  *  4. Check link status on receipt of hot-plug interrupt
4297  *
4298  * intel_dp_short_pulse -  handles short pulse interrupts
4299  * when full detection is not required.
4300  * Returns %true if short pulse is handled and full detection
4301  * is NOT required and %false otherwise.
4302  */
4303 static bool
4304 intel_dp_short_pulse(struct intel_dp *intel_dp)
4305 {
4306         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4307         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4308         u8 sink_irq_vector = 0;
4309         u8 old_sink_count = intel_dp->sink_count;
4310         bool ret;
4311
4312         /*
4313          * Clearing compliance test variables to allow capturing
4314          * of values for next automated test request.
4315          */
4316         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4317
4318         /*
4319          * Now read the DPCD to see if it's actually running
4320          * If the current value of sink count doesn't match with
4321          * the value that was stored earlier or dpcd read failed
4322          * we need to do full detection
4323          */
4324         ret = intel_dp_get_dpcd(intel_dp);
4325
4326         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4327                 /* No need to proceed if we are going to do full detect */
4328                 return false;
4329         }
4330
4331         /* Try to read the source of the interrupt */
4332         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4333             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4334             sink_irq_vector != 0) {
4335                 /* Clear interrupt source */
4336                 drm_dp_dpcd_writeb(&intel_dp->aux,
4337                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4338                                    sink_irq_vector);
4339
4340                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4341                         intel_dp_handle_test_request(intel_dp);
4342                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4343                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4344         }
4345
4346         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4347         intel_dp_check_link_status(intel_dp);
4348         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4349         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4350                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4351                 /* Send a Hotplug Uevent to userspace to start modeset */
4352                 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4353         }
4354
4355         return true;
4356 }
4357
4358 /* XXX this is probably wrong for multiple downstream ports */
4359 static enum drm_connector_status
4360 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4361 {
4362         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4363         uint8_t *dpcd = intel_dp->dpcd;
4364         uint8_t type;
4365
4366         if (lspcon->active)
4367                 lspcon_resume(lspcon);
4368
4369         if (!intel_dp_get_dpcd(intel_dp))
4370                 return connector_status_disconnected;
4371
4372         if (is_edp(intel_dp))
4373                 return connector_status_connected;
4374
4375         /* if there's no downstream port, we're done */
4376         if (!drm_dp_is_branch(dpcd))
4377                 return connector_status_connected;
4378
4379         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4380         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4381             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4382
4383                 return intel_dp->sink_count ?
4384                 connector_status_connected : connector_status_disconnected;
4385         }
4386
4387         if (intel_dp_can_mst(intel_dp))
4388                 return connector_status_connected;
4389
4390         /* If no HPD, poke DDC gently */
4391         if (drm_probe_ddc(&intel_dp->aux.ddc))
4392                 return connector_status_connected;
4393
4394         /* Well we tried, say unknown for unreliable port types */
4395         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4396                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4397                 if (type == DP_DS_PORT_TYPE_VGA ||
4398                     type == DP_DS_PORT_TYPE_NON_EDID)
4399                         return connector_status_unknown;
4400         } else {
4401                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4402                         DP_DWN_STRM_PORT_TYPE_MASK;
4403                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4404                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4405                         return connector_status_unknown;
4406         }
4407
4408         /* Anything else is out of spec, warn and ignore */
4409         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4410         return connector_status_disconnected;
4411 }
4412
4413 static enum drm_connector_status
4414 edp_detect(struct intel_dp *intel_dp)
4415 {
4416         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4417         struct drm_i915_private *dev_priv = to_i915(dev);
4418         enum drm_connector_status status;
4419
4420         status = intel_panel_detect(dev_priv);
4421         if (status == connector_status_unknown)
4422                 status = connector_status_connected;
4423
4424         return status;
4425 }
4426
4427 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4428                                        struct intel_digital_port *port)
4429 {
4430         u32 bit;
4431
4432         switch (port->port) {
4433         case PORT_A:
4434                 return true;
4435         case PORT_B:
4436                 bit = SDE_PORTB_HOTPLUG;
4437                 break;
4438         case PORT_C:
4439                 bit = SDE_PORTC_HOTPLUG;
4440                 break;
4441         case PORT_D:
4442                 bit = SDE_PORTD_HOTPLUG;
4443                 break;
4444         default:
4445                 MISSING_CASE(port->port);
4446                 return false;
4447         }
4448
4449         return I915_READ(SDEISR) & bit;
4450 }
4451
4452 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4453                                        struct intel_digital_port *port)
4454 {
4455         u32 bit;
4456
4457         switch (port->port) {
4458         case PORT_A:
4459                 return true;
4460         case PORT_B:
4461                 bit = SDE_PORTB_HOTPLUG_CPT;
4462                 break;
4463         case PORT_C:
4464                 bit = SDE_PORTC_HOTPLUG_CPT;
4465                 break;
4466         case PORT_D:
4467                 bit = SDE_PORTD_HOTPLUG_CPT;
4468                 break;
4469         case PORT_E:
4470                 bit = SDE_PORTE_HOTPLUG_SPT;
4471                 break;
4472         default:
4473                 MISSING_CASE(port->port);
4474                 return false;
4475         }
4476
4477         return I915_READ(SDEISR) & bit;
4478 }
4479
4480 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4481                                        struct intel_digital_port *port)
4482 {
4483         u32 bit;
4484
4485         switch (port->port) {
4486         case PORT_B:
4487                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4488                 break;
4489         case PORT_C:
4490                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4491                 break;
4492         case PORT_D:
4493                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4494                 break;
4495         default:
4496                 MISSING_CASE(port->port);
4497                 return false;
4498         }
4499
4500         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4501 }
4502
4503 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4504                                         struct intel_digital_port *port)
4505 {
4506         u32 bit;
4507
4508         switch (port->port) {
4509         case PORT_B:
4510                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4511                 break;
4512         case PORT_C:
4513                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4514                 break;
4515         case PORT_D:
4516                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4517                 break;
4518         default:
4519                 MISSING_CASE(port->port);
4520                 return false;
4521         }
4522
4523         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4524 }
4525
4526 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4527                                        struct intel_digital_port *intel_dig_port)
4528 {
4529         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4530         enum port port;
4531         u32 bit;
4532
4533         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4534         switch (port) {
4535         case PORT_A:
4536                 bit = BXT_DE_PORT_HP_DDIA;
4537                 break;
4538         case PORT_B:
4539                 bit = BXT_DE_PORT_HP_DDIB;
4540                 break;
4541         case PORT_C:
4542                 bit = BXT_DE_PORT_HP_DDIC;
4543                 break;
4544         default:
4545                 MISSING_CASE(port);
4546                 return false;
4547         }
4548
4549         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4550 }
4551
4552 /*
4553  * intel_digital_port_connected - is the specified port connected?
4554  * @dev_priv: i915 private structure
4555  * @port: the port to test
4556  *
4557  * Return %true if @port is connected, %false otherwise.
4558  */
4559 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4560                                   struct intel_digital_port *port)
4561 {
4562         if (HAS_PCH_IBX(dev_priv))
4563                 return ibx_digital_port_connected(dev_priv, port);
4564         else if (HAS_PCH_SPLIT(dev_priv))
4565                 return cpt_digital_port_connected(dev_priv, port);
4566         else if (IS_GEN9_LP(dev_priv))
4567                 return bxt_digital_port_connected(dev_priv, port);
4568         else if (IS_GM45(dev_priv))
4569                 return gm45_digital_port_connected(dev_priv, port);
4570         else
4571                 return g4x_digital_port_connected(dev_priv, port);
4572 }
4573
4574 static struct edid *
4575 intel_dp_get_edid(struct intel_dp *intel_dp)
4576 {
4577         struct intel_connector *intel_connector = intel_dp->attached_connector;
4578
4579         /* use cached edid if we have one */
4580         if (intel_connector->edid) {
4581                 /* invalid edid */
4582                 if (IS_ERR(intel_connector->edid))
4583                         return NULL;
4584
4585                 return drm_edid_duplicate(intel_connector->edid);
4586         } else
4587                 return drm_get_edid(&intel_connector->base,
4588                                     &intel_dp->aux.ddc);
4589 }
4590
4591 static void
4592 intel_dp_set_edid(struct intel_dp *intel_dp)
4593 {
4594         struct intel_connector *intel_connector = intel_dp->attached_connector;
4595         struct edid *edid;
4596
4597         intel_dp_unset_edid(intel_dp);
4598         edid = intel_dp_get_edid(intel_dp);
4599         intel_connector->detect_edid = edid;
4600
4601         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4602                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4603         else
4604                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4605 }
4606
4607 static void
4608 intel_dp_unset_edid(struct intel_dp *intel_dp)
4609 {
4610         struct intel_connector *intel_connector = intel_dp->attached_connector;
4611
4612         kfree(intel_connector->detect_edid);
4613         intel_connector->detect_edid = NULL;
4614
4615         intel_dp->has_audio = false;
4616 }
4617
4618 static int
4619 intel_dp_long_pulse(struct intel_connector *intel_connector)
4620 {
4621         struct drm_connector *connector = &intel_connector->base;
4622         struct intel_dp *intel_dp = intel_attached_dp(connector);
4623         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4624         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4625         struct drm_device *dev = connector->dev;
4626         enum drm_connector_status status;
4627         u8 sink_irq_vector = 0;
4628
4629         WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex));
4630
4631         intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4632
4633         /* Can't disconnect eDP, but you can close the lid... */
4634         if (is_edp(intel_dp))
4635                 status = edp_detect(intel_dp);
4636         else if (intel_digital_port_connected(to_i915(dev),
4637                                               dp_to_dig_port(intel_dp)))
4638                 status = intel_dp_detect_dpcd(intel_dp);
4639         else
4640                 status = connector_status_disconnected;
4641
4642         if (status == connector_status_disconnected) {
4643                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4644
4645                 if (intel_dp->is_mst) {
4646                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4647                                       intel_dp->is_mst,
4648                                       intel_dp->mst_mgr.mst_state);
4649                         intel_dp->is_mst = false;
4650                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4651                                                         intel_dp->is_mst);
4652                 }
4653
4654                 goto out;
4655         }
4656
4657         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4658                 intel_encoder->type = INTEL_OUTPUT_DP;
4659
4660         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4661                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
4662                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4663
4664         if (intel_dp->reset_link_params) {
4665                 /* Initial max link lane count */
4666                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4667
4668                 /* Initial max link rate */
4669                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4670
4671                 intel_dp->reset_link_params = false;
4672         }
4673
4674         intel_dp_print_rates(intel_dp);
4675
4676         intel_dp_read_desc(intel_dp);
4677
4678         intel_dp_configure_mst(intel_dp);
4679
4680         if (intel_dp->is_mst) {
4681                 /*
4682                  * If we are in MST mode then this connector
4683                  * won't appear connected or have anything
4684                  * with EDID on it
4685                  */
4686                 status = connector_status_disconnected;
4687                 goto out;
4688         } else {
4689                 /*
4690                  * If display is now connected check links status,
4691                  * there has been known issues of link loss triggerring
4692                  * long pulse.
4693                  *
4694                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4695                  * weird HPD ping pong during modesets. So we can apparently
4696                  * end up with HPD going low during a modeset, and then
4697                  * going back up soon after. And once that happens we must
4698                  * retrain the link to get a picture. That's in case no
4699                  * userspace component reacted to intermittent HPD dip.
4700                  */
4701                 intel_dp_check_link_status(intel_dp);
4702         }
4703
4704         /*
4705          * Clearing NACK and defer counts to get their exact values
4706          * while reading EDID which are required by Compliance tests
4707          * 4.2.2.4 and 4.2.2.5
4708          */
4709         intel_dp->aux.i2c_nack_count = 0;
4710         intel_dp->aux.i2c_defer_count = 0;
4711
4712         intel_dp_set_edid(intel_dp);
4713         if (is_edp(intel_dp) || intel_connector->detect_edid)
4714                 status = connector_status_connected;
4715         intel_dp->detect_done = true;
4716
4717         /* Try to read the source of the interrupt */
4718         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4719             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4720             sink_irq_vector != 0) {
4721                 /* Clear interrupt source */
4722                 drm_dp_dpcd_writeb(&intel_dp->aux,
4723                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4724                                    sink_irq_vector);
4725
4726                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4727                         intel_dp_handle_test_request(intel_dp);
4728                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4729                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4730         }
4731
4732 out:
4733         if (status != connector_status_connected && !intel_dp->is_mst)
4734                 intel_dp_unset_edid(intel_dp);
4735
4736         intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4737         return status;
4738 }
4739
4740 static int
4741 intel_dp_detect(struct drm_connector *connector,
4742                 struct drm_modeset_acquire_ctx *ctx,
4743                 bool force)
4744 {
4745         struct intel_dp *intel_dp = intel_attached_dp(connector);
4746         int status = connector->status;
4747
4748         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4749                       connector->base.id, connector->name);
4750
4751         /* If full detect is not performed yet, do a full detect */
4752         if (!intel_dp->detect_done)
4753                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4754
4755         intel_dp->detect_done = false;
4756
4757         return status;
4758 }
4759
4760 static void
4761 intel_dp_force(struct drm_connector *connector)
4762 {
4763         struct intel_dp *intel_dp = intel_attached_dp(connector);
4764         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4765         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4766
4767         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4768                       connector->base.id, connector->name);
4769         intel_dp_unset_edid(intel_dp);
4770
4771         if (connector->status != connector_status_connected)
4772                 return;
4773
4774         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4775
4776         intel_dp_set_edid(intel_dp);
4777
4778         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4779
4780         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4781                 intel_encoder->type = INTEL_OUTPUT_DP;
4782 }
4783
4784 static int intel_dp_get_modes(struct drm_connector *connector)
4785 {
4786         struct intel_connector *intel_connector = to_intel_connector(connector);
4787         struct edid *edid;
4788
4789         edid = intel_connector->detect_edid;
4790         if (edid) {
4791                 int ret = intel_connector_update_modes(connector, edid);
4792                 if (ret)
4793                         return ret;
4794         }
4795
4796         /* if eDP has no EDID, fall back to fixed mode */
4797         if (is_edp(intel_attached_dp(connector)) &&
4798             intel_connector->panel.fixed_mode) {
4799                 struct drm_display_mode *mode;
4800
4801                 mode = drm_mode_duplicate(connector->dev,
4802                                           intel_connector->panel.fixed_mode);
4803                 if (mode) {
4804                         drm_mode_probed_add(connector, mode);
4805                         return 1;
4806                 }
4807         }
4808
4809         return 0;
4810 }
4811
4812 static bool
4813 intel_dp_detect_audio(struct drm_connector *connector)
4814 {
4815         bool has_audio = false;
4816         struct edid *edid;
4817
4818         edid = to_intel_connector(connector)->detect_edid;
4819         if (edid)
4820                 has_audio = drm_detect_monitor_audio(edid);
4821
4822         return has_audio;
4823 }
4824
4825 static int
4826 intel_dp_set_property(struct drm_connector *connector,
4827                       struct drm_property *property,
4828                       uint64_t val)
4829 {
4830         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4831         struct intel_connector *intel_connector = to_intel_connector(connector);
4832         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4833         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4834         int ret;
4835
4836         ret = drm_object_property_set_value(&connector->base, property, val);
4837         if (ret)
4838                 return ret;
4839
4840         if (property == dev_priv->force_audio_property) {
4841                 int i = val;
4842                 bool has_audio;
4843
4844                 if (i == intel_dp->force_audio)
4845                         return 0;
4846
4847                 intel_dp->force_audio = i;
4848
4849                 if (i == HDMI_AUDIO_AUTO)
4850                         has_audio = intel_dp_detect_audio(connector);
4851                 else
4852                         has_audio = (i == HDMI_AUDIO_ON);
4853
4854                 if (has_audio == intel_dp->has_audio)
4855                         return 0;
4856
4857                 intel_dp->has_audio = has_audio;
4858                 goto done;
4859         }
4860
4861         if (property == dev_priv->broadcast_rgb_property) {
4862                 bool old_auto = intel_dp->color_range_auto;
4863                 bool old_range = intel_dp->limited_color_range;
4864
4865                 switch (val) {
4866                 case INTEL_BROADCAST_RGB_AUTO:
4867                         intel_dp->color_range_auto = true;
4868                         break;
4869                 case INTEL_BROADCAST_RGB_FULL:
4870                         intel_dp->color_range_auto = false;
4871                         intel_dp->limited_color_range = false;
4872                         break;
4873                 case INTEL_BROADCAST_RGB_LIMITED:
4874                         intel_dp->color_range_auto = false;
4875                         intel_dp->limited_color_range = true;
4876                         break;
4877                 default:
4878                         return -EINVAL;
4879                 }
4880
4881                 if (old_auto == intel_dp->color_range_auto &&
4882                     old_range == intel_dp->limited_color_range)
4883                         return 0;
4884
4885                 goto done;
4886         }
4887
4888         if (is_edp(intel_dp) &&
4889             property == connector->dev->mode_config.scaling_mode_property) {
4890                 if (val == DRM_MODE_SCALE_NONE) {
4891                         DRM_DEBUG_KMS("no scaling not supported\n");
4892                         return -EINVAL;
4893                 }
4894                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4895                     val == DRM_MODE_SCALE_CENTER) {
4896                         DRM_DEBUG_KMS("centering not supported\n");
4897                         return -EINVAL;
4898                 }
4899
4900                 if (intel_connector->panel.fitting_mode == val) {
4901                         /* the eDP scaling property is not changed */
4902                         return 0;
4903                 }
4904                 intel_connector->panel.fitting_mode = val;
4905
4906                 goto done;
4907         }
4908
4909         return -EINVAL;
4910
4911 done:
4912         if (intel_encoder->base.crtc)
4913                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4914
4915         return 0;
4916 }
4917
4918 static int
4919 intel_dp_connector_register(struct drm_connector *connector)
4920 {
4921         struct intel_dp *intel_dp = intel_attached_dp(connector);
4922         int ret;
4923
4924         ret = intel_connector_register(connector);
4925         if (ret)
4926                 return ret;
4927
4928         i915_debugfs_connector_add(connector);
4929
4930         DRM_DEBUG_KMS("registering %s bus for %s\n",
4931                       intel_dp->aux.name, connector->kdev->kobj.name);
4932
4933         intel_dp->aux.dev = connector->kdev;
4934         return drm_dp_aux_register(&intel_dp->aux);
4935 }
4936
4937 static void
4938 intel_dp_connector_unregister(struct drm_connector *connector)
4939 {
4940         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4941         intel_connector_unregister(connector);
4942 }
4943
4944 static void
4945 intel_dp_connector_destroy(struct drm_connector *connector)
4946 {
4947         struct intel_connector *intel_connector = to_intel_connector(connector);
4948
4949         kfree(intel_connector->detect_edid);
4950
4951         if (!IS_ERR_OR_NULL(intel_connector->edid))
4952                 kfree(intel_connector->edid);
4953
4954         /* Can't call is_edp() since the encoder may have been destroyed
4955          * already. */
4956         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4957                 intel_panel_fini(&intel_connector->panel);
4958
4959         drm_connector_cleanup(connector);
4960         kfree(connector);
4961 }
4962
4963 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4964 {
4965         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4966         struct intel_dp *intel_dp = &intel_dig_port->dp;
4967
4968         intel_dp_mst_encoder_cleanup(intel_dig_port);
4969         if (is_edp(intel_dp)) {
4970                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4971                 /*
4972                  * vdd might still be enabled do to the delayed vdd off.
4973                  * Make sure vdd is actually turned off here.
4974                  */
4975                 pps_lock(intel_dp);
4976                 edp_panel_vdd_off_sync(intel_dp);
4977                 pps_unlock(intel_dp);
4978
4979                 if (intel_dp->edp_notifier.notifier_call) {
4980                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4981                         intel_dp->edp_notifier.notifier_call = NULL;
4982                 }
4983         }
4984
4985         intel_dp_aux_fini(intel_dp);
4986
4987         drm_encoder_cleanup(encoder);
4988         kfree(intel_dig_port);
4989 }
4990
4991 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4992 {
4993         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4994
4995         if (!is_edp(intel_dp))
4996                 return;
4997
4998         /*
4999          * vdd might still be enabled do to the delayed vdd off.
5000          * Make sure vdd is actually turned off here.
5001          */
5002         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5003         pps_lock(intel_dp);
5004         edp_panel_vdd_off_sync(intel_dp);
5005         pps_unlock(intel_dp);
5006 }
5007
5008 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5009 {
5010         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5011         struct drm_device *dev = intel_dig_port->base.base.dev;
5012         struct drm_i915_private *dev_priv = to_i915(dev);
5013
5014         lockdep_assert_held(&dev_priv->pps_mutex);
5015
5016         if (!edp_have_panel_vdd(intel_dp))
5017                 return;
5018
5019         /*
5020          * The VDD bit needs a power domain reference, so if the bit is
5021          * already enabled when we boot or resume, grab this reference and
5022          * schedule a vdd off, so we don't hold on to the reference
5023          * indefinitely.
5024          */
5025         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5026         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5027
5028         edp_panel_vdd_schedule_off(intel_dp);
5029 }
5030
5031 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5032 {
5033         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5034
5035         if ((intel_dp->DP & DP_PORT_EN) == 0)
5036                 return INVALID_PIPE;
5037
5038         if (IS_CHERRYVIEW(dev_priv))
5039                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5040         else
5041                 return PORT_TO_PIPE(intel_dp->DP);
5042 }
5043
5044 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5045 {
5046         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5047         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5048         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5049
5050         if (!HAS_DDI(dev_priv))
5051                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5052
5053         if (lspcon->active)
5054                 lspcon_resume(lspcon);
5055
5056         intel_dp->reset_link_params = true;
5057
5058         pps_lock(intel_dp);
5059
5060         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5061                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5062
5063         if (is_edp(intel_dp)) {
5064                 /* Reinit the power sequencer, in case BIOS did something with it. */
5065                 intel_dp_pps_init(encoder->dev, intel_dp);
5066                 intel_edp_panel_vdd_sanitize(intel_dp);
5067         }
5068
5069         pps_unlock(intel_dp);
5070 }
5071
5072 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5073         .dpms = drm_atomic_helper_connector_dpms,
5074         .force = intel_dp_force,
5075         .fill_modes = drm_helper_probe_single_connector_modes,
5076         .set_property = intel_dp_set_property,
5077         .atomic_get_property = intel_connector_atomic_get_property,
5078         .late_register = intel_dp_connector_register,
5079         .early_unregister = intel_dp_connector_unregister,
5080         .destroy = intel_dp_connector_destroy,
5081         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5082         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
5083 };
5084
5085 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5086         .detect_ctx = intel_dp_detect,
5087         .get_modes = intel_dp_get_modes,
5088         .mode_valid = intel_dp_mode_valid,
5089 };
5090
5091 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5092         .reset = intel_dp_encoder_reset,
5093         .destroy = intel_dp_encoder_destroy,
5094 };
5095
5096 enum irqreturn
5097 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5098 {
5099         struct intel_dp *intel_dp = &intel_dig_port->dp;
5100         struct drm_device *dev = intel_dig_port->base.base.dev;
5101         struct drm_i915_private *dev_priv = to_i915(dev);
5102         enum irqreturn ret = IRQ_NONE;
5103
5104         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5105             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5106                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5107
5108         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5109                 /*
5110                  * vdd off can generate a long pulse on eDP which
5111                  * would require vdd on to handle it, and thus we
5112                  * would end up in an endless cycle of
5113                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5114                  */
5115                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5116                               port_name(intel_dig_port->port));
5117                 return IRQ_HANDLED;
5118         }
5119
5120         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5121                       port_name(intel_dig_port->port),
5122                       long_hpd ? "long" : "short");
5123
5124         if (long_hpd) {
5125                 intel_dp->reset_link_params = true;
5126                 intel_dp->detect_done = false;
5127                 return IRQ_NONE;
5128         }
5129
5130         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5131
5132         if (intel_dp->is_mst) {
5133                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5134                         /*
5135                          * If we were in MST mode, and device is not
5136                          * there, get out of MST mode
5137                          */
5138                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5139                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5140                         intel_dp->is_mst = false;
5141                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5142                                                         intel_dp->is_mst);
5143                         intel_dp->detect_done = false;
5144                         goto put_power;
5145                 }
5146         }
5147
5148         if (!intel_dp->is_mst) {
5149                 if (!intel_dp_short_pulse(intel_dp)) {
5150                         intel_dp->detect_done = false;
5151                         goto put_power;
5152                 }
5153         }
5154
5155         ret = IRQ_HANDLED;
5156
5157 put_power:
5158         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5159
5160         return ret;
5161 }
5162
5163 /* check the VBT to see whether the eDP is on another port */
5164 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5165 {
5166         /*
5167          * eDP not supported on g4x. so bail out early just
5168          * for a bit extra safety in case the VBT is bonkers.
5169          */
5170         if (INTEL_GEN(dev_priv) < 5)
5171                 return false;
5172
5173         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5174                 return true;
5175
5176         return intel_bios_is_port_edp(dev_priv, port);
5177 }
5178
5179 static void
5180 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5181 {
5182         struct intel_connector *intel_connector = to_intel_connector(connector);
5183
5184         intel_attach_force_audio_property(connector);
5185         intel_attach_broadcast_rgb_property(connector);
5186         intel_dp->color_range_auto = true;
5187
5188         if (is_edp(intel_dp)) {
5189                 drm_mode_create_scaling_mode_property(connector->dev);
5190                 drm_object_attach_property(
5191                         &connector->base,
5192                         connector->dev->mode_config.scaling_mode_property,
5193                         DRM_MODE_SCALE_ASPECT);
5194                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5195         }
5196 }
5197
5198 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5199 {
5200         intel_dp->panel_power_off_time = ktime_get_boottime();
5201         intel_dp->last_power_on = jiffies;
5202         intel_dp->last_backlight_off = jiffies;
5203 }
5204
5205 static void
5206 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5207                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
5208 {
5209         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5210         struct pps_registers regs;
5211
5212         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5213
5214         /* Workaround: Need to write PP_CONTROL with the unlock key as
5215          * the very first thing. */
5216         pp_ctl = ironlake_get_pp_control(intel_dp);
5217
5218         pp_on = I915_READ(regs.pp_on);
5219         pp_off = I915_READ(regs.pp_off);
5220         if (!IS_GEN9_LP(dev_priv)) {
5221                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5222                 pp_div = I915_READ(regs.pp_div);
5223         }
5224
5225         /* Pull timing values out of registers */
5226         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5227                      PANEL_POWER_UP_DELAY_SHIFT;
5228
5229         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5230                   PANEL_LIGHT_ON_DELAY_SHIFT;
5231
5232         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5233                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5234
5235         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5236                    PANEL_POWER_DOWN_DELAY_SHIFT;
5237
5238         if (IS_GEN9_LP(dev_priv)) {
5239                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5240                         BXT_POWER_CYCLE_DELAY_SHIFT;
5241                 if (tmp > 0)
5242                         seq->t11_t12 = (tmp - 1) * 1000;
5243                 else
5244                         seq->t11_t12 = 0;
5245         } else {
5246                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5247                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5248         }
5249 }
5250
5251 static void
5252 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5253 {
5254         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5255                       state_name,
5256                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5257 }
5258
5259 static void
5260 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5261                        struct intel_dp *intel_dp)
5262 {
5263         struct edp_power_seq hw;
5264         struct edp_power_seq *sw = &intel_dp->pps_delays;
5265
5266         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5267
5268         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5269             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5270                 DRM_ERROR("PPS state mismatch\n");
5271                 intel_pps_dump_state("sw", sw);
5272                 intel_pps_dump_state("hw", &hw);
5273         }
5274 }
5275
5276 static void
5277 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5278                                     struct intel_dp *intel_dp)
5279 {
5280         struct drm_i915_private *dev_priv = to_i915(dev);
5281         struct edp_power_seq cur, vbt, spec,
5282                 *final = &intel_dp->pps_delays;
5283
5284         lockdep_assert_held(&dev_priv->pps_mutex);
5285
5286         /* already initialized? */
5287         if (final->t11_t12 != 0)
5288                 return;
5289
5290         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5291
5292         intel_pps_dump_state("cur", &cur);
5293
5294         vbt = dev_priv->vbt.edp.pps;
5295
5296         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5297          * our hw here, which are all in 100usec. */
5298         spec.t1_t3 = 210 * 10;
5299         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5300         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5301         spec.t10 = 500 * 10;
5302         /* This one is special and actually in units of 100ms, but zero
5303          * based in the hw (so we need to add 100 ms). But the sw vbt
5304          * table multiplies it with 1000 to make it in units of 100usec,
5305          * too. */
5306         spec.t11_t12 = (510 + 100) * 10;
5307
5308         intel_pps_dump_state("vbt", &vbt);
5309
5310         /* Use the max of the register settings and vbt. If both are
5311          * unset, fall back to the spec limits. */
5312 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5313                                        spec.field : \
5314                                        max(cur.field, vbt.field))
5315         assign_final(t1_t3);
5316         assign_final(t8);
5317         assign_final(t9);
5318         assign_final(t10);
5319         assign_final(t11_t12);
5320 #undef assign_final
5321
5322 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5323         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5324         intel_dp->backlight_on_delay = get_delay(t8);
5325         intel_dp->backlight_off_delay = get_delay(t9);
5326         intel_dp->panel_power_down_delay = get_delay(t10);
5327         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5328 #undef get_delay
5329
5330         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5331                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5332                       intel_dp->panel_power_cycle_delay);
5333
5334         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5335                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5336
5337         /*
5338          * We override the HW backlight delays to 1 because we do manual waits
5339          * on them. For T8, even BSpec recommends doing it. For T9, if we
5340          * don't do this, we'll end up waiting for the backlight off delay
5341          * twice: once when we do the manual sleep, and once when we disable
5342          * the panel and wait for the PP_STATUS bit to become zero.
5343          */
5344         final->t8 = 1;
5345         final->t9 = 1;
5346 }
5347
5348 static void
5349 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5350                                               struct intel_dp *intel_dp,
5351                                               bool force_disable_vdd)
5352 {
5353         struct drm_i915_private *dev_priv = to_i915(dev);
5354         u32 pp_on, pp_off, pp_div, port_sel = 0;
5355         int div = dev_priv->rawclk_freq / 1000;
5356         struct pps_registers regs;
5357         enum port port = dp_to_dig_port(intel_dp)->port;
5358         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5359
5360         lockdep_assert_held(&dev_priv->pps_mutex);
5361
5362         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5363
5364         /*
5365          * On some VLV machines the BIOS can leave the VDD
5366          * enabled even on power seqeuencers which aren't
5367          * hooked up to any port. This would mess up the
5368          * power domain tracking the first time we pick
5369          * one of these power sequencers for use since
5370          * edp_panel_vdd_on() would notice that the VDD was
5371          * already on and therefore wouldn't grab the power
5372          * domain reference. Disable VDD first to avoid this.
5373          * This also avoids spuriously turning the VDD on as
5374          * soon as the new power seqeuencer gets initialized.
5375          */
5376         if (force_disable_vdd) {
5377                 u32 pp = ironlake_get_pp_control(intel_dp);
5378
5379                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5380
5381                 if (pp & EDP_FORCE_VDD)
5382                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5383
5384                 pp &= ~EDP_FORCE_VDD;
5385
5386                 I915_WRITE(regs.pp_ctrl, pp);
5387         }
5388
5389         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5390                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5391         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5392                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5393         /* Compute the divisor for the pp clock, simply match the Bspec
5394          * formula. */
5395         if (IS_GEN9_LP(dev_priv)) {
5396                 pp_div = I915_READ(regs.pp_ctrl);
5397                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5398                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5399                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5400         } else {
5401                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5402                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5403                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5404         }
5405
5406         /* Haswell doesn't have any port selection bits for the panel
5407          * power sequencer any more. */
5408         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5409                 port_sel = PANEL_PORT_SELECT_VLV(port);
5410         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5411                 if (port == PORT_A)
5412                         port_sel = PANEL_PORT_SELECT_DPA;
5413                 else
5414                         port_sel = PANEL_PORT_SELECT_DPD;
5415         }
5416
5417         pp_on |= port_sel;
5418
5419         I915_WRITE(regs.pp_on, pp_on);
5420         I915_WRITE(regs.pp_off, pp_off);
5421         if (IS_GEN9_LP(dev_priv))
5422                 I915_WRITE(regs.pp_ctrl, pp_div);
5423         else
5424                 I915_WRITE(regs.pp_div, pp_div);
5425
5426         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5427                       I915_READ(regs.pp_on),
5428                       I915_READ(regs.pp_off),
5429                       IS_GEN9_LP(dev_priv) ?
5430                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5431                       I915_READ(regs.pp_div));
5432 }
5433
5434 static void intel_dp_pps_init(struct drm_device *dev,
5435                               struct intel_dp *intel_dp)
5436 {
5437         struct drm_i915_private *dev_priv = to_i915(dev);
5438
5439         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5440                 vlv_initial_power_sequencer_setup(intel_dp);
5441         } else {
5442                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5443                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5444         }
5445 }
5446
5447 /**
5448  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5449  * @dev_priv: i915 device
5450  * @crtc_state: a pointer to the active intel_crtc_state
5451  * @refresh_rate: RR to be programmed
5452  *
5453  * This function gets called when refresh rate (RR) has to be changed from
5454  * one frequency to another. Switches can be between high and low RR
5455  * supported by the panel or to any other RR based on media playback (in
5456  * this case, RR value needs to be passed from user space).
5457  *
5458  * The caller of this function needs to take a lock on dev_priv->drrs.
5459  */
5460 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5461                                     struct intel_crtc_state *crtc_state,
5462                                     int refresh_rate)
5463 {
5464         struct intel_encoder *encoder;
5465         struct intel_digital_port *dig_port = NULL;
5466         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5468         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5469
5470         if (refresh_rate <= 0) {
5471                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5472                 return;
5473         }
5474
5475         if (intel_dp == NULL) {
5476                 DRM_DEBUG_KMS("DRRS not supported.\n");
5477                 return;
5478         }
5479
5480         /*
5481          * FIXME: This needs proper synchronization with psr state for some
5482          * platforms that cannot have PSR and DRRS enabled at the same time.
5483          */
5484
5485         dig_port = dp_to_dig_port(intel_dp);
5486         encoder = &dig_port->base;
5487         intel_crtc = to_intel_crtc(encoder->base.crtc);
5488
5489         if (!intel_crtc) {
5490                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5491                 return;
5492         }
5493
5494         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5495                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5496                 return;
5497         }
5498
5499         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5500                         refresh_rate)
5501                 index = DRRS_LOW_RR;
5502
5503         if (index == dev_priv->drrs.refresh_rate_type) {
5504                 DRM_DEBUG_KMS(
5505                         "DRRS requested for previously set RR...ignoring\n");
5506                 return;
5507         }
5508
5509         if (!crtc_state->base.active) {
5510                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5511                 return;
5512         }
5513
5514         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5515                 switch (index) {
5516                 case DRRS_HIGH_RR:
5517                         intel_dp_set_m_n(intel_crtc, M1_N1);
5518                         break;
5519                 case DRRS_LOW_RR:
5520                         intel_dp_set_m_n(intel_crtc, M2_N2);
5521                         break;
5522                 case DRRS_MAX_RR:
5523                 default:
5524                         DRM_ERROR("Unsupported refreshrate type\n");
5525                 }
5526         } else if (INTEL_GEN(dev_priv) > 6) {
5527                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5528                 u32 val;
5529
5530                 val = I915_READ(reg);
5531                 if (index > DRRS_HIGH_RR) {
5532                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5533                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5534                         else
5535                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5536                 } else {
5537                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5538                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5539                         else
5540                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5541                 }
5542                 I915_WRITE(reg, val);
5543         }
5544
5545         dev_priv->drrs.refresh_rate_type = index;
5546
5547         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5548 }
5549
5550 /**
5551  * intel_edp_drrs_enable - init drrs struct if supported
5552  * @intel_dp: DP struct
5553  * @crtc_state: A pointer to the active crtc state.
5554  *
5555  * Initializes frontbuffer_bits and drrs.dp
5556  */
5557 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5558                            struct intel_crtc_state *crtc_state)
5559 {
5560         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5561         struct drm_i915_private *dev_priv = to_i915(dev);
5562
5563         if (!crtc_state->has_drrs) {
5564                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5565                 return;
5566         }
5567
5568         mutex_lock(&dev_priv->drrs.mutex);
5569         if (WARN_ON(dev_priv->drrs.dp)) {
5570                 DRM_ERROR("DRRS already enabled\n");
5571                 goto unlock;
5572         }
5573
5574         dev_priv->drrs.busy_frontbuffer_bits = 0;
5575
5576         dev_priv->drrs.dp = intel_dp;
5577
5578 unlock:
5579         mutex_unlock(&dev_priv->drrs.mutex);
5580 }
5581
5582 /**
5583  * intel_edp_drrs_disable - Disable DRRS
5584  * @intel_dp: DP struct
5585  * @old_crtc_state: Pointer to old crtc_state.
5586  *
5587  */
5588 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5589                             struct intel_crtc_state *old_crtc_state)
5590 {
5591         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5592         struct drm_i915_private *dev_priv = to_i915(dev);
5593
5594         if (!old_crtc_state->has_drrs)
5595                 return;
5596
5597         mutex_lock(&dev_priv->drrs.mutex);
5598         if (!dev_priv->drrs.dp) {
5599                 mutex_unlock(&dev_priv->drrs.mutex);
5600                 return;
5601         }
5602
5603         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5604                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5605                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5606
5607         dev_priv->drrs.dp = NULL;
5608         mutex_unlock(&dev_priv->drrs.mutex);
5609
5610         cancel_delayed_work_sync(&dev_priv->drrs.work);
5611 }
5612
5613 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5614 {
5615         struct drm_i915_private *dev_priv =
5616                 container_of(work, typeof(*dev_priv), drrs.work.work);
5617         struct intel_dp *intel_dp;
5618
5619         mutex_lock(&dev_priv->drrs.mutex);
5620
5621         intel_dp = dev_priv->drrs.dp;
5622
5623         if (!intel_dp)
5624                 goto unlock;
5625
5626         /*
5627          * The delayed work can race with an invalidate hence we need to
5628          * recheck.
5629          */
5630
5631         if (dev_priv->drrs.busy_frontbuffer_bits)
5632                 goto unlock;
5633
5634         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5635                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5636
5637                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5638                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5639         }
5640
5641 unlock:
5642         mutex_unlock(&dev_priv->drrs.mutex);
5643 }
5644
5645 /**
5646  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5647  * @dev_priv: i915 device
5648  * @frontbuffer_bits: frontbuffer plane tracking bits
5649  *
5650  * This function gets called everytime rendering on the given planes start.
5651  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5652  *
5653  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5654  */
5655 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5656                                unsigned int frontbuffer_bits)
5657 {
5658         struct drm_crtc *crtc;
5659         enum pipe pipe;
5660
5661         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5662                 return;
5663
5664         cancel_delayed_work(&dev_priv->drrs.work);
5665
5666         mutex_lock(&dev_priv->drrs.mutex);
5667         if (!dev_priv->drrs.dp) {
5668                 mutex_unlock(&dev_priv->drrs.mutex);
5669                 return;
5670         }
5671
5672         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5673         pipe = to_intel_crtc(crtc)->pipe;
5674
5675         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5676         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5677
5678         /* invalidate means busy screen hence upclock */
5679         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5680                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5681                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5682
5683         mutex_unlock(&dev_priv->drrs.mutex);
5684 }
5685
5686 /**
5687  * intel_edp_drrs_flush - Restart Idleness DRRS
5688  * @dev_priv: i915 device
5689  * @frontbuffer_bits: frontbuffer plane tracking bits
5690  *
5691  * This function gets called every time rendering on the given planes has
5692  * completed or flip on a crtc is completed. So DRRS should be upclocked
5693  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5694  * if no other planes are dirty.
5695  *
5696  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5697  */
5698 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5699                           unsigned int frontbuffer_bits)
5700 {
5701         struct drm_crtc *crtc;
5702         enum pipe pipe;
5703
5704         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5705                 return;
5706
5707         cancel_delayed_work(&dev_priv->drrs.work);
5708
5709         mutex_lock(&dev_priv->drrs.mutex);
5710         if (!dev_priv->drrs.dp) {
5711                 mutex_unlock(&dev_priv->drrs.mutex);
5712                 return;
5713         }
5714
5715         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5716         pipe = to_intel_crtc(crtc)->pipe;
5717
5718         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5719         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5720
5721         /* flush means busy screen hence upclock */
5722         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5723                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5724                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5725
5726         /*
5727          * flush also means no more activity hence schedule downclock, if all
5728          * other fbs are quiescent too
5729          */
5730         if (!dev_priv->drrs.busy_frontbuffer_bits)
5731                 schedule_delayed_work(&dev_priv->drrs.work,
5732                                 msecs_to_jiffies(1000));
5733         mutex_unlock(&dev_priv->drrs.mutex);
5734 }
5735
5736 /**
5737  * DOC: Display Refresh Rate Switching (DRRS)
5738  *
5739  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5740  * which enables swtching between low and high refresh rates,
5741  * dynamically, based on the usage scenario. This feature is applicable
5742  * for internal panels.
5743  *
5744  * Indication that the panel supports DRRS is given by the panel EDID, which
5745  * would list multiple refresh rates for one resolution.
5746  *
5747  * DRRS is of 2 types - static and seamless.
5748  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5749  * (may appear as a blink on screen) and is used in dock-undock scenario.
5750  * Seamless DRRS involves changing RR without any visual effect to the user
5751  * and can be used during normal system usage. This is done by programming
5752  * certain registers.
5753  *
5754  * Support for static/seamless DRRS may be indicated in the VBT based on
5755  * inputs from the panel spec.
5756  *
5757  * DRRS saves power by switching to low RR based on usage scenarios.
5758  *
5759  * The implementation is based on frontbuffer tracking implementation.  When
5760  * there is a disturbance on the screen triggered by user activity or a periodic
5761  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5762  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5763  * made.
5764  *
5765  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5766  * and intel_edp_drrs_flush() are called.
5767  *
5768  * DRRS can be further extended to support other internal panels and also
5769  * the scenario of video playback wherein RR is set based on the rate
5770  * requested by userspace.
5771  */
5772
5773 /**
5774  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5775  * @intel_connector: eDP connector
5776  * @fixed_mode: preferred mode of panel
5777  *
5778  * This function is  called only once at driver load to initialize basic
5779  * DRRS stuff.
5780  *
5781  * Returns:
5782  * Downclock mode if panel supports it, else return NULL.
5783  * DRRS support is determined by the presence of downclock mode (apart
5784  * from VBT setting).
5785  */
5786 static struct drm_display_mode *
5787 intel_dp_drrs_init(struct intel_connector *intel_connector,
5788                 struct drm_display_mode *fixed_mode)
5789 {
5790         struct drm_connector *connector = &intel_connector->base;
5791         struct drm_device *dev = connector->dev;
5792         struct drm_i915_private *dev_priv = to_i915(dev);
5793         struct drm_display_mode *downclock_mode = NULL;
5794
5795         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5796         mutex_init(&dev_priv->drrs.mutex);
5797
5798         if (INTEL_GEN(dev_priv) <= 6) {
5799                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5800                 return NULL;
5801         }
5802
5803         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5804                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5805                 return NULL;
5806         }
5807
5808         downclock_mode = intel_find_panel_downclock
5809                                         (dev_priv, fixed_mode, connector);
5810
5811         if (!downclock_mode) {
5812                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5813                 return NULL;
5814         }
5815
5816         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5817
5818         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5819         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5820         return downclock_mode;
5821 }
5822
5823 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5824                                      struct intel_connector *intel_connector)
5825 {
5826         struct drm_connector *connector = &intel_connector->base;
5827         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5828         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5829         struct drm_device *dev = intel_encoder->base.dev;
5830         struct drm_i915_private *dev_priv = to_i915(dev);
5831         struct drm_display_mode *fixed_mode = NULL;
5832         struct drm_display_mode *downclock_mode = NULL;
5833         bool has_dpcd;
5834         struct drm_display_mode *scan;
5835         struct edid *edid;
5836         enum pipe pipe = INVALID_PIPE;
5837
5838         if (!is_edp(intel_dp))
5839                 return true;
5840
5841         /*
5842          * On IBX/CPT we may get here with LVDS already registered. Since the
5843          * driver uses the only internal power sequencer available for both
5844          * eDP and LVDS bail out early in this case to prevent interfering
5845          * with an already powered-on LVDS power sequencer.
5846          */
5847         if (intel_get_lvds_encoder(dev)) {
5848                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5849                 DRM_INFO("LVDS was detected, not registering eDP\n");
5850
5851                 return false;
5852         }
5853
5854         pps_lock(intel_dp);
5855
5856         intel_dp_init_panel_power_timestamps(intel_dp);
5857         intel_dp_pps_init(dev, intel_dp);
5858         intel_edp_panel_vdd_sanitize(intel_dp);
5859
5860         pps_unlock(intel_dp);
5861
5862         /* Cache DPCD and EDID for edp. */
5863         has_dpcd = intel_edp_init_dpcd(intel_dp);
5864
5865         if (!has_dpcd) {
5866                 /* if this fails, presume the device is a ghost */
5867                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5868                 goto out_vdd_off;
5869         }
5870
5871         mutex_lock(&dev->mode_config.mutex);
5872         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5873         if (edid) {
5874                 if (drm_add_edid_modes(connector, edid)) {
5875                         drm_mode_connector_update_edid_property(connector,
5876                                                                 edid);
5877                         drm_edid_to_eld(connector, edid);
5878                 } else {
5879                         kfree(edid);
5880                         edid = ERR_PTR(-EINVAL);
5881                 }
5882         } else {
5883                 edid = ERR_PTR(-ENOENT);
5884         }
5885         intel_connector->edid = edid;
5886
5887         /* prefer fixed mode from EDID if available */
5888         list_for_each_entry(scan, &connector->probed_modes, head) {
5889                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5890                         fixed_mode = drm_mode_duplicate(dev, scan);
5891                         downclock_mode = intel_dp_drrs_init(
5892                                                 intel_connector, fixed_mode);
5893                         break;
5894                 }
5895         }
5896
5897         /* fallback to VBT if available for eDP */
5898         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5899                 fixed_mode = drm_mode_duplicate(dev,
5900                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5901                 if (fixed_mode) {
5902                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5903                         connector->display_info.width_mm = fixed_mode->width_mm;
5904                         connector->display_info.height_mm = fixed_mode->height_mm;
5905                 }
5906         }
5907         mutex_unlock(&dev->mode_config.mutex);
5908
5909         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5910                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5911                 register_reboot_notifier(&intel_dp->edp_notifier);
5912
5913                 /*
5914                  * Figure out the current pipe for the initial backlight setup.
5915                  * If the current pipe isn't valid, try the PPS pipe, and if that
5916                  * fails just assume pipe A.
5917                  */
5918                 pipe = vlv_active_pipe(intel_dp);
5919
5920                 if (pipe != PIPE_A && pipe != PIPE_B)
5921                         pipe = intel_dp->pps_pipe;
5922
5923                 if (pipe != PIPE_A && pipe != PIPE_B)
5924                         pipe = PIPE_A;
5925
5926                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5927                               pipe_name(pipe));
5928         }
5929
5930         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5931         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5932         intel_panel_setup_backlight(connector, pipe);
5933
5934         return true;
5935
5936 out_vdd_off:
5937         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5938         /*
5939          * vdd might still be enabled do to the delayed vdd off.
5940          * Make sure vdd is actually turned off here.
5941          */
5942         pps_lock(intel_dp);
5943         edp_panel_vdd_off_sync(intel_dp);
5944         pps_unlock(intel_dp);
5945
5946         return false;
5947 }
5948
5949 /* Set up the hotplug pin and aux power domain. */
5950 static void
5951 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5952 {
5953         struct intel_encoder *encoder = &intel_dig_port->base;
5954         struct intel_dp *intel_dp = &intel_dig_port->dp;
5955
5956         switch (intel_dig_port->port) {
5957         case PORT_A:
5958                 encoder->hpd_pin = HPD_PORT_A;
5959                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5960                 break;
5961         case PORT_B:
5962                 encoder->hpd_pin = HPD_PORT_B;
5963                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5964                 break;
5965         case PORT_C:
5966                 encoder->hpd_pin = HPD_PORT_C;
5967                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5968                 break;
5969         case PORT_D:
5970                 encoder->hpd_pin = HPD_PORT_D;
5971                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5972                 break;
5973         case PORT_E:
5974                 encoder->hpd_pin = HPD_PORT_E;
5975
5976                 /* FIXME: Check VBT for actual wiring of PORT E */
5977                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5978                 break;
5979         default:
5980                 MISSING_CASE(intel_dig_port->port);
5981         }
5982 }
5983
5984 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5985 {
5986         struct intel_connector *intel_connector;
5987         struct drm_connector *connector;
5988
5989         intel_connector = container_of(work, typeof(*intel_connector),
5990                                        modeset_retry_work);
5991         connector = &intel_connector->base;
5992         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5993                       connector->name);
5994
5995         /* Grab the locks before changing connector property*/
5996         mutex_lock(&connector->dev->mode_config.mutex);
5997         /* Set connector link status to BAD and send a Uevent to notify
5998          * userspace to do a modeset.
5999          */
6000         drm_mode_connector_set_link_status_property(connector,
6001                                                     DRM_MODE_LINK_STATUS_BAD);
6002         mutex_unlock(&connector->dev->mode_config.mutex);
6003         /* Send Hotplug uevent so userspace can reprobe */
6004         drm_kms_helper_hotplug_event(connector->dev);
6005 }
6006
6007 bool
6008 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6009                         struct intel_connector *intel_connector)
6010 {
6011         struct drm_connector *connector = &intel_connector->base;
6012         struct intel_dp *intel_dp = &intel_dig_port->dp;
6013         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6014         struct drm_device *dev = intel_encoder->base.dev;
6015         struct drm_i915_private *dev_priv = to_i915(dev);
6016         enum port port = intel_dig_port->port;
6017         int type;
6018
6019         /* Initialize the work for modeset in case of link train failure */
6020         INIT_WORK(&intel_connector->modeset_retry_work,
6021                   intel_dp_modeset_retry_work_fn);
6022
6023         if (WARN(intel_dig_port->max_lanes < 1,
6024                  "Not enough lanes (%d) for DP on port %c\n",
6025                  intel_dig_port->max_lanes, port_name(port)))
6026                 return false;
6027
6028         intel_dp_set_source_rates(intel_dp);
6029
6030         intel_dp->reset_link_params = true;
6031         intel_dp->pps_pipe = INVALID_PIPE;
6032         intel_dp->active_pipe = INVALID_PIPE;
6033
6034         /* intel_dp vfuncs */
6035         if (INTEL_GEN(dev_priv) >= 9)
6036                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6037         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6038                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6039         else if (HAS_PCH_SPLIT(dev_priv))
6040                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6041         else
6042                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6043
6044         if (INTEL_GEN(dev_priv) >= 9)
6045                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6046         else
6047                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6048
6049         if (HAS_DDI(dev_priv))
6050                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6051
6052         /* Preserve the current hw state. */
6053         intel_dp->DP = I915_READ(intel_dp->output_reg);
6054         intel_dp->attached_connector = intel_connector;
6055
6056         if (intel_dp_is_edp(dev_priv, port))
6057                 type = DRM_MODE_CONNECTOR_eDP;
6058         else
6059                 type = DRM_MODE_CONNECTOR_DisplayPort;
6060
6061         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6062                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6063
6064         /*
6065          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6066          * for DP the encoder type can be set by the caller to
6067          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6068          */
6069         if (type == DRM_MODE_CONNECTOR_eDP)
6070                 intel_encoder->type = INTEL_OUTPUT_EDP;
6071
6072         /* eDP only on port B and/or C on vlv/chv */
6073         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6074                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
6075                 return false;
6076
6077         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6078                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6079                         port_name(port));
6080
6081         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6082         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6083
6084         connector->interlace_allowed = true;
6085         connector->doublescan_allowed = 0;
6086
6087         intel_dp_init_connector_port_info(intel_dig_port);
6088
6089         intel_dp_aux_init(intel_dp);
6090
6091         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6092                           edp_panel_vdd_work);
6093
6094         intel_connector_attach_encoder(intel_connector, intel_encoder);
6095
6096         if (HAS_DDI(dev_priv))
6097                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6098         else
6099                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6100
6101         /* init MST on ports that can support it */
6102         if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
6103             (port == PORT_B || port == PORT_C || port == PORT_D))
6104                 intel_dp_mst_encoder_init(intel_dig_port,
6105                                           intel_connector->base.base.id);
6106
6107         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6108                 intel_dp_aux_fini(intel_dp);
6109                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6110                 goto fail;
6111         }
6112
6113         intel_dp_add_properties(intel_dp, connector);
6114
6115         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6116          * 0xd.  Failure to do so will result in spurious interrupts being
6117          * generated on the port when a cable is not attached.
6118          */
6119         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6120                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6121                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6122         }
6123
6124         return true;
6125
6126 fail:
6127         drm_connector_cleanup(connector);
6128
6129         return false;
6130 }
6131
6132 bool intel_dp_init(struct drm_i915_private *dev_priv,
6133                    i915_reg_t output_reg,
6134                    enum port port)
6135 {
6136         struct intel_digital_port *intel_dig_port;
6137         struct intel_encoder *intel_encoder;
6138         struct drm_encoder *encoder;
6139         struct intel_connector *intel_connector;
6140
6141         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6142         if (!intel_dig_port)
6143                 return false;
6144
6145         intel_connector = intel_connector_alloc();
6146         if (!intel_connector)
6147                 goto err_connector_alloc;
6148
6149         intel_encoder = &intel_dig_port->base;
6150         encoder = &intel_encoder->base;
6151
6152         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6153                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6154                              "DP %c", port_name(port)))
6155                 goto err_encoder_init;
6156
6157         intel_encoder->compute_config = intel_dp_compute_config;
6158         intel_encoder->disable = intel_disable_dp;
6159         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6160         intel_encoder->get_config = intel_dp_get_config;
6161         intel_encoder->suspend = intel_dp_encoder_suspend;
6162         if (IS_CHERRYVIEW(dev_priv)) {
6163                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6164                 intel_encoder->pre_enable = chv_pre_enable_dp;
6165                 intel_encoder->enable = vlv_enable_dp;
6166                 intel_encoder->post_disable = chv_post_disable_dp;
6167                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6168         } else if (IS_VALLEYVIEW(dev_priv)) {
6169                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6170                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6171                 intel_encoder->enable = vlv_enable_dp;
6172                 intel_encoder->post_disable = vlv_post_disable_dp;
6173         } else {
6174                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6175                 intel_encoder->enable = g4x_enable_dp;
6176                 if (INTEL_GEN(dev_priv) >= 5)
6177                         intel_encoder->post_disable = ilk_post_disable_dp;
6178         }
6179
6180         intel_dig_port->port = port;
6181         intel_dig_port->dp.output_reg = output_reg;
6182         intel_dig_port->max_lanes = 4;
6183
6184         intel_encoder->type = INTEL_OUTPUT_DP;
6185         intel_encoder->power_domain = intel_port_to_power_domain(port);
6186         if (IS_CHERRYVIEW(dev_priv)) {
6187                 if (port == PORT_D)
6188                         intel_encoder->crtc_mask = 1 << 2;
6189                 else
6190                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6191         } else {
6192                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6193         }
6194         intel_encoder->cloneable = 0;
6195         intel_encoder->port = port;
6196
6197         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6198         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6199
6200         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6201                 goto err_init_connector;
6202
6203         return true;
6204
6205 err_init_connector:
6206         drm_encoder_cleanup(encoder);
6207 err_encoder_init:
6208         kfree(intel_connector);
6209 err_connector_alloc:
6210         kfree(intel_dig_port);
6211         return false;
6212 }
6213
6214 void intel_dp_mst_suspend(struct drm_device *dev)
6215 {
6216         struct drm_i915_private *dev_priv = to_i915(dev);
6217         int i;
6218
6219         /* disable MST */
6220         for (i = 0; i < I915_MAX_PORTS; i++) {
6221                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6222
6223                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6224                         continue;
6225
6226                 if (intel_dig_port->dp.is_mst)
6227                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6228         }
6229 }
6230
6231 void intel_dp_mst_resume(struct drm_device *dev)
6232 {
6233         struct drm_i915_private *dev_priv = to_i915(dev);
6234         int i;
6235
6236         for (i = 0; i < I915_MAX_PORTS; i++) {
6237                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6238                 int ret;
6239
6240                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6241                         continue;
6242
6243                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6244                 if (ret)
6245                         intel_dp_check_mst_status(&intel_dig_port->dp);
6246         }
6247 }