drivers/gpu/drm/i915/intel_dp_link_training.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_dp.h"
  25 #include "intel_drv.h"
  26
  27 static void
  28 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
  29 {
  30
  31         DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
  32                       link_status[0], link_status[1], link_status[2],
  33                       link_status[3], link_status[4], link_status[5]);
  34 }
  35
  36 static void
  37 intel_get_adjust_train(struct intel_dp *intel_dp,
  38                        const u8 link_status[DP_LINK_STATUS_SIZE])
  39 {
  40         u8 v = 0;
  41         u8 p = 0;
  42         int lane;
  43         u8 voltage_max;
  44         u8 preemph_max;
  45
  46         for (lane = 0; lane < intel_dp->lane_count; lane++) {
  47                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
  48                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
  49
  50                 if (this_v > v)
  51                         v = this_v;
  52                 if (this_p > p)
  53                         p = this_p;
  54         }
  55
  56         voltage_max = intel_dp_voltage_max(intel_dp);
  57         if (v >= voltage_max)
  58                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  59
  60         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
  61         if (p >= preemph_max)
  62                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  63
  64         for (lane = 0; lane < 4; lane++)
  65                 intel_dp->train_set[lane] = v | p;
  66 }
  67
  68 static bool
  69 intel_dp_set_link_train(struct intel_dp *intel_dp,
  70                         u8 dp_train_pat)
  71 {
  72         u8 buf[sizeof(intel_dp->train_set) + 1];
  73         int ret, len;
  74
  75         intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
  76
  77         buf[0] = dp_train_pat;
  78         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
  79             DP_TRAINING_PATTERN_DISABLE) {
  80                 /* don't write DP_TRAINING_LANEx_SET on disable */
  81                 len = 1;
  82         } else {
  83                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
  84                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
  85                 len = intel_dp->lane_count + 1;
  86         }
  87
  88         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
  89                                 buf, len);
  90
  91         return ret == len;
  92 }
  93
  94 static bool
  95 intel_dp_reset_link_train(struct intel_dp *intel_dp,
  96                         u8 dp_train_pat)
  97 {
  98         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
  99         intel_dp_set_signal_levels(intel_dp);
 100         return intel_dp_set_link_train(intel_dp, dp_train_pat);
 101 }
 102
 103 static bool
 104 intel_dp_update_link_train(struct intel_dp *intel_dp)
 105 {
 106         int ret;
 107
 108         intel_dp_set_signal_levels(intel_dp);
 109
 110         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
 111                                 intel_dp->train_set, intel_dp->lane_count);
 112
 113         return ret == intel_dp->lane_count;
 114 }
 115
 116 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
 117 {
 118         int lane;
 119
 120         for (lane = 0; lane < intel_dp->lane_count; lane++)
 121                 if ((intel_dp->train_set[lane] &
 122                      DP_TRAIN_MAX_SWING_REACHED) == 0)
 123                         return false;
 124
 125         return true;
 126 }
 127
 128 /* Enable corresponding port and start training pattern 1 */
 129 static bool
 130 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 131 {
 132         u8 voltage;
 133         int voltage_tries, cr_tries, max_cr_tries;
 134         bool max_vswing_reached = false;
 135         u8 link_config[2];
 136         u8 link_bw, rate_select;
 137
 138         if (intel_dp->prepare_link_retrain)
 139                 intel_dp->prepare_link_retrain(intel_dp);
 140
 141         intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
 142                               &link_bw, &rate_select);
 143
 144         if (link_bw)
 145                 DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw);
 146         else
 147                 DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select);
 148
 149         /* Write the link configuration data */
 150         link_config[0] = link_bw;
 151         link_config[1] = intel_dp->lane_count;
 152         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 153                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 154         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 155
 156         /* eDP 1.4 rate select method. */
 157         if (!link_bw)
 158                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 159                                   &rate_select, 1);
 160
 161         link_config[0] = 0;
 162         link_config[1] = DP_SET_ANSI_8B10B;
 163         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 164
 165         intel_dp->DP |= DP_PORT_EN;
 166
 167         /* clock recovery */
 168         if (!intel_dp_reset_link_train(intel_dp,
 169                                        DP_TRAINING_PATTERN_1 |
 170                                        DP_LINK_SCRAMBLING_DISABLE)) {
 171                 DRM_ERROR("failed to enable link training\n");
 172                 return false;
 173         }
 174
 175         /*
 176          * The DP 1.4 spec defines the max clock recovery retries value
 177          * as 10 but for pre-DP 1.4 devices we set a very tolerant
 178          * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
 179          * x 5 identical voltage retries). Since the previous specs didn't
 180          * define a limit and created the possibility of an infinite loop
 181          * we want to prevent any sync from triggering that corner case.
 182          */
 183         if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 184                 max_cr_tries = 10;
 185         else
 186                 max_cr_tries = 80;
 187
 188         voltage_tries = 1;
 189         for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 190                 u8 link_status[DP_LINK_STATUS_SIZE];
 191
 192                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
 193
 194                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 195                         DRM_ERROR("failed to get link status\n");
 196                         return false;
 197                 }
 198
 199                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 200                         DRM_DEBUG_KMS("clock recovery OK\n");
 201                         return true;
 202                 }
 203
 204                 if (voltage_tries == 5) {
 205                         DRM_DEBUG_KMS("Same voltage tried 5 times\n");
 206                         return false;
 207                 }
 208
 209                 if (max_vswing_reached) {
 210                         DRM_DEBUG_KMS("Max Voltage Swing reached\n");
 211                         return false;
 212                 }
 213
 214                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 215
 216                 /* Update training set as requested by target */
 217                 intel_get_adjust_train(intel_dp, link_status);
 218                 if (!intel_dp_update_link_train(intel_dp)) {
 219                         DRM_ERROR("failed to update link training\n");
 220                         return false;
 221                 }
 222
 223                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
 224                     voltage)
 225                         ++voltage_tries;
 226                 else
 227                         voltage_tries = 1;
 228
 229                 if (intel_dp_link_max_vswing_reached(intel_dp))
 230                         max_vswing_reached = true;
 231
 232         }
 233         DRM_ERROR("Failed clock recovery %d times, giving up!\n", max_cr_tries);
 234         return false;
 235 }
 236
 237 /*
 238  * Pick training pattern for channel equalization. Training pattern 4 for HBR3
 239  * or for 1.4 devices that support it, training Pattern 3 for HBR2
 240  * or 1.2 devices that support it, Training Pattern 2 otherwise.
 241  */
 242 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 243 {
 244         bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 245
 246         /*
 247          * Intel platforms that support HBR3 also support TPS4. It is mandatory
 248          * for all downstream devices that support HBR3. There are no known eDP
 249          * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
 250          * specification.
 251          */
 252         source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
 253         sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
 254         if (source_tps4 && sink_tps4) {
 255                 return DP_TRAINING_PATTERN_4;
 256         } else if (intel_dp->link_rate == 810000) {
 257                 if (!source_tps4)
 258                         DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n");
 259                 if (!sink_tps4)
 260                         DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n");
 261         }
 262         /*
 263          * Intel platforms that support HBR2 also support TPS3. TPS3 support is
 264          * also mandatory for downstream devices that support HBR2. However, not
 265          * all sinks follow the spec.
 266          */
 267         source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
 268         sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
 269         if (source_tps3 && sink_tps3) {
 270                 return  DP_TRAINING_PATTERN_3;
 271         } else if (intel_dp->link_rate >= 540000) {
 272                 if (!source_tps3)
 273                         DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
 274                 if (!sink_tps3)
 275                         DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
 276         }
 277
 278         return DP_TRAINING_PATTERN_2;
 279 }
 280
 281 static bool
 282 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 283 {
 284         int tries;
 285         u32 training_pattern;
 286         u8 link_status[DP_LINK_STATUS_SIZE];
 287         bool channel_eq = false;
 288
 289         training_pattern = intel_dp_training_pattern(intel_dp);
 290         /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 291         if (training_pattern != DP_TRAINING_PATTERN_4)
 292                 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 293
 294         /* channel equalization */
 295         if (!intel_dp_set_link_train(intel_dp,
 296                                      training_pattern)) {
 297                 DRM_ERROR("failed to start channel equalization\n");
 298                 return false;
 299         }
 300
 301         for (tries = 0; tries < 5; tries++) {
 302
 303                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
 304                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 305                         DRM_ERROR("failed to get link status\n");
 306                         break;
 307                 }
 308
 309                 /* Make sure clock is still ok */
 310                 if (!drm_dp_clock_recovery_ok(link_status,
 311                                               intel_dp->lane_count)) {
 312                         intel_dp_dump_link_status(link_status);
 313                         DRM_DEBUG_KMS("Clock recovery check failed, cannot "
 314                                       "continue channel equalization\n");
 315                         break;
 316                 }
 317
 318                 if (drm_dp_channel_eq_ok(link_status,
 319                                          intel_dp->lane_count)) {
 320                         channel_eq = true;
 321                         DRM_DEBUG_KMS("Channel EQ done. DP Training "
 322                                       "successful\n");
 323                         break;
 324                 }
 325
 326                 /* Update training set as requested by target */
 327                 intel_get_adjust_train(intel_dp, link_status);
 328                 if (!intel_dp_update_link_train(intel_dp)) {
 329                         DRM_ERROR("failed to update link training\n");
 330                         break;
 331                 }
 332         }
 333
 334         /* Try 5 times, else fail and try at lower BW */
 335         if (tries == 5) {
 336                 intel_dp_dump_link_status(link_status);
 337                 DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
 338         }
 339
 340         intel_dp_set_idle_link_train(intel_dp);
 341
 342         return channel_eq;
 343
 344 }
 345
 346 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
 347 {
 348         intel_dp->link_trained = true;
 349
 350         intel_dp_set_link_train(intel_dp,
 351                                 DP_TRAINING_PATTERN_DISABLE);
 352 }
 353
 354 void
 355 intel_dp_start_link_train(struct intel_dp *intel_dp)
 356 {
 357         struct intel_connector *intel_connector = intel_dp->attached_connector;
 358
 359         if (!intel_dp_link_training_clock_recovery(intel_dp))
 360                 goto failure_handling;
 361         if (!intel_dp_link_training_channel_equalization(intel_dp))
 362                 goto failure_handling;
 363
 364         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
 365                       intel_connector->base.base.id,
 366                       intel_connector->base.name,
 367                       intel_dp->link_rate, intel_dp->lane_count);
 368         return;
 369
 370  failure_handling:
 371         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
 372                       intel_connector->base.base.id,
 373                       intel_connector->base.name,
 374                       intel_dp->link_rate, intel_dp->lane_count);
 375         if (!intel_dp_get_link_train_fallback_values(intel_dp,
 376                                                      intel_dp->link_rate,
 377                                                      intel_dp->lane_count))
 378                 /* Schedule a Hotplug Uevent to userspace to start modeset */
 379                 schedule_work(&intel_connector->modeset_retry_work);
 380         return;
 381 }