2 * Copyright © 2008-2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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11 * The above copyright notice and this permission notice (including the next
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24 #include "intel_drv.h"
27 intel_get_adjust_train(struct intel_dp *intel_dp,
28 const uint8_t link_status[DP_LINK_STATUS_SIZE])
36 for (lane = 0; lane < intel_dp->lane_count; lane++) {
37 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
38 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
46 voltage_max = intel_dp_voltage_max(intel_dp);
48 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
50 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
52 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
54 for (lane = 0; lane < 4; lane++)
55 intel_dp->train_set[lane] = v | p;
59 intel_dp_set_link_train(struct intel_dp *intel_dp,
62 uint8_t buf[sizeof(intel_dp->train_set) + 1];
65 intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
67 buf[0] = dp_train_pat;
68 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
69 DP_TRAINING_PATTERN_DISABLE) {
70 /* don't write DP_TRAINING_LANEx_SET on disable */
73 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
74 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
75 len = intel_dp->lane_count + 1;
78 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
85 intel_dp_reset_link_train(struct intel_dp *intel_dp,
88 if (!intel_dp->train_set_valid)
89 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
90 intel_dp_set_signal_levels(intel_dp);
91 return intel_dp_set_link_train(intel_dp, dp_train_pat);
95 intel_dp_update_link_train(struct intel_dp *intel_dp)
99 intel_dp_set_signal_levels(intel_dp);
101 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
102 intel_dp->train_set, intel_dp->lane_count);
104 return ret == intel_dp->lane_count;
107 /* Enable corresponding port and start training pattern 1 */
109 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
113 int voltage_tries, loop_tries;
114 uint8_t link_config[2];
115 uint8_t link_bw, rate_select;
117 if (intel_dp->prepare_link_retrain)
118 intel_dp->prepare_link_retrain(intel_dp);
120 intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
121 &link_bw, &rate_select);
123 /* Write the link configuration data */
124 link_config[0] = link_bw;
125 link_config[1] = intel_dp->lane_count;
126 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
127 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
128 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
129 if (intel_dp->num_sink_rates)
130 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
134 link_config[1] = DP_SET_ANSI_8B10B;
135 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
137 intel_dp->DP |= DP_PORT_EN;
140 if (!intel_dp_reset_link_train(intel_dp,
141 DP_TRAINING_PATTERN_1 |
142 DP_LINK_SCRAMBLING_DISABLE)) {
143 DRM_ERROR("failed to enable link training\n");
151 uint8_t link_status[DP_LINK_STATUS_SIZE];
153 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
154 if (!intel_dp_get_link_status(intel_dp, link_status)) {
155 DRM_ERROR("failed to get link status\n");
159 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
160 DRM_DEBUG_KMS("clock recovery OK\n");
165 * if we used previously trained voltage and pre-emphasis values
166 * and we don't get clock recovery, reset link training values
168 if (intel_dp->train_set_valid) {
169 DRM_DEBUG_KMS("clock recovery not ok, reset");
170 /* clear the flag as we are not reusing train set */
171 intel_dp->train_set_valid = false;
172 if (!intel_dp_reset_link_train(intel_dp,
173 DP_TRAINING_PATTERN_1 |
174 DP_LINK_SCRAMBLING_DISABLE)) {
175 DRM_ERROR("failed to enable link training\n");
181 /* Check to see if we've tried the max voltage */
182 for (i = 0; i < intel_dp->lane_count; i++)
183 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
185 if (i == intel_dp->lane_count) {
187 if (loop_tries == 5) {
188 DRM_ERROR("too many full retries, give up\n");
191 intel_dp_reset_link_train(intel_dp,
192 DP_TRAINING_PATTERN_1 |
193 DP_LINK_SCRAMBLING_DISABLE);
198 /* Check to see if we've tried the same voltage 5 times */
199 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
201 if (voltage_tries == 5) {
202 DRM_ERROR("too many voltage retries, give up\n");
207 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
209 /* Update training set as requested by target */
210 intel_get_adjust_train(intel_dp, link_status);
211 if (!intel_dp_update_link_train(intel_dp)) {
212 DRM_ERROR("failed to update link training\n");
219 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
221 bool channel_eq = false;
223 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
226 * Training Pattern 3 for HBR2 or 1.2 devices that support it.
228 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
229 * also mandatory for downstream devices that support HBR2.
231 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
232 * supported but still not enabled.
234 if (intel_dp_source_supports_hbr2(intel_dp) &&
235 drm_dp_tps3_supported(intel_dp->dpcd))
236 training_pattern = DP_TRAINING_PATTERN_3;
237 else if (intel_dp->link_rate == 540000)
238 DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
240 /* channel equalization */
241 if (!intel_dp_set_link_train(intel_dp,
243 DP_LINK_SCRAMBLING_DISABLE)) {
244 DRM_ERROR("failed to start channel equalization\n");
252 uint8_t link_status[DP_LINK_STATUS_SIZE];
255 DRM_ERROR("failed to train DP, aborting\n");
259 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
260 if (!intel_dp_get_link_status(intel_dp, link_status)) {
261 DRM_ERROR("failed to get link status\n");
265 /* Make sure clock is still ok */
266 if (!drm_dp_clock_recovery_ok(link_status,
267 intel_dp->lane_count)) {
268 intel_dp->train_set_valid = false;
269 intel_dp_link_training_clock_recovery(intel_dp);
270 intel_dp_set_link_train(intel_dp,
272 DP_LINK_SCRAMBLING_DISABLE);
277 if (drm_dp_channel_eq_ok(link_status,
278 intel_dp->lane_count)) {
283 /* Try 5 times, then try clock recovery if that fails */
285 intel_dp->train_set_valid = false;
286 intel_dp_link_training_clock_recovery(intel_dp);
287 intel_dp_set_link_train(intel_dp,
289 DP_LINK_SCRAMBLING_DISABLE);
295 /* Update training set as requested by target */
296 intel_get_adjust_train(intel_dp, link_status);
297 if (!intel_dp_update_link_train(intel_dp)) {
298 DRM_ERROR("failed to update link training\n");
304 intel_dp_set_idle_link_train(intel_dp);
307 intel_dp->train_set_valid = true;
308 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
312 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
314 intel_dp_set_link_train(intel_dp,
315 DP_TRAINING_PATTERN_DISABLE);
319 intel_dp_start_link_train(struct intel_dp *intel_dp)
321 intel_dp_link_training_clock_recovery(intel_dp);
322 intel_dp_link_training_channel_equalization(intel_dp);