2 * Copyright © 2006-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
29 * Display PLLs used for driving outputs vary by platform. While some have
30 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
31 * from a pool. In the latter scenario, it is possible that multiple pipes
32 * share a PLL if their configurations match.
34 * This file provides an abstraction over display PLLs. The function
35 * intel_shared_dpll_init() initializes the PLLs for the given platform. The
36 * users of a PLL are tracked and that tracking is integrated with the atomic
37 * modest interface. During an atomic operation, a PLL can be requested for a
38 * given CRTC and encoder configuration by calling intel_get_shared_dpll() and
39 * a previously used PLL can be released with intel_release_shared_dpll().
40 * Changes to the users are first staged in the atomic state, and then made
41 * effective by calling intel_shared_dpll_swap_state() during the atomic
46 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
47 struct intel_shared_dpll_state *shared_dpll)
51 /* Copy shared dpll state */
52 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
53 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
55 shared_dpll[i] = pll->state;
59 static struct intel_shared_dpll_state *
60 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
62 struct intel_atomic_state *state = to_intel_atomic_state(s);
64 WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
66 if (!state->dpll_set) {
67 state->dpll_set = true;
69 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
73 return state->shared_dpll;
77 * intel_get_shared_dpll_by_id - get a DPLL given its id
78 * @dev_priv: i915 device instance
82 * A pointer to the DPLL with @id
84 struct intel_shared_dpll *
85 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
86 enum intel_dpll_id id)
88 return &dev_priv->shared_dplls[id];
92 * intel_get_shared_dpll_id - get the id of a DPLL
93 * @dev_priv: i915 device instance
100 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
101 struct intel_shared_dpll *pll)
103 if (WARN_ON(pll < dev_priv->shared_dplls||
104 pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll]))
107 return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
111 void assert_shared_dpll(struct drm_i915_private *dev_priv,
112 struct intel_shared_dpll *pll,
116 struct intel_dpll_hw_state hw_state;
118 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
121 cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state);
122 I915_STATE_WARN(cur_state != state,
123 "%s assertion failure (expected %s, current %s)\n",
124 pll->name, onoff(state), onoff(cur_state));
128 * intel_prepare_shared_dpll - call a dpll's prepare hook
129 * @crtc: CRTC which has a shared dpll
131 * This calls the PLL's prepare hook if it has one and if the PLL is not
132 * already enabled. The prepare hook is platform specific.
134 void intel_prepare_shared_dpll(struct intel_crtc *crtc)
136 struct drm_device *dev = crtc->base.dev;
137 struct drm_i915_private *dev_priv = to_i915(dev);
138 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
140 if (WARN_ON(pll == NULL))
143 mutex_lock(&dev_priv->dpll_lock);
144 WARN_ON(!pll->state.crtc_mask);
145 if (!pll->active_mask) {
146 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
148 assert_shared_dpll_disabled(dev_priv, pll);
150 pll->funcs.prepare(dev_priv, pll);
152 mutex_unlock(&dev_priv->dpll_lock);
156 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
157 * @crtc: CRTC which has a shared DPLL
159 * Enable the shared DPLL used by @crtc.
161 void intel_enable_shared_dpll(struct intel_crtc *crtc)
163 struct drm_device *dev = crtc->base.dev;
164 struct drm_i915_private *dev_priv = to_i915(dev);
165 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
166 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
169 if (WARN_ON(pll == NULL))
172 mutex_lock(&dev_priv->dpll_lock);
173 old_mask = pll->active_mask;
175 if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) ||
176 WARN_ON(pll->active_mask & crtc_mask))
179 pll->active_mask |= crtc_mask;
181 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
182 pll->name, pll->active_mask, pll->on,
187 assert_shared_dpll_enabled(dev_priv, pll);
192 DRM_DEBUG_KMS("enabling %s\n", pll->name);
193 pll->funcs.enable(dev_priv, pll);
197 mutex_unlock(&dev_priv->dpll_lock);
201 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
202 * @crtc: CRTC which has a shared DPLL
204 * Disable the shared DPLL used by @crtc.
206 void intel_disable_shared_dpll(struct intel_crtc *crtc)
208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
209 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
210 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
212 /* PCH only available on ILK+ */
213 if (INTEL_GEN(dev_priv) < 5)
219 mutex_lock(&dev_priv->dpll_lock);
220 if (WARN_ON(!(pll->active_mask & crtc_mask)))
223 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
224 pll->name, pll->active_mask, pll->on,
227 assert_shared_dpll_enabled(dev_priv, pll);
230 pll->active_mask &= ~crtc_mask;
231 if (pll->active_mask)
234 DRM_DEBUG_KMS("disabling %s\n", pll->name);
235 pll->funcs.disable(dev_priv, pll);
239 mutex_unlock(&dev_priv->dpll_lock);
242 static struct intel_shared_dpll *
243 intel_find_shared_dpll(struct intel_crtc *crtc,
244 struct intel_crtc_state *crtc_state,
245 enum intel_dpll_id range_min,
246 enum intel_dpll_id range_max)
248 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
249 struct intel_shared_dpll *pll;
250 struct intel_shared_dpll_state *shared_dpll;
251 enum intel_dpll_id i;
253 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
255 for (i = range_min; i <= range_max; i++) {
256 pll = &dev_priv->shared_dplls[i];
258 /* Only want to check enabled timings first */
259 if (shared_dpll[i].crtc_mask == 0)
262 if (memcmp(&crtc_state->dpll_hw_state,
263 &shared_dpll[i].hw_state,
264 sizeof(crtc_state->dpll_hw_state)) == 0) {
265 DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
266 crtc->base.base.id, crtc->base.name, pll->name,
267 shared_dpll[i].crtc_mask,
273 /* Ok no matching timings, maybe there's a free one? */
274 for (i = range_min; i <= range_max; i++) {
275 pll = &dev_priv->shared_dplls[i];
276 if (shared_dpll[i].crtc_mask == 0) {
277 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
278 crtc->base.base.id, crtc->base.name, pll->name);
287 intel_reference_shared_dpll(struct intel_shared_dpll *pll,
288 struct intel_crtc_state *crtc_state)
290 struct intel_shared_dpll_state *shared_dpll;
291 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
292 enum intel_dpll_id i = pll->id;
294 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
296 if (shared_dpll[i].crtc_mask == 0)
297 shared_dpll[i].hw_state =
298 crtc_state->dpll_hw_state;
300 crtc_state->shared_dpll = pll;
301 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
302 pipe_name(crtc->pipe));
304 shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe;
308 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
309 * @state: atomic state
311 * This is the dpll version of drm_atomic_helper_swap_state() since the
312 * helper does not handle driver-specific global state.
314 * For consistency with atomic helpers this function does a complete swap,
315 * i.e. it also puts the current state into @state, even though there is no
316 * need for that at this moment.
318 void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
320 struct drm_i915_private *dev_priv = to_i915(state->dev);
321 struct intel_shared_dpll_state *shared_dpll;
322 struct intel_shared_dpll *pll;
323 enum intel_dpll_id i;
325 if (!to_intel_atomic_state(state)->dpll_set)
328 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
329 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
330 struct intel_shared_dpll_state tmp;
332 pll = &dev_priv->shared_dplls[i];
335 pll->state = shared_dpll[i];
336 shared_dpll[i] = tmp;
340 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
341 struct intel_shared_dpll *pll,
342 struct intel_dpll_hw_state *hw_state)
346 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
349 val = I915_READ(PCH_DPLL(pll->id));
350 hw_state->dpll = val;
351 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
352 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
354 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
356 return val & DPLL_VCO_ENABLE;
359 static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
360 struct intel_shared_dpll *pll)
362 I915_WRITE(PCH_FP0(pll->id), pll->state.hw_state.fp0);
363 I915_WRITE(PCH_FP1(pll->id), pll->state.hw_state.fp1);
366 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
371 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
373 val = I915_READ(PCH_DREF_CONTROL);
374 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
375 DREF_SUPERSPREAD_SOURCE_MASK));
376 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
379 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
380 struct intel_shared_dpll *pll)
382 /* PCH refclock must be enabled first */
383 ibx_assert_pch_refclk_enabled(dev_priv);
385 I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
387 /* Wait for the clocks to stabilize. */
388 POSTING_READ(PCH_DPLL(pll->id));
391 /* The pixel multiplier can only be updated once the
392 * DPLL is enabled and the clocks are stable.
396 I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
397 POSTING_READ(PCH_DPLL(pll->id));
401 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
402 struct intel_shared_dpll *pll)
404 struct drm_device *dev = &dev_priv->drm;
405 struct intel_crtc *crtc;
407 /* Make sure no transcoder isn't still depending on us. */
408 for_each_intel_crtc(dev, crtc) {
409 if (crtc->config->shared_dpll == pll)
410 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
413 I915_WRITE(PCH_DPLL(pll->id), 0);
414 POSTING_READ(PCH_DPLL(pll->id));
418 static struct intel_shared_dpll *
419 ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
420 struct intel_encoder *encoder)
422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
423 struct intel_shared_dpll *pll;
424 enum intel_dpll_id i;
426 if (HAS_PCH_IBX(dev_priv)) {
427 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
428 i = (enum intel_dpll_id) crtc->pipe;
429 pll = &dev_priv->shared_dplls[i];
431 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
432 crtc->base.base.id, crtc->base.name, pll->name);
434 pll = intel_find_shared_dpll(crtc, crtc_state,
442 /* reference the pll */
443 intel_reference_shared_dpll(pll, crtc_state);
448 static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
449 struct intel_dpll_hw_state *hw_state)
451 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
452 "fp0: 0x%x, fp1: 0x%x\n",
459 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
460 .prepare = ibx_pch_dpll_prepare,
461 .enable = ibx_pch_dpll_enable,
462 .disable = ibx_pch_dpll_disable,
463 .get_hw_state = ibx_pch_dpll_get_hw_state,
466 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
467 struct intel_shared_dpll *pll)
469 I915_WRITE(WRPLL_CTL(pll->id), pll->state.hw_state.wrpll);
470 POSTING_READ(WRPLL_CTL(pll->id));
474 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
475 struct intel_shared_dpll *pll)
477 I915_WRITE(SPLL_CTL, pll->state.hw_state.spll);
478 POSTING_READ(SPLL_CTL);
482 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
483 struct intel_shared_dpll *pll)
487 val = I915_READ(WRPLL_CTL(pll->id));
488 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
489 POSTING_READ(WRPLL_CTL(pll->id));
492 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
493 struct intel_shared_dpll *pll)
497 val = I915_READ(SPLL_CTL);
498 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
499 POSTING_READ(SPLL_CTL);
502 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
503 struct intel_shared_dpll *pll,
504 struct intel_dpll_hw_state *hw_state)
508 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
511 val = I915_READ(WRPLL_CTL(pll->id));
512 hw_state->wrpll = val;
514 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
516 return val & WRPLL_PLL_ENABLE;
519 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
520 struct intel_shared_dpll *pll,
521 struct intel_dpll_hw_state *hw_state)
525 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
528 val = I915_READ(SPLL_CTL);
529 hw_state->spll = val;
531 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
533 return val & SPLL_PLL_ENABLE;
537 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
543 /* Constraints for PLL good behavior */
549 struct hsw_wrpll_rnp {
553 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
627 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
628 unsigned r2, unsigned n2, unsigned p,
629 struct hsw_wrpll_rnp *best)
631 uint64_t a, b, c, d, diff, diff_best;
633 /* No best (r,n,p) yet */
642 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
646 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
649 * and we would like delta <= budget.
651 * If the discrepancy is above the PPM-based budget, always prefer to
652 * improve upon the previous solution. However, if you're within the
653 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
655 a = freq2k * budget * p * r2;
656 b = freq2k * budget * best->p * best->r2;
657 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
658 diff_best = abs_diff(freq2k * best->p * best->r2,
659 LC_FREQ_2K * best->n2);
661 d = 1000000 * diff_best;
663 if (a < c && b < d) {
664 /* If both are above the budget, pick the closer */
665 if (best->p * best->r2 * diff < p * r2 * diff_best) {
670 } else if (a >= c && b < d) {
671 /* If A is below the threshold but B is above it? Update. */
675 } else if (a >= c && b >= d) {
676 /* Both are below the limit, so pick the higher n2/(r2*r2) */
677 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
683 /* Otherwise a < c && b >= d, do nothing */
687 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
688 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
692 struct hsw_wrpll_rnp best = { 0, 0, 0 };
695 freq2k = clock / 100;
697 budget = hsw_wrpll_get_budget_for_freq(clock);
699 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
700 * and directly pass the LC PLL to it. */
701 if (freq2k == 5400000) {
709 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
712 * We want R so that REF_MIN <= Ref <= REF_MAX.
713 * Injecting R2 = 2 * R gives:
714 * REF_MAX * r2 > LC_FREQ * 2 and
715 * REF_MIN * r2 < LC_FREQ * 2
717 * Which means the desired boundaries for r2 are:
718 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
721 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
722 r2 <= LC_FREQ * 2 / REF_MIN;
726 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
728 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
729 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
730 * VCO_MAX * r2 > n2 * LC_FREQ and
731 * VCO_MIN * r2 < n2 * LC_FREQ)
733 * Which means the desired boundaries for n2 are:
734 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
736 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
737 n2 <= VCO_MAX * r2 / LC_FREQ;
740 for (p = P_MIN; p <= P_MAX; p += P_INC)
741 hsw_wrpll_update_rnp(freq2k, budget,
751 static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock,
752 struct intel_crtc *crtc,
753 struct intel_crtc_state *crtc_state)
755 struct intel_shared_dpll *pll;
757 unsigned int p, n2, r2;
759 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
761 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
762 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
763 WRPLL_DIVIDER_POST(p);
765 crtc_state->dpll_hw_state.wrpll = val;
767 pll = intel_find_shared_dpll(crtc, crtc_state,
768 DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
776 static struct intel_shared_dpll *
777 hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, int clock)
779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
780 struct intel_shared_dpll *pll;
781 enum intel_dpll_id pll_id;
785 pll_id = DPLL_ID_LCPLL_810;
788 pll_id = DPLL_ID_LCPLL_1350;
791 pll_id = DPLL_ID_LCPLL_2700;
794 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
798 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
806 static struct intel_shared_dpll *
807 hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
808 struct intel_encoder *encoder)
810 struct intel_shared_dpll *pll;
811 int clock = crtc_state->port_clock;
813 memset(&crtc_state->dpll_hw_state, 0,
814 sizeof(crtc_state->dpll_hw_state));
816 if (encoder->type == INTEL_OUTPUT_HDMI) {
817 pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state);
819 } else if (encoder->type == INTEL_OUTPUT_DP ||
820 encoder->type == INTEL_OUTPUT_DP_MST ||
821 encoder->type == INTEL_OUTPUT_EDP) {
822 pll = hsw_ddi_dp_get_dpll(encoder, clock);
824 } else if (encoder->type == INTEL_OUTPUT_ANALOG) {
825 if (WARN_ON(crtc_state->port_clock / 2 != 135000))
828 crtc_state->dpll_hw_state.spll =
829 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
831 pll = intel_find_shared_dpll(crtc, crtc_state,
832 DPLL_ID_SPLL, DPLL_ID_SPLL);
840 intel_reference_shared_dpll(pll, crtc_state);
845 static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
846 struct intel_dpll_hw_state *hw_state)
848 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
849 hw_state->wrpll, hw_state->spll);
852 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
853 .enable = hsw_ddi_wrpll_enable,
854 .disable = hsw_ddi_wrpll_disable,
855 .get_hw_state = hsw_ddi_wrpll_get_hw_state,
858 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
859 .enable = hsw_ddi_spll_enable,
860 .disable = hsw_ddi_spll_disable,
861 .get_hw_state = hsw_ddi_spll_get_hw_state,
864 static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
865 struct intel_shared_dpll *pll)
869 static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
870 struct intel_shared_dpll *pll)
874 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
875 struct intel_shared_dpll *pll,
876 struct intel_dpll_hw_state *hw_state)
881 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
882 .enable = hsw_ddi_lcpll_enable,
883 .disable = hsw_ddi_lcpll_disable,
884 .get_hw_state = hsw_ddi_lcpll_get_hw_state,
887 struct skl_dpll_regs {
888 i915_reg_t ctl, cfgcr1, cfgcr2;
891 /* this array is indexed by the *shared* pll id */
892 static const struct skl_dpll_regs skl_dpll_regs[4] = {
896 /* DPLL 0 doesn't support HDMI mode */
901 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
902 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
907 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
908 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
913 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
914 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
918 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
919 struct intel_shared_dpll *pll)
923 val = I915_READ(DPLL_CTRL1);
925 val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) |
926 DPLL_CTRL1_LINK_RATE_MASK(pll->id));
927 val |= pll->state.hw_state.ctrl1 << (pll->id * 6);
929 I915_WRITE(DPLL_CTRL1, val);
930 POSTING_READ(DPLL_CTRL1);
933 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
934 struct intel_shared_dpll *pll)
936 const struct skl_dpll_regs *regs = skl_dpll_regs;
938 skl_ddi_pll_write_ctrl1(dev_priv, pll);
940 I915_WRITE(regs[pll->id].cfgcr1, pll->state.hw_state.cfgcr1);
941 I915_WRITE(regs[pll->id].cfgcr2, pll->state.hw_state.cfgcr2);
942 POSTING_READ(regs[pll->id].cfgcr1);
943 POSTING_READ(regs[pll->id].cfgcr2);
945 /* the enable bit is always bit 31 */
946 I915_WRITE(regs[pll->id].ctl,
947 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
949 if (intel_wait_for_register(dev_priv,
954 DRM_ERROR("DPLL %d not locked\n", pll->id);
957 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
958 struct intel_shared_dpll *pll)
960 skl_ddi_pll_write_ctrl1(dev_priv, pll);
963 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
964 struct intel_shared_dpll *pll)
966 const struct skl_dpll_regs *regs = skl_dpll_regs;
968 /* the enable bit is always bit 31 */
969 I915_WRITE(regs[pll->id].ctl,
970 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
971 POSTING_READ(regs[pll->id].ctl);
974 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
975 struct intel_shared_dpll *pll)
979 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
980 struct intel_shared_dpll *pll,
981 struct intel_dpll_hw_state *hw_state)
984 const struct skl_dpll_regs *regs = skl_dpll_regs;
987 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
992 val = I915_READ(regs[pll->id].ctl);
993 if (!(val & LCPLL_PLL_ENABLE))
996 val = I915_READ(DPLL_CTRL1);
997 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
999 /* avoid reading back stale values if HDMI mode is not enabled */
1000 if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) {
1001 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1002 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1007 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1012 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
1013 struct intel_shared_dpll *pll,
1014 struct intel_dpll_hw_state *hw_state)
1017 const struct skl_dpll_regs *regs = skl_dpll_regs;
1020 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1025 /* DPLL0 is always enabled since it drives CDCLK */
1026 val = I915_READ(regs[pll->id].ctl);
1027 if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
1030 val = I915_READ(DPLL_CTRL1);
1031 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
1036 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1041 struct skl_wrpll_context {
1042 uint64_t min_deviation; /* current minimal deviation */
1043 uint64_t central_freq; /* chosen central freq */
1044 uint64_t dco_freq; /* chosen dco freq */
1045 unsigned int p; /* chosen divider */
1048 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1050 memset(ctx, 0, sizeof(*ctx));
1052 ctx->min_deviation = U64_MAX;
1055 /* DCO freq must be within +1%/-6% of the DCO central freq */
1056 #define SKL_DCO_MAX_PDEVIATION 100
1057 #define SKL_DCO_MAX_NDEVIATION 600
1059 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1060 uint64_t central_freq,
1062 unsigned int divider)
1066 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1069 /* positive deviation */
1070 if (dco_freq >= central_freq) {
1071 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1072 deviation < ctx->min_deviation) {
1073 ctx->min_deviation = deviation;
1074 ctx->central_freq = central_freq;
1075 ctx->dco_freq = dco_freq;
1078 /* negative deviation */
1079 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1080 deviation < ctx->min_deviation) {
1081 ctx->min_deviation = deviation;
1082 ctx->central_freq = central_freq;
1083 ctx->dco_freq = dco_freq;
1088 static void skl_wrpll_get_multipliers(unsigned int p,
1089 unsigned int *p0 /* out */,
1090 unsigned int *p1 /* out */,
1091 unsigned int *p2 /* out */)
1095 unsigned int half = p / 2;
1097 if (half == 1 || half == 2 || half == 3 || half == 5) {
1101 } else if (half % 2 == 0) {
1105 } else if (half % 3 == 0) {
1109 } else if (half % 7 == 0) {
1114 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1118 } else if (p == 5 || p == 7) {
1122 } else if (p == 15) {
1126 } else if (p == 21) {
1130 } else if (p == 35) {
1137 struct skl_wrpll_params {
1138 uint32_t dco_fraction;
1139 uint32_t dco_integer;
1140 uint32_t qdiv_ratio;
1144 uint32_t central_freq;
1147 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1149 uint64_t central_freq,
1150 uint32_t p0, uint32_t p1, uint32_t p2)
1154 switch (central_freq) {
1156 params->central_freq = 0;
1159 params->central_freq = 1;
1162 params->central_freq = 3;
1179 WARN(1, "Incorrect PDiv\n");
1196 WARN(1, "Incorrect KDiv\n");
1199 params->qdiv_ratio = p1;
1200 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1202 dco_freq = p0 * p1 * p2 * afe_clock;
1205 * Intermediate values are in Hz.
1206 * Divide by MHz to match bsepc
1208 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1209 params->dco_fraction =
1210 div_u64((div_u64(dco_freq, 24) -
1211 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1215 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1216 struct skl_wrpll_params *wrpll_params)
1218 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1219 uint64_t dco_central_freq[3] = {8400000000ULL,
1222 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1223 24, 28, 30, 32, 36, 40, 42, 44,
1224 48, 52, 54, 56, 60, 64, 66, 68,
1225 70, 72, 76, 78, 80, 84, 88, 90,
1227 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1228 static const struct {
1232 { even_dividers, ARRAY_SIZE(even_dividers) },
1233 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1235 struct skl_wrpll_context ctx;
1236 unsigned int dco, d, i;
1237 unsigned int p0, p1, p2;
1239 skl_wrpll_context_init(&ctx);
1241 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1242 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1243 for (i = 0; i < dividers[d].n_dividers; i++) {
1244 unsigned int p = dividers[d].list[i];
1245 uint64_t dco_freq = p * afe_clock;
1247 skl_wrpll_try_divider(&ctx,
1248 dco_central_freq[dco],
1252 * Skip the remaining dividers if we're sure to
1253 * have found the definitive divider, we can't
1254 * improve a 0 deviation.
1256 if (ctx.min_deviation == 0)
1257 goto skip_remaining_dividers;
1261 skip_remaining_dividers:
1263 * If a solution is found with an even divider, prefer
1266 if (d == 0 && ctx.p)
1271 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1276 * gcc incorrectly analyses that these can be used without being
1277 * initialized. To be fair, it's hard to guess.
1280 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1281 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1287 static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
1288 struct intel_crtc_state *crtc_state,
1291 uint32_t ctrl1, cfgcr1, cfgcr2;
1292 struct skl_wrpll_params wrpll_params = { 0, };
1295 * See comment in intel_dpll_hw_state to understand why we always use 0
1296 * as the DPLL id in this function.
1298 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1300 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1302 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1305 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1306 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1307 wrpll_params.dco_integer;
1309 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1310 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1311 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1312 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1313 wrpll_params.central_freq;
1315 memset(&crtc_state->dpll_hw_state, 0,
1316 sizeof(crtc_state->dpll_hw_state));
1318 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1319 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1320 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1325 skl_ddi_dp_set_dpll_hw_state(int clock,
1326 struct intel_dpll_hw_state *dpll_hw_state)
1331 * See comment in intel_dpll_hw_state to understand why we always use 0
1332 * as the DPLL id in this function.
1334 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1335 switch (clock / 2) {
1337 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1340 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1343 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1347 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1350 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1353 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1357 dpll_hw_state->ctrl1 = ctrl1;
1361 static struct intel_shared_dpll *
1362 skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1363 struct intel_encoder *encoder)
1365 struct intel_shared_dpll *pll;
1366 int clock = crtc_state->port_clock;
1368 struct intel_dpll_hw_state dpll_hw_state;
1370 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
1372 if (encoder->type == INTEL_OUTPUT_HDMI) {
1373 bret = skl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
1375 DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
1378 } else if (encoder->type == INTEL_OUTPUT_DP ||
1379 encoder->type == INTEL_OUTPUT_DP_MST ||
1380 encoder->type == INTEL_OUTPUT_EDP) {
1381 bret = skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
1383 DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
1386 crtc_state->dpll_hw_state = dpll_hw_state;
1391 if (encoder->type == INTEL_OUTPUT_EDP)
1392 pll = intel_find_shared_dpll(crtc, crtc_state,
1396 pll = intel_find_shared_dpll(crtc, crtc_state,
1402 intel_reference_shared_dpll(pll, crtc_state);
1407 static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
1408 struct intel_dpll_hw_state *hw_state)
1410 DRM_DEBUG_KMS("dpll_hw_state: "
1411 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1417 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1418 .enable = skl_ddi_pll_enable,
1419 .disable = skl_ddi_pll_disable,
1420 .get_hw_state = skl_ddi_pll_get_hw_state,
1423 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1424 .enable = skl_ddi_dpll0_enable,
1425 .disable = skl_ddi_dpll0_disable,
1426 .get_hw_state = skl_ddi_dpll0_get_hw_state,
1429 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1430 struct intel_shared_dpll *pll)
1433 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1435 enum dpio_channel ch;
1437 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1439 /* Non-SSC reference */
1440 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1441 temp |= PORT_PLL_REF_SEL;
1442 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1444 if (IS_GEMINILAKE(dev_priv)) {
1445 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1446 temp |= PORT_PLL_POWER_ENABLE;
1447 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1449 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1450 PORT_PLL_POWER_STATE), 200))
1451 DRM_ERROR("Power state not set for PLL:%d\n", port);
1454 /* Disable 10 bit clock */
1455 temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1456 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1457 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1460 temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1461 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
1462 temp |= pll->state.hw_state.ebb0;
1463 I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp);
1465 /* Write M2 integer */
1466 temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1467 temp &= ~PORT_PLL_M2_MASK;
1468 temp |= pll->state.hw_state.pll0;
1469 I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp);
1472 temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1473 temp &= ~PORT_PLL_N_MASK;
1474 temp |= pll->state.hw_state.pll1;
1475 I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp);
1477 /* Write M2 fraction */
1478 temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1479 temp &= ~PORT_PLL_M2_FRAC_MASK;
1480 temp |= pll->state.hw_state.pll2;
1481 I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp);
1483 /* Write M2 fraction enable */
1484 temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1485 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
1486 temp |= pll->state.hw_state.pll3;
1487 I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp);
1490 temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1491 temp &= ~PORT_PLL_PROP_COEFF_MASK;
1492 temp &= ~PORT_PLL_INT_COEFF_MASK;
1493 temp &= ~PORT_PLL_GAIN_CTL_MASK;
1494 temp |= pll->state.hw_state.pll6;
1495 I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp);
1497 /* Write calibration val */
1498 temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1499 temp &= ~PORT_PLL_TARGET_CNT_MASK;
1500 temp |= pll->state.hw_state.pll8;
1501 I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp);
1503 temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1504 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
1505 temp |= pll->state.hw_state.pll9;
1506 I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp);
1508 temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1509 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1510 temp &= ~PORT_PLL_DCO_AMP_MASK;
1511 temp |= pll->state.hw_state.pll10;
1512 I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp);
1514 /* Recalibrate with new settings */
1515 temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1516 temp |= PORT_PLL_RECALIBRATE;
1517 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1518 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1519 temp |= pll->state.hw_state.ebb4;
1520 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1523 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1524 temp |= PORT_PLL_ENABLE;
1525 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1526 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1528 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1530 DRM_ERROR("PLL %d not locked\n", port);
1532 if (IS_GEMINILAKE(dev_priv)) {
1533 temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));
1534 temp |= DCC_DELAY_RANGE_2;
1535 I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp);
1539 * While we write to the group register to program all lanes at once we
1540 * can read only lane registers and we pick lanes 0/1 for that.
1542 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1543 temp &= ~LANE_STAGGER_MASK;
1544 temp &= ~LANESTAGGER_STRAP_OVRD;
1545 temp |= pll->state.hw_state.pcsdw12;
1546 I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
1549 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
1550 struct intel_shared_dpll *pll)
1552 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1555 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1556 temp &= ~PORT_PLL_ENABLE;
1557 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1558 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1560 if (IS_GEMINILAKE(dev_priv)) {
1561 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1562 temp &= ~PORT_PLL_POWER_ENABLE;
1563 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1565 if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1566 PORT_PLL_POWER_STATE), 200))
1567 DRM_ERROR("Power state not reset for PLL:%d\n", port);
1571 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1572 struct intel_shared_dpll *pll,
1573 struct intel_dpll_hw_state *hw_state)
1575 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1579 enum dpio_channel ch;
1581 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1583 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1588 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
1589 if (!(val & PORT_PLL_ENABLE))
1592 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1593 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
1595 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1596 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
1598 hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1599 hw_state->pll0 &= PORT_PLL_M2_MASK;
1601 hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1602 hw_state->pll1 &= PORT_PLL_N_MASK;
1604 hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1605 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1607 hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1608 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1610 hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1611 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
1612 PORT_PLL_INT_COEFF_MASK |
1613 PORT_PLL_GAIN_CTL_MASK;
1615 hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1616 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
1618 hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1619 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
1621 hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1622 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
1623 PORT_PLL_DCO_AMP_MASK;
1626 * While we write to the group register to program all lanes at once we
1627 * can read only lane registers. We configure all lanes the same way, so
1628 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1630 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1631 if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
1632 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1634 I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));
1635 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
1640 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1645 /* bxt clock parameters */
1646 struct bxt_clk_div {
1658 /* pre-calculated values for DP linkrates */
1659 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1660 {162000, 4, 2, 32, 1677722, 1, 1},
1661 {270000, 4, 1, 27, 0, 0, 1},
1662 {540000, 2, 1, 27, 0, 0, 1},
1663 {216000, 3, 2, 32, 1677722, 1, 1},
1664 {243000, 4, 1, 24, 1258291, 1, 1},
1665 {324000, 4, 1, 32, 1677722, 1, 1},
1666 {432000, 3, 1, 32, 1677722, 1, 1}
1670 bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
1671 struct intel_crtc_state *crtc_state, int clock,
1672 struct bxt_clk_div *clk_div)
1674 struct dpll best_clock;
1676 /* Calculate HDMI div */
1678 * FIXME: tie the following calculation into
1679 * i9xx_crtc_compute_clock
1681 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1682 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1683 clock, pipe_name(intel_crtc->pipe));
1687 clk_div->p1 = best_clock.p1;
1688 clk_div->p2 = best_clock.p2;
1689 WARN_ON(best_clock.m1 != 2);
1690 clk_div->n = best_clock.n;
1691 clk_div->m2_int = best_clock.m2 >> 22;
1692 clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
1693 clk_div->m2_frac_en = clk_div->m2_frac != 0;
1695 clk_div->vco = best_clock.vco;
1700 static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
1704 *clk_div = bxt_dp_clk_val[0];
1705 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1706 if (bxt_dp_clk_val[i].clock == clock) {
1707 *clk_div = bxt_dp_clk_val[i];
1712 clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
1715 static bool bxt_ddi_set_dpll_hw_state(int clock,
1716 struct bxt_clk_div *clk_div,
1717 struct intel_dpll_hw_state *dpll_hw_state)
1719 int vco = clk_div->vco;
1720 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1721 uint32_t lanestagger;
1723 if (vco >= 6200000 && vco <= 6700000) {
1728 } else if ((vco > 5400000 && vco < 6200000) ||
1729 (vco >= 4800000 && vco < 5400000)) {
1734 } else if (vco == 5400000) {
1740 DRM_ERROR("Invalid VCO\n");
1746 else if (clock > 135000)
1748 else if (clock > 67000)
1750 else if (clock > 33000)
1755 dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
1756 dpll_hw_state->pll0 = clk_div->m2_int;
1757 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
1758 dpll_hw_state->pll2 = clk_div->m2_frac;
1760 if (clk_div->m2_frac_en)
1761 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
1763 dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
1764 dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
1766 dpll_hw_state->pll8 = targ_cnt;
1768 dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1770 dpll_hw_state->pll10 =
1771 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1772 | PORT_PLL_DCO_AMP_OVR_EN_H;
1774 dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1776 dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
1782 bxt_ddi_dp_set_dpll_hw_state(int clock,
1783 struct intel_dpll_hw_state *dpll_hw_state)
1785 struct bxt_clk_div clk_div = {0};
1787 bxt_ddi_dp_pll_dividers(clock, &clk_div);
1789 return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
1793 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc *intel_crtc,
1794 struct intel_crtc_state *crtc_state, int clock,
1795 struct intel_dpll_hw_state *dpll_hw_state)
1797 struct bxt_clk_div clk_div = { };
1799 bxt_ddi_hdmi_pll_dividers(intel_crtc, crtc_state, clock, &clk_div);
1801 return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
1804 static struct intel_shared_dpll *
1805 bxt_get_dpll(struct intel_crtc *crtc,
1806 struct intel_crtc_state *crtc_state,
1807 struct intel_encoder *encoder)
1809 struct intel_dpll_hw_state dpll_hw_state = { };
1810 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1811 struct intel_digital_port *intel_dig_port;
1812 struct intel_shared_dpll *pll;
1813 int i, clock = crtc_state->port_clock;
1815 if (encoder->type == INTEL_OUTPUT_HDMI &&
1816 !bxt_ddi_hdmi_set_dpll_hw_state(crtc, crtc_state, clock,
1820 if ((encoder->type == INTEL_OUTPUT_DP ||
1821 encoder->type == INTEL_OUTPUT_EDP ||
1822 encoder->type == INTEL_OUTPUT_DP_MST) &&
1823 !bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
1826 memset(&crtc_state->dpll_hw_state, 0,
1827 sizeof(crtc_state->dpll_hw_state));
1829 crtc_state->dpll_hw_state = dpll_hw_state;
1831 if (encoder->type == INTEL_OUTPUT_DP_MST) {
1832 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
1834 intel_dig_port = intel_mst->primary;
1836 intel_dig_port = enc_to_dig_port(&encoder->base);
1838 /* 1:1 mapping between ports and PLLs */
1839 i = (enum intel_dpll_id) intel_dig_port->port;
1840 pll = intel_get_shared_dpll_by_id(dev_priv, i);
1842 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1843 crtc->base.base.id, crtc->base.name, pll->name);
1845 intel_reference_shared_dpll(pll, crtc_state);
1850 static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
1851 struct intel_dpll_hw_state *hw_state)
1853 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
1854 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1855 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
1869 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
1870 .enable = bxt_ddi_pll_enable,
1871 .disable = bxt_ddi_pll_disable,
1872 .get_hw_state = bxt_ddi_pll_get_hw_state,
1875 static void intel_ddi_pll_init(struct drm_device *dev)
1877 struct drm_i915_private *dev_priv = to_i915(dev);
1879 if (INTEL_GEN(dev_priv) < 9) {
1880 uint32_t val = I915_READ(LCPLL_CTL);
1883 * The LCPLL register should be turned on by the BIOS. For now
1884 * let's just check its state and print errors in case
1885 * something is wrong. Don't even try to turn it on.
1888 if (val & LCPLL_CD_SOURCE_FCLK)
1889 DRM_ERROR("CDCLK source is not LCPLL\n");
1891 if (val & LCPLL_PLL_DISABLE)
1892 DRM_ERROR("LCPLL is disabled\n");
1899 const struct intel_shared_dpll_funcs *funcs;
1903 struct intel_dpll_mgr {
1904 const struct dpll_info *dpll_info;
1906 struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,
1907 struct intel_crtc_state *crtc_state,
1908 struct intel_encoder *encoder);
1910 void (*dump_hw_state)(struct drm_i915_private *dev_priv,
1911 struct intel_dpll_hw_state *hw_state);
1914 static const struct dpll_info pch_plls[] = {
1915 { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 },
1916 { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 },
1917 { NULL, -1, NULL, 0 },
1920 static const struct intel_dpll_mgr pch_pll_mgr = {
1921 .dpll_info = pch_plls,
1922 .get_dpll = ibx_get_dpll,
1923 .dump_hw_state = ibx_dump_hw_state,
1926 static const struct dpll_info hsw_plls[] = {
1927 { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs, 0 },
1928 { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs, 0 },
1929 { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs, 0 },
1930 { "LCPLL 810", DPLL_ID_LCPLL_810, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1931 { "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1932 { "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1933 { NULL, -1, NULL, },
1936 static const struct intel_dpll_mgr hsw_pll_mgr = {
1937 .dpll_info = hsw_plls,
1938 .get_dpll = hsw_get_dpll,
1939 .dump_hw_state = hsw_dump_hw_state,
1942 static const struct dpll_info skl_plls[] = {
1943 { "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON },
1944 { "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs, 0 },
1945 { "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs, 0 },
1946 { "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs, 0 },
1947 { NULL, -1, NULL, },
1950 static const struct intel_dpll_mgr skl_pll_mgr = {
1951 .dpll_info = skl_plls,
1952 .get_dpll = skl_get_dpll,
1953 .dump_hw_state = skl_dump_hw_state,
1956 static const struct dpll_info bxt_plls[] = {
1957 { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
1958 { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
1959 { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
1960 { NULL, -1, NULL, },
1963 static const struct intel_dpll_mgr bxt_pll_mgr = {
1964 .dpll_info = bxt_plls,
1965 .get_dpll = bxt_get_dpll,
1966 .dump_hw_state = bxt_dump_hw_state,
1969 static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1970 struct intel_shared_dpll *pll)
1974 /* 1. Enable DPLL power in DPLL_ENABLE. */
1975 val = I915_READ(CNL_DPLL_ENABLE(pll->id));
1976 val |= PLL_POWER_ENABLE;
1977 I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
1979 /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
1980 if (intel_wait_for_register(dev_priv,
1981 CNL_DPLL_ENABLE(pll->id),
1985 DRM_ERROR("PLL %d Power not enabled\n", pll->id);
1988 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
1989 * select DP mode, and set DP link rate.
1991 val = pll->state.hw_state.cfgcr0;
1992 I915_WRITE(CNL_DPLL_CFGCR0(pll->id), val);
1994 /* 4. Reab back to ensure writes completed */
1995 POSTING_READ(CNL_DPLL_CFGCR0(pll->id));
1997 /* 3. Configure DPLL_CFGCR0 */
1998 /* Avoid touch CFGCR1 if HDMI mode is not enabled */
1999 if (pll->state.hw_state.cfgcr0 & DPLL_CTRL1_HDMI_MODE(pll->id)) {
2000 val = pll->state.hw_state.cfgcr1;
2001 I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
2002 /* 4. Reab back to ensure writes completed */
2003 POSTING_READ(CNL_DPLL_CFGCR1(pll->id));
2007 * 5. If the frequency will result in a change to the voltage
2008 * requirement, follow the Display Voltage Frequency Switching
2009 * Sequence Before Frequency Change
2011 * FIXME: (DVFS) is used to adjust the display voltage to match the
2012 * display clock frequencies
2015 /* 6. Enable DPLL in DPLL_ENABLE. */
2016 val = I915_READ(CNL_DPLL_ENABLE(pll->id));
2018 I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
2020 /* 7. Wait for PLL lock status in DPLL_ENABLE. */
2021 if (intel_wait_for_register(dev_priv,
2022 CNL_DPLL_ENABLE(pll->id),
2026 DRM_ERROR("PLL %d not locked\n", pll->id);
2029 * 8. If the frequency will result in a change to the voltage
2030 * requirement, follow the Display Voltage Frequency Switching
2031 * Sequence After Frequency Change
2033 * FIXME: (DVFS) is used to adjust the display voltage to match the
2034 * display clock frequencies
2038 * 9. turn on the clock for the DDI and map the DPLL to the DDI
2039 * Done at intel_ddi_clk_select
2043 static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2044 struct intel_shared_dpll *pll)
2049 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
2050 * Done at intel_ddi_post_disable
2054 * 2. If the frequency will result in a change to the voltage
2055 * requirement, follow the Display Voltage Frequency Switching
2056 * Sequence Before Frequency Change
2058 * FIXME: (DVFS) is used to adjust the display voltage to match the
2059 * display clock frequencies
2062 /* 3. Disable DPLL through DPLL_ENABLE. */
2063 val = I915_READ(CNL_DPLL_ENABLE(pll->id));
2065 I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
2067 /* 4. Wait for PLL not locked status in DPLL_ENABLE. */
2068 if (intel_wait_for_register(dev_priv,
2069 CNL_DPLL_ENABLE(pll->id),
2073 DRM_ERROR("PLL %d locked\n", pll->id);
2076 * 5. If the frequency will result in a change to the voltage
2077 * requirement, follow the Display Voltage Frequency Switching
2078 * Sequence After Frequency Change
2080 * FIXME: (DVFS) is used to adjust the display voltage to match the
2081 * display clock frequencies
2084 /* 6. Disable DPLL power in DPLL_ENABLE. */
2085 val = I915_READ(CNL_DPLL_ENABLE(pll->id));
2086 val &= ~PLL_POWER_ENABLE;
2087 I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
2089 /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
2090 if (intel_wait_for_register(dev_priv,
2091 CNL_DPLL_ENABLE(pll->id),
2095 DRM_ERROR("PLL %d Power not disabled\n", pll->id);
2098 static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2099 struct intel_shared_dpll *pll,
2100 struct intel_dpll_hw_state *hw_state)
2105 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
2110 val = I915_READ(CNL_DPLL_ENABLE(pll->id));
2111 if (!(val & PLL_ENABLE))
2114 val = I915_READ(CNL_DPLL_CFGCR0(pll->id));
2115 hw_state->cfgcr0 = val;
2117 /* avoid reading back stale values if HDMI mode is not enabled */
2118 if (val & DPLL_CFGCR0_HDMI_MODE) {
2119 hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll->id));
2124 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2129 static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
2130 struct intel_crtc_state *crtc_state,
2133 uint32_t cfgcr0, cfgcr1;
2134 struct skl_wrpll_params wrpll_params = { 0, };
2136 cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
2138 /* FIXME: Proper wrpll calculation done in a following patch */
2141 cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
2142 wrpll_params.dco_integer;
2144 cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
2145 DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
2146 DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
2147 DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
2148 wrpll_params.central_freq |
2149 DPLL_CFGCR1_CENTRAL_FREQ;
2151 memset(&crtc_state->dpll_hw_state, 0,
2152 sizeof(crtc_state->dpll_hw_state));
2154 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
2155 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
2159 bool cnl_ddi_dp_set_dpll_hw_state(int clock,
2160 struct intel_dpll_hw_state *dpll_hw_state)
2164 cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
2166 switch (clock / 2) {
2168 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
2171 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
2174 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
2178 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
2181 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
2184 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
2187 /* Some SKUs may require elevated I/O voltage to support this */
2188 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
2191 /* Some SKUs may require elevated I/O voltage to support this */
2192 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
2196 dpll_hw_state->cfgcr0 = cfgcr0;
2200 static struct intel_shared_dpll *
2201 cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
2202 struct intel_encoder *encoder)
2204 struct intel_shared_dpll *pll;
2205 int clock = crtc_state->port_clock;
2207 struct intel_dpll_hw_state dpll_hw_state;
2209 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
2211 if (encoder->type == INTEL_OUTPUT_HDMI) {
2212 bret = cnl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
2214 DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
2217 } else if (encoder->type == INTEL_OUTPUT_DP ||
2218 encoder->type == INTEL_OUTPUT_DP_MST ||
2219 encoder->type == INTEL_OUTPUT_EDP) {
2220 bret = cnl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
2222 DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
2225 crtc_state->dpll_hw_state = dpll_hw_state;
2227 DRM_DEBUG_KMS("Skip DPLL setup for encoder %d\n",
2232 pll = intel_find_shared_dpll(crtc, crtc_state,
2236 DRM_DEBUG_KMS("No PLL selected\n");
2240 intel_reference_shared_dpll(pll, crtc_state);
2245 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
2246 .enable = cnl_ddi_pll_enable,
2247 .disable = cnl_ddi_pll_disable,
2248 .get_hw_state = cnl_ddi_pll_get_hw_state,
2251 static const struct dpll_info cnl_plls[] = {
2252 { "DPLL 0", DPLL_ID_SKL_DPLL0, &cnl_ddi_pll_funcs, 0 },
2253 { "DPLL 1", DPLL_ID_SKL_DPLL1, &cnl_ddi_pll_funcs, 0 },
2254 { "DPLL 2", DPLL_ID_SKL_DPLL2, &cnl_ddi_pll_funcs, 0 },
2255 { NULL, -1, NULL, },
2258 static const struct intel_dpll_mgr cnl_pll_mgr = {
2259 .dpll_info = cnl_plls,
2260 .get_dpll = cnl_get_dpll,
2261 .dump_hw_state = skl_dump_hw_state,
2265 * intel_shared_dpll_init - Initialize shared DPLLs
2268 * Initialize shared DPLLs for @dev.
2270 void intel_shared_dpll_init(struct drm_device *dev)
2272 struct drm_i915_private *dev_priv = to_i915(dev);
2273 const struct intel_dpll_mgr *dpll_mgr = NULL;
2274 const struct dpll_info *dpll_info;
2277 if (IS_CANNONLAKE(dev_priv))
2278 dpll_mgr = &cnl_pll_mgr;
2279 else if (IS_GEN9_BC(dev_priv))
2280 dpll_mgr = &skl_pll_mgr;
2281 else if (IS_GEN9_LP(dev_priv))
2282 dpll_mgr = &bxt_pll_mgr;
2283 else if (HAS_DDI(dev_priv))
2284 dpll_mgr = &hsw_pll_mgr;
2285 else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
2286 dpll_mgr = &pch_pll_mgr;
2289 dev_priv->num_shared_dpll = 0;
2293 dpll_info = dpll_mgr->dpll_info;
2295 for (i = 0; dpll_info[i].id >= 0; i++) {
2296 WARN_ON(i != dpll_info[i].id);
2298 dev_priv->shared_dplls[i].id = dpll_info[i].id;
2299 dev_priv->shared_dplls[i].name = dpll_info[i].name;
2300 dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs;
2301 dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
2304 dev_priv->dpll_mgr = dpll_mgr;
2305 dev_priv->num_shared_dpll = i;
2306 mutex_init(&dev_priv->dpll_lock);
2308 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
2310 /* FIXME: Move this to a more suitable place */
2311 if (HAS_DDI(dev_priv))
2312 intel_ddi_pll_init(dev);
2316 * intel_get_shared_dpll - get a shared DPLL for CRTC and encoder combination
2318 * @crtc_state: atomic state for @crtc
2321 * Find an appropriate DPLL for the given CRTC and encoder combination. A
2322 * reference from the @crtc to the returned pll is registered in the atomic
2323 * state. That configuration is made effective by calling
2324 * intel_shared_dpll_swap_state(). The reference should be released by calling
2325 * intel_release_shared_dpll().
2328 * A shared DPLL to be used by @crtc and @encoder with the given @crtc_state.
2330 struct intel_shared_dpll *
2331 intel_get_shared_dpll(struct intel_crtc *crtc,
2332 struct intel_crtc_state *crtc_state,
2333 struct intel_encoder *encoder)
2335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2336 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
2338 if (WARN_ON(!dpll_mgr))
2341 return dpll_mgr->get_dpll(crtc, crtc_state, encoder);
2345 * intel_release_shared_dpll - end use of DPLL by CRTC in atomic state
2346 * @dpll: dpll in use by @crtc
2348 * @state: atomic state
2350 * This function releases the reference from @crtc to @dpll from the
2351 * atomic @state. The new configuration is made effective by calling
2352 * intel_shared_dpll_swap_state().
2354 void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
2355 struct intel_crtc *crtc,
2356 struct drm_atomic_state *state)
2358 struct intel_shared_dpll_state *shared_dpll_state;
2360 shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
2361 shared_dpll_state[dpll->id].crtc_mask &= ~(1 << crtc->pipe);
2365 * intel_shared_dpll_dump_hw_state - write hw_state to dmesg
2366 * @dev_priv: i915 drm device
2367 * @hw_state: hw state to be written to the log
2369 * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS.
2371 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
2372 struct intel_dpll_hw_state *hw_state)
2374 if (dev_priv->dpll_mgr) {
2375 dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state);
2377 /* fallback for platforms that don't use the shared dpll
2380 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
2381 "fp0: 0x%x, fp1: 0x%x\n",