drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  *
  51  * TODO: When modesetting has fully transitioned to atomic, the below
  52  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  53  * added.
  54  */
  55 #define _wait_for(COND, US, W) ({ \
  56         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  57         int ret__;                                                      \
  58         for (;;) {                                                      \
  59                 bool expired__ = time_after(jiffies, timeout__);        \
  60                 if (COND) {                                             \
  61                         ret__ = 0;                                      \
  62                         break;                                          \
  63                 }                                                       \
  64                 if (expired__) {                                        \
  65                         ret__ = -ETIMEDOUT;                             \
  66                         break;                                          \
  67                 }                                                       \
  68                 if ((W) && drm_can_sleep()) {                           \
  69                         usleep_range((W), (W)*2);                       \
  70                 } else {                                                \
  71                         cpu_relax();                                    \
  72                 }                                                       \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  78
  79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  82 #else
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  84 #endif
  85
  86 #define _wait_for_atomic(COND, US, ATOMIC) \
  87 ({ \
  88         int cpu, ret, timeout = (US) * 1000; \
  89         u64 base; \
  90         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  91         BUILD_BUG_ON((US) > 50000); \
  92         if (!(ATOMIC)) { \
  93                 preempt_disable(); \
  94                 cpu = smp_processor_id(); \
  95         } \
  96         base = local_clock(); \
  97         for (;;) { \
  98                 u64 now = local_clock(); \
  99                 if (!(ATOMIC)) \
 100                         preempt_enable(); \
 101                 if (COND) { \
 102                         ret = 0; \
 103                         break; \
 104                 } \
 105                 if (now - base >= timeout) { \
 106                         ret = -ETIMEDOUT; \
 107                         break; \
 108                 } \
 109                 cpu_relax(); \
 110                 if (!(ATOMIC)) { \
 111                         preempt_disable(); \
 112                         if (unlikely(cpu != smp_processor_id())) { \
 113                                 timeout -= now - base; \
 114                                 cpu = smp_processor_id(); \
 115                                 base = local_clock(); \
 116                         } \
 117                 } \
 118         } \
 119         ret; \
 120 })
 121
 122 #define wait_for_us(COND, US) \
 123 ({ \
 124         int ret__; \
 125         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 126         if ((US) > 10) \
 127                 ret__ = _wait_for((COND), (US), 10); \
 128         else \
 129                 ret__ = _wait_for_atomic((COND), (US), 0); \
 130         ret__; \
 131 })
 132
 133 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 134 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 135
 136 #define KHz(x) (1000 * (x))
 137 #define MHz(x) KHz(1000 * (x))
 138
 139 /*
 140  * Display related stuff
 141  */
 142
 143 /* store information about an Ixxx DVO */
 144 /* The i830->i865 use multiple DVOs with multiple i2cs */
 145 /* the i915, i945 have a single sDVO i2c bus - which is different */
 146 #define MAX_OUTPUTS 6
 147 /* maximum connectors per crtcs in the mode set */
 148
 149 /* Maximum cursor sizes */
 150 #define GEN2_CURSOR_WIDTH 64
 151 #define GEN2_CURSOR_HEIGHT 64
 152 #define MAX_CURSOR_WIDTH 256
 153 #define MAX_CURSOR_HEIGHT 256
 154
 155 #define INTEL_I2C_BUS_DVO 1
 156 #define INTEL_I2C_BUS_SDVO 2
 157
 158 /* these are outputs from the chip - integrated only
 159    external chips are via DVO or SDVO output */
 160 enum intel_output_type {
 161         INTEL_OUTPUT_UNUSED = 0,
 162         INTEL_OUTPUT_ANALOG = 1,
 163         INTEL_OUTPUT_DVO = 2,
 164         INTEL_OUTPUT_SDVO = 3,
 165         INTEL_OUTPUT_LVDS = 4,
 166         INTEL_OUTPUT_TVOUT = 5,
 167         INTEL_OUTPUT_HDMI = 6,
 168         INTEL_OUTPUT_DP = 7,
 169         INTEL_OUTPUT_EDP = 8,
 170         INTEL_OUTPUT_DSI = 9,
 171         INTEL_OUTPUT_UNKNOWN = 10,
 172         INTEL_OUTPUT_DP_MST = 11,
 173 };
 174
 175 #define INTEL_DVO_CHIP_NONE 0
 176 #define INTEL_DVO_CHIP_LVDS 1
 177 #define INTEL_DVO_CHIP_TMDS 2
 178 #define INTEL_DVO_CHIP_TVOUT 4
 179
 180 #define INTEL_DSI_VIDEO_MODE    0
 181 #define INTEL_DSI_COMMAND_MODE  1
 182
 183 struct intel_framebuffer {
 184         struct drm_framebuffer base;
 185         struct drm_i915_gem_object *obj;
 186         struct intel_rotation_info rot_info;
 187
 188         /* for each plane in the normal GTT view */
 189         struct {
 190                 unsigned int x, y;
 191         } normal[2];
 192         /* for each plane in the rotated GTT view */
 193         struct {
 194                 unsigned int x, y;
 195                 unsigned int pitch; /* pixels */
 196         } rotated[2];
 197 };
 198
 199 struct intel_fbdev {
 200         struct drm_fb_helper helper;
 201         struct intel_framebuffer *fb;
 202         struct i915_vma *vma;
 203         async_cookie_t cookie;
 204         int preferred_bpp;
 205 };
 206
 207 struct intel_encoder {
 208         struct drm_encoder base;
 209
 210         enum intel_output_type type;
 211         enum port port;
 212         unsigned int cloneable;
 213         void (*hot_plug)(struct intel_encoder *);
 214         bool (*compute_config)(struct intel_encoder *,
 215                                struct intel_crtc_state *,
 216                                struct drm_connector_state *);
 217         void (*pre_pll_enable)(struct intel_encoder *,
 218                                struct intel_crtc_state *,
 219                                struct drm_connector_state *);
 220         void (*pre_enable)(struct intel_encoder *,
 221                            struct intel_crtc_state *,
 222                            struct drm_connector_state *);
 223         void (*enable)(struct intel_encoder *,
 224                        struct intel_crtc_state *,
 225                        struct drm_connector_state *);
 226         void (*disable)(struct intel_encoder *,
 227                         struct intel_crtc_state *,
 228                         struct drm_connector_state *);
 229         void (*post_disable)(struct intel_encoder *,
 230                              struct intel_crtc_state *,
 231                              struct drm_connector_state *);
 232         void (*post_pll_disable)(struct intel_encoder *,
 233                                  struct intel_crtc_state *,
 234                                  struct drm_connector_state *);
 235         /* Read out the current hw state of this connector, returning true if
 236          * the encoder is active. If the encoder is enabled it also set the pipe
 237          * it is connected to in the pipe parameter. */
 238         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 239         /* Reconstructs the equivalent mode flags for the current hardware
 240          * state. This must be called _after_ display->get_pipe_config has
 241          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 242          * be set correctly before calling this function. */
 243         void (*get_config)(struct intel_encoder *,
 244                            struct intel_crtc_state *pipe_config);
 245         /* Returns a mask of power domains that need to be referenced as part
 246          * of the hardware state readout code. */
 247         u64 (*get_power_domains)(struct intel_encoder *encoder);
 248         /*
 249          * Called during system suspend after all pending requests for the
 250          * encoder are flushed (for example for DP AUX transactions) and
 251          * device interrupts are disabled.
 252          */
 253         void (*suspend)(struct intel_encoder *);
 254         int crtc_mask;
 255         enum hpd_pin hpd_pin;
 256         enum intel_display_power_domain power_domain;
 257         /* for communication with audio component; protected by av_mutex */
 258         const struct drm_connector *audio_connector;
 259 };
 260
 261 struct intel_panel {
 262         struct drm_display_mode *fixed_mode;
 263         struct drm_display_mode *downclock_mode;
 264         int fitting_mode;
 265
 266         /* backlight */
 267         struct {
 268                 bool present;
 269                 u32 level;
 270                 u32 min;
 271                 u32 max;
 272                 bool enabled;
 273                 bool combination_mode;  /* gen 2/4 only */
 274                 bool active_low_pwm;
 275                 bool alternate_pwm_increment;   /* lpt+ */
 276
 277                 /* PWM chip */
 278                 bool util_pin_active_low;       /* bxt+ */
 279                 u8 controller;          /* bxt+ only */
 280                 struct pwm_device *pwm;
 281
 282                 struct backlight_device *device;
 283
 284                 /* Connector and platform specific backlight functions */
 285                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 286                 uint32_t (*get)(struct intel_connector *connector);
 287                 void (*set)(struct intel_connector *connector, uint32_t level);
 288                 void (*disable)(struct intel_connector *connector);
 289                 void (*enable)(struct intel_connector *connector);
 290                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 291                                       uint32_t hz);
 292                 void (*power)(struct intel_connector *, bool enable);
 293         } backlight;
 294 };
 295
 296 struct intel_connector {
 297         struct drm_connector base;
 298         /*
 299          * The fixed encoder this connector is connected to.
 300          */
 301         struct intel_encoder *encoder;
 302
 303         /* ACPI device id for ACPI and driver cooperation */
 304         u32 acpi_device_id;
 305
 306         /* Reads out the current hw, returning true if the connector is enabled
 307          * and active (i.e. dpms ON state). */
 308         bool (*get_hw_state)(struct intel_connector *);
 309
 310         /* Panel info for eDP and LVDS */
 311         struct intel_panel panel;
 312
 313         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 314         struct edid *edid;
 315         struct edid *detect_edid;
 316
 317         /* since POLL and HPD connectors may use the same HPD line keep the native
 318            state of connector->polled in case hotplug storm detection changes it */
 319         u8 polled;
 320
 321         void *port; /* store this opaque as its illegal to dereference it */
 322
 323         struct intel_dp *mst_port;
 324
 325         /* Work struct to schedule a uevent on link train failure */
 326         struct work_struct modeset_retry_work;
 327 };
 328
 329 struct dpll {
 330         /* given values */
 331         int n;
 332         int m1, m2;
 333         int p1, p2;
 334         /* derived values */
 335         int     dot;
 336         int     vco;
 337         int     m;
 338         int     p;
 339 };
 340
 341 struct intel_atomic_state {
 342         struct drm_atomic_state base;
 343
 344         struct {
 345                 /*
 346                  * Logical state of cdclk (used for all scaling, watermark,
 347                  * etc. calculations and checks). This is computed as if all
 348                  * enabled crtcs were active.
 349                  */
 350                 struct intel_cdclk_state logical;
 351
 352                 /*
 353                  * Actual state of cdclk, can be different from the logical
 354                  * state only when all crtc's are DPMS off.
 355                  */
 356                 struct intel_cdclk_state actual;
 357         } cdclk;
 358
 359         bool dpll_set, modeset;
 360
 361         /*
 362          * Does this transaction change the pipes that are active?  This mask
 363          * tracks which CRTC's have changed their active state at the end of
 364          * the transaction (not counting the temporary disable during modesets).
 365          * This mask should only be non-zero when intel_state->modeset is true,
 366          * but the converse is not necessarily true; simply changing a mode may
 367          * not flip the final active status of any CRTC's
 368          */
 369         unsigned int active_pipe_changes;
 370
 371         unsigned int active_crtcs;
 372         unsigned int min_pixclk[I915_MAX_PIPES];
 373
 374         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 375
 376         /*
 377          * Current watermarks can't be trusted during hardware readout, so
 378          * don't bother calculating intermediate watermarks.
 379          */
 380         bool skip_intermediate_wm;
 381
 382         /* Gen9+ only */
 383         struct skl_wm_values wm_results;
 384
 385         struct i915_sw_fence commit_ready;
 386
 387         struct llist_node freed;
 388 };
 389
 390 struct intel_plane_state {
 391         struct drm_plane_state base;
 392         struct drm_rect clip;
 393         struct i915_vma *vma;
 394
 395         struct {
 396                 u32 offset;
 397                 int x, y;
 398         } main;
 399         struct {
 400                 u32 offset;
 401                 int x, y;
 402         } aux;
 403
 404         /* plane control register */
 405         u32 ctl;
 406
 407         /*
 408          * scaler_id
 409          *    = -1 : not using a scaler
 410          *    >=  0 : using a scalers
 411          *
 412          * plane requiring a scaler:
 413          *   - During check_plane, its bit is set in
 414          *     crtc_state->scaler_state.scaler_users by calling helper function
 415          *     update_scaler_plane.
 416          *   - scaler_id indicates the scaler it got assigned.
 417          *
 418          * plane doesn't require a scaler:
 419          *   - this can happen when scaling is no more required or plane simply
 420          *     got disabled.
 421          *   - During check_plane, corresponding bit is reset in
 422          *     crtc_state->scaler_state.scaler_users by calling helper function
 423          *     update_scaler_plane.
 424          */
 425         int scaler_id;
 426
 427         struct drm_intel_sprite_colorkey ckey;
 428 };
 429
 430 struct intel_initial_plane_config {
 431         struct intel_framebuffer *fb;
 432         unsigned int tiling;
 433         int size;
 434         u32 base;
 435 };
 436
 437 #define SKL_MIN_SRC_W 8
 438 #define SKL_MAX_SRC_W 4096
 439 #define SKL_MIN_SRC_H 8
 440 #define SKL_MAX_SRC_H 4096
 441 #define SKL_MIN_DST_W 8
 442 #define SKL_MAX_DST_W 4096
 443 #define SKL_MIN_DST_H 8
 444 #define SKL_MAX_DST_H 4096
 445
 446 struct intel_scaler {
 447         int in_use;
 448         uint32_t mode;
 449 };
 450
 451 struct intel_crtc_scaler_state {
 452 #define SKL_NUM_SCALERS 2
 453         struct intel_scaler scalers[SKL_NUM_SCALERS];
 454
 455         /*
 456          * scaler_users: keeps track of users requesting scalers on this crtc.
 457          *
 458          *     If a bit is set, a user is using a scaler.
 459          *     Here user can be a plane or crtc as defined below:
 460          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 461          *       bit 31    - crtc
 462          *
 463          * Instead of creating a new index to cover planes and crtc, using
 464          * existing drm_plane_index for planes which is well less than 31
 465          * planes and bit 31 for crtc. This should be fine to cover all
 466          * our platforms.
 467          *
 468          * intel_atomic_setup_scalers will setup available scalers to users
 469          * requesting scalers. It will gracefully fail if request exceeds
 470          * avilability.
 471          */
 472 #define SKL_CRTC_INDEX 31
 473         unsigned scaler_users;
 474
 475         /* scaler used by crtc for panel fitting purpose */
 476         int scaler_id;
 477 };
 478
 479 /* drm_mode->private_flags */
 480 #define I915_MODE_FLAG_INHERITED 1
 481
 482 struct intel_pipe_wm {
 483         struct intel_wm_level wm[5];
 484         struct intel_wm_level raw_wm[5];
 485         uint32_t linetime;
 486         bool fbc_wm_enabled;
 487         bool pipe_enabled;
 488         bool sprites_enabled;
 489         bool sprites_scaled;
 490 };
 491
 492 struct skl_plane_wm {
 493         struct skl_wm_level wm[8];
 494         struct skl_wm_level trans_wm;
 495 };
 496
 497 struct skl_pipe_wm {
 498         struct skl_plane_wm planes[I915_MAX_PLANES];
 499         uint32_t linetime;
 500 };
 501
 502 enum vlv_wm_level {
 503         VLV_WM_LEVEL_PM2,
 504         VLV_WM_LEVEL_PM5,
 505         VLV_WM_LEVEL_DDR_DVFS,
 506         NUM_VLV_WM_LEVELS,
 507 };
 508
 509 struct vlv_wm_state {
 510         struct vlv_pipe_wm wm[NUM_VLV_WM_LEVELS];
 511         struct vlv_sr_wm sr[NUM_VLV_WM_LEVELS];
 512         uint8_t num_levels;
 513         bool cxsr;
 514 };
 515
 516 struct vlv_fifo_state {
 517         u16 plane[I915_MAX_PLANES];
 518 };
 519
 520 struct intel_crtc_wm_state {
 521         union {
 522                 struct {
 523                         /*
 524                          * Intermediate watermarks; these can be
 525                          * programmed immediately since they satisfy
 526                          * both the current configuration we're
 527                          * switching away from and the new
 528                          * configuration we're switching to.
 529                          */
 530                         struct intel_pipe_wm intermediate;
 531
 532                         /*
 533                          * Optimal watermarks, programmed post-vblank
 534                          * when this state is committed.
 535                          */
 536                         struct intel_pipe_wm optimal;
 537                 } ilk;
 538
 539                 struct {
 540                         /* gen9+ only needs 1-step wm programming */
 541                         struct skl_pipe_wm optimal;
 542                         struct skl_ddb_entry ddb;
 543                 } skl;
 544
 545                 struct {
 546                         /* "raw" watermarks (not inverted) */
 547                         struct vlv_pipe_wm raw[NUM_VLV_WM_LEVELS];
 548                         /* intermediate watermarks (inverted) */
 549                         struct vlv_wm_state intermediate;
 550                         /* optimal watermarks (inverted) */
 551                         struct vlv_wm_state optimal;
 552                         /* display FIFO split */
 553                         struct vlv_fifo_state fifo_state;
 554                 } vlv;
 555         };
 556
 557         /*
 558          * Platforms with two-step watermark programming will need to
 559          * update watermark programming post-vblank to switch from the
 560          * safe intermediate watermarks to the optimal final
 561          * watermarks.
 562          */
 563         bool need_postvbl_update;
 564 };
 565
 566 struct intel_crtc_state {
 567         struct drm_crtc_state base;
 568
 569         /**
 570          * quirks - bitfield with hw state readout quirks
 571          *
 572          * For various reasons the hw state readout code might not be able to
 573          * completely faithfully read out the current state. These cases are
 574          * tracked with quirk flags so that fastboot and state checker can act
 575          * accordingly.
 576          */
 577 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 578         unsigned long quirks;
 579
 580         unsigned fb_bits; /* framebuffers to flip */
 581         bool update_pipe; /* can a fast modeset be performed? */
 582         bool disable_cxsr;
 583         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 584         bool fb_changed; /* fb on any of the planes is changed */
 585         bool fifo_changed; /* FIFO split is changed */
 586
 587         /* Pipe source size (ie. panel fitter input size)
 588          * All planes will be positioned inside this space,
 589          * and get clipped at the edges. */
 590         int pipe_src_w, pipe_src_h;
 591
 592         /*
 593          * Pipe pixel rate, adjusted for
 594          * panel fitter/pipe scaler downscaling.
 595          */
 596         unsigned int pixel_rate;
 597
 598         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 599          * between pch encoders and cpu encoders. */
 600         bool has_pch_encoder;
 601
 602         /* Are we sending infoframes on the attached port */
 603         bool has_infoframe;
 604
 605         /* CPU Transcoder for the pipe. Currently this can only differ from the
 606          * pipe on Haswell and later (where we have a special eDP transcoder)
 607          * and Broxton (where we have special DSI transcoders). */
 608         enum transcoder cpu_transcoder;
 609
 610         /*
 611          * Use reduced/limited/broadcast rbg range, compressing from the full
 612          * range fed into the crtcs.
 613          */
 614         bool limited_color_range;
 615
 616         /* Bitmask of encoder types (enum intel_output_type)
 617          * driven by the pipe.
 618          */
 619         unsigned int output_types;
 620
 621         /* Whether we should send NULL infoframes. Required for audio. */
 622         bool has_hdmi_sink;
 623
 624         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 625          * has_dp_encoder is set. */
 626         bool has_audio;
 627
 628         /*
 629          * Enable dithering, used when the selected pipe bpp doesn't match the
 630          * plane bpp.
 631          */
 632         bool dither;
 633
 634         /*
 635          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 636          * compliance video pattern tests.
 637          * Disable dither only if it is a compliance test request for
 638          * 18bpp.
 639          */
 640         bool dither_force_disable;
 641
 642         /* Controls for the clock computation, to override various stages. */
 643         bool clock_set;
 644
 645         /* SDVO TV has a bunch of special case. To make multifunction encoders
 646          * work correctly, we need to track this at runtime.*/
 647         bool sdvo_tv_clock;
 648
 649         /*
 650          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 651          * required. This is set in the 2nd loop of calling encoder's
 652          * ->compute_config if the first pick doesn't work out.
 653          */
 654         bool bw_constrained;
 655
 656         /* Settings for the intel dpll used on pretty much everything but
 657          * haswell. */
 658         struct dpll dpll;
 659
 660         /* Selected dpll when shared or NULL. */
 661         struct intel_shared_dpll *shared_dpll;
 662
 663         /* Actual register state of the dpll, for shared dpll cross-checking. */
 664         struct intel_dpll_hw_state dpll_hw_state;
 665
 666         /* DSI PLL registers */
 667         struct {
 668                 u32 ctrl, div;
 669         } dsi_pll;
 670
 671         int pipe_bpp;
 672         struct intel_link_m_n dp_m_n;
 673
 674         /* m2_n2 for eDP downclock */
 675         struct intel_link_m_n dp_m2_n2;
 676         bool has_drrs;
 677
 678         /*
 679          * Frequence the dpll for the port should run at. Differs from the
 680          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 681          * already multiplied by pixel_multiplier.
 682          */
 683         int port_clock;
 684
 685         /* Used by SDVO (and if we ever fix it, HDMI). */
 686         unsigned pixel_multiplier;
 687
 688         uint8_t lane_count;
 689
 690         /*
 691          * Used by platforms having DP/HDMI PHY with programmable lane
 692          * latency optimization.
 693          */
 694         uint8_t lane_lat_optim_mask;
 695
 696         /* Panel fitter controls for gen2-gen4 + VLV */
 697         struct {
 698                 u32 control;
 699                 u32 pgm_ratios;
 700                 u32 lvds_border_bits;
 701         } gmch_pfit;
 702
 703         /* Panel fitter placement and size for Ironlake+ */
 704         struct {
 705                 u32 pos;
 706                 u32 size;
 707                 bool enabled;
 708                 bool force_thru;
 709         } pch_pfit;
 710
 711         /* FDI configuration, only valid if has_pch_encoder is set. */
 712         int fdi_lanes;
 713         struct intel_link_m_n fdi_m_n;
 714
 715         bool ips_enabled;
 716
 717         bool enable_fbc;
 718
 719         bool double_wide;
 720
 721         int pbn;
 722
 723         struct intel_crtc_scaler_state scaler_state;
 724
 725         /* w/a for waiting 2 vblanks during crtc enable */
 726         enum pipe hsw_workaround_pipe;
 727
 728         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 729         bool disable_lp_wm;
 730
 731         struct intel_crtc_wm_state wm;
 732
 733         /* Gamma mode programmed on the pipe */
 734         uint32_t gamma_mode;
 735
 736         /* bitmask of visible planes (enum plane_id) */
 737         u8 active_planes;
 738
 739         /* HDMI scrambling status */
 740         bool hdmi_scrambling;
 741
 742         /* HDMI High TMDS char rate ratio */
 743         bool hdmi_high_tmds_clock_ratio;
 744 };
 745
 746 struct intel_crtc {
 747         struct drm_crtc base;
 748         enum pipe pipe;
 749         enum plane plane;
 750         u8 lut_r[256], lut_g[256], lut_b[256];
 751         /*
 752          * Whether the crtc and the connected output pipeline is active. Implies
 753          * that crtc->enabled is set, i.e. the current mode configuration has
 754          * some outputs connected to this crtc.
 755          */
 756         bool active;
 757         bool lowfreq_avail;
 758         u8 plane_ids_mask;
 759         unsigned long long enabled_power_domains;
 760         struct intel_overlay *overlay;
 761         struct intel_flip_work *flip_work;
 762
 763         atomic_t unpin_work_count;
 764
 765         /* Display surface base address adjustement for pageflips. Note that on
 766          * gen4+ this only adjusts up to a tile, offsets within a tile are
 767          * handled in the hw itself (with the TILEOFF register). */
 768         u32 dspaddr_offset;
 769         int adjusted_x;
 770         int adjusted_y;
 771
 772         uint32_t cursor_addr;
 773         uint32_t cursor_cntl;
 774         uint32_t cursor_size;
 775         uint32_t cursor_base;
 776
 777         struct intel_crtc_state *config;
 778
 779         /* global reset count when the last flip was submitted */
 780         unsigned int reset_count;
 781
 782         /* Access to these should be protected by dev_priv->irq_lock. */
 783         bool cpu_fifo_underrun_disabled;
 784         bool pch_fifo_underrun_disabled;
 785
 786         /* per-pipe watermark state */
 787         struct {
 788                 /* watermarks currently being used  */
 789                 union {
 790                         struct intel_pipe_wm ilk;
 791                         struct vlv_wm_state vlv;
 792                 } active;
 793         } wm;
 794
 795         int scanline_offset;
 796
 797         struct {
 798                 unsigned start_vbl_count;
 799                 ktime_t start_vbl_time;
 800                 int min_vbl, max_vbl;
 801                 int scanline_start;
 802         } debug;
 803
 804         /* scalers available on this crtc */
 805         int num_scalers;
 806 };
 807
 808 struct intel_plane {
 809         struct drm_plane base;
 810         u8 plane;
 811         enum plane_id id;
 812         enum pipe pipe;
 813         bool can_scale;
 814         int max_downscale;
 815         uint32_t frontbuffer_bit;
 816
 817         /*
 818          * NOTE: Do not place new plane state fields here (e.g., when adding
 819          * new plane properties).  New runtime state should now be placed in
 820          * the intel_plane_state structure and accessed via plane_state.
 821          */
 822
 823         void (*update_plane)(struct drm_plane *plane,
 824                              const struct intel_crtc_state *crtc_state,
 825                              const struct intel_plane_state *plane_state);
 826         void (*disable_plane)(struct drm_plane *plane,
 827                               struct drm_crtc *crtc);
 828         int (*check_plane)(struct drm_plane *plane,
 829                            struct intel_crtc_state *crtc_state,
 830                            struct intel_plane_state *state);
 831 };
 832
 833 struct intel_watermark_params {
 834         u16 fifo_size;
 835         u16 max_wm;
 836         u8 default_wm;
 837         u8 guard_size;
 838         u8 cacheline_size;
 839 };
 840
 841 struct cxsr_latency {
 842         bool is_desktop : 1;
 843         bool is_ddr3 : 1;
 844         u16 fsb_freq;
 845         u16 mem_freq;
 846         u16 display_sr;
 847         u16 display_hpll_disable;
 848         u16 cursor_sr;
 849         u16 cursor_hpll_disable;
 850 };
 851
 852 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 853 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 854 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 855 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 856 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 857 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 858 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 859 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 860 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 861
 862 struct intel_hdmi {
 863         i915_reg_t hdmi_reg;
 864         int ddc_bus;
 865         struct {
 866                 enum drm_dp_dual_mode_type type;
 867                 int max_tmds_clock;
 868         } dp_dual_mode;
 869         bool limited_color_range;
 870         bool color_range_auto;
 871         bool has_hdmi_sink;
 872         bool has_audio;
 873         enum hdmi_force_audio force_audio;
 874         bool rgb_quant_range_selectable;
 875         enum hdmi_picture_aspect aspect_ratio;
 876         struct intel_connector *attached_connector;
 877         void (*write_infoframe)(struct drm_encoder *encoder,
 878                                 const struct intel_crtc_state *crtc_state,
 879                                 enum hdmi_infoframe_type type,
 880                                 const void *frame, ssize_t len);
 881         void (*set_infoframes)(struct drm_encoder *encoder,
 882                                bool enable,
 883                                const struct intel_crtc_state *crtc_state,
 884                                const struct drm_connector_state *conn_state);
 885         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 886                                   const struct intel_crtc_state *pipe_config);
 887 };
 888
 889 struct intel_dp_mst_encoder;
 890 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 891
 892 /*
 893  * enum link_m_n_set:
 894  *      When platform provides two set of M_N registers for dp, we can
 895  *      program them and switch between them incase of DRRS.
 896  *      But When only one such register is provided, we have to program the
 897  *      required divider value on that registers itself based on the DRRS state.
 898  *
 899  * M1_N1        : Program dp_m_n on M1_N1 registers
 900  *                        dp_m2_n2 on M2_N2 registers (If supported)
 901  *
 902  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 903  *                        M2_N2 registers are not supported
 904  */
 905
 906 enum link_m_n_set {
 907         /* Sets the m1_n1 and m2_n2 */
 908         M1_N1 = 0,
 909         M2_N2
 910 };
 911
 912 struct intel_dp_desc {
 913         u8 oui[3];
 914         u8 device_id[6];
 915         u8 hw_rev;
 916         u8 sw_major_rev;
 917         u8 sw_minor_rev;
 918 } __packed;
 919
 920 struct intel_dp_compliance_data {
 921         unsigned long edid;
 922         uint8_t video_pattern;
 923         uint16_t hdisplay, vdisplay;
 924         uint8_t bpc;
 925 };
 926
 927 struct intel_dp_compliance {
 928         unsigned long test_type;
 929         struct intel_dp_compliance_data test_data;
 930         bool test_active;
 931         int test_link_rate;
 932         u8 test_lane_count;
 933 };
 934
 935 struct intel_dp {
 936         i915_reg_t output_reg;
 937         i915_reg_t aux_ch_ctl_reg;
 938         i915_reg_t aux_ch_data_reg[5];
 939         uint32_t DP;
 940         int link_rate;
 941         uint8_t lane_count;
 942         uint8_t sink_count;
 943         bool link_mst;
 944         bool has_audio;
 945         bool detect_done;
 946         bool channel_eq_status;
 947         bool reset_link_params;
 948         enum hdmi_force_audio force_audio;
 949         bool limited_color_range;
 950         bool color_range_auto;
 951         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 952         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 953         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 954         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 955         /* source rates */
 956         int num_source_rates;
 957         const int *source_rates;
 958         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 959         int num_sink_rates;
 960         int sink_rates[DP_MAX_SUPPORTED_RATES];
 961         bool use_rate_select;
 962         /* intersection of source and sink rates */
 963         int num_common_rates;
 964         int common_rates[DP_MAX_SUPPORTED_RATES];
 965         /* Max lane count for the current link */
 966         int max_link_lane_count;
 967         /* Max rate for the current link */
 968         int max_link_rate;
 969         /* sink or branch descriptor */
 970         struct intel_dp_desc desc;
 971         struct drm_dp_aux aux;
 972         enum intel_display_power_domain aux_power_domain;
 973         uint8_t train_set[4];
 974         int panel_power_up_delay;
 975         int panel_power_down_delay;
 976         int panel_power_cycle_delay;
 977         int backlight_on_delay;
 978         int backlight_off_delay;
 979         struct delayed_work panel_vdd_work;
 980         bool want_panel_vdd;
 981         unsigned long last_power_on;
 982         unsigned long last_backlight_off;
 983         ktime_t panel_power_off_time;
 984
 985         struct notifier_block edp_notifier;
 986
 987         /*
 988          * Pipe whose power sequencer is currently locked into
 989          * this port. Only relevant on VLV/CHV.
 990          */
 991         enum pipe pps_pipe;
 992         /*
 993          * Pipe currently driving the port. Used for preventing
 994          * the use of the PPS for any pipe currentrly driving
 995          * external DP as that will mess things up on VLV.
 996          */
 997         enum pipe active_pipe;
 998         /*
 999          * Set if the sequencer may be reset due to a power transition,
1000          * requiring a reinitialization. Only relevant on BXT.
1001          */
1002         bool pps_reset;
1003         struct edp_power_seq pps_delays;
1004
1005         bool can_mst; /* this port supports mst */
1006         bool is_mst;
1007         int active_mst_links;
1008         /* connector directly attached - won't be use for modeset in mst world */
1009         struct intel_connector *attached_connector;
1010
1011         /* mst connector list */
1012         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1013         struct drm_dp_mst_topology_mgr mst_mgr;
1014
1015         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1016         /*
1017          * This function returns the value we have to program the AUX_CTL
1018          * register with to kick off an AUX transaction.
1019          */
1020         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1021                                      bool has_aux_irq,
1022                                      int send_bytes,
1023                                      uint32_t aux_clock_divider);
1024
1025         /* This is called before a link training is starterd */
1026         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1027
1028         /* Displayport compliance testing */
1029         struct intel_dp_compliance compliance;
1030 };
1031
1032 struct intel_lspcon {
1033         bool active;
1034         enum drm_lspcon_mode mode;
1035 };
1036
1037 struct intel_digital_port {
1038         struct intel_encoder base;
1039         enum port port;
1040         u32 saved_port_bits;
1041         struct intel_dp dp;
1042         struct intel_hdmi hdmi;
1043         struct intel_lspcon lspcon;
1044         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1045         bool release_cl2_override;
1046         uint8_t max_lanes;
1047         enum intel_display_power_domain ddi_io_power_domain;
1048 };
1049
1050 struct intel_dp_mst_encoder {
1051         struct intel_encoder base;
1052         enum pipe pipe;
1053         struct intel_digital_port *primary;
1054         struct intel_connector *connector;
1055 };
1056
1057 static inline enum dpio_channel
1058 vlv_dport_to_channel(struct intel_digital_port *dport)
1059 {
1060         switch (dport->port) {
1061         case PORT_B:
1062         case PORT_D:
1063                 return DPIO_CH0;
1064         case PORT_C:
1065                 return DPIO_CH1;
1066         default:
1067                 BUG();
1068         }
1069 }
1070
1071 static inline enum dpio_phy
1072 vlv_dport_to_phy(struct intel_digital_port *dport)
1073 {
1074         switch (dport->port) {
1075         case PORT_B:
1076         case PORT_C:
1077                 return DPIO_PHY0;
1078         case PORT_D:
1079                 return DPIO_PHY1;
1080         default:
1081                 BUG();
1082         }
1083 }
1084
1085 static inline enum dpio_channel
1086 vlv_pipe_to_channel(enum pipe pipe)
1087 {
1088         switch (pipe) {
1089         case PIPE_A:
1090         case PIPE_C:
1091                 return DPIO_CH0;
1092         case PIPE_B:
1093                 return DPIO_CH1;
1094         default:
1095                 BUG();
1096         }
1097 }
1098
1099 static inline struct intel_crtc *
1100 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1101 {
1102         return dev_priv->pipe_to_crtc_mapping[pipe];
1103 }
1104
1105 static inline struct intel_crtc *
1106 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1107 {
1108         return dev_priv->plane_to_crtc_mapping[plane];
1109 }
1110
1111 struct intel_flip_work {
1112         struct work_struct unpin_work;
1113         struct work_struct mmio_work;
1114
1115         struct drm_crtc *crtc;
1116         struct i915_vma *old_vma;
1117         struct drm_framebuffer *old_fb;
1118         struct drm_i915_gem_object *pending_flip_obj;
1119         struct drm_pending_vblank_event *event;
1120         atomic_t pending;
1121         u32 flip_count;
1122         u32 gtt_offset;
1123         struct drm_i915_gem_request *flip_queued_req;
1124         u32 flip_queued_vblank;
1125         u32 flip_ready_vblank;
1126         unsigned int rotation;
1127 };
1128
1129 struct intel_load_detect_pipe {
1130         struct drm_atomic_state *restore_state;
1131 };
1132
1133 static inline struct intel_encoder *
1134 intel_attached_encoder(struct drm_connector *connector)
1135 {
1136         return to_intel_connector(connector)->encoder;
1137 }
1138
1139 static inline struct intel_digital_port *
1140 enc_to_dig_port(struct drm_encoder *encoder)
1141 {
1142         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1143
1144         switch (intel_encoder->type) {
1145         case INTEL_OUTPUT_UNKNOWN:
1146                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1147         case INTEL_OUTPUT_DP:
1148         case INTEL_OUTPUT_EDP:
1149         case INTEL_OUTPUT_HDMI:
1150                 return container_of(encoder, struct intel_digital_port,
1151                                     base.base);
1152         default:
1153                 return NULL;
1154         }
1155 }
1156
1157 static inline struct intel_dp_mst_encoder *
1158 enc_to_mst(struct drm_encoder *encoder)
1159 {
1160         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1161 }
1162
1163 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1164 {
1165         return &enc_to_dig_port(encoder)->dp;
1166 }
1167
1168 static inline struct intel_digital_port *
1169 dp_to_dig_port(struct intel_dp *intel_dp)
1170 {
1171         return container_of(intel_dp, struct intel_digital_port, dp);
1172 }
1173
1174 static inline struct intel_lspcon *
1175 dp_to_lspcon(struct intel_dp *intel_dp)
1176 {
1177         return &dp_to_dig_port(intel_dp)->lspcon;
1178 }
1179
1180 static inline struct intel_digital_port *
1181 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1182 {
1183         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1184 }
1185
1186 /* intel_fifo_underrun.c */
1187 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1188                                            enum pipe pipe, bool enable);
1189 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1190                                            enum transcoder pch_transcoder,
1191                                            bool enable);
1192 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1193                                          enum pipe pipe);
1194 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1195                                          enum transcoder pch_transcoder);
1196 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1197 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1198
1199 /* i915_irq.c */
1200 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1201 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1202 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1203 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1204 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1205 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1206 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1207 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1208 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1209 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1210
1211 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1212                                             u32 mask)
1213 {
1214         return mask & ~i915->rps.pm_intrmsk_mbz;
1215 }
1216
1217 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1218 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1219 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1220 {
1221         /*
1222          * We only use drm_irq_uninstall() at unload and VT switch, so
1223          * this is the only thing we need to check.
1224          */
1225         return dev_priv->pm.irqs_enabled;
1226 }
1227
1228 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1229 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1230                                      unsigned int pipe_mask);
1231 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1232                                      unsigned int pipe_mask);
1233 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1234 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1235 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1236
1237 /* intel_crt.c */
1238 void intel_crt_init(struct drm_i915_private *dev_priv);
1239 void intel_crt_reset(struct drm_encoder *encoder);
1240
1241 /* intel_ddi.c */
1242 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1243                                 struct intel_crtc_state *old_crtc_state,
1244                                 struct drm_connector_state *old_conn_state);
1245 void hsw_fdi_link_train(struct intel_crtc *crtc,
1246                         const struct intel_crtc_state *crtc_state);
1247 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1248 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1249 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1250 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1251 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1252                                        enum transcoder cpu_transcoder);
1253 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1254 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1255 struct intel_encoder *
1256 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1257 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1258 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1259 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1260 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1261                                  struct intel_crtc *intel_crtc);
1262 void intel_ddi_get_config(struct intel_encoder *encoder,
1263                           struct intel_crtc_state *pipe_config);
1264
1265 void intel_ddi_clock_get(struct intel_encoder *encoder,
1266                          struct intel_crtc_state *pipe_config);
1267 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1268                                     bool state);
1269 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1270 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1271
1272 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1273                                    int plane, unsigned int height);
1274
1275 /* intel_audio.c */
1276 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1277 void intel_audio_codec_enable(struct intel_encoder *encoder,
1278                               const struct intel_crtc_state *crtc_state,
1279                               const struct drm_connector_state *conn_state);
1280 void intel_audio_codec_disable(struct intel_encoder *encoder);
1281 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1282 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1283 void intel_audio_init(struct drm_i915_private *dev_priv);
1284 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1285
1286 /* intel_cdclk.c */
1287 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1288 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1289 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1290 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1291 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1292 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1293 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1294 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1295 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1296                                const struct intel_cdclk_state *b);
1297 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1298                      const struct intel_cdclk_state *cdclk_state);
1299
1300 /* intel_display.c */
1301 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1302 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1303 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1304 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1305                       const char *name, u32 reg, int ref_freq);
1306 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1307                            const char *name, u32 reg);
1308 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1309 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1310 extern const struct drm_plane_funcs intel_plane_funcs;
1311 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1312 unsigned int intel_fb_xy_to_linear(int x, int y,
1313                                    const struct intel_plane_state *state,
1314                                    int plane);
1315 void intel_add_fb_offsets(int *x, int *y,
1316                           const struct intel_plane_state *state, int plane);
1317 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1318 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1319 void intel_mark_busy(struct drm_i915_private *dev_priv);
1320 void intel_mark_idle(struct drm_i915_private *dev_priv);
1321 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1322 int intel_display_suspend(struct drm_device *dev);
1323 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1324 void intel_encoder_destroy(struct drm_encoder *encoder);
1325 int intel_connector_init(struct intel_connector *);
1326 struct intel_connector *intel_connector_alloc(void);
1327 bool intel_connector_get_hw_state(struct intel_connector *connector);
1328 void intel_connector_attach_encoder(struct intel_connector *connector,
1329                                     struct intel_encoder *encoder);
1330 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1331                                              struct drm_crtc *crtc);
1332 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1333 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1334                                 struct drm_file *file_priv);
1335 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1336                                              enum pipe pipe);
1337 static inline bool
1338 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1339                     enum intel_output_type type)
1340 {
1341         return crtc_state->output_types & (1 << type);
1342 }
1343 static inline bool
1344 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1345 {
1346         return crtc_state->output_types &
1347                 ((1 << INTEL_OUTPUT_DP) |
1348                  (1 << INTEL_OUTPUT_DP_MST) |
1349                  (1 << INTEL_OUTPUT_EDP));
1350 }
1351 static inline void
1352 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1353 {
1354         drm_wait_one_vblank(&dev_priv->drm, pipe);
1355 }
1356 static inline void
1357 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1358 {
1359         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1360
1361         if (crtc->active)
1362                 intel_wait_for_vblank(dev_priv, pipe);
1363 }
1364
1365 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1366
1367 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1368 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1369                          struct intel_digital_port *dport,
1370                          unsigned int expected_mask);
1371 int intel_get_load_detect_pipe(struct drm_connector *connector,
1372                                struct drm_display_mode *mode,
1373                                struct intel_load_detect_pipe *old,
1374                                struct drm_modeset_acquire_ctx *ctx);
1375 void intel_release_load_detect_pipe(struct drm_connector *connector,
1376                                     struct intel_load_detect_pipe *old,
1377                                     struct drm_modeset_acquire_ctx *ctx);
1378 struct i915_vma *
1379 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1380 void intel_unpin_fb_vma(struct i915_vma *vma);
1381 struct drm_framebuffer *
1382 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1383                          struct drm_mode_fb_cmd2 *mode_cmd);
1384 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1385 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1386 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1387 int intel_prepare_plane_fb(struct drm_plane *plane,
1388                            struct drm_plane_state *new_state);
1389 void intel_cleanup_plane_fb(struct drm_plane *plane,
1390                             struct drm_plane_state *old_state);
1391 int intel_plane_atomic_get_property(struct drm_plane *plane,
1392                                     const struct drm_plane_state *state,
1393                                     struct drm_property *property,
1394                                     uint64_t *val);
1395 int intel_plane_atomic_set_property(struct drm_plane *plane,
1396                                     struct drm_plane_state *state,
1397                                     struct drm_property *property,
1398                                     uint64_t val);
1399 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1400                                     struct drm_plane_state *plane_state);
1401
1402 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1403                                     enum pipe pipe);
1404
1405 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1406                      const struct dpll *dpll);
1407 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1408 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1409
1410 /* modesetting asserts */
1411 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1412                            enum pipe pipe);
1413 void assert_pll(struct drm_i915_private *dev_priv,
1414                 enum pipe pipe, bool state);
1415 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1416 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1417 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1418 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1419 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1420 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1421                        enum pipe pipe, bool state);
1422 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1423 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1424 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1425 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1426 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1427 u32 intel_compute_tile_offset(int *x, int *y,
1428                               const struct intel_plane_state *state, int plane);
1429 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1430 void intel_finish_reset(struct drm_i915_private *dev_priv);
1431 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1432 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1433 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1434 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1435 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1436 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1437 unsigned int skl_cdclk_get_vco(unsigned int freq);
1438 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1439 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1440 void intel_dp_get_m_n(struct intel_crtc *crtc,
1441                       struct intel_crtc_state *pipe_config);
1442 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1443 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1444 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1445                         struct dpll *best_clock);
1446 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1447
1448 bool intel_crtc_active(struct intel_crtc *crtc);
1449 void hsw_enable_ips(struct intel_crtc *crtc);
1450 void hsw_disable_ips(struct intel_crtc *crtc);
1451 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1452 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1453                                  struct intel_crtc_state *pipe_config);
1454
1455 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1456 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1457
1458 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1459 {
1460         return i915_ggtt_offset(state->vma);
1461 }
1462
1463 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1464                   const struct intel_plane_state *plane_state);
1465 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1466                      unsigned int rotation);
1467 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1468 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1469
1470 /* intel_csr.c */
1471 void intel_csr_ucode_init(struct drm_i915_private *);
1472 void intel_csr_load_program(struct drm_i915_private *);
1473 void intel_csr_ucode_fini(struct drm_i915_private *);
1474 void intel_csr_ucode_suspend(struct drm_i915_private *);
1475 void intel_csr_ucode_resume(struct drm_i915_private *);
1476
1477 /* intel_dp.c */
1478 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1479                    enum port port);
1480 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1481                              struct intel_connector *intel_connector);
1482 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1483                               int link_rate, uint8_t lane_count,
1484                               bool link_mst);
1485 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1486                                             int link_rate, uint8_t lane_count);
1487 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1488 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1489 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1490 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1491 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1492 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1493 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1494 bool intel_dp_compute_config(struct intel_encoder *encoder,
1495                              struct intel_crtc_state *pipe_config,
1496                              struct drm_connector_state *conn_state);
1497 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1498 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1499                                   bool long_hpd);
1500 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1501 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1502 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1503 void intel_edp_panel_on(struct intel_dp *intel_dp);
1504 void intel_edp_panel_off(struct intel_dp *intel_dp);
1505 void intel_dp_mst_suspend(struct drm_device *dev);
1506 void intel_dp_mst_resume(struct drm_device *dev);
1507 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1508 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1509 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1510 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1511 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1512 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1513 void intel_plane_destroy(struct drm_plane *plane);
1514 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1515                            struct intel_crtc_state *crtc_state);
1516 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1517                            struct intel_crtc_state *crtc_state);
1518 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1519                                unsigned int frontbuffer_bits);
1520 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1521                           unsigned int frontbuffer_bits);
1522
1523 void
1524 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1525                                        uint8_t dp_train_pat);
1526 void
1527 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1528 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1529 uint8_t
1530 intel_dp_voltage_max(struct intel_dp *intel_dp);
1531 uint8_t
1532 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1533 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1534                            uint8_t *link_bw, uint8_t *rate_select);
1535 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1536 bool
1537 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1538
1539 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1540 {
1541         return ~((1 << lane_count) - 1) & 0xf;
1542 }
1543
1544 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1545 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1546                           struct intel_dp_desc *desc);
1547 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1548 int intel_dp_link_required(int pixel_clock, int bpp);
1549 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1550 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1551                                   struct intel_digital_port *port);
1552
1553 /* intel_dp_aux_backlight.c */
1554 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1555
1556 /* intel_dp_mst.c */
1557 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1558 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1559 /* intel_dsi.c */
1560 void intel_dsi_init(struct drm_i915_private *dev_priv);
1561
1562 /* intel_dsi_dcs_backlight.c */
1563 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1564
1565 /* intel_dvo.c */
1566 void intel_dvo_init(struct drm_i915_private *dev_priv);
1567 /* intel_hotplug.c */
1568 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1569
1570
1571 /* legacy fbdev emulation in intel_fbdev.c */
1572 #ifdef CONFIG_DRM_FBDEV_EMULATION
1573 extern int intel_fbdev_init(struct drm_device *dev);
1574 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1575 extern void intel_fbdev_fini(struct drm_device *dev);
1576 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1577 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1578 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1579 #else
1580 static inline int intel_fbdev_init(struct drm_device *dev)
1581 {
1582         return 0;
1583 }
1584
1585 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1586 {
1587 }
1588
1589 static inline void intel_fbdev_fini(struct drm_device *dev)
1590 {
1591 }
1592
1593 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1594 {
1595 }
1596
1597 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1598 {
1599 }
1600
1601 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1602 {
1603 }
1604 #endif
1605
1606 /* intel_fbc.c */
1607 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1608                            struct drm_atomic_state *state);
1609 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1610 void intel_fbc_pre_update(struct intel_crtc *crtc,
1611                           struct intel_crtc_state *crtc_state,
1612                           struct intel_plane_state *plane_state);
1613 void intel_fbc_post_update(struct intel_crtc *crtc);
1614 void intel_fbc_init(struct drm_i915_private *dev_priv);
1615 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1616 void intel_fbc_enable(struct intel_crtc *crtc,
1617                       struct intel_crtc_state *crtc_state,
1618                       struct intel_plane_state *plane_state);
1619 void intel_fbc_disable(struct intel_crtc *crtc);
1620 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1621 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1622                           unsigned int frontbuffer_bits,
1623                           enum fb_op_origin origin);
1624 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1625                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1626 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1627 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1628
1629 /* intel_hdmi.c */
1630 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1631                      enum port port);
1632 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1633                                struct intel_connector *intel_connector);
1634 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1635 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1636                                struct intel_crtc_state *pipe_config,
1637                                struct drm_connector_state *conn_state);
1638 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1639                                        struct drm_connector *connector,
1640                                        bool high_tmds_clock_ratio,
1641                                        bool scrambling);
1642 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1643
1644
1645 /* intel_lvds.c */
1646 void intel_lvds_init(struct drm_i915_private *dev_priv);
1647 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1648 bool intel_is_dual_link_lvds(struct drm_device *dev);
1649
1650
1651 /* intel_modes.c */
1652 int intel_connector_update_modes(struct drm_connector *connector,
1653                                  struct edid *edid);
1654 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1655 void intel_attach_force_audio_property(struct drm_connector *connector);
1656 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1657 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1658
1659
1660 /* intel_overlay.c */
1661 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1662 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1663 int intel_overlay_switch_off(struct intel_overlay *overlay);
1664 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1665                                   struct drm_file *file_priv);
1666 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1667                               struct drm_file *file_priv);
1668 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1669
1670
1671 /* intel_panel.c */
1672 int intel_panel_init(struct intel_panel *panel,
1673                      struct drm_display_mode *fixed_mode,
1674                      struct drm_display_mode *downclock_mode);
1675 void intel_panel_fini(struct intel_panel *panel);
1676 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1677                             struct drm_display_mode *adjusted_mode);
1678 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1679                              struct intel_crtc_state *pipe_config,
1680                              int fitting_mode);
1681 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1682                               struct intel_crtc_state *pipe_config,
1683                               int fitting_mode);
1684 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1685                                     u32 level, u32 max);
1686 int intel_panel_setup_backlight(struct drm_connector *connector,
1687                                 enum pipe pipe);
1688 void intel_panel_enable_backlight(struct intel_connector *connector);
1689 void intel_panel_disable_backlight(struct intel_connector *connector);
1690 void intel_panel_destroy_backlight(struct drm_connector *connector);
1691 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1692 extern struct drm_display_mode *intel_find_panel_downclock(
1693                                 struct drm_i915_private *dev_priv,
1694                                 struct drm_display_mode *fixed_mode,
1695                                 struct drm_connector *connector);
1696
1697 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1698 int intel_backlight_device_register(struct intel_connector *connector);
1699 void intel_backlight_device_unregister(struct intel_connector *connector);
1700 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1701 static int intel_backlight_device_register(struct intel_connector *connector)
1702 {
1703         return 0;
1704 }
1705 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1706 {
1707 }
1708 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1709
1710
1711 /* intel_psr.c */
1712 void intel_psr_enable(struct intel_dp *intel_dp);
1713 void intel_psr_disable(struct intel_dp *intel_dp);
1714 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1715                           unsigned frontbuffer_bits);
1716 void intel_psr_flush(struct drm_i915_private *dev_priv,
1717                      unsigned frontbuffer_bits,
1718                      enum fb_op_origin origin);
1719 void intel_psr_init(struct drm_i915_private *dev_priv);
1720 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1721                                    unsigned frontbuffer_bits);
1722
1723 /* intel_runtime_pm.c */
1724 int intel_power_domains_init(struct drm_i915_private *);
1725 void intel_power_domains_fini(struct drm_i915_private *);
1726 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1727 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1728 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1729 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1730 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1731 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1732 const char *
1733 intel_display_power_domain_str(enum intel_display_power_domain domain);
1734
1735 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1736                                     enum intel_display_power_domain domain);
1737 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1738                                       enum intel_display_power_domain domain);
1739 void intel_display_power_get(struct drm_i915_private *dev_priv,
1740                              enum intel_display_power_domain domain);
1741 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1742                                         enum intel_display_power_domain domain);
1743 void intel_display_power_put(struct drm_i915_private *dev_priv,
1744                              enum intel_display_power_domain domain);
1745
1746 static inline void
1747 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1748 {
1749         WARN_ONCE(dev_priv->pm.suspended,
1750                   "Device suspended during HW access\n");
1751 }
1752
1753 static inline void
1754 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1755 {
1756         assert_rpm_device_not_suspended(dev_priv);
1757         WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1758                   "RPM wakelock ref not held during HW access");
1759 }
1760
1761 /**
1762  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1763  * @dev_priv: i915 device instance
1764  *
1765  * This function disable asserts that check if we hold an RPM wakelock
1766  * reference, while keeping the device-not-suspended checks still enabled.
1767  * It's meant to be used only in special circumstances where our rule about
1768  * the wakelock refcount wrt. the device power state doesn't hold. According
1769  * to this rule at any point where we access the HW or want to keep the HW in
1770  * an active state we must hold an RPM wakelock reference acquired via one of
1771  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1772  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1773  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1774  * users should avoid using this function.
1775  *
1776  * Any calls to this function must have a symmetric call to
1777  * enable_rpm_wakeref_asserts().
1778  */
1779 static inline void
1780 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1781 {
1782         atomic_inc(&dev_priv->pm.wakeref_count);
1783 }
1784
1785 /**
1786  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1787  * @dev_priv: i915 device instance
1788  *
1789  * This function re-enables the RPM assert checks after disabling them with
1790  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1791  * circumstances otherwise its use should be avoided.
1792  *
1793  * Any calls to this function must have a symmetric call to
1794  * disable_rpm_wakeref_asserts().
1795  */
1796 static inline void
1797 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1798 {
1799         atomic_dec(&dev_priv->pm.wakeref_count);
1800 }
1801
1802 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1803 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1804 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1805 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1806
1807 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1808
1809 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1810                              bool override, unsigned int mask);
1811 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1812                           enum dpio_channel ch, bool override);
1813
1814
1815 /* intel_pm.c */
1816 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1817 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1818 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1819 void intel_update_watermarks(struct intel_crtc *crtc);
1820 void intel_init_pm(struct drm_i915_private *dev_priv);
1821 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1822 void intel_pm_setup(struct drm_i915_private *dev_priv);
1823 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1824 void intel_gpu_ips_teardown(void);
1825 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1826 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1827 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1828 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1829 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1830 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1831 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1832 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1833 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1834 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1835 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1836                     struct intel_rps_client *rps,
1837                     unsigned long submitted);
1838 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1839 void vlv_wm_get_hw_state(struct drm_device *dev);
1840 void ilk_wm_get_hw_state(struct drm_device *dev);
1841 void skl_wm_get_hw_state(struct drm_device *dev);
1842 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1843                           struct skl_ddb_allocation *ddb /* out */);
1844 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1845                               struct skl_pipe_wm *out);
1846 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1847 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1848 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1849 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1850 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1851                          const struct skl_wm_level *l2);
1852 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1853                                  const struct skl_ddb_entry *ddb,
1854                                  int ignore);
1855 bool ilk_disable_lp_wm(struct drm_device *dev);
1856 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1857 static inline int intel_enable_rc6(void)
1858 {
1859         return i915.enable_rc6;
1860 }
1861
1862 /* intel_sdvo.c */
1863 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1864                      i915_reg_t reg, enum port port);
1865
1866
1867 /* intel_sprite.c */
1868 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1869                              int usecs);
1870 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1871                                               enum pipe pipe, int plane);
1872 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1873                               struct drm_file *file_priv);
1874 void intel_pipe_update_start(struct intel_crtc *crtc);
1875 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1876
1877 /* intel_tv.c */
1878 void intel_tv_init(struct drm_i915_private *dev_priv);
1879
1880 /* intel_atomic.c */
1881 int intel_connector_atomic_get_property(struct drm_connector *connector,
1882                                         const struct drm_connector_state *state,
1883                                         struct drm_property *property,
1884                                         uint64_t *val);
1885 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1886 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1887                                struct drm_crtc_state *state);
1888 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1889 void intel_atomic_state_clear(struct drm_atomic_state *);
1890
1891 static inline struct intel_crtc_state *
1892 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1893                             struct intel_crtc *crtc)
1894 {
1895         struct drm_crtc_state *crtc_state;
1896         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1897         if (IS_ERR(crtc_state))
1898                 return ERR_CAST(crtc_state);
1899
1900         return to_intel_crtc_state(crtc_state);
1901 }
1902
1903 static inline struct intel_crtc_state *
1904 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1905                                      struct intel_crtc *crtc)
1906 {
1907         struct drm_crtc_state *crtc_state;
1908
1909         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1910
1911         if (crtc_state)
1912                 return to_intel_crtc_state(crtc_state);
1913         else
1914                 return NULL;
1915 }
1916
1917 static inline struct intel_plane_state *
1918 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1919                                       struct intel_plane *plane)
1920 {
1921         struct drm_plane_state *plane_state;
1922
1923         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1924
1925         return to_intel_plane_state(plane_state);
1926 }
1927
1928 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1929                                struct intel_crtc *intel_crtc,
1930                                struct intel_crtc_state *crtc_state);
1931
1932 /* intel_atomic_plane.c */
1933 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1934 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1935 void intel_plane_destroy_state(struct drm_plane *plane,
1936                                struct drm_plane_state *state);
1937 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1938 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1939                                         struct intel_plane_state *intel_state);
1940
1941 /* intel_color.c */
1942 void intel_color_init(struct drm_crtc *crtc);
1943 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1944 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1945 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1946
1947 /* intel_lspcon.c */
1948 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1949 void lspcon_resume(struct intel_lspcon *lspcon);
1950 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1951
1952 /* intel_pipe_crc.c */
1953 int intel_pipe_crc_create(struct drm_minor *minor);
1954 #ifdef CONFIG_DEBUG_FS
1955 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1956                               size_t *values_cnt);
1957 #else
1958 #define intel_crtc_set_crc_source NULL
1959 #endif
1960 extern const struct file_operations i915_display_crc_ctl_fops;
1961 #endif /* __INTEL_DRV_H__ */