2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
44 * _wait_for - magic (register) wait macro
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
51 * TODO: When modesetting has fully transitioned to atomic, the below
52 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
55 #define _wait_for(COND, US, W) ({ \
56 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
59 bool expired__ = time_after(jiffies, timeout__); \
68 if ((W) && drm_can_sleep()) { \
69 usleep_range((W), (W)*2); \
77 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
86 #define _wait_for_atomic(COND, US, ATOMIC) \
88 int cpu, ret, timeout = (US) * 1000; \
90 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
93 cpu = smp_processor_id(); \
95 base = local_clock(); \
97 u64 now = local_clock(); \
104 if (now - base >= timeout) { \
111 if (unlikely(cpu != smp_processor_id())) { \
112 timeout -= now - base; \
113 cpu = smp_processor_id(); \
114 base = local_clock(); \
121 #define wait_for_us(COND, US) \
124 BUILD_BUG_ON(!__builtin_constant_p(US)); \
126 ret__ = _wait_for((COND), (US), 10); \
128 ret__ = _wait_for_atomic((COND), (US), 0); \
132 #define wait_for_atomic_us(COND, US) \
134 BUILD_BUG_ON(!__builtin_constant_p(US)); \
135 BUILD_BUG_ON((US) > 50000); \
136 _wait_for_atomic((COND), (US), 1); \
139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
141 #define KHz(x) (1000 * (x))
142 #define MHz(x) KHz(1000 * (x))
145 * Display related stuff
148 /* store information about an Ixxx DVO */
149 /* The i830->i865 use multiple DVOs with multiple i2cs */
150 /* the i915, i945 have a single sDVO i2c bus - which is different */
151 #define MAX_OUTPUTS 6
152 /* maximum connectors per crtcs in the mode set */
154 /* Maximum cursor sizes */
155 #define GEN2_CURSOR_WIDTH 64
156 #define GEN2_CURSOR_HEIGHT 64
157 #define MAX_CURSOR_WIDTH 256
158 #define MAX_CURSOR_HEIGHT 256
160 #define INTEL_I2C_BUS_DVO 1
161 #define INTEL_I2C_BUS_SDVO 2
163 /* these are outputs from the chip - integrated only
164 external chips are via DVO or SDVO output */
165 enum intel_output_type {
166 INTEL_OUTPUT_UNUSED = 0,
167 INTEL_OUTPUT_ANALOG = 1,
168 INTEL_OUTPUT_DVO = 2,
169 INTEL_OUTPUT_SDVO = 3,
170 INTEL_OUTPUT_LVDS = 4,
171 INTEL_OUTPUT_TVOUT = 5,
172 INTEL_OUTPUT_HDMI = 6,
174 INTEL_OUTPUT_EDP = 8,
175 INTEL_OUTPUT_DSI = 9,
176 INTEL_OUTPUT_UNKNOWN = 10,
177 INTEL_OUTPUT_DP_MST = 11,
180 #define INTEL_DVO_CHIP_NONE 0
181 #define INTEL_DVO_CHIP_LVDS 1
182 #define INTEL_DVO_CHIP_TMDS 2
183 #define INTEL_DVO_CHIP_TVOUT 4
185 #define INTEL_DSI_VIDEO_MODE 0
186 #define INTEL_DSI_COMMAND_MODE 1
188 struct intel_framebuffer {
189 struct drm_framebuffer base;
190 struct drm_i915_gem_object *obj;
191 struct intel_rotation_info rot_info;
193 /* for each plane in the normal GTT view */
197 /* for each plane in the rotated GTT view */
200 unsigned int pitch; /* pixels */
205 struct drm_fb_helper helper;
206 struct intel_framebuffer *fb;
207 struct i915_vma *vma;
208 async_cookie_t cookie;
212 struct intel_encoder {
213 struct drm_encoder base;
215 enum intel_output_type type;
217 unsigned int cloneable;
218 void (*hot_plug)(struct intel_encoder *);
219 bool (*compute_config)(struct intel_encoder *,
220 struct intel_crtc_state *,
221 struct drm_connector_state *);
222 void (*pre_pll_enable)(struct intel_encoder *,
223 struct intel_crtc_state *,
224 struct drm_connector_state *);
225 void (*pre_enable)(struct intel_encoder *,
226 struct intel_crtc_state *,
227 struct drm_connector_state *);
228 void (*enable)(struct intel_encoder *,
229 struct intel_crtc_state *,
230 struct drm_connector_state *);
231 void (*disable)(struct intel_encoder *,
232 struct intel_crtc_state *,
233 struct drm_connector_state *);
234 void (*post_disable)(struct intel_encoder *,
235 struct intel_crtc_state *,
236 struct drm_connector_state *);
237 void (*post_pll_disable)(struct intel_encoder *,
238 struct intel_crtc_state *,
239 struct drm_connector_state *);
240 /* Read out the current hw state of this connector, returning true if
241 * the encoder is active. If the encoder is enabled it also set the pipe
242 * it is connected to in the pipe parameter. */
243 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
244 /* Reconstructs the equivalent mode flags for the current hardware
245 * state. This must be called _after_ display->get_pipe_config has
246 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
247 * be set correctly before calling this function. */
248 void (*get_config)(struct intel_encoder *,
249 struct intel_crtc_state *pipe_config);
250 /* Returns a mask of power domains that need to be referenced as part
251 * of the hardware state readout code. */
252 u64 (*get_power_domains)(struct intel_encoder *encoder);
254 * Called during system suspend after all pending requests for the
255 * encoder are flushed (for example for DP AUX transactions) and
256 * device interrupts are disabled.
258 void (*suspend)(struct intel_encoder *);
260 enum hpd_pin hpd_pin;
261 enum intel_display_power_domain power_domain;
262 /* for communication with audio component; protected by av_mutex */
263 const struct drm_connector *audio_connector;
267 struct drm_display_mode *fixed_mode;
268 struct drm_display_mode *downclock_mode;
277 bool combination_mode; /* gen 2/4 only */
279 bool alternate_pwm_increment; /* lpt+ */
282 bool util_pin_active_low; /* bxt+ */
283 u8 controller; /* bxt+ only */
284 struct pwm_device *pwm;
286 struct backlight_device *device;
288 /* Connector and platform specific backlight functions */
289 int (*setup)(struct intel_connector *connector, enum pipe pipe);
290 uint32_t (*get)(struct intel_connector *connector);
291 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
292 void (*disable)(const struct drm_connector_state *conn_state);
293 void (*enable)(const struct intel_crtc_state *crtc_state,
294 const struct drm_connector_state *conn_state);
295 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
297 void (*power)(struct intel_connector *, bool enable);
301 struct intel_connector {
302 struct drm_connector base;
304 * The fixed encoder this connector is connected to.
306 struct intel_encoder *encoder;
308 /* ACPI device id for ACPI and driver cooperation */
311 /* Reads out the current hw, returning true if the connector is enabled
312 * and active (i.e. dpms ON state). */
313 bool (*get_hw_state)(struct intel_connector *);
315 /* Panel info for eDP and LVDS */
316 struct intel_panel panel;
318 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
320 struct edid *detect_edid;
322 /* since POLL and HPD connectors may use the same HPD line keep the native
323 state of connector->polled in case hotplug storm detection changes it */
326 void *port; /* store this opaque as its illegal to dereference it */
328 struct intel_dp *mst_port;
330 /* Work struct to schedule a uevent on link train failure */
331 struct work_struct modeset_retry_work;
334 struct intel_digital_connector_state {
335 struct drm_connector_state base;
337 enum hdmi_force_audio force_audio;
341 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
355 struct intel_atomic_state {
356 struct drm_atomic_state base;
360 * Logical state of cdclk (used for all scaling, watermark,
361 * etc. calculations and checks). This is computed as if all
362 * enabled crtcs were active.
364 struct intel_cdclk_state logical;
367 * Actual state of cdclk, can be different from the logical
368 * state only when all crtc's are DPMS off.
370 struct intel_cdclk_state actual;
373 bool dpll_set, modeset;
376 * Does this transaction change the pipes that are active? This mask
377 * tracks which CRTC's have changed their active state at the end of
378 * the transaction (not counting the temporary disable during modesets).
379 * This mask should only be non-zero when intel_state->modeset is true,
380 * but the converse is not necessarily true; simply changing a mode may
381 * not flip the final active status of any CRTC's
383 unsigned int active_pipe_changes;
385 unsigned int active_crtcs;
386 unsigned int min_pixclk[I915_MAX_PIPES];
388 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
391 * Current watermarks can't be trusted during hardware readout, so
392 * don't bother calculating intermediate watermarks.
394 bool skip_intermediate_wm;
397 struct skl_wm_values wm_results;
399 struct i915_sw_fence commit_ready;
401 struct llist_node freed;
404 struct intel_plane_state {
405 struct drm_plane_state base;
406 struct drm_rect clip;
407 struct i915_vma *vma;
418 /* plane control register */
423 * = -1 : not using a scaler
424 * >= 0 : using a scalers
426 * plane requiring a scaler:
427 * - During check_plane, its bit is set in
428 * crtc_state->scaler_state.scaler_users by calling helper function
429 * update_scaler_plane.
430 * - scaler_id indicates the scaler it got assigned.
432 * plane doesn't require a scaler:
433 * - this can happen when scaling is no more required or plane simply
435 * - During check_plane, corresponding bit is reset in
436 * crtc_state->scaler_state.scaler_users by calling helper function
437 * update_scaler_plane.
441 struct drm_intel_sprite_colorkey ckey;
444 struct intel_initial_plane_config {
445 struct intel_framebuffer *fb;
451 #define SKL_MIN_SRC_W 8
452 #define SKL_MAX_SRC_W 4096
453 #define SKL_MIN_SRC_H 8
454 #define SKL_MAX_SRC_H 4096
455 #define SKL_MIN_DST_W 8
456 #define SKL_MAX_DST_W 4096
457 #define SKL_MIN_DST_H 8
458 #define SKL_MAX_DST_H 4096
460 struct intel_scaler {
465 struct intel_crtc_scaler_state {
466 #define SKL_NUM_SCALERS 2
467 struct intel_scaler scalers[SKL_NUM_SCALERS];
470 * scaler_users: keeps track of users requesting scalers on this crtc.
472 * If a bit is set, a user is using a scaler.
473 * Here user can be a plane or crtc as defined below:
474 * bits 0-30 - plane (bit position is index from drm_plane_index)
477 * Instead of creating a new index to cover planes and crtc, using
478 * existing drm_plane_index for planes which is well less than 31
479 * planes and bit 31 for crtc. This should be fine to cover all
482 * intel_atomic_setup_scalers will setup available scalers to users
483 * requesting scalers. It will gracefully fail if request exceeds
486 #define SKL_CRTC_INDEX 31
487 unsigned scaler_users;
489 /* scaler used by crtc for panel fitting purpose */
493 /* drm_mode->private_flags */
494 #define I915_MODE_FLAG_INHERITED 1
496 struct intel_pipe_wm {
497 struct intel_wm_level wm[5];
498 struct intel_wm_level raw_wm[5];
502 bool sprites_enabled;
506 struct skl_plane_wm {
507 struct skl_wm_level wm[8];
508 struct skl_wm_level trans_wm;
512 struct skl_plane_wm planes[I915_MAX_PLANES];
519 VLV_WM_LEVEL_DDR_DVFS,
523 struct vlv_wm_state {
524 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
525 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
530 struct vlv_fifo_state {
531 u16 plane[I915_MAX_PLANES];
541 struct g4x_wm_state {
542 struct g4x_pipe_wm wm;
544 struct g4x_sr_wm hpll;
550 struct intel_crtc_wm_state {
554 * Intermediate watermarks; these can be
555 * programmed immediately since they satisfy
556 * both the current configuration we're
557 * switching away from and the new
558 * configuration we're switching to.
560 struct intel_pipe_wm intermediate;
563 * Optimal watermarks, programmed post-vblank
564 * when this state is committed.
566 struct intel_pipe_wm optimal;
570 /* gen9+ only needs 1-step wm programming */
571 struct skl_pipe_wm optimal;
572 struct skl_ddb_entry ddb;
576 /* "raw" watermarks (not inverted) */
577 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
578 /* intermediate watermarks (inverted) */
579 struct vlv_wm_state intermediate;
580 /* optimal watermarks (inverted) */
581 struct vlv_wm_state optimal;
582 /* display FIFO split */
583 struct vlv_fifo_state fifo_state;
587 /* "raw" watermarks */
588 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
589 /* intermediate watermarks */
590 struct g4x_wm_state intermediate;
591 /* optimal watermarks */
592 struct g4x_wm_state optimal;
597 * Platforms with two-step watermark programming will need to
598 * update watermark programming post-vblank to switch from the
599 * safe intermediate watermarks to the optimal final
602 bool need_postvbl_update;
605 struct intel_crtc_state {
606 struct drm_crtc_state base;
609 * quirks - bitfield with hw state readout quirks
611 * For various reasons the hw state readout code might not be able to
612 * completely faithfully read out the current state. These cases are
613 * tracked with quirk flags so that fastboot and state checker can act
616 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
617 unsigned long quirks;
619 unsigned fb_bits; /* framebuffers to flip */
620 bool update_pipe; /* can a fast modeset be performed? */
622 bool update_wm_pre, update_wm_post; /* watermarks are updated */
623 bool fb_changed; /* fb on any of the planes is changed */
624 bool fifo_changed; /* FIFO split is changed */
626 /* Pipe source size (ie. panel fitter input size)
627 * All planes will be positioned inside this space,
628 * and get clipped at the edges. */
629 int pipe_src_w, pipe_src_h;
632 * Pipe pixel rate, adjusted for
633 * panel fitter/pipe scaler downscaling.
635 unsigned int pixel_rate;
637 /* Whether to set up the PCH/FDI. Note that we never allow sharing
638 * between pch encoders and cpu encoders. */
639 bool has_pch_encoder;
641 /* Are we sending infoframes on the attached port */
644 /* CPU Transcoder for the pipe. Currently this can only differ from the
645 * pipe on Haswell and later (where we have a special eDP transcoder)
646 * and Broxton (where we have special DSI transcoders). */
647 enum transcoder cpu_transcoder;
650 * Use reduced/limited/broadcast rbg range, compressing from the full
651 * range fed into the crtcs.
653 bool limited_color_range;
655 /* Bitmask of encoder types (enum intel_output_type)
656 * driven by the pipe.
658 unsigned int output_types;
660 /* Whether we should send NULL infoframes. Required for audio. */
663 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
664 * has_dp_encoder is set. */
668 * Enable dithering, used when the selected pipe bpp doesn't match the
674 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
675 * compliance video pattern tests.
676 * Disable dither only if it is a compliance test request for
679 bool dither_force_disable;
681 /* Controls for the clock computation, to override various stages. */
684 /* SDVO TV has a bunch of special case. To make multifunction encoders
685 * work correctly, we need to track this at runtime.*/
689 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
690 * required. This is set in the 2nd loop of calling encoder's
691 * ->compute_config if the first pick doesn't work out.
695 /* Settings for the intel dpll used on pretty much everything but
699 /* Selected dpll when shared or NULL. */
700 struct intel_shared_dpll *shared_dpll;
702 /* Actual register state of the dpll, for shared dpll cross-checking. */
703 struct intel_dpll_hw_state dpll_hw_state;
705 /* DSI PLL registers */
711 struct intel_link_m_n dp_m_n;
713 /* m2_n2 for eDP downclock */
714 struct intel_link_m_n dp_m2_n2;
718 * Frequence the dpll for the port should run at. Differs from the
719 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
720 * already multiplied by pixel_multiplier.
724 /* Used by SDVO (and if we ever fix it, HDMI). */
725 unsigned pixel_multiplier;
730 * Used by platforms having DP/HDMI PHY with programmable lane
731 * latency optimization.
733 uint8_t lane_lat_optim_mask;
735 /* Panel fitter controls for gen2-gen4 + VLV */
739 u32 lvds_border_bits;
742 /* Panel fitter placement and size for Ironlake+ */
750 /* FDI configuration, only valid if has_pch_encoder is set. */
752 struct intel_link_m_n fdi_m_n;
762 struct intel_crtc_scaler_state scaler_state;
764 /* w/a for waiting 2 vblanks during crtc enable */
765 enum pipe hsw_workaround_pipe;
767 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
770 struct intel_crtc_wm_state wm;
772 /* Gamma mode programmed on the pipe */
775 /* bitmask of visible planes (enum plane_id) */
778 /* HDMI scrambling status */
779 bool hdmi_scrambling;
781 /* HDMI High TMDS char rate ratio */
782 bool hdmi_high_tmds_clock_ratio;
786 struct drm_crtc base;
789 u8 lut_r[256], lut_g[256], lut_b[256];
791 * Whether the crtc and the connected output pipeline is active. Implies
792 * that crtc->enabled is set, i.e. the current mode configuration has
793 * some outputs connected to this crtc.
798 unsigned long long enabled_power_domains;
799 struct intel_overlay *overlay;
800 struct intel_flip_work *flip_work;
802 atomic_t unpin_work_count;
804 /* Display surface base address adjustement for pageflips. Note that on
805 * gen4+ this only adjusts up to a tile, offsets within a tile are
806 * handled in the hw itself (with the TILEOFF register). */
811 struct intel_crtc_state *config;
813 /* global reset count when the last flip was submitted */
814 unsigned int reset_count;
816 /* Access to these should be protected by dev_priv->irq_lock. */
817 bool cpu_fifo_underrun_disabled;
818 bool pch_fifo_underrun_disabled;
820 /* per-pipe watermark state */
822 /* watermarks currently being used */
824 struct intel_pipe_wm ilk;
825 struct vlv_wm_state vlv;
826 struct g4x_wm_state g4x;
833 unsigned start_vbl_count;
834 ktime_t start_vbl_time;
835 int min_vbl, max_vbl;
839 /* scalers available on this crtc */
844 struct drm_plane base;
850 uint32_t frontbuffer_bit;
853 u32 base, cntl, size;
857 * NOTE: Do not place new plane state fields here (e.g., when adding
858 * new plane properties). New runtime state should now be placed in
859 * the intel_plane_state structure and accessed via plane_state.
862 void (*update_plane)(struct intel_plane *plane,
863 const struct intel_crtc_state *crtc_state,
864 const struct intel_plane_state *plane_state);
865 void (*disable_plane)(struct intel_plane *plane,
866 struct intel_crtc *crtc);
867 int (*check_plane)(struct intel_plane *plane,
868 struct intel_crtc_state *crtc_state,
869 struct intel_plane_state *state);
872 struct intel_watermark_params {
880 struct cxsr_latency {
886 u16 display_hpll_disable;
888 u16 cursor_hpll_disable;
891 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
892 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
893 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
894 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
895 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
896 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
897 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
898 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
899 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
905 enum drm_dp_dual_mode_type type;
910 bool rgb_quant_range_selectable;
911 struct intel_connector *attached_connector;
912 void (*write_infoframe)(struct drm_encoder *encoder,
913 const struct intel_crtc_state *crtc_state,
914 enum hdmi_infoframe_type type,
915 const void *frame, ssize_t len);
916 void (*set_infoframes)(struct drm_encoder *encoder,
918 const struct intel_crtc_state *crtc_state,
919 const struct drm_connector_state *conn_state);
920 bool (*infoframe_enabled)(struct drm_encoder *encoder,
921 const struct intel_crtc_state *pipe_config);
924 struct intel_dp_mst_encoder;
925 #define DP_MAX_DOWNSTREAM_PORTS 0x10
929 * When platform provides two set of M_N registers for dp, we can
930 * program them and switch between them incase of DRRS.
931 * But When only one such register is provided, we have to program the
932 * required divider value on that registers itself based on the DRRS state.
934 * M1_N1 : Program dp_m_n on M1_N1 registers
935 * dp_m2_n2 on M2_N2 registers (If supported)
937 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
938 * M2_N2 registers are not supported
942 /* Sets the m1_n1 and m2_n2 */
947 struct intel_dp_desc {
955 struct intel_dp_compliance_data {
957 uint8_t video_pattern;
958 uint16_t hdisplay, vdisplay;
962 struct intel_dp_compliance {
963 unsigned long test_type;
964 struct intel_dp_compliance_data test_data;
971 i915_reg_t output_reg;
972 i915_reg_t aux_ch_ctl_reg;
973 i915_reg_t aux_ch_data_reg[5];
981 bool channel_eq_status;
982 bool reset_link_params;
983 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
984 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
985 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
986 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
988 int num_source_rates;
989 const int *source_rates;
990 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
992 int sink_rates[DP_MAX_SUPPORTED_RATES];
993 bool use_rate_select;
994 /* intersection of source and sink rates */
995 int num_common_rates;
996 int common_rates[DP_MAX_SUPPORTED_RATES];
997 /* Max lane count for the current link */
998 int max_link_lane_count;
999 /* Max rate for the current link */
1001 /* sink or branch descriptor */
1002 struct intel_dp_desc desc;
1003 struct drm_dp_aux aux;
1004 enum intel_display_power_domain aux_power_domain;
1005 uint8_t train_set[4];
1006 int panel_power_up_delay;
1007 int panel_power_down_delay;
1008 int panel_power_cycle_delay;
1009 int backlight_on_delay;
1010 int backlight_off_delay;
1011 struct delayed_work panel_vdd_work;
1012 bool want_panel_vdd;
1013 unsigned long last_power_on;
1014 unsigned long last_backlight_off;
1015 ktime_t panel_power_off_time;
1017 struct notifier_block edp_notifier;
1020 * Pipe whose power sequencer is currently locked into
1021 * this port. Only relevant on VLV/CHV.
1025 * Pipe currently driving the port. Used for preventing
1026 * the use of the PPS for any pipe currentrly driving
1027 * external DP as that will mess things up on VLV.
1029 enum pipe active_pipe;
1031 * Set if the sequencer may be reset due to a power transition,
1032 * requiring a reinitialization. Only relevant on BXT.
1035 struct edp_power_seq pps_delays;
1037 bool can_mst; /* this port supports mst */
1039 int active_mst_links;
1040 /* connector directly attached - won't be use for modeset in mst world */
1041 struct intel_connector *attached_connector;
1043 /* mst connector list */
1044 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1045 struct drm_dp_mst_topology_mgr mst_mgr;
1047 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1049 * This function returns the value we have to program the AUX_CTL
1050 * register with to kick off an AUX transaction.
1052 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1055 uint32_t aux_clock_divider);
1057 /* This is called before a link training is starterd */
1058 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1060 /* Displayport compliance testing */
1061 struct intel_dp_compliance compliance;
1064 struct intel_lspcon {
1066 enum drm_lspcon_mode mode;
1069 struct intel_digital_port {
1070 struct intel_encoder base;
1072 u32 saved_port_bits;
1074 struct intel_hdmi hdmi;
1075 struct intel_lspcon lspcon;
1076 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1077 bool release_cl2_override;
1079 enum intel_display_power_domain ddi_io_power_domain;
1082 struct intel_dp_mst_encoder {
1083 struct intel_encoder base;
1085 struct intel_digital_port *primary;
1086 struct intel_connector *connector;
1089 static inline enum dpio_channel
1090 vlv_dport_to_channel(struct intel_digital_port *dport)
1092 switch (dport->port) {
1103 static inline enum dpio_phy
1104 vlv_dport_to_phy(struct intel_digital_port *dport)
1106 switch (dport->port) {
1117 static inline enum dpio_channel
1118 vlv_pipe_to_channel(enum pipe pipe)
1131 static inline struct intel_crtc *
1132 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1134 return dev_priv->pipe_to_crtc_mapping[pipe];
1137 static inline struct intel_crtc *
1138 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1140 return dev_priv->plane_to_crtc_mapping[plane];
1143 struct intel_flip_work {
1144 struct work_struct unpin_work;
1145 struct work_struct mmio_work;
1147 struct drm_crtc *crtc;
1148 struct i915_vma *old_vma;
1149 struct drm_framebuffer *old_fb;
1150 struct drm_i915_gem_object *pending_flip_obj;
1151 struct drm_pending_vblank_event *event;
1155 struct drm_i915_gem_request *flip_queued_req;
1156 u32 flip_queued_vblank;
1157 u32 flip_ready_vblank;
1158 unsigned int rotation;
1161 struct intel_load_detect_pipe {
1162 struct drm_atomic_state *restore_state;
1165 static inline struct intel_encoder *
1166 intel_attached_encoder(struct drm_connector *connector)
1168 return to_intel_connector(connector)->encoder;
1171 static inline struct intel_digital_port *
1172 enc_to_dig_port(struct drm_encoder *encoder)
1174 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1176 switch (intel_encoder->type) {
1177 case INTEL_OUTPUT_UNKNOWN:
1178 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1179 case INTEL_OUTPUT_DP:
1180 case INTEL_OUTPUT_EDP:
1181 case INTEL_OUTPUT_HDMI:
1182 return container_of(encoder, struct intel_digital_port,
1189 static inline struct intel_dp_mst_encoder *
1190 enc_to_mst(struct drm_encoder *encoder)
1192 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1195 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1197 return &enc_to_dig_port(encoder)->dp;
1200 static inline struct intel_digital_port *
1201 dp_to_dig_port(struct intel_dp *intel_dp)
1203 return container_of(intel_dp, struct intel_digital_port, dp);
1206 static inline struct intel_lspcon *
1207 dp_to_lspcon(struct intel_dp *intel_dp)
1209 return &dp_to_dig_port(intel_dp)->lspcon;
1212 static inline struct intel_digital_port *
1213 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1215 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1218 /* intel_fifo_underrun.c */
1219 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool enable);
1221 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1222 enum transcoder pch_transcoder,
1224 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1226 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1227 enum transcoder pch_transcoder);
1228 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1229 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1232 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1233 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1234 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1235 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1236 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1237 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1238 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1239 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1240 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1241 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1243 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1246 return mask & ~i915->rps.pm_intrmsk_mbz;
1249 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1250 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1251 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1254 * We only use drm_irq_uninstall() at unload and VT switch, so
1255 * this is the only thing we need to check.
1257 return dev_priv->pm.irqs_enabled;
1260 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1261 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1262 unsigned int pipe_mask);
1263 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1264 unsigned int pipe_mask);
1265 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1266 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1267 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1270 void intel_crt_init(struct drm_i915_private *dev_priv);
1271 void intel_crt_reset(struct drm_encoder *encoder);
1274 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1275 struct intel_crtc_state *old_crtc_state,
1276 struct drm_connector_state *old_conn_state);
1277 void hsw_fdi_link_train(struct intel_crtc *crtc,
1278 const struct intel_crtc_state *crtc_state);
1279 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1280 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1281 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1282 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1283 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1284 enum transcoder cpu_transcoder);
1285 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1286 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1287 struct intel_encoder *
1288 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1289 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1290 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1291 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1292 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1293 struct intel_crtc *intel_crtc);
1294 void intel_ddi_get_config(struct intel_encoder *encoder,
1295 struct intel_crtc_state *pipe_config);
1297 void intel_ddi_clock_get(struct intel_encoder *encoder,
1298 struct intel_crtc_state *pipe_config);
1299 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1301 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1302 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1304 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1305 int plane, unsigned int height);
1308 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1309 void intel_audio_codec_enable(struct intel_encoder *encoder,
1310 const struct intel_crtc_state *crtc_state,
1311 const struct drm_connector_state *conn_state);
1312 void intel_audio_codec_disable(struct intel_encoder *encoder);
1313 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1314 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1315 void intel_audio_init(struct drm_i915_private *dev_priv);
1316 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1319 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1320 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1321 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1322 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1323 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1324 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1325 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1326 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1327 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1328 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1329 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1330 const struct intel_cdclk_state *b);
1331 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1332 const struct intel_cdclk_state *cdclk_state);
1334 /* intel_display.c */
1335 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1336 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1337 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1338 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1339 const char *name, u32 reg, int ref_freq);
1340 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1341 const char *name, u32 reg);
1342 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1343 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1344 extern const struct drm_plane_funcs intel_plane_funcs;
1345 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1346 unsigned int intel_fb_xy_to_linear(int x, int y,
1347 const struct intel_plane_state *state,
1349 void intel_add_fb_offsets(int *x, int *y,
1350 const struct intel_plane_state *state, int plane);
1351 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1352 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1353 void intel_mark_busy(struct drm_i915_private *dev_priv);
1354 void intel_mark_idle(struct drm_i915_private *dev_priv);
1355 int intel_display_suspend(struct drm_device *dev);
1356 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1357 void intel_encoder_destroy(struct drm_encoder *encoder);
1358 int intel_connector_init(struct intel_connector *);
1359 struct intel_connector *intel_connector_alloc(void);
1360 bool intel_connector_get_hw_state(struct intel_connector *connector);
1361 void intel_connector_attach_encoder(struct intel_connector *connector,
1362 struct intel_encoder *encoder);
1363 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1364 struct drm_crtc *crtc);
1365 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1366 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1367 struct drm_file *file_priv);
1368 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1371 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1372 enum intel_output_type type)
1374 return crtc_state->output_types & (1 << type);
1377 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1379 return crtc_state->output_types &
1380 ((1 << INTEL_OUTPUT_DP) |
1381 (1 << INTEL_OUTPUT_DP_MST) |
1382 (1 << INTEL_OUTPUT_EDP));
1385 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1387 drm_wait_one_vblank(&dev_priv->drm, pipe);
1390 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1392 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1395 intel_wait_for_vblank(dev_priv, pipe);
1398 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1400 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1401 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1402 struct intel_digital_port *dport,
1403 unsigned int expected_mask);
1404 int intel_get_load_detect_pipe(struct drm_connector *connector,
1405 struct drm_display_mode *mode,
1406 struct intel_load_detect_pipe *old,
1407 struct drm_modeset_acquire_ctx *ctx);
1408 void intel_release_load_detect_pipe(struct drm_connector *connector,
1409 struct intel_load_detect_pipe *old,
1410 struct drm_modeset_acquire_ctx *ctx);
1412 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1413 void intel_unpin_fb_vma(struct i915_vma *vma);
1414 struct drm_framebuffer *
1415 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1416 struct drm_mode_fb_cmd2 *mode_cmd);
1417 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1418 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1419 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1420 int intel_prepare_plane_fb(struct drm_plane *plane,
1421 struct drm_plane_state *new_state);
1422 void intel_cleanup_plane_fb(struct drm_plane *plane,
1423 struct drm_plane_state *old_state);
1424 int intel_plane_atomic_get_property(struct drm_plane *plane,
1425 const struct drm_plane_state *state,
1426 struct drm_property *property,
1428 int intel_plane_atomic_set_property(struct drm_plane *plane,
1429 struct drm_plane_state *state,
1430 struct drm_property *property,
1432 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1433 struct drm_plane_state *plane_state);
1435 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1438 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1439 const struct dpll *dpll);
1440 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1441 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1443 /* modesetting asserts */
1444 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1446 void assert_pll(struct drm_i915_private *dev_priv,
1447 enum pipe pipe, bool state);
1448 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1449 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1450 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1451 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1452 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1453 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, bool state);
1455 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1456 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1457 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1458 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1459 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1460 u32 intel_compute_tile_offset(int *x, int *y,
1461 const struct intel_plane_state *state, int plane);
1462 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1463 void intel_finish_reset(struct drm_i915_private *dev_priv);
1464 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1465 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1466 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1467 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1468 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1469 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1470 unsigned int skl_cdclk_get_vco(unsigned int freq);
1471 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1472 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1473 void intel_dp_get_m_n(struct intel_crtc *crtc,
1474 struct intel_crtc_state *pipe_config);
1475 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1476 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1477 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1478 struct dpll *best_clock);
1479 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1481 bool intel_crtc_active(struct intel_crtc *crtc);
1482 void hsw_enable_ips(struct intel_crtc *crtc);
1483 void hsw_disable_ips(struct intel_crtc *crtc);
1484 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1485 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1486 struct intel_crtc_state *pipe_config);
1488 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1489 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1491 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1493 return i915_ggtt_offset(state->vma);
1496 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1497 const struct intel_plane_state *plane_state);
1498 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1499 unsigned int rotation);
1500 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1501 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1504 void intel_csr_ucode_init(struct drm_i915_private *);
1505 void intel_csr_load_program(struct drm_i915_private *);
1506 void intel_csr_ucode_fini(struct drm_i915_private *);
1507 void intel_csr_ucode_suspend(struct drm_i915_private *);
1508 void intel_csr_ucode_resume(struct drm_i915_private *);
1511 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1513 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1514 struct intel_connector *intel_connector);
1515 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1516 int link_rate, uint8_t lane_count,
1518 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1519 int link_rate, uint8_t lane_count);
1520 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1521 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1522 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1523 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1524 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1525 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1526 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1527 bool intel_dp_compute_config(struct intel_encoder *encoder,
1528 struct intel_crtc_state *pipe_config,
1529 struct drm_connector_state *conn_state);
1530 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1531 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1533 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1534 const struct drm_connector_state *conn_state);
1535 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1536 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1537 void intel_edp_panel_on(struct intel_dp *intel_dp);
1538 void intel_edp_panel_off(struct intel_dp *intel_dp);
1539 void intel_dp_mst_suspend(struct drm_device *dev);
1540 void intel_dp_mst_resume(struct drm_device *dev);
1541 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1542 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1543 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1544 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1545 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1546 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1547 void intel_plane_destroy(struct drm_plane *plane);
1548 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1549 struct intel_crtc_state *crtc_state);
1550 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1551 struct intel_crtc_state *crtc_state);
1552 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1553 unsigned int frontbuffer_bits);
1554 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1555 unsigned int frontbuffer_bits);
1558 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1559 uint8_t dp_train_pat);
1561 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1562 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1564 intel_dp_voltage_max(struct intel_dp *intel_dp);
1566 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1567 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1568 uint8_t *link_bw, uint8_t *rate_select);
1569 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1571 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1573 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1575 return ~((1 << lane_count) - 1) & 0xf;
1578 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1579 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1580 struct intel_dp_desc *desc);
1581 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1582 int intel_dp_link_required(int pixel_clock, int bpp);
1583 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1584 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1585 struct intel_digital_port *port);
1587 /* intel_dp_aux_backlight.c */
1588 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1590 /* intel_dp_mst.c */
1591 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1592 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1594 void intel_dsi_init(struct drm_i915_private *dev_priv);
1596 /* intel_dsi_dcs_backlight.c */
1597 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1600 void intel_dvo_init(struct drm_i915_private *dev_priv);
1601 /* intel_hotplug.c */
1602 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1605 /* legacy fbdev emulation in intel_fbdev.c */
1606 #ifdef CONFIG_DRM_FBDEV_EMULATION
1607 extern int intel_fbdev_init(struct drm_device *dev);
1608 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1609 extern void intel_fbdev_fini(struct drm_device *dev);
1610 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1611 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1612 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1614 static inline int intel_fbdev_init(struct drm_device *dev)
1619 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1623 static inline void intel_fbdev_fini(struct drm_device *dev)
1627 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1631 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1635 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1641 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1642 struct drm_atomic_state *state);
1643 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1644 void intel_fbc_pre_update(struct intel_crtc *crtc,
1645 struct intel_crtc_state *crtc_state,
1646 struct intel_plane_state *plane_state);
1647 void intel_fbc_post_update(struct intel_crtc *crtc);
1648 void intel_fbc_init(struct drm_i915_private *dev_priv);
1649 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1650 void intel_fbc_enable(struct intel_crtc *crtc,
1651 struct intel_crtc_state *crtc_state,
1652 struct intel_plane_state *plane_state);
1653 void intel_fbc_disable(struct intel_crtc *crtc);
1654 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1655 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1656 unsigned int frontbuffer_bits,
1657 enum fb_op_origin origin);
1658 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1659 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1660 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1661 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1664 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1666 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1667 struct intel_connector *intel_connector);
1668 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1669 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1670 struct intel_crtc_state *pipe_config,
1671 struct drm_connector_state *conn_state);
1672 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1673 struct drm_connector *connector,
1674 bool high_tmds_clock_ratio,
1676 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1680 void intel_lvds_init(struct drm_i915_private *dev_priv);
1681 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1682 bool intel_is_dual_link_lvds(struct drm_device *dev);
1686 int intel_connector_update_modes(struct drm_connector *connector,
1688 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1689 void intel_attach_force_audio_property(struct drm_connector *connector);
1690 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1691 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1694 /* intel_overlay.c */
1695 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1696 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1697 int intel_overlay_switch_off(struct intel_overlay *overlay);
1698 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1699 struct drm_file *file_priv);
1700 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1701 struct drm_file *file_priv);
1702 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1706 int intel_panel_init(struct intel_panel *panel,
1707 struct drm_display_mode *fixed_mode,
1708 struct drm_display_mode *downclock_mode);
1709 void intel_panel_fini(struct intel_panel *panel);
1710 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1711 struct drm_display_mode *adjusted_mode);
1712 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1713 struct intel_crtc_state *pipe_config,
1715 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1716 struct intel_crtc_state *pipe_config,
1718 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1719 u32 level, u32 max);
1720 int intel_panel_setup_backlight(struct drm_connector *connector,
1722 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1723 const struct drm_connector_state *conn_state);
1724 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1725 void intel_panel_destroy_backlight(struct drm_connector *connector);
1726 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1727 extern struct drm_display_mode *intel_find_panel_downclock(
1728 struct drm_i915_private *dev_priv,
1729 struct drm_display_mode *fixed_mode,
1730 struct drm_connector *connector);
1732 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1733 int intel_backlight_device_register(struct intel_connector *connector);
1734 void intel_backlight_device_unregister(struct intel_connector *connector);
1735 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1736 static int intel_backlight_device_register(struct intel_connector *connector)
1740 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1743 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1747 void intel_psr_enable(struct intel_dp *intel_dp);
1748 void intel_psr_disable(struct intel_dp *intel_dp);
1749 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1750 unsigned frontbuffer_bits);
1751 void intel_psr_flush(struct drm_i915_private *dev_priv,
1752 unsigned frontbuffer_bits,
1753 enum fb_op_origin origin);
1754 void intel_psr_init(struct drm_i915_private *dev_priv);
1755 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1756 unsigned frontbuffer_bits);
1758 /* intel_runtime_pm.c */
1759 int intel_power_domains_init(struct drm_i915_private *);
1760 void intel_power_domains_fini(struct drm_i915_private *);
1761 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1762 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1763 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1764 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1765 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1766 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1768 intel_display_power_domain_str(enum intel_display_power_domain domain);
1770 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1771 enum intel_display_power_domain domain);
1772 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1773 enum intel_display_power_domain domain);
1774 void intel_display_power_get(struct drm_i915_private *dev_priv,
1775 enum intel_display_power_domain domain);
1776 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1777 enum intel_display_power_domain domain);
1778 void intel_display_power_put(struct drm_i915_private *dev_priv,
1779 enum intel_display_power_domain domain);
1782 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1784 WARN_ONCE(dev_priv->pm.suspended,
1785 "Device suspended during HW access\n");
1789 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1791 assert_rpm_device_not_suspended(dev_priv);
1792 WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1793 "RPM wakelock ref not held during HW access");
1797 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1798 * @dev_priv: i915 device instance
1800 * This function disable asserts that check if we hold an RPM wakelock
1801 * reference, while keeping the device-not-suspended checks still enabled.
1802 * It's meant to be used only in special circumstances where our rule about
1803 * the wakelock refcount wrt. the device power state doesn't hold. According
1804 * to this rule at any point where we access the HW or want to keep the HW in
1805 * an active state we must hold an RPM wakelock reference acquired via one of
1806 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1807 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1808 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1809 * users should avoid using this function.
1811 * Any calls to this function must have a symmetric call to
1812 * enable_rpm_wakeref_asserts().
1815 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1817 atomic_inc(&dev_priv->pm.wakeref_count);
1821 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1822 * @dev_priv: i915 device instance
1824 * This function re-enables the RPM assert checks after disabling them with
1825 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1826 * circumstances otherwise its use should be avoided.
1828 * Any calls to this function must have a symmetric call to
1829 * disable_rpm_wakeref_asserts().
1832 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1834 atomic_dec(&dev_priv->pm.wakeref_count);
1837 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1838 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1839 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1840 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1842 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1844 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1845 bool override, unsigned int mask);
1846 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1847 enum dpio_channel ch, bool override);
1851 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1852 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1853 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1854 void intel_update_watermarks(struct intel_crtc *crtc);
1855 void intel_init_pm(struct drm_i915_private *dev_priv);
1856 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1857 void intel_pm_setup(struct drm_i915_private *dev_priv);
1858 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1859 void intel_gpu_ips_teardown(void);
1860 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1861 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1862 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1863 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1864 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1865 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1866 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1867 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1868 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1869 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1870 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1871 struct intel_rps_client *rps,
1872 unsigned long submitted);
1873 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1874 void g4x_wm_get_hw_state(struct drm_device *dev);
1875 void vlv_wm_get_hw_state(struct drm_device *dev);
1876 void ilk_wm_get_hw_state(struct drm_device *dev);
1877 void skl_wm_get_hw_state(struct drm_device *dev);
1878 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1879 struct skl_ddb_allocation *ddb /* out */);
1880 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1881 struct skl_pipe_wm *out);
1882 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1883 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1884 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1885 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1886 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1887 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1888 const struct skl_wm_level *l2);
1889 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1890 const struct skl_ddb_entry *ddb,
1892 bool ilk_disable_lp_wm(struct drm_device *dev);
1893 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1894 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
1895 struct intel_crtc_state *cstate);
1896 static inline int intel_enable_rc6(void)
1898 return i915.enable_rc6;
1902 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1903 i915_reg_t reg, enum port port);
1906 /* intel_sprite.c */
1907 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1909 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1910 enum pipe pipe, int plane);
1911 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1912 struct drm_file *file_priv);
1913 void intel_pipe_update_start(struct intel_crtc *crtc);
1914 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1917 void intel_tv_init(struct drm_i915_private *dev_priv);
1919 /* intel_atomic.c */
1920 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
1921 const struct drm_connector_state *state,
1922 struct drm_property *property,
1924 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
1925 struct drm_connector_state *state,
1926 struct drm_property *property,
1928 int intel_digital_connector_atomic_check(struct drm_connector *conn,
1929 struct drm_connector_state *new_state);
1930 struct drm_connector_state *
1931 intel_digital_connector_duplicate_state(struct drm_connector *connector);
1933 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1934 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1935 struct drm_crtc_state *state);
1936 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1937 void intel_atomic_state_clear(struct drm_atomic_state *);
1939 static inline struct intel_crtc_state *
1940 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1941 struct intel_crtc *crtc)
1943 struct drm_crtc_state *crtc_state;
1944 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1945 if (IS_ERR(crtc_state))
1946 return ERR_CAST(crtc_state);
1948 return to_intel_crtc_state(crtc_state);
1951 static inline struct intel_crtc_state *
1952 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1953 struct intel_crtc *crtc)
1955 struct drm_crtc_state *crtc_state;
1957 crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1960 return to_intel_crtc_state(crtc_state);
1965 static inline struct intel_plane_state *
1966 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1967 struct intel_plane *plane)
1969 struct drm_plane_state *plane_state;
1971 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1973 return to_intel_plane_state(plane_state);
1976 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1977 struct intel_crtc *intel_crtc,
1978 struct intel_crtc_state *crtc_state);
1980 /* intel_atomic_plane.c */
1981 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1982 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1983 void intel_plane_destroy_state(struct drm_plane *plane,
1984 struct drm_plane_state *state);
1985 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1986 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1987 struct intel_plane_state *intel_state);
1990 void intel_color_init(struct drm_crtc *crtc);
1991 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1992 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1993 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1995 /* intel_lspcon.c */
1996 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1997 void lspcon_resume(struct intel_lspcon *lspcon);
1998 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2000 /* intel_pipe_crc.c */
2001 int intel_pipe_crc_create(struct drm_minor *minor);
2002 #ifdef CONFIG_DEBUG_FS
2003 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2004 size_t *values_cnt);
2006 #define intel_crtc_set_crc_source NULL
2008 extern const struct file_operations i915_display_crc_ctl_fops;
2009 #endif /* __INTEL_DRV_H__ */