drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_encoder.h>
  36 #include <drm/drm_fb_helper.h>
  37 #include <drm/drm_dp_dual_mode_helper.h>
  38 #include <drm/drm_dp_mst_helper.h>
  39 #include <drm/drm_rect.h>
  40 #include <drm/drm_atomic.h>
  41
  42 /**
  43  * _wait_for - magic (register) wait macro
  44  *
  45  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46  * contexts. Note that it's important that we check the condition again after
  47  * having timed out, since the timeout could be due to preemption or similar and
  48  * we've never had a chance to check the condition before the timeout.
  49  *
  50  * TODO: When modesetting has fully transitioned to atomic, the below
  51  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  52  * added.
  53  */
  54 #define _wait_for(COND, US, W) ({ \
  55         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  56         int ret__;                                                      \
  57         for (;;) {                                                      \
  58                 bool expired__ = time_after(jiffies, timeout__);        \
  59                 if (COND) {                                             \
  60                         ret__ = 0;                                      \
  61                         break;                                          \
  62                 }                                                       \
  63                 if (expired__) {                                        \
  64                         ret__ = -ETIMEDOUT;                             \
  65                         break;                                          \
  66                 }                                                       \
  67                 if ((W) && drm_can_sleep()) {                           \
  68                         usleep_range((W), (W)*2);                       \
  69                 } else {                                                \
  70                         cpu_relax();                                    \
  71                 }                                                       \
  72         }                                                               \
  73         ret__;                                                          \
  74 })
  75
  76 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  77
  78 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  79 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  80 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  81 #else
  82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  83 #endif
  84
  85 #define _wait_for_atomic(COND, US, ATOMIC) \
  86 ({ \
  87         int cpu, ret, timeout = (US) * 1000; \
  88         u64 base; \
  89         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  90         BUILD_BUG_ON((US) > 50000); \
  91         if (!(ATOMIC)) { \
  92                 preempt_disable(); \
  93                 cpu = smp_processor_id(); \
  94         } \
  95         base = local_clock(); \
  96         for (;;) { \
  97                 u64 now = local_clock(); \
  98                 if (!(ATOMIC)) \
  99                         preempt_enable(); \
 100                 if (COND) { \
 101                         ret = 0; \
 102                         break; \
 103                 } \
 104                 if (now - base >= timeout) { \
 105                         ret = -ETIMEDOUT; \
 106                         break; \
 107                 } \
 108                 cpu_relax(); \
 109                 if (!(ATOMIC)) { \
 110                         preempt_disable(); \
 111                         if (unlikely(cpu != smp_processor_id())) { \
 112                                 timeout -= now - base; \
 113                                 cpu = smp_processor_id(); \
 114                                 base = local_clock(); \
 115                         } \
 116                 } \
 117         } \
 118         ret; \
 119 })
 120
 121 #define wait_for_us(COND, US) \
 122 ({ \
 123         int ret__; \
 124         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 125         if ((US) > 10) \
 126                 ret__ = _wait_for((COND), (US), 10); \
 127         else \
 128                 ret__ = _wait_for_atomic((COND), (US), 0); \
 129         ret__; \
 130 })
 131
 132 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 133 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 134
 135 #define KHz(x) (1000 * (x))
 136 #define MHz(x) KHz(1000 * (x))
 137
 138 /*
 139  * Display related stuff
 140  */
 141
 142 /* store information about an Ixxx DVO */
 143 /* The i830->i865 use multiple DVOs with multiple i2cs */
 144 /* the i915, i945 have a single sDVO i2c bus - which is different */
 145 #define MAX_OUTPUTS 6
 146 /* maximum connectors per crtcs in the mode set */
 147
 148 /* Maximum cursor sizes */
 149 #define GEN2_CURSOR_WIDTH 64
 150 #define GEN2_CURSOR_HEIGHT 64
 151 #define MAX_CURSOR_WIDTH 256
 152 #define MAX_CURSOR_HEIGHT 256
 153
 154 #define INTEL_I2C_BUS_DVO 1
 155 #define INTEL_I2C_BUS_SDVO 2
 156
 157 /* these are outputs from the chip - integrated only
 158    external chips are via DVO or SDVO output */
 159 enum intel_output_type {
 160         INTEL_OUTPUT_UNUSED = 0,
 161         INTEL_OUTPUT_ANALOG = 1,
 162         INTEL_OUTPUT_DVO = 2,
 163         INTEL_OUTPUT_SDVO = 3,
 164         INTEL_OUTPUT_LVDS = 4,
 165         INTEL_OUTPUT_TVOUT = 5,
 166         INTEL_OUTPUT_HDMI = 6,
 167         INTEL_OUTPUT_DP = 7,
 168         INTEL_OUTPUT_EDP = 8,
 169         INTEL_OUTPUT_DSI = 9,
 170         INTEL_OUTPUT_UNKNOWN = 10,
 171         INTEL_OUTPUT_DP_MST = 11,
 172 };
 173
 174 #define INTEL_DVO_CHIP_NONE 0
 175 #define INTEL_DVO_CHIP_LVDS 1
 176 #define INTEL_DVO_CHIP_TMDS 2
 177 #define INTEL_DVO_CHIP_TVOUT 4
 178
 179 #define INTEL_DSI_VIDEO_MODE    0
 180 #define INTEL_DSI_COMMAND_MODE  1
 181
 182 struct intel_framebuffer {
 183         struct drm_framebuffer base;
 184         struct drm_i915_gem_object *obj;
 185         struct intel_rotation_info rot_info;
 186
 187         /* for each plane in the normal GTT view */
 188         struct {
 189                 unsigned int x, y;
 190         } normal[2];
 191         /* for each plane in the rotated GTT view */
 192         struct {
 193                 unsigned int x, y;
 194                 unsigned int pitch; /* pixels */
 195         } rotated[2];
 196 };
 197
 198 struct intel_fbdev {
 199         struct drm_fb_helper helper;
 200         struct intel_framebuffer *fb;
 201         struct i915_vma *vma;
 202         async_cookie_t cookie;
 203         int preferred_bpp;
 204 };
 205
 206 struct intel_encoder {
 207         struct drm_encoder base;
 208
 209         enum intel_output_type type;
 210         enum port port;
 211         unsigned int cloneable;
 212         void (*hot_plug)(struct intel_encoder *);
 213         bool (*compute_config)(struct intel_encoder *,
 214                                struct intel_crtc_state *,
 215                                struct drm_connector_state *);
 216         void (*pre_pll_enable)(struct intel_encoder *,
 217                                struct intel_crtc_state *,
 218                                struct drm_connector_state *);
 219         void (*pre_enable)(struct intel_encoder *,
 220                            struct intel_crtc_state *,
 221                            struct drm_connector_state *);
 222         void (*enable)(struct intel_encoder *,
 223                        struct intel_crtc_state *,
 224                        struct drm_connector_state *);
 225         void (*disable)(struct intel_encoder *,
 226                         struct intel_crtc_state *,
 227                         struct drm_connector_state *);
 228         void (*post_disable)(struct intel_encoder *,
 229                              struct intel_crtc_state *,
 230                              struct drm_connector_state *);
 231         void (*post_pll_disable)(struct intel_encoder *,
 232                                  struct intel_crtc_state *,
 233                                  struct drm_connector_state *);
 234         /* Read out the current hw state of this connector, returning true if
 235          * the encoder is active. If the encoder is enabled it also set the pipe
 236          * it is connected to in the pipe parameter. */
 237         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 238         /* Reconstructs the equivalent mode flags for the current hardware
 239          * state. This must be called _after_ display->get_pipe_config has
 240          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 241          * be set correctly before calling this function. */
 242         void (*get_config)(struct intel_encoder *,
 243                            struct intel_crtc_state *pipe_config);
 244         /* Returns a mask of power domains that need to be referenced as part
 245          * of the hardware state readout code. */
 246         u64 (*get_power_domains)(struct intel_encoder *encoder);
 247         /*
 248          * Called during system suspend after all pending requests for the
 249          * encoder are flushed (for example for DP AUX transactions) and
 250          * device interrupts are disabled.
 251          */
 252         void (*suspend)(struct intel_encoder *);
 253         int crtc_mask;
 254         enum hpd_pin hpd_pin;
 255         enum intel_display_power_domain power_domain;
 256         /* for communication with audio component; protected by av_mutex */
 257         const struct drm_connector *audio_connector;
 258 };
 259
 260 struct intel_panel {
 261         struct drm_display_mode *fixed_mode;
 262         struct drm_display_mode *downclock_mode;
 263         int fitting_mode;
 264
 265         /* backlight */
 266         struct {
 267                 bool present;
 268                 u32 level;
 269                 u32 min;
 270                 u32 max;
 271                 bool enabled;
 272                 bool combination_mode;  /* gen 2/4 only */
 273                 bool active_low_pwm;
 274                 bool alternate_pwm_increment;   /* lpt+ */
 275
 276                 /* PWM chip */
 277                 bool util_pin_active_low;       /* bxt+ */
 278                 u8 controller;          /* bxt+ only */
 279                 struct pwm_device *pwm;
 280
 281                 struct backlight_device *device;
 282
 283                 /* Connector and platform specific backlight functions */
 284                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 285                 uint32_t (*get)(struct intel_connector *connector);
 286                 void (*set)(struct intel_connector *connector, uint32_t level);
 287                 void (*disable)(struct intel_connector *connector);
 288                 void (*enable)(struct intel_connector *connector);
 289                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 290                                       uint32_t hz);
 291                 void (*power)(struct intel_connector *, bool enable);
 292         } backlight;
 293 };
 294
 295 struct intel_connector {
 296         struct drm_connector base;
 297         /*
 298          * The fixed encoder this connector is connected to.
 299          */
 300         struct intel_encoder *encoder;
 301
 302         /* ACPI device id for ACPI and driver cooperation */
 303         u32 acpi_device_id;
 304
 305         /* Reads out the current hw, returning true if the connector is enabled
 306          * and active (i.e. dpms ON state). */
 307         bool (*get_hw_state)(struct intel_connector *);
 308
 309         /* Panel info for eDP and LVDS */
 310         struct intel_panel panel;
 311
 312         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 313         struct edid *edid;
 314         struct edid *detect_edid;
 315
 316         /* since POLL and HPD connectors may use the same HPD line keep the native
 317            state of connector->polled in case hotplug storm detection changes it */
 318         u8 polled;
 319
 320         void *port; /* store this opaque as its illegal to dereference it */
 321
 322         struct intel_dp *mst_port;
 323 };
 324
 325 struct dpll {
 326         /* given values */
 327         int n;
 328         int m1, m2;
 329         int p1, p2;
 330         /* derived values */
 331         int     dot;
 332         int     vco;
 333         int     m;
 334         int     p;
 335 };
 336
 337 struct intel_atomic_state {
 338         struct drm_atomic_state base;
 339
 340         struct {
 341                 /*
 342                  * Logical state of cdclk (used for all scaling, watermark,
 343                  * etc. calculations and checks). This is computed as if all
 344                  * enabled crtcs were active.
 345                  */
 346                 struct intel_cdclk_state logical;
 347
 348                 /*
 349                  * Actual state of cdclk, can be different from the logical
 350                  * state only when all crtc's are DPMS off.
 351                  */
 352                 struct intel_cdclk_state actual;
 353         } cdclk;
 354
 355         bool dpll_set, modeset;
 356
 357         /*
 358          * Does this transaction change the pipes that are active?  This mask
 359          * tracks which CRTC's have changed their active state at the end of
 360          * the transaction (not counting the temporary disable during modesets).
 361          * This mask should only be non-zero when intel_state->modeset is true,
 362          * but the converse is not necessarily true; simply changing a mode may
 363          * not flip the final active status of any CRTC's
 364          */
 365         unsigned int active_pipe_changes;
 366
 367         unsigned int active_crtcs;
 368         unsigned int min_pixclk[I915_MAX_PIPES];
 369
 370         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 371
 372         /*
 373          * Current watermarks can't be trusted during hardware readout, so
 374          * don't bother calculating intermediate watermarks.
 375          */
 376         bool skip_intermediate_wm;
 377
 378         /* Gen9+ only */
 379         struct skl_wm_values wm_results;
 380
 381         struct i915_sw_fence commit_ready;
 382
 383         struct llist_node freed;
 384 };
 385
 386 struct intel_plane_state {
 387         struct drm_plane_state base;
 388         struct drm_rect clip;
 389         struct i915_vma *vma;
 390
 391         struct {
 392                 u32 offset;
 393                 int x, y;
 394         } main;
 395         struct {
 396                 u32 offset;
 397                 int x, y;
 398         } aux;
 399
 400         /*
 401          * scaler_id
 402          *    = -1 : not using a scaler
 403          *    >=  0 : using a scalers
 404          *
 405          * plane requiring a scaler:
 406          *   - During check_plane, its bit is set in
 407          *     crtc_state->scaler_state.scaler_users by calling helper function
 408          *     update_scaler_plane.
 409          *   - scaler_id indicates the scaler it got assigned.
 410          *
 411          * plane doesn't require a scaler:
 412          *   - this can happen when scaling is no more required or plane simply
 413          *     got disabled.
 414          *   - During check_plane, corresponding bit is reset in
 415          *     crtc_state->scaler_state.scaler_users by calling helper function
 416          *     update_scaler_plane.
 417          */
 418         int scaler_id;
 419
 420         struct drm_intel_sprite_colorkey ckey;
 421 };
 422
 423 struct intel_initial_plane_config {
 424         struct intel_framebuffer *fb;
 425         unsigned int tiling;
 426         int size;
 427         u32 base;
 428 };
 429
 430 #define SKL_MIN_SRC_W 8
 431 #define SKL_MAX_SRC_W 4096
 432 #define SKL_MIN_SRC_H 8
 433 #define SKL_MAX_SRC_H 4096
 434 #define SKL_MIN_DST_W 8
 435 #define SKL_MAX_DST_W 4096
 436 #define SKL_MIN_DST_H 8
 437 #define SKL_MAX_DST_H 4096
 438
 439 struct intel_scaler {
 440         int in_use;
 441         uint32_t mode;
 442 };
 443
 444 struct intel_crtc_scaler_state {
 445 #define SKL_NUM_SCALERS 2
 446         struct intel_scaler scalers[SKL_NUM_SCALERS];
 447
 448         /*
 449          * scaler_users: keeps track of users requesting scalers on this crtc.
 450          *
 451          *     If a bit is set, a user is using a scaler.
 452          *     Here user can be a plane or crtc as defined below:
 453          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 454          *       bit 31    - crtc
 455          *
 456          * Instead of creating a new index to cover planes and crtc, using
 457          * existing drm_plane_index for planes which is well less than 31
 458          * planes and bit 31 for crtc. This should be fine to cover all
 459          * our platforms.
 460          *
 461          * intel_atomic_setup_scalers will setup available scalers to users
 462          * requesting scalers. It will gracefully fail if request exceeds
 463          * avilability.
 464          */
 465 #define SKL_CRTC_INDEX 31
 466         unsigned scaler_users;
 467
 468         /* scaler used by crtc for panel fitting purpose */
 469         int scaler_id;
 470 };
 471
 472 /* drm_mode->private_flags */
 473 #define I915_MODE_FLAG_INHERITED 1
 474
 475 struct intel_pipe_wm {
 476         struct intel_wm_level wm[5];
 477         struct intel_wm_level raw_wm[5];
 478         uint32_t linetime;
 479         bool fbc_wm_enabled;
 480         bool pipe_enabled;
 481         bool sprites_enabled;
 482         bool sprites_scaled;
 483 };
 484
 485 struct skl_plane_wm {
 486         struct skl_wm_level wm[8];
 487         struct skl_wm_level trans_wm;
 488 };
 489
 490 struct skl_pipe_wm {
 491         struct skl_plane_wm planes[I915_MAX_PLANES];
 492         uint32_t linetime;
 493 };
 494
 495 enum vlv_wm_level {
 496         VLV_WM_LEVEL_PM2,
 497         VLV_WM_LEVEL_PM5,
 498         VLV_WM_LEVEL_DDR_DVFS,
 499         NUM_VLV_WM_LEVELS,
 500 };
 501
 502 struct vlv_wm_state {
 503         struct vlv_pipe_wm wm[NUM_VLV_WM_LEVELS];
 504         struct vlv_sr_wm sr[NUM_VLV_WM_LEVELS];
 505         uint8_t num_levels;
 506         bool cxsr;
 507 };
 508
 509 struct vlv_fifo_state {
 510         u16 plane[I915_MAX_PLANES];
 511 };
 512
 513 struct intel_crtc_wm_state {
 514         union {
 515                 struct {
 516                         /*
 517                          * Intermediate watermarks; these can be
 518                          * programmed immediately since they satisfy
 519                          * both the current configuration we're
 520                          * switching away from and the new
 521                          * configuration we're switching to.
 522                          */
 523                         struct intel_pipe_wm intermediate;
 524
 525                         /*
 526                          * Optimal watermarks, programmed post-vblank
 527                          * when this state is committed.
 528                          */
 529                         struct intel_pipe_wm optimal;
 530                 } ilk;
 531
 532                 struct {
 533                         /* gen9+ only needs 1-step wm programming */
 534                         struct skl_pipe_wm optimal;
 535                         struct skl_ddb_entry ddb;
 536                 } skl;
 537
 538                 struct {
 539                         /* "raw" watermarks (not inverted) */
 540                         struct vlv_pipe_wm raw[NUM_VLV_WM_LEVELS];
 541                         /* optimal watermarks (inverted) */
 542                         struct vlv_wm_state optimal;
 543                         /* display FIFO split */
 544                         struct vlv_fifo_state fifo_state;
 545                 } vlv;
 546         };
 547
 548         /*
 549          * Platforms with two-step watermark programming will need to
 550          * update watermark programming post-vblank to switch from the
 551          * safe intermediate watermarks to the optimal final
 552          * watermarks.
 553          */
 554         bool need_postvbl_update;
 555 };
 556
 557 struct intel_crtc_state {
 558         struct drm_crtc_state base;
 559
 560         /**
 561          * quirks - bitfield with hw state readout quirks
 562          *
 563          * For various reasons the hw state readout code might not be able to
 564          * completely faithfully read out the current state. These cases are
 565          * tracked with quirk flags so that fastboot and state checker can act
 566          * accordingly.
 567          */
 568 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 569         unsigned long quirks;
 570
 571         unsigned fb_bits; /* framebuffers to flip */
 572         bool update_pipe; /* can a fast modeset be performed? */
 573         bool disable_cxsr;
 574         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 575         bool fb_changed; /* fb on any of the planes is changed */
 576
 577         /* Pipe source size (ie. panel fitter input size)
 578          * All planes will be positioned inside this space,
 579          * and get clipped at the edges. */
 580         int pipe_src_w, pipe_src_h;
 581
 582         /*
 583          * Pipe pixel rate, adjusted for
 584          * panel fitter/pipe scaler downscaling.
 585          */
 586         unsigned int pixel_rate;
 587
 588         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 589          * between pch encoders and cpu encoders. */
 590         bool has_pch_encoder;
 591
 592         /* Are we sending infoframes on the attached port */
 593         bool has_infoframe;
 594
 595         /* CPU Transcoder for the pipe. Currently this can only differ from the
 596          * pipe on Haswell and later (where we have a special eDP transcoder)
 597          * and Broxton (where we have special DSI transcoders). */
 598         enum transcoder cpu_transcoder;
 599
 600         /*
 601          * Use reduced/limited/broadcast rbg range, compressing from the full
 602          * range fed into the crtcs.
 603          */
 604         bool limited_color_range;
 605
 606         /* Bitmask of encoder types (enum intel_output_type)
 607          * driven by the pipe.
 608          */
 609         unsigned int output_types;
 610
 611         /* Whether we should send NULL infoframes. Required for audio. */
 612         bool has_hdmi_sink;
 613
 614         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 615          * has_dp_encoder is set. */
 616         bool has_audio;
 617
 618         /*
 619          * Enable dithering, used when the selected pipe bpp doesn't match the
 620          * plane bpp.
 621          */
 622         bool dither;
 623
 624         /*
 625          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 626          * compliance video pattern tests.
 627          * Disable dither only if it is a compliance test request for
 628          * 18bpp.
 629          */
 630         bool dither_force_disable;
 631
 632         /* Controls for the clock computation, to override various stages. */
 633         bool clock_set;
 634
 635         /* SDVO TV has a bunch of special case. To make multifunction encoders
 636          * work correctly, we need to track this at runtime.*/
 637         bool sdvo_tv_clock;
 638
 639         /*
 640          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 641          * required. This is set in the 2nd loop of calling encoder's
 642          * ->compute_config if the first pick doesn't work out.
 643          */
 644         bool bw_constrained;
 645
 646         /* Settings for the intel dpll used on pretty much everything but
 647          * haswell. */
 648         struct dpll dpll;
 649
 650         /* Selected dpll when shared or NULL. */
 651         struct intel_shared_dpll *shared_dpll;
 652
 653         /* Actual register state of the dpll, for shared dpll cross-checking. */
 654         struct intel_dpll_hw_state dpll_hw_state;
 655
 656         /* DSI PLL registers */
 657         struct {
 658                 u32 ctrl, div;
 659         } dsi_pll;
 660
 661         int pipe_bpp;
 662         struct intel_link_m_n dp_m_n;
 663
 664         /* m2_n2 for eDP downclock */
 665         struct intel_link_m_n dp_m2_n2;
 666         bool has_drrs;
 667
 668         /*
 669          * Frequence the dpll for the port should run at. Differs from the
 670          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 671          * already multiplied by pixel_multiplier.
 672          */
 673         int port_clock;
 674
 675         /* Used by SDVO (and if we ever fix it, HDMI). */
 676         unsigned pixel_multiplier;
 677
 678         uint8_t lane_count;
 679
 680         /*
 681          * Used by platforms having DP/HDMI PHY with programmable lane
 682          * latency optimization.
 683          */
 684         uint8_t lane_lat_optim_mask;
 685
 686         /* Panel fitter controls for gen2-gen4 + VLV */
 687         struct {
 688                 u32 control;
 689                 u32 pgm_ratios;
 690                 u32 lvds_border_bits;
 691         } gmch_pfit;
 692
 693         /* Panel fitter placement and size for Ironlake+ */
 694         struct {
 695                 u32 pos;
 696                 u32 size;
 697                 bool enabled;
 698                 bool force_thru;
 699         } pch_pfit;
 700
 701         /* FDI configuration, only valid if has_pch_encoder is set. */
 702         int fdi_lanes;
 703         struct intel_link_m_n fdi_m_n;
 704
 705         bool ips_enabled;
 706
 707         bool enable_fbc;
 708
 709         bool double_wide;
 710
 711         int pbn;
 712
 713         struct intel_crtc_scaler_state scaler_state;
 714
 715         /* w/a for waiting 2 vblanks during crtc enable */
 716         enum pipe hsw_workaround_pipe;
 717
 718         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 719         bool disable_lp_wm;
 720
 721         struct intel_crtc_wm_state wm;
 722
 723         /* Gamma mode programmed on the pipe */
 724         uint32_t gamma_mode;
 725
 726         /* bitmask of visible planes (enum plane_id) */
 727         u8 active_planes;
 728 };
 729
 730 struct intel_crtc {
 731         struct drm_crtc base;
 732         enum pipe pipe;
 733         enum plane plane;
 734         u8 lut_r[256], lut_g[256], lut_b[256];
 735         /*
 736          * Whether the crtc and the connected output pipeline is active. Implies
 737          * that crtc->enabled is set, i.e. the current mode configuration has
 738          * some outputs connected to this crtc.
 739          */
 740         bool active;
 741         bool lowfreq_avail;
 742         u8 plane_ids_mask;
 743         unsigned long long enabled_power_domains;
 744         struct intel_overlay *overlay;
 745         struct intel_flip_work *flip_work;
 746
 747         atomic_t unpin_work_count;
 748
 749         /* Display surface base address adjustement for pageflips. Note that on
 750          * gen4+ this only adjusts up to a tile, offsets within a tile are
 751          * handled in the hw itself (with the TILEOFF register). */
 752         u32 dspaddr_offset;
 753         int adjusted_x;
 754         int adjusted_y;
 755
 756         uint32_t cursor_addr;
 757         uint32_t cursor_cntl;
 758         uint32_t cursor_size;
 759         uint32_t cursor_base;
 760
 761         struct intel_crtc_state *config;
 762
 763         /* global reset count when the last flip was submitted */
 764         unsigned int reset_count;
 765
 766         /* Access to these should be protected by dev_priv->irq_lock. */
 767         bool cpu_fifo_underrun_disabled;
 768         bool pch_fifo_underrun_disabled;
 769
 770         /* per-pipe watermark state */
 771         struct {
 772                 /* watermarks currently being used  */
 773                 union {
 774                         struct intel_pipe_wm ilk;
 775                         struct vlv_wm_state vlv;
 776                 } active;
 777
 778                 /* allow CxSR on this pipe */
 779                 bool cxsr_allowed;
 780         } wm;
 781
 782         int scanline_offset;
 783
 784         struct {
 785                 unsigned start_vbl_count;
 786                 ktime_t start_vbl_time;
 787                 int min_vbl, max_vbl;
 788                 int scanline_start;
 789         } debug;
 790
 791         /* scalers available on this crtc */
 792         int num_scalers;
 793 };
 794
 795 struct intel_plane {
 796         struct drm_plane base;
 797         u8 plane;
 798         enum plane_id id;
 799         enum pipe pipe;
 800         bool can_scale;
 801         int max_downscale;
 802         uint32_t frontbuffer_bit;
 803
 804         /*
 805          * NOTE: Do not place new plane state fields here (e.g., when adding
 806          * new plane properties).  New runtime state should now be placed in
 807          * the intel_plane_state structure and accessed via plane_state.
 808          */
 809
 810         void (*update_plane)(struct drm_plane *plane,
 811                              const struct intel_crtc_state *crtc_state,
 812                              const struct intel_plane_state *plane_state);
 813         void (*disable_plane)(struct drm_plane *plane,
 814                               struct drm_crtc *crtc);
 815         int (*check_plane)(struct drm_plane *plane,
 816                            struct intel_crtc_state *crtc_state,
 817                            struct intel_plane_state *state);
 818 };
 819
 820 struct intel_watermark_params {
 821         u16 fifo_size;
 822         u16 max_wm;
 823         u8 default_wm;
 824         u8 guard_size;
 825         u8 cacheline_size;
 826 };
 827
 828 struct cxsr_latency {
 829         bool is_desktop : 1;
 830         bool is_ddr3 : 1;
 831         u16 fsb_freq;
 832         u16 mem_freq;
 833         u16 display_sr;
 834         u16 display_hpll_disable;
 835         u16 cursor_sr;
 836         u16 cursor_hpll_disable;
 837 };
 838
 839 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 840 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 841 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 842 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 843 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 844 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 845 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 846 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 847 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 848
 849 struct intel_hdmi {
 850         i915_reg_t hdmi_reg;
 851         int ddc_bus;
 852         struct {
 853                 enum drm_dp_dual_mode_type type;
 854                 int max_tmds_clock;
 855         } dp_dual_mode;
 856         bool limited_color_range;
 857         bool color_range_auto;
 858         bool has_hdmi_sink;
 859         bool has_audio;
 860         enum hdmi_force_audio force_audio;
 861         bool rgb_quant_range_selectable;
 862         enum hdmi_picture_aspect aspect_ratio;
 863         struct intel_connector *attached_connector;
 864         void (*write_infoframe)(struct drm_encoder *encoder,
 865                                 const struct intel_crtc_state *crtc_state,
 866                                 enum hdmi_infoframe_type type,
 867                                 const void *frame, ssize_t len);
 868         void (*set_infoframes)(struct drm_encoder *encoder,
 869                                bool enable,
 870                                const struct intel_crtc_state *crtc_state,
 871                                const struct drm_connector_state *conn_state);
 872         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 873                                   const struct intel_crtc_state *pipe_config);
 874 };
 875
 876 struct intel_dp_mst_encoder;
 877 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 878
 879 /*
 880  * enum link_m_n_set:
 881  *      When platform provides two set of M_N registers for dp, we can
 882  *      program them and switch between them incase of DRRS.
 883  *      But When only one such register is provided, we have to program the
 884  *      required divider value on that registers itself based on the DRRS state.
 885  *
 886  * M1_N1        : Program dp_m_n on M1_N1 registers
 887  *                        dp_m2_n2 on M2_N2 registers (If supported)
 888  *
 889  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 890  *                        M2_N2 registers are not supported
 891  */
 892
 893 enum link_m_n_set {
 894         /* Sets the m1_n1 and m2_n2 */
 895         M1_N1 = 0,
 896         M2_N2
 897 };
 898
 899 struct intel_dp_desc {
 900         u8 oui[3];
 901         u8 device_id[6];
 902         u8 hw_rev;
 903         u8 sw_major_rev;
 904         u8 sw_minor_rev;
 905 } __packed;
 906
 907 struct intel_dp_compliance_data {
 908         unsigned long edid;
 909         uint8_t video_pattern;
 910         uint16_t hdisplay, vdisplay;
 911         uint8_t bpc;
 912 };
 913
 914 struct intel_dp_compliance {
 915         unsigned long test_type;
 916         struct intel_dp_compliance_data test_data;
 917         bool test_active;
 918         int test_link_rate;
 919         u8 test_lane_count;
 920 };
 921
 922 struct intel_dp {
 923         i915_reg_t output_reg;
 924         i915_reg_t aux_ch_ctl_reg;
 925         i915_reg_t aux_ch_data_reg[5];
 926         uint32_t DP;
 927         int link_rate;
 928         uint8_t lane_count;
 929         uint8_t sink_count;
 930         bool link_mst;
 931         bool has_audio;
 932         bool detect_done;
 933         bool channel_eq_status;
 934         bool reset_link_params;
 935         enum hdmi_force_audio force_audio;
 936         bool limited_color_range;
 937         bool color_range_auto;
 938         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 939         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 940         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 941         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 942         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 943         uint8_t num_sink_rates;
 944         int sink_rates[DP_MAX_SUPPORTED_RATES];
 945         /* Max lane count for the sink as per DPCD registers */
 946         uint8_t max_sink_lane_count;
 947         /* Max link BW for the sink as per DPCD registers */
 948         int max_sink_link_bw;
 949         /* sink or branch descriptor */
 950         struct intel_dp_desc desc;
 951         struct drm_dp_aux aux;
 952         enum intel_display_power_domain aux_power_domain;
 953         uint8_t train_set[4];
 954         int panel_power_up_delay;
 955         int panel_power_down_delay;
 956         int panel_power_cycle_delay;
 957         int backlight_on_delay;
 958         int backlight_off_delay;
 959         struct delayed_work panel_vdd_work;
 960         bool want_panel_vdd;
 961         unsigned long last_power_on;
 962         unsigned long last_backlight_off;
 963         ktime_t panel_power_off_time;
 964
 965         struct notifier_block edp_notifier;
 966
 967         /*
 968          * Pipe whose power sequencer is currently locked into
 969          * this port. Only relevant on VLV/CHV.
 970          */
 971         enum pipe pps_pipe;
 972         /*
 973          * Pipe currently driving the port. Used for preventing
 974          * the use of the PPS for any pipe currentrly driving
 975          * external DP as that will mess things up on VLV.
 976          */
 977         enum pipe active_pipe;
 978         /*
 979          * Set if the sequencer may be reset due to a power transition,
 980          * requiring a reinitialization. Only relevant on BXT.
 981          */
 982         bool pps_reset;
 983         struct edp_power_seq pps_delays;
 984
 985         bool can_mst; /* this port supports mst */
 986         bool is_mst;
 987         int active_mst_links;
 988         /* connector directly attached - won't be use for modeset in mst world */
 989         struct intel_connector *attached_connector;
 990
 991         /* mst connector list */
 992         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 993         struct drm_dp_mst_topology_mgr mst_mgr;
 994
 995         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 996         /*
 997          * This function returns the value we have to program the AUX_CTL
 998          * register with to kick off an AUX transaction.
 999          */
1000         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1001                                      bool has_aux_irq,
1002                                      int send_bytes,
1003                                      uint32_t aux_clock_divider);
1004
1005         /* This is called before a link training is starterd */
1006         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1007
1008         /* Displayport compliance testing */
1009         struct intel_dp_compliance compliance;
1010 };
1011
1012 struct intel_lspcon {
1013         bool active;
1014         enum drm_lspcon_mode mode;
1015 };
1016
1017 struct intel_digital_port {
1018         struct intel_encoder base;
1019         enum port port;
1020         u32 saved_port_bits;
1021         struct intel_dp dp;
1022         struct intel_hdmi hdmi;
1023         struct intel_lspcon lspcon;
1024         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1025         bool release_cl2_override;
1026         uint8_t max_lanes;
1027         enum intel_display_power_domain ddi_io_power_domain;
1028 };
1029
1030 struct intel_dp_mst_encoder {
1031         struct intel_encoder base;
1032         enum pipe pipe;
1033         struct intel_digital_port *primary;
1034         struct intel_connector *connector;
1035 };
1036
1037 static inline enum dpio_channel
1038 vlv_dport_to_channel(struct intel_digital_port *dport)
1039 {
1040         switch (dport->port) {
1041         case PORT_B:
1042         case PORT_D:
1043                 return DPIO_CH0;
1044         case PORT_C:
1045                 return DPIO_CH1;
1046         default:
1047                 BUG();
1048         }
1049 }
1050
1051 static inline enum dpio_phy
1052 vlv_dport_to_phy(struct intel_digital_port *dport)
1053 {
1054         switch (dport->port) {
1055         case PORT_B:
1056         case PORT_C:
1057                 return DPIO_PHY0;
1058         case PORT_D:
1059                 return DPIO_PHY1;
1060         default:
1061                 BUG();
1062         }
1063 }
1064
1065 static inline enum dpio_channel
1066 vlv_pipe_to_channel(enum pipe pipe)
1067 {
1068         switch (pipe) {
1069         case PIPE_A:
1070         case PIPE_C:
1071                 return DPIO_CH0;
1072         case PIPE_B:
1073                 return DPIO_CH1;
1074         default:
1075                 BUG();
1076         }
1077 }
1078
1079 static inline struct intel_crtc *
1080 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1081 {
1082         return dev_priv->pipe_to_crtc_mapping[pipe];
1083 }
1084
1085 static inline struct intel_crtc *
1086 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1087 {
1088         return dev_priv->plane_to_crtc_mapping[plane];
1089 }
1090
1091 struct intel_flip_work {
1092         struct work_struct unpin_work;
1093         struct work_struct mmio_work;
1094
1095         struct drm_crtc *crtc;
1096         struct i915_vma *old_vma;
1097         struct drm_framebuffer *old_fb;
1098         struct drm_i915_gem_object *pending_flip_obj;
1099         struct drm_pending_vblank_event *event;
1100         atomic_t pending;
1101         u32 flip_count;
1102         u32 gtt_offset;
1103         struct drm_i915_gem_request *flip_queued_req;
1104         u32 flip_queued_vblank;
1105         u32 flip_ready_vblank;
1106         unsigned int rotation;
1107 };
1108
1109 struct intel_load_detect_pipe {
1110         struct drm_atomic_state *restore_state;
1111 };
1112
1113 static inline struct intel_encoder *
1114 intel_attached_encoder(struct drm_connector *connector)
1115 {
1116         return to_intel_connector(connector)->encoder;
1117 }
1118
1119 static inline struct intel_digital_port *
1120 enc_to_dig_port(struct drm_encoder *encoder)
1121 {
1122         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1123
1124         switch (intel_encoder->type) {
1125         case INTEL_OUTPUT_UNKNOWN:
1126                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1127         case INTEL_OUTPUT_DP:
1128         case INTEL_OUTPUT_EDP:
1129         case INTEL_OUTPUT_HDMI:
1130                 return container_of(encoder, struct intel_digital_port,
1131                                     base.base);
1132         default:
1133                 return NULL;
1134         }
1135 }
1136
1137 static inline struct intel_dp_mst_encoder *
1138 enc_to_mst(struct drm_encoder *encoder)
1139 {
1140         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1141 }
1142
1143 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1144 {
1145         return &enc_to_dig_port(encoder)->dp;
1146 }
1147
1148 static inline struct intel_digital_port *
1149 dp_to_dig_port(struct intel_dp *intel_dp)
1150 {
1151         return container_of(intel_dp, struct intel_digital_port, dp);
1152 }
1153
1154 static inline struct intel_lspcon *
1155 dp_to_lspcon(struct intel_dp *intel_dp)
1156 {
1157         return &dp_to_dig_port(intel_dp)->lspcon;
1158 }
1159
1160 static inline struct intel_digital_port *
1161 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1162 {
1163         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1164 }
1165
1166 /* intel_fifo_underrun.c */
1167 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1168                                            enum pipe pipe, bool enable);
1169 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1170                                            enum transcoder pch_transcoder,
1171                                            bool enable);
1172 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1173                                          enum pipe pipe);
1174 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1175                                          enum transcoder pch_transcoder);
1176 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1177 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1178
1179 /* i915_irq.c */
1180 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1181 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1182 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1183 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1184 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1185 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1186 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1187 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1188 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1189 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1190 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1191 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1192 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1193 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1194 {
1195         /*
1196          * We only use drm_irq_uninstall() at unload and VT switch, so
1197          * this is the only thing we need to check.
1198          */
1199         return dev_priv->pm.irqs_enabled;
1200 }
1201
1202 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1203 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1204                                      unsigned int pipe_mask);
1205 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1206                                      unsigned int pipe_mask);
1207 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1208 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1209 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1210
1211 /* intel_crt.c */
1212 void intel_crt_init(struct drm_i915_private *dev_priv);
1213 void intel_crt_reset(struct drm_encoder *encoder);
1214
1215 /* intel_ddi.c */
1216 void intel_ddi_clk_select(struct intel_encoder *encoder,
1217                           struct intel_shared_dpll *pll);
1218 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1219                                 struct intel_crtc_state *old_crtc_state,
1220                                 struct drm_connector_state *old_conn_state);
1221 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1222 void hsw_fdi_link_train(struct intel_crtc *crtc,
1223                         const struct intel_crtc_state *crtc_state);
1224 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1225 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1226 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1227 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1228 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1229                                        enum transcoder cpu_transcoder);
1230 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1231 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1232 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1233                           struct intel_crtc_state *crtc_state);
1234 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1235 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1236 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1237 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1238                                  struct intel_crtc *intel_crtc);
1239 void intel_ddi_get_config(struct intel_encoder *encoder,
1240                           struct intel_crtc_state *pipe_config);
1241 struct intel_encoder *
1242 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1243
1244 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1245 void intel_ddi_clock_get(struct intel_encoder *encoder,
1246                          struct intel_crtc_state *pipe_config);
1247 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1248                                     bool state);
1249 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1250 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1251
1252 unsigned int intel_fb_align_height(struct drm_i915_private *dev_priv,
1253                                    unsigned int height,
1254                                    uint32_t pixel_format,
1255                                    uint64_t fb_format_modifier);
1256 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1257                               uint64_t fb_modifier, uint32_t pixel_format);
1258
1259 /* intel_audio.c */
1260 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1261 void intel_audio_codec_enable(struct intel_encoder *encoder,
1262                               const struct intel_crtc_state *crtc_state,
1263                               const struct drm_connector_state *conn_state);
1264 void intel_audio_codec_disable(struct intel_encoder *encoder);
1265 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1266 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1267
1268 /* intel_cdclk.c */
1269 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1270 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1271 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1272 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1273 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1274                                const struct intel_cdclk_state *b);
1275 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1276                      const struct intel_cdclk_state *cdclk_state);
1277
1278 /* intel_display.c */
1279 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1280 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1281 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1282 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1283                       const char *name, u32 reg, int ref_freq);
1284 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1285                            const char *name, u32 reg);
1286 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1287 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1288 extern const struct drm_plane_funcs intel_plane_funcs;
1289 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1290 unsigned int intel_fb_xy_to_linear(int x, int y,
1291                                    const struct intel_plane_state *state,
1292                                    int plane);
1293 void intel_add_fb_offsets(int *x, int *y,
1294                           const struct intel_plane_state *state, int plane);
1295 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1296 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1297 void intel_mark_busy(struct drm_i915_private *dev_priv);
1298 void intel_mark_idle(struct drm_i915_private *dev_priv);
1299 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1300 int intel_display_suspend(struct drm_device *dev);
1301 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1302 void intel_encoder_destroy(struct drm_encoder *encoder);
1303 int intel_connector_init(struct intel_connector *);
1304 struct intel_connector *intel_connector_alloc(void);
1305 bool intel_connector_get_hw_state(struct intel_connector *connector);
1306 void intel_connector_attach_encoder(struct intel_connector *connector,
1307                                     struct intel_encoder *encoder);
1308 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1309                                              struct drm_crtc *crtc);
1310 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1311 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1312                                 struct drm_file *file_priv);
1313 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1314                                              enum pipe pipe);
1315 static inline bool
1316 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1317                     enum intel_output_type type)
1318 {
1319         return crtc_state->output_types & (1 << type);
1320 }
1321 static inline bool
1322 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1323 {
1324         return crtc_state->output_types &
1325                 ((1 << INTEL_OUTPUT_DP) |
1326                  (1 << INTEL_OUTPUT_DP_MST) |
1327                  (1 << INTEL_OUTPUT_EDP));
1328 }
1329 static inline void
1330 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1331 {
1332         drm_wait_one_vblank(&dev_priv->drm, pipe);
1333 }
1334 static inline void
1335 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1336 {
1337         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1338
1339         if (crtc->active)
1340                 intel_wait_for_vblank(dev_priv, pipe);
1341 }
1342
1343 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1344
1345 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1346 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1347                          struct intel_digital_port *dport,
1348                          unsigned int expected_mask);
1349 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1350                                 struct drm_display_mode *mode,
1351                                 struct intel_load_detect_pipe *old,
1352                                 struct drm_modeset_acquire_ctx *ctx);
1353 void intel_release_load_detect_pipe(struct drm_connector *connector,
1354                                     struct intel_load_detect_pipe *old,
1355                                     struct drm_modeset_acquire_ctx *ctx);
1356 struct i915_vma *
1357 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1358 void intel_unpin_fb_vma(struct i915_vma *vma);
1359 struct drm_framebuffer *
1360 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1361                          struct drm_mode_fb_cmd2 *mode_cmd);
1362 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1363 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1364 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1365 int intel_prepare_plane_fb(struct drm_plane *plane,
1366                            struct drm_plane_state *new_state);
1367 void intel_cleanup_plane_fb(struct drm_plane *plane,
1368                             struct drm_plane_state *old_state);
1369 int intel_plane_atomic_get_property(struct drm_plane *plane,
1370                                     const struct drm_plane_state *state,
1371                                     struct drm_property *property,
1372                                     uint64_t *val);
1373 int intel_plane_atomic_set_property(struct drm_plane *plane,
1374                                     struct drm_plane_state *state,
1375                                     struct drm_property *property,
1376                                     uint64_t val);
1377 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1378                                     struct drm_plane_state *plane_state);
1379
1380 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1381                                uint64_t fb_modifier, unsigned int cpp);
1382
1383 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1384                                     enum pipe pipe);
1385
1386 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1387                      const struct dpll *dpll);
1388 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1389 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1390
1391 /* modesetting asserts */
1392 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1393                            enum pipe pipe);
1394 void assert_pll(struct drm_i915_private *dev_priv,
1395                 enum pipe pipe, bool state);
1396 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1397 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1398 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1399 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1400 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1401 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1402                        enum pipe pipe, bool state);
1403 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1404 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1405 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1406 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1407 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1408 u32 intel_compute_tile_offset(int *x, int *y,
1409                               const struct intel_plane_state *state, int plane);
1410 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1411 void intel_finish_reset(struct drm_i915_private *dev_priv);
1412 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1413 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1414 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1415 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1416 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1417 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1418 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1419 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1420 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1421 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1422 unsigned int skl_cdclk_get_vco(unsigned int freq);
1423 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1424 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1425 void intel_dp_get_m_n(struct intel_crtc *crtc,
1426                       struct intel_crtc_state *pipe_config);
1427 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1428 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1429 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1430                         struct dpll *best_clock);
1431 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1432
1433 bool intel_crtc_active(struct intel_crtc *crtc);
1434 void hsw_enable_ips(struct intel_crtc *crtc);
1435 void hsw_disable_ips(struct intel_crtc *crtc);
1436 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1437 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1438                                  struct intel_crtc_state *pipe_config);
1439
1440 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1441 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1442
1443 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1444 {
1445         return i915_ggtt_offset(state->vma);
1446 }
1447
1448 u32 skl_plane_ctl_format(uint32_t pixel_format);
1449 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1450 u32 skl_plane_ctl_rotation(unsigned int rotation);
1451 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1452                      unsigned int rotation);
1453 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1454
1455 /* intel_csr.c */
1456 void intel_csr_ucode_init(struct drm_i915_private *);
1457 void intel_csr_load_program(struct drm_i915_private *);
1458 void intel_csr_ucode_fini(struct drm_i915_private *);
1459 void intel_csr_ucode_suspend(struct drm_i915_private *);
1460 void intel_csr_ucode_resume(struct drm_i915_private *);
1461
1462 /* intel_dp.c */
1463 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1464                    enum port port);
1465 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1466                              struct intel_connector *intel_connector);
1467 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1468                               int link_rate, uint8_t lane_count,
1469                               bool link_mst);
1470 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1471                                             int link_rate, uint8_t lane_count);
1472 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1473 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1474 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1475 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1476 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1477 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1478 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1479 bool intel_dp_compute_config(struct intel_encoder *encoder,
1480                              struct intel_crtc_state *pipe_config,
1481                              struct drm_connector_state *conn_state);
1482 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1483 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1484                                   bool long_hpd);
1485 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1486 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1487 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1488 void intel_edp_panel_on(struct intel_dp *intel_dp);
1489 void intel_edp_panel_off(struct intel_dp *intel_dp);
1490 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1491 void intel_dp_mst_suspend(struct drm_device *dev);
1492 void intel_dp_mst_resume(struct drm_device *dev);
1493 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1494 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1495 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1496 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1497 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1498 void intel_plane_destroy(struct drm_plane *plane);
1499 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1500                            struct intel_crtc_state *crtc_state);
1501 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1502                            struct intel_crtc_state *crtc_state);
1503 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1504                                unsigned int frontbuffer_bits);
1505 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1506                           unsigned int frontbuffer_bits);
1507
1508 void
1509 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1510                                        uint8_t dp_train_pat);
1511 void
1512 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1513 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1514 uint8_t
1515 intel_dp_voltage_max(struct intel_dp *intel_dp);
1516 uint8_t
1517 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1518 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1519                            uint8_t *link_bw, uint8_t *rate_select);
1520 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1521 bool
1522 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1523
1524 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1525 {
1526         return ~((1 << lane_count) - 1) & 0xf;
1527 }
1528
1529 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1530 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1531                           struct intel_dp_desc *desc);
1532 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1533 int intel_dp_link_required(int pixel_clock, int bpp);
1534 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1535 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1536                                   struct intel_digital_port *port);
1537
1538 /* intel_dp_aux_backlight.c */
1539 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1540
1541 /* intel_dp_mst.c */
1542 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1543 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1544 /* intel_dsi.c */
1545 void intel_dsi_init(struct drm_i915_private *dev_priv);
1546
1547 /* intel_dsi_dcs_backlight.c */
1548 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1549
1550 /* intel_dvo.c */
1551 void intel_dvo_init(struct drm_i915_private *dev_priv);
1552 /* intel_hotplug.c */
1553 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1554
1555
1556 /* legacy fbdev emulation in intel_fbdev.c */
1557 #ifdef CONFIG_DRM_FBDEV_EMULATION
1558 extern int intel_fbdev_init(struct drm_device *dev);
1559 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1560 extern void intel_fbdev_fini(struct drm_device *dev);
1561 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1562 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1563 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1564 #else
1565 static inline int intel_fbdev_init(struct drm_device *dev)
1566 {
1567         return 0;
1568 }
1569
1570 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1571 {
1572 }
1573
1574 static inline void intel_fbdev_fini(struct drm_device *dev)
1575 {
1576 }
1577
1578 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1579 {
1580 }
1581
1582 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1583 {
1584 }
1585
1586 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1587 {
1588 }
1589 #endif
1590
1591 /* intel_fbc.c */
1592 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1593                            struct drm_atomic_state *state);
1594 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1595 void intel_fbc_pre_update(struct intel_crtc *crtc,
1596                           struct intel_crtc_state *crtc_state,
1597                           struct intel_plane_state *plane_state);
1598 void intel_fbc_post_update(struct intel_crtc *crtc);
1599 void intel_fbc_init(struct drm_i915_private *dev_priv);
1600 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1601 void intel_fbc_enable(struct intel_crtc *crtc,
1602                       struct intel_crtc_state *crtc_state,
1603                       struct intel_plane_state *plane_state);
1604 void intel_fbc_disable(struct intel_crtc *crtc);
1605 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1606 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1607                           unsigned int frontbuffer_bits,
1608                           enum fb_op_origin origin);
1609 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1610                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1611 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1612 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1613
1614 /* intel_hdmi.c */
1615 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1616                      enum port port);
1617 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1618                                struct intel_connector *intel_connector);
1619 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1620 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1621                                struct intel_crtc_state *pipe_config,
1622                                struct drm_connector_state *conn_state);
1623 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1624
1625
1626 /* intel_lvds.c */
1627 void intel_lvds_init(struct drm_i915_private *dev_priv);
1628 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1629 bool intel_is_dual_link_lvds(struct drm_device *dev);
1630
1631
1632 /* intel_modes.c */
1633 int intel_connector_update_modes(struct drm_connector *connector,
1634                                  struct edid *edid);
1635 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1636 void intel_attach_force_audio_property(struct drm_connector *connector);
1637 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1638 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1639
1640
1641 /* intel_overlay.c */
1642 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1643 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1644 int intel_overlay_switch_off(struct intel_overlay *overlay);
1645 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1646                                   struct drm_file *file_priv);
1647 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1648                               struct drm_file *file_priv);
1649 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1650
1651
1652 /* intel_panel.c */
1653 int intel_panel_init(struct intel_panel *panel,
1654                      struct drm_display_mode *fixed_mode,
1655                      struct drm_display_mode *downclock_mode);
1656 void intel_panel_fini(struct intel_panel *panel);
1657 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1658                             struct drm_display_mode *adjusted_mode);
1659 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1660                              struct intel_crtc_state *pipe_config,
1661                              int fitting_mode);
1662 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1663                               struct intel_crtc_state *pipe_config,
1664                               int fitting_mode);
1665 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1666                                     u32 level, u32 max);
1667 int intel_panel_setup_backlight(struct drm_connector *connector,
1668                                 enum pipe pipe);
1669 void intel_panel_enable_backlight(struct intel_connector *connector);
1670 void intel_panel_disable_backlight(struct intel_connector *connector);
1671 void intel_panel_destroy_backlight(struct drm_connector *connector);
1672 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1673 extern struct drm_display_mode *intel_find_panel_downclock(
1674                                 struct drm_i915_private *dev_priv,
1675                                 struct drm_display_mode *fixed_mode,
1676                                 struct drm_connector *connector);
1677
1678 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1679 int intel_backlight_device_register(struct intel_connector *connector);
1680 void intel_backlight_device_unregister(struct intel_connector *connector);
1681 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1682 static int intel_backlight_device_register(struct intel_connector *connector)
1683 {
1684         return 0;
1685 }
1686 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1687 {
1688 }
1689 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1690
1691
1692 /* intel_psr.c */
1693 void intel_psr_enable(struct intel_dp *intel_dp);
1694 void intel_psr_disable(struct intel_dp *intel_dp);
1695 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1696                           unsigned frontbuffer_bits);
1697 void intel_psr_flush(struct drm_i915_private *dev_priv,
1698                      unsigned frontbuffer_bits,
1699                      enum fb_op_origin origin);
1700 void intel_psr_init(struct drm_i915_private *dev_priv);
1701 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1702                                    unsigned frontbuffer_bits);
1703
1704 /* intel_runtime_pm.c */
1705 int intel_power_domains_init(struct drm_i915_private *);
1706 void intel_power_domains_fini(struct drm_i915_private *);
1707 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1708 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1709 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1710 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1711 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1712 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1713 const char *
1714 intel_display_power_domain_str(enum intel_display_power_domain domain);
1715
1716 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1717                                     enum intel_display_power_domain domain);
1718 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1719                                       enum intel_display_power_domain domain);
1720 void intel_display_power_get(struct drm_i915_private *dev_priv,
1721                              enum intel_display_power_domain domain);
1722 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1723                                         enum intel_display_power_domain domain);
1724 void intel_display_power_put(struct drm_i915_private *dev_priv,
1725                              enum intel_display_power_domain domain);
1726
1727 static inline void
1728 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1729 {
1730         WARN_ONCE(dev_priv->pm.suspended,
1731                   "Device suspended during HW access\n");
1732 }
1733
1734 static inline void
1735 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1736 {
1737         assert_rpm_device_not_suspended(dev_priv);
1738         WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1739                   "RPM wakelock ref not held during HW access");
1740 }
1741
1742 /**
1743  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1744  * @dev_priv: i915 device instance
1745  *
1746  * This function disable asserts that check if we hold an RPM wakelock
1747  * reference, while keeping the device-not-suspended checks still enabled.
1748  * It's meant to be used only in special circumstances where our rule about
1749  * the wakelock refcount wrt. the device power state doesn't hold. According
1750  * to this rule at any point where we access the HW or want to keep the HW in
1751  * an active state we must hold an RPM wakelock reference acquired via one of
1752  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1753  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1754  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1755  * users should avoid using this function.
1756  *
1757  * Any calls to this function must have a symmetric call to
1758  * enable_rpm_wakeref_asserts().
1759  */
1760 static inline void
1761 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1762 {
1763         atomic_inc(&dev_priv->pm.wakeref_count);
1764 }
1765
1766 /**
1767  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1768  * @dev_priv: i915 device instance
1769  *
1770  * This function re-enables the RPM assert checks after disabling them with
1771  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1772  * circumstances otherwise its use should be avoided.
1773  *
1774  * Any calls to this function must have a symmetric call to
1775  * disable_rpm_wakeref_asserts().
1776  */
1777 static inline void
1778 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1779 {
1780         atomic_dec(&dev_priv->pm.wakeref_count);
1781 }
1782
1783 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1784 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1785 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1786 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1787
1788 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1789
1790 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1791                              bool override, unsigned int mask);
1792 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1793                           enum dpio_channel ch, bool override);
1794
1795
1796 /* intel_pm.c */
1797 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1798 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1799 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1800 void intel_update_watermarks(struct intel_crtc *crtc);
1801 void intel_init_pm(struct drm_i915_private *dev_priv);
1802 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1803 void intel_pm_setup(struct drm_i915_private *dev_priv);
1804 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1805 void intel_gpu_ips_teardown(void);
1806 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1807 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1808 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1809 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1810 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1811 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1812 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1813 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1814 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1815 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1816 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1817                     struct intel_rps_client *rps,
1818                     unsigned long submitted);
1819 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1820 void vlv_wm_get_hw_state(struct drm_device *dev);
1821 void ilk_wm_get_hw_state(struct drm_device *dev);
1822 void skl_wm_get_hw_state(struct drm_device *dev);
1823 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1824                           struct skl_ddb_allocation *ddb /* out */);
1825 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1826                               struct skl_pipe_wm *out);
1827 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1828 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1829 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1830 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1831                          const struct skl_wm_level *l2);
1832 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1833                                  const struct skl_ddb_entry *ddb,
1834                                  int ignore);
1835 bool ilk_disable_lp_wm(struct drm_device *dev);
1836 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1837 static inline int intel_enable_rc6(void)
1838 {
1839         return i915.enable_rc6;
1840 }
1841
1842 /* intel_sdvo.c */
1843 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1844                      i915_reg_t reg, enum port port);
1845
1846
1847 /* intel_sprite.c */
1848 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1849                              int usecs);
1850 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1851                                               enum pipe pipe, int plane);
1852 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1853                               struct drm_file *file_priv);
1854 void intel_pipe_update_start(struct intel_crtc *crtc);
1855 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1856
1857 /* intel_tv.c */
1858 void intel_tv_init(struct drm_i915_private *dev_priv);
1859
1860 /* intel_atomic.c */
1861 int intel_connector_atomic_get_property(struct drm_connector *connector,
1862                                         const struct drm_connector_state *state,
1863                                         struct drm_property *property,
1864                                         uint64_t *val);
1865 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1866 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1867                                struct drm_crtc_state *state);
1868 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1869 void intel_atomic_state_clear(struct drm_atomic_state *);
1870
1871 static inline struct intel_crtc_state *
1872 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1873                             struct intel_crtc *crtc)
1874 {
1875         struct drm_crtc_state *crtc_state;
1876         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1877         if (IS_ERR(crtc_state))
1878                 return ERR_CAST(crtc_state);
1879
1880         return to_intel_crtc_state(crtc_state);
1881 }
1882
1883 static inline struct intel_crtc_state *
1884 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1885                                      struct intel_crtc *crtc)
1886 {
1887         struct drm_crtc_state *crtc_state;
1888
1889         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1890
1891         if (crtc_state)
1892                 return to_intel_crtc_state(crtc_state);
1893         else
1894                 return NULL;
1895 }
1896
1897 static inline struct intel_plane_state *
1898 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1899                                       struct intel_plane *plane)
1900 {
1901         struct drm_plane_state *plane_state;
1902
1903         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1904
1905         return to_intel_plane_state(plane_state);
1906 }
1907
1908 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1909                                struct intel_crtc *intel_crtc,
1910                                struct intel_crtc_state *crtc_state);
1911
1912 /* intel_atomic_plane.c */
1913 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1914 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1915 void intel_plane_destroy_state(struct drm_plane *plane,
1916                                struct drm_plane_state *state);
1917 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1918 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1919                                         struct intel_plane_state *intel_state);
1920
1921 /* intel_color.c */
1922 void intel_color_init(struct drm_crtc *crtc);
1923 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1924 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1925 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1926
1927 /* intel_lspcon.c */
1928 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1929 void lspcon_resume(struct intel_lspcon *lspcon);
1930 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1931
1932 /* intel_pipe_crc.c */
1933 int intel_pipe_crc_create(struct drm_minor *minor);
1934 void intel_pipe_crc_cleanup(struct drm_minor *minor);
1935 #ifdef CONFIG_DEBUG_FS
1936 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1937                               size_t *values_cnt);
1938 #else
1939 #define intel_crtc_set_crc_source NULL
1940 #endif
1941 extern const struct file_operations i915_display_crc_ctl_fops;
1942 #endif /* __INTEL_DRV_H__ */