2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <linux/stackdepot.h>
33 #include <drm/i915_drm.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_rect.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/drm_atomic.h>
44 #include <drm/i915_mei_hdcp_interface.h>
45 #include <media/cec-notifier.h>
50 * __wait_for - magic wait macro
52 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
53 * important that we check the condition again after having timed out, since the
54 * timeout could be due to preemption or similar and we've never had a chance to
55 * check the condition before the timeout.
57 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
58 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
59 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
63 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
65 /* Guarantee COND check prior to timeout */ \
75 usleep_range(wait__, wait__ * 2); \
76 if (wait__ < (Wmax)) \
82 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
84 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
86 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
87 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
88 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
90 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
93 #define _wait_for_atomic(COND, US, ATOMIC) \
95 int cpu, ret, timeout = (US) * 1000; \
97 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
100 cpu = smp_processor_id(); \
102 base = local_clock(); \
104 u64 now = local_clock(); \
107 /* Guarantee COND check prior to timeout */ \
113 if (now - base >= timeout) { \
120 if (unlikely(cpu != smp_processor_id())) { \
121 timeout -= now - base; \
122 cpu = smp_processor_id(); \
123 base = local_clock(); \
130 #define wait_for_us(COND, US) \
133 BUILD_BUG_ON(!__builtin_constant_p(US)); \
135 ret__ = _wait_for((COND), (US), 10, 10); \
137 ret__ = _wait_for_atomic((COND), (US), 0); \
141 #define wait_for_atomic_us(COND, US) \
143 BUILD_BUG_ON(!__builtin_constant_p(US)); \
144 BUILD_BUG_ON((US) > 50000); \
145 _wait_for_atomic((COND), (US), 1); \
148 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
150 #define KHz(x) (1000 * (x))
151 #define MHz(x) KHz(1000 * (x))
153 #define KBps(x) (1000 * (x))
154 #define MBps(x) KBps(1000 * (x))
155 #define GBps(x) ((u64)1000 * MBps((x)))
158 * Display related stuff
161 /* store information about an Ixxx DVO */
162 /* The i830->i865 use multiple DVOs with multiple i2cs */
163 /* the i915, i945 have a single sDVO i2c bus - which is different */
164 #define MAX_OUTPUTS 6
165 /* maximum connectors per crtcs in the mode set */
167 #define INTEL_I2C_BUS_DVO 1
168 #define INTEL_I2C_BUS_SDVO 2
170 /* these are outputs from the chip - integrated only
171 external chips are via DVO or SDVO output */
172 enum intel_output_type {
173 INTEL_OUTPUT_UNUSED = 0,
174 INTEL_OUTPUT_ANALOG = 1,
175 INTEL_OUTPUT_DVO = 2,
176 INTEL_OUTPUT_SDVO = 3,
177 INTEL_OUTPUT_LVDS = 4,
178 INTEL_OUTPUT_TVOUT = 5,
179 INTEL_OUTPUT_HDMI = 6,
181 INTEL_OUTPUT_EDP = 8,
182 INTEL_OUTPUT_DSI = 9,
183 INTEL_OUTPUT_DDI = 10,
184 INTEL_OUTPUT_DP_MST = 11,
187 #define INTEL_DVO_CHIP_NONE 0
188 #define INTEL_DVO_CHIP_LVDS 1
189 #define INTEL_DVO_CHIP_TMDS 2
190 #define INTEL_DVO_CHIP_TVOUT 4
192 #define INTEL_DSI_VIDEO_MODE 0
193 #define INTEL_DSI_COMMAND_MODE 1
195 struct intel_framebuffer {
196 struct drm_framebuffer base;
197 struct intel_rotation_info rot_info;
199 /* for each plane in the normal GTT view */
203 /* for each plane in the rotated GTT view */
206 unsigned int pitch; /* pixels */
211 struct drm_fb_helper helper;
212 struct intel_framebuffer *fb;
213 struct i915_vma *vma;
214 unsigned long vma_flags;
215 async_cookie_t cookie;
218 /* Whether or not fbdev hpd processing is temporarily suspended */
219 bool hpd_suspended : 1;
220 /* Set when a hotplug was received while HPD processing was
223 bool hpd_waiting : 1;
225 /* Protects hpd_suspended */
226 struct mutex hpd_lock;
229 struct intel_encoder {
230 struct drm_encoder base;
232 enum intel_output_type type;
234 unsigned int cloneable;
235 bool (*hotplug)(struct intel_encoder *encoder,
236 struct intel_connector *connector);
237 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
238 struct intel_crtc_state *,
239 struct drm_connector_state *);
240 int (*compute_config)(struct intel_encoder *,
241 struct intel_crtc_state *,
242 struct drm_connector_state *);
243 void (*pre_pll_enable)(struct intel_encoder *,
244 const struct intel_crtc_state *,
245 const struct drm_connector_state *);
246 void (*pre_enable)(struct intel_encoder *,
247 const struct intel_crtc_state *,
248 const struct drm_connector_state *);
249 void (*enable)(struct intel_encoder *,
250 const struct intel_crtc_state *,
251 const struct drm_connector_state *);
252 void (*disable)(struct intel_encoder *,
253 const struct intel_crtc_state *,
254 const struct drm_connector_state *);
255 void (*post_disable)(struct intel_encoder *,
256 const struct intel_crtc_state *,
257 const struct drm_connector_state *);
258 void (*post_pll_disable)(struct intel_encoder *,
259 const struct intel_crtc_state *,
260 const struct drm_connector_state *);
261 void (*update_pipe)(struct intel_encoder *,
262 const struct intel_crtc_state *,
263 const struct drm_connector_state *);
264 /* Read out the current hw state of this connector, returning true if
265 * the encoder is active. If the encoder is enabled it also set the pipe
266 * it is connected to in the pipe parameter. */
267 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
268 /* Reconstructs the equivalent mode flags for the current hardware
269 * state. This must be called _after_ display->get_pipe_config has
270 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
271 * be set correctly before calling this function. */
272 void (*get_config)(struct intel_encoder *,
273 struct intel_crtc_state *pipe_config);
274 /* Returns a mask of power domains that need to be referenced as part
275 * of the hardware state readout code. */
276 u64 (*get_power_domains)(struct intel_encoder *encoder,
277 struct intel_crtc_state *crtc_state);
279 * Called during system suspend after all pending requests for the
280 * encoder are flushed (for example for DP AUX transactions) and
281 * device interrupts are disabled.
283 void (*suspend)(struct intel_encoder *);
285 enum hpd_pin hpd_pin;
286 enum intel_display_power_domain power_domain;
287 /* for communication with audio component; protected by av_mutex */
288 const struct drm_connector *audio_connector;
292 struct drm_display_mode *fixed_mode;
293 struct drm_display_mode *downclock_mode;
302 bool combination_mode; /* gen 2/4 only */
304 bool alternate_pwm_increment; /* lpt+ */
307 bool util_pin_active_low; /* bxt+ */
308 u8 controller; /* bxt+ only */
309 struct pwm_device *pwm;
311 struct backlight_device *device;
313 /* Connector and platform specific backlight functions */
314 int (*setup)(struct intel_connector *connector, enum pipe pipe);
315 u32 (*get)(struct intel_connector *connector);
316 void (*set)(const struct drm_connector_state *conn_state, u32 level);
317 void (*disable)(const struct drm_connector_state *conn_state);
318 void (*enable)(const struct intel_crtc_state *crtc_state,
319 const struct drm_connector_state *conn_state);
320 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
321 void (*power)(struct intel_connector *, bool enable);
325 struct intel_digital_port;
327 enum check_link_response {
328 HDCP_LINK_PROTECTED = 0,
329 HDCP_TOPOLOGY_CHANGE,
330 HDCP_LINK_INTEGRITY_FAILURE,
335 * This structure serves as a translation layer between the generic HDCP code
336 * and the bus-specific code. What that means is that HDCP over HDMI differs
337 * from HDCP over DP, so to account for these differences, we need to
338 * communicate with the receiver through this shim.
340 * For completeness, the 2 buses differ in the following ways:
342 * HDCP registers on the receiver are set via DP AUX for DP, and
343 * they are set via DDC for HDMI.
344 * - Receiver register offsets
345 * The offsets of the registers are different for DP vs. HDMI
346 * - Receiver register masks/offsets
347 * For instance, the ready bit for the KSV fifo is in a different
348 * place on DP vs HDMI
349 * - Receiver register names
350 * Seriously. In the DP spec, the 16-bit register containing
351 * downstream information is called BINFO, on HDMI it's called
352 * BSTATUS. To confuse matters further, DP has a BSTATUS register
353 * with a completely different definition.
355 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
356 * be read 3 keys at a time
358 * Since Aksv is hidden in hardware, there's different procedures
359 * to send it over DP AUX vs DDC
361 struct intel_hdcp_shim {
362 /* Outputs the transmitter's An and Aksv values to the receiver. */
363 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
365 /* Reads the receiver's key selection vector */
366 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
369 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
370 * definitions are the same in the respective specs, but the names are
371 * different. Call it BSTATUS since that's the name the HDMI spec
372 * uses and it was there first.
374 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
377 /* Determines whether a repeater is present downstream */
378 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
379 bool *repeater_present);
381 /* Reads the receiver's Ri' value */
382 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
384 /* Determines if the receiver's KSV FIFO is ready for consumption */
385 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
388 /* Reads the ksv fifo for num_downstream devices */
389 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
390 int num_downstream, u8 *ksv_fifo);
392 /* Reads a 32-bit part of V' from the receiver */
393 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
396 /* Enables HDCP signalling on the port */
397 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
400 /* Ensures the link is still protected */
401 bool (*check_link)(struct intel_digital_port *intel_dig_port);
403 /* Detects panel's hdcp capability. This is optional for HDMI. */
404 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
407 /* HDCP adaptation(DP/HDMI) required on the port */
408 enum hdcp_wired_protocol protocol;
410 /* Detects whether sink is HDCP2.2 capable */
411 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
414 /* Write HDCP2.2 messages */
415 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
416 void *buf, size_t size);
418 /* Read HDCP2.2 messages */
419 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
420 u8 msg_id, void *buf, size_t size);
423 * Implementation of DP HDCP2.2 Errata for the communication of stream
424 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
425 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
427 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
428 bool is_repeater, u8 type);
430 /* HDCP2.2 Link Integrity Check */
431 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
435 const struct intel_hdcp_shim *shim;
436 /* Mutex for hdcp state of the connector */
439 struct delayed_work check_work;
440 struct work_struct prop_work;
442 /* HDCP1.4 Encryption status */
445 /* HDCP2.2 related definitions */
446 /* Flag indicates whether this connector supports HDCP2.2 or not. */
447 bool hdcp2_supported;
449 /* HDCP2.2 Encryption status */
450 bool hdcp2_encrypted;
453 * Content Stream Type defined by content owner. TYPE0(0x0) content can
454 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
455 * content can flow only through a link protected by HDCP2.2.
458 struct hdcp_port_data port_data;
464 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
465 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
466 * When it rolls over re-auth has to be triggered.
471 * Count of RepeaterAuth_Stream_Manage msg propagated.
472 * Initialized to 0 on AKE_INIT. Incremented after every successful
473 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
474 * over re-Auth has to be triggered.
479 * Work queue to signal the CP_IRQ. Used for the waiters to read the
480 * available information from HDCP DP sink.
482 wait_queue_head_t cp_irq_queue;
483 atomic_t cp_irq_count;
484 int cp_irq_count_cached;
487 struct intel_connector {
488 struct drm_connector base;
490 * The fixed encoder this connector is connected to.
492 struct intel_encoder *encoder;
494 /* ACPI device id for ACPI and driver cooperation */
497 /* Reads out the current hw, returning true if the connector is enabled
498 * and active (i.e. dpms ON state). */
499 bool (*get_hw_state)(struct intel_connector *);
501 /* Panel info for eDP and LVDS */
502 struct intel_panel panel;
504 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
506 struct edid *detect_edid;
508 /* since POLL and HPD connectors may use the same HPD line keep the native
509 state of connector->polled in case hotplug storm detection changes it */
512 void *port; /* store this opaque as its illegal to dereference it */
514 struct intel_dp *mst_port;
516 /* Work struct to schedule a uevent on link train failure */
517 struct work_struct modeset_retry_work;
519 struct intel_hdcp hdcp;
522 struct intel_digital_connector_state {
523 struct drm_connector_state base;
525 enum hdmi_force_audio force_audio;
529 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
543 struct intel_atomic_state {
544 struct drm_atomic_state base;
548 * Logical state of cdclk (used for all scaling, watermark,
549 * etc. calculations and checks). This is computed as if all
550 * enabled crtcs were active.
552 struct intel_cdclk_state logical;
555 * Actual state of cdclk, can be different from the logical
556 * state only when all crtc's are DPMS off.
558 struct intel_cdclk_state actual;
561 bool dpll_set, modeset;
564 * Does this transaction change the pipes that are active? This mask
565 * tracks which CRTC's have changed their active state at the end of
566 * the transaction (not counting the temporary disable during modesets).
567 * This mask should only be non-zero when intel_state->modeset is true,
568 * but the converse is not necessarily true; simply changing a mode may
569 * not flip the final active status of any CRTC's
571 unsigned int active_pipe_changes;
573 unsigned int active_crtcs;
574 /* minimum acceptable cdclk for each pipe */
575 int min_cdclk[I915_MAX_PIPES];
576 /* minimum acceptable voltage level for each pipe */
577 u8 min_voltage_level[I915_MAX_PIPES];
579 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
582 * Current watermarks can't be trusted during hardware readout, so
583 * don't bother calculating intermediate watermarks.
585 bool skip_intermediate_wm;
587 bool rps_interactive;
590 struct skl_ddb_values wm_results;
592 struct i915_sw_fence commit_ready;
594 struct llist_node freed;
597 struct intel_plane_state {
598 struct drm_plane_state base;
599 struct i915_ggtt_view view;
600 struct i915_vma *vma;
602 #define PLANE_HAS_FENCE BIT(0)
608 * bytes for 0/180 degree rotation
609 * pixels for 90/270 degree rotation
615 /* plane control register */
618 /* plane color control register */
623 * = -1 : not using a scaler
624 * >= 0 : using a scalers
626 * plane requiring a scaler:
627 * - During check_plane, its bit is set in
628 * crtc_state->scaler_state.scaler_users by calling helper function
629 * update_scaler_plane.
630 * - scaler_id indicates the scaler it got assigned.
632 * plane doesn't require a scaler:
633 * - this can happen when scaling is no more required or plane simply
635 * - During check_plane, corresponding bit is reset in
636 * crtc_state->scaler_state.scaler_users by calling helper function
637 * update_scaler_plane.
644 * ICL planar formats require 2 planes that are updated as pairs.
645 * This member is used to make sure the other plane is also updated
646 * when required, and for update_slave() to find the correct
647 * plane_state to pass as argument.
649 struct intel_plane *linked_plane;
653 * If set don't update use the linked plane's state for updating
654 * this plane during atomic commit with the update_slave() callback.
656 * It's also used by the watermark code to ignore wm calculations on
657 * this plane. They're calculated by the linked plane's wm code.
661 struct drm_intel_sprite_colorkey ckey;
664 struct intel_initial_plane_config {
665 struct intel_framebuffer *fb;
672 #define SKL_MIN_SRC_W 8
673 #define SKL_MAX_SRC_W 4096
674 #define SKL_MIN_SRC_H 8
675 #define SKL_MAX_SRC_H 4096
676 #define SKL_MIN_DST_W 8
677 #define SKL_MAX_DST_W 4096
678 #define SKL_MIN_DST_H 8
679 #define SKL_MAX_DST_H 4096
680 #define ICL_MAX_SRC_W 5120
681 #define ICL_MAX_SRC_H 4096
682 #define ICL_MAX_DST_W 5120
683 #define ICL_MAX_DST_H 4096
684 #define SKL_MIN_YUV_420_SRC_W 16
685 #define SKL_MIN_YUV_420_SRC_H 16
687 struct intel_scaler {
692 struct intel_crtc_scaler_state {
693 #define SKL_NUM_SCALERS 2
694 struct intel_scaler scalers[SKL_NUM_SCALERS];
697 * scaler_users: keeps track of users requesting scalers on this crtc.
699 * If a bit is set, a user is using a scaler.
700 * Here user can be a plane or crtc as defined below:
701 * bits 0-30 - plane (bit position is index from drm_plane_index)
704 * Instead of creating a new index to cover planes and crtc, using
705 * existing drm_plane_index for planes which is well less than 31
706 * planes and bit 31 for crtc. This should be fine to cover all
709 * intel_atomic_setup_scalers will setup available scalers to users
710 * requesting scalers. It will gracefully fail if request exceeds
713 #define SKL_CRTC_INDEX 31
714 unsigned scaler_users;
716 /* scaler used by crtc for panel fitting purpose */
720 /* drm_mode->private_flags */
721 #define I915_MODE_FLAG_INHERITED (1<<0)
722 /* Flag to get scanline using frame time stamps */
723 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
724 /* Flag to use the scanline counter instead of the pixel counter */
725 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
727 struct intel_pipe_wm {
728 struct intel_wm_level wm[5];
732 bool sprites_enabled;
736 struct skl_plane_wm {
737 struct skl_wm_level wm[8];
738 struct skl_wm_level uv_wm[8];
739 struct skl_wm_level trans_wm;
744 struct skl_plane_wm planes[I915_MAX_PLANES];
751 VLV_WM_LEVEL_DDR_DVFS,
755 struct vlv_wm_state {
756 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
757 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
762 struct vlv_fifo_state {
763 u16 plane[I915_MAX_PLANES];
773 struct g4x_wm_state {
774 struct g4x_pipe_wm wm;
776 struct g4x_sr_wm hpll;
782 struct intel_crtc_wm_state {
786 * Intermediate watermarks; these can be
787 * programmed immediately since they satisfy
788 * both the current configuration we're
789 * switching away from and the new
790 * configuration we're switching to.
792 struct intel_pipe_wm intermediate;
795 * Optimal watermarks, programmed post-vblank
796 * when this state is committed.
798 struct intel_pipe_wm optimal;
802 /* gen9+ only needs 1-step wm programming */
803 struct skl_pipe_wm optimal;
804 struct skl_ddb_entry ddb;
805 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
806 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
810 /* "raw" watermarks (not inverted) */
811 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
812 /* intermediate watermarks (inverted) */
813 struct vlv_wm_state intermediate;
814 /* optimal watermarks (inverted) */
815 struct vlv_wm_state optimal;
816 /* display FIFO split */
817 struct vlv_fifo_state fifo_state;
821 /* "raw" watermarks */
822 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
823 /* intermediate watermarks */
824 struct g4x_wm_state intermediate;
825 /* optimal watermarks */
826 struct g4x_wm_state optimal;
831 * Platforms with two-step watermark programming will need to
832 * update watermark programming post-vblank to switch from the
833 * safe intermediate watermarks to the optimal final
836 bool need_postvbl_update;
839 enum intel_output_format {
840 INTEL_OUTPUT_FORMAT_INVALID,
841 INTEL_OUTPUT_FORMAT_RGB,
842 INTEL_OUTPUT_FORMAT_YCBCR420,
843 INTEL_OUTPUT_FORMAT_YCBCR444,
846 struct intel_crtc_state {
847 struct drm_crtc_state base;
850 * quirks - bitfield with hw state readout quirks
852 * For various reasons the hw state readout code might not be able to
853 * completely faithfully read out the current state. These cases are
854 * tracked with quirk flags so that fastboot and state checker can act
857 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
858 unsigned long quirks;
860 unsigned fb_bits; /* framebuffers to flip */
861 bool update_pipe; /* can a fast modeset be performed? */
863 bool update_wm_pre, update_wm_post; /* watermarks are updated */
864 bool fb_changed; /* fb on any of the planes is changed */
865 bool fifo_changed; /* FIFO split is changed */
867 /* Pipe source size (ie. panel fitter input size)
868 * All planes will be positioned inside this space,
869 * and get clipped at the edges. */
870 int pipe_src_w, pipe_src_h;
873 * Pipe pixel rate, adjusted for
874 * panel fitter/pipe scaler downscaling.
876 unsigned int pixel_rate;
878 /* Whether to set up the PCH/FDI. Note that we never allow sharing
879 * between pch encoders and cpu encoders. */
880 bool has_pch_encoder;
882 /* Are we sending infoframes on the attached port */
885 /* CPU Transcoder for the pipe. Currently this can only differ from the
886 * pipe on Haswell and later (where we have a special eDP transcoder)
887 * and Broxton (where we have special DSI transcoders). */
888 enum transcoder cpu_transcoder;
891 * Use reduced/limited/broadcast rbg range, compressing from the full
892 * range fed into the crtcs.
894 bool limited_color_range;
896 /* Bitmask of encoder types (enum intel_output_type)
897 * driven by the pipe.
899 unsigned int output_types;
901 /* Whether we should send NULL infoframes. Required for audio. */
904 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
905 * has_dp_encoder is set. */
909 * Enable dithering, used when the selected pipe bpp doesn't match the
915 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
916 * compliance video pattern tests.
917 * Disable dither only if it is a compliance test request for
920 bool dither_force_disable;
922 /* Controls for the clock computation, to override various stages. */
925 /* SDVO TV has a bunch of special case. To make multifunction encoders
926 * work correctly, we need to track this at runtime.*/
930 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
931 * required. This is set in the 2nd loop of calling encoder's
932 * ->compute_config if the first pick doesn't work out.
936 /* Settings for the intel dpll used on pretty much everything but
940 /* Selected dpll when shared or NULL. */
941 struct intel_shared_dpll *shared_dpll;
943 /* Actual register state of the dpll, for shared dpll cross-checking. */
944 struct intel_dpll_hw_state dpll_hw_state;
946 /* DSI PLL registers */
952 struct intel_link_m_n dp_m_n;
954 /* m2_n2 for eDP downclock */
955 struct intel_link_m_n dp_m2_n2;
962 * Frequence the dpll for the port should run at. Differs from the
963 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
964 * already multiplied by pixel_multiplier.
968 /* Used by SDVO (and if we ever fix it, HDMI). */
969 unsigned pixel_multiplier;
974 * Used by platforms having DP/HDMI PHY with programmable lane
975 * latency optimization.
977 u8 lane_lat_optim_mask;
979 /* minimum acceptable voltage level */
980 u8 min_voltage_level;
982 /* Panel fitter controls for gen2-gen4 + VLV */
986 u32 lvds_border_bits;
989 /* Panel fitter placement and size for Ironlake+ */
997 /* FDI configuration, only valid if has_pch_encoder is set. */
999 struct intel_link_m_n fdi_m_n;
1011 struct intel_crtc_scaler_state scaler_state;
1013 /* w/a for waiting 2 vblanks during crtc enable */
1014 enum pipe hsw_workaround_pipe;
1016 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1019 struct intel_crtc_wm_state wm;
1021 /* Gamma mode programmed on the pipe */
1025 /* CSC mode programmed on the pipe */
1032 /* bitmask of visible planes (enum plane_id) */
1037 /* bitmask of planes that will be updated during the commit */
1043 union hdmi_infoframe avi;
1044 union hdmi_infoframe spd;
1045 union hdmi_infoframe hdmi;
1048 /* HDMI scrambling status */
1049 bool hdmi_scrambling;
1051 /* HDMI High TMDS char rate ratio */
1052 bool hdmi_high_tmds_clock_ratio;
1054 /* Output format RGB/YCBCR etc */
1055 enum intel_output_format output_format;
1057 /* Output down scaling is done in LSPCON device */
1058 bool lspcon_downsampling;
1060 /* enable pipe gamma? */
1063 /* enable pipe csc? */
1066 /* Display Stream compression state */
1068 bool compression_enable;
1073 struct drm_dsc_config dp_dsc_cfg;
1075 /* Forward Error correction State */
1080 struct drm_crtc base;
1083 * Whether the crtc and the connected output pipeline is active. Implies
1084 * that crtc->enabled is set, i.e. the current mode configuration has
1085 * some outputs connected to this crtc.
1089 unsigned long long enabled_power_domains;
1090 struct intel_overlay *overlay;
1092 struct intel_crtc_state *config;
1094 /* Access to these should be protected by dev_priv->irq_lock. */
1095 bool cpu_fifo_underrun_disabled;
1096 bool pch_fifo_underrun_disabled;
1098 /* per-pipe watermark state */
1100 /* watermarks currently being used */
1102 struct intel_pipe_wm ilk;
1103 struct vlv_wm_state vlv;
1104 struct g4x_wm_state g4x;
1108 int scanline_offset;
1111 unsigned start_vbl_count;
1112 ktime_t start_vbl_time;
1113 int min_vbl, max_vbl;
1117 /* scalers available on this crtc */
1121 struct intel_plane {
1122 struct drm_plane base;
1123 enum i9xx_plane_id i9xx_plane;
1128 u32 frontbuffer_bit;
1131 u32 base, cntl, size;
1135 * NOTE: Do not place new plane state fields here (e.g., when adding
1136 * new plane properties). New runtime state should now be placed in
1137 * the intel_plane_state structure and accessed via plane_state.
1140 unsigned int (*max_stride)(struct intel_plane *plane,
1141 u32 pixel_format, u64 modifier,
1142 unsigned int rotation);
1143 void (*update_plane)(struct intel_plane *plane,
1144 const struct intel_crtc_state *crtc_state,
1145 const struct intel_plane_state *plane_state);
1146 void (*update_slave)(struct intel_plane *plane,
1147 const struct intel_crtc_state *crtc_state,
1148 const struct intel_plane_state *plane_state);
1149 void (*disable_plane)(struct intel_plane *plane,
1150 const struct intel_crtc_state *crtc_state);
1151 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1152 int (*check_plane)(struct intel_crtc_state *crtc_state,
1153 struct intel_plane_state *plane_state);
1156 struct intel_watermark_params {
1164 struct cxsr_latency {
1165 bool is_desktop : 1;
1170 u16 display_hpll_disable;
1172 u16 cursor_hpll_disable;
1175 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1176 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1177 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1178 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1179 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1180 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1181 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1182 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1183 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1186 i915_reg_t hdmi_reg;
1189 enum drm_dp_dual_mode_type type;
1194 struct intel_connector *attached_connector;
1195 struct cec_notifier *cec_notifier;
1198 struct intel_dp_mst_encoder;
1199 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1202 * enum link_m_n_set:
1203 * When platform provides two set of M_N registers for dp, we can
1204 * program them and switch between them incase of DRRS.
1205 * But When only one such register is provided, we have to program the
1206 * required divider value on that registers itself based on the DRRS state.
1208 * M1_N1 : Program dp_m_n on M1_N1 registers
1209 * dp_m2_n2 on M2_N2 registers (If supported)
1211 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1212 * M2_N2 registers are not supported
1216 /* Sets the m1_n1 and m2_n2 */
1221 struct intel_dp_compliance_data {
1224 u16 hdisplay, vdisplay;
1228 struct intel_dp_compliance {
1229 unsigned long test_type;
1230 struct intel_dp_compliance_data test_data;
1237 i915_reg_t output_reg;
1245 bool reset_link_params;
1246 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1247 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1248 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1249 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1250 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1253 int num_source_rates;
1254 const int *source_rates;
1255 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1257 int sink_rates[DP_MAX_SUPPORTED_RATES];
1258 bool use_rate_select;
1259 /* intersection of source and sink rates */
1260 int num_common_rates;
1261 int common_rates[DP_MAX_SUPPORTED_RATES];
1262 /* Max lane count for the current link */
1263 int max_link_lane_count;
1264 /* Max rate for the current link */
1266 /* sink or branch descriptor */
1267 struct drm_dp_desc desc;
1268 struct drm_dp_aux aux;
1270 int panel_power_up_delay;
1271 int panel_power_down_delay;
1272 int panel_power_cycle_delay;
1273 int backlight_on_delay;
1274 int backlight_off_delay;
1275 struct delayed_work panel_vdd_work;
1276 bool want_panel_vdd;
1277 unsigned long last_power_on;
1278 unsigned long last_backlight_off;
1279 ktime_t panel_power_off_time;
1281 struct notifier_block edp_notifier;
1284 * Pipe whose power sequencer is currently locked into
1285 * this port. Only relevant on VLV/CHV.
1289 * Pipe currently driving the port. Used for preventing
1290 * the use of the PPS for any pipe currentrly driving
1291 * external DP as that will mess things up on VLV.
1293 enum pipe active_pipe;
1295 * Set if the sequencer may be reset due to a power transition,
1296 * requiring a reinitialization. Only relevant on BXT.
1299 struct edp_power_seq pps_delays;
1301 bool can_mst; /* this port supports mst */
1303 int active_mst_links;
1304 /* connector directly attached - won't be use for modeset in mst world */
1305 struct intel_connector *attached_connector;
1307 /* mst connector list */
1308 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1309 struct drm_dp_mst_topology_mgr mst_mgr;
1311 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1313 * This function returns the value we have to program the AUX_CTL
1314 * register with to kick off an AUX transaction.
1316 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1317 u32 aux_clock_divider);
1319 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1320 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1322 /* This is called before a link training is starterd */
1323 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1325 /* Displayport compliance testing */
1326 struct intel_dp_compliance compliance;
1328 /* Display stream compression testing */
1332 enum lspcon_vendor {
1334 LSPCON_VENDOR_PARADE
1337 struct intel_lspcon {
1339 enum drm_lspcon_mode mode;
1340 enum lspcon_vendor vendor;
1343 struct intel_digital_port {
1344 struct intel_encoder base;
1345 u32 saved_port_bits;
1347 struct intel_hdmi hdmi;
1348 struct intel_lspcon lspcon;
1349 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1350 bool release_cl2_override;
1352 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1354 enum intel_display_power_domain ddi_io_power_domain;
1355 bool tc_legacy_port:1;
1356 enum tc_port_type tc_type;
1358 void (*write_infoframe)(struct intel_encoder *encoder,
1359 const struct intel_crtc_state *crtc_state,
1361 const void *frame, ssize_t len);
1362 void (*read_infoframe)(struct intel_encoder *encoder,
1363 const struct intel_crtc_state *crtc_state,
1365 void *frame, ssize_t len);
1366 void (*set_infoframes)(struct intel_encoder *encoder,
1368 const struct intel_crtc_state *crtc_state,
1369 const struct drm_connector_state *conn_state);
1370 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1371 const struct intel_crtc_state *pipe_config);
1374 struct intel_dp_mst_encoder {
1375 struct intel_encoder base;
1377 struct intel_digital_port *primary;
1378 struct intel_connector *connector;
1381 static inline enum dpio_channel
1382 vlv_dport_to_channel(struct intel_digital_port *dport)
1384 switch (dport->base.port) {
1395 static inline enum dpio_phy
1396 vlv_dport_to_phy(struct intel_digital_port *dport)
1398 switch (dport->base.port) {
1409 static inline enum dpio_channel
1410 vlv_pipe_to_channel(enum pipe pipe)
1423 static inline struct intel_crtc *
1424 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1426 return dev_priv->pipe_to_crtc_mapping[pipe];
1429 static inline struct intel_crtc *
1430 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1432 return dev_priv->plane_to_crtc_mapping[plane];
1435 struct intel_load_detect_pipe {
1436 struct drm_atomic_state *restore_state;
1439 static inline struct intel_encoder *
1440 intel_attached_encoder(struct drm_connector *connector)
1442 return to_intel_connector(connector)->encoder;
1445 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1447 switch (encoder->type) {
1448 case INTEL_OUTPUT_DDI:
1449 case INTEL_OUTPUT_DP:
1450 case INTEL_OUTPUT_EDP:
1451 case INTEL_OUTPUT_HDMI:
1458 static inline struct intel_digital_port *
1459 enc_to_dig_port(struct drm_encoder *encoder)
1461 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1463 if (intel_encoder_is_dig_port(intel_encoder))
1464 return container_of(encoder, struct intel_digital_port,
1470 static inline struct intel_digital_port *
1471 conn_to_dig_port(struct intel_connector *connector)
1473 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1476 static inline struct intel_dp_mst_encoder *
1477 enc_to_mst(struct drm_encoder *encoder)
1479 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1482 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1484 return &enc_to_dig_port(encoder)->dp;
1487 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1489 switch (encoder->type) {
1490 case INTEL_OUTPUT_DP:
1491 case INTEL_OUTPUT_EDP:
1493 case INTEL_OUTPUT_DDI:
1494 /* Skip pure HDMI/DVI DDI encoders */
1495 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1501 static inline struct intel_lspcon *
1502 enc_to_intel_lspcon(struct drm_encoder *encoder)
1504 return &enc_to_dig_port(encoder)->lspcon;
1507 static inline struct intel_digital_port *
1508 dp_to_dig_port(struct intel_dp *intel_dp)
1510 return container_of(intel_dp, struct intel_digital_port, dp);
1513 static inline struct intel_lspcon *
1514 dp_to_lspcon(struct intel_dp *intel_dp)
1516 return &dp_to_dig_port(intel_dp)->lspcon;
1519 static inline struct drm_i915_private *
1520 dp_to_i915(struct intel_dp *intel_dp)
1522 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1525 static inline struct intel_digital_port *
1526 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1528 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1531 static inline struct intel_plane_state *
1532 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1533 struct intel_plane *plane)
1535 struct drm_plane_state *ret =
1536 drm_atomic_get_plane_state(&state->base, &plane->base);
1539 return ERR_CAST(ret);
1541 return to_intel_plane_state(ret);
1544 static inline struct intel_plane_state *
1545 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1546 struct intel_plane *plane)
1548 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1552 static inline struct intel_plane_state *
1553 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1554 struct intel_plane *plane)
1556 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1560 static inline struct intel_crtc_state *
1561 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1562 struct intel_crtc *crtc)
1564 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1568 static inline struct intel_crtc_state *
1569 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1570 struct intel_crtc *crtc)
1572 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1576 /* intel_fifo_underrun.c */
1577 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1578 enum pipe pipe, bool enable);
1579 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1580 enum pipe pch_transcoder,
1582 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1584 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1585 enum pipe pch_transcoder);
1586 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1587 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1590 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1591 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1592 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1593 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1594 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1595 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1596 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1597 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1599 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1602 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1605 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1606 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1607 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1610 * We only use drm_irq_uninstall() at unload and VT switch, so
1611 * this is the only thing we need to check.
1613 return dev_priv->runtime_pm.irqs_enabled;
1616 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1617 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1619 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1621 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1622 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1623 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1626 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1627 i915_reg_t adpa_reg, enum pipe *pipe);
1628 void intel_crt_init(struct drm_i915_private *dev_priv);
1629 void intel_crt_reset(struct drm_encoder *encoder);
1632 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1633 const struct intel_crtc_state *old_crtc_state,
1634 const struct drm_connector_state *old_conn_state);
1635 void hsw_fdi_link_train(struct intel_crtc *crtc,
1636 const struct intel_crtc_state *crtc_state);
1637 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1638 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1639 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1640 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1641 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1642 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1643 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1644 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1645 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1646 void intel_ddi_get_config(struct intel_encoder *encoder,
1647 struct intel_crtc_state *pipe_config);
1649 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1651 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1652 struct intel_crtc_state *crtc_state);
1653 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1654 u32 ddi_signal_levels(struct intel_dp *intel_dp);
1655 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1656 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1658 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1660 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1661 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1662 struct intel_dpll_hw_state *state);
1664 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1665 int color_plane, unsigned int height);
1668 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1669 void intel_audio_codec_enable(struct intel_encoder *encoder,
1670 const struct intel_crtc_state *crtc_state,
1671 const struct drm_connector_state *conn_state);
1672 void intel_audio_codec_disable(struct intel_encoder *encoder,
1673 const struct intel_crtc_state *old_crtc_state,
1674 const struct drm_connector_state *old_conn_state);
1675 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1676 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1677 void intel_audio_init(struct drm_i915_private *dev_priv);
1678 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1681 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1682 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1683 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1684 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1685 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1686 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1687 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1688 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1689 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1690 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1691 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1692 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1693 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1694 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1695 const struct intel_cdclk_state *b);
1696 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1697 const struct intel_cdclk_state *b);
1698 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1699 const struct intel_cdclk_state *cdclk_state);
1700 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1701 const char *context);
1703 /* intel_display.c */
1704 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1705 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1706 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1707 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1708 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1709 const char *name, u32 reg, int ref_freq);
1710 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1711 const char *name, u32 reg);
1712 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1713 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1714 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1715 unsigned int intel_fb_xy_to_linear(int x, int y,
1716 const struct intel_plane_state *state,
1718 void intel_add_fb_offsets(int *x, int *y,
1719 const struct intel_plane_state *state, int plane);
1720 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1721 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1722 void intel_mark_busy(struct drm_i915_private *dev_priv);
1723 void intel_mark_idle(struct drm_i915_private *dev_priv);
1724 int intel_display_suspend(struct drm_device *dev);
1725 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1726 void intel_encoder_destroy(struct drm_encoder *encoder);
1727 struct drm_display_mode *
1728 intel_encoder_current_mode(struct intel_encoder *encoder);
1729 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1730 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1731 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1733 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1734 struct drm_file *file_priv);
1735 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1738 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1739 enum intel_output_type type)
1741 return crtc_state->output_types & (1 << type);
1744 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1746 return crtc_state->output_types &
1747 ((1 << INTEL_OUTPUT_DP) |
1748 (1 << INTEL_OUTPUT_DP_MST) |
1749 (1 << INTEL_OUTPUT_EDP));
1752 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1754 drm_wait_one_vblank(&dev_priv->drm, pipe);
1757 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1759 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1762 intel_wait_for_vblank(dev_priv, pipe);
1765 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1767 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1768 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1769 struct intel_digital_port *dport,
1770 unsigned int expected_mask);
1771 int intel_get_load_detect_pipe(struct drm_connector *connector,
1772 const struct drm_display_mode *mode,
1773 struct intel_load_detect_pipe *old,
1774 struct drm_modeset_acquire_ctx *ctx);
1775 void intel_release_load_detect_pipe(struct drm_connector *connector,
1776 struct intel_load_detect_pipe *old,
1777 struct drm_modeset_acquire_ctx *ctx);
1779 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1780 const struct i915_ggtt_view *view,
1782 unsigned long *out_flags);
1783 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1784 struct drm_framebuffer *
1785 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1786 struct drm_mode_fb_cmd2 *mode_cmd);
1787 int intel_prepare_plane_fb(struct drm_plane *plane,
1788 struct drm_plane_state *new_state);
1789 void intel_cleanup_plane_fb(struct drm_plane *plane,
1790 struct drm_plane_state *old_state);
1791 int intel_plane_atomic_get_property(struct drm_plane *plane,
1792 const struct drm_plane_state *state,
1793 struct drm_property *property,
1795 int intel_plane_atomic_set_property(struct drm_plane *plane,
1796 struct drm_plane_state *state,
1797 struct drm_property *property,
1799 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1800 struct drm_crtc_state *crtc_state,
1801 const struct intel_plane_state *old_plane_state,
1802 struct drm_plane_state *plane_state);
1804 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1807 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1808 const struct dpll *dpll);
1809 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1810 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1812 /* modesetting asserts */
1813 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1815 void assert_pll(struct drm_i915_private *dev_priv,
1816 enum pipe pipe, bool state);
1817 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1818 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1819 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1820 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1821 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1822 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1823 enum pipe pipe, bool state);
1824 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1825 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1826 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1827 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1828 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1829 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1830 void intel_finish_reset(struct drm_i915_private *dev_priv);
1831 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1832 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1833 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1834 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1835 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1836 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1837 unsigned int skl_cdclk_get_vco(unsigned int freq);
1838 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1839 void intel_dp_get_m_n(struct intel_crtc *crtc,
1840 struct intel_crtc_state *pipe_config);
1841 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1842 enum link_m_n_set m_n);
1843 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1844 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1845 struct dpll *best_clock);
1846 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1848 bool intel_crtc_active(struct intel_crtc *crtc);
1849 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1850 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1851 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1852 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1853 enum intel_display_power_domain
1854 intel_aux_power_domain(struct intel_digital_port *dig_port);
1855 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1856 struct intel_crtc_state *pipe_config);
1857 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1858 struct intel_crtc_state *crtc_state);
1860 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1861 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1862 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1865 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1867 return i915_ggtt_offset(state->vma);
1870 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1871 const struct intel_plane_state *plane_state);
1872 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1873 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1874 const struct intel_plane_state *plane_state);
1875 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1876 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1878 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1879 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1880 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1881 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1882 u32 pixel_format, u64 modifier,
1883 unsigned int rotation);
1885 /* intel_connector.c */
1886 int intel_connector_init(struct intel_connector *connector);
1887 struct intel_connector *intel_connector_alloc(void);
1888 void intel_connector_free(struct intel_connector *connector);
1889 void intel_connector_destroy(struct drm_connector *connector);
1890 int intel_connector_register(struct drm_connector *connector);
1891 void intel_connector_unregister(struct drm_connector *connector);
1892 void intel_connector_attach_encoder(struct intel_connector *connector,
1893 struct intel_encoder *encoder);
1894 bool intel_connector_get_hw_state(struct intel_connector *connector);
1895 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1896 int intel_connector_update_modes(struct drm_connector *connector,
1898 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1899 void intel_attach_force_audio_property(struct drm_connector *connector);
1900 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1901 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1904 void intel_csr_ucode_init(struct drm_i915_private *);
1905 void intel_csr_load_program(struct drm_i915_private *);
1906 void intel_csr_ucode_fini(struct drm_i915_private *);
1907 void intel_csr_ucode_suspend(struct drm_i915_private *);
1908 void intel_csr_ucode_resume(struct drm_i915_private *);
1911 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1912 i915_reg_t dp_reg, enum port port,
1914 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1916 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1917 struct intel_connector *intel_connector);
1918 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1919 int link_rate, u8 lane_count,
1921 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1922 int link_rate, u8 lane_count);
1923 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1924 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1925 int intel_dp_retrain_link(struct intel_encoder *encoder,
1926 struct drm_modeset_acquire_ctx *ctx);
1927 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1928 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1929 const struct intel_crtc_state *crtc_state,
1931 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1932 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1933 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
1934 int intel_dp_compute_config(struct intel_encoder *encoder,
1935 struct intel_crtc_state *pipe_config,
1936 struct drm_connector_state *conn_state);
1937 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1938 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1939 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1941 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1942 const struct drm_connector_state *conn_state);
1943 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1944 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1945 void intel_edp_panel_on(struct intel_dp *intel_dp);
1946 void intel_edp_panel_off(struct intel_dp *intel_dp);
1947 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1948 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1949 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1950 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1951 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1952 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1953 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1954 u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
1955 void intel_plane_destroy(struct drm_plane *plane);
1956 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1957 const struct intel_crtc_state *crtc_state);
1958 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1959 const struct intel_crtc_state *crtc_state);
1960 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1961 unsigned int frontbuffer_bits);
1962 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1963 unsigned int frontbuffer_bits);
1966 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1969 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1970 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1972 intel_dp_voltage_max(struct intel_dp *intel_dp);
1974 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
1975 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1976 u8 *link_bw, u8 *rate_select);
1977 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1978 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1980 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]);
1981 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
1982 int mode_clock, int mode_hdisplay);
1983 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1987 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1988 struct intel_crtc_state *pipe_config);
1989 enum intel_display_power_domain
1990 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
1992 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1994 return ~((1 << lane_count) - 1) & 0xf;
1997 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1998 int intel_dp_link_required(int pixel_clock, int bpp);
1999 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
2000 bool intel_digital_port_connected(struct intel_encoder *encoder);
2001 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
2002 struct intel_digital_port *dig_port);
2004 /* intel_dp_aux_backlight.c */
2005 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
2007 /* intel_dp_mst.c */
2008 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
2009 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
2011 void vlv_dsi_init(struct drm_i915_private *dev_priv);
2014 void icl_dsi_init(struct drm_i915_private *dev_priv);
2016 /* intel_dsi_dcs_backlight.c */
2017 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
2020 void intel_dvo_init(struct drm_i915_private *dev_priv);
2021 /* intel_hotplug.c */
2022 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
2023 bool intel_encoder_hotplug(struct intel_encoder *encoder,
2024 struct intel_connector *connector);
2026 /* legacy fbdev emulation in intel_fbdev.c */
2027 #ifdef CONFIG_DRM_FBDEV_EMULATION
2028 extern int intel_fbdev_init(struct drm_device *dev);
2029 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
2030 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
2031 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
2032 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
2033 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
2034 extern void intel_fbdev_restore_mode(struct drm_device *dev);
2036 static inline int intel_fbdev_init(struct drm_device *dev)
2041 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
2045 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
2049 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
2053 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
2057 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
2061 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
2067 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
2068 struct intel_atomic_state *state);
2069 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
2070 void intel_fbc_pre_update(struct intel_crtc *crtc,
2071 struct intel_crtc_state *crtc_state,
2072 struct intel_plane_state *plane_state);
2073 void intel_fbc_post_update(struct intel_crtc *crtc);
2074 void intel_fbc_init(struct drm_i915_private *dev_priv);
2075 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
2076 void intel_fbc_enable(struct intel_crtc *crtc,
2077 struct intel_crtc_state *crtc_state,
2078 struct intel_plane_state *plane_state);
2079 void intel_fbc_disable(struct intel_crtc *crtc);
2080 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
2081 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
2082 unsigned int frontbuffer_bits,
2083 enum fb_op_origin origin);
2084 void intel_fbc_flush(struct drm_i915_private *dev_priv,
2085 unsigned int frontbuffer_bits, enum fb_op_origin origin);
2086 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
2087 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
2088 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
2091 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
2093 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2094 struct intel_connector *intel_connector);
2095 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
2096 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2097 struct intel_crtc_state *pipe_config,
2098 struct drm_connector_state *conn_state);
2099 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2100 struct drm_connector *connector,
2101 bool high_tmds_clock_ratio,
2103 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
2104 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
2105 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
2106 const struct intel_crtc_state *crtc_state);
2107 u32 intel_hdmi_infoframe_enable(unsigned int type);
2108 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
2109 struct intel_crtc_state *crtc_state);
2110 void intel_read_infoframe(struct intel_encoder *encoder,
2111 const struct intel_crtc_state *crtc_state,
2112 enum hdmi_infoframe_type type,
2113 union hdmi_infoframe *frame);
2116 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
2117 i915_reg_t lvds_reg, enum pipe *pipe);
2118 void intel_lvds_init(struct drm_i915_private *dev_priv);
2119 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv);
2120 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv);
2122 /* intel_overlay.c */
2123 void intel_overlay_setup(struct drm_i915_private *dev_priv);
2124 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
2125 int intel_overlay_switch_off(struct intel_overlay *overlay);
2126 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
2127 struct drm_file *file_priv);
2128 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
2129 struct drm_file *file_priv);
2130 void intel_overlay_reset(struct drm_i915_private *dev_priv);
2134 int intel_panel_init(struct intel_panel *panel,
2135 struct drm_display_mode *fixed_mode,
2136 struct drm_display_mode *downclock_mode);
2137 void intel_panel_fini(struct intel_panel *panel);
2138 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2139 struct drm_display_mode *adjusted_mode);
2140 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2141 struct intel_crtc_state *pipe_config,
2143 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2144 struct intel_crtc_state *pipe_config,
2146 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2147 u32 level, u32 max);
2148 int intel_panel_setup_backlight(struct drm_connector *connector,
2150 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2151 const struct drm_connector_state *conn_state);
2152 void intel_panel_update_backlight(struct intel_encoder *encoder,
2153 const struct intel_crtc_state *crtc_state,
2154 const struct drm_connector_state *conn_state);
2155 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2156 struct drm_display_mode *
2157 intel_panel_edid_downclock_mode(struct intel_connector *connector,
2158 const struct drm_display_mode *fixed_mode);
2159 struct drm_display_mode *
2160 intel_panel_edid_fixed_mode(struct intel_connector *connector);
2161 struct drm_display_mode *
2162 intel_panel_vbt_fixed_mode(struct intel_connector *connector);
2164 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2165 int intel_backlight_device_register(struct intel_connector *connector);
2166 void intel_backlight_device_unregister(struct intel_connector *connector);
2167 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2168 static inline int intel_backlight_device_register(struct intel_connector *connector)
2172 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2175 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2178 void intel_hdcp_atomic_check(struct drm_connector *connector,
2179 struct drm_connector_state *old_state,
2180 struct drm_connector_state *new_state);
2181 int intel_hdcp_init(struct intel_connector *connector,
2182 const struct intel_hdcp_shim *hdcp_shim);
2183 int intel_hdcp_enable(struct intel_connector *connector);
2184 int intel_hdcp_disable(struct intel_connector *connector);
2185 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2186 bool intel_hdcp_capable(struct intel_connector *connector);
2187 void intel_hdcp_component_init(struct drm_i915_private *dev_priv);
2188 void intel_hdcp_component_fini(struct drm_i915_private *dev_priv);
2189 void intel_hdcp_cleanup(struct intel_connector *connector);
2190 void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
2193 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2194 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2195 void intel_psr_enable(struct intel_dp *intel_dp,
2196 const struct intel_crtc_state *crtc_state);
2197 void intel_psr_disable(struct intel_dp *intel_dp,
2198 const struct intel_crtc_state *old_crtc_state);
2199 void intel_psr_update(struct intel_dp *intel_dp,
2200 const struct intel_crtc_state *crtc_state);
2201 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
2202 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2203 unsigned frontbuffer_bits,
2204 enum fb_op_origin origin);
2205 void intel_psr_flush(struct drm_i915_private *dev_priv,
2206 unsigned frontbuffer_bits,
2207 enum fb_op_origin origin);
2208 void intel_psr_init(struct drm_i915_private *dev_priv);
2209 void intel_psr_compute_config(struct intel_dp *intel_dp,
2210 struct intel_crtc_state *crtc_state);
2211 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2212 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2213 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2214 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2216 bool intel_psr_enabled(struct intel_dp *intel_dp);
2218 /* intel_quirks.c */
2219 void intel_init_quirks(struct drm_i915_private *dev_priv);
2221 /* intel_runtime_pm.c */
2222 void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv);
2223 int intel_power_domains_init(struct drm_i915_private *);
2224 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2225 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2226 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2227 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2228 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2229 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2230 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2232 enum i915_drm_suspend_mode {
2233 I915_DRM_SUSPEND_IDLE,
2234 I915_DRM_SUSPEND_MEM,
2235 I915_DRM_SUSPEND_HIBERNATE,
2238 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2239 enum i915_drm_suspend_mode);
2240 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2241 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2242 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2243 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2244 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2245 void intel_runtime_pm_cleanup(struct drm_i915_private *dev_priv);
2247 intel_display_power_domain_str(enum intel_display_power_domain domain);
2249 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2250 enum intel_display_power_domain domain);
2251 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2252 enum intel_display_power_domain domain);
2253 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
2254 enum intel_display_power_domain domain);
2256 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2257 enum intel_display_power_domain domain);
2258 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
2259 enum intel_display_power_domain domain);
2260 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2261 void intel_display_power_put(struct drm_i915_private *dev_priv,
2262 enum intel_display_power_domain domain,
2263 intel_wakeref_t wakeref);
2265 #define intel_display_power_put(i915, domain, wakeref) \
2266 intel_display_power_put_unchecked(i915, domain)
2268 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2272 assert_rpm_device_not_suspended(struct i915_runtime_pm *rpm)
2274 WARN_ONCE(rpm->suspended,
2275 "Device suspended during HW access\n");
2279 __assert_rpm_wakelock_held(struct i915_runtime_pm *rpm)
2281 assert_rpm_device_not_suspended(rpm);
2282 WARN_ONCE(!atomic_read(&rpm->wakeref_count),
2283 "RPM wakelock ref not held during HW access");
2287 assert_rpm_wakelock_held(struct drm_i915_private *i915)
2289 __assert_rpm_wakelock_held(&i915->runtime_pm);
2293 * disable_rpm_wakeref_asserts - disable the RPM assert checks
2294 * @i915: i915 device instance
2296 * This function disable asserts that check if we hold an RPM wakelock
2297 * reference, while keeping the device-not-suspended checks still enabled.
2298 * It's meant to be used only in special circumstances where our rule about
2299 * the wakelock refcount wrt. the device power state doesn't hold. According
2300 * to this rule at any point where we access the HW or want to keep the HW in
2301 * an active state we must hold an RPM wakelock reference acquired via one of
2302 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2303 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2304 * forcewake release timer, and the GPU RPS and hangcheck works. All other
2305 * users should avoid using this function.
2307 * Any calls to this function must have a symmetric call to
2308 * enable_rpm_wakeref_asserts().
2311 disable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2313 atomic_inc(&i915->runtime_pm.wakeref_count);
2317 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2318 * @i915: i915 device instance
2320 * This function re-enables the RPM assert checks after disabling them with
2321 * disable_rpm_wakeref_asserts. It's meant to be used only in special
2322 * circumstances otherwise its use should be avoided.
2324 * Any calls to this function must have a symmetric call to
2325 * disable_rpm_wakeref_asserts().
2328 enable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2330 atomic_dec(&i915->runtime_pm.wakeref_count);
2333 intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915);
2334 intel_wakeref_t intel_runtime_pm_get_if_in_use(struct drm_i915_private *i915);
2335 intel_wakeref_t intel_runtime_pm_get_noresume(struct drm_i915_private *i915);
2337 #define with_intel_runtime_pm(i915, wf) \
2338 for ((wf) = intel_runtime_pm_get(i915); (wf); \
2339 intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2341 #define with_intel_runtime_pm_if_in_use(i915, wf) \
2342 for ((wf) = intel_runtime_pm_get_if_in_use(i915); (wf); \
2343 intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2345 void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915);
2346 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2347 void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref);
2349 #define intel_runtime_pm_put(i915, wref) intel_runtime_pm_put_unchecked(i915)
2352 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2353 void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2354 struct drm_printer *p);
2356 static inline void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2357 struct drm_printer *p)
2362 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2363 bool override, unsigned int mask);
2364 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2365 enum dpio_channel ch, bool override);
2369 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2370 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2371 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2372 void intel_update_watermarks(struct intel_crtc *crtc);
2373 void intel_init_pm(struct drm_i915_private *dev_priv);
2374 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2375 void intel_pm_setup(struct drm_i915_private *dev_priv);
2376 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2377 void intel_gpu_ips_teardown(void);
2378 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2379 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2380 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2381 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2382 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2383 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2384 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2385 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2386 void gen6_rps_boost(struct i915_request *rq);
2387 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
2388 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
2389 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
2390 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
2391 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2392 struct skl_ddb_entry *ddb_y,
2393 struct skl_ddb_entry *ddb_uv);
2394 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2395 struct skl_ddb_allocation *ddb /* out */);
2396 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
2397 struct skl_pipe_wm *out);
2398 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2399 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2400 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2401 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2402 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2403 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2404 const struct skl_wm_level *l2);
2405 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2406 const struct skl_ddb_entry entries[],
2407 int num_entries, int ignore_idx);
2408 void skl_write_plane_wm(struct intel_plane *plane,
2409 const struct intel_crtc_state *crtc_state);
2410 void skl_write_cursor_wm(struct intel_plane *plane,
2411 const struct intel_crtc_state *crtc_state);
2412 bool ilk_disable_lp_wm(struct drm_device *dev);
2413 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2414 struct intel_crtc_state *cstate);
2415 void intel_init_ipc(struct drm_i915_private *dev_priv);
2416 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2419 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2420 i915_reg_t sdvo_reg, enum pipe *pipe);
2421 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2422 i915_reg_t reg, enum port port);
2425 /* intel_sprite.c */
2426 bool is_planar_yuv_format(u32 pixelformat);
2427 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2429 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2430 enum pipe pipe, int plane);
2431 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2432 struct drm_file *file_priv);
2433 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2434 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2435 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2436 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2437 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2438 struct intel_plane *
2439 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2440 enum pipe pipe, enum plane_id plane_id);
2442 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2444 /* Don't need to do a gen check, these planes are only available on gen11 */
2445 if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2451 static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
2452 enum plane_id plane_id)
2454 if (INTEL_GEN(dev_priv) < 11)
2457 return plane_id < PLANE_SPRITE2;
2461 void intel_tv_init(struct drm_i915_private *dev_priv);
2463 /* intel_atomic.c */
2464 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2465 const struct drm_connector_state *state,
2466 struct drm_property *property,
2468 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2469 struct drm_connector_state *state,
2470 struct drm_property *property,
2472 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2473 struct drm_connector_state *new_state);
2474 struct drm_connector_state *
2475 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2477 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2478 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2479 struct drm_crtc_state *state);
2480 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2481 void intel_atomic_state_clear(struct drm_atomic_state *);
2483 static inline struct intel_crtc_state *
2484 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2485 struct intel_crtc *crtc)
2487 struct drm_crtc_state *crtc_state;
2488 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2489 if (IS_ERR(crtc_state))
2490 return ERR_CAST(crtc_state);
2492 return to_intel_crtc_state(crtc_state);
2495 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2496 struct intel_crtc *intel_crtc,
2497 struct intel_crtc_state *crtc_state);
2499 /* intel_atomic_plane.c */
2500 void intel_update_plane(struct intel_plane *plane,
2501 const struct intel_crtc_state *crtc_state,
2502 const struct intel_plane_state *plane_state);
2503 void intel_update_slave(struct intel_plane *plane,
2504 const struct intel_crtc_state *crtc_state,
2505 const struct intel_plane_state *plane_state);
2506 void intel_disable_plane(struct intel_plane *plane,
2507 const struct intel_crtc_state *crtc_state);
2508 struct intel_plane *intel_plane_alloc(void);
2509 void intel_plane_free(struct intel_plane *plane);
2510 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2511 void intel_plane_destroy_state(struct drm_plane *plane,
2512 struct drm_plane_state *state);
2513 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2514 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2515 struct intel_crtc *crtc);
2516 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2517 struct intel_crtc *crtc);
2518 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2519 struct intel_crtc_state *crtc_state,
2520 const struct intel_plane_state *old_plane_state,
2521 struct intel_plane_state *intel_state);
2524 void intel_color_init(struct intel_crtc *crtc);
2525 int intel_color_check(struct intel_crtc_state *crtc_state);
2526 void intel_color_commit(const struct intel_crtc_state *crtc_state);
2527 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
2529 /* intel_lspcon.c */
2530 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2531 void lspcon_resume(struct intel_lspcon *lspcon);
2532 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2533 void lspcon_write_infoframe(struct intel_encoder *encoder,
2534 const struct intel_crtc_state *crtc_state,
2536 const void *buf, ssize_t len);
2537 void lspcon_read_infoframe(struct intel_encoder *encoder,
2538 const struct intel_crtc_state *crtc_state,
2540 void *frame, ssize_t len);
2541 void lspcon_set_infoframes(struct intel_encoder *encoder,
2543 const struct intel_crtc_state *crtc_state,
2544 const struct drm_connector_state *conn_state);
2545 u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
2546 const struct intel_crtc_state *pipe_config);
2547 void lspcon_ycbcr420_config(struct drm_connector *connector,
2548 struct intel_crtc_state *crtc_state);
2550 /* intel_pipe_crc.c */
2551 #ifdef CONFIG_DEBUG_FS
2552 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2553 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2554 const char *source_name, size_t *values_cnt);
2555 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2557 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2558 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2560 #define intel_crtc_set_crc_source NULL
2561 #define intel_crtc_verify_crc_source NULL
2562 #define intel_crtc_get_crc_sources NULL
2563 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2567 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2571 #endif /* __INTEL_DRV_H__ */