drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  *
  51  * TODO: When modesetting has fully transitioned to atomic, the below
  52  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  53  * added.
  54  */
  55 #define _wait_for(COND, US, W) ({ \
  56         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  57         int ret__;                                                      \
  58         for (;;) {                                                      \
  59                 bool expired__ = time_after(jiffies, timeout__);        \
  60                 if (COND) {                                             \
  61                         ret__ = 0;                                      \
  62                         break;                                          \
  63                 }                                                       \
  64                 if (expired__) {                                        \
  65                         ret__ = -ETIMEDOUT;                             \
  66                         break;                                          \
  67                 }                                                       \
  68                 if ((W) && drm_can_sleep()) {                           \
  69                         usleep_range((W), (W)*2);                       \
  70                 } else {                                                \
  71                         cpu_relax();                                    \
  72                 }                                                       \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  78
  79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  82 #else
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  84 #endif
  85
  86 #define _wait_for_atomic(COND, US, ATOMIC) \
  87 ({ \
  88         int cpu, ret, timeout = (US) * 1000; \
  89         u64 base; \
  90         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  91         if (!(ATOMIC)) { \
  92                 preempt_disable(); \
  93                 cpu = smp_processor_id(); \
  94         } \
  95         base = local_clock(); \
  96         for (;;) { \
  97                 u64 now = local_clock(); \
  98                 if (!(ATOMIC)) \
  99                         preempt_enable(); \
 100                 if (COND) { \
 101                         ret = 0; \
 102                         break; \
 103                 } \
 104                 if (now - base >= timeout) { \
 105                         ret = -ETIMEDOUT; \
 106                         break; \
 107                 } \
 108                 cpu_relax(); \
 109                 if (!(ATOMIC)) { \
 110                         preempt_disable(); \
 111                         if (unlikely(cpu != smp_processor_id())) { \
 112                                 timeout -= now - base; \
 113                                 cpu = smp_processor_id(); \
 114                                 base = local_clock(); \
 115                         } \
 116                 } \
 117         } \
 118         ret; \
 119 })
 120
 121 #define wait_for_us(COND, US) \
 122 ({ \
 123         int ret__; \
 124         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 125         if ((US) > 10) \
 126                 ret__ = _wait_for((COND), (US), 10); \
 127         else \
 128                 ret__ = _wait_for_atomic((COND), (US), 0); \
 129         ret__; \
 130 })
 131
 132 #define wait_for_atomic_us(COND, US) \
 133 ({ \
 134         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 135         BUILD_BUG_ON((US) > 50000); \
 136         _wait_for_atomic((COND), (US), 1); \
 137 })
 138
 139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 140
 141 #define KHz(x) (1000 * (x))
 142 #define MHz(x) KHz(1000 * (x))
 143
 144 /*
 145  * Display related stuff
 146  */
 147
 148 /* store information about an Ixxx DVO */
 149 /* The i830->i865 use multiple DVOs with multiple i2cs */
 150 /* the i915, i945 have a single sDVO i2c bus - which is different */
 151 #define MAX_OUTPUTS 6
 152 /* maximum connectors per crtcs in the mode set */
 153
 154 /* Maximum cursor sizes */
 155 #define GEN2_CURSOR_WIDTH 64
 156 #define GEN2_CURSOR_HEIGHT 64
 157 #define MAX_CURSOR_WIDTH 256
 158 #define MAX_CURSOR_HEIGHT 256
 159
 160 #define INTEL_I2C_BUS_DVO 1
 161 #define INTEL_I2C_BUS_SDVO 2
 162
 163 /* these are outputs from the chip - integrated only
 164    external chips are via DVO or SDVO output */
 165 enum intel_output_type {
 166         INTEL_OUTPUT_UNUSED = 0,
 167         INTEL_OUTPUT_ANALOG = 1,
 168         INTEL_OUTPUT_DVO = 2,
 169         INTEL_OUTPUT_SDVO = 3,
 170         INTEL_OUTPUT_LVDS = 4,
 171         INTEL_OUTPUT_TVOUT = 5,
 172         INTEL_OUTPUT_HDMI = 6,
 173         INTEL_OUTPUT_DP = 7,
 174         INTEL_OUTPUT_EDP = 8,
 175         INTEL_OUTPUT_DSI = 9,
 176         INTEL_OUTPUT_UNKNOWN = 10,
 177         INTEL_OUTPUT_DP_MST = 11,
 178 };
 179
 180 #define INTEL_DVO_CHIP_NONE 0
 181 #define INTEL_DVO_CHIP_LVDS 1
 182 #define INTEL_DVO_CHIP_TMDS 2
 183 #define INTEL_DVO_CHIP_TVOUT 4
 184
 185 #define INTEL_DSI_VIDEO_MODE    0
 186 #define INTEL_DSI_COMMAND_MODE  1
 187
 188 struct intel_framebuffer {
 189         struct drm_framebuffer base;
 190         struct drm_i915_gem_object *obj;
 191         struct intel_rotation_info rot_info;
 192
 193         /* for each plane in the normal GTT view */
 194         struct {
 195                 unsigned int x, y;
 196         } normal[2];
 197         /* for each plane in the rotated GTT view */
 198         struct {
 199                 unsigned int x, y;
 200                 unsigned int pitch; /* pixels */
 201         } rotated[2];
 202 };
 203
 204 struct intel_fbdev {
 205         struct drm_fb_helper helper;
 206         struct intel_framebuffer *fb;
 207         struct i915_vma *vma;
 208         async_cookie_t cookie;
 209         int preferred_bpp;
 210 };
 211
 212 struct intel_encoder {
 213         struct drm_encoder base;
 214
 215         enum intel_output_type type;
 216         enum port port;
 217         unsigned int cloneable;
 218         void (*hot_plug)(struct intel_encoder *);
 219         bool (*compute_config)(struct intel_encoder *,
 220                                struct intel_crtc_state *,
 221                                struct drm_connector_state *);
 222         void (*pre_pll_enable)(struct intel_encoder *,
 223                                struct intel_crtc_state *,
 224                                struct drm_connector_state *);
 225         void (*pre_enable)(struct intel_encoder *,
 226                            struct intel_crtc_state *,
 227                            struct drm_connector_state *);
 228         void (*enable)(struct intel_encoder *,
 229                        struct intel_crtc_state *,
 230                        struct drm_connector_state *);
 231         void (*disable)(struct intel_encoder *,
 232                         struct intel_crtc_state *,
 233                         struct drm_connector_state *);
 234         void (*post_disable)(struct intel_encoder *,
 235                              struct intel_crtc_state *,
 236                              struct drm_connector_state *);
 237         void (*post_pll_disable)(struct intel_encoder *,
 238                                  struct intel_crtc_state *,
 239                                  struct drm_connector_state *);
 240         /* Read out the current hw state of this connector, returning true if
 241          * the encoder is active. If the encoder is enabled it also set the pipe
 242          * it is connected to in the pipe parameter. */
 243         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 244         /* Reconstructs the equivalent mode flags for the current hardware
 245          * state. This must be called _after_ display->get_pipe_config has
 246          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 247          * be set correctly before calling this function. */
 248         void (*get_config)(struct intel_encoder *,
 249                            struct intel_crtc_state *pipe_config);
 250         /* Returns a mask of power domains that need to be referenced as part
 251          * of the hardware state readout code. */
 252         u64 (*get_power_domains)(struct intel_encoder *encoder);
 253         /*
 254          * Called during system suspend after all pending requests for the
 255          * encoder are flushed (for example for DP AUX transactions) and
 256          * device interrupts are disabled.
 257          */
 258         void (*suspend)(struct intel_encoder *);
 259         int crtc_mask;
 260         enum hpd_pin hpd_pin;
 261         enum intel_display_power_domain power_domain;
 262         /* for communication with audio component; protected by av_mutex */
 263         const struct drm_connector *audio_connector;
 264 };
 265
 266 struct intel_panel {
 267         struct drm_display_mode *fixed_mode;
 268         struct drm_display_mode *downclock_mode;
 269         int fitting_mode;
 270
 271         /* backlight */
 272         struct {
 273                 bool present;
 274                 u32 level;
 275                 u32 min;
 276                 u32 max;
 277                 bool enabled;
 278                 bool combination_mode;  /* gen 2/4 only */
 279                 bool active_low_pwm;
 280                 bool alternate_pwm_increment;   /* lpt+ */
 281
 282                 /* PWM chip */
 283                 bool util_pin_active_low;       /* bxt+ */
 284                 u8 controller;          /* bxt+ only */
 285                 struct pwm_device *pwm;
 286
 287                 struct backlight_device *device;
 288
 289                 /* Connector and platform specific backlight functions */
 290                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 291                 uint32_t (*get)(struct intel_connector *connector);
 292                 void (*set)(struct intel_connector *connector, uint32_t level);
 293                 void (*disable)(struct intel_connector *connector);
 294                 void (*enable)(struct intel_connector *connector);
 295                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 296                                       uint32_t hz);
 297                 void (*power)(struct intel_connector *, bool enable);
 298         } backlight;
 299 };
 300
 301 struct intel_connector {
 302         struct drm_connector base;
 303         /*
 304          * The fixed encoder this connector is connected to.
 305          */
 306         struct intel_encoder *encoder;
 307
 308         /* ACPI device id for ACPI and driver cooperation */
 309         u32 acpi_device_id;
 310
 311         /* Reads out the current hw, returning true if the connector is enabled
 312          * and active (i.e. dpms ON state). */
 313         bool (*get_hw_state)(struct intel_connector *);
 314
 315         /* Panel info for eDP and LVDS */
 316         struct intel_panel panel;
 317
 318         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 319         struct edid *edid;
 320         struct edid *detect_edid;
 321
 322         /* since POLL and HPD connectors may use the same HPD line keep the native
 323            state of connector->polled in case hotplug storm detection changes it */
 324         u8 polled;
 325
 326         void *port; /* store this opaque as its illegal to dereference it */
 327
 328         struct intel_dp *mst_port;
 329
 330         /* Work struct to schedule a uevent on link train failure */
 331         struct work_struct modeset_retry_work;
 332 };
 333
 334 struct dpll {
 335         /* given values */
 336         int n;
 337         int m1, m2;
 338         int p1, p2;
 339         /* derived values */
 340         int     dot;
 341         int     vco;
 342         int     m;
 343         int     p;
 344 };
 345
 346 struct intel_atomic_state {
 347         struct drm_atomic_state base;
 348
 349         struct {
 350                 /*
 351                  * Logical state of cdclk (used for all scaling, watermark,
 352                  * etc. calculations and checks). This is computed as if all
 353                  * enabled crtcs were active.
 354                  */
 355                 struct intel_cdclk_state logical;
 356
 357                 /*
 358                  * Actual state of cdclk, can be different from the logical
 359                  * state only when all crtc's are DPMS off.
 360                  */
 361                 struct intel_cdclk_state actual;
 362         } cdclk;
 363
 364         bool dpll_set, modeset;
 365
 366         /*
 367          * Does this transaction change the pipes that are active?  This mask
 368          * tracks which CRTC's have changed their active state at the end of
 369          * the transaction (not counting the temporary disable during modesets).
 370          * This mask should only be non-zero when intel_state->modeset is true,
 371          * but the converse is not necessarily true; simply changing a mode may
 372          * not flip the final active status of any CRTC's
 373          */
 374         unsigned int active_pipe_changes;
 375
 376         unsigned int active_crtcs;
 377         unsigned int min_pixclk[I915_MAX_PIPES];
 378
 379         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 380
 381         /*
 382          * Current watermarks can't be trusted during hardware readout, so
 383          * don't bother calculating intermediate watermarks.
 384          */
 385         bool skip_intermediate_wm;
 386
 387         /* Gen9+ only */
 388         struct skl_wm_values wm_results;
 389
 390         struct i915_sw_fence commit_ready;
 391
 392         struct llist_node freed;
 393 };
 394
 395 struct intel_plane_state {
 396         struct drm_plane_state base;
 397         struct drm_rect clip;
 398         struct i915_vma *vma;
 399
 400         struct {
 401                 u32 offset;
 402                 int x, y;
 403         } main;
 404         struct {
 405                 u32 offset;
 406                 int x, y;
 407         } aux;
 408
 409         /* plane control register */
 410         u32 ctl;
 411
 412         /*
 413          * scaler_id
 414          *    = -1 : not using a scaler
 415          *    >=  0 : using a scalers
 416          *
 417          * plane requiring a scaler:
 418          *   - During check_plane, its bit is set in
 419          *     crtc_state->scaler_state.scaler_users by calling helper function
 420          *     update_scaler_plane.
 421          *   - scaler_id indicates the scaler it got assigned.
 422          *
 423          * plane doesn't require a scaler:
 424          *   - this can happen when scaling is no more required or plane simply
 425          *     got disabled.
 426          *   - During check_plane, corresponding bit is reset in
 427          *     crtc_state->scaler_state.scaler_users by calling helper function
 428          *     update_scaler_plane.
 429          */
 430         int scaler_id;
 431
 432         struct drm_intel_sprite_colorkey ckey;
 433 };
 434
 435 struct intel_initial_plane_config {
 436         struct intel_framebuffer *fb;
 437         unsigned int tiling;
 438         int size;
 439         u32 base;
 440 };
 441
 442 #define SKL_MIN_SRC_W 8
 443 #define SKL_MAX_SRC_W 4096
 444 #define SKL_MIN_SRC_H 8
 445 #define SKL_MAX_SRC_H 4096
 446 #define SKL_MIN_DST_W 8
 447 #define SKL_MAX_DST_W 4096
 448 #define SKL_MIN_DST_H 8
 449 #define SKL_MAX_DST_H 4096
 450
 451 struct intel_scaler {
 452         int in_use;
 453         uint32_t mode;
 454 };
 455
 456 struct intel_crtc_scaler_state {
 457 #define SKL_NUM_SCALERS 2
 458         struct intel_scaler scalers[SKL_NUM_SCALERS];
 459
 460         /*
 461          * scaler_users: keeps track of users requesting scalers on this crtc.
 462          *
 463          *     If a bit is set, a user is using a scaler.
 464          *     Here user can be a plane or crtc as defined below:
 465          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 466          *       bit 31    - crtc
 467          *
 468          * Instead of creating a new index to cover planes and crtc, using
 469          * existing drm_plane_index for planes which is well less than 31
 470          * planes and bit 31 for crtc. This should be fine to cover all
 471          * our platforms.
 472          *
 473          * intel_atomic_setup_scalers will setup available scalers to users
 474          * requesting scalers. It will gracefully fail if request exceeds
 475          * avilability.
 476          */
 477 #define SKL_CRTC_INDEX 31
 478         unsigned scaler_users;
 479
 480         /* scaler used by crtc for panel fitting purpose */
 481         int scaler_id;
 482 };
 483
 484 /* drm_mode->private_flags */
 485 #define I915_MODE_FLAG_INHERITED 1
 486
 487 struct intel_pipe_wm {
 488         struct intel_wm_level wm[5];
 489         struct intel_wm_level raw_wm[5];
 490         uint32_t linetime;
 491         bool fbc_wm_enabled;
 492         bool pipe_enabled;
 493         bool sprites_enabled;
 494         bool sprites_scaled;
 495 };
 496
 497 struct skl_plane_wm {
 498         struct skl_wm_level wm[8];
 499         struct skl_wm_level trans_wm;
 500 };
 501
 502 struct skl_pipe_wm {
 503         struct skl_plane_wm planes[I915_MAX_PLANES];
 504         uint32_t linetime;
 505 };
 506
 507 enum vlv_wm_level {
 508         VLV_WM_LEVEL_PM2,
 509         VLV_WM_LEVEL_PM5,
 510         VLV_WM_LEVEL_DDR_DVFS,
 511         NUM_VLV_WM_LEVELS,
 512 };
 513
 514 struct vlv_wm_state {
 515         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 516         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 517         uint8_t num_levels;
 518         bool cxsr;
 519 };
 520
 521 struct vlv_fifo_state {
 522         u16 plane[I915_MAX_PLANES];
 523 };
 524
 525 enum g4x_wm_level {
 526         G4X_WM_LEVEL_NORMAL,
 527         G4X_WM_LEVEL_SR,
 528         G4X_WM_LEVEL_HPLL,
 529         NUM_G4X_WM_LEVELS,
 530 };
 531
 532 struct g4x_wm_state {
 533         struct g4x_pipe_wm wm;
 534         struct g4x_sr_wm sr;
 535         struct g4x_sr_wm hpll;
 536         bool cxsr;
 537         bool hpll_en;
 538         bool fbc_en;
 539 };
 540
 541 struct intel_crtc_wm_state {
 542         union {
 543                 struct {
 544                         /*
 545                          * Intermediate watermarks; these can be
 546                          * programmed immediately since they satisfy
 547                          * both the current configuration we're
 548                          * switching away from and the new
 549                          * configuration we're switching to.
 550                          */
 551                         struct intel_pipe_wm intermediate;
 552
 553                         /*
 554                          * Optimal watermarks, programmed post-vblank
 555                          * when this state is committed.
 556                          */
 557                         struct intel_pipe_wm optimal;
 558                 } ilk;
 559
 560                 struct {
 561                         /* gen9+ only needs 1-step wm programming */
 562                         struct skl_pipe_wm optimal;
 563                         struct skl_ddb_entry ddb;
 564                 } skl;
 565
 566                 struct {
 567                         /* "raw" watermarks (not inverted) */
 568                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 569                         /* intermediate watermarks (inverted) */
 570                         struct vlv_wm_state intermediate;
 571                         /* optimal watermarks (inverted) */
 572                         struct vlv_wm_state optimal;
 573                         /* display FIFO split */
 574                         struct vlv_fifo_state fifo_state;
 575                 } vlv;
 576
 577                 struct {
 578                         /* "raw" watermarks */
 579                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 580                         /* intermediate watermarks */
 581                         struct g4x_wm_state intermediate;
 582                         /* optimal watermarks */
 583                         struct g4x_wm_state optimal;
 584                 } g4x;
 585         };
 586
 587         /*
 588          * Platforms with two-step watermark programming will need to
 589          * update watermark programming post-vblank to switch from the
 590          * safe intermediate watermarks to the optimal final
 591          * watermarks.
 592          */
 593         bool need_postvbl_update;
 594 };
 595
 596 struct intel_crtc_state {
 597         struct drm_crtc_state base;
 598
 599         /**
 600          * quirks - bitfield with hw state readout quirks
 601          *
 602          * For various reasons the hw state readout code might not be able to
 603          * completely faithfully read out the current state. These cases are
 604          * tracked with quirk flags so that fastboot and state checker can act
 605          * accordingly.
 606          */
 607 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 608         unsigned long quirks;
 609
 610         unsigned fb_bits; /* framebuffers to flip */
 611         bool update_pipe; /* can a fast modeset be performed? */
 612         bool disable_cxsr;
 613         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 614         bool fb_changed; /* fb on any of the planes is changed */
 615         bool fifo_changed; /* FIFO split is changed */
 616
 617         /* Pipe source size (ie. panel fitter input size)
 618          * All planes will be positioned inside this space,
 619          * and get clipped at the edges. */
 620         int pipe_src_w, pipe_src_h;
 621
 622         /*
 623          * Pipe pixel rate, adjusted for
 624          * panel fitter/pipe scaler downscaling.
 625          */
 626         unsigned int pixel_rate;
 627
 628         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 629          * between pch encoders and cpu encoders. */
 630         bool has_pch_encoder;
 631
 632         /* Are we sending infoframes on the attached port */
 633         bool has_infoframe;
 634
 635         /* CPU Transcoder for the pipe. Currently this can only differ from the
 636          * pipe on Haswell and later (where we have a special eDP transcoder)
 637          * and Broxton (where we have special DSI transcoders). */
 638         enum transcoder cpu_transcoder;
 639
 640         /*
 641          * Use reduced/limited/broadcast rbg range, compressing from the full
 642          * range fed into the crtcs.
 643          */
 644         bool limited_color_range;
 645
 646         /* Bitmask of encoder types (enum intel_output_type)
 647          * driven by the pipe.
 648          */
 649         unsigned int output_types;
 650
 651         /* Whether we should send NULL infoframes. Required for audio. */
 652         bool has_hdmi_sink;
 653
 654         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 655          * has_dp_encoder is set. */
 656         bool has_audio;
 657
 658         /*
 659          * Enable dithering, used when the selected pipe bpp doesn't match the
 660          * plane bpp.
 661          */
 662         bool dither;
 663
 664         /*
 665          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 666          * compliance video pattern tests.
 667          * Disable dither only if it is a compliance test request for
 668          * 18bpp.
 669          */
 670         bool dither_force_disable;
 671
 672         /* Controls for the clock computation, to override various stages. */
 673         bool clock_set;
 674
 675         /* SDVO TV has a bunch of special case. To make multifunction encoders
 676          * work correctly, we need to track this at runtime.*/
 677         bool sdvo_tv_clock;
 678
 679         /*
 680          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 681          * required. This is set in the 2nd loop of calling encoder's
 682          * ->compute_config if the first pick doesn't work out.
 683          */
 684         bool bw_constrained;
 685
 686         /* Settings for the intel dpll used on pretty much everything but
 687          * haswell. */
 688         struct dpll dpll;
 689
 690         /* Selected dpll when shared or NULL. */
 691         struct intel_shared_dpll *shared_dpll;
 692
 693         /* Actual register state of the dpll, for shared dpll cross-checking. */
 694         struct intel_dpll_hw_state dpll_hw_state;
 695
 696         /* DSI PLL registers */
 697         struct {
 698                 u32 ctrl, div;
 699         } dsi_pll;
 700
 701         int pipe_bpp;
 702         struct intel_link_m_n dp_m_n;
 703
 704         /* m2_n2 for eDP downclock */
 705         struct intel_link_m_n dp_m2_n2;
 706         bool has_drrs;
 707
 708         /*
 709          * Frequence the dpll for the port should run at. Differs from the
 710          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 711          * already multiplied by pixel_multiplier.
 712          */
 713         int port_clock;
 714
 715         /* Used by SDVO (and if we ever fix it, HDMI). */
 716         unsigned pixel_multiplier;
 717
 718         uint8_t lane_count;
 719
 720         /*
 721          * Used by platforms having DP/HDMI PHY with programmable lane
 722          * latency optimization.
 723          */
 724         uint8_t lane_lat_optim_mask;
 725
 726         /* Panel fitter controls for gen2-gen4 + VLV */
 727         struct {
 728                 u32 control;
 729                 u32 pgm_ratios;
 730                 u32 lvds_border_bits;
 731         } gmch_pfit;
 732
 733         /* Panel fitter placement and size for Ironlake+ */
 734         struct {
 735                 u32 pos;
 736                 u32 size;
 737                 bool enabled;
 738                 bool force_thru;
 739         } pch_pfit;
 740
 741         /* FDI configuration, only valid if has_pch_encoder is set. */
 742         int fdi_lanes;
 743         struct intel_link_m_n fdi_m_n;
 744
 745         bool ips_enabled;
 746
 747         bool enable_fbc;
 748
 749         bool double_wide;
 750
 751         int pbn;
 752
 753         struct intel_crtc_scaler_state scaler_state;
 754
 755         /* w/a for waiting 2 vblanks during crtc enable */
 756         enum pipe hsw_workaround_pipe;
 757
 758         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 759         bool disable_lp_wm;
 760
 761         struct intel_crtc_wm_state wm;
 762
 763         /* Gamma mode programmed on the pipe */
 764         uint32_t gamma_mode;
 765
 766         /* bitmask of visible planes (enum plane_id) */
 767         u8 active_planes;
 768
 769         /* HDMI scrambling status */
 770         bool hdmi_scrambling;
 771
 772         /* HDMI High TMDS char rate ratio */
 773         bool hdmi_high_tmds_clock_ratio;
 774 };
 775
 776 struct intel_crtc {
 777         struct drm_crtc base;
 778         enum pipe pipe;
 779         enum plane plane;
 780         u8 lut_r[256], lut_g[256], lut_b[256];
 781         /*
 782          * Whether the crtc and the connected output pipeline is active. Implies
 783          * that crtc->enabled is set, i.e. the current mode configuration has
 784          * some outputs connected to this crtc.
 785          */
 786         bool active;
 787         bool lowfreq_avail;
 788         u8 plane_ids_mask;
 789         unsigned long long enabled_power_domains;
 790         struct intel_overlay *overlay;
 791         struct intel_flip_work *flip_work;
 792
 793         atomic_t unpin_work_count;
 794
 795         /* Display surface base address adjustement for pageflips. Note that on
 796          * gen4+ this only adjusts up to a tile, offsets within a tile are
 797          * handled in the hw itself (with the TILEOFF register). */
 798         u32 dspaddr_offset;
 799         int adjusted_x;
 800         int adjusted_y;
 801
 802         uint32_t cursor_addr;
 803         uint32_t cursor_cntl;
 804         uint32_t cursor_size;
 805         uint32_t cursor_base;
 806
 807         struct intel_crtc_state *config;
 808
 809         /* global reset count when the last flip was submitted */
 810         unsigned int reset_count;
 811
 812         /* Access to these should be protected by dev_priv->irq_lock. */
 813         bool cpu_fifo_underrun_disabled;
 814         bool pch_fifo_underrun_disabled;
 815
 816         /* per-pipe watermark state */
 817         struct {
 818                 /* watermarks currently being used  */
 819                 union {
 820                         struct intel_pipe_wm ilk;
 821                         struct vlv_wm_state vlv;
 822                         struct g4x_wm_state g4x;
 823                 } active;
 824         } wm;
 825
 826         int scanline_offset;
 827
 828         struct {
 829                 unsigned start_vbl_count;
 830                 ktime_t start_vbl_time;
 831                 int min_vbl, max_vbl;
 832                 int scanline_start;
 833         } debug;
 834
 835         /* scalers available on this crtc */
 836         int num_scalers;
 837 };
 838
 839 struct intel_plane {
 840         struct drm_plane base;
 841         u8 plane;
 842         enum plane_id id;
 843         enum pipe pipe;
 844         bool can_scale;
 845         int max_downscale;
 846         uint32_t frontbuffer_bit;
 847
 848         /*
 849          * NOTE: Do not place new plane state fields here (e.g., when adding
 850          * new plane properties).  New runtime state should now be placed in
 851          * the intel_plane_state structure and accessed via plane_state.
 852          */
 853
 854         void (*update_plane)(struct drm_plane *plane,
 855                              const struct intel_crtc_state *crtc_state,
 856                              const struct intel_plane_state *plane_state);
 857         void (*disable_plane)(struct drm_plane *plane,
 858                               struct drm_crtc *crtc);
 859         int (*check_plane)(struct drm_plane *plane,
 860                            struct intel_crtc_state *crtc_state,
 861                            struct intel_plane_state *state);
 862 };
 863
 864 struct intel_watermark_params {
 865         u16 fifo_size;
 866         u16 max_wm;
 867         u8 default_wm;
 868         u8 guard_size;
 869         u8 cacheline_size;
 870 };
 871
 872 struct cxsr_latency {
 873         bool is_desktop : 1;
 874         bool is_ddr3 : 1;
 875         u16 fsb_freq;
 876         u16 mem_freq;
 877         u16 display_sr;
 878         u16 display_hpll_disable;
 879         u16 cursor_sr;
 880         u16 cursor_hpll_disable;
 881 };
 882
 883 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 884 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 885 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 886 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 887 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 888 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 889 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 890 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 891 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 892
 893 struct intel_hdmi {
 894         i915_reg_t hdmi_reg;
 895         int ddc_bus;
 896         struct {
 897                 enum drm_dp_dual_mode_type type;
 898                 int max_tmds_clock;
 899         } dp_dual_mode;
 900         bool limited_color_range;
 901         bool color_range_auto;
 902         bool has_hdmi_sink;
 903         bool has_audio;
 904         enum hdmi_force_audio force_audio;
 905         bool rgb_quant_range_selectable;
 906         enum hdmi_picture_aspect aspect_ratio;
 907         struct intel_connector *attached_connector;
 908         void (*write_infoframe)(struct drm_encoder *encoder,
 909                                 const struct intel_crtc_state *crtc_state,
 910                                 enum hdmi_infoframe_type type,
 911                                 const void *frame, ssize_t len);
 912         void (*set_infoframes)(struct drm_encoder *encoder,
 913                                bool enable,
 914                                const struct intel_crtc_state *crtc_state,
 915                                const struct drm_connector_state *conn_state);
 916         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 917                                   const struct intel_crtc_state *pipe_config);
 918 };
 919
 920 struct intel_dp_mst_encoder;
 921 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 922
 923 /*
 924  * enum link_m_n_set:
 925  *      When platform provides two set of M_N registers for dp, we can
 926  *      program them and switch between them incase of DRRS.
 927  *      But When only one such register is provided, we have to program the
 928  *      required divider value on that registers itself based on the DRRS state.
 929  *
 930  * M1_N1        : Program dp_m_n on M1_N1 registers
 931  *                        dp_m2_n2 on M2_N2 registers (If supported)
 932  *
 933  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 934  *                        M2_N2 registers are not supported
 935  */
 936
 937 enum link_m_n_set {
 938         /* Sets the m1_n1 and m2_n2 */
 939         M1_N1 = 0,
 940         M2_N2
 941 };
 942
 943 struct intel_dp_desc {
 944         u8 oui[3];
 945         u8 device_id[6];
 946         u8 hw_rev;
 947         u8 sw_major_rev;
 948         u8 sw_minor_rev;
 949 } __packed;
 950
 951 struct intel_dp_compliance_data {
 952         unsigned long edid;
 953         uint8_t video_pattern;
 954         uint16_t hdisplay, vdisplay;
 955         uint8_t bpc;
 956 };
 957
 958 struct intel_dp_compliance {
 959         unsigned long test_type;
 960         struct intel_dp_compliance_data test_data;
 961         bool test_active;
 962         int test_link_rate;
 963         u8 test_lane_count;
 964 };
 965
 966 struct intel_dp {
 967         i915_reg_t output_reg;
 968         i915_reg_t aux_ch_ctl_reg;
 969         i915_reg_t aux_ch_data_reg[5];
 970         uint32_t DP;
 971         int link_rate;
 972         uint8_t lane_count;
 973         uint8_t sink_count;
 974         bool link_mst;
 975         bool has_audio;
 976         bool detect_done;
 977         bool channel_eq_status;
 978         bool reset_link_params;
 979         enum hdmi_force_audio force_audio;
 980         bool limited_color_range;
 981         bool color_range_auto;
 982         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 983         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 984         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 985         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 986         /* source rates */
 987         int num_source_rates;
 988         const int *source_rates;
 989         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 990         int num_sink_rates;
 991         int sink_rates[DP_MAX_SUPPORTED_RATES];
 992         bool use_rate_select;
 993         /* intersection of source and sink rates */
 994         int num_common_rates;
 995         int common_rates[DP_MAX_SUPPORTED_RATES];
 996         /* Max lane count for the current link */
 997         int max_link_lane_count;
 998         /* Max rate for the current link */
 999         int max_link_rate;
1000         /* sink or branch descriptor */
1001         struct intel_dp_desc desc;
1002         struct drm_dp_aux aux;
1003         enum intel_display_power_domain aux_power_domain;
1004         uint8_t train_set[4];
1005         int panel_power_up_delay;
1006         int panel_power_down_delay;
1007         int panel_power_cycle_delay;
1008         int backlight_on_delay;
1009         int backlight_off_delay;
1010         struct delayed_work panel_vdd_work;
1011         bool want_panel_vdd;
1012         unsigned long last_power_on;
1013         unsigned long last_backlight_off;
1014         ktime_t panel_power_off_time;
1015
1016         struct notifier_block edp_notifier;
1017
1018         /*
1019          * Pipe whose power sequencer is currently locked into
1020          * this port. Only relevant on VLV/CHV.
1021          */
1022         enum pipe pps_pipe;
1023         /*
1024          * Pipe currently driving the port. Used for preventing
1025          * the use of the PPS for any pipe currentrly driving
1026          * external DP as that will mess things up on VLV.
1027          */
1028         enum pipe active_pipe;
1029         /*
1030          * Set if the sequencer may be reset due to a power transition,
1031          * requiring a reinitialization. Only relevant on BXT.
1032          */
1033         bool pps_reset;
1034         struct edp_power_seq pps_delays;
1035
1036         bool can_mst; /* this port supports mst */
1037         bool is_mst;
1038         int active_mst_links;
1039         /* connector directly attached - won't be use for modeset in mst world */
1040         struct intel_connector *attached_connector;
1041
1042         /* mst connector list */
1043         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1044         struct drm_dp_mst_topology_mgr mst_mgr;
1045
1046         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1047         /*
1048          * This function returns the value we have to program the AUX_CTL
1049          * register with to kick off an AUX transaction.
1050          */
1051         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1052                                      bool has_aux_irq,
1053                                      int send_bytes,
1054                                      uint32_t aux_clock_divider);
1055
1056         /* This is called before a link training is starterd */
1057         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1058
1059         /* Displayport compliance testing */
1060         struct intel_dp_compliance compliance;
1061 };
1062
1063 struct intel_lspcon {
1064         bool active;
1065         enum drm_lspcon_mode mode;
1066 };
1067
1068 struct intel_digital_port {
1069         struct intel_encoder base;
1070         enum port port;
1071         u32 saved_port_bits;
1072         struct intel_dp dp;
1073         struct intel_hdmi hdmi;
1074         struct intel_lspcon lspcon;
1075         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1076         bool release_cl2_override;
1077         uint8_t max_lanes;
1078         enum intel_display_power_domain ddi_io_power_domain;
1079 };
1080
1081 struct intel_dp_mst_encoder {
1082         struct intel_encoder base;
1083         enum pipe pipe;
1084         struct intel_digital_port *primary;
1085         struct intel_connector *connector;
1086 };
1087
1088 static inline enum dpio_channel
1089 vlv_dport_to_channel(struct intel_digital_port *dport)
1090 {
1091         switch (dport->port) {
1092         case PORT_B:
1093         case PORT_D:
1094                 return DPIO_CH0;
1095         case PORT_C:
1096                 return DPIO_CH1;
1097         default:
1098                 BUG();
1099         }
1100 }
1101
1102 static inline enum dpio_phy
1103 vlv_dport_to_phy(struct intel_digital_port *dport)
1104 {
1105         switch (dport->port) {
1106         case PORT_B:
1107         case PORT_C:
1108                 return DPIO_PHY0;
1109         case PORT_D:
1110                 return DPIO_PHY1;
1111         default:
1112                 BUG();
1113         }
1114 }
1115
1116 static inline enum dpio_channel
1117 vlv_pipe_to_channel(enum pipe pipe)
1118 {
1119         switch (pipe) {
1120         case PIPE_A:
1121         case PIPE_C:
1122                 return DPIO_CH0;
1123         case PIPE_B:
1124                 return DPIO_CH1;
1125         default:
1126                 BUG();
1127         }
1128 }
1129
1130 static inline struct intel_crtc *
1131 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1132 {
1133         return dev_priv->pipe_to_crtc_mapping[pipe];
1134 }
1135
1136 static inline struct intel_crtc *
1137 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1138 {
1139         return dev_priv->plane_to_crtc_mapping[plane];
1140 }
1141
1142 struct intel_flip_work {
1143         struct work_struct unpin_work;
1144         struct work_struct mmio_work;
1145
1146         struct drm_crtc *crtc;
1147         struct i915_vma *old_vma;
1148         struct drm_framebuffer *old_fb;
1149         struct drm_i915_gem_object *pending_flip_obj;
1150         struct drm_pending_vblank_event *event;
1151         atomic_t pending;
1152         u32 flip_count;
1153         u32 gtt_offset;
1154         struct drm_i915_gem_request *flip_queued_req;
1155         u32 flip_queued_vblank;
1156         u32 flip_ready_vblank;
1157         unsigned int rotation;
1158 };
1159
1160 struct intel_load_detect_pipe {
1161         struct drm_atomic_state *restore_state;
1162 };
1163
1164 static inline struct intel_encoder *
1165 intel_attached_encoder(struct drm_connector *connector)
1166 {
1167         return to_intel_connector(connector)->encoder;
1168 }
1169
1170 static inline struct intel_digital_port *
1171 enc_to_dig_port(struct drm_encoder *encoder)
1172 {
1173         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1174
1175         switch (intel_encoder->type) {
1176         case INTEL_OUTPUT_UNKNOWN:
1177                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1178         case INTEL_OUTPUT_DP:
1179         case INTEL_OUTPUT_EDP:
1180         case INTEL_OUTPUT_HDMI:
1181                 return container_of(encoder, struct intel_digital_port,
1182                                     base.base);
1183         default:
1184                 return NULL;
1185         }
1186 }
1187
1188 static inline struct intel_dp_mst_encoder *
1189 enc_to_mst(struct drm_encoder *encoder)
1190 {
1191         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1192 }
1193
1194 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1195 {
1196         return &enc_to_dig_port(encoder)->dp;
1197 }
1198
1199 static inline struct intel_digital_port *
1200 dp_to_dig_port(struct intel_dp *intel_dp)
1201 {
1202         return container_of(intel_dp, struct intel_digital_port, dp);
1203 }
1204
1205 static inline struct intel_lspcon *
1206 dp_to_lspcon(struct intel_dp *intel_dp)
1207 {
1208         return &dp_to_dig_port(intel_dp)->lspcon;
1209 }
1210
1211 static inline struct intel_digital_port *
1212 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1213 {
1214         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1215 }
1216
1217 /* intel_fifo_underrun.c */
1218 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1219                                            enum pipe pipe, bool enable);
1220 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1221                                            enum transcoder pch_transcoder,
1222                                            bool enable);
1223 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1224                                          enum pipe pipe);
1225 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1226                                          enum transcoder pch_transcoder);
1227 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1228 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1229
1230 /* i915_irq.c */
1231 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1232 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1233 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1234 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1235 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1236 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1237 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1238 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1239 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1240 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1241
1242 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1243                                             u32 mask)
1244 {
1245         return mask & ~i915->rps.pm_intrmsk_mbz;
1246 }
1247
1248 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1249 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1250 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1251 {
1252         /*
1253          * We only use drm_irq_uninstall() at unload and VT switch, so
1254          * this is the only thing we need to check.
1255          */
1256         return dev_priv->pm.irqs_enabled;
1257 }
1258
1259 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1260 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1261                                      unsigned int pipe_mask);
1262 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1263                                      unsigned int pipe_mask);
1264 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1265 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1266 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1267
1268 /* intel_crt.c */
1269 void intel_crt_init(struct drm_i915_private *dev_priv);
1270 void intel_crt_reset(struct drm_encoder *encoder);
1271
1272 /* intel_ddi.c */
1273 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1274                                 struct intel_crtc_state *old_crtc_state,
1275                                 struct drm_connector_state *old_conn_state);
1276 void hsw_fdi_link_train(struct intel_crtc *crtc,
1277                         const struct intel_crtc_state *crtc_state);
1278 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1279 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1280 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1281 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1282 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1283                                        enum transcoder cpu_transcoder);
1284 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1285 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1286 struct intel_encoder *
1287 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1288 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1289 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1290 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1291 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1292                                  struct intel_crtc *intel_crtc);
1293 void intel_ddi_get_config(struct intel_encoder *encoder,
1294                           struct intel_crtc_state *pipe_config);
1295
1296 void intel_ddi_clock_get(struct intel_encoder *encoder,
1297                          struct intel_crtc_state *pipe_config);
1298 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1299                                     bool state);
1300 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1301 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1302
1303 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1304                                    int plane, unsigned int height);
1305
1306 /* intel_audio.c */
1307 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1308 void intel_audio_codec_enable(struct intel_encoder *encoder,
1309                               const struct intel_crtc_state *crtc_state,
1310                               const struct drm_connector_state *conn_state);
1311 void intel_audio_codec_disable(struct intel_encoder *encoder);
1312 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1313 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1314 void intel_audio_init(struct drm_i915_private *dev_priv);
1315 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1316
1317 /* intel_cdclk.c */
1318 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1319 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1320 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1321 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1322 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1323 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1324 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1325 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1326 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1327                                const struct intel_cdclk_state *b);
1328 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1329                      const struct intel_cdclk_state *cdclk_state);
1330
1331 /* intel_display.c */
1332 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1333 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1334 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1335 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1336                       const char *name, u32 reg, int ref_freq);
1337 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1338                            const char *name, u32 reg);
1339 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1340 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1341 extern const struct drm_plane_funcs intel_plane_funcs;
1342 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1343 unsigned int intel_fb_xy_to_linear(int x, int y,
1344                                    const struct intel_plane_state *state,
1345                                    int plane);
1346 void intel_add_fb_offsets(int *x, int *y,
1347                           const struct intel_plane_state *state, int plane);
1348 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1349 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1350 void intel_mark_busy(struct drm_i915_private *dev_priv);
1351 void intel_mark_idle(struct drm_i915_private *dev_priv);
1352 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1353 int intel_display_suspend(struct drm_device *dev);
1354 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1355 void intel_encoder_destroy(struct drm_encoder *encoder);
1356 int intel_connector_init(struct intel_connector *);
1357 struct intel_connector *intel_connector_alloc(void);
1358 bool intel_connector_get_hw_state(struct intel_connector *connector);
1359 void intel_connector_attach_encoder(struct intel_connector *connector,
1360                                     struct intel_encoder *encoder);
1361 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1362                                              struct drm_crtc *crtc);
1363 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1364 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1365                                 struct drm_file *file_priv);
1366 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1367                                              enum pipe pipe);
1368 static inline bool
1369 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1370                     enum intel_output_type type)
1371 {
1372         return crtc_state->output_types & (1 << type);
1373 }
1374 static inline bool
1375 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1376 {
1377         return crtc_state->output_types &
1378                 ((1 << INTEL_OUTPUT_DP) |
1379                  (1 << INTEL_OUTPUT_DP_MST) |
1380                  (1 << INTEL_OUTPUT_EDP));
1381 }
1382 static inline void
1383 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1384 {
1385         drm_wait_one_vblank(&dev_priv->drm, pipe);
1386 }
1387 static inline void
1388 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1389 {
1390         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1391
1392         if (crtc->active)
1393                 intel_wait_for_vblank(dev_priv, pipe);
1394 }
1395
1396 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1397
1398 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1399 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1400                          struct intel_digital_port *dport,
1401                          unsigned int expected_mask);
1402 int intel_get_load_detect_pipe(struct drm_connector *connector,
1403                                struct drm_display_mode *mode,
1404                                struct intel_load_detect_pipe *old,
1405                                struct drm_modeset_acquire_ctx *ctx);
1406 void intel_release_load_detect_pipe(struct drm_connector *connector,
1407                                     struct intel_load_detect_pipe *old,
1408                                     struct drm_modeset_acquire_ctx *ctx);
1409 struct i915_vma *
1410 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1411 void intel_unpin_fb_vma(struct i915_vma *vma);
1412 struct drm_framebuffer *
1413 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1414                          struct drm_mode_fb_cmd2 *mode_cmd);
1415 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1416 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1417 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1418 int intel_prepare_plane_fb(struct drm_plane *plane,
1419                            struct drm_plane_state *new_state);
1420 void intel_cleanup_plane_fb(struct drm_plane *plane,
1421                             struct drm_plane_state *old_state);
1422 int intel_plane_atomic_get_property(struct drm_plane *plane,
1423                                     const struct drm_plane_state *state,
1424                                     struct drm_property *property,
1425                                     uint64_t *val);
1426 int intel_plane_atomic_set_property(struct drm_plane *plane,
1427                                     struct drm_plane_state *state,
1428                                     struct drm_property *property,
1429                                     uint64_t val);
1430 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1431                                     struct drm_plane_state *plane_state);
1432
1433 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1434                                     enum pipe pipe);
1435
1436 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1437                      const struct dpll *dpll);
1438 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1439 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1440
1441 /* modesetting asserts */
1442 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1443                            enum pipe pipe);
1444 void assert_pll(struct drm_i915_private *dev_priv,
1445                 enum pipe pipe, bool state);
1446 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1447 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1448 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1449 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1450 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1451 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1452                        enum pipe pipe, bool state);
1453 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1454 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1455 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1456 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1457 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1458 u32 intel_compute_tile_offset(int *x, int *y,
1459                               const struct intel_plane_state *state, int plane);
1460 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1461 void intel_finish_reset(struct drm_i915_private *dev_priv);
1462 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1463 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1464 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1465 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1466 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1467 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1468 unsigned int skl_cdclk_get_vco(unsigned int freq);
1469 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1470 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1471 void intel_dp_get_m_n(struct intel_crtc *crtc,
1472                       struct intel_crtc_state *pipe_config);
1473 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1474 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1475 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1476                         struct dpll *best_clock);
1477 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1478
1479 bool intel_crtc_active(struct intel_crtc *crtc);
1480 void hsw_enable_ips(struct intel_crtc *crtc);
1481 void hsw_disable_ips(struct intel_crtc *crtc);
1482 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1483 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1484                                  struct intel_crtc_state *pipe_config);
1485
1486 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1487 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1488
1489 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1490 {
1491         return i915_ggtt_offset(state->vma);
1492 }
1493
1494 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1495                   const struct intel_plane_state *plane_state);
1496 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1497                      unsigned int rotation);
1498 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1499 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1500
1501 /* intel_csr.c */
1502 void intel_csr_ucode_init(struct drm_i915_private *);
1503 void intel_csr_load_program(struct drm_i915_private *);
1504 void intel_csr_ucode_fini(struct drm_i915_private *);
1505 void intel_csr_ucode_suspend(struct drm_i915_private *);
1506 void intel_csr_ucode_resume(struct drm_i915_private *);
1507
1508 /* intel_dp.c */
1509 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1510                    enum port port);
1511 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1512                              struct intel_connector *intel_connector);
1513 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1514                               int link_rate, uint8_t lane_count,
1515                               bool link_mst);
1516 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1517                                             int link_rate, uint8_t lane_count);
1518 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1519 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1520 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1521 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1522 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1523 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1524 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1525 bool intel_dp_compute_config(struct intel_encoder *encoder,
1526                              struct intel_crtc_state *pipe_config,
1527                              struct drm_connector_state *conn_state);
1528 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1529 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1530                                   bool long_hpd);
1531 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1532 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1533 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1534 void intel_edp_panel_on(struct intel_dp *intel_dp);
1535 void intel_edp_panel_off(struct intel_dp *intel_dp);
1536 void intel_dp_mst_suspend(struct drm_device *dev);
1537 void intel_dp_mst_resume(struct drm_device *dev);
1538 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1539 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1540 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1541 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1542 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1543 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1544 void intel_plane_destroy(struct drm_plane *plane);
1545 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1546                            struct intel_crtc_state *crtc_state);
1547 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1548                            struct intel_crtc_state *crtc_state);
1549 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1550                                unsigned int frontbuffer_bits);
1551 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1552                           unsigned int frontbuffer_bits);
1553
1554 void
1555 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1556                                        uint8_t dp_train_pat);
1557 void
1558 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1559 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1560 uint8_t
1561 intel_dp_voltage_max(struct intel_dp *intel_dp);
1562 uint8_t
1563 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1564 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1565                            uint8_t *link_bw, uint8_t *rate_select);
1566 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1567 bool
1568 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1569
1570 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1571 {
1572         return ~((1 << lane_count) - 1) & 0xf;
1573 }
1574
1575 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1576 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1577                           struct intel_dp_desc *desc);
1578 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1579 int intel_dp_link_required(int pixel_clock, int bpp);
1580 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1581 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1582                                   struct intel_digital_port *port);
1583
1584 /* intel_dp_aux_backlight.c */
1585 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1586
1587 /* intel_dp_mst.c */
1588 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1589 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1590 /* intel_dsi.c */
1591 void intel_dsi_init(struct drm_i915_private *dev_priv);
1592
1593 /* intel_dsi_dcs_backlight.c */
1594 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1595
1596 /* intel_dvo.c */
1597 void intel_dvo_init(struct drm_i915_private *dev_priv);
1598 /* intel_hotplug.c */
1599 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1600
1601
1602 /* legacy fbdev emulation in intel_fbdev.c */
1603 #ifdef CONFIG_DRM_FBDEV_EMULATION
1604 extern int intel_fbdev_init(struct drm_device *dev);
1605 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1606 extern void intel_fbdev_fini(struct drm_device *dev);
1607 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1608 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1609 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1610 #else
1611 static inline int intel_fbdev_init(struct drm_device *dev)
1612 {
1613         return 0;
1614 }
1615
1616 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1617 {
1618 }
1619
1620 static inline void intel_fbdev_fini(struct drm_device *dev)
1621 {
1622 }
1623
1624 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1625 {
1626 }
1627
1628 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1629 {
1630 }
1631
1632 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1633 {
1634 }
1635 #endif
1636
1637 /* intel_fbc.c */
1638 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1639                            struct drm_atomic_state *state);
1640 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1641 void intel_fbc_pre_update(struct intel_crtc *crtc,
1642                           struct intel_crtc_state *crtc_state,
1643                           struct intel_plane_state *plane_state);
1644 void intel_fbc_post_update(struct intel_crtc *crtc);
1645 void intel_fbc_init(struct drm_i915_private *dev_priv);
1646 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1647 void intel_fbc_enable(struct intel_crtc *crtc,
1648                       struct intel_crtc_state *crtc_state,
1649                       struct intel_plane_state *plane_state);
1650 void intel_fbc_disable(struct intel_crtc *crtc);
1651 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1652 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1653                           unsigned int frontbuffer_bits,
1654                           enum fb_op_origin origin);
1655 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1656                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1657 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1658 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1659
1660 /* intel_hdmi.c */
1661 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1662                      enum port port);
1663 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1664                                struct intel_connector *intel_connector);
1665 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1666 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1667                                struct intel_crtc_state *pipe_config,
1668                                struct drm_connector_state *conn_state);
1669 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1670                                        struct drm_connector *connector,
1671                                        bool high_tmds_clock_ratio,
1672                                        bool scrambling);
1673 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1674
1675
1676 /* intel_lvds.c */
1677 void intel_lvds_init(struct drm_i915_private *dev_priv);
1678 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1679 bool intel_is_dual_link_lvds(struct drm_device *dev);
1680
1681
1682 /* intel_modes.c */
1683 int intel_connector_update_modes(struct drm_connector *connector,
1684                                  struct edid *edid);
1685 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1686 void intel_attach_force_audio_property(struct drm_connector *connector);
1687 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1688 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1689
1690
1691 /* intel_overlay.c */
1692 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1693 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1694 int intel_overlay_switch_off(struct intel_overlay *overlay);
1695 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1696                                   struct drm_file *file_priv);
1697 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1698                               struct drm_file *file_priv);
1699 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1700
1701
1702 /* intel_panel.c */
1703 int intel_panel_init(struct intel_panel *panel,
1704                      struct drm_display_mode *fixed_mode,
1705                      struct drm_display_mode *downclock_mode);
1706 void intel_panel_fini(struct intel_panel *panel);
1707 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1708                             struct drm_display_mode *adjusted_mode);
1709 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1710                              struct intel_crtc_state *pipe_config,
1711                              int fitting_mode);
1712 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1713                               struct intel_crtc_state *pipe_config,
1714                               int fitting_mode);
1715 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1716                                     u32 level, u32 max);
1717 int intel_panel_setup_backlight(struct drm_connector *connector,
1718                                 enum pipe pipe);
1719 void intel_panel_enable_backlight(struct intel_connector *connector);
1720 void intel_panel_disable_backlight(struct intel_connector *connector);
1721 void intel_panel_destroy_backlight(struct drm_connector *connector);
1722 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1723 extern struct drm_display_mode *intel_find_panel_downclock(
1724                                 struct drm_i915_private *dev_priv,
1725                                 struct drm_display_mode *fixed_mode,
1726                                 struct drm_connector *connector);
1727
1728 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1729 int intel_backlight_device_register(struct intel_connector *connector);
1730 void intel_backlight_device_unregister(struct intel_connector *connector);
1731 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1732 static int intel_backlight_device_register(struct intel_connector *connector)
1733 {
1734         return 0;
1735 }
1736 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1737 {
1738 }
1739 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1740
1741
1742 /* intel_psr.c */
1743 void intel_psr_enable(struct intel_dp *intel_dp);
1744 void intel_psr_disable(struct intel_dp *intel_dp);
1745 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1746                           unsigned frontbuffer_bits);
1747 void intel_psr_flush(struct drm_i915_private *dev_priv,
1748                      unsigned frontbuffer_bits,
1749                      enum fb_op_origin origin);
1750 void intel_psr_init(struct drm_i915_private *dev_priv);
1751 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1752                                    unsigned frontbuffer_bits);
1753
1754 /* intel_runtime_pm.c */
1755 int intel_power_domains_init(struct drm_i915_private *);
1756 void intel_power_domains_fini(struct drm_i915_private *);
1757 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1758 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1759 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1760 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1761 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1762 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1763 const char *
1764 intel_display_power_domain_str(enum intel_display_power_domain domain);
1765
1766 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1767                                     enum intel_display_power_domain domain);
1768 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1769                                       enum intel_display_power_domain domain);
1770 void intel_display_power_get(struct drm_i915_private *dev_priv,
1771                              enum intel_display_power_domain domain);
1772 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1773                                         enum intel_display_power_domain domain);
1774 void intel_display_power_put(struct drm_i915_private *dev_priv,
1775                              enum intel_display_power_domain domain);
1776
1777 static inline void
1778 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1779 {
1780         WARN_ONCE(dev_priv->pm.suspended,
1781                   "Device suspended during HW access\n");
1782 }
1783
1784 static inline void
1785 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1786 {
1787         assert_rpm_device_not_suspended(dev_priv);
1788         WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1789                   "RPM wakelock ref not held during HW access");
1790 }
1791
1792 /**
1793  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1794  * @dev_priv: i915 device instance
1795  *
1796  * This function disable asserts that check if we hold an RPM wakelock
1797  * reference, while keeping the device-not-suspended checks still enabled.
1798  * It's meant to be used only in special circumstances where our rule about
1799  * the wakelock refcount wrt. the device power state doesn't hold. According
1800  * to this rule at any point where we access the HW or want to keep the HW in
1801  * an active state we must hold an RPM wakelock reference acquired via one of
1802  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1803  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1804  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1805  * users should avoid using this function.
1806  *
1807  * Any calls to this function must have a symmetric call to
1808  * enable_rpm_wakeref_asserts().
1809  */
1810 static inline void
1811 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1812 {
1813         atomic_inc(&dev_priv->pm.wakeref_count);
1814 }
1815
1816 /**
1817  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1818  * @dev_priv: i915 device instance
1819  *
1820  * This function re-enables the RPM assert checks after disabling them with
1821  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1822  * circumstances otherwise its use should be avoided.
1823  *
1824  * Any calls to this function must have a symmetric call to
1825  * disable_rpm_wakeref_asserts().
1826  */
1827 static inline void
1828 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1829 {
1830         atomic_dec(&dev_priv->pm.wakeref_count);
1831 }
1832
1833 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1834 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1835 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1836 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1837
1838 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1839
1840 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1841                              bool override, unsigned int mask);
1842 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1843                           enum dpio_channel ch, bool override);
1844
1845
1846 /* intel_pm.c */
1847 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1848 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1849 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1850 void intel_update_watermarks(struct intel_crtc *crtc);
1851 void intel_init_pm(struct drm_i915_private *dev_priv);
1852 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1853 void intel_pm_setup(struct drm_i915_private *dev_priv);
1854 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1855 void intel_gpu_ips_teardown(void);
1856 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1857 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1858 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1859 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1860 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1861 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1862 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1863 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1864 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1865 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1866 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1867                     struct intel_rps_client *rps,
1868                     unsigned long submitted);
1869 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1870 void g4x_wm_get_hw_state(struct drm_device *dev);
1871 void vlv_wm_get_hw_state(struct drm_device *dev);
1872 void ilk_wm_get_hw_state(struct drm_device *dev);
1873 void skl_wm_get_hw_state(struct drm_device *dev);
1874 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1875                           struct skl_ddb_allocation *ddb /* out */);
1876 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1877                               struct skl_pipe_wm *out);
1878 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1879 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1880 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1881 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1882 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1883 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1884                          const struct skl_wm_level *l2);
1885 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1886                                  const struct skl_ddb_entry *ddb,
1887                                  int ignore);
1888 bool ilk_disable_lp_wm(struct drm_device *dev);
1889 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1890 static inline int intel_enable_rc6(void)
1891 {
1892         return i915.enable_rc6;
1893 }
1894
1895 /* intel_sdvo.c */
1896 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1897                      i915_reg_t reg, enum port port);
1898
1899
1900 /* intel_sprite.c */
1901 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1902                              int usecs);
1903 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1904                                               enum pipe pipe, int plane);
1905 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1906                               struct drm_file *file_priv);
1907 void intel_pipe_update_start(struct intel_crtc *crtc);
1908 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1909
1910 /* intel_tv.c */
1911 void intel_tv_init(struct drm_i915_private *dev_priv);
1912
1913 /* intel_atomic.c */
1914 int intel_connector_atomic_get_property(struct drm_connector *connector,
1915                                         const struct drm_connector_state *state,
1916                                         struct drm_property *property,
1917                                         uint64_t *val);
1918 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1919 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1920                                struct drm_crtc_state *state);
1921 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1922 void intel_atomic_state_clear(struct drm_atomic_state *);
1923
1924 static inline struct intel_crtc_state *
1925 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1926                             struct intel_crtc *crtc)
1927 {
1928         struct drm_crtc_state *crtc_state;
1929         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1930         if (IS_ERR(crtc_state))
1931                 return ERR_CAST(crtc_state);
1932
1933         return to_intel_crtc_state(crtc_state);
1934 }
1935
1936 static inline struct intel_crtc_state *
1937 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1938                                      struct intel_crtc *crtc)
1939 {
1940         struct drm_crtc_state *crtc_state;
1941
1942         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1943
1944         if (crtc_state)
1945                 return to_intel_crtc_state(crtc_state);
1946         else
1947                 return NULL;
1948 }
1949
1950 static inline struct intel_plane_state *
1951 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1952                                       struct intel_plane *plane)
1953 {
1954         struct drm_plane_state *plane_state;
1955
1956         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1957
1958         return to_intel_plane_state(plane_state);
1959 }
1960
1961 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1962                                struct intel_crtc *intel_crtc,
1963                                struct intel_crtc_state *crtc_state);
1964
1965 /* intel_atomic_plane.c */
1966 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1967 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1968 void intel_plane_destroy_state(struct drm_plane *plane,
1969                                struct drm_plane_state *state);
1970 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1971 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1972                                         struct intel_plane_state *intel_state);
1973
1974 /* intel_color.c */
1975 void intel_color_init(struct drm_crtc *crtc);
1976 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1977 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1978 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1979
1980 /* intel_lspcon.c */
1981 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1982 void lspcon_resume(struct intel_lspcon *lspcon);
1983 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1984
1985 /* intel_pipe_crc.c */
1986 int intel_pipe_crc_create(struct drm_minor *minor);
1987 #ifdef CONFIG_DEBUG_FS
1988 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1989                               size_t *values_cnt);
1990 #else
1991 #define intel_crtc_set_crc_source NULL
1992 #endif
1993 extern const struct file_operations i915_display_crc_ctl_fops;
1994 #endif /* __INTEL_DRV_H__ */