drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  *
  51  * TODO: When modesetting has fully transitioned to atomic, the below
  52  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  53  * added.
  54  */
  55 #define _wait_for(COND, US, W) ({ \
  56         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  57         int ret__;                                                      \
  58         for (;;) {                                                      \
  59                 bool expired__ = time_after(jiffies, timeout__);        \
  60                 if (COND) {                                             \
  61                         ret__ = 0;                                      \
  62                         break;                                          \
  63                 }                                                       \
  64                 if (expired__) {                                        \
  65                         ret__ = -ETIMEDOUT;                             \
  66                         break;                                          \
  67                 }                                                       \
  68                 if ((W) && drm_can_sleep()) {                           \
  69                         usleep_range((W), (W)*2);                       \
  70                 } else {                                                \
  71                         cpu_relax();                                    \
  72                 }                                                       \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  78
  79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  82 #else
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  84 #endif
  85
  86 #define _wait_for_atomic(COND, US, ATOMIC) \
  87 ({ \
  88         int cpu, ret, timeout = (US) * 1000; \
  89         u64 base; \
  90         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  91         if (!(ATOMIC)) { \
  92                 preempt_disable(); \
  93                 cpu = smp_processor_id(); \
  94         } \
  95         base = local_clock(); \
  96         for (;;) { \
  97                 u64 now = local_clock(); \
  98                 if (!(ATOMIC)) \
  99                         preempt_enable(); \
 100                 if (COND) { \
 101                         ret = 0; \
 102                         break; \
 103                 } \
 104                 if (now - base >= timeout) { \
 105                         ret = -ETIMEDOUT; \
 106                         break; \
 107                 } \
 108                 cpu_relax(); \
 109                 if (!(ATOMIC)) { \
 110                         preempt_disable(); \
 111                         if (unlikely(cpu != smp_processor_id())) { \
 112                                 timeout -= now - base; \
 113                                 cpu = smp_processor_id(); \
 114                                 base = local_clock(); \
 115                         } \
 116                 } \
 117         } \
 118         ret; \
 119 })
 120
 121 #define wait_for_us(COND, US) \
 122 ({ \
 123         int ret__; \
 124         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 125         if ((US) > 10) \
 126                 ret__ = _wait_for((COND), (US), 10); \
 127         else \
 128                 ret__ = _wait_for_atomic((COND), (US), 0); \
 129         ret__; \
 130 })
 131
 132 #define wait_for_atomic_us(COND, US) \
 133 ({ \
 134         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 135         BUILD_BUG_ON((US) > 50000); \
 136         _wait_for_atomic((COND), (US), 1); \
 137 })
 138
 139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 140
 141 #define KHz(x) (1000 * (x))
 142 #define MHz(x) KHz(1000 * (x))
 143
 144 /*
 145  * Display related stuff
 146  */
 147
 148 /* store information about an Ixxx DVO */
 149 /* The i830->i865 use multiple DVOs with multiple i2cs */
 150 /* the i915, i945 have a single sDVO i2c bus - which is different */
 151 #define MAX_OUTPUTS 6
 152 /* maximum connectors per crtcs in the mode set */
 153
 154 /* Maximum cursor sizes */
 155 #define GEN2_CURSOR_WIDTH 64
 156 #define GEN2_CURSOR_HEIGHT 64
 157 #define MAX_CURSOR_WIDTH 256
 158 #define MAX_CURSOR_HEIGHT 256
 159
 160 #define INTEL_I2C_BUS_DVO 1
 161 #define INTEL_I2C_BUS_SDVO 2
 162
 163 /* these are outputs from the chip - integrated only
 164    external chips are via DVO or SDVO output */
 165 enum intel_output_type {
 166         INTEL_OUTPUT_UNUSED = 0,
 167         INTEL_OUTPUT_ANALOG = 1,
 168         INTEL_OUTPUT_DVO = 2,
 169         INTEL_OUTPUT_SDVO = 3,
 170         INTEL_OUTPUT_LVDS = 4,
 171         INTEL_OUTPUT_TVOUT = 5,
 172         INTEL_OUTPUT_HDMI = 6,
 173         INTEL_OUTPUT_DP = 7,
 174         INTEL_OUTPUT_EDP = 8,
 175         INTEL_OUTPUT_DSI = 9,
 176         INTEL_OUTPUT_UNKNOWN = 10,
 177         INTEL_OUTPUT_DP_MST = 11,
 178 };
 179
 180 #define INTEL_DVO_CHIP_NONE 0
 181 #define INTEL_DVO_CHIP_LVDS 1
 182 #define INTEL_DVO_CHIP_TMDS 2
 183 #define INTEL_DVO_CHIP_TVOUT 4
 184
 185 #define INTEL_DSI_VIDEO_MODE    0
 186 #define INTEL_DSI_COMMAND_MODE  1
 187
 188 struct intel_framebuffer {
 189         struct drm_framebuffer base;
 190         struct drm_i915_gem_object *obj;
 191         struct intel_rotation_info rot_info;
 192
 193         /* for each plane in the normal GTT view */
 194         struct {
 195                 unsigned int x, y;
 196         } normal[2];
 197         /* for each plane in the rotated GTT view */
 198         struct {
 199                 unsigned int x, y;
 200                 unsigned int pitch; /* pixels */
 201         } rotated[2];
 202 };
 203
 204 struct intel_fbdev {
 205         struct drm_fb_helper helper;
 206         struct intel_framebuffer *fb;
 207         struct i915_vma *vma;
 208         async_cookie_t cookie;
 209         int preferred_bpp;
 210 };
 211
 212 struct intel_encoder {
 213         struct drm_encoder base;
 214
 215         enum intel_output_type type;
 216         enum port port;
 217         unsigned int cloneable;
 218         void (*hot_plug)(struct intel_encoder *);
 219         bool (*compute_config)(struct intel_encoder *,
 220                                struct intel_crtc_state *,
 221                                struct drm_connector_state *);
 222         void (*pre_pll_enable)(struct intel_encoder *,
 223                                struct intel_crtc_state *,
 224                                struct drm_connector_state *);
 225         void (*pre_enable)(struct intel_encoder *,
 226                            struct intel_crtc_state *,
 227                            struct drm_connector_state *);
 228         void (*enable)(struct intel_encoder *,
 229                        struct intel_crtc_state *,
 230                        struct drm_connector_state *);
 231         void (*disable)(struct intel_encoder *,
 232                         struct intel_crtc_state *,
 233                         struct drm_connector_state *);
 234         void (*post_disable)(struct intel_encoder *,
 235                              struct intel_crtc_state *,
 236                              struct drm_connector_state *);
 237         void (*post_pll_disable)(struct intel_encoder *,
 238                                  struct intel_crtc_state *,
 239                                  struct drm_connector_state *);
 240         /* Read out the current hw state of this connector, returning true if
 241          * the encoder is active. If the encoder is enabled it also set the pipe
 242          * it is connected to in the pipe parameter. */
 243         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 244         /* Reconstructs the equivalent mode flags for the current hardware
 245          * state. This must be called _after_ display->get_pipe_config has
 246          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 247          * be set correctly before calling this function. */
 248         void (*get_config)(struct intel_encoder *,
 249                            struct intel_crtc_state *pipe_config);
 250         /* Returns a mask of power domains that need to be referenced as part
 251          * of the hardware state readout code. */
 252         u64 (*get_power_domains)(struct intel_encoder *encoder);
 253         /*
 254          * Called during system suspend after all pending requests for the
 255          * encoder are flushed (for example for DP AUX transactions) and
 256          * device interrupts are disabled.
 257          */
 258         void (*suspend)(struct intel_encoder *);
 259         int crtc_mask;
 260         enum hpd_pin hpd_pin;
 261         enum intel_display_power_domain power_domain;
 262         /* for communication with audio component; protected by av_mutex */
 263         const struct drm_connector *audio_connector;
 264 };
 265
 266 struct intel_panel {
 267         struct drm_display_mode *fixed_mode;
 268         struct drm_display_mode *downclock_mode;
 269
 270         /* backlight */
 271         struct {
 272                 bool present;
 273                 u32 level;
 274                 u32 min;
 275                 u32 max;
 276                 bool enabled;
 277                 bool combination_mode;  /* gen 2/4 only */
 278                 bool active_low_pwm;
 279                 bool alternate_pwm_increment;   /* lpt+ */
 280
 281                 /* PWM chip */
 282                 bool util_pin_active_low;       /* bxt+ */
 283                 u8 controller;          /* bxt+ only */
 284                 struct pwm_device *pwm;
 285
 286                 struct backlight_device *device;
 287
 288                 /* Connector and platform specific backlight functions */
 289                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 290                 uint32_t (*get)(struct intel_connector *connector);
 291                 void (*set)(struct intel_connector *connector, uint32_t level);
 292                 void (*disable)(struct intel_connector *connector);
 293                 void (*enable)(struct intel_connector *connector);
 294                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 295                                       uint32_t hz);
 296                 void (*power)(struct intel_connector *, bool enable);
 297         } backlight;
 298 };
 299
 300 struct intel_connector {
 301         struct drm_connector base;
 302         /*
 303          * The fixed encoder this connector is connected to.
 304          */
 305         struct intel_encoder *encoder;
 306
 307         /* ACPI device id for ACPI and driver cooperation */
 308         u32 acpi_device_id;
 309
 310         /* Reads out the current hw, returning true if the connector is enabled
 311          * and active (i.e. dpms ON state). */
 312         bool (*get_hw_state)(struct intel_connector *);
 313
 314         /* Panel info for eDP and LVDS */
 315         struct intel_panel panel;
 316
 317         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 318         struct edid *edid;
 319         struct edid *detect_edid;
 320
 321         /* since POLL and HPD connectors may use the same HPD line keep the native
 322            state of connector->polled in case hotplug storm detection changes it */
 323         u8 polled;
 324
 325         void *port; /* store this opaque as its illegal to dereference it */
 326
 327         struct intel_dp *mst_port;
 328
 329         /* Work struct to schedule a uevent on link train failure */
 330         struct work_struct modeset_retry_work;
 331 };
 332
 333 struct intel_digital_connector_state {
 334         struct drm_connector_state base;
 335
 336         enum hdmi_force_audio force_audio;
 337         int broadcast_rgb;
 338 };
 339
 340 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 341
 342 struct dpll {
 343         /* given values */
 344         int n;
 345         int m1, m2;
 346         int p1, p2;
 347         /* derived values */
 348         int     dot;
 349         int     vco;
 350         int     m;
 351         int     p;
 352 };
 353
 354 struct intel_atomic_state {
 355         struct drm_atomic_state base;
 356
 357         struct {
 358                 /*
 359                  * Logical state of cdclk (used for all scaling, watermark,
 360                  * etc. calculations and checks). This is computed as if all
 361                  * enabled crtcs were active.
 362                  */
 363                 struct intel_cdclk_state logical;
 364
 365                 /*
 366                  * Actual state of cdclk, can be different from the logical
 367                  * state only when all crtc's are DPMS off.
 368                  */
 369                 struct intel_cdclk_state actual;
 370         } cdclk;
 371
 372         bool dpll_set, modeset;
 373
 374         /*
 375          * Does this transaction change the pipes that are active?  This mask
 376          * tracks which CRTC's have changed their active state at the end of
 377          * the transaction (not counting the temporary disable during modesets).
 378          * This mask should only be non-zero when intel_state->modeset is true,
 379          * but the converse is not necessarily true; simply changing a mode may
 380          * not flip the final active status of any CRTC's
 381          */
 382         unsigned int active_pipe_changes;
 383
 384         unsigned int active_crtcs;
 385         unsigned int min_pixclk[I915_MAX_PIPES];
 386
 387         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 388
 389         /*
 390          * Current watermarks can't be trusted during hardware readout, so
 391          * don't bother calculating intermediate watermarks.
 392          */
 393         bool skip_intermediate_wm;
 394
 395         /* Gen9+ only */
 396         struct skl_wm_values wm_results;
 397
 398         struct i915_sw_fence commit_ready;
 399
 400         struct llist_node freed;
 401 };
 402
 403 struct intel_plane_state {
 404         struct drm_plane_state base;
 405         struct drm_rect clip;
 406         struct i915_vma *vma;
 407
 408         struct {
 409                 u32 offset;
 410                 int x, y;
 411         } main;
 412         struct {
 413                 u32 offset;
 414                 int x, y;
 415         } aux;
 416
 417         /* plane control register */
 418         u32 ctl;
 419
 420         /*
 421          * scaler_id
 422          *    = -1 : not using a scaler
 423          *    >=  0 : using a scalers
 424          *
 425          * plane requiring a scaler:
 426          *   - During check_plane, its bit is set in
 427          *     crtc_state->scaler_state.scaler_users by calling helper function
 428          *     update_scaler_plane.
 429          *   - scaler_id indicates the scaler it got assigned.
 430          *
 431          * plane doesn't require a scaler:
 432          *   - this can happen when scaling is no more required or plane simply
 433          *     got disabled.
 434          *   - During check_plane, corresponding bit is reset in
 435          *     crtc_state->scaler_state.scaler_users by calling helper function
 436          *     update_scaler_plane.
 437          */
 438         int scaler_id;
 439
 440         struct drm_intel_sprite_colorkey ckey;
 441 };
 442
 443 struct intel_initial_plane_config {
 444         struct intel_framebuffer *fb;
 445         unsigned int tiling;
 446         int size;
 447         u32 base;
 448 };
 449
 450 #define SKL_MIN_SRC_W 8
 451 #define SKL_MAX_SRC_W 4096
 452 #define SKL_MIN_SRC_H 8
 453 #define SKL_MAX_SRC_H 4096
 454 #define SKL_MIN_DST_W 8
 455 #define SKL_MAX_DST_W 4096
 456 #define SKL_MIN_DST_H 8
 457 #define SKL_MAX_DST_H 4096
 458
 459 struct intel_scaler {
 460         int in_use;
 461         uint32_t mode;
 462 };
 463
 464 struct intel_crtc_scaler_state {
 465 #define SKL_NUM_SCALERS 2
 466         struct intel_scaler scalers[SKL_NUM_SCALERS];
 467
 468         /*
 469          * scaler_users: keeps track of users requesting scalers on this crtc.
 470          *
 471          *     If a bit is set, a user is using a scaler.
 472          *     Here user can be a plane or crtc as defined below:
 473          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 474          *       bit 31    - crtc
 475          *
 476          * Instead of creating a new index to cover planes and crtc, using
 477          * existing drm_plane_index for planes which is well less than 31
 478          * planes and bit 31 for crtc. This should be fine to cover all
 479          * our platforms.
 480          *
 481          * intel_atomic_setup_scalers will setup available scalers to users
 482          * requesting scalers. It will gracefully fail if request exceeds
 483          * avilability.
 484          */
 485 #define SKL_CRTC_INDEX 31
 486         unsigned scaler_users;
 487
 488         /* scaler used by crtc for panel fitting purpose */
 489         int scaler_id;
 490 };
 491
 492 /* drm_mode->private_flags */
 493 #define I915_MODE_FLAG_INHERITED 1
 494
 495 struct intel_pipe_wm {
 496         struct intel_wm_level wm[5];
 497         struct intel_wm_level raw_wm[5];
 498         uint32_t linetime;
 499         bool fbc_wm_enabled;
 500         bool pipe_enabled;
 501         bool sprites_enabled;
 502         bool sprites_scaled;
 503 };
 504
 505 struct skl_plane_wm {
 506         struct skl_wm_level wm[8];
 507         struct skl_wm_level trans_wm;
 508 };
 509
 510 struct skl_pipe_wm {
 511         struct skl_plane_wm planes[I915_MAX_PLANES];
 512         uint32_t linetime;
 513 };
 514
 515 enum vlv_wm_level {
 516         VLV_WM_LEVEL_PM2,
 517         VLV_WM_LEVEL_PM5,
 518         VLV_WM_LEVEL_DDR_DVFS,
 519         NUM_VLV_WM_LEVELS,
 520 };
 521
 522 struct vlv_wm_state {
 523         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 524         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 525         uint8_t num_levels;
 526         bool cxsr;
 527 };
 528
 529 struct vlv_fifo_state {
 530         u16 plane[I915_MAX_PLANES];
 531 };
 532
 533 enum g4x_wm_level {
 534         G4X_WM_LEVEL_NORMAL,
 535         G4X_WM_LEVEL_SR,
 536         G4X_WM_LEVEL_HPLL,
 537         NUM_G4X_WM_LEVELS,
 538 };
 539
 540 struct g4x_wm_state {
 541         struct g4x_pipe_wm wm;
 542         struct g4x_sr_wm sr;
 543         struct g4x_sr_wm hpll;
 544         bool cxsr;
 545         bool hpll_en;
 546         bool fbc_en;
 547 };
 548
 549 struct intel_crtc_wm_state {
 550         union {
 551                 struct {
 552                         /*
 553                          * Intermediate watermarks; these can be
 554                          * programmed immediately since they satisfy
 555                          * both the current configuration we're
 556                          * switching away from and the new
 557                          * configuration we're switching to.
 558                          */
 559                         struct intel_pipe_wm intermediate;
 560
 561                         /*
 562                          * Optimal watermarks, programmed post-vblank
 563                          * when this state is committed.
 564                          */
 565                         struct intel_pipe_wm optimal;
 566                 } ilk;
 567
 568                 struct {
 569                         /* gen9+ only needs 1-step wm programming */
 570                         struct skl_pipe_wm optimal;
 571                         struct skl_ddb_entry ddb;
 572                 } skl;
 573
 574                 struct {
 575                         /* "raw" watermarks (not inverted) */
 576                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 577                         /* intermediate watermarks (inverted) */
 578                         struct vlv_wm_state intermediate;
 579                         /* optimal watermarks (inverted) */
 580                         struct vlv_wm_state optimal;
 581                         /* display FIFO split */
 582                         struct vlv_fifo_state fifo_state;
 583                 } vlv;
 584
 585                 struct {
 586                         /* "raw" watermarks */
 587                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 588                         /* intermediate watermarks */
 589                         struct g4x_wm_state intermediate;
 590                         /* optimal watermarks */
 591                         struct g4x_wm_state optimal;
 592                 } g4x;
 593         };
 594
 595         /*
 596          * Platforms with two-step watermark programming will need to
 597          * update watermark programming post-vblank to switch from the
 598          * safe intermediate watermarks to the optimal final
 599          * watermarks.
 600          */
 601         bool need_postvbl_update;
 602 };
 603
 604 struct intel_crtc_state {
 605         struct drm_crtc_state base;
 606
 607         /**
 608          * quirks - bitfield with hw state readout quirks
 609          *
 610          * For various reasons the hw state readout code might not be able to
 611          * completely faithfully read out the current state. These cases are
 612          * tracked with quirk flags so that fastboot and state checker can act
 613          * accordingly.
 614          */
 615 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 616         unsigned long quirks;
 617
 618         unsigned fb_bits; /* framebuffers to flip */
 619         bool update_pipe; /* can a fast modeset be performed? */
 620         bool disable_cxsr;
 621         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 622         bool fb_changed; /* fb on any of the planes is changed */
 623         bool fifo_changed; /* FIFO split is changed */
 624
 625         /* Pipe source size (ie. panel fitter input size)
 626          * All planes will be positioned inside this space,
 627          * and get clipped at the edges. */
 628         int pipe_src_w, pipe_src_h;
 629
 630         /*
 631          * Pipe pixel rate, adjusted for
 632          * panel fitter/pipe scaler downscaling.
 633          */
 634         unsigned int pixel_rate;
 635
 636         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 637          * between pch encoders and cpu encoders. */
 638         bool has_pch_encoder;
 639
 640         /* Are we sending infoframes on the attached port */
 641         bool has_infoframe;
 642
 643         /* CPU Transcoder for the pipe. Currently this can only differ from the
 644          * pipe on Haswell and later (where we have a special eDP transcoder)
 645          * and Broxton (where we have special DSI transcoders). */
 646         enum transcoder cpu_transcoder;
 647
 648         /*
 649          * Use reduced/limited/broadcast rbg range, compressing from the full
 650          * range fed into the crtcs.
 651          */
 652         bool limited_color_range;
 653
 654         /* Bitmask of encoder types (enum intel_output_type)
 655          * driven by the pipe.
 656          */
 657         unsigned int output_types;
 658
 659         /* Whether we should send NULL infoframes. Required for audio. */
 660         bool has_hdmi_sink;
 661
 662         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 663          * has_dp_encoder is set. */
 664         bool has_audio;
 665
 666         /*
 667          * Enable dithering, used when the selected pipe bpp doesn't match the
 668          * plane bpp.
 669          */
 670         bool dither;
 671
 672         /*
 673          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 674          * compliance video pattern tests.
 675          * Disable dither only if it is a compliance test request for
 676          * 18bpp.
 677          */
 678         bool dither_force_disable;
 679
 680         /* Controls for the clock computation, to override various stages. */
 681         bool clock_set;
 682
 683         /* SDVO TV has a bunch of special case. To make multifunction encoders
 684          * work correctly, we need to track this at runtime.*/
 685         bool sdvo_tv_clock;
 686
 687         /*
 688          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 689          * required. This is set in the 2nd loop of calling encoder's
 690          * ->compute_config if the first pick doesn't work out.
 691          */
 692         bool bw_constrained;
 693
 694         /* Settings for the intel dpll used on pretty much everything but
 695          * haswell. */
 696         struct dpll dpll;
 697
 698         /* Selected dpll when shared or NULL. */
 699         struct intel_shared_dpll *shared_dpll;
 700
 701         /* Actual register state of the dpll, for shared dpll cross-checking. */
 702         struct intel_dpll_hw_state dpll_hw_state;
 703
 704         /* DSI PLL registers */
 705         struct {
 706                 u32 ctrl, div;
 707         } dsi_pll;
 708
 709         int pipe_bpp;
 710         struct intel_link_m_n dp_m_n;
 711
 712         /* m2_n2 for eDP downclock */
 713         struct intel_link_m_n dp_m2_n2;
 714         bool has_drrs;
 715
 716         /*
 717          * Frequence the dpll for the port should run at. Differs from the
 718          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 719          * already multiplied by pixel_multiplier.
 720          */
 721         int port_clock;
 722
 723         /* Used by SDVO (and if we ever fix it, HDMI). */
 724         unsigned pixel_multiplier;
 725
 726         uint8_t lane_count;
 727
 728         /*
 729          * Used by platforms having DP/HDMI PHY with programmable lane
 730          * latency optimization.
 731          */
 732         uint8_t lane_lat_optim_mask;
 733
 734         /* Panel fitter controls for gen2-gen4 + VLV */
 735         struct {
 736                 u32 control;
 737                 u32 pgm_ratios;
 738                 u32 lvds_border_bits;
 739         } gmch_pfit;
 740
 741         /* Panel fitter placement and size for Ironlake+ */
 742         struct {
 743                 u32 pos;
 744                 u32 size;
 745                 bool enabled;
 746                 bool force_thru;
 747         } pch_pfit;
 748
 749         /* FDI configuration, only valid if has_pch_encoder is set. */
 750         int fdi_lanes;
 751         struct intel_link_m_n fdi_m_n;
 752
 753         bool ips_enabled;
 754
 755         bool enable_fbc;
 756
 757         bool double_wide;
 758
 759         int pbn;
 760
 761         struct intel_crtc_scaler_state scaler_state;
 762
 763         /* w/a for waiting 2 vblanks during crtc enable */
 764         enum pipe hsw_workaround_pipe;
 765
 766         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 767         bool disable_lp_wm;
 768
 769         struct intel_crtc_wm_state wm;
 770
 771         /* Gamma mode programmed on the pipe */
 772         uint32_t gamma_mode;
 773
 774         /* bitmask of visible planes (enum plane_id) */
 775         u8 active_planes;
 776
 777         /* HDMI scrambling status */
 778         bool hdmi_scrambling;
 779
 780         /* HDMI High TMDS char rate ratio */
 781         bool hdmi_high_tmds_clock_ratio;
 782 };
 783
 784 struct intel_crtc {
 785         struct drm_crtc base;
 786         enum pipe pipe;
 787         enum plane plane;
 788         u8 lut_r[256], lut_g[256], lut_b[256];
 789         /*
 790          * Whether the crtc and the connected output pipeline is active. Implies
 791          * that crtc->enabled is set, i.e. the current mode configuration has
 792          * some outputs connected to this crtc.
 793          */
 794         bool active;
 795         bool lowfreq_avail;
 796         u8 plane_ids_mask;
 797         unsigned long long enabled_power_domains;
 798         struct intel_overlay *overlay;
 799         struct intel_flip_work *flip_work;
 800
 801         atomic_t unpin_work_count;
 802
 803         /* Display surface base address adjustement for pageflips. Note that on
 804          * gen4+ this only adjusts up to a tile, offsets within a tile are
 805          * handled in the hw itself (with the TILEOFF register). */
 806         u32 dspaddr_offset;
 807         int adjusted_x;
 808         int adjusted_y;
 809
 810         struct intel_crtc_state *config;
 811
 812         /* global reset count when the last flip was submitted */
 813         unsigned int reset_count;
 814
 815         /* Access to these should be protected by dev_priv->irq_lock. */
 816         bool cpu_fifo_underrun_disabled;
 817         bool pch_fifo_underrun_disabled;
 818
 819         /* per-pipe watermark state */
 820         struct {
 821                 /* watermarks currently being used  */
 822                 union {
 823                         struct intel_pipe_wm ilk;
 824                         struct vlv_wm_state vlv;
 825                         struct g4x_wm_state g4x;
 826                 } active;
 827         } wm;
 828
 829         int scanline_offset;
 830
 831         struct {
 832                 unsigned start_vbl_count;
 833                 ktime_t start_vbl_time;
 834                 int min_vbl, max_vbl;
 835                 int scanline_start;
 836         } debug;
 837
 838         /* scalers available on this crtc */
 839         int num_scalers;
 840 };
 841
 842 struct intel_plane {
 843         struct drm_plane base;
 844         u8 plane;
 845         enum plane_id id;
 846         enum pipe pipe;
 847         bool can_scale;
 848         int max_downscale;
 849         uint32_t frontbuffer_bit;
 850
 851         struct {
 852                 u32 base, cntl, size;
 853         } cursor;
 854
 855         /*
 856          * NOTE: Do not place new plane state fields here (e.g., when adding
 857          * new plane properties).  New runtime state should now be placed in
 858          * the intel_plane_state structure and accessed via plane_state.
 859          */
 860
 861         void (*update_plane)(struct intel_plane *plane,
 862                              const struct intel_crtc_state *crtc_state,
 863                              const struct intel_plane_state *plane_state);
 864         void (*disable_plane)(struct intel_plane *plane,
 865                               struct intel_crtc *crtc);
 866         int (*check_plane)(struct intel_plane *plane,
 867                            struct intel_crtc_state *crtc_state,
 868                            struct intel_plane_state *state);
 869 };
 870
 871 struct intel_watermark_params {
 872         u16 fifo_size;
 873         u16 max_wm;
 874         u8 default_wm;
 875         u8 guard_size;
 876         u8 cacheline_size;
 877 };
 878
 879 struct cxsr_latency {
 880         bool is_desktop : 1;
 881         bool is_ddr3 : 1;
 882         u16 fsb_freq;
 883         u16 mem_freq;
 884         u16 display_sr;
 885         u16 display_hpll_disable;
 886         u16 cursor_sr;
 887         u16 cursor_hpll_disable;
 888 };
 889
 890 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 891 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 892 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 893 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 894 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 895 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 896 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 897 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 898 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 899
 900 struct intel_hdmi {
 901         i915_reg_t hdmi_reg;
 902         int ddc_bus;
 903         struct {
 904                 enum drm_dp_dual_mode_type type;
 905                 int max_tmds_clock;
 906         } dp_dual_mode;
 907         bool limited_color_range;
 908         bool color_range_auto;
 909         bool has_hdmi_sink;
 910         bool has_audio;
 911         enum hdmi_force_audio force_audio;
 912         bool rgb_quant_range_selectable;
 913         struct intel_connector *attached_connector;
 914         void (*write_infoframe)(struct drm_encoder *encoder,
 915                                 const struct intel_crtc_state *crtc_state,
 916                                 enum hdmi_infoframe_type type,
 917                                 const void *frame, ssize_t len);
 918         void (*set_infoframes)(struct drm_encoder *encoder,
 919                                bool enable,
 920                                const struct intel_crtc_state *crtc_state,
 921                                const struct drm_connector_state *conn_state);
 922         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 923                                   const struct intel_crtc_state *pipe_config);
 924 };
 925
 926 struct intel_dp_mst_encoder;
 927 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 928
 929 /*
 930  * enum link_m_n_set:
 931  *      When platform provides two set of M_N registers for dp, we can
 932  *      program them and switch between them incase of DRRS.
 933  *      But When only one such register is provided, we have to program the
 934  *      required divider value on that registers itself based on the DRRS state.
 935  *
 936  * M1_N1        : Program dp_m_n on M1_N1 registers
 937  *                        dp_m2_n2 on M2_N2 registers (If supported)
 938  *
 939  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 940  *                        M2_N2 registers are not supported
 941  */
 942
 943 enum link_m_n_set {
 944         /* Sets the m1_n1 and m2_n2 */
 945         M1_N1 = 0,
 946         M2_N2
 947 };
 948
 949 struct intel_dp_desc {
 950         u8 oui[3];
 951         u8 device_id[6];
 952         u8 hw_rev;
 953         u8 sw_major_rev;
 954         u8 sw_minor_rev;
 955 } __packed;
 956
 957 struct intel_dp_compliance_data {
 958         unsigned long edid;
 959         uint8_t video_pattern;
 960         uint16_t hdisplay, vdisplay;
 961         uint8_t bpc;
 962 };
 963
 964 struct intel_dp_compliance {
 965         unsigned long test_type;
 966         struct intel_dp_compliance_data test_data;
 967         bool test_active;
 968         int test_link_rate;
 969         u8 test_lane_count;
 970 };
 971
 972 struct intel_dp {
 973         i915_reg_t output_reg;
 974         i915_reg_t aux_ch_ctl_reg;
 975         i915_reg_t aux_ch_data_reg[5];
 976         uint32_t DP;
 977         int link_rate;
 978         uint8_t lane_count;
 979         uint8_t sink_count;
 980         bool link_mst;
 981         bool has_audio;
 982         bool detect_done;
 983         bool channel_eq_status;
 984         bool reset_link_params;
 985         enum hdmi_force_audio force_audio;
 986         bool limited_color_range;
 987         bool color_range_auto;
 988         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 989         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 990         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 991         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 992         /* source rates */
 993         int num_source_rates;
 994         const int *source_rates;
 995         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 996         int num_sink_rates;
 997         int sink_rates[DP_MAX_SUPPORTED_RATES];
 998         bool use_rate_select;
 999         /* intersection of source and sink rates */
1000         int num_common_rates;
1001         int common_rates[DP_MAX_SUPPORTED_RATES];
1002         /* Max lane count for the current link */
1003         int max_link_lane_count;
1004         /* Max rate for the current link */
1005         int max_link_rate;
1006         /* sink or branch descriptor */
1007         struct intel_dp_desc desc;
1008         struct drm_dp_aux aux;
1009         enum intel_display_power_domain aux_power_domain;
1010         uint8_t train_set[4];
1011         int panel_power_up_delay;
1012         int panel_power_down_delay;
1013         int panel_power_cycle_delay;
1014         int backlight_on_delay;
1015         int backlight_off_delay;
1016         struct delayed_work panel_vdd_work;
1017         bool want_panel_vdd;
1018         unsigned long last_power_on;
1019         unsigned long last_backlight_off;
1020         ktime_t panel_power_off_time;
1021
1022         struct notifier_block edp_notifier;
1023
1024         /*
1025          * Pipe whose power sequencer is currently locked into
1026          * this port. Only relevant on VLV/CHV.
1027          */
1028         enum pipe pps_pipe;
1029         /*
1030          * Pipe currently driving the port. Used for preventing
1031          * the use of the PPS for any pipe currentrly driving
1032          * external DP as that will mess things up on VLV.
1033          */
1034         enum pipe active_pipe;
1035         /*
1036          * Set if the sequencer may be reset due to a power transition,
1037          * requiring a reinitialization. Only relevant on BXT.
1038          */
1039         bool pps_reset;
1040         struct edp_power_seq pps_delays;
1041
1042         bool can_mst; /* this port supports mst */
1043         bool is_mst;
1044         int active_mst_links;
1045         /* connector directly attached - won't be use for modeset in mst world */
1046         struct intel_connector *attached_connector;
1047
1048         /* mst connector list */
1049         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1050         struct drm_dp_mst_topology_mgr mst_mgr;
1051
1052         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1053         /*
1054          * This function returns the value we have to program the AUX_CTL
1055          * register with to kick off an AUX transaction.
1056          */
1057         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1058                                      bool has_aux_irq,
1059                                      int send_bytes,
1060                                      uint32_t aux_clock_divider);
1061
1062         /* This is called before a link training is starterd */
1063         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1064
1065         /* Displayport compliance testing */
1066         struct intel_dp_compliance compliance;
1067 };
1068
1069 struct intel_lspcon {
1070         bool active;
1071         enum drm_lspcon_mode mode;
1072 };
1073
1074 struct intel_digital_port {
1075         struct intel_encoder base;
1076         enum port port;
1077         u32 saved_port_bits;
1078         struct intel_dp dp;
1079         struct intel_hdmi hdmi;
1080         struct intel_lspcon lspcon;
1081         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1082         bool release_cl2_override;
1083         uint8_t max_lanes;
1084         enum intel_display_power_domain ddi_io_power_domain;
1085 };
1086
1087 struct intel_dp_mst_encoder {
1088         struct intel_encoder base;
1089         enum pipe pipe;
1090         struct intel_digital_port *primary;
1091         struct intel_connector *connector;
1092 };
1093
1094 static inline enum dpio_channel
1095 vlv_dport_to_channel(struct intel_digital_port *dport)
1096 {
1097         switch (dport->port) {
1098         case PORT_B:
1099         case PORT_D:
1100                 return DPIO_CH0;
1101         case PORT_C:
1102                 return DPIO_CH1;
1103         default:
1104                 BUG();
1105         }
1106 }
1107
1108 static inline enum dpio_phy
1109 vlv_dport_to_phy(struct intel_digital_port *dport)
1110 {
1111         switch (dport->port) {
1112         case PORT_B:
1113         case PORT_C:
1114                 return DPIO_PHY0;
1115         case PORT_D:
1116                 return DPIO_PHY1;
1117         default:
1118                 BUG();
1119         }
1120 }
1121
1122 static inline enum dpio_channel
1123 vlv_pipe_to_channel(enum pipe pipe)
1124 {
1125         switch (pipe) {
1126         case PIPE_A:
1127         case PIPE_C:
1128                 return DPIO_CH0;
1129         case PIPE_B:
1130                 return DPIO_CH1;
1131         default:
1132                 BUG();
1133         }
1134 }
1135
1136 static inline struct intel_crtc *
1137 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1138 {
1139         return dev_priv->pipe_to_crtc_mapping[pipe];
1140 }
1141
1142 static inline struct intel_crtc *
1143 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1144 {
1145         return dev_priv->plane_to_crtc_mapping[plane];
1146 }
1147
1148 struct intel_flip_work {
1149         struct work_struct unpin_work;
1150         struct work_struct mmio_work;
1151
1152         struct drm_crtc *crtc;
1153         struct i915_vma *old_vma;
1154         struct drm_framebuffer *old_fb;
1155         struct drm_i915_gem_object *pending_flip_obj;
1156         struct drm_pending_vblank_event *event;
1157         atomic_t pending;
1158         u32 flip_count;
1159         u32 gtt_offset;
1160         struct drm_i915_gem_request *flip_queued_req;
1161         u32 flip_queued_vblank;
1162         u32 flip_ready_vblank;
1163         unsigned int rotation;
1164 };
1165
1166 struct intel_load_detect_pipe {
1167         struct drm_atomic_state *restore_state;
1168 };
1169
1170 static inline struct intel_encoder *
1171 intel_attached_encoder(struct drm_connector *connector)
1172 {
1173         return to_intel_connector(connector)->encoder;
1174 }
1175
1176 static inline struct intel_digital_port *
1177 enc_to_dig_port(struct drm_encoder *encoder)
1178 {
1179         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1180
1181         switch (intel_encoder->type) {
1182         case INTEL_OUTPUT_UNKNOWN:
1183                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1184         case INTEL_OUTPUT_DP:
1185         case INTEL_OUTPUT_EDP:
1186         case INTEL_OUTPUT_HDMI:
1187                 return container_of(encoder, struct intel_digital_port,
1188                                     base.base);
1189         default:
1190                 return NULL;
1191         }
1192 }
1193
1194 static inline struct intel_dp_mst_encoder *
1195 enc_to_mst(struct drm_encoder *encoder)
1196 {
1197         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1198 }
1199
1200 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1201 {
1202         return &enc_to_dig_port(encoder)->dp;
1203 }
1204
1205 static inline struct intel_digital_port *
1206 dp_to_dig_port(struct intel_dp *intel_dp)
1207 {
1208         return container_of(intel_dp, struct intel_digital_port, dp);
1209 }
1210
1211 static inline struct intel_lspcon *
1212 dp_to_lspcon(struct intel_dp *intel_dp)
1213 {
1214         return &dp_to_dig_port(intel_dp)->lspcon;
1215 }
1216
1217 static inline struct intel_digital_port *
1218 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1219 {
1220         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1221 }
1222
1223 /* intel_fifo_underrun.c */
1224 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1225                                            enum pipe pipe, bool enable);
1226 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1227                                            enum transcoder pch_transcoder,
1228                                            bool enable);
1229 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1230                                          enum pipe pipe);
1231 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1232                                          enum transcoder pch_transcoder);
1233 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1234 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1235
1236 /* i915_irq.c */
1237 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1238 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1239 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1240 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1241 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1242 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1243 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1244 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1245 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1246 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1247
1248 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1249                                             u32 mask)
1250 {
1251         return mask & ~i915->rps.pm_intrmsk_mbz;
1252 }
1253
1254 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1255 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1256 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1257 {
1258         /*
1259          * We only use drm_irq_uninstall() at unload and VT switch, so
1260          * this is the only thing we need to check.
1261          */
1262         return dev_priv->pm.irqs_enabled;
1263 }
1264
1265 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1266 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1267                                      unsigned int pipe_mask);
1268 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1269                                      unsigned int pipe_mask);
1270 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1271 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1272 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1273
1274 /* intel_crt.c */
1275 void intel_crt_init(struct drm_i915_private *dev_priv);
1276 void intel_crt_reset(struct drm_encoder *encoder);
1277
1278 /* intel_ddi.c */
1279 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1280                                 struct intel_crtc_state *old_crtc_state,
1281                                 struct drm_connector_state *old_conn_state);
1282 void hsw_fdi_link_train(struct intel_crtc *crtc,
1283                         const struct intel_crtc_state *crtc_state);
1284 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1285 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1286 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1287 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1288 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1289                                        enum transcoder cpu_transcoder);
1290 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1291 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1292 struct intel_encoder *
1293 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1294 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1295 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1296 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1297 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1298                                  struct intel_crtc *intel_crtc);
1299 void intel_ddi_get_config(struct intel_encoder *encoder,
1300                           struct intel_crtc_state *pipe_config);
1301
1302 void intel_ddi_clock_get(struct intel_encoder *encoder,
1303                          struct intel_crtc_state *pipe_config);
1304 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1305                                     bool state);
1306 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1307 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1308
1309 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1310                                    int plane, unsigned int height);
1311
1312 /* intel_audio.c */
1313 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1314 void intel_audio_codec_enable(struct intel_encoder *encoder,
1315                               const struct intel_crtc_state *crtc_state,
1316                               const struct drm_connector_state *conn_state);
1317 void intel_audio_codec_disable(struct intel_encoder *encoder);
1318 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1319 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1320 void intel_audio_init(struct drm_i915_private *dev_priv);
1321 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1322
1323 /* intel_cdclk.c */
1324 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1325 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1326 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1327 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1328 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1329 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1330 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1331 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1332 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1333                                const struct intel_cdclk_state *b);
1334 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1335                      const struct intel_cdclk_state *cdclk_state);
1336
1337 /* intel_display.c */
1338 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1339 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1340 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1341 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1342                       const char *name, u32 reg, int ref_freq);
1343 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1344                            const char *name, u32 reg);
1345 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1346 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1347 extern const struct drm_plane_funcs intel_plane_funcs;
1348 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1349 unsigned int intel_fb_xy_to_linear(int x, int y,
1350                                    const struct intel_plane_state *state,
1351                                    int plane);
1352 void intel_add_fb_offsets(int *x, int *y,
1353                           const struct intel_plane_state *state, int plane);
1354 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1355 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1356 void intel_mark_busy(struct drm_i915_private *dev_priv);
1357 void intel_mark_idle(struct drm_i915_private *dev_priv);
1358 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1359 int intel_display_suspend(struct drm_device *dev);
1360 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1361 void intel_encoder_destroy(struct drm_encoder *encoder);
1362 int intel_connector_init(struct intel_connector *);
1363 struct intel_connector *intel_connector_alloc(void);
1364 bool intel_connector_get_hw_state(struct intel_connector *connector);
1365 void intel_connector_attach_encoder(struct intel_connector *connector,
1366                                     struct intel_encoder *encoder);
1367 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1368                                              struct drm_crtc *crtc);
1369 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1370 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1371                                 struct drm_file *file_priv);
1372 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1373                                              enum pipe pipe);
1374 static inline bool
1375 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1376                     enum intel_output_type type)
1377 {
1378         return crtc_state->output_types & (1 << type);
1379 }
1380 static inline bool
1381 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1382 {
1383         return crtc_state->output_types &
1384                 ((1 << INTEL_OUTPUT_DP) |
1385                  (1 << INTEL_OUTPUT_DP_MST) |
1386                  (1 << INTEL_OUTPUT_EDP));
1387 }
1388 static inline void
1389 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1390 {
1391         drm_wait_one_vblank(&dev_priv->drm, pipe);
1392 }
1393 static inline void
1394 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1395 {
1396         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1397
1398         if (crtc->active)
1399                 intel_wait_for_vblank(dev_priv, pipe);
1400 }
1401
1402 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1403
1404 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1405 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1406                          struct intel_digital_port *dport,
1407                          unsigned int expected_mask);
1408 int intel_get_load_detect_pipe(struct drm_connector *connector,
1409                                struct drm_display_mode *mode,
1410                                struct intel_load_detect_pipe *old,
1411                                struct drm_modeset_acquire_ctx *ctx);
1412 void intel_release_load_detect_pipe(struct drm_connector *connector,
1413                                     struct intel_load_detect_pipe *old,
1414                                     struct drm_modeset_acquire_ctx *ctx);
1415 struct i915_vma *
1416 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1417 void intel_unpin_fb_vma(struct i915_vma *vma);
1418 struct drm_framebuffer *
1419 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1420                          struct drm_mode_fb_cmd2 *mode_cmd);
1421 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1422 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1423 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1424 int intel_prepare_plane_fb(struct drm_plane *plane,
1425                            struct drm_plane_state *new_state);
1426 void intel_cleanup_plane_fb(struct drm_plane *plane,
1427                             struct drm_plane_state *old_state);
1428 int intel_plane_atomic_get_property(struct drm_plane *plane,
1429                                     const struct drm_plane_state *state,
1430                                     struct drm_property *property,
1431                                     uint64_t *val);
1432 int intel_plane_atomic_set_property(struct drm_plane *plane,
1433                                     struct drm_plane_state *state,
1434                                     struct drm_property *property,
1435                                     uint64_t val);
1436 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1437                                     struct drm_plane_state *plane_state);
1438
1439 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1440                                     enum pipe pipe);
1441
1442 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1443                      const struct dpll *dpll);
1444 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1445 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1446
1447 /* modesetting asserts */
1448 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1449                            enum pipe pipe);
1450 void assert_pll(struct drm_i915_private *dev_priv,
1451                 enum pipe pipe, bool state);
1452 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1453 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1454 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1455 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1456 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1457 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1458                        enum pipe pipe, bool state);
1459 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1460 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1461 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1462 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1463 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1464 u32 intel_compute_tile_offset(int *x, int *y,
1465                               const struct intel_plane_state *state, int plane);
1466 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1467 void intel_finish_reset(struct drm_i915_private *dev_priv);
1468 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1469 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1470 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1471 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1472 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1473 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1474 unsigned int skl_cdclk_get_vco(unsigned int freq);
1475 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1476 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1477 void intel_dp_get_m_n(struct intel_crtc *crtc,
1478                       struct intel_crtc_state *pipe_config);
1479 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1480 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1481 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1482                         struct dpll *best_clock);
1483 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1484
1485 bool intel_crtc_active(struct intel_crtc *crtc);
1486 void hsw_enable_ips(struct intel_crtc *crtc);
1487 void hsw_disable_ips(struct intel_crtc *crtc);
1488 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1489 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1490                                  struct intel_crtc_state *pipe_config);
1491
1492 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1493 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1494
1495 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1496 {
1497         return i915_ggtt_offset(state->vma);
1498 }
1499
1500 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1501                   const struct intel_plane_state *plane_state);
1502 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1503                      unsigned int rotation);
1504 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1505 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1506
1507 /* intel_csr.c */
1508 void intel_csr_ucode_init(struct drm_i915_private *);
1509 void intel_csr_load_program(struct drm_i915_private *);
1510 void intel_csr_ucode_fini(struct drm_i915_private *);
1511 void intel_csr_ucode_suspend(struct drm_i915_private *);
1512 void intel_csr_ucode_resume(struct drm_i915_private *);
1513
1514 /* intel_dp.c */
1515 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1516                    enum port port);
1517 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1518                              struct intel_connector *intel_connector);
1519 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1520                               int link_rate, uint8_t lane_count,
1521                               bool link_mst);
1522 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1523                                             int link_rate, uint8_t lane_count);
1524 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1525 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1526 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1527 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1528 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1529 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1530 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1531 bool intel_dp_compute_config(struct intel_encoder *encoder,
1532                              struct intel_crtc_state *pipe_config,
1533                              struct drm_connector_state *conn_state);
1534 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1535 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1536                                   bool long_hpd);
1537 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1538 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1539 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1540 void intel_edp_panel_on(struct intel_dp *intel_dp);
1541 void intel_edp_panel_off(struct intel_dp *intel_dp);
1542 void intel_dp_mst_suspend(struct drm_device *dev);
1543 void intel_dp_mst_resume(struct drm_device *dev);
1544 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1545 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1546 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1547 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1548 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1549 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1550 void intel_plane_destroy(struct drm_plane *plane);
1551 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1552                            struct intel_crtc_state *crtc_state);
1553 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1554                            struct intel_crtc_state *crtc_state);
1555 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1556                                unsigned int frontbuffer_bits);
1557 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1558                           unsigned int frontbuffer_bits);
1559
1560 void
1561 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1562                                        uint8_t dp_train_pat);
1563 void
1564 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1565 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1566 uint8_t
1567 intel_dp_voltage_max(struct intel_dp *intel_dp);
1568 uint8_t
1569 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1570 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1571                            uint8_t *link_bw, uint8_t *rate_select);
1572 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1573 bool
1574 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1575
1576 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1577 {
1578         return ~((1 << lane_count) - 1) & 0xf;
1579 }
1580
1581 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1582 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1583                           struct intel_dp_desc *desc);
1584 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1585 int intel_dp_link_required(int pixel_clock, int bpp);
1586 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1587 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1588                                   struct intel_digital_port *port);
1589
1590 /* intel_dp_aux_backlight.c */
1591 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1592
1593 /* intel_dp_mst.c */
1594 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1595 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1596 /* intel_dsi.c */
1597 void intel_dsi_init(struct drm_i915_private *dev_priv);
1598
1599 /* intel_dsi_dcs_backlight.c */
1600 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1601
1602 /* intel_dvo.c */
1603 void intel_dvo_init(struct drm_i915_private *dev_priv);
1604 /* intel_hotplug.c */
1605 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1606
1607
1608 /* legacy fbdev emulation in intel_fbdev.c */
1609 #ifdef CONFIG_DRM_FBDEV_EMULATION
1610 extern int intel_fbdev_init(struct drm_device *dev);
1611 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1612 extern void intel_fbdev_fini(struct drm_device *dev);
1613 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1614 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1615 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1616 #else
1617 static inline int intel_fbdev_init(struct drm_device *dev)
1618 {
1619         return 0;
1620 }
1621
1622 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1623 {
1624 }
1625
1626 static inline void intel_fbdev_fini(struct drm_device *dev)
1627 {
1628 }
1629
1630 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1631 {
1632 }
1633
1634 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1635 {
1636 }
1637
1638 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1639 {
1640 }
1641 #endif
1642
1643 /* intel_fbc.c */
1644 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1645                            struct drm_atomic_state *state);
1646 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1647 void intel_fbc_pre_update(struct intel_crtc *crtc,
1648                           struct intel_crtc_state *crtc_state,
1649                           struct intel_plane_state *plane_state);
1650 void intel_fbc_post_update(struct intel_crtc *crtc);
1651 void intel_fbc_init(struct drm_i915_private *dev_priv);
1652 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1653 void intel_fbc_enable(struct intel_crtc *crtc,
1654                       struct intel_crtc_state *crtc_state,
1655                       struct intel_plane_state *plane_state);
1656 void intel_fbc_disable(struct intel_crtc *crtc);
1657 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1658 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1659                           unsigned int frontbuffer_bits,
1660                           enum fb_op_origin origin);
1661 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1662                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1663 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1664 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1665
1666 /* intel_hdmi.c */
1667 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1668                      enum port port);
1669 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1670                                struct intel_connector *intel_connector);
1671 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1672 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1673                                struct intel_crtc_state *pipe_config,
1674                                struct drm_connector_state *conn_state);
1675 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1676                                        struct drm_connector *connector,
1677                                        bool high_tmds_clock_ratio,
1678                                        bool scrambling);
1679 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1680
1681
1682 /* intel_lvds.c */
1683 void intel_lvds_init(struct drm_i915_private *dev_priv);
1684 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1685 bool intel_is_dual_link_lvds(struct drm_device *dev);
1686
1687
1688 /* intel_modes.c */
1689 int intel_connector_update_modes(struct drm_connector *connector,
1690                                  struct edid *edid);
1691 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1692 void intel_attach_force_audio_property(struct drm_connector *connector);
1693 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1694 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1695
1696
1697 /* intel_overlay.c */
1698 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1699 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1700 int intel_overlay_switch_off(struct intel_overlay *overlay);
1701 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1702                                   struct drm_file *file_priv);
1703 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1704                               struct drm_file *file_priv);
1705 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1706
1707
1708 /* intel_panel.c */
1709 int intel_panel_init(struct intel_panel *panel,
1710                      struct drm_display_mode *fixed_mode,
1711                      struct drm_display_mode *downclock_mode);
1712 void intel_panel_fini(struct intel_panel *panel);
1713 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1714                             struct drm_display_mode *adjusted_mode);
1715 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1716                              struct intel_crtc_state *pipe_config,
1717                              int fitting_mode);
1718 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1719                               struct intel_crtc_state *pipe_config,
1720                               int fitting_mode);
1721 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1722                                     u32 level, u32 max);
1723 int intel_panel_setup_backlight(struct drm_connector *connector,
1724                                 enum pipe pipe);
1725 void intel_panel_enable_backlight(struct intel_connector *connector);
1726 void intel_panel_disable_backlight(struct intel_connector *connector);
1727 void intel_panel_destroy_backlight(struct drm_connector *connector);
1728 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1729 extern struct drm_display_mode *intel_find_panel_downclock(
1730                                 struct drm_i915_private *dev_priv,
1731                                 struct drm_display_mode *fixed_mode,
1732                                 struct drm_connector *connector);
1733
1734 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1735 int intel_backlight_device_register(struct intel_connector *connector);
1736 void intel_backlight_device_unregister(struct intel_connector *connector);
1737 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1738 static int intel_backlight_device_register(struct intel_connector *connector)
1739 {
1740         return 0;
1741 }
1742 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1743 {
1744 }
1745 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1746
1747
1748 /* intel_psr.c */
1749 void intel_psr_enable(struct intel_dp *intel_dp);
1750 void intel_psr_disable(struct intel_dp *intel_dp);
1751 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1752                           unsigned frontbuffer_bits);
1753 void intel_psr_flush(struct drm_i915_private *dev_priv,
1754                      unsigned frontbuffer_bits,
1755                      enum fb_op_origin origin);
1756 void intel_psr_init(struct drm_i915_private *dev_priv);
1757 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1758                                    unsigned frontbuffer_bits);
1759
1760 /* intel_runtime_pm.c */
1761 int intel_power_domains_init(struct drm_i915_private *);
1762 void intel_power_domains_fini(struct drm_i915_private *);
1763 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1764 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1765 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1766 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1767 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1768 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1769 const char *
1770 intel_display_power_domain_str(enum intel_display_power_domain domain);
1771
1772 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1773                                     enum intel_display_power_domain domain);
1774 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1775                                       enum intel_display_power_domain domain);
1776 void intel_display_power_get(struct drm_i915_private *dev_priv,
1777                              enum intel_display_power_domain domain);
1778 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1779                                         enum intel_display_power_domain domain);
1780 void intel_display_power_put(struct drm_i915_private *dev_priv,
1781                              enum intel_display_power_domain domain);
1782
1783 static inline void
1784 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1785 {
1786         WARN_ONCE(dev_priv->pm.suspended,
1787                   "Device suspended during HW access\n");
1788 }
1789
1790 static inline void
1791 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1792 {
1793         assert_rpm_device_not_suspended(dev_priv);
1794         WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1795                   "RPM wakelock ref not held during HW access");
1796 }
1797
1798 /**
1799  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1800  * @dev_priv: i915 device instance
1801  *
1802  * This function disable asserts that check if we hold an RPM wakelock
1803  * reference, while keeping the device-not-suspended checks still enabled.
1804  * It's meant to be used only in special circumstances where our rule about
1805  * the wakelock refcount wrt. the device power state doesn't hold. According
1806  * to this rule at any point where we access the HW or want to keep the HW in
1807  * an active state we must hold an RPM wakelock reference acquired via one of
1808  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1809  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1810  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1811  * users should avoid using this function.
1812  *
1813  * Any calls to this function must have a symmetric call to
1814  * enable_rpm_wakeref_asserts().
1815  */
1816 static inline void
1817 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1818 {
1819         atomic_inc(&dev_priv->pm.wakeref_count);
1820 }
1821
1822 /**
1823  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1824  * @dev_priv: i915 device instance
1825  *
1826  * This function re-enables the RPM assert checks after disabling them with
1827  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1828  * circumstances otherwise its use should be avoided.
1829  *
1830  * Any calls to this function must have a symmetric call to
1831  * disable_rpm_wakeref_asserts().
1832  */
1833 static inline void
1834 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1835 {
1836         atomic_dec(&dev_priv->pm.wakeref_count);
1837 }
1838
1839 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1840 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1841 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1842 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1843
1844 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1845
1846 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1847                              bool override, unsigned int mask);
1848 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1849                           enum dpio_channel ch, bool override);
1850
1851
1852 /* intel_pm.c */
1853 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1854 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1855 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1856 void intel_update_watermarks(struct intel_crtc *crtc);
1857 void intel_init_pm(struct drm_i915_private *dev_priv);
1858 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1859 void intel_pm_setup(struct drm_i915_private *dev_priv);
1860 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1861 void intel_gpu_ips_teardown(void);
1862 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1863 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1864 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1865 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1866 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1867 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1868 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1869 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1870 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1871 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1872 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1873                     struct intel_rps_client *rps,
1874                     unsigned long submitted);
1875 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1876 void g4x_wm_get_hw_state(struct drm_device *dev);
1877 void vlv_wm_get_hw_state(struct drm_device *dev);
1878 void ilk_wm_get_hw_state(struct drm_device *dev);
1879 void skl_wm_get_hw_state(struct drm_device *dev);
1880 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1881                           struct skl_ddb_allocation *ddb /* out */);
1882 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1883                               struct skl_pipe_wm *out);
1884 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1885 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1886 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1887 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1888 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1889 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1890                          const struct skl_wm_level *l2);
1891 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1892                                  const struct skl_ddb_entry *ddb,
1893                                  int ignore);
1894 bool ilk_disable_lp_wm(struct drm_device *dev);
1895 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1896 static inline int intel_enable_rc6(void)
1897 {
1898         return i915.enable_rc6;
1899 }
1900
1901 /* intel_sdvo.c */
1902 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1903                      i915_reg_t reg, enum port port);
1904
1905
1906 /* intel_sprite.c */
1907 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1908                              int usecs);
1909 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1910                                               enum pipe pipe, int plane);
1911 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1912                               struct drm_file *file_priv);
1913 void intel_pipe_update_start(struct intel_crtc *crtc);
1914 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1915
1916 /* intel_tv.c */
1917 void intel_tv_init(struct drm_i915_private *dev_priv);
1918
1919 /* intel_atomic.c */
1920 int intel_connector_atomic_get_property(struct drm_connector *connector,
1921                                         const struct drm_connector_state *state,
1922                                         struct drm_property *property,
1923                                         uint64_t *val);
1924
1925 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
1926                                                 const struct drm_connector_state *state,
1927                                                 struct drm_property *property,
1928                                                 uint64_t *val);
1929 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
1930                                                 struct drm_connector_state *state,
1931                                                 struct drm_property *property,
1932                                                 uint64_t val);
1933 int intel_digital_connector_atomic_check(struct drm_connector *conn,
1934                                          struct drm_connector_state *new_state);
1935 struct drm_connector_state *
1936 intel_digital_connector_duplicate_state(struct drm_connector *connector);
1937
1938 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1939 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1940                                struct drm_crtc_state *state);
1941 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1942 void intel_atomic_state_clear(struct drm_atomic_state *);
1943
1944 static inline struct intel_crtc_state *
1945 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1946                             struct intel_crtc *crtc)
1947 {
1948         struct drm_crtc_state *crtc_state;
1949         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1950         if (IS_ERR(crtc_state))
1951                 return ERR_CAST(crtc_state);
1952
1953         return to_intel_crtc_state(crtc_state);
1954 }
1955
1956 static inline struct intel_crtc_state *
1957 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1958                                      struct intel_crtc *crtc)
1959 {
1960         struct drm_crtc_state *crtc_state;
1961
1962         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1963
1964         if (crtc_state)
1965                 return to_intel_crtc_state(crtc_state);
1966         else
1967                 return NULL;
1968 }
1969
1970 static inline struct intel_plane_state *
1971 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1972                                       struct intel_plane *plane)
1973 {
1974         struct drm_plane_state *plane_state;
1975
1976         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1977
1978         return to_intel_plane_state(plane_state);
1979 }
1980
1981 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1982                                struct intel_crtc *intel_crtc,
1983                                struct intel_crtc_state *crtc_state);
1984
1985 /* intel_atomic_plane.c */
1986 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1987 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1988 void intel_plane_destroy_state(struct drm_plane *plane,
1989                                struct drm_plane_state *state);
1990 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1991 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1992                                         struct intel_plane_state *intel_state);
1993
1994 /* intel_color.c */
1995 void intel_color_init(struct drm_crtc *crtc);
1996 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1997 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1998 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1999
2000 /* intel_lspcon.c */
2001 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2002 void lspcon_resume(struct intel_lspcon *lspcon);
2003 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2004
2005 /* intel_pipe_crc.c */
2006 int intel_pipe_crc_create(struct drm_minor *minor);
2007 #ifdef CONFIG_DEBUG_FS
2008 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2009                               size_t *values_cnt);
2010 #else
2011 #define intel_crtc_set_crc_source NULL
2012 #endif
2013 extern const struct file_operations i915_display_crc_ctl_fops;
2014 #endif /* __INTEL_DRV_H__ */