2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
42 #include <media/cec-notifier.h>
45 * __wait_for - magic wait macro
47 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
48 * important that we check the condition again after having timed out, since the
49 * timeout could be due to preemption or similar and we've never had a chance to
50 * check the condition before the timeout.
52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
53 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
54 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
58 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
60 /* Guarantee COND check prior to timeout */ \
70 usleep_range(wait__, wait__ * 2); \
71 if (wait__ < (Wmax)) \
77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
79 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
88 #define _wait_for_atomic(COND, US, ATOMIC) \
90 int cpu, ret, timeout = (US) * 1000; \
92 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
95 cpu = smp_processor_id(); \
97 base = local_clock(); \
99 u64 now = local_clock(); \
102 /* Guarantee COND check prior to timeout */ \
108 if (now - base >= timeout) { \
115 if (unlikely(cpu != smp_processor_id())) { \
116 timeout -= now - base; \
117 cpu = smp_processor_id(); \
118 base = local_clock(); \
125 #define wait_for_us(COND, US) \
128 BUILD_BUG_ON(!__builtin_constant_p(US)); \
130 ret__ = _wait_for((COND), (US), 10, 10); \
132 ret__ = _wait_for_atomic((COND), (US), 0); \
136 #define wait_for_atomic_us(COND, US) \
138 BUILD_BUG_ON(!__builtin_constant_p(US)); \
139 BUILD_BUG_ON((US) > 50000); \
140 _wait_for_atomic((COND), (US), 1); \
143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
145 #define KHz(x) (1000 * (x))
146 #define MHz(x) KHz(1000 * (x))
148 #define KBps(x) (1000 * (x))
149 #define MBps(x) KBps(1000 * (x))
150 #define GBps(x) ((u64)1000 * MBps((x)))
153 * Display related stuff
156 /* store information about an Ixxx DVO */
157 /* The i830->i865 use multiple DVOs with multiple i2cs */
158 /* the i915, i945 have a single sDVO i2c bus - which is different */
159 #define MAX_OUTPUTS 6
160 /* maximum connectors per crtcs in the mode set */
162 #define INTEL_I2C_BUS_DVO 1
163 #define INTEL_I2C_BUS_SDVO 2
165 /* these are outputs from the chip - integrated only
166 external chips are via DVO or SDVO output */
167 enum intel_output_type {
168 INTEL_OUTPUT_UNUSED = 0,
169 INTEL_OUTPUT_ANALOG = 1,
170 INTEL_OUTPUT_DVO = 2,
171 INTEL_OUTPUT_SDVO = 3,
172 INTEL_OUTPUT_LVDS = 4,
173 INTEL_OUTPUT_TVOUT = 5,
174 INTEL_OUTPUT_HDMI = 6,
176 INTEL_OUTPUT_EDP = 8,
177 INTEL_OUTPUT_DSI = 9,
178 INTEL_OUTPUT_DDI = 10,
179 INTEL_OUTPUT_DP_MST = 11,
182 #define INTEL_DVO_CHIP_NONE 0
183 #define INTEL_DVO_CHIP_LVDS 1
184 #define INTEL_DVO_CHIP_TMDS 2
185 #define INTEL_DVO_CHIP_TVOUT 4
187 #define INTEL_DSI_VIDEO_MODE 0
188 #define INTEL_DSI_COMMAND_MODE 1
190 struct intel_framebuffer {
191 struct drm_framebuffer base;
192 struct intel_rotation_info rot_info;
194 /* for each plane in the normal GTT view */
198 /* for each plane in the rotated GTT view */
201 unsigned int pitch; /* pixels */
206 struct drm_fb_helper helper;
207 struct intel_framebuffer *fb;
208 struct i915_vma *vma;
209 unsigned long vma_flags;
210 async_cookie_t cookie;
214 struct intel_encoder {
215 struct drm_encoder base;
217 enum intel_output_type type;
219 unsigned int cloneable;
220 bool (*hotplug)(struct intel_encoder *encoder,
221 struct intel_connector *connector);
222 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
223 struct intel_crtc_state *,
224 struct drm_connector_state *);
225 bool (*compute_config)(struct intel_encoder *,
226 struct intel_crtc_state *,
227 struct drm_connector_state *);
228 void (*pre_pll_enable)(struct intel_encoder *,
229 const struct intel_crtc_state *,
230 const struct drm_connector_state *);
231 void (*pre_enable)(struct intel_encoder *,
232 const struct intel_crtc_state *,
233 const struct drm_connector_state *);
234 void (*enable)(struct intel_encoder *,
235 const struct intel_crtc_state *,
236 const struct drm_connector_state *);
237 void (*disable)(struct intel_encoder *,
238 const struct intel_crtc_state *,
239 const struct drm_connector_state *);
240 void (*post_disable)(struct intel_encoder *,
241 const struct intel_crtc_state *,
242 const struct drm_connector_state *);
243 void (*post_pll_disable)(struct intel_encoder *,
244 const struct intel_crtc_state *,
245 const struct drm_connector_state *);
246 /* Read out the current hw state of this connector, returning true if
247 * the encoder is active. If the encoder is enabled it also set the pipe
248 * it is connected to in the pipe parameter. */
249 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
250 /* Reconstructs the equivalent mode flags for the current hardware
251 * state. This must be called _after_ display->get_pipe_config has
252 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
253 * be set correctly before calling this function. */
254 void (*get_config)(struct intel_encoder *,
255 struct intel_crtc_state *pipe_config);
256 /* Returns a mask of power domains that need to be referenced as part
257 * of the hardware state readout code. */
258 u64 (*get_power_domains)(struct intel_encoder *encoder,
259 struct intel_crtc_state *crtc_state);
261 * Called during system suspend after all pending requests for the
262 * encoder are flushed (for example for DP AUX transactions) and
263 * device interrupts are disabled.
265 void (*suspend)(struct intel_encoder *);
267 enum hpd_pin hpd_pin;
268 enum intel_display_power_domain power_domain;
269 /* for communication with audio component; protected by av_mutex */
270 const struct drm_connector *audio_connector;
274 struct drm_display_mode *fixed_mode;
275 struct drm_display_mode *downclock_mode;
284 bool combination_mode; /* gen 2/4 only */
286 bool alternate_pwm_increment; /* lpt+ */
289 bool util_pin_active_low; /* bxt+ */
290 u8 controller; /* bxt+ only */
291 struct pwm_device *pwm;
293 struct backlight_device *device;
295 /* Connector and platform specific backlight functions */
296 int (*setup)(struct intel_connector *connector, enum pipe pipe);
297 uint32_t (*get)(struct intel_connector *connector);
298 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
299 void (*disable)(const struct drm_connector_state *conn_state);
300 void (*enable)(const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state);
302 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
304 void (*power)(struct intel_connector *, bool enable);
308 struct intel_digital_port;
311 * This structure serves as a translation layer between the generic HDCP code
312 * and the bus-specific code. What that means is that HDCP over HDMI differs
313 * from HDCP over DP, so to account for these differences, we need to
314 * communicate with the receiver through this shim.
316 * For completeness, the 2 buses differ in the following ways:
318 * HDCP registers on the receiver are set via DP AUX for DP, and
319 * they are set via DDC for HDMI.
320 * - Receiver register offsets
321 * The offsets of the registers are different for DP vs. HDMI
322 * - Receiver register masks/offsets
323 * For instance, the ready bit for the KSV fifo is in a different
324 * place on DP vs HDMI
325 * - Receiver register names
326 * Seriously. In the DP spec, the 16-bit register containing
327 * downstream information is called BINFO, on HDMI it's called
328 * BSTATUS. To confuse matters further, DP has a BSTATUS register
329 * with a completely different definition.
331 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
332 * be read 3 keys at a time
334 * Since Aksv is hidden in hardware, there's different procedures
335 * to send it over DP AUX vs DDC
337 struct intel_hdcp_shim {
338 /* Outputs the transmitter's An and Aksv values to the receiver. */
339 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
341 /* Reads the receiver's key selection vector */
342 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
345 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
346 * definitions are the same in the respective specs, but the names are
347 * different. Call it BSTATUS since that's the name the HDMI spec
348 * uses and it was there first.
350 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
353 /* Determines whether a repeater is present downstream */
354 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
355 bool *repeater_present);
357 /* Reads the receiver's Ri' value */
358 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
360 /* Determines if the receiver's KSV FIFO is ready for consumption */
361 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
364 /* Reads the ksv fifo for num_downstream devices */
365 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
366 int num_downstream, u8 *ksv_fifo);
368 /* Reads a 32-bit part of V' from the receiver */
369 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
372 /* Enables HDCP signalling on the port */
373 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
376 /* Ensures the link is still protected */
377 bool (*check_link)(struct intel_digital_port *intel_dig_port);
379 /* Detects panel's hdcp capability. This is optional for HDMI. */
380 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
385 const struct intel_hdcp_shim *shim;
386 /* Mutex for hdcp state of the connector */
389 struct delayed_work check_work;
390 struct work_struct prop_work;
393 struct intel_connector {
394 struct drm_connector base;
396 * The fixed encoder this connector is connected to.
398 struct intel_encoder *encoder;
400 /* ACPI device id for ACPI and driver cooperation */
403 /* Reads out the current hw, returning true if the connector is enabled
404 * and active (i.e. dpms ON state). */
405 bool (*get_hw_state)(struct intel_connector *);
407 /* Panel info for eDP and LVDS */
408 struct intel_panel panel;
410 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
412 struct edid *detect_edid;
414 /* since POLL and HPD connectors may use the same HPD line keep the native
415 state of connector->polled in case hotplug storm detection changes it */
418 void *port; /* store this opaque as its illegal to dereference it */
420 struct intel_dp *mst_port;
422 /* Work struct to schedule a uevent on link train failure */
423 struct work_struct modeset_retry_work;
425 struct intel_hdcp hdcp;
428 struct intel_digital_connector_state {
429 struct drm_connector_state base;
431 enum hdmi_force_audio force_audio;
435 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
449 struct intel_atomic_state {
450 struct drm_atomic_state base;
454 * Logical state of cdclk (used for all scaling, watermark,
455 * etc. calculations and checks). This is computed as if all
456 * enabled crtcs were active.
458 struct intel_cdclk_state logical;
461 * Actual state of cdclk, can be different from the logical
462 * state only when all crtc's are DPMS off.
464 struct intel_cdclk_state actual;
467 bool dpll_set, modeset;
470 * Does this transaction change the pipes that are active? This mask
471 * tracks which CRTC's have changed their active state at the end of
472 * the transaction (not counting the temporary disable during modesets).
473 * This mask should only be non-zero when intel_state->modeset is true,
474 * but the converse is not necessarily true; simply changing a mode may
475 * not flip the final active status of any CRTC's
477 unsigned int active_pipe_changes;
479 unsigned int active_crtcs;
480 /* minimum acceptable cdclk for each pipe */
481 int min_cdclk[I915_MAX_PIPES];
482 /* minimum acceptable voltage level for each pipe */
483 u8 min_voltage_level[I915_MAX_PIPES];
485 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
488 * Current watermarks can't be trusted during hardware readout, so
489 * don't bother calculating intermediate watermarks.
491 bool skip_intermediate_wm;
493 bool rps_interactive;
496 struct skl_ddb_values wm_results;
498 struct i915_sw_fence commit_ready;
500 struct llist_node freed;
503 struct intel_plane_state {
504 struct drm_plane_state base;
505 struct i915_ggtt_view view;
506 struct i915_vma *vma;
508 #define PLANE_HAS_FENCE BIT(0)
514 * bytes for 0/180 degree rotation
515 * pixels for 90/270 degree rotation
521 /* plane control register */
524 /* plane color control register */
529 * = -1 : not using a scaler
530 * >= 0 : using a scalers
532 * plane requiring a scaler:
533 * - During check_plane, its bit is set in
534 * crtc_state->scaler_state.scaler_users by calling helper function
535 * update_scaler_plane.
536 * - scaler_id indicates the scaler it got assigned.
538 * plane doesn't require a scaler:
539 * - this can happen when scaling is no more required or plane simply
541 * - During check_plane, corresponding bit is reset in
542 * crtc_state->scaler_state.scaler_users by calling helper function
543 * update_scaler_plane.
550 * ICL planar formats require 2 planes that are updated as pairs.
551 * This member is used to make sure the other plane is also updated
552 * when required, and for update_slave() to find the correct
553 * plane_state to pass as argument.
555 struct intel_plane *linked_plane;
559 * If set don't update use the linked plane's state for updating
560 * this plane during atomic commit with the update_slave() callback.
562 * It's also used by the watermark code to ignore wm calculations on
563 * this plane. They're calculated by the linked plane's wm code.
567 struct drm_intel_sprite_colorkey ckey;
570 struct intel_initial_plane_config {
571 struct intel_framebuffer *fb;
578 #define SKL_MIN_SRC_W 8
579 #define SKL_MAX_SRC_W 4096
580 #define SKL_MIN_SRC_H 8
581 #define SKL_MAX_SRC_H 4096
582 #define SKL_MIN_DST_W 8
583 #define SKL_MAX_DST_W 4096
584 #define SKL_MIN_DST_H 8
585 #define SKL_MAX_DST_H 4096
586 #define ICL_MAX_SRC_W 5120
587 #define ICL_MAX_SRC_H 4096
588 #define ICL_MAX_DST_W 5120
589 #define ICL_MAX_DST_H 4096
590 #define SKL_MIN_YUV_420_SRC_W 16
591 #define SKL_MIN_YUV_420_SRC_H 16
593 struct intel_scaler {
598 struct intel_crtc_scaler_state {
599 #define SKL_NUM_SCALERS 2
600 struct intel_scaler scalers[SKL_NUM_SCALERS];
603 * scaler_users: keeps track of users requesting scalers on this crtc.
605 * If a bit is set, a user is using a scaler.
606 * Here user can be a plane or crtc as defined below:
607 * bits 0-30 - plane (bit position is index from drm_plane_index)
610 * Instead of creating a new index to cover planes and crtc, using
611 * existing drm_plane_index for planes which is well less than 31
612 * planes and bit 31 for crtc. This should be fine to cover all
615 * intel_atomic_setup_scalers will setup available scalers to users
616 * requesting scalers. It will gracefully fail if request exceeds
619 #define SKL_CRTC_INDEX 31
620 unsigned scaler_users;
622 /* scaler used by crtc for panel fitting purpose */
626 /* drm_mode->private_flags */
627 #define I915_MODE_FLAG_INHERITED 1
628 /* Flag to get scanline using frame time stamps */
629 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
631 struct intel_pipe_wm {
632 struct intel_wm_level wm[5];
636 bool sprites_enabled;
640 struct skl_plane_wm {
641 struct skl_wm_level wm[8];
642 struct skl_wm_level uv_wm[8];
643 struct skl_wm_level trans_wm;
648 struct skl_plane_wm planes[I915_MAX_PLANES];
655 VLV_WM_LEVEL_DDR_DVFS,
659 struct vlv_wm_state {
660 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
661 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
666 struct vlv_fifo_state {
667 u16 plane[I915_MAX_PLANES];
677 struct g4x_wm_state {
678 struct g4x_pipe_wm wm;
680 struct g4x_sr_wm hpll;
686 struct intel_crtc_wm_state {
690 * Intermediate watermarks; these can be
691 * programmed immediately since they satisfy
692 * both the current configuration we're
693 * switching away from and the new
694 * configuration we're switching to.
696 struct intel_pipe_wm intermediate;
699 * Optimal watermarks, programmed post-vblank
700 * when this state is committed.
702 struct intel_pipe_wm optimal;
706 /* gen9+ only needs 1-step wm programming */
707 struct skl_pipe_wm optimal;
708 struct skl_ddb_entry ddb;
709 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
710 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
714 /* "raw" watermarks (not inverted) */
715 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
716 /* intermediate watermarks (inverted) */
717 struct vlv_wm_state intermediate;
718 /* optimal watermarks (inverted) */
719 struct vlv_wm_state optimal;
720 /* display FIFO split */
721 struct vlv_fifo_state fifo_state;
725 /* "raw" watermarks */
726 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
727 /* intermediate watermarks */
728 struct g4x_wm_state intermediate;
729 /* optimal watermarks */
730 struct g4x_wm_state optimal;
735 * Platforms with two-step watermark programming will need to
736 * update watermark programming post-vblank to switch from the
737 * safe intermediate watermarks to the optimal final
740 bool need_postvbl_update;
743 enum intel_output_format {
744 INTEL_OUTPUT_FORMAT_INVALID,
745 INTEL_OUTPUT_FORMAT_RGB,
746 INTEL_OUTPUT_FORMAT_YCBCR420,
747 INTEL_OUTPUT_FORMAT_YCBCR444,
750 struct intel_crtc_state {
751 struct drm_crtc_state base;
754 * quirks - bitfield with hw state readout quirks
756 * For various reasons the hw state readout code might not be able to
757 * completely faithfully read out the current state. These cases are
758 * tracked with quirk flags so that fastboot and state checker can act
761 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
762 unsigned long quirks;
764 unsigned fb_bits; /* framebuffers to flip */
765 bool update_pipe; /* can a fast modeset be performed? */
767 bool update_wm_pre, update_wm_post; /* watermarks are updated */
768 bool fb_changed; /* fb on any of the planes is changed */
769 bool fifo_changed; /* FIFO split is changed */
771 /* Pipe source size (ie. panel fitter input size)
772 * All planes will be positioned inside this space,
773 * and get clipped at the edges. */
774 int pipe_src_w, pipe_src_h;
777 * Pipe pixel rate, adjusted for
778 * panel fitter/pipe scaler downscaling.
780 unsigned int pixel_rate;
782 /* Whether to set up the PCH/FDI. Note that we never allow sharing
783 * between pch encoders and cpu encoders. */
784 bool has_pch_encoder;
786 /* Are we sending infoframes on the attached port */
789 /* CPU Transcoder for the pipe. Currently this can only differ from the
790 * pipe on Haswell and later (where we have a special eDP transcoder)
791 * and Broxton (where we have special DSI transcoders). */
792 enum transcoder cpu_transcoder;
795 * Use reduced/limited/broadcast rbg range, compressing from the full
796 * range fed into the crtcs.
798 bool limited_color_range;
800 /* Bitmask of encoder types (enum intel_output_type)
801 * driven by the pipe.
803 unsigned int output_types;
805 /* Whether we should send NULL infoframes. Required for audio. */
808 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
809 * has_dp_encoder is set. */
813 * Enable dithering, used when the selected pipe bpp doesn't match the
819 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
820 * compliance video pattern tests.
821 * Disable dither only if it is a compliance test request for
824 bool dither_force_disable;
826 /* Controls for the clock computation, to override various stages. */
829 /* SDVO TV has a bunch of special case. To make multifunction encoders
830 * work correctly, we need to track this at runtime.*/
834 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
835 * required. This is set in the 2nd loop of calling encoder's
836 * ->compute_config if the first pick doesn't work out.
840 /* Settings for the intel dpll used on pretty much everything but
844 /* Selected dpll when shared or NULL. */
845 struct intel_shared_dpll *shared_dpll;
847 /* Actual register state of the dpll, for shared dpll cross-checking. */
848 struct intel_dpll_hw_state dpll_hw_state;
850 /* DSI PLL registers */
856 struct intel_link_m_n dp_m_n;
858 /* m2_n2 for eDP downclock */
859 struct intel_link_m_n dp_m2_n2;
866 * Frequence the dpll for the port should run at. Differs from the
867 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
868 * already multiplied by pixel_multiplier.
872 /* Used by SDVO (and if we ever fix it, HDMI). */
873 unsigned pixel_multiplier;
878 * Used by platforms having DP/HDMI PHY with programmable lane
879 * latency optimization.
881 uint8_t lane_lat_optim_mask;
883 /* minimum acceptable voltage level */
884 u8 min_voltage_level;
886 /* Panel fitter controls for gen2-gen4 + VLV */
890 u32 lvds_border_bits;
893 /* Panel fitter placement and size for Ironlake+ */
901 /* FDI configuration, only valid if has_pch_encoder is set. */
903 struct intel_link_m_n fdi_m_n;
906 bool ips_force_disable;
914 struct intel_crtc_scaler_state scaler_state;
916 /* w/a for waiting 2 vblanks during crtc enable */
917 enum pipe hsw_workaround_pipe;
919 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
922 struct intel_crtc_wm_state wm;
924 /* Gamma mode programmed on the pipe */
927 /* bitmask of visible planes (enum plane_id) */
931 /* bitmask of planes that will be updated during the commit */
934 /* HDMI scrambling status */
935 bool hdmi_scrambling;
937 /* HDMI High TMDS char rate ratio */
938 bool hdmi_high_tmds_clock_ratio;
940 /* Output format RGB/YCBCR etc */
941 enum intel_output_format output_format;
943 /* Output down scaling is done in LSPCON device */
944 bool lspcon_downsampling;
946 /* Display Stream compression state */
948 bool compression_enable;
953 struct drm_dsc_config dp_dsc_cfg;
957 struct drm_crtc base;
960 * Whether the crtc and the connected output pipeline is active. Implies
961 * that crtc->enabled is set, i.e. the current mode configuration has
962 * some outputs connected to this crtc.
966 unsigned long long enabled_power_domains;
967 struct intel_overlay *overlay;
969 struct intel_crtc_state *config;
971 /* global reset count when the last flip was submitted */
972 unsigned int reset_count;
974 /* Access to these should be protected by dev_priv->irq_lock. */
975 bool cpu_fifo_underrun_disabled;
976 bool pch_fifo_underrun_disabled;
978 /* per-pipe watermark state */
980 /* watermarks currently being used */
982 struct intel_pipe_wm ilk;
983 struct vlv_wm_state vlv;
984 struct g4x_wm_state g4x;
991 unsigned start_vbl_count;
992 ktime_t start_vbl_time;
993 int min_vbl, max_vbl;
997 /* scalers available on this crtc */
1001 struct intel_plane {
1002 struct drm_plane base;
1003 enum i9xx_plane_id i9xx_plane;
1008 uint32_t frontbuffer_bit;
1011 u32 base, cntl, size;
1015 * NOTE: Do not place new plane state fields here (e.g., when adding
1016 * new plane properties). New runtime state should now be placed in
1017 * the intel_plane_state structure and accessed via plane_state.
1020 unsigned int (*max_stride)(struct intel_plane *plane,
1021 u32 pixel_format, u64 modifier,
1022 unsigned int rotation);
1023 void (*update_plane)(struct intel_plane *plane,
1024 const struct intel_crtc_state *crtc_state,
1025 const struct intel_plane_state *plane_state);
1026 void (*update_slave)(struct intel_plane *plane,
1027 const struct intel_crtc_state *crtc_state,
1028 const struct intel_plane_state *plane_state);
1029 void (*disable_plane)(struct intel_plane *plane,
1030 const struct intel_crtc_state *crtc_state);
1031 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1032 int (*check_plane)(struct intel_crtc_state *crtc_state,
1033 struct intel_plane_state *plane_state);
1036 struct intel_watermark_params {
1044 struct cxsr_latency {
1045 bool is_desktop : 1;
1050 u16 display_hpll_disable;
1052 u16 cursor_hpll_disable;
1055 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1056 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1057 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1058 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1059 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1060 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1061 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1062 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1063 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1066 i915_reg_t hdmi_reg;
1069 enum drm_dp_dual_mode_type type;
1074 bool rgb_quant_range_selectable;
1075 struct intel_connector *attached_connector;
1076 struct cec_notifier *cec_notifier;
1079 struct intel_dp_mst_encoder;
1080 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1083 * enum link_m_n_set:
1084 * When platform provides two set of M_N registers for dp, we can
1085 * program them and switch between them incase of DRRS.
1086 * But When only one such register is provided, we have to program the
1087 * required divider value on that registers itself based on the DRRS state.
1089 * M1_N1 : Program dp_m_n on M1_N1 registers
1090 * dp_m2_n2 on M2_N2 registers (If supported)
1092 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1093 * M2_N2 registers are not supported
1097 /* Sets the m1_n1 and m2_n2 */
1102 struct intel_dp_compliance_data {
1104 uint8_t video_pattern;
1105 uint16_t hdisplay, vdisplay;
1109 struct intel_dp_compliance {
1110 unsigned long test_type;
1111 struct intel_dp_compliance_data test_data;
1118 i915_reg_t output_reg;
1126 bool reset_link_params;
1127 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1128 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1129 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1130 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1131 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1134 int num_source_rates;
1135 const int *source_rates;
1136 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1138 int sink_rates[DP_MAX_SUPPORTED_RATES];
1139 bool use_rate_select;
1140 /* intersection of source and sink rates */
1141 int num_common_rates;
1142 int common_rates[DP_MAX_SUPPORTED_RATES];
1143 /* Max lane count for the current link */
1144 int max_link_lane_count;
1145 /* Max rate for the current link */
1147 /* sink or branch descriptor */
1148 struct drm_dp_desc desc;
1149 struct drm_dp_aux aux;
1150 uint8_t train_set[4];
1151 int panel_power_up_delay;
1152 int panel_power_down_delay;
1153 int panel_power_cycle_delay;
1154 int backlight_on_delay;
1155 int backlight_off_delay;
1156 struct delayed_work panel_vdd_work;
1157 bool want_panel_vdd;
1158 unsigned long last_power_on;
1159 unsigned long last_backlight_off;
1160 ktime_t panel_power_off_time;
1162 struct notifier_block edp_notifier;
1165 * Pipe whose power sequencer is currently locked into
1166 * this port. Only relevant on VLV/CHV.
1170 * Pipe currently driving the port. Used for preventing
1171 * the use of the PPS for any pipe currentrly driving
1172 * external DP as that will mess things up on VLV.
1174 enum pipe active_pipe;
1176 * Set if the sequencer may be reset due to a power transition,
1177 * requiring a reinitialization. Only relevant on BXT.
1180 struct edp_power_seq pps_delays;
1182 bool can_mst; /* this port supports mst */
1184 int active_mst_links;
1185 /* connector directly attached - won't be use for modeset in mst world */
1186 struct intel_connector *attached_connector;
1188 /* mst connector list */
1189 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1190 struct drm_dp_mst_topology_mgr mst_mgr;
1192 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1194 * This function returns the value we have to program the AUX_CTL
1195 * register with to kick off an AUX transaction.
1197 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1199 uint32_t aux_clock_divider);
1201 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1202 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1204 /* This is called before a link training is starterd */
1205 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1207 /* Displayport compliance testing */
1208 struct intel_dp_compliance compliance;
1211 enum lspcon_vendor {
1213 LSPCON_VENDOR_PARADE
1216 struct intel_lspcon {
1218 enum drm_lspcon_mode mode;
1219 enum lspcon_vendor vendor;
1222 struct intel_digital_port {
1223 struct intel_encoder base;
1224 u32 saved_port_bits;
1226 struct intel_hdmi hdmi;
1227 struct intel_lspcon lspcon;
1228 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1229 bool release_cl2_override;
1231 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1233 enum intel_display_power_domain ddi_io_power_domain;
1234 enum tc_port_type tc_type;
1236 void (*write_infoframe)(struct intel_encoder *encoder,
1237 const struct intel_crtc_state *crtc_state,
1239 const void *frame, ssize_t len);
1240 void (*set_infoframes)(struct intel_encoder *encoder,
1242 const struct intel_crtc_state *crtc_state,
1243 const struct drm_connector_state *conn_state);
1244 bool (*infoframe_enabled)(struct intel_encoder *encoder,
1245 const struct intel_crtc_state *pipe_config);
1248 struct intel_dp_mst_encoder {
1249 struct intel_encoder base;
1251 struct intel_digital_port *primary;
1252 struct intel_connector *connector;
1255 static inline enum dpio_channel
1256 vlv_dport_to_channel(struct intel_digital_port *dport)
1258 switch (dport->base.port) {
1269 static inline enum dpio_phy
1270 vlv_dport_to_phy(struct intel_digital_port *dport)
1272 switch (dport->base.port) {
1283 static inline enum dpio_channel
1284 vlv_pipe_to_channel(enum pipe pipe)
1297 static inline struct intel_crtc *
1298 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1300 return dev_priv->pipe_to_crtc_mapping[pipe];
1303 static inline struct intel_crtc *
1304 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1306 return dev_priv->plane_to_crtc_mapping[plane];
1309 struct intel_load_detect_pipe {
1310 struct drm_atomic_state *restore_state;
1313 static inline struct intel_encoder *
1314 intel_attached_encoder(struct drm_connector *connector)
1316 return to_intel_connector(connector)->encoder;
1319 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1321 switch (encoder->type) {
1322 case INTEL_OUTPUT_DDI:
1323 case INTEL_OUTPUT_DP:
1324 case INTEL_OUTPUT_EDP:
1325 case INTEL_OUTPUT_HDMI:
1332 static inline struct intel_digital_port *
1333 enc_to_dig_port(struct drm_encoder *encoder)
1335 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1337 if (intel_encoder_is_dig_port(intel_encoder))
1338 return container_of(encoder, struct intel_digital_port,
1344 static inline struct intel_digital_port *
1345 conn_to_dig_port(struct intel_connector *connector)
1347 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1350 static inline struct intel_dp_mst_encoder *
1351 enc_to_mst(struct drm_encoder *encoder)
1353 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1356 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1358 return &enc_to_dig_port(encoder)->dp;
1361 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1363 switch (encoder->type) {
1364 case INTEL_OUTPUT_DP:
1365 case INTEL_OUTPUT_EDP:
1367 case INTEL_OUTPUT_DDI:
1368 /* Skip pure HDMI/DVI DDI encoders */
1369 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1375 static inline struct intel_lspcon *
1376 enc_to_intel_lspcon(struct drm_encoder *encoder)
1378 return &enc_to_dig_port(encoder)->lspcon;
1381 static inline struct intel_digital_port *
1382 dp_to_dig_port(struct intel_dp *intel_dp)
1384 return container_of(intel_dp, struct intel_digital_port, dp);
1387 static inline struct intel_lspcon *
1388 dp_to_lspcon(struct intel_dp *intel_dp)
1390 return &dp_to_dig_port(intel_dp)->lspcon;
1393 static inline struct drm_i915_private *
1394 dp_to_i915(struct intel_dp *intel_dp)
1396 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1399 static inline struct intel_digital_port *
1400 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1402 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1405 static inline struct intel_plane_state *
1406 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1407 struct intel_plane *plane)
1409 struct drm_plane_state *ret =
1410 drm_atomic_get_plane_state(&state->base, &plane->base);
1413 return ERR_CAST(ret);
1415 return to_intel_plane_state(ret);
1418 static inline struct intel_plane_state *
1419 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1420 struct intel_plane *plane)
1422 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1426 static inline struct intel_plane_state *
1427 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1428 struct intel_plane *plane)
1430 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1434 static inline struct intel_crtc_state *
1435 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1436 struct intel_crtc *crtc)
1438 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1442 static inline struct intel_crtc_state *
1443 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1444 struct intel_crtc *crtc)
1446 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1450 /* intel_fifo_underrun.c */
1451 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, bool enable);
1453 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1454 enum pipe pch_transcoder,
1456 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1458 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1459 enum pipe pch_transcoder);
1460 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1461 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1464 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1465 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1466 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1467 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1468 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1469 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1470 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1471 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1473 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1476 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1479 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1480 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1481 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1484 * We only use drm_irq_uninstall() at unload and VT switch, so
1485 * this is the only thing we need to check.
1487 return dev_priv->runtime_pm.irqs_enabled;
1490 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1491 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1493 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1495 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1496 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1497 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1500 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1501 i915_reg_t adpa_reg, enum pipe *pipe);
1502 void intel_crt_init(struct drm_i915_private *dev_priv);
1503 void intel_crt_reset(struct drm_encoder *encoder);
1506 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1507 const struct intel_crtc_state *old_crtc_state,
1508 const struct drm_connector_state *old_conn_state);
1509 void hsw_fdi_link_train(struct intel_crtc *crtc,
1510 const struct intel_crtc_state *crtc_state);
1511 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1512 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1513 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1514 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1515 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1516 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1517 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1518 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1519 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1520 void intel_ddi_get_config(struct intel_encoder *encoder,
1521 struct intel_crtc_state *pipe_config);
1523 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1525 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1526 struct intel_crtc_state *crtc_state);
1527 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1528 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1529 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1530 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1532 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1534 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1535 struct intel_crtc_state *crtc_state,
1536 struct drm_atomic_state *old_state);
1537 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1538 struct intel_crtc_state *crtc_state,
1539 struct drm_atomic_state *old_state);
1540 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1542 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1543 int color_plane, unsigned int height);
1546 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1547 void intel_audio_codec_enable(struct intel_encoder *encoder,
1548 const struct intel_crtc_state *crtc_state,
1549 const struct drm_connector_state *conn_state);
1550 void intel_audio_codec_disable(struct intel_encoder *encoder,
1551 const struct intel_crtc_state *old_crtc_state,
1552 const struct drm_connector_state *old_conn_state);
1553 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1554 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1555 void intel_audio_init(struct drm_i915_private *dev_priv);
1556 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1559 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1560 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1561 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1562 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1563 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1564 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1565 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1566 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1567 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1568 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1569 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1570 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1571 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1572 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1573 const struct intel_cdclk_state *b);
1574 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1575 const struct intel_cdclk_state *b);
1576 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1577 const struct intel_cdclk_state *cdclk_state);
1578 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1579 const char *context);
1581 /* intel_display.c */
1582 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1583 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1584 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1585 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1586 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1587 const char *name, u32 reg, int ref_freq);
1588 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1589 const char *name, u32 reg);
1590 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1591 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1592 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1593 unsigned int intel_fb_xy_to_linear(int x, int y,
1594 const struct intel_plane_state *state,
1596 void intel_add_fb_offsets(int *x, int *y,
1597 const struct intel_plane_state *state, int plane);
1598 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1599 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1600 void intel_mark_busy(struct drm_i915_private *dev_priv);
1601 void intel_mark_idle(struct drm_i915_private *dev_priv);
1602 int intel_display_suspend(struct drm_device *dev);
1603 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1604 void intel_encoder_destroy(struct drm_encoder *encoder);
1605 struct drm_display_mode *
1606 intel_encoder_current_mode(struct intel_encoder *encoder);
1607 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1608 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1609 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1611 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1612 struct drm_file *file_priv);
1613 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1616 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1617 enum intel_output_type type)
1619 return crtc_state->output_types & (1 << type);
1622 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1624 return crtc_state->output_types &
1625 ((1 << INTEL_OUTPUT_DP) |
1626 (1 << INTEL_OUTPUT_DP_MST) |
1627 (1 << INTEL_OUTPUT_EDP));
1630 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1632 drm_wait_one_vblank(&dev_priv->drm, pipe);
1635 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1637 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1640 intel_wait_for_vblank(dev_priv, pipe);
1643 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1645 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1646 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1647 struct intel_digital_port *dport,
1648 unsigned int expected_mask);
1649 int intel_get_load_detect_pipe(struct drm_connector *connector,
1650 const struct drm_display_mode *mode,
1651 struct intel_load_detect_pipe *old,
1652 struct drm_modeset_acquire_ctx *ctx);
1653 void intel_release_load_detect_pipe(struct drm_connector *connector,
1654 struct intel_load_detect_pipe *old,
1655 struct drm_modeset_acquire_ctx *ctx);
1657 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1658 const struct i915_ggtt_view *view,
1660 unsigned long *out_flags);
1661 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1662 struct drm_framebuffer *
1663 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1664 struct drm_mode_fb_cmd2 *mode_cmd);
1665 int intel_prepare_plane_fb(struct drm_plane *plane,
1666 struct drm_plane_state *new_state);
1667 void intel_cleanup_plane_fb(struct drm_plane *plane,
1668 struct drm_plane_state *old_state);
1669 int intel_plane_atomic_get_property(struct drm_plane *plane,
1670 const struct drm_plane_state *state,
1671 struct drm_property *property,
1673 int intel_plane_atomic_set_property(struct drm_plane *plane,
1674 struct drm_plane_state *state,
1675 struct drm_property *property,
1677 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1678 struct drm_crtc_state *crtc_state,
1679 const struct intel_plane_state *old_plane_state,
1680 struct drm_plane_state *plane_state);
1682 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1685 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1686 const struct dpll *dpll);
1687 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1688 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1690 /* modesetting asserts */
1691 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1693 void assert_pll(struct drm_i915_private *dev_priv,
1694 enum pipe pipe, bool state);
1695 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1696 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1697 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1698 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1699 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1700 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1701 enum pipe pipe, bool state);
1702 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1703 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1704 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1705 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1706 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1707 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1708 void intel_finish_reset(struct drm_i915_private *dev_priv);
1709 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1710 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1711 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1712 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1713 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1714 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1715 unsigned int skl_cdclk_get_vco(unsigned int freq);
1716 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1717 void intel_dp_get_m_n(struct intel_crtc *crtc,
1718 struct intel_crtc_state *pipe_config);
1719 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1720 enum link_m_n_set m_n);
1721 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1722 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1723 struct dpll *best_clock);
1724 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1726 bool intel_crtc_active(struct intel_crtc *crtc);
1727 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1728 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1729 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1730 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1731 enum intel_display_power_domain
1732 intel_aux_power_domain(struct intel_digital_port *dig_port);
1733 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1734 struct intel_crtc_state *pipe_config);
1735 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1736 struct intel_crtc_state *crtc_state);
1738 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1739 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1740 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1743 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1745 return i915_ggtt_offset(state->vma);
1748 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1749 const struct intel_plane_state *plane_state);
1750 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1751 const struct intel_plane_state *plane_state);
1752 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1753 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1755 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1756 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1757 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1758 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1759 u32 pixel_format, u64 modifier,
1760 unsigned int rotation);
1762 /* intel_connector.c */
1763 int intel_connector_init(struct intel_connector *connector);
1764 struct intel_connector *intel_connector_alloc(void);
1765 void intel_connector_free(struct intel_connector *connector);
1766 void intel_connector_destroy(struct drm_connector *connector);
1767 int intel_connector_register(struct drm_connector *connector);
1768 void intel_connector_unregister(struct drm_connector *connector);
1769 void intel_connector_attach_encoder(struct intel_connector *connector,
1770 struct intel_encoder *encoder);
1771 bool intel_connector_get_hw_state(struct intel_connector *connector);
1772 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1773 int intel_connector_update_modes(struct drm_connector *connector,
1775 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1776 void intel_attach_force_audio_property(struct drm_connector *connector);
1777 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1778 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1781 void intel_csr_ucode_init(struct drm_i915_private *);
1782 void intel_csr_load_program(struct drm_i915_private *);
1783 void intel_csr_ucode_fini(struct drm_i915_private *);
1784 void intel_csr_ucode_suspend(struct drm_i915_private *);
1785 void intel_csr_ucode_resume(struct drm_i915_private *);
1788 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1789 i915_reg_t dp_reg, enum port port,
1791 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1793 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1794 struct intel_connector *intel_connector);
1795 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1796 int link_rate, uint8_t lane_count,
1798 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1799 int link_rate, uint8_t lane_count);
1800 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1801 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1802 int intel_dp_retrain_link(struct intel_encoder *encoder,
1803 struct drm_modeset_acquire_ctx *ctx);
1804 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1805 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1806 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1807 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1808 bool intel_dp_compute_config(struct intel_encoder *encoder,
1809 struct intel_crtc_state *pipe_config,
1810 struct drm_connector_state *conn_state);
1811 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1812 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1813 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1815 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1816 const struct drm_connector_state *conn_state);
1817 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1818 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1819 void intel_edp_panel_on(struct intel_dp *intel_dp);
1820 void intel_edp_panel_off(struct intel_dp *intel_dp);
1821 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1822 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1823 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1824 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1825 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1826 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1827 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1828 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1829 void intel_plane_destroy(struct drm_plane *plane);
1830 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1831 const struct intel_crtc_state *crtc_state);
1832 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1833 const struct intel_crtc_state *crtc_state);
1834 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1835 unsigned int frontbuffer_bits);
1836 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1837 unsigned int frontbuffer_bits);
1840 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1841 uint8_t dp_train_pat);
1843 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1844 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1846 intel_dp_voltage_max(struct intel_dp *intel_dp);
1848 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1849 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1850 uint8_t *link_bw, uint8_t *rate_select);
1851 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1852 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1854 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1855 uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
1856 int mode_clock, int mode_hdisplay);
1857 uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1861 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1862 struct intel_crtc_state *pipe_config);
1864 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1866 return ~((1 << lane_count) - 1) & 0xf;
1869 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1870 int intel_dp_link_required(int pixel_clock, int bpp);
1871 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1872 bool intel_digital_port_connected(struct intel_encoder *encoder);
1874 /* intel_dp_aux_backlight.c */
1875 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1877 /* intel_dp_mst.c */
1878 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1879 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1881 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1884 void icl_dsi_init(struct drm_i915_private *dev_priv);
1886 /* intel_dsi_dcs_backlight.c */
1887 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1890 void intel_dvo_init(struct drm_i915_private *dev_priv);
1891 /* intel_hotplug.c */
1892 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1893 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1894 struct intel_connector *connector);
1896 /* legacy fbdev emulation in intel_fbdev.c */
1897 #ifdef CONFIG_DRM_FBDEV_EMULATION
1898 extern int intel_fbdev_init(struct drm_device *dev);
1899 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1900 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1901 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1902 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1903 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1904 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1906 static inline int intel_fbdev_init(struct drm_device *dev)
1911 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1915 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1919 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1923 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1927 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1931 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1937 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1938 struct intel_atomic_state *state);
1939 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1940 void intel_fbc_pre_update(struct intel_crtc *crtc,
1941 struct intel_crtc_state *crtc_state,
1942 struct intel_plane_state *plane_state);
1943 void intel_fbc_post_update(struct intel_crtc *crtc);
1944 void intel_fbc_init(struct drm_i915_private *dev_priv);
1945 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1946 void intel_fbc_enable(struct intel_crtc *crtc,
1947 struct intel_crtc_state *crtc_state,
1948 struct intel_plane_state *plane_state);
1949 void intel_fbc_disable(struct intel_crtc *crtc);
1950 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1951 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1952 unsigned int frontbuffer_bits,
1953 enum fb_op_origin origin);
1954 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1955 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1956 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1957 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1958 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1961 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1963 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1964 struct intel_connector *intel_connector);
1965 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1966 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1967 struct intel_crtc_state *pipe_config,
1968 struct drm_connector_state *conn_state);
1969 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1970 struct drm_connector *connector,
1971 bool high_tmds_clock_ratio,
1973 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1974 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1977 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1978 i915_reg_t lvds_reg, enum pipe *pipe);
1979 void intel_lvds_init(struct drm_i915_private *dev_priv);
1980 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1981 bool intel_is_dual_link_lvds(struct drm_device *dev);
1983 /* intel_overlay.c */
1984 void intel_overlay_setup(struct drm_i915_private *dev_priv);
1985 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
1986 int intel_overlay_switch_off(struct intel_overlay *overlay);
1987 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1988 struct drm_file *file_priv);
1989 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1990 struct drm_file *file_priv);
1991 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1995 int intel_panel_init(struct intel_panel *panel,
1996 struct drm_display_mode *fixed_mode,
1997 struct drm_display_mode *downclock_mode);
1998 void intel_panel_fini(struct intel_panel *panel);
1999 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2000 struct drm_display_mode *adjusted_mode);
2001 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2002 struct intel_crtc_state *pipe_config,
2004 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2005 struct intel_crtc_state *pipe_config,
2007 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2008 u32 level, u32 max);
2009 int intel_panel_setup_backlight(struct drm_connector *connector,
2011 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2012 const struct drm_connector_state *conn_state);
2013 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2014 extern struct drm_display_mode *intel_find_panel_downclock(
2015 struct drm_i915_private *dev_priv,
2016 struct drm_display_mode *fixed_mode,
2017 struct drm_connector *connector);
2019 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2020 int intel_backlight_device_register(struct intel_connector *connector);
2021 void intel_backlight_device_unregister(struct intel_connector *connector);
2022 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2023 static inline int intel_backlight_device_register(struct intel_connector *connector)
2027 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2030 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2033 void intel_hdcp_atomic_check(struct drm_connector *connector,
2034 struct drm_connector_state *old_state,
2035 struct drm_connector_state *new_state);
2036 int intel_hdcp_init(struct intel_connector *connector,
2037 const struct intel_hdcp_shim *hdcp_shim);
2038 int intel_hdcp_enable(struct intel_connector *connector);
2039 int intel_hdcp_disable(struct intel_connector *connector);
2040 int intel_hdcp_check_link(struct intel_connector *connector);
2041 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2042 bool intel_hdcp_capable(struct intel_connector *connector);
2045 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2046 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2047 void intel_psr_enable(struct intel_dp *intel_dp,
2048 const struct intel_crtc_state *crtc_state);
2049 void intel_psr_disable(struct intel_dp *intel_dp,
2050 const struct intel_crtc_state *old_crtc_state);
2051 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
2052 struct drm_modeset_acquire_ctx *ctx,
2054 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2055 unsigned frontbuffer_bits,
2056 enum fb_op_origin origin);
2057 void intel_psr_flush(struct drm_i915_private *dev_priv,
2058 unsigned frontbuffer_bits,
2059 enum fb_op_origin origin);
2060 void intel_psr_init(struct drm_i915_private *dev_priv);
2061 void intel_psr_compute_config(struct intel_dp *intel_dp,
2062 struct intel_crtc_state *crtc_state);
2063 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2064 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2065 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2066 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2068 bool intel_psr_enabled(struct intel_dp *intel_dp);
2070 /* intel_quirks.c */
2071 void intel_init_quirks(struct drm_i915_private *dev_priv);
2073 /* intel_runtime_pm.c */
2074 int intel_power_domains_init(struct drm_i915_private *);
2075 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2076 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2077 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2078 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2079 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2080 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2081 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2083 enum i915_drm_suspend_mode {
2084 I915_DRM_SUSPEND_IDLE,
2085 I915_DRM_SUSPEND_MEM,
2086 I915_DRM_SUSPEND_HIBERNATE,
2089 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2090 enum i915_drm_suspend_mode);
2091 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2092 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2093 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2094 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2095 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2097 intel_display_power_domain_str(enum intel_display_power_domain domain);
2099 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2100 enum intel_display_power_domain domain);
2101 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2102 enum intel_display_power_domain domain);
2103 void intel_display_power_get(struct drm_i915_private *dev_priv,
2104 enum intel_display_power_domain domain);
2105 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2106 enum intel_display_power_domain domain);
2107 void intel_display_power_put(struct drm_i915_private *dev_priv,
2108 enum intel_display_power_domain domain);
2109 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2113 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2115 WARN_ONCE(dev_priv->runtime_pm.suspended,
2116 "Device suspended during HW access\n");
2120 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2122 assert_rpm_device_not_suspended(dev_priv);
2123 WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2124 "RPM wakelock ref not held during HW access");
2128 * disable_rpm_wakeref_asserts - disable the RPM assert checks
2129 * @dev_priv: i915 device instance
2131 * This function disable asserts that check if we hold an RPM wakelock
2132 * reference, while keeping the device-not-suspended checks still enabled.
2133 * It's meant to be used only in special circumstances where our rule about
2134 * the wakelock refcount wrt. the device power state doesn't hold. According
2135 * to this rule at any point where we access the HW or want to keep the HW in
2136 * an active state we must hold an RPM wakelock reference acquired via one of
2137 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2138 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2139 * forcewake release timer, and the GPU RPS and hangcheck works. All other
2140 * users should avoid using this function.
2142 * Any calls to this function must have a symmetric call to
2143 * enable_rpm_wakeref_asserts().
2146 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2148 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2152 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2153 * @dev_priv: i915 device instance
2155 * This function re-enables the RPM assert checks after disabling them with
2156 * disable_rpm_wakeref_asserts. It's meant to be used only in special
2157 * circumstances otherwise its use should be avoided.
2159 * Any calls to this function must have a symmetric call to
2160 * disable_rpm_wakeref_asserts().
2163 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2165 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2168 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2169 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2170 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2171 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2173 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2174 bool override, unsigned int mask);
2175 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2176 enum dpio_channel ch, bool override);
2180 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2181 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2182 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2183 void intel_update_watermarks(struct intel_crtc *crtc);
2184 void intel_init_pm(struct drm_i915_private *dev_priv);
2185 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2186 void intel_pm_setup(struct drm_i915_private *dev_priv);
2187 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2188 void intel_gpu_ips_teardown(void);
2189 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2190 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2191 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2192 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2193 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2194 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2195 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2196 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2197 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2198 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2199 void g4x_wm_get_hw_state(struct drm_device *dev);
2200 void vlv_wm_get_hw_state(struct drm_device *dev);
2201 void ilk_wm_get_hw_state(struct drm_device *dev);
2202 void skl_wm_get_hw_state(struct drm_device *dev);
2203 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2204 struct skl_ddb_entry *ddb_y,
2205 struct skl_ddb_entry *ddb_uv);
2206 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2207 struct skl_ddb_allocation *ddb /* out */);
2208 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2209 struct skl_pipe_wm *out);
2210 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2211 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2212 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2213 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2214 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2215 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2216 const struct skl_wm_level *l2);
2217 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2218 const struct skl_ddb_entry entries[],
2219 int num_entries, int ignore_idx);
2220 void skl_write_plane_wm(struct intel_plane *plane,
2221 const struct intel_crtc_state *crtc_state);
2222 void skl_write_cursor_wm(struct intel_plane *plane,
2223 const struct intel_crtc_state *crtc_state);
2224 bool ilk_disable_lp_wm(struct drm_device *dev);
2225 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2226 struct intel_crtc_state *cstate);
2227 void intel_init_ipc(struct drm_i915_private *dev_priv);
2228 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2231 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2232 i915_reg_t sdvo_reg, enum pipe *pipe);
2233 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2234 i915_reg_t reg, enum port port);
2237 /* intel_sprite.c */
2238 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2240 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2241 enum pipe pipe, int plane);
2242 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2243 struct drm_file *file_priv);
2244 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2245 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2246 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2247 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2248 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2249 struct intel_plane *
2250 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2251 enum pipe pipe, enum plane_id plane_id);
2253 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2255 /* Don't need to do a gen check, these planes are only available on gen11 */
2256 if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2262 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2264 if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2267 return plane->id < PLANE_SPRITE2;
2271 void intel_tv_init(struct drm_i915_private *dev_priv);
2273 /* intel_atomic.c */
2274 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2275 const struct drm_connector_state *state,
2276 struct drm_property *property,
2278 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2279 struct drm_connector_state *state,
2280 struct drm_property *property,
2282 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2283 struct drm_connector_state *new_state);
2284 struct drm_connector_state *
2285 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2287 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2288 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2289 struct drm_crtc_state *state);
2290 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2291 void intel_atomic_state_clear(struct drm_atomic_state *);
2293 static inline struct intel_crtc_state *
2294 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2295 struct intel_crtc *crtc)
2297 struct drm_crtc_state *crtc_state;
2298 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2299 if (IS_ERR(crtc_state))
2300 return ERR_CAST(crtc_state);
2302 return to_intel_crtc_state(crtc_state);
2305 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2306 struct intel_crtc *intel_crtc,
2307 struct intel_crtc_state *crtc_state);
2309 /* intel_atomic_plane.c */
2310 struct intel_plane *intel_plane_alloc(void);
2311 void intel_plane_free(struct intel_plane *plane);
2312 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2313 void intel_plane_destroy_state(struct drm_plane *plane,
2314 struct drm_plane_state *state);
2315 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2316 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2317 struct intel_crtc *crtc);
2318 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2319 struct intel_crtc *crtc);
2320 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2321 struct intel_crtc_state *crtc_state,
2322 const struct intel_plane_state *old_plane_state,
2323 struct intel_plane_state *intel_state);
2326 void intel_color_init(struct drm_crtc *crtc);
2327 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2328 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2329 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2331 /* intel_lspcon.c */
2332 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2333 void lspcon_resume(struct intel_lspcon *lspcon);
2334 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2335 void lspcon_write_infoframe(struct intel_encoder *encoder,
2336 const struct intel_crtc_state *crtc_state,
2338 const void *buf, ssize_t len);
2339 void lspcon_set_infoframes(struct intel_encoder *encoder,
2341 const struct intel_crtc_state *crtc_state,
2342 const struct drm_connector_state *conn_state);
2343 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2344 const struct intel_crtc_state *pipe_config);
2345 void lspcon_ycbcr420_config(struct drm_connector *connector,
2346 struct intel_crtc_state *crtc_state);
2348 /* intel_pipe_crc.c */
2349 #ifdef CONFIG_DEBUG_FS
2350 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2351 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2352 const char *source_name, size_t *values_cnt);
2353 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2355 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2356 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2358 #define intel_crtc_set_crc_source NULL
2359 #define intel_crtc_verify_crc_source NULL
2360 #define intel_crtc_get_crc_sources NULL
2361 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2365 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2369 #endif /* __INTEL_DRV_H__ */