2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
42 #include <media/cec-notifier.h>
45 * __wait_for - magic wait macro
47 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
48 * important that we check the condition again after having timed out, since the
49 * timeout could be due to preemption or similar and we've never had a chance to
50 * check the condition before the timeout.
52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
53 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
54 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
58 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
60 /* Guarantee COND check prior to timeout */ \
70 usleep_range(wait__, wait__ * 2); \
71 if (wait__ < (Wmax)) \
77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
79 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
88 #define _wait_for_atomic(COND, US, ATOMIC) \
90 int cpu, ret, timeout = (US) * 1000; \
92 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
95 cpu = smp_processor_id(); \
97 base = local_clock(); \
99 u64 now = local_clock(); \
102 /* Guarantee COND check prior to timeout */ \
108 if (now - base >= timeout) { \
115 if (unlikely(cpu != smp_processor_id())) { \
116 timeout -= now - base; \
117 cpu = smp_processor_id(); \
118 base = local_clock(); \
125 #define wait_for_us(COND, US) \
128 BUILD_BUG_ON(!__builtin_constant_p(US)); \
130 ret__ = _wait_for((COND), (US), 10, 10); \
132 ret__ = _wait_for_atomic((COND), (US), 0); \
136 #define wait_for_atomic_us(COND, US) \
138 BUILD_BUG_ON(!__builtin_constant_p(US)); \
139 BUILD_BUG_ON((US) > 50000); \
140 _wait_for_atomic((COND), (US), 1); \
143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
145 #define KHz(x) (1000 * (x))
146 #define MHz(x) KHz(1000 * (x))
148 #define KBps(x) (1000 * (x))
149 #define MBps(x) KBps(1000 * (x))
150 #define GBps(x) ((u64)1000 * MBps((x)))
153 * Display related stuff
156 /* store information about an Ixxx DVO */
157 /* The i830->i865 use multiple DVOs with multiple i2cs */
158 /* the i915, i945 have a single sDVO i2c bus - which is different */
159 #define MAX_OUTPUTS 6
160 /* maximum connectors per crtcs in the mode set */
162 #define INTEL_I2C_BUS_DVO 1
163 #define INTEL_I2C_BUS_SDVO 2
165 /* these are outputs from the chip - integrated only
166 external chips are via DVO or SDVO output */
167 enum intel_output_type {
168 INTEL_OUTPUT_UNUSED = 0,
169 INTEL_OUTPUT_ANALOG = 1,
170 INTEL_OUTPUT_DVO = 2,
171 INTEL_OUTPUT_SDVO = 3,
172 INTEL_OUTPUT_LVDS = 4,
173 INTEL_OUTPUT_TVOUT = 5,
174 INTEL_OUTPUT_HDMI = 6,
176 INTEL_OUTPUT_EDP = 8,
177 INTEL_OUTPUT_DSI = 9,
178 INTEL_OUTPUT_DDI = 10,
179 INTEL_OUTPUT_DP_MST = 11,
182 #define INTEL_DVO_CHIP_NONE 0
183 #define INTEL_DVO_CHIP_LVDS 1
184 #define INTEL_DVO_CHIP_TMDS 2
185 #define INTEL_DVO_CHIP_TVOUT 4
187 #define INTEL_DSI_VIDEO_MODE 0
188 #define INTEL_DSI_COMMAND_MODE 1
190 struct intel_framebuffer {
191 struct drm_framebuffer base;
192 struct intel_rotation_info rot_info;
194 /* for each plane in the normal GTT view */
198 /* for each plane in the rotated GTT view */
201 unsigned int pitch; /* pixels */
206 struct drm_fb_helper helper;
207 struct intel_framebuffer *fb;
208 struct i915_vma *vma;
209 unsigned long vma_flags;
210 async_cookie_t cookie;
214 struct intel_encoder {
215 struct drm_encoder base;
217 enum intel_output_type type;
219 unsigned int cloneable;
220 bool (*hotplug)(struct intel_encoder *encoder,
221 struct intel_connector *connector);
222 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
223 struct intel_crtc_state *,
224 struct drm_connector_state *);
225 bool (*compute_config)(struct intel_encoder *,
226 struct intel_crtc_state *,
227 struct drm_connector_state *);
228 void (*pre_pll_enable)(struct intel_encoder *,
229 const struct intel_crtc_state *,
230 const struct drm_connector_state *);
231 void (*pre_enable)(struct intel_encoder *,
232 const struct intel_crtc_state *,
233 const struct drm_connector_state *);
234 void (*enable)(struct intel_encoder *,
235 const struct intel_crtc_state *,
236 const struct drm_connector_state *);
237 void (*disable)(struct intel_encoder *,
238 const struct intel_crtc_state *,
239 const struct drm_connector_state *);
240 void (*post_disable)(struct intel_encoder *,
241 const struct intel_crtc_state *,
242 const struct drm_connector_state *);
243 void (*post_pll_disable)(struct intel_encoder *,
244 const struct intel_crtc_state *,
245 const struct drm_connector_state *);
246 /* Read out the current hw state of this connector, returning true if
247 * the encoder is active. If the encoder is enabled it also set the pipe
248 * it is connected to in the pipe parameter. */
249 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
250 /* Reconstructs the equivalent mode flags for the current hardware
251 * state. This must be called _after_ display->get_pipe_config has
252 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
253 * be set correctly before calling this function. */
254 void (*get_config)(struct intel_encoder *,
255 struct intel_crtc_state *pipe_config);
256 /* Returns a mask of power domains that need to be referenced as part
257 * of the hardware state readout code. */
258 u64 (*get_power_domains)(struct intel_encoder *encoder,
259 struct intel_crtc_state *crtc_state);
261 * Called during system suspend after all pending requests for the
262 * encoder are flushed (for example for DP AUX transactions) and
263 * device interrupts are disabled.
265 void (*suspend)(struct intel_encoder *);
267 enum hpd_pin hpd_pin;
268 enum intel_display_power_domain power_domain;
269 /* for communication with audio component; protected by av_mutex */
270 const struct drm_connector *audio_connector;
274 struct drm_display_mode *fixed_mode;
275 struct drm_display_mode *downclock_mode;
284 bool combination_mode; /* gen 2/4 only */
286 bool alternate_pwm_increment; /* lpt+ */
289 bool util_pin_active_low; /* bxt+ */
290 u8 controller; /* bxt+ only */
291 struct pwm_device *pwm;
293 struct backlight_device *device;
295 /* Connector and platform specific backlight functions */
296 int (*setup)(struct intel_connector *connector, enum pipe pipe);
297 uint32_t (*get)(struct intel_connector *connector);
298 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
299 void (*disable)(const struct drm_connector_state *conn_state);
300 void (*enable)(const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state);
302 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
304 void (*power)(struct intel_connector *, bool enable);
308 struct intel_digital_port;
311 * This structure serves as a translation layer between the generic HDCP code
312 * and the bus-specific code. What that means is that HDCP over HDMI differs
313 * from HDCP over DP, so to account for these differences, we need to
314 * communicate with the receiver through this shim.
316 * For completeness, the 2 buses differ in the following ways:
318 * HDCP registers on the receiver are set via DP AUX for DP, and
319 * they are set via DDC for HDMI.
320 * - Receiver register offsets
321 * The offsets of the registers are different for DP vs. HDMI
322 * - Receiver register masks/offsets
323 * For instance, the ready bit for the KSV fifo is in a different
324 * place on DP vs HDMI
325 * - Receiver register names
326 * Seriously. In the DP spec, the 16-bit register containing
327 * downstream information is called BINFO, on HDMI it's called
328 * BSTATUS. To confuse matters further, DP has a BSTATUS register
329 * with a completely different definition.
331 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
332 * be read 3 keys at a time
334 * Since Aksv is hidden in hardware, there's different procedures
335 * to send it over DP AUX vs DDC
337 struct intel_hdcp_shim {
338 /* Outputs the transmitter's An and Aksv values to the receiver. */
339 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
341 /* Reads the receiver's key selection vector */
342 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
345 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
346 * definitions are the same in the respective specs, but the names are
347 * different. Call it BSTATUS since that's the name the HDMI spec
348 * uses and it was there first.
350 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
353 /* Determines whether a repeater is present downstream */
354 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
355 bool *repeater_present);
357 /* Reads the receiver's Ri' value */
358 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
360 /* Determines if the receiver's KSV FIFO is ready for consumption */
361 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
364 /* Reads the ksv fifo for num_downstream devices */
365 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
366 int num_downstream, u8 *ksv_fifo);
368 /* Reads a 32-bit part of V' from the receiver */
369 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
372 /* Enables HDCP signalling on the port */
373 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
376 /* Ensures the link is still protected */
377 bool (*check_link)(struct intel_digital_port *intel_dig_port);
379 /* Detects panel's hdcp capability. This is optional for HDMI. */
380 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
384 struct intel_connector {
385 struct drm_connector base;
387 * The fixed encoder this connector is connected to.
389 struct intel_encoder *encoder;
391 /* ACPI device id for ACPI and driver cooperation */
394 /* Reads out the current hw, returning true if the connector is enabled
395 * and active (i.e. dpms ON state). */
396 bool (*get_hw_state)(struct intel_connector *);
398 /* Panel info for eDP and LVDS */
399 struct intel_panel panel;
401 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
403 struct edid *detect_edid;
405 /* since POLL and HPD connectors may use the same HPD line keep the native
406 state of connector->polled in case hotplug storm detection changes it */
409 void *port; /* store this opaque as its illegal to dereference it */
411 struct intel_dp *mst_port;
413 /* Work struct to schedule a uevent on link train failure */
414 struct work_struct modeset_retry_work;
416 const struct intel_hdcp_shim *hdcp_shim;
417 struct mutex hdcp_mutex;
418 uint64_t hdcp_value; /* protected by hdcp_mutex */
419 struct delayed_work hdcp_check_work;
420 struct work_struct hdcp_prop_work;
423 struct intel_digital_connector_state {
424 struct drm_connector_state base;
426 enum hdmi_force_audio force_audio;
430 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
444 struct intel_atomic_state {
445 struct drm_atomic_state base;
449 * Logical state of cdclk (used for all scaling, watermark,
450 * etc. calculations and checks). This is computed as if all
451 * enabled crtcs were active.
453 struct intel_cdclk_state logical;
456 * Actual state of cdclk, can be different from the logical
457 * state only when all crtc's are DPMS off.
459 struct intel_cdclk_state actual;
462 bool dpll_set, modeset;
465 * Does this transaction change the pipes that are active? This mask
466 * tracks which CRTC's have changed their active state at the end of
467 * the transaction (not counting the temporary disable during modesets).
468 * This mask should only be non-zero when intel_state->modeset is true,
469 * but the converse is not necessarily true; simply changing a mode may
470 * not flip the final active status of any CRTC's
472 unsigned int active_pipe_changes;
474 unsigned int active_crtcs;
475 /* minimum acceptable cdclk for each pipe */
476 int min_cdclk[I915_MAX_PIPES];
477 /* minimum acceptable voltage level for each pipe */
478 u8 min_voltage_level[I915_MAX_PIPES];
480 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
483 * Current watermarks can't be trusted during hardware readout, so
484 * don't bother calculating intermediate watermarks.
486 bool skip_intermediate_wm;
488 bool rps_interactive;
491 struct skl_ddb_values wm_results;
493 struct i915_sw_fence commit_ready;
495 struct llist_node freed;
498 struct intel_plane_state {
499 struct drm_plane_state base;
500 struct i915_ggtt_view view;
501 struct i915_vma *vma;
503 #define PLANE_HAS_FENCE BIT(0)
509 * bytes for 0/180 degree rotation
510 * pixels for 90/270 degree rotation
516 /* plane control register */
519 /* plane color control register */
524 * = -1 : not using a scaler
525 * >= 0 : using a scalers
527 * plane requiring a scaler:
528 * - During check_plane, its bit is set in
529 * crtc_state->scaler_state.scaler_users by calling helper function
530 * update_scaler_plane.
531 * - scaler_id indicates the scaler it got assigned.
533 * plane doesn't require a scaler:
534 * - this can happen when scaling is no more required or plane simply
536 * - During check_plane, corresponding bit is reset in
537 * crtc_state->scaler_state.scaler_users by calling helper function
538 * update_scaler_plane.
542 struct drm_intel_sprite_colorkey ckey;
545 struct intel_initial_plane_config {
546 struct intel_framebuffer *fb;
552 #define SKL_MIN_SRC_W 8
553 #define SKL_MAX_SRC_W 4096
554 #define SKL_MIN_SRC_H 8
555 #define SKL_MAX_SRC_H 4096
556 #define SKL_MIN_DST_W 8
557 #define SKL_MAX_DST_W 4096
558 #define SKL_MIN_DST_H 8
559 #define SKL_MAX_DST_H 4096
560 #define ICL_MAX_SRC_W 5120
561 #define ICL_MAX_SRC_H 4096
562 #define ICL_MAX_DST_W 5120
563 #define ICL_MAX_DST_H 4096
564 #define SKL_MIN_YUV_420_SRC_W 16
565 #define SKL_MIN_YUV_420_SRC_H 16
567 struct intel_scaler {
572 struct intel_crtc_scaler_state {
573 #define SKL_NUM_SCALERS 2
574 struct intel_scaler scalers[SKL_NUM_SCALERS];
577 * scaler_users: keeps track of users requesting scalers on this crtc.
579 * If a bit is set, a user is using a scaler.
580 * Here user can be a plane or crtc as defined below:
581 * bits 0-30 - plane (bit position is index from drm_plane_index)
584 * Instead of creating a new index to cover planes and crtc, using
585 * existing drm_plane_index for planes which is well less than 31
586 * planes and bit 31 for crtc. This should be fine to cover all
589 * intel_atomic_setup_scalers will setup available scalers to users
590 * requesting scalers. It will gracefully fail if request exceeds
593 #define SKL_CRTC_INDEX 31
594 unsigned scaler_users;
596 /* scaler used by crtc for panel fitting purpose */
600 /* drm_mode->private_flags */
601 #define I915_MODE_FLAG_INHERITED 1
602 /* Flag to get scanline using frame time stamps */
603 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
605 struct intel_pipe_wm {
606 struct intel_wm_level wm[5];
610 bool sprites_enabled;
614 struct skl_plane_wm {
615 struct skl_wm_level wm[8];
616 struct skl_wm_level uv_wm[8];
617 struct skl_wm_level trans_wm;
622 struct skl_plane_wm planes[I915_MAX_PLANES];
629 VLV_WM_LEVEL_DDR_DVFS,
633 struct vlv_wm_state {
634 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
635 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
640 struct vlv_fifo_state {
641 u16 plane[I915_MAX_PLANES];
651 struct g4x_wm_state {
652 struct g4x_pipe_wm wm;
654 struct g4x_sr_wm hpll;
660 struct intel_crtc_wm_state {
664 * Intermediate watermarks; these can be
665 * programmed immediately since they satisfy
666 * both the current configuration we're
667 * switching away from and the new
668 * configuration we're switching to.
670 struct intel_pipe_wm intermediate;
673 * Optimal watermarks, programmed post-vblank
674 * when this state is committed.
676 struct intel_pipe_wm optimal;
680 /* gen9+ only needs 1-step wm programming */
681 struct skl_pipe_wm optimal;
682 struct skl_ddb_entry ddb;
686 /* "raw" watermarks (not inverted) */
687 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
688 /* intermediate watermarks (inverted) */
689 struct vlv_wm_state intermediate;
690 /* optimal watermarks (inverted) */
691 struct vlv_wm_state optimal;
692 /* display FIFO split */
693 struct vlv_fifo_state fifo_state;
697 /* "raw" watermarks */
698 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
699 /* intermediate watermarks */
700 struct g4x_wm_state intermediate;
701 /* optimal watermarks */
702 struct g4x_wm_state optimal;
707 * Platforms with two-step watermark programming will need to
708 * update watermark programming post-vblank to switch from the
709 * safe intermediate watermarks to the optimal final
712 bool need_postvbl_update;
715 struct intel_crtc_state {
716 struct drm_crtc_state base;
719 * quirks - bitfield with hw state readout quirks
721 * For various reasons the hw state readout code might not be able to
722 * completely faithfully read out the current state. These cases are
723 * tracked with quirk flags so that fastboot and state checker can act
726 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
727 unsigned long quirks;
729 unsigned fb_bits; /* framebuffers to flip */
730 bool update_pipe; /* can a fast modeset be performed? */
732 bool update_wm_pre, update_wm_post; /* watermarks are updated */
733 bool fb_changed; /* fb on any of the planes is changed */
734 bool fifo_changed; /* FIFO split is changed */
736 /* Pipe source size (ie. panel fitter input size)
737 * All planes will be positioned inside this space,
738 * and get clipped at the edges. */
739 int pipe_src_w, pipe_src_h;
742 * Pipe pixel rate, adjusted for
743 * panel fitter/pipe scaler downscaling.
745 unsigned int pixel_rate;
747 /* Whether to set up the PCH/FDI. Note that we never allow sharing
748 * between pch encoders and cpu encoders. */
749 bool has_pch_encoder;
751 /* Are we sending infoframes on the attached port */
754 /* CPU Transcoder for the pipe. Currently this can only differ from the
755 * pipe on Haswell and later (where we have a special eDP transcoder)
756 * and Broxton (where we have special DSI transcoders). */
757 enum transcoder cpu_transcoder;
760 * Use reduced/limited/broadcast rbg range, compressing from the full
761 * range fed into the crtcs.
763 bool limited_color_range;
765 /* Bitmask of encoder types (enum intel_output_type)
766 * driven by the pipe.
768 unsigned int output_types;
770 /* Whether we should send NULL infoframes. Required for audio. */
773 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
774 * has_dp_encoder is set. */
778 * Enable dithering, used when the selected pipe bpp doesn't match the
784 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
785 * compliance video pattern tests.
786 * Disable dither only if it is a compliance test request for
789 bool dither_force_disable;
791 /* Controls for the clock computation, to override various stages. */
794 /* SDVO TV has a bunch of special case. To make multifunction encoders
795 * work correctly, we need to track this at runtime.*/
799 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
800 * required. This is set in the 2nd loop of calling encoder's
801 * ->compute_config if the first pick doesn't work out.
805 /* Settings for the intel dpll used on pretty much everything but
809 /* Selected dpll when shared or NULL. */
810 struct intel_shared_dpll *shared_dpll;
812 /* Actual register state of the dpll, for shared dpll cross-checking. */
813 struct intel_dpll_hw_state dpll_hw_state;
815 /* DSI PLL registers */
821 struct intel_link_m_n dp_m_n;
823 /* m2_n2 for eDP downclock */
824 struct intel_link_m_n dp_m2_n2;
831 * Frequence the dpll for the port should run at. Differs from the
832 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
833 * already multiplied by pixel_multiplier.
837 /* Used by SDVO (and if we ever fix it, HDMI). */
838 unsigned pixel_multiplier;
843 * Used by platforms having DP/HDMI PHY with programmable lane
844 * latency optimization.
846 uint8_t lane_lat_optim_mask;
848 /* minimum acceptable voltage level */
849 u8 min_voltage_level;
851 /* Panel fitter controls for gen2-gen4 + VLV */
855 u32 lvds_border_bits;
858 /* Panel fitter placement and size for Ironlake+ */
866 /* FDI configuration, only valid if has_pch_encoder is set. */
868 struct intel_link_m_n fdi_m_n;
871 bool ips_force_disable;
879 struct intel_crtc_scaler_state scaler_state;
881 /* w/a for waiting 2 vblanks during crtc enable */
882 enum pipe hsw_workaround_pipe;
884 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
887 struct intel_crtc_wm_state wm;
889 /* Gamma mode programmed on the pipe */
892 /* bitmask of visible planes (enum plane_id) */
896 /* HDMI scrambling status */
897 bool hdmi_scrambling;
899 /* HDMI High TMDS char rate ratio */
900 bool hdmi_high_tmds_clock_ratio;
902 /* output format is YCBCR 4:2:0 */
907 struct drm_crtc base;
910 * Whether the crtc and the connected output pipeline is active. Implies
911 * that crtc->enabled is set, i.e. the current mode configuration has
912 * some outputs connected to this crtc.
916 unsigned long long enabled_power_domains;
917 struct intel_overlay *overlay;
919 struct intel_crtc_state *config;
921 /* global reset count when the last flip was submitted */
922 unsigned int reset_count;
924 /* Access to these should be protected by dev_priv->irq_lock. */
925 bool cpu_fifo_underrun_disabled;
926 bool pch_fifo_underrun_disabled;
928 /* per-pipe watermark state */
930 /* watermarks currently being used */
932 struct intel_pipe_wm ilk;
933 struct vlv_wm_state vlv;
934 struct g4x_wm_state g4x;
941 unsigned start_vbl_count;
942 ktime_t start_vbl_time;
943 int min_vbl, max_vbl;
947 /* scalers available on this crtc */
952 struct drm_plane base;
953 enum i9xx_plane_id i9xx_plane;
958 uint32_t frontbuffer_bit;
961 u32 base, cntl, size;
965 * NOTE: Do not place new plane state fields here (e.g., when adding
966 * new plane properties). New runtime state should now be placed in
967 * the intel_plane_state structure and accessed via plane_state.
970 unsigned int (*max_stride)(struct intel_plane *plane,
971 u32 pixel_format, u64 modifier,
972 unsigned int rotation);
973 void (*update_plane)(struct intel_plane *plane,
974 const struct intel_crtc_state *crtc_state,
975 const struct intel_plane_state *plane_state);
976 void (*disable_plane)(struct intel_plane *plane,
977 struct intel_crtc *crtc);
978 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
979 int (*check_plane)(struct intel_crtc_state *crtc_state,
980 struct intel_plane_state *plane_state);
983 struct intel_watermark_params {
991 struct cxsr_latency {
997 u16 display_hpll_disable;
999 u16 cursor_hpll_disable;
1002 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1003 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1004 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1005 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1006 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1007 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1008 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1009 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1010 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1013 i915_reg_t hdmi_reg;
1016 enum drm_dp_dual_mode_type type;
1021 bool rgb_quant_range_selectable;
1022 struct intel_connector *attached_connector;
1023 struct cec_notifier *cec_notifier;
1026 struct intel_dp_mst_encoder;
1027 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1030 * enum link_m_n_set:
1031 * When platform provides two set of M_N registers for dp, we can
1032 * program them and switch between them incase of DRRS.
1033 * But When only one such register is provided, we have to program the
1034 * required divider value on that registers itself based on the DRRS state.
1036 * M1_N1 : Program dp_m_n on M1_N1 registers
1037 * dp_m2_n2 on M2_N2 registers (If supported)
1039 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1040 * M2_N2 registers are not supported
1044 /* Sets the m1_n1 and m2_n2 */
1049 struct intel_dp_compliance_data {
1051 uint8_t video_pattern;
1052 uint16_t hdisplay, vdisplay;
1056 struct intel_dp_compliance {
1057 unsigned long test_type;
1058 struct intel_dp_compliance_data test_data;
1065 i915_reg_t output_reg;
1073 bool reset_link_params;
1075 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1076 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1077 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1078 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1080 int num_source_rates;
1081 const int *source_rates;
1082 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1084 int sink_rates[DP_MAX_SUPPORTED_RATES];
1085 bool use_rate_select;
1086 /* intersection of source and sink rates */
1087 int num_common_rates;
1088 int common_rates[DP_MAX_SUPPORTED_RATES];
1089 /* Max lane count for the current link */
1090 int max_link_lane_count;
1091 /* Max rate for the current link */
1093 /* sink or branch descriptor */
1094 struct drm_dp_desc desc;
1095 struct drm_dp_aux aux;
1096 enum intel_display_power_domain aux_power_domain;
1097 uint8_t train_set[4];
1098 int panel_power_up_delay;
1099 int panel_power_down_delay;
1100 int panel_power_cycle_delay;
1101 int backlight_on_delay;
1102 int backlight_off_delay;
1103 struct delayed_work panel_vdd_work;
1104 bool want_panel_vdd;
1105 unsigned long last_power_on;
1106 unsigned long last_backlight_off;
1107 ktime_t panel_power_off_time;
1109 struct notifier_block edp_notifier;
1112 * Pipe whose power sequencer is currently locked into
1113 * this port. Only relevant on VLV/CHV.
1117 * Pipe currently driving the port. Used for preventing
1118 * the use of the PPS for any pipe currentrly driving
1119 * external DP as that will mess things up on VLV.
1121 enum pipe active_pipe;
1123 * Set if the sequencer may be reset due to a power transition,
1124 * requiring a reinitialization. Only relevant on BXT.
1127 struct edp_power_seq pps_delays;
1129 bool can_mst; /* this port supports mst */
1131 int active_mst_links;
1132 /* connector directly attached - won't be use for modeset in mst world */
1133 struct intel_connector *attached_connector;
1135 /* mst connector list */
1136 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1137 struct drm_dp_mst_topology_mgr mst_mgr;
1139 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1141 * This function returns the value we have to program the AUX_CTL
1142 * register with to kick off an AUX transaction.
1144 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1146 uint32_t aux_clock_divider);
1148 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1149 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1151 /* This is called before a link training is starterd */
1152 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1154 /* Displayport compliance testing */
1155 struct intel_dp_compliance compliance;
1158 struct intel_lspcon {
1160 enum drm_lspcon_mode mode;
1163 struct intel_digital_port {
1164 struct intel_encoder base;
1165 u32 saved_port_bits;
1167 struct intel_hdmi hdmi;
1168 struct intel_lspcon lspcon;
1169 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1170 bool release_cl2_override;
1172 enum intel_display_power_domain ddi_io_power_domain;
1173 enum tc_port_type tc_type;
1175 void (*write_infoframe)(struct intel_encoder *encoder,
1176 const struct intel_crtc_state *crtc_state,
1178 const void *frame, ssize_t len);
1179 void (*set_infoframes)(struct intel_encoder *encoder,
1181 const struct intel_crtc_state *crtc_state,
1182 const struct drm_connector_state *conn_state);
1183 bool (*infoframe_enabled)(struct intel_encoder *encoder,
1184 const struct intel_crtc_state *pipe_config);
1187 struct intel_dp_mst_encoder {
1188 struct intel_encoder base;
1190 struct intel_digital_port *primary;
1191 struct intel_connector *connector;
1194 static inline enum dpio_channel
1195 vlv_dport_to_channel(struct intel_digital_port *dport)
1197 switch (dport->base.port) {
1208 static inline enum dpio_phy
1209 vlv_dport_to_phy(struct intel_digital_port *dport)
1211 switch (dport->base.port) {
1222 static inline enum dpio_channel
1223 vlv_pipe_to_channel(enum pipe pipe)
1236 static inline struct intel_crtc *
1237 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1239 return dev_priv->pipe_to_crtc_mapping[pipe];
1242 static inline struct intel_crtc *
1243 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1245 return dev_priv->plane_to_crtc_mapping[plane];
1248 struct intel_load_detect_pipe {
1249 struct drm_atomic_state *restore_state;
1252 static inline struct intel_encoder *
1253 intel_attached_encoder(struct drm_connector *connector)
1255 return to_intel_connector(connector)->encoder;
1258 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1260 switch (encoder->type) {
1261 case INTEL_OUTPUT_DDI:
1262 case INTEL_OUTPUT_DP:
1263 case INTEL_OUTPUT_EDP:
1264 case INTEL_OUTPUT_HDMI:
1271 static inline struct intel_digital_port *
1272 enc_to_dig_port(struct drm_encoder *encoder)
1274 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1276 if (intel_encoder_is_dig_port(intel_encoder))
1277 return container_of(encoder, struct intel_digital_port,
1283 static inline struct intel_dp_mst_encoder *
1284 enc_to_mst(struct drm_encoder *encoder)
1286 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1289 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1291 return &enc_to_dig_port(encoder)->dp;
1294 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1296 switch (encoder->type) {
1297 case INTEL_OUTPUT_DP:
1298 case INTEL_OUTPUT_EDP:
1300 case INTEL_OUTPUT_DDI:
1301 /* Skip pure HDMI/DVI DDI encoders */
1302 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1308 static inline struct intel_digital_port *
1309 dp_to_dig_port(struct intel_dp *intel_dp)
1311 return container_of(intel_dp, struct intel_digital_port, dp);
1314 static inline struct intel_lspcon *
1315 dp_to_lspcon(struct intel_dp *intel_dp)
1317 return &dp_to_dig_port(intel_dp)->lspcon;
1320 static inline struct drm_i915_private *
1321 dp_to_i915(struct intel_dp *intel_dp)
1323 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1326 static inline struct intel_digital_port *
1327 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1329 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1332 static inline struct intel_plane_state *
1333 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1334 struct intel_plane *plane)
1336 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1340 static inline struct intel_crtc_state *
1341 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1342 struct intel_crtc *crtc)
1344 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1348 static inline struct intel_crtc_state *
1349 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1350 struct intel_crtc *crtc)
1352 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1356 /* intel_fifo_underrun.c */
1357 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, bool enable);
1359 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1360 enum pipe pch_transcoder,
1362 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1364 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1365 enum pipe pch_transcoder);
1366 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1367 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1370 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1371 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1372 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1373 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1374 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1375 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1376 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1377 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1379 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1382 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1385 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1386 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1387 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1390 * We only use drm_irq_uninstall() at unload and VT switch, so
1391 * this is the only thing we need to check.
1393 return dev_priv->runtime_pm.irqs_enabled;
1396 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1397 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1399 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1401 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1402 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1403 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1406 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1407 i915_reg_t adpa_reg, enum pipe *pipe);
1408 void intel_crt_init(struct drm_i915_private *dev_priv);
1409 void intel_crt_reset(struct drm_encoder *encoder);
1412 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1413 const struct intel_crtc_state *old_crtc_state,
1414 const struct drm_connector_state *old_conn_state);
1415 void hsw_fdi_link_train(struct intel_crtc *crtc,
1416 const struct intel_crtc_state *crtc_state);
1417 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1418 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1419 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1420 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1421 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1422 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1423 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1424 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1425 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1426 void intel_ddi_get_config(struct intel_encoder *encoder,
1427 struct intel_crtc_state *pipe_config);
1429 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1431 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1432 struct intel_crtc_state *crtc_state);
1433 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1434 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1435 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1436 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1438 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1440 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1441 struct intel_crtc_state *crtc_state,
1442 struct drm_atomic_state *old_state);
1443 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1444 struct intel_crtc_state *crtc_state,
1445 struct drm_atomic_state *old_state);
1447 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1448 int color_plane, unsigned int height);
1451 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1452 void intel_audio_codec_enable(struct intel_encoder *encoder,
1453 const struct intel_crtc_state *crtc_state,
1454 const struct drm_connector_state *conn_state);
1455 void intel_audio_codec_disable(struct intel_encoder *encoder,
1456 const struct intel_crtc_state *old_crtc_state,
1457 const struct drm_connector_state *old_conn_state);
1458 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1459 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1460 void intel_audio_init(struct drm_i915_private *dev_priv);
1461 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1464 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1465 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1466 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1467 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1468 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1469 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1470 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1471 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1472 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1473 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1474 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1475 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1476 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1477 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1478 const struct intel_cdclk_state *b);
1479 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1480 const struct intel_cdclk_state *b);
1481 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1482 const struct intel_cdclk_state *cdclk_state);
1483 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1484 const char *context);
1486 /* intel_display.c */
1487 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1488 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1489 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1490 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1491 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1492 const char *name, u32 reg, int ref_freq);
1493 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1494 const char *name, u32 reg);
1495 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1496 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1497 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1498 unsigned int intel_fb_xy_to_linear(int x, int y,
1499 const struct intel_plane_state *state,
1501 void intel_add_fb_offsets(int *x, int *y,
1502 const struct intel_plane_state *state, int plane);
1503 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1504 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1505 void intel_mark_busy(struct drm_i915_private *dev_priv);
1506 void intel_mark_idle(struct drm_i915_private *dev_priv);
1507 int intel_display_suspend(struct drm_device *dev);
1508 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1509 void intel_encoder_destroy(struct drm_encoder *encoder);
1510 struct drm_display_mode *
1511 intel_encoder_current_mode(struct intel_encoder *encoder);
1512 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1513 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1516 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1517 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1518 struct drm_file *file_priv);
1519 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1522 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1523 enum intel_output_type type)
1525 return crtc_state->output_types & (1 << type);
1528 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1530 return crtc_state->output_types &
1531 ((1 << INTEL_OUTPUT_DP) |
1532 (1 << INTEL_OUTPUT_DP_MST) |
1533 (1 << INTEL_OUTPUT_EDP));
1536 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1538 drm_wait_one_vblank(&dev_priv->drm, pipe);
1541 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1543 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1546 intel_wait_for_vblank(dev_priv, pipe);
1549 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1551 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1552 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1553 struct intel_digital_port *dport,
1554 unsigned int expected_mask);
1555 int intel_get_load_detect_pipe(struct drm_connector *connector,
1556 const struct drm_display_mode *mode,
1557 struct intel_load_detect_pipe *old,
1558 struct drm_modeset_acquire_ctx *ctx);
1559 void intel_release_load_detect_pipe(struct drm_connector *connector,
1560 struct intel_load_detect_pipe *old,
1561 struct drm_modeset_acquire_ctx *ctx);
1563 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1564 const struct i915_ggtt_view *view,
1566 unsigned long *out_flags);
1567 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1568 struct drm_framebuffer *
1569 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1570 struct drm_mode_fb_cmd2 *mode_cmd);
1571 int intel_prepare_plane_fb(struct drm_plane *plane,
1572 struct drm_plane_state *new_state);
1573 void intel_cleanup_plane_fb(struct drm_plane *plane,
1574 struct drm_plane_state *old_state);
1575 int intel_plane_atomic_get_property(struct drm_plane *plane,
1576 const struct drm_plane_state *state,
1577 struct drm_property *property,
1579 int intel_plane_atomic_set_property(struct drm_plane *plane,
1580 struct drm_plane_state *state,
1581 struct drm_property *property,
1583 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1584 struct drm_crtc_state *crtc_state,
1585 const struct intel_plane_state *old_plane_state,
1586 struct drm_plane_state *plane_state);
1588 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1591 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1592 const struct dpll *dpll);
1593 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1594 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1596 /* modesetting asserts */
1597 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1599 void assert_pll(struct drm_i915_private *dev_priv,
1600 enum pipe pipe, bool state);
1601 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1602 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1603 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1604 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1605 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1606 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1607 enum pipe pipe, bool state);
1608 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1609 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1610 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1611 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1612 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1613 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1614 void intel_finish_reset(struct drm_i915_private *dev_priv);
1615 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1616 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1617 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1618 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1619 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1620 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1621 unsigned int skl_cdclk_get_vco(unsigned int freq);
1622 void intel_dp_get_m_n(struct intel_crtc *crtc,
1623 struct intel_crtc_state *pipe_config);
1624 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1625 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1626 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1627 struct dpll *best_clock);
1628 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1630 bool intel_crtc_active(struct intel_crtc *crtc);
1631 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1632 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1633 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1634 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1635 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1636 struct intel_crtc_state *pipe_config);
1637 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1638 struct intel_crtc_state *crtc_state);
1640 u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1641 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1642 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1645 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1647 return i915_ggtt_offset(state->vma);
1650 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1651 const struct intel_plane_state *plane_state);
1652 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1653 const struct intel_plane_state *plane_state);
1654 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1655 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1657 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1658 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1659 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1660 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1661 u32 pixel_format, u64 modifier,
1662 unsigned int rotation);
1664 /* intel_connector.c */
1665 int intel_connector_init(struct intel_connector *connector);
1666 struct intel_connector *intel_connector_alloc(void);
1667 void intel_connector_free(struct intel_connector *connector);
1668 void intel_connector_destroy(struct drm_connector *connector);
1669 int intel_connector_register(struct drm_connector *connector);
1670 void intel_connector_unregister(struct drm_connector *connector);
1671 void intel_connector_attach_encoder(struct intel_connector *connector,
1672 struct intel_encoder *encoder);
1673 bool intel_connector_get_hw_state(struct intel_connector *connector);
1674 int intel_connector_update_modes(struct drm_connector *connector,
1676 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1677 void intel_attach_force_audio_property(struct drm_connector *connector);
1678 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1679 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1682 void intel_csr_ucode_init(struct drm_i915_private *);
1683 void intel_csr_load_program(struct drm_i915_private *);
1684 void intel_csr_ucode_fini(struct drm_i915_private *);
1685 void intel_csr_ucode_suspend(struct drm_i915_private *);
1686 void intel_csr_ucode_resume(struct drm_i915_private *);
1689 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1690 i915_reg_t dp_reg, enum port port,
1692 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1694 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1695 struct intel_connector *intel_connector);
1696 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1697 int link_rate, uint8_t lane_count,
1699 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1700 int link_rate, uint8_t lane_count);
1701 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1702 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1703 int intel_dp_retrain_link(struct intel_encoder *encoder,
1704 struct drm_modeset_acquire_ctx *ctx);
1705 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1706 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1707 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1708 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1709 bool intel_dp_compute_config(struct intel_encoder *encoder,
1710 struct intel_crtc_state *pipe_config,
1711 struct drm_connector_state *conn_state);
1712 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1713 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1714 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1716 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1717 const struct drm_connector_state *conn_state);
1718 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1719 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1720 void intel_edp_panel_on(struct intel_dp *intel_dp);
1721 void intel_edp_panel_off(struct intel_dp *intel_dp);
1722 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1723 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1724 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1725 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1726 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1727 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1728 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1729 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1730 void intel_plane_destroy(struct drm_plane *plane);
1731 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1732 const struct intel_crtc_state *crtc_state);
1733 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1734 const struct intel_crtc_state *crtc_state);
1735 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1736 unsigned int frontbuffer_bits);
1737 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1738 unsigned int frontbuffer_bits);
1739 void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
1740 void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port);
1741 void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port);
1744 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1745 uint8_t dp_train_pat);
1747 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1748 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1750 intel_dp_voltage_max(struct intel_dp *intel_dp);
1752 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1753 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1754 uint8_t *link_bw, uint8_t *rate_select);
1755 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1756 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1758 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1760 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1762 return ~((1 << lane_count) - 1) & 0xf;
1765 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1766 int intel_dp_link_required(int pixel_clock, int bpp);
1767 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1768 bool intel_digital_port_connected(struct intel_encoder *encoder);
1770 /* intel_dp_aux_backlight.c */
1771 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1773 /* intel_dp_mst.c */
1774 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1775 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1777 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1779 /* intel_dsi_dcs_backlight.c */
1780 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1783 void intel_dvo_init(struct drm_i915_private *dev_priv);
1784 /* intel_hotplug.c */
1785 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1786 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1787 struct intel_connector *connector);
1789 /* legacy fbdev emulation in intel_fbdev.c */
1790 #ifdef CONFIG_DRM_FBDEV_EMULATION
1791 extern int intel_fbdev_init(struct drm_device *dev);
1792 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1793 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1794 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1795 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1796 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1797 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1799 static inline int intel_fbdev_init(struct drm_device *dev)
1804 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1808 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1812 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1816 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1820 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1824 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1830 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1831 struct intel_atomic_state *state);
1832 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1833 void intel_fbc_pre_update(struct intel_crtc *crtc,
1834 struct intel_crtc_state *crtc_state,
1835 struct intel_plane_state *plane_state);
1836 void intel_fbc_post_update(struct intel_crtc *crtc);
1837 void intel_fbc_init(struct drm_i915_private *dev_priv);
1838 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1839 void intel_fbc_enable(struct intel_crtc *crtc,
1840 struct intel_crtc_state *crtc_state,
1841 struct intel_plane_state *plane_state);
1842 void intel_fbc_disable(struct intel_crtc *crtc);
1843 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1844 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1845 unsigned int frontbuffer_bits,
1846 enum fb_op_origin origin);
1847 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1848 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1849 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1850 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1851 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1854 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1856 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1857 struct intel_connector *intel_connector);
1858 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1859 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1860 struct intel_crtc_state *pipe_config,
1861 struct drm_connector_state *conn_state);
1862 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1863 struct drm_connector *connector,
1864 bool high_tmds_clock_ratio,
1866 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1867 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1871 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1872 i915_reg_t lvds_reg, enum pipe *pipe);
1873 void intel_lvds_init(struct drm_i915_private *dev_priv);
1874 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1875 bool intel_is_dual_link_lvds(struct drm_device *dev);
1877 /* intel_overlay.c */
1878 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1879 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1880 int intel_overlay_switch_off(struct intel_overlay *overlay);
1881 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1882 struct drm_file *file_priv);
1883 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1884 struct drm_file *file_priv);
1885 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1889 int intel_panel_init(struct intel_panel *panel,
1890 struct drm_display_mode *fixed_mode,
1891 struct drm_display_mode *downclock_mode);
1892 void intel_panel_fini(struct intel_panel *panel);
1893 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1894 struct drm_display_mode *adjusted_mode);
1895 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1896 struct intel_crtc_state *pipe_config,
1898 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1899 struct intel_crtc_state *pipe_config,
1901 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1902 u32 level, u32 max);
1903 int intel_panel_setup_backlight(struct drm_connector *connector,
1905 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1906 const struct drm_connector_state *conn_state);
1907 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1908 extern struct drm_display_mode *intel_find_panel_downclock(
1909 struct drm_i915_private *dev_priv,
1910 struct drm_display_mode *fixed_mode,
1911 struct drm_connector *connector);
1913 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1914 int intel_backlight_device_register(struct intel_connector *connector);
1915 void intel_backlight_device_unregister(struct intel_connector *connector);
1916 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1917 static inline int intel_backlight_device_register(struct intel_connector *connector)
1921 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1924 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1927 void intel_hdcp_atomic_check(struct drm_connector *connector,
1928 struct drm_connector_state *old_state,
1929 struct drm_connector_state *new_state);
1930 int intel_hdcp_init(struct intel_connector *connector,
1931 const struct intel_hdcp_shim *hdcp_shim);
1932 int intel_hdcp_enable(struct intel_connector *connector);
1933 int intel_hdcp_disable(struct intel_connector *connector);
1934 int intel_hdcp_check_link(struct intel_connector *connector);
1935 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1938 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1939 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1940 void intel_psr_enable(struct intel_dp *intel_dp,
1941 const struct intel_crtc_state *crtc_state);
1942 void intel_psr_disable(struct intel_dp *intel_dp,
1943 const struct intel_crtc_state *old_crtc_state);
1944 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
1945 struct drm_modeset_acquire_ctx *ctx,
1947 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1948 unsigned frontbuffer_bits,
1949 enum fb_op_origin origin);
1950 void intel_psr_flush(struct drm_i915_private *dev_priv,
1951 unsigned frontbuffer_bits,
1952 enum fb_op_origin origin);
1953 void intel_psr_init(struct drm_i915_private *dev_priv);
1954 void intel_psr_compute_config(struct intel_dp *intel_dp,
1955 struct intel_crtc_state *crtc_state);
1956 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
1957 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1958 void intel_psr_short_pulse(struct intel_dp *intel_dp);
1959 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
1962 /* intel_runtime_pm.c */
1963 int intel_power_domains_init(struct drm_i915_private *);
1964 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
1965 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1966 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
1967 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
1968 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
1970 enum i915_drm_suspend_mode {
1971 I915_DRM_SUSPEND_IDLE,
1972 I915_DRM_SUSPEND_MEM,
1973 I915_DRM_SUSPEND_HIBERNATE,
1976 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
1977 enum i915_drm_suspend_mode);
1978 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
1979 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1980 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1981 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1982 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
1984 intel_display_power_domain_str(enum intel_display_power_domain domain);
1986 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1987 enum intel_display_power_domain domain);
1988 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1989 enum intel_display_power_domain domain);
1990 void intel_display_power_get(struct drm_i915_private *dev_priv,
1991 enum intel_display_power_domain domain);
1992 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1993 enum intel_display_power_domain domain);
1994 void intel_display_power_put(struct drm_i915_private *dev_priv,
1995 enum intel_display_power_domain domain);
1996 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2000 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2002 WARN_ONCE(dev_priv->runtime_pm.suspended,
2003 "Device suspended during HW access\n");
2007 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2009 assert_rpm_device_not_suspended(dev_priv);
2010 WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2011 "RPM wakelock ref not held during HW access");
2015 * disable_rpm_wakeref_asserts - disable the RPM assert checks
2016 * @dev_priv: i915 device instance
2018 * This function disable asserts that check if we hold an RPM wakelock
2019 * reference, while keeping the device-not-suspended checks still enabled.
2020 * It's meant to be used only in special circumstances where our rule about
2021 * the wakelock refcount wrt. the device power state doesn't hold. According
2022 * to this rule at any point where we access the HW or want to keep the HW in
2023 * an active state we must hold an RPM wakelock reference acquired via one of
2024 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2025 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2026 * forcewake release timer, and the GPU RPS and hangcheck works. All other
2027 * users should avoid using this function.
2029 * Any calls to this function must have a symmetric call to
2030 * enable_rpm_wakeref_asserts().
2033 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2035 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2039 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2040 * @dev_priv: i915 device instance
2042 * This function re-enables the RPM assert checks after disabling them with
2043 * disable_rpm_wakeref_asserts. It's meant to be used only in special
2044 * circumstances otherwise its use should be avoided.
2046 * Any calls to this function must have a symmetric call to
2047 * disable_rpm_wakeref_asserts().
2050 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2052 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2055 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2056 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2057 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2058 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2060 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2061 bool override, unsigned int mask);
2062 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2063 enum dpio_channel ch, bool override);
2067 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2068 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2069 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2070 void intel_update_watermarks(struct intel_crtc *crtc);
2071 void intel_init_pm(struct drm_i915_private *dev_priv);
2072 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2073 void intel_pm_setup(struct drm_i915_private *dev_priv);
2074 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2075 void intel_gpu_ips_teardown(void);
2076 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2077 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2078 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2079 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2080 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2081 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2082 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2083 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2084 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2085 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2086 void g4x_wm_get_hw_state(struct drm_device *dev);
2087 void vlv_wm_get_hw_state(struct drm_device *dev);
2088 void ilk_wm_get_hw_state(struct drm_device *dev);
2089 void skl_wm_get_hw_state(struct drm_device *dev);
2090 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2091 struct skl_ddb_allocation *ddb /* out */);
2092 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2093 struct skl_pipe_wm *out);
2094 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2095 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2096 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2097 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2098 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2099 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2100 const struct skl_wm_level *l2);
2101 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2102 const struct skl_ddb_entry **entries,
2103 const struct skl_ddb_entry *ddb,
2105 bool ilk_disable_lp_wm(struct drm_device *dev);
2106 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2107 struct intel_crtc_state *cstate);
2108 void intel_init_ipc(struct drm_i915_private *dev_priv);
2109 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2112 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2113 i915_reg_t sdvo_reg, enum pipe *pipe);
2114 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2115 i915_reg_t reg, enum port port);
2118 /* intel_sprite.c */
2119 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2121 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2122 enum pipe pipe, int plane);
2123 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2124 struct drm_file *file_priv);
2125 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2126 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2127 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2128 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2129 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2130 struct intel_plane *intel_plane_alloc(void);
2131 void intel_plane_free(struct intel_plane *plane);
2132 struct intel_plane *
2133 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2134 enum pipe pipe, enum plane_id plane_id);
2137 void intel_tv_init(struct drm_i915_private *dev_priv);
2139 /* intel_atomic.c */
2140 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2141 const struct drm_connector_state *state,
2142 struct drm_property *property,
2144 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2145 struct drm_connector_state *state,
2146 struct drm_property *property,
2148 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2149 struct drm_connector_state *new_state);
2150 struct drm_connector_state *
2151 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2153 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2154 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2155 struct drm_crtc_state *state);
2156 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2157 void intel_atomic_state_clear(struct drm_atomic_state *);
2159 static inline struct intel_crtc_state *
2160 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2161 struct intel_crtc *crtc)
2163 struct drm_crtc_state *crtc_state;
2164 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2165 if (IS_ERR(crtc_state))
2166 return ERR_CAST(crtc_state);
2168 return to_intel_crtc_state(crtc_state);
2171 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2172 struct intel_crtc *intel_crtc,
2173 struct intel_crtc_state *crtc_state);
2175 /* intel_atomic_plane.c */
2176 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2177 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2178 void intel_plane_destroy_state(struct drm_plane *plane,
2179 struct drm_plane_state *state);
2180 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2181 void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
2182 struct intel_crtc *crtc,
2183 struct intel_crtc_state *old_crtc_state,
2184 struct intel_crtc_state *new_crtc_state);
2185 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2186 struct intel_crtc_state *crtc_state,
2187 const struct intel_plane_state *old_plane_state,
2188 struct intel_plane_state *intel_state);
2191 void intel_color_init(struct drm_crtc *crtc);
2192 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2193 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2194 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2196 /* intel_lspcon.c */
2197 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2198 void lspcon_resume(struct intel_lspcon *lspcon);
2199 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2201 /* intel_pipe_crc.c */
2202 #ifdef CONFIG_DEBUG_FS
2203 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2204 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2205 const char *source_name, size_t *values_cnt);
2206 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2208 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2209 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2211 #define intel_crtc_set_crc_source NULL
2212 #define intel_crtc_verify_crc_source NULL
2213 #define intel_crtc_get_crc_sources NULL
2214 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2218 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2222 #endif /* __INTEL_DRV_H__ */