2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
42 #include <media/cec-notifier.h>
45 * __wait_for - magic wait macro
47 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
48 * important that we check the condition again after having timed out, since the
49 * timeout could be due to preemption or similar and we've never had a chance to
50 * check the condition before the timeout.
52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
53 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
54 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
58 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
60 /* Guarantee COND check prior to timeout */ \
70 usleep_range(wait__, wait__ * 2); \
71 if (wait__ < (Wmax)) \
77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
79 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
88 #define _wait_for_atomic(COND, US, ATOMIC) \
90 int cpu, ret, timeout = (US) * 1000; \
92 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
95 cpu = smp_processor_id(); \
97 base = local_clock(); \
99 u64 now = local_clock(); \
102 /* Guarantee COND check prior to timeout */ \
108 if (now - base >= timeout) { \
115 if (unlikely(cpu != smp_processor_id())) { \
116 timeout -= now - base; \
117 cpu = smp_processor_id(); \
118 base = local_clock(); \
125 #define wait_for_us(COND, US) \
128 BUILD_BUG_ON(!__builtin_constant_p(US)); \
130 ret__ = _wait_for((COND), (US), 10, 10); \
132 ret__ = _wait_for_atomic((COND), (US), 0); \
136 #define wait_for_atomic_us(COND, US) \
138 BUILD_BUG_ON(!__builtin_constant_p(US)); \
139 BUILD_BUG_ON((US) > 50000); \
140 _wait_for_atomic((COND), (US), 1); \
143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
145 #define KHz(x) (1000 * (x))
146 #define MHz(x) KHz(1000 * (x))
148 #define KBps(x) (1000 * (x))
149 #define MBps(x) KBps(1000 * (x))
150 #define GBps(x) ((u64)1000 * MBps((x)))
153 * Display related stuff
156 /* store information about an Ixxx DVO */
157 /* The i830->i865 use multiple DVOs with multiple i2cs */
158 /* the i915, i945 have a single sDVO i2c bus - which is different */
159 #define MAX_OUTPUTS 6
160 /* maximum connectors per crtcs in the mode set */
162 #define INTEL_I2C_BUS_DVO 1
163 #define INTEL_I2C_BUS_SDVO 2
165 /* these are outputs from the chip - integrated only
166 external chips are via DVO or SDVO output */
167 enum intel_output_type {
168 INTEL_OUTPUT_UNUSED = 0,
169 INTEL_OUTPUT_ANALOG = 1,
170 INTEL_OUTPUT_DVO = 2,
171 INTEL_OUTPUT_SDVO = 3,
172 INTEL_OUTPUT_LVDS = 4,
173 INTEL_OUTPUT_TVOUT = 5,
174 INTEL_OUTPUT_HDMI = 6,
176 INTEL_OUTPUT_EDP = 8,
177 INTEL_OUTPUT_DSI = 9,
178 INTEL_OUTPUT_DDI = 10,
179 INTEL_OUTPUT_DP_MST = 11,
182 #define INTEL_DVO_CHIP_NONE 0
183 #define INTEL_DVO_CHIP_LVDS 1
184 #define INTEL_DVO_CHIP_TMDS 2
185 #define INTEL_DVO_CHIP_TVOUT 4
187 #define INTEL_DSI_VIDEO_MODE 0
188 #define INTEL_DSI_COMMAND_MODE 1
190 struct intel_framebuffer {
191 struct drm_framebuffer base;
192 struct intel_rotation_info rot_info;
194 /* for each plane in the normal GTT view */
198 /* for each plane in the rotated GTT view */
201 unsigned int pitch; /* pixels */
206 struct drm_fb_helper helper;
207 struct intel_framebuffer *fb;
208 struct i915_vma *vma;
209 unsigned long vma_flags;
210 async_cookie_t cookie;
214 struct intel_encoder {
215 struct drm_encoder base;
217 enum intel_output_type type;
219 unsigned int cloneable;
220 bool (*hotplug)(struct intel_encoder *encoder,
221 struct intel_connector *connector);
222 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
223 struct intel_crtc_state *,
224 struct drm_connector_state *);
225 bool (*compute_config)(struct intel_encoder *,
226 struct intel_crtc_state *,
227 struct drm_connector_state *);
228 void (*pre_pll_enable)(struct intel_encoder *,
229 const struct intel_crtc_state *,
230 const struct drm_connector_state *);
231 void (*pre_enable)(struct intel_encoder *,
232 const struct intel_crtc_state *,
233 const struct drm_connector_state *);
234 void (*enable)(struct intel_encoder *,
235 const struct intel_crtc_state *,
236 const struct drm_connector_state *);
237 void (*disable)(struct intel_encoder *,
238 const struct intel_crtc_state *,
239 const struct drm_connector_state *);
240 void (*post_disable)(struct intel_encoder *,
241 const struct intel_crtc_state *,
242 const struct drm_connector_state *);
243 void (*post_pll_disable)(struct intel_encoder *,
244 const struct intel_crtc_state *,
245 const struct drm_connector_state *);
246 /* Read out the current hw state of this connector, returning true if
247 * the encoder is active. If the encoder is enabled it also set the pipe
248 * it is connected to in the pipe parameter. */
249 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
250 /* Reconstructs the equivalent mode flags for the current hardware
251 * state. This must be called _after_ display->get_pipe_config has
252 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
253 * be set correctly before calling this function. */
254 void (*get_config)(struct intel_encoder *,
255 struct intel_crtc_state *pipe_config);
256 /* Returns a mask of power domains that need to be referenced as part
257 * of the hardware state readout code. */
258 u64 (*get_power_domains)(struct intel_encoder *encoder,
259 struct intel_crtc_state *crtc_state);
261 * Called during system suspend after all pending requests for the
262 * encoder are flushed (for example for DP AUX transactions) and
263 * device interrupts are disabled.
265 void (*suspend)(struct intel_encoder *);
267 enum hpd_pin hpd_pin;
268 enum intel_display_power_domain power_domain;
269 /* for communication with audio component; protected by av_mutex */
270 const struct drm_connector *audio_connector;
274 struct drm_display_mode *fixed_mode;
275 struct drm_display_mode *downclock_mode;
284 bool combination_mode; /* gen 2/4 only */
286 bool alternate_pwm_increment; /* lpt+ */
289 bool util_pin_active_low; /* bxt+ */
290 u8 controller; /* bxt+ only */
291 struct pwm_device *pwm;
293 struct backlight_device *device;
295 /* Connector and platform specific backlight functions */
296 int (*setup)(struct intel_connector *connector, enum pipe pipe);
297 uint32_t (*get)(struct intel_connector *connector);
298 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
299 void (*disable)(const struct drm_connector_state *conn_state);
300 void (*enable)(const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state);
302 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
304 void (*power)(struct intel_connector *, bool enable);
308 struct intel_digital_port;
311 * This structure serves as a translation layer between the generic HDCP code
312 * and the bus-specific code. What that means is that HDCP over HDMI differs
313 * from HDCP over DP, so to account for these differences, we need to
314 * communicate with the receiver through this shim.
316 * For completeness, the 2 buses differ in the following ways:
318 * HDCP registers on the receiver are set via DP AUX for DP, and
319 * they are set via DDC for HDMI.
320 * - Receiver register offsets
321 * The offsets of the registers are different for DP vs. HDMI
322 * - Receiver register masks/offsets
323 * For instance, the ready bit for the KSV fifo is in a different
324 * place on DP vs HDMI
325 * - Receiver register names
326 * Seriously. In the DP spec, the 16-bit register containing
327 * downstream information is called BINFO, on HDMI it's called
328 * BSTATUS. To confuse matters further, DP has a BSTATUS register
329 * with a completely different definition.
331 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
332 * be read 3 keys at a time
334 * Since Aksv is hidden in hardware, there's different procedures
335 * to send it over DP AUX vs DDC
337 struct intel_hdcp_shim {
338 /* Outputs the transmitter's An and Aksv values to the receiver. */
339 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
341 /* Reads the receiver's key selection vector */
342 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
345 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
346 * definitions are the same in the respective specs, but the names are
347 * different. Call it BSTATUS since that's the name the HDMI spec
348 * uses and it was there first.
350 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
353 /* Determines whether a repeater is present downstream */
354 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
355 bool *repeater_present);
357 /* Reads the receiver's Ri' value */
358 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
360 /* Determines if the receiver's KSV FIFO is ready for consumption */
361 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
364 /* Reads the ksv fifo for num_downstream devices */
365 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
366 int num_downstream, u8 *ksv_fifo);
368 /* Reads a 32-bit part of V' from the receiver */
369 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
372 /* Enables HDCP signalling on the port */
373 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
376 /* Ensures the link is still protected */
377 bool (*check_link)(struct intel_digital_port *intel_dig_port);
379 /* Detects panel's hdcp capability. This is optional for HDMI. */
380 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
385 const struct intel_hdcp_shim *shim;
386 /* Mutex for hdcp state of the connector */
389 struct delayed_work check_work;
390 struct work_struct prop_work;
393 struct intel_connector {
394 struct drm_connector base;
396 * The fixed encoder this connector is connected to.
398 struct intel_encoder *encoder;
400 /* ACPI device id for ACPI and driver cooperation */
403 /* Reads out the current hw, returning true if the connector is enabled
404 * and active (i.e. dpms ON state). */
405 bool (*get_hw_state)(struct intel_connector *);
407 /* Panel info for eDP and LVDS */
408 struct intel_panel panel;
410 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
412 struct edid *detect_edid;
414 /* since POLL and HPD connectors may use the same HPD line keep the native
415 state of connector->polled in case hotplug storm detection changes it */
418 void *port; /* store this opaque as its illegal to dereference it */
420 struct intel_dp *mst_port;
422 /* Work struct to schedule a uevent on link train failure */
423 struct work_struct modeset_retry_work;
425 struct intel_hdcp hdcp;
428 struct intel_digital_connector_state {
429 struct drm_connector_state base;
431 enum hdmi_force_audio force_audio;
435 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
449 struct intel_atomic_state {
450 struct drm_atomic_state base;
454 * Logical state of cdclk (used for all scaling, watermark,
455 * etc. calculations and checks). This is computed as if all
456 * enabled crtcs were active.
458 struct intel_cdclk_state logical;
461 * Actual state of cdclk, can be different from the logical
462 * state only when all crtc's are DPMS off.
464 struct intel_cdclk_state actual;
467 bool dpll_set, modeset;
470 * Does this transaction change the pipes that are active? This mask
471 * tracks which CRTC's have changed their active state at the end of
472 * the transaction (not counting the temporary disable during modesets).
473 * This mask should only be non-zero when intel_state->modeset is true,
474 * but the converse is not necessarily true; simply changing a mode may
475 * not flip the final active status of any CRTC's
477 unsigned int active_pipe_changes;
479 unsigned int active_crtcs;
480 /* minimum acceptable cdclk for each pipe */
481 int min_cdclk[I915_MAX_PIPES];
482 /* minimum acceptable voltage level for each pipe */
483 u8 min_voltage_level[I915_MAX_PIPES];
485 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
488 * Current watermarks can't be trusted during hardware readout, so
489 * don't bother calculating intermediate watermarks.
491 bool skip_intermediate_wm;
493 bool rps_interactive;
496 struct skl_ddb_values wm_results;
498 struct i915_sw_fence commit_ready;
500 struct llist_node freed;
503 struct intel_plane_state {
504 struct drm_plane_state base;
505 struct i915_ggtt_view view;
506 struct i915_vma *vma;
508 #define PLANE_HAS_FENCE BIT(0)
514 * bytes for 0/180 degree rotation
515 * pixels for 90/270 degree rotation
521 /* plane control register */
524 /* plane color control register */
529 * = -1 : not using a scaler
530 * >= 0 : using a scalers
532 * plane requiring a scaler:
533 * - During check_plane, its bit is set in
534 * crtc_state->scaler_state.scaler_users by calling helper function
535 * update_scaler_plane.
536 * - scaler_id indicates the scaler it got assigned.
538 * plane doesn't require a scaler:
539 * - this can happen when scaling is no more required or plane simply
541 * - During check_plane, corresponding bit is reset in
542 * crtc_state->scaler_state.scaler_users by calling helper function
543 * update_scaler_plane.
550 * ICL planar formats require 2 planes that are updated as pairs.
551 * This member is used to make sure the other plane is also updated
552 * when required, and for update_slave() to find the correct
553 * plane_state to pass as argument.
555 struct intel_plane *linked_plane;
559 * If set don't update use the linked plane's state for updating
560 * this plane during atomic commit with the update_slave() callback.
562 * It's also used by the watermark code to ignore wm calculations on
563 * this plane. They're calculated by the linked plane's wm code.
567 struct drm_intel_sprite_colorkey ckey;
570 struct intel_initial_plane_config {
571 struct intel_framebuffer *fb;
577 #define SKL_MIN_SRC_W 8
578 #define SKL_MAX_SRC_W 4096
579 #define SKL_MIN_SRC_H 8
580 #define SKL_MAX_SRC_H 4096
581 #define SKL_MIN_DST_W 8
582 #define SKL_MAX_DST_W 4096
583 #define SKL_MIN_DST_H 8
584 #define SKL_MAX_DST_H 4096
585 #define ICL_MAX_SRC_W 5120
586 #define ICL_MAX_SRC_H 4096
587 #define ICL_MAX_DST_W 5120
588 #define ICL_MAX_DST_H 4096
589 #define SKL_MIN_YUV_420_SRC_W 16
590 #define SKL_MIN_YUV_420_SRC_H 16
592 struct intel_scaler {
597 struct intel_crtc_scaler_state {
598 #define SKL_NUM_SCALERS 2
599 struct intel_scaler scalers[SKL_NUM_SCALERS];
602 * scaler_users: keeps track of users requesting scalers on this crtc.
604 * If a bit is set, a user is using a scaler.
605 * Here user can be a plane or crtc as defined below:
606 * bits 0-30 - plane (bit position is index from drm_plane_index)
609 * Instead of creating a new index to cover planes and crtc, using
610 * existing drm_plane_index for planes which is well less than 31
611 * planes and bit 31 for crtc. This should be fine to cover all
614 * intel_atomic_setup_scalers will setup available scalers to users
615 * requesting scalers. It will gracefully fail if request exceeds
618 #define SKL_CRTC_INDEX 31
619 unsigned scaler_users;
621 /* scaler used by crtc for panel fitting purpose */
625 /* drm_mode->private_flags */
626 #define I915_MODE_FLAG_INHERITED 1
627 /* Flag to get scanline using frame time stamps */
628 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
630 struct intel_pipe_wm {
631 struct intel_wm_level wm[5];
635 bool sprites_enabled;
639 struct skl_plane_wm {
640 struct skl_wm_level wm[8];
641 struct skl_wm_level uv_wm[8];
642 struct skl_wm_level trans_wm;
647 struct skl_plane_wm planes[I915_MAX_PLANES];
654 VLV_WM_LEVEL_DDR_DVFS,
658 struct vlv_wm_state {
659 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
660 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
665 struct vlv_fifo_state {
666 u16 plane[I915_MAX_PLANES];
676 struct g4x_wm_state {
677 struct g4x_pipe_wm wm;
679 struct g4x_sr_wm hpll;
685 struct intel_crtc_wm_state {
689 * Intermediate watermarks; these can be
690 * programmed immediately since they satisfy
691 * both the current configuration we're
692 * switching away from and the new
693 * configuration we're switching to.
695 struct intel_pipe_wm intermediate;
698 * Optimal watermarks, programmed post-vblank
699 * when this state is committed.
701 struct intel_pipe_wm optimal;
705 /* gen9+ only needs 1-step wm programming */
706 struct skl_pipe_wm optimal;
707 struct skl_ddb_entry ddb;
711 /* "raw" watermarks (not inverted) */
712 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
713 /* intermediate watermarks (inverted) */
714 struct vlv_wm_state intermediate;
715 /* optimal watermarks (inverted) */
716 struct vlv_wm_state optimal;
717 /* display FIFO split */
718 struct vlv_fifo_state fifo_state;
722 /* "raw" watermarks */
723 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
724 /* intermediate watermarks */
725 struct g4x_wm_state intermediate;
726 /* optimal watermarks */
727 struct g4x_wm_state optimal;
732 * Platforms with two-step watermark programming will need to
733 * update watermark programming post-vblank to switch from the
734 * safe intermediate watermarks to the optimal final
737 bool need_postvbl_update;
740 enum intel_output_format {
741 INTEL_OUTPUT_FORMAT_INVALID,
742 INTEL_OUTPUT_FORMAT_RGB,
743 INTEL_OUTPUT_FORMAT_YCBCR420,
744 INTEL_OUTPUT_FORMAT_YCBCR444,
747 struct intel_crtc_state {
748 struct drm_crtc_state base;
751 * quirks - bitfield with hw state readout quirks
753 * For various reasons the hw state readout code might not be able to
754 * completely faithfully read out the current state. These cases are
755 * tracked with quirk flags so that fastboot and state checker can act
758 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
759 unsigned long quirks;
761 unsigned fb_bits; /* framebuffers to flip */
762 bool update_pipe; /* can a fast modeset be performed? */
764 bool update_wm_pre, update_wm_post; /* watermarks are updated */
765 bool fb_changed; /* fb on any of the planes is changed */
766 bool fifo_changed; /* FIFO split is changed */
768 /* Pipe source size (ie. panel fitter input size)
769 * All planes will be positioned inside this space,
770 * and get clipped at the edges. */
771 int pipe_src_w, pipe_src_h;
774 * Pipe pixel rate, adjusted for
775 * panel fitter/pipe scaler downscaling.
777 unsigned int pixel_rate;
779 /* Whether to set up the PCH/FDI. Note that we never allow sharing
780 * between pch encoders and cpu encoders. */
781 bool has_pch_encoder;
783 /* Are we sending infoframes on the attached port */
786 /* CPU Transcoder for the pipe. Currently this can only differ from the
787 * pipe on Haswell and later (where we have a special eDP transcoder)
788 * and Broxton (where we have special DSI transcoders). */
789 enum transcoder cpu_transcoder;
792 * Use reduced/limited/broadcast rbg range, compressing from the full
793 * range fed into the crtcs.
795 bool limited_color_range;
797 /* Bitmask of encoder types (enum intel_output_type)
798 * driven by the pipe.
800 unsigned int output_types;
802 /* Whether we should send NULL infoframes. Required for audio. */
805 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
806 * has_dp_encoder is set. */
810 * Enable dithering, used when the selected pipe bpp doesn't match the
816 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
817 * compliance video pattern tests.
818 * Disable dither only if it is a compliance test request for
821 bool dither_force_disable;
823 /* Controls for the clock computation, to override various stages. */
826 /* SDVO TV has a bunch of special case. To make multifunction encoders
827 * work correctly, we need to track this at runtime.*/
831 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
832 * required. This is set in the 2nd loop of calling encoder's
833 * ->compute_config if the first pick doesn't work out.
837 /* Settings for the intel dpll used on pretty much everything but
841 /* Selected dpll when shared or NULL. */
842 struct intel_shared_dpll *shared_dpll;
844 /* Actual register state of the dpll, for shared dpll cross-checking. */
845 struct intel_dpll_hw_state dpll_hw_state;
847 /* DSI PLL registers */
853 struct intel_link_m_n dp_m_n;
855 /* m2_n2 for eDP downclock */
856 struct intel_link_m_n dp_m2_n2;
863 * Frequence the dpll for the port should run at. Differs from the
864 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
865 * already multiplied by pixel_multiplier.
869 /* Used by SDVO (and if we ever fix it, HDMI). */
870 unsigned pixel_multiplier;
875 * Used by platforms having DP/HDMI PHY with programmable lane
876 * latency optimization.
878 uint8_t lane_lat_optim_mask;
880 /* minimum acceptable voltage level */
881 u8 min_voltage_level;
883 /* Panel fitter controls for gen2-gen4 + VLV */
887 u32 lvds_border_bits;
890 /* Panel fitter placement and size for Ironlake+ */
898 /* FDI configuration, only valid if has_pch_encoder is set. */
900 struct intel_link_m_n fdi_m_n;
903 bool ips_force_disable;
911 struct intel_crtc_scaler_state scaler_state;
913 /* w/a for waiting 2 vblanks during crtc enable */
914 enum pipe hsw_workaround_pipe;
916 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
919 struct intel_crtc_wm_state wm;
921 /* Gamma mode programmed on the pipe */
924 /* bitmask of visible planes (enum plane_id) */
928 /* HDMI scrambling status */
929 bool hdmi_scrambling;
931 /* HDMI High TMDS char rate ratio */
932 bool hdmi_high_tmds_clock_ratio;
934 /* Output format RGB/YCBCR etc */
935 enum intel_output_format output_format;
937 /* Output down scaling is done in LSPCON device */
938 bool lspcon_downsampling;
942 struct drm_crtc base;
945 * Whether the crtc and the connected output pipeline is active. Implies
946 * that crtc->enabled is set, i.e. the current mode configuration has
947 * some outputs connected to this crtc.
951 unsigned long long enabled_power_domains;
952 struct intel_overlay *overlay;
954 struct intel_crtc_state *config;
956 /* global reset count when the last flip was submitted */
957 unsigned int reset_count;
959 /* Access to these should be protected by dev_priv->irq_lock. */
960 bool cpu_fifo_underrun_disabled;
961 bool pch_fifo_underrun_disabled;
963 /* per-pipe watermark state */
965 /* watermarks currently being used */
967 struct intel_pipe_wm ilk;
968 struct vlv_wm_state vlv;
969 struct g4x_wm_state g4x;
976 unsigned start_vbl_count;
977 ktime_t start_vbl_time;
978 int min_vbl, max_vbl;
982 /* scalers available on this crtc */
987 struct drm_plane base;
988 enum i9xx_plane_id i9xx_plane;
993 uint32_t frontbuffer_bit;
996 u32 base, cntl, size;
1000 * NOTE: Do not place new plane state fields here (e.g., when adding
1001 * new plane properties). New runtime state should now be placed in
1002 * the intel_plane_state structure and accessed via plane_state.
1005 unsigned int (*max_stride)(struct intel_plane *plane,
1006 u32 pixel_format, u64 modifier,
1007 unsigned int rotation);
1008 void (*update_plane)(struct intel_plane *plane,
1009 const struct intel_crtc_state *crtc_state,
1010 const struct intel_plane_state *plane_state);
1011 void (*update_slave)(struct intel_plane *plane,
1012 const struct intel_crtc_state *crtc_state,
1013 const struct intel_plane_state *plane_state);
1014 void (*disable_plane)(struct intel_plane *plane,
1015 struct intel_crtc *crtc);
1016 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1017 int (*check_plane)(struct intel_crtc_state *crtc_state,
1018 struct intel_plane_state *plane_state);
1021 struct intel_watermark_params {
1029 struct cxsr_latency {
1030 bool is_desktop : 1;
1035 u16 display_hpll_disable;
1037 u16 cursor_hpll_disable;
1040 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1041 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1042 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1043 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1044 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1045 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1046 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1047 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1048 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1051 i915_reg_t hdmi_reg;
1054 enum drm_dp_dual_mode_type type;
1059 bool rgb_quant_range_selectable;
1060 struct intel_connector *attached_connector;
1061 struct cec_notifier *cec_notifier;
1064 struct intel_dp_mst_encoder;
1065 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1068 * enum link_m_n_set:
1069 * When platform provides two set of M_N registers for dp, we can
1070 * program them and switch between them incase of DRRS.
1071 * But When only one such register is provided, we have to program the
1072 * required divider value on that registers itself based on the DRRS state.
1074 * M1_N1 : Program dp_m_n on M1_N1 registers
1075 * dp_m2_n2 on M2_N2 registers (If supported)
1077 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1078 * M2_N2 registers are not supported
1082 /* Sets the m1_n1 and m2_n2 */
1087 struct intel_dp_compliance_data {
1089 uint8_t video_pattern;
1090 uint16_t hdisplay, vdisplay;
1094 struct intel_dp_compliance {
1095 unsigned long test_type;
1096 struct intel_dp_compliance_data test_data;
1103 i915_reg_t output_reg;
1111 bool reset_link_params;
1113 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1114 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1115 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1116 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1117 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1119 int num_source_rates;
1120 const int *source_rates;
1121 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1123 int sink_rates[DP_MAX_SUPPORTED_RATES];
1124 bool use_rate_select;
1125 /* intersection of source and sink rates */
1126 int num_common_rates;
1127 int common_rates[DP_MAX_SUPPORTED_RATES];
1128 /* Max lane count for the current link */
1129 int max_link_lane_count;
1130 /* Max rate for the current link */
1132 /* sink or branch descriptor */
1133 struct drm_dp_desc desc;
1134 struct drm_dp_aux aux;
1135 enum intel_display_power_domain aux_power_domain;
1136 uint8_t train_set[4];
1137 int panel_power_up_delay;
1138 int panel_power_down_delay;
1139 int panel_power_cycle_delay;
1140 int backlight_on_delay;
1141 int backlight_off_delay;
1142 struct delayed_work panel_vdd_work;
1143 bool want_panel_vdd;
1144 unsigned long last_power_on;
1145 unsigned long last_backlight_off;
1146 ktime_t panel_power_off_time;
1148 struct notifier_block edp_notifier;
1151 * Pipe whose power sequencer is currently locked into
1152 * this port. Only relevant on VLV/CHV.
1156 * Pipe currently driving the port. Used for preventing
1157 * the use of the PPS for any pipe currentrly driving
1158 * external DP as that will mess things up on VLV.
1160 enum pipe active_pipe;
1162 * Set if the sequencer may be reset due to a power transition,
1163 * requiring a reinitialization. Only relevant on BXT.
1166 struct edp_power_seq pps_delays;
1168 bool can_mst; /* this port supports mst */
1170 int active_mst_links;
1171 /* connector directly attached - won't be use for modeset in mst world */
1172 struct intel_connector *attached_connector;
1174 /* mst connector list */
1175 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1176 struct drm_dp_mst_topology_mgr mst_mgr;
1178 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1180 * This function returns the value we have to program the AUX_CTL
1181 * register with to kick off an AUX transaction.
1183 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1185 uint32_t aux_clock_divider);
1187 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1188 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1190 /* This is called before a link training is starterd */
1191 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1193 /* Displayport compliance testing */
1194 struct intel_dp_compliance compliance;
1197 enum lspcon_vendor {
1199 LSPCON_VENDOR_PARADE
1202 struct intel_lspcon {
1204 enum drm_lspcon_mode mode;
1205 enum lspcon_vendor vendor;
1208 struct intel_digital_port {
1209 struct intel_encoder base;
1210 u32 saved_port_bits;
1212 struct intel_hdmi hdmi;
1213 struct intel_lspcon lspcon;
1214 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1215 bool release_cl2_override;
1217 enum intel_display_power_domain ddi_io_power_domain;
1218 enum tc_port_type tc_type;
1220 void (*write_infoframe)(struct intel_encoder *encoder,
1221 const struct intel_crtc_state *crtc_state,
1223 const void *frame, ssize_t len);
1224 void (*set_infoframes)(struct intel_encoder *encoder,
1226 const struct intel_crtc_state *crtc_state,
1227 const struct drm_connector_state *conn_state);
1228 bool (*infoframe_enabled)(struct intel_encoder *encoder,
1229 const struct intel_crtc_state *pipe_config);
1232 struct intel_dp_mst_encoder {
1233 struct intel_encoder base;
1235 struct intel_digital_port *primary;
1236 struct intel_connector *connector;
1239 static inline enum dpio_channel
1240 vlv_dport_to_channel(struct intel_digital_port *dport)
1242 switch (dport->base.port) {
1253 static inline enum dpio_phy
1254 vlv_dport_to_phy(struct intel_digital_port *dport)
1256 switch (dport->base.port) {
1267 static inline enum dpio_channel
1268 vlv_pipe_to_channel(enum pipe pipe)
1281 static inline struct intel_crtc *
1282 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1284 return dev_priv->pipe_to_crtc_mapping[pipe];
1287 static inline struct intel_crtc *
1288 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1290 return dev_priv->plane_to_crtc_mapping[plane];
1293 struct intel_load_detect_pipe {
1294 struct drm_atomic_state *restore_state;
1297 static inline struct intel_encoder *
1298 intel_attached_encoder(struct drm_connector *connector)
1300 return to_intel_connector(connector)->encoder;
1303 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1305 switch (encoder->type) {
1306 case INTEL_OUTPUT_DDI:
1307 case INTEL_OUTPUT_DP:
1308 case INTEL_OUTPUT_EDP:
1309 case INTEL_OUTPUT_HDMI:
1316 static inline struct intel_digital_port *
1317 enc_to_dig_port(struct drm_encoder *encoder)
1319 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1321 if (intel_encoder_is_dig_port(intel_encoder))
1322 return container_of(encoder, struct intel_digital_port,
1328 static inline struct intel_digital_port *
1329 conn_to_dig_port(struct intel_connector *connector)
1331 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1334 static inline struct intel_dp_mst_encoder *
1335 enc_to_mst(struct drm_encoder *encoder)
1337 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1340 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1342 return &enc_to_dig_port(encoder)->dp;
1345 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1347 switch (encoder->type) {
1348 case INTEL_OUTPUT_DP:
1349 case INTEL_OUTPUT_EDP:
1351 case INTEL_OUTPUT_DDI:
1352 /* Skip pure HDMI/DVI DDI encoders */
1353 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1359 static inline struct intel_lspcon *
1360 enc_to_intel_lspcon(struct drm_encoder *encoder)
1362 return &enc_to_dig_port(encoder)->lspcon;
1365 static inline struct intel_digital_port *
1366 dp_to_dig_port(struct intel_dp *intel_dp)
1368 return container_of(intel_dp, struct intel_digital_port, dp);
1371 static inline struct intel_lspcon *
1372 dp_to_lspcon(struct intel_dp *intel_dp)
1374 return &dp_to_dig_port(intel_dp)->lspcon;
1377 static inline struct drm_i915_private *
1378 dp_to_i915(struct intel_dp *intel_dp)
1380 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1383 static inline struct intel_digital_port *
1384 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1386 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1389 static inline struct intel_plane_state *
1390 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1391 struct intel_plane *plane)
1393 struct drm_plane_state *ret =
1394 drm_atomic_get_plane_state(&state->base, &plane->base);
1397 return ERR_CAST(ret);
1399 return to_intel_plane_state(ret);
1402 static inline struct intel_plane_state *
1403 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1404 struct intel_plane *plane)
1406 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1410 static inline struct intel_plane_state *
1411 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1412 struct intel_plane *plane)
1414 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1418 static inline struct intel_crtc_state *
1419 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1420 struct intel_crtc *crtc)
1422 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1426 static inline struct intel_crtc_state *
1427 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1428 struct intel_crtc *crtc)
1430 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1434 /* intel_fifo_underrun.c */
1435 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1436 enum pipe pipe, bool enable);
1437 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1438 enum pipe pch_transcoder,
1440 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1442 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1443 enum pipe pch_transcoder);
1444 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1445 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1448 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1449 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1450 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1451 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1452 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1453 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1454 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1455 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1457 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1460 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1463 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1464 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1465 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1468 * We only use drm_irq_uninstall() at unload and VT switch, so
1469 * this is the only thing we need to check.
1471 return dev_priv->runtime_pm.irqs_enabled;
1474 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1475 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1477 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1479 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1480 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1481 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1484 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1485 i915_reg_t adpa_reg, enum pipe *pipe);
1486 void intel_crt_init(struct drm_i915_private *dev_priv);
1487 void intel_crt_reset(struct drm_encoder *encoder);
1490 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1491 const struct intel_crtc_state *old_crtc_state,
1492 const struct drm_connector_state *old_conn_state);
1493 void hsw_fdi_link_train(struct intel_crtc *crtc,
1494 const struct intel_crtc_state *crtc_state);
1495 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1496 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1497 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1498 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1499 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1500 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1501 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1502 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1503 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1504 void intel_ddi_get_config(struct intel_encoder *encoder,
1505 struct intel_crtc_state *pipe_config);
1507 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1509 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1510 struct intel_crtc_state *crtc_state);
1511 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1512 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1513 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1514 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1516 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1518 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1519 struct intel_crtc_state *crtc_state,
1520 struct drm_atomic_state *old_state);
1521 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1522 struct intel_crtc_state *crtc_state,
1523 struct drm_atomic_state *old_state);
1525 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1526 int color_plane, unsigned int height);
1529 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1530 void intel_audio_codec_enable(struct intel_encoder *encoder,
1531 const struct intel_crtc_state *crtc_state,
1532 const struct drm_connector_state *conn_state);
1533 void intel_audio_codec_disable(struct intel_encoder *encoder,
1534 const struct intel_crtc_state *old_crtc_state,
1535 const struct drm_connector_state *old_conn_state);
1536 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1537 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1538 void intel_audio_init(struct drm_i915_private *dev_priv);
1539 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1542 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1543 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1544 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1545 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1546 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1547 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1548 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1549 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1550 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1551 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1552 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1553 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1554 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1555 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1556 const struct intel_cdclk_state *b);
1557 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1558 const struct intel_cdclk_state *b);
1559 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1560 const struct intel_cdclk_state *cdclk_state);
1561 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1562 const char *context);
1564 /* intel_display.c */
1565 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1566 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1567 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1568 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1569 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1570 const char *name, u32 reg, int ref_freq);
1571 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1572 const char *name, u32 reg);
1573 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1574 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1575 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1576 unsigned int intel_fb_xy_to_linear(int x, int y,
1577 const struct intel_plane_state *state,
1579 void intel_add_fb_offsets(int *x, int *y,
1580 const struct intel_plane_state *state, int plane);
1581 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1582 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1583 void intel_mark_busy(struct drm_i915_private *dev_priv);
1584 void intel_mark_idle(struct drm_i915_private *dev_priv);
1585 int intel_display_suspend(struct drm_device *dev);
1586 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1587 void intel_encoder_destroy(struct drm_encoder *encoder);
1588 struct drm_display_mode *
1589 intel_encoder_current_mode(struct intel_encoder *encoder);
1590 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1591 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1592 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1594 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1595 struct drm_file *file_priv);
1596 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1599 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1600 enum intel_output_type type)
1602 return crtc_state->output_types & (1 << type);
1605 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1607 return crtc_state->output_types &
1608 ((1 << INTEL_OUTPUT_DP) |
1609 (1 << INTEL_OUTPUT_DP_MST) |
1610 (1 << INTEL_OUTPUT_EDP));
1613 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1615 drm_wait_one_vblank(&dev_priv->drm, pipe);
1618 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1620 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1623 intel_wait_for_vblank(dev_priv, pipe);
1626 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1628 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1629 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1630 struct intel_digital_port *dport,
1631 unsigned int expected_mask);
1632 int intel_get_load_detect_pipe(struct drm_connector *connector,
1633 const struct drm_display_mode *mode,
1634 struct intel_load_detect_pipe *old,
1635 struct drm_modeset_acquire_ctx *ctx);
1636 void intel_release_load_detect_pipe(struct drm_connector *connector,
1637 struct intel_load_detect_pipe *old,
1638 struct drm_modeset_acquire_ctx *ctx);
1640 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1641 const struct i915_ggtt_view *view,
1643 unsigned long *out_flags);
1644 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1645 struct drm_framebuffer *
1646 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1647 struct drm_mode_fb_cmd2 *mode_cmd);
1648 int intel_prepare_plane_fb(struct drm_plane *plane,
1649 struct drm_plane_state *new_state);
1650 void intel_cleanup_plane_fb(struct drm_plane *plane,
1651 struct drm_plane_state *old_state);
1652 int intel_plane_atomic_get_property(struct drm_plane *plane,
1653 const struct drm_plane_state *state,
1654 struct drm_property *property,
1656 int intel_plane_atomic_set_property(struct drm_plane *plane,
1657 struct drm_plane_state *state,
1658 struct drm_property *property,
1660 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1661 struct drm_crtc_state *crtc_state,
1662 const struct intel_plane_state *old_plane_state,
1663 struct drm_plane_state *plane_state);
1665 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1668 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1669 const struct dpll *dpll);
1670 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1671 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1673 /* modesetting asserts */
1674 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1676 void assert_pll(struct drm_i915_private *dev_priv,
1677 enum pipe pipe, bool state);
1678 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1679 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1680 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1681 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1682 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1683 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1684 enum pipe pipe, bool state);
1685 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1686 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1687 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1688 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1689 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1690 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1691 void intel_finish_reset(struct drm_i915_private *dev_priv);
1692 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1693 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1694 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1695 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1696 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1697 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1698 unsigned int skl_cdclk_get_vco(unsigned int freq);
1699 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1700 void intel_dp_get_m_n(struct intel_crtc *crtc,
1701 struct intel_crtc_state *pipe_config);
1702 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1703 enum link_m_n_set m_n);
1704 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1705 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1706 struct dpll *best_clock);
1707 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1709 bool intel_crtc_active(struct intel_crtc *crtc);
1710 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1711 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1712 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1713 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1714 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1715 struct intel_crtc_state *pipe_config);
1716 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1717 struct intel_crtc_state *crtc_state);
1719 u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1720 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1721 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1724 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1726 return i915_ggtt_offset(state->vma);
1729 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1730 const struct intel_plane_state *plane_state);
1731 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1732 const struct intel_plane_state *plane_state);
1733 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1734 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1736 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1737 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1738 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1739 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1740 u32 pixel_format, u64 modifier,
1741 unsigned int rotation);
1743 /* intel_connector.c */
1744 int intel_connector_init(struct intel_connector *connector);
1745 struct intel_connector *intel_connector_alloc(void);
1746 void intel_connector_free(struct intel_connector *connector);
1747 void intel_connector_destroy(struct drm_connector *connector);
1748 int intel_connector_register(struct drm_connector *connector);
1749 void intel_connector_unregister(struct drm_connector *connector);
1750 void intel_connector_attach_encoder(struct intel_connector *connector,
1751 struct intel_encoder *encoder);
1752 bool intel_connector_get_hw_state(struct intel_connector *connector);
1753 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1754 int intel_connector_update_modes(struct drm_connector *connector,
1756 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1757 void intel_attach_force_audio_property(struct drm_connector *connector);
1758 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1759 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1762 void intel_csr_ucode_init(struct drm_i915_private *);
1763 void intel_csr_load_program(struct drm_i915_private *);
1764 void intel_csr_ucode_fini(struct drm_i915_private *);
1765 void intel_csr_ucode_suspend(struct drm_i915_private *);
1766 void intel_csr_ucode_resume(struct drm_i915_private *);
1769 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1770 i915_reg_t dp_reg, enum port port,
1772 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1774 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1775 struct intel_connector *intel_connector);
1776 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1777 int link_rate, uint8_t lane_count,
1779 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1780 int link_rate, uint8_t lane_count);
1781 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1782 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1783 int intel_dp_retrain_link(struct intel_encoder *encoder,
1784 struct drm_modeset_acquire_ctx *ctx);
1785 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1786 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1787 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1788 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1789 bool intel_dp_compute_config(struct intel_encoder *encoder,
1790 struct intel_crtc_state *pipe_config,
1791 struct drm_connector_state *conn_state);
1792 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1793 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1794 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1796 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1797 const struct drm_connector_state *conn_state);
1798 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1799 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1800 void intel_edp_panel_on(struct intel_dp *intel_dp);
1801 void intel_edp_panel_off(struct intel_dp *intel_dp);
1802 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1803 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1804 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1805 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1806 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1807 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1808 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1809 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1810 void intel_plane_destroy(struct drm_plane *plane);
1811 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1812 const struct intel_crtc_state *crtc_state);
1813 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1814 const struct intel_crtc_state *crtc_state);
1815 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1816 unsigned int frontbuffer_bits);
1817 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1818 unsigned int frontbuffer_bits);
1819 void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
1820 void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port);
1821 void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port);
1824 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1825 uint8_t dp_train_pat);
1827 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1828 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1830 intel_dp_voltage_max(struct intel_dp *intel_dp);
1832 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1833 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1834 uint8_t *link_bw, uint8_t *rate_select);
1835 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1836 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1838 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1840 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1842 return ~((1 << lane_count) - 1) & 0xf;
1845 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1846 int intel_dp_link_required(int pixel_clock, int bpp);
1847 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1848 bool intel_digital_port_connected(struct intel_encoder *encoder);
1850 /* intel_dp_aux_backlight.c */
1851 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1853 /* intel_dp_mst.c */
1854 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1855 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1857 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1859 /* intel_dsi_dcs_backlight.c */
1860 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1863 void intel_dvo_init(struct drm_i915_private *dev_priv);
1864 /* intel_hotplug.c */
1865 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1866 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1867 struct intel_connector *connector);
1869 /* legacy fbdev emulation in intel_fbdev.c */
1870 #ifdef CONFIG_DRM_FBDEV_EMULATION
1871 extern int intel_fbdev_init(struct drm_device *dev);
1872 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1873 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1874 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1875 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1876 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1877 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1879 static inline int intel_fbdev_init(struct drm_device *dev)
1884 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1888 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1892 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1896 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1900 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1904 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1910 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1911 struct intel_atomic_state *state);
1912 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1913 void intel_fbc_pre_update(struct intel_crtc *crtc,
1914 struct intel_crtc_state *crtc_state,
1915 struct intel_plane_state *plane_state);
1916 void intel_fbc_post_update(struct intel_crtc *crtc);
1917 void intel_fbc_init(struct drm_i915_private *dev_priv);
1918 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1919 void intel_fbc_enable(struct intel_crtc *crtc,
1920 struct intel_crtc_state *crtc_state,
1921 struct intel_plane_state *plane_state);
1922 void intel_fbc_disable(struct intel_crtc *crtc);
1923 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1924 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1925 unsigned int frontbuffer_bits,
1926 enum fb_op_origin origin);
1927 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1928 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1929 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1930 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1931 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1934 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1936 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1937 struct intel_connector *intel_connector);
1938 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1939 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1940 struct intel_crtc_state *pipe_config,
1941 struct drm_connector_state *conn_state);
1942 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1943 struct drm_connector *connector,
1944 bool high_tmds_clock_ratio,
1946 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1947 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1950 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1951 i915_reg_t lvds_reg, enum pipe *pipe);
1952 void intel_lvds_init(struct drm_i915_private *dev_priv);
1953 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1954 bool intel_is_dual_link_lvds(struct drm_device *dev);
1956 /* intel_overlay.c */
1957 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1958 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1959 int intel_overlay_switch_off(struct intel_overlay *overlay);
1960 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1961 struct drm_file *file_priv);
1962 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1963 struct drm_file *file_priv);
1964 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1968 int intel_panel_init(struct intel_panel *panel,
1969 struct drm_display_mode *fixed_mode,
1970 struct drm_display_mode *downclock_mode);
1971 void intel_panel_fini(struct intel_panel *panel);
1972 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1973 struct drm_display_mode *adjusted_mode);
1974 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1975 struct intel_crtc_state *pipe_config,
1977 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1978 struct intel_crtc_state *pipe_config,
1980 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1981 u32 level, u32 max);
1982 int intel_panel_setup_backlight(struct drm_connector *connector,
1984 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1985 const struct drm_connector_state *conn_state);
1986 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1987 extern struct drm_display_mode *intel_find_panel_downclock(
1988 struct drm_i915_private *dev_priv,
1989 struct drm_display_mode *fixed_mode,
1990 struct drm_connector *connector);
1992 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1993 int intel_backlight_device_register(struct intel_connector *connector);
1994 void intel_backlight_device_unregister(struct intel_connector *connector);
1995 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1996 static inline int intel_backlight_device_register(struct intel_connector *connector)
2000 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2003 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2006 void intel_hdcp_atomic_check(struct drm_connector *connector,
2007 struct drm_connector_state *old_state,
2008 struct drm_connector_state *new_state);
2009 int intel_hdcp_init(struct intel_connector *connector,
2010 const struct intel_hdcp_shim *hdcp_shim);
2011 int intel_hdcp_enable(struct intel_connector *connector);
2012 int intel_hdcp_disable(struct intel_connector *connector);
2013 int intel_hdcp_check_link(struct intel_connector *connector);
2014 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2015 bool intel_hdcp_capable(struct intel_connector *connector);
2018 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2019 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2020 void intel_psr_enable(struct intel_dp *intel_dp,
2021 const struct intel_crtc_state *crtc_state);
2022 void intel_psr_disable(struct intel_dp *intel_dp,
2023 const struct intel_crtc_state *old_crtc_state);
2024 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
2025 struct drm_modeset_acquire_ctx *ctx,
2027 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2028 unsigned frontbuffer_bits,
2029 enum fb_op_origin origin);
2030 void intel_psr_flush(struct drm_i915_private *dev_priv,
2031 unsigned frontbuffer_bits,
2032 enum fb_op_origin origin);
2033 void intel_psr_init(struct drm_i915_private *dev_priv);
2034 void intel_psr_compute_config(struct intel_dp *intel_dp,
2035 struct intel_crtc_state *crtc_state);
2036 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2037 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2038 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2039 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2042 /* intel_quirks.c */
2043 void intel_init_quirks(struct drm_i915_private *dev_priv);
2045 /* intel_runtime_pm.c */
2046 int intel_power_domains_init(struct drm_i915_private *);
2047 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2048 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2049 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2050 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2051 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2052 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2053 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2055 enum i915_drm_suspend_mode {
2056 I915_DRM_SUSPEND_IDLE,
2057 I915_DRM_SUSPEND_MEM,
2058 I915_DRM_SUSPEND_HIBERNATE,
2061 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2062 enum i915_drm_suspend_mode);
2063 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2064 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2065 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2066 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2067 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2069 intel_display_power_domain_str(enum intel_display_power_domain domain);
2071 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2072 enum intel_display_power_domain domain);
2073 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2074 enum intel_display_power_domain domain);
2075 void intel_display_power_get(struct drm_i915_private *dev_priv,
2076 enum intel_display_power_domain domain);
2077 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2078 enum intel_display_power_domain domain);
2079 void intel_display_power_put(struct drm_i915_private *dev_priv,
2080 enum intel_display_power_domain domain);
2081 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2085 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2087 WARN_ONCE(dev_priv->runtime_pm.suspended,
2088 "Device suspended during HW access\n");
2092 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2094 assert_rpm_device_not_suspended(dev_priv);
2095 WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2096 "RPM wakelock ref not held during HW access");
2100 * disable_rpm_wakeref_asserts - disable the RPM assert checks
2101 * @dev_priv: i915 device instance
2103 * This function disable asserts that check if we hold an RPM wakelock
2104 * reference, while keeping the device-not-suspended checks still enabled.
2105 * It's meant to be used only in special circumstances where our rule about
2106 * the wakelock refcount wrt. the device power state doesn't hold. According
2107 * to this rule at any point where we access the HW or want to keep the HW in
2108 * an active state we must hold an RPM wakelock reference acquired via one of
2109 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2110 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2111 * forcewake release timer, and the GPU RPS and hangcheck works. All other
2112 * users should avoid using this function.
2114 * Any calls to this function must have a symmetric call to
2115 * enable_rpm_wakeref_asserts().
2118 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2120 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2124 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2125 * @dev_priv: i915 device instance
2127 * This function re-enables the RPM assert checks after disabling them with
2128 * disable_rpm_wakeref_asserts. It's meant to be used only in special
2129 * circumstances otherwise its use should be avoided.
2131 * Any calls to this function must have a symmetric call to
2132 * disable_rpm_wakeref_asserts().
2135 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2137 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2140 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2141 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2142 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2143 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2145 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2146 bool override, unsigned int mask);
2147 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2148 enum dpio_channel ch, bool override);
2152 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2153 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2154 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2155 void intel_update_watermarks(struct intel_crtc *crtc);
2156 void intel_init_pm(struct drm_i915_private *dev_priv);
2157 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2158 void intel_pm_setup(struct drm_i915_private *dev_priv);
2159 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2160 void intel_gpu_ips_teardown(void);
2161 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2162 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2163 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2164 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2165 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2166 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2167 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2168 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2169 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2170 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2171 void g4x_wm_get_hw_state(struct drm_device *dev);
2172 void vlv_wm_get_hw_state(struct drm_device *dev);
2173 void ilk_wm_get_hw_state(struct drm_device *dev);
2174 void skl_wm_get_hw_state(struct drm_device *dev);
2175 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2176 struct skl_ddb_allocation *ddb /* out */);
2177 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2178 struct skl_pipe_wm *out);
2179 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2180 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2181 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2182 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2183 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2184 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2185 const struct skl_wm_level *l2);
2186 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2187 const struct skl_ddb_entry **entries,
2188 const struct skl_ddb_entry *ddb,
2190 bool ilk_disable_lp_wm(struct drm_device *dev);
2191 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2192 struct intel_crtc_state *cstate);
2193 void intel_init_ipc(struct drm_i915_private *dev_priv);
2194 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2197 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2198 i915_reg_t sdvo_reg, enum pipe *pipe);
2199 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2200 i915_reg_t reg, enum port port);
2203 /* intel_sprite.c */
2204 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2206 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2207 enum pipe pipe, int plane);
2208 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2209 struct drm_file *file_priv);
2210 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2211 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2212 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2213 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2214 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2215 struct intel_plane *intel_plane_alloc(void);
2216 void intel_plane_free(struct intel_plane *plane);
2217 struct intel_plane *
2218 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2219 enum pipe pipe, enum plane_id plane_id);
2221 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2223 /* Don't need to do a gen check, these planes are only available on gen11 */
2224 if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2230 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2232 if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2235 return plane->id < PLANE_SPRITE2;
2239 void intel_tv_init(struct drm_i915_private *dev_priv);
2241 /* intel_atomic.c */
2242 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2243 const struct drm_connector_state *state,
2244 struct drm_property *property,
2246 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2247 struct drm_connector_state *state,
2248 struct drm_property *property,
2250 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2251 struct drm_connector_state *new_state);
2252 struct drm_connector_state *
2253 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2255 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2256 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2257 struct drm_crtc_state *state);
2258 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2259 void intel_atomic_state_clear(struct drm_atomic_state *);
2261 static inline struct intel_crtc_state *
2262 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2263 struct intel_crtc *crtc)
2265 struct drm_crtc_state *crtc_state;
2266 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2267 if (IS_ERR(crtc_state))
2268 return ERR_CAST(crtc_state);
2270 return to_intel_crtc_state(crtc_state);
2273 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2274 struct intel_crtc *intel_crtc,
2275 struct intel_crtc_state *crtc_state);
2277 /* intel_atomic_plane.c */
2278 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2279 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2280 void intel_plane_destroy_state(struct drm_plane *plane,
2281 struct drm_plane_state *state);
2282 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2283 void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
2284 struct intel_crtc *crtc,
2285 struct intel_crtc_state *old_crtc_state,
2286 struct intel_crtc_state *new_crtc_state);
2287 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2288 struct intel_crtc_state *crtc_state,
2289 const struct intel_plane_state *old_plane_state,
2290 struct intel_plane_state *intel_state);
2293 void intel_color_init(struct drm_crtc *crtc);
2294 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2295 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2296 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2298 /* intel_lspcon.c */
2299 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2300 void lspcon_resume(struct intel_lspcon *lspcon);
2301 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2302 void lspcon_write_infoframe(struct intel_encoder *encoder,
2303 const struct intel_crtc_state *crtc_state,
2305 const void *buf, ssize_t len);
2306 void lspcon_set_infoframes(struct intel_encoder *encoder,
2308 const struct intel_crtc_state *crtc_state,
2309 const struct drm_connector_state *conn_state);
2310 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2311 const struct intel_crtc_state *pipe_config);
2312 void lspcon_ycbcr420_config(struct drm_connector *connector,
2313 struct intel_crtc_state *crtc_state);
2315 /* intel_pipe_crc.c */
2316 #ifdef CONFIG_DEBUG_FS
2317 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2318 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2319 const char *source_name, size_t *values_cnt);
2320 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2322 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2323 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2325 #define intel_crtc_set_crc_source NULL
2326 #define intel_crtc_verify_crc_source NULL
2327 #define intel_crtc_get_crc_sources NULL
2328 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2332 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2336 #endif /* __INTEL_DRV_H__ */