2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_rect.h>
39 #include <drm/drm_atomic.h>
42 * _wait_for - magic (register) wait macro
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 #define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 bool expired__ = time_after(jiffies, timeout__); \
66 if ((W) && drm_can_sleep()) { \
67 usleep_range((W), (W)*2); \
75 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
77 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
78 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
84 #define _wait_for_atomic(COND, US, ATOMIC) \
86 int cpu, ret, timeout = (US) * 1000; \
88 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
89 BUILD_BUG_ON((US) > 50000); \
92 cpu = smp_processor_id(); \
94 base = local_clock(); \
96 u64 now = local_clock(); \
103 if (now - base >= timeout) { \
110 if (unlikely(cpu != smp_processor_id())) { \
111 timeout -= now - base; \
112 cpu = smp_processor_id(); \
113 base = local_clock(); \
120 #define wait_for_us(COND, US) \
123 BUILD_BUG_ON(!__builtin_constant_p(US)); \
125 ret__ = _wait_for((COND), (US), 10); \
127 ret__ = _wait_for_atomic((COND), (US), 0); \
131 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
132 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
134 #define KHz(x) (1000 * (x))
135 #define MHz(x) KHz(1000 * (x))
138 * Display related stuff
141 /* store information about an Ixxx DVO */
142 /* The i830->i865 use multiple DVOs with multiple i2cs */
143 /* the i915, i945 have a single sDVO i2c bus - which is different */
144 #define MAX_OUTPUTS 6
145 /* maximum connectors per crtcs in the mode set */
147 /* Maximum cursor sizes */
148 #define GEN2_CURSOR_WIDTH 64
149 #define GEN2_CURSOR_HEIGHT 64
150 #define MAX_CURSOR_WIDTH 256
151 #define MAX_CURSOR_HEIGHT 256
153 #define INTEL_I2C_BUS_DVO 1
154 #define INTEL_I2C_BUS_SDVO 2
156 /* these are outputs from the chip - integrated only
157 external chips are via DVO or SDVO output */
158 enum intel_output_type {
159 INTEL_OUTPUT_UNUSED = 0,
160 INTEL_OUTPUT_ANALOG = 1,
161 INTEL_OUTPUT_DVO = 2,
162 INTEL_OUTPUT_SDVO = 3,
163 INTEL_OUTPUT_LVDS = 4,
164 INTEL_OUTPUT_TVOUT = 5,
165 INTEL_OUTPUT_HDMI = 6,
167 INTEL_OUTPUT_EDP = 8,
168 INTEL_OUTPUT_DSI = 9,
169 INTEL_OUTPUT_UNKNOWN = 10,
170 INTEL_OUTPUT_DP_MST = 11,
173 #define INTEL_DVO_CHIP_NONE 0
174 #define INTEL_DVO_CHIP_LVDS 1
175 #define INTEL_DVO_CHIP_TMDS 2
176 #define INTEL_DVO_CHIP_TVOUT 4
178 #define INTEL_DSI_VIDEO_MODE 0
179 #define INTEL_DSI_COMMAND_MODE 1
181 struct intel_framebuffer {
182 struct drm_framebuffer base;
183 struct drm_i915_gem_object *obj;
184 struct intel_rotation_info rot_info;
186 /* for each plane in the normal GTT view */
190 /* for each plane in the rotated GTT view */
193 unsigned int pitch; /* pixels */
198 struct drm_fb_helper helper;
199 struct intel_framebuffer *fb;
200 struct i915_vma *vma;
201 async_cookie_t cookie;
205 struct intel_encoder {
206 struct drm_encoder base;
208 enum intel_output_type type;
210 unsigned int cloneable;
211 void (*hot_plug)(struct intel_encoder *);
212 bool (*compute_config)(struct intel_encoder *,
213 struct intel_crtc_state *,
214 struct drm_connector_state *);
215 void (*pre_pll_enable)(struct intel_encoder *,
216 struct intel_crtc_state *,
217 struct drm_connector_state *);
218 void (*pre_enable)(struct intel_encoder *,
219 struct intel_crtc_state *,
220 struct drm_connector_state *);
221 void (*enable)(struct intel_encoder *,
222 struct intel_crtc_state *,
223 struct drm_connector_state *);
224 void (*disable)(struct intel_encoder *,
225 struct intel_crtc_state *,
226 struct drm_connector_state *);
227 void (*post_disable)(struct intel_encoder *,
228 struct intel_crtc_state *,
229 struct drm_connector_state *);
230 void (*post_pll_disable)(struct intel_encoder *,
231 struct intel_crtc_state *,
232 struct drm_connector_state *);
233 /* Read out the current hw state of this connector, returning true if
234 * the encoder is active. If the encoder is enabled it also set the pipe
235 * it is connected to in the pipe parameter. */
236 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
237 /* Reconstructs the equivalent mode flags for the current hardware
238 * state. This must be called _after_ display->get_pipe_config has
239 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
240 * be set correctly before calling this function. */
241 void (*get_config)(struct intel_encoder *,
242 struct intel_crtc_state *pipe_config);
244 * Called during system suspend after all pending requests for the
245 * encoder are flushed (for example for DP AUX transactions) and
246 * device interrupts are disabled.
248 void (*suspend)(struct intel_encoder *);
250 enum hpd_pin hpd_pin;
251 /* for communication with audio component; protected by av_mutex */
252 const struct drm_connector *audio_connector;
256 struct drm_display_mode *fixed_mode;
257 struct drm_display_mode *downclock_mode;
267 bool combination_mode; /* gen 2/4 only */
269 bool alternate_pwm_increment; /* lpt+ */
272 bool util_pin_active_low; /* bxt+ */
273 u8 controller; /* bxt+ only */
274 struct pwm_device *pwm;
276 struct backlight_device *device;
278 /* Connector and platform specific backlight functions */
279 int (*setup)(struct intel_connector *connector, enum pipe pipe);
280 uint32_t (*get)(struct intel_connector *connector);
281 void (*set)(struct intel_connector *connector, uint32_t level);
282 void (*disable)(struct intel_connector *connector);
283 void (*enable)(struct intel_connector *connector);
284 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
286 void (*power)(struct intel_connector *, bool enable);
290 struct intel_connector {
291 struct drm_connector base;
293 * The fixed encoder this connector is connected to.
295 struct intel_encoder *encoder;
297 /* ACPI device id for ACPI and driver cooperation */
300 /* Reads out the current hw, returning true if the connector is enabled
301 * and active (i.e. dpms ON state). */
302 bool (*get_hw_state)(struct intel_connector *);
304 /* Panel info for eDP and LVDS */
305 struct intel_panel panel;
307 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
309 struct edid *detect_edid;
311 /* since POLL and HPD connectors may use the same HPD line keep the native
312 state of connector->polled in case hotplug storm detection changes it */
315 void *port; /* store this opaque as its illegal to dereference it */
317 struct intel_dp *mst_port;
332 struct intel_atomic_state {
333 struct drm_atomic_state base;
338 * Calculated device cdclk, can be different from cdclk
339 * only when all crtc's are DPMS off.
341 unsigned int dev_cdclk;
343 bool dpll_set, modeset;
346 * Does this transaction change the pipes that are active? This mask
347 * tracks which CRTC's have changed their active state at the end of
348 * the transaction (not counting the temporary disable during modesets).
349 * This mask should only be non-zero when intel_state->modeset is true,
350 * but the converse is not necessarily true; simply changing a mode may
351 * not flip the final active status of any CRTC's
353 unsigned int active_pipe_changes;
355 unsigned int active_crtcs;
356 unsigned int min_pixclk[I915_MAX_PIPES];
359 unsigned int cdclk_pll_vco;
361 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
364 * Current watermarks can't be trusted during hardware readout, so
365 * don't bother calculating intermediate watermarks.
367 bool skip_intermediate_wm;
370 struct skl_wm_values wm_results;
372 struct i915_sw_fence commit_ready;
374 struct llist_node freed;
377 struct intel_plane_state {
378 struct drm_plane_state base;
379 struct drm_rect clip;
392 * = -1 : not using a scaler
393 * >= 0 : using a scalers
395 * plane requiring a scaler:
396 * - During check_plane, its bit is set in
397 * crtc_state->scaler_state.scaler_users by calling helper function
398 * update_scaler_plane.
399 * - scaler_id indicates the scaler it got assigned.
401 * plane doesn't require a scaler:
402 * - this can happen when scaling is no more required or plane simply
404 * - During check_plane, corresponding bit is reset in
405 * crtc_state->scaler_state.scaler_users by calling helper function
406 * update_scaler_plane.
410 struct drm_intel_sprite_colorkey ckey;
413 struct intel_initial_plane_config {
414 struct intel_framebuffer *fb;
420 #define SKL_MIN_SRC_W 8
421 #define SKL_MAX_SRC_W 4096
422 #define SKL_MIN_SRC_H 8
423 #define SKL_MAX_SRC_H 4096
424 #define SKL_MIN_DST_W 8
425 #define SKL_MAX_DST_W 4096
426 #define SKL_MIN_DST_H 8
427 #define SKL_MAX_DST_H 4096
429 struct intel_scaler {
434 struct intel_crtc_scaler_state {
435 #define SKL_NUM_SCALERS 2
436 struct intel_scaler scalers[SKL_NUM_SCALERS];
439 * scaler_users: keeps track of users requesting scalers on this crtc.
441 * If a bit is set, a user is using a scaler.
442 * Here user can be a plane or crtc as defined below:
443 * bits 0-30 - plane (bit position is index from drm_plane_index)
446 * Instead of creating a new index to cover planes and crtc, using
447 * existing drm_plane_index for planes which is well less than 31
448 * planes and bit 31 for crtc. This should be fine to cover all
451 * intel_atomic_setup_scalers will setup available scalers to users
452 * requesting scalers. It will gracefully fail if request exceeds
455 #define SKL_CRTC_INDEX 31
456 unsigned scaler_users;
458 /* scaler used by crtc for panel fitting purpose */
462 /* drm_mode->private_flags */
463 #define I915_MODE_FLAG_INHERITED 1
465 struct intel_pipe_wm {
466 struct intel_wm_level wm[5];
467 struct intel_wm_level raw_wm[5];
471 bool sprites_enabled;
475 struct skl_plane_wm {
476 struct skl_wm_level wm[8];
477 struct skl_wm_level trans_wm;
481 struct skl_plane_wm planes[I915_MAX_PLANES];
485 struct intel_crtc_wm_state {
489 * Intermediate watermarks; these can be
490 * programmed immediately since they satisfy
491 * both the current configuration we're
492 * switching away from and the new
493 * configuration we're switching to.
495 struct intel_pipe_wm intermediate;
498 * Optimal watermarks, programmed post-vblank
499 * when this state is committed.
501 struct intel_pipe_wm optimal;
505 /* gen9+ only needs 1-step wm programming */
506 struct skl_pipe_wm optimal;
507 struct skl_ddb_entry ddb;
512 * Platforms with two-step watermark programming will need to
513 * update watermark programming post-vblank to switch from the
514 * safe intermediate watermarks to the optimal final
517 bool need_postvbl_update;
520 struct intel_crtc_state {
521 struct drm_crtc_state base;
524 * quirks - bitfield with hw state readout quirks
526 * For various reasons the hw state readout code might not be able to
527 * completely faithfully read out the current state. These cases are
528 * tracked with quirk flags so that fastboot and state checker can act
531 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
532 unsigned long quirks;
534 unsigned fb_bits; /* framebuffers to flip */
535 bool update_pipe; /* can a fast modeset be performed? */
537 bool update_wm_pre, update_wm_post; /* watermarks are updated */
538 bool fb_changed; /* fb on any of the planes is changed */
540 /* Pipe source size (ie. panel fitter input size)
541 * All planes will be positioned inside this space,
542 * and get clipped at the edges. */
543 int pipe_src_w, pipe_src_h;
545 /* Whether to set up the PCH/FDI. Note that we never allow sharing
546 * between pch encoders and cpu encoders. */
547 bool has_pch_encoder;
549 /* Are we sending infoframes on the attached port */
552 /* CPU Transcoder for the pipe. Currently this can only differ from the
553 * pipe on Haswell and later (where we have a special eDP transcoder)
554 * and Broxton (where we have special DSI transcoders). */
555 enum transcoder cpu_transcoder;
558 * Use reduced/limited/broadcast rbg range, compressing from the full
559 * range fed into the crtcs.
561 bool limited_color_range;
563 /* Bitmask of encoder types (enum intel_output_type)
564 * driven by the pipe.
566 unsigned int output_types;
568 /* Whether we should send NULL infoframes. Required for audio. */
571 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
572 * has_dp_encoder is set. */
576 * Enable dithering, used when the selected pipe bpp doesn't match the
581 /* Controls for the clock computation, to override various stages. */
584 /* SDVO TV has a bunch of special case. To make multifunction encoders
585 * work correctly, we need to track this at runtime.*/
589 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
590 * required. This is set in the 2nd loop of calling encoder's
591 * ->compute_config if the first pick doesn't work out.
595 /* Settings for the intel dpll used on pretty much everything but
599 /* Selected dpll when shared or NULL. */
600 struct intel_shared_dpll *shared_dpll;
602 /* Actual register state of the dpll, for shared dpll cross-checking. */
603 struct intel_dpll_hw_state dpll_hw_state;
605 /* DSI PLL registers */
611 struct intel_link_m_n dp_m_n;
613 /* m2_n2 for eDP downclock */
614 struct intel_link_m_n dp_m2_n2;
618 * Frequence the dpll for the port should run at. Differs from the
619 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
620 * already multiplied by pixel_multiplier.
624 /* Used by SDVO (and if we ever fix it, HDMI). */
625 unsigned pixel_multiplier;
630 * Used by platforms having DP/HDMI PHY with programmable lane
631 * latency optimization.
633 uint8_t lane_lat_optim_mask;
635 /* Panel fitter controls for gen2-gen4 + VLV */
639 u32 lvds_border_bits;
642 /* Panel fitter placement and size for Ironlake+ */
650 /* FDI configuration, only valid if has_pch_encoder is set. */
652 struct intel_link_m_n fdi_m_n;
662 struct intel_crtc_scaler_state scaler_state;
664 /* w/a for waiting 2 vblanks during crtc enable */
665 enum pipe hsw_workaround_pipe;
667 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
670 struct intel_crtc_wm_state wm;
672 /* Gamma mode programmed on the pipe */
676 struct vlv_wm_state {
677 struct vlv_pipe_wm wm[3];
678 struct vlv_sr_wm sr[3];
679 uint8_t num_active_planes;
686 struct drm_crtc base;
689 u8 lut_r[256], lut_g[256], lut_b[256];
691 * Whether the crtc and the connected output pipeline is active. Implies
692 * that crtc->enabled is set, i.e. the current mode configuration has
693 * some outputs connected to this crtc.
696 unsigned long enabled_power_domains;
698 struct intel_overlay *overlay;
699 struct intel_flip_work *flip_work;
701 atomic_t unpin_work_count;
703 /* Display surface base address adjustement for pageflips. Note that on
704 * gen4+ this only adjusts up to a tile, offsets within a tile are
705 * handled in the hw itself (with the TILEOFF register). */
710 uint32_t cursor_addr;
711 uint32_t cursor_cntl;
712 uint32_t cursor_size;
713 uint32_t cursor_base;
715 struct intel_crtc_state *config;
717 /* global reset count when the last flip was submitted */
718 unsigned int reset_count;
720 /* Access to these should be protected by dev_priv->irq_lock. */
721 bool cpu_fifo_underrun_disabled;
722 bool pch_fifo_underrun_disabled;
724 /* per-pipe watermark state */
726 /* watermarks currently being used */
728 struct intel_pipe_wm ilk;
731 /* allow CxSR on this pipe */
738 unsigned start_vbl_count;
739 ktime_t start_vbl_time;
740 int min_vbl, max_vbl;
744 /* scalers available on this crtc */
747 struct vlv_wm_state wm_state;
750 struct intel_plane_wm_parameters {
751 uint32_t horiz_pixels;
752 uint32_t vert_pixels;
754 * For packed pixel formats:
755 * bytes_per_pixel - holds bytes per pixel
756 * For planar pixel formats:
757 * bytes_per_pixel - holds bytes per pixel for uv-plane
758 * y_bytes_per_pixel - holds bytes per pixel for y-plane
760 uint8_t bytes_per_pixel;
761 uint8_t y_bytes_per_pixel;
765 unsigned int rotation;
770 struct drm_plane base;
775 uint32_t frontbuffer_bit;
777 /* Since we need to change the watermarks before/after
778 * enabling/disabling the planes, we need to store the parameters here
779 * as the other pieces of the struct may not reflect the values we want
780 * for the watermark calculations. Currently only Haswell uses this.
782 struct intel_plane_wm_parameters wm;
785 * NOTE: Do not place new plane state fields here (e.g., when adding
786 * new plane properties). New runtime state should now be placed in
787 * the intel_plane_state structure and accessed via plane_state.
790 void (*update_plane)(struct drm_plane *plane,
791 const struct intel_crtc_state *crtc_state,
792 const struct intel_plane_state *plane_state);
793 void (*disable_plane)(struct drm_plane *plane,
794 struct drm_crtc *crtc);
795 int (*check_plane)(struct drm_plane *plane,
796 struct intel_crtc_state *crtc_state,
797 struct intel_plane_state *state);
800 struct intel_watermark_params {
808 struct cxsr_latency {
814 u16 display_hpll_disable;
816 u16 cursor_hpll_disable;
819 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
820 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
821 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
822 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
823 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
824 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
825 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
826 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
827 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
833 enum drm_dp_dual_mode_type type;
836 bool limited_color_range;
837 bool color_range_auto;
840 enum hdmi_force_audio force_audio;
841 bool rgb_quant_range_selectable;
842 enum hdmi_picture_aspect aspect_ratio;
843 struct intel_connector *attached_connector;
844 void (*write_infoframe)(struct drm_encoder *encoder,
845 enum hdmi_infoframe_type type,
846 const void *frame, ssize_t len);
847 void (*set_infoframes)(struct drm_encoder *encoder,
849 const struct drm_display_mode *adjusted_mode);
850 bool (*infoframe_enabled)(struct drm_encoder *encoder,
851 const struct intel_crtc_state *pipe_config);
854 struct intel_dp_mst_encoder;
855 #define DP_MAX_DOWNSTREAM_PORTS 0x10
859 * When platform provides two set of M_N registers for dp, we can
860 * program them and switch between them incase of DRRS.
861 * But When only one such register is provided, we have to program the
862 * required divider value on that registers itself based on the DRRS state.
864 * M1_N1 : Program dp_m_n on M1_N1 registers
865 * dp_m2_n2 on M2_N2 registers (If supported)
867 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
868 * M2_N2 registers are not supported
872 /* Sets the m1_n1 and m2_n2 */
877 struct intel_dp_desc {
886 i915_reg_t output_reg;
887 i915_reg_t aux_ch_ctl_reg;
888 i915_reg_t aux_ch_data_reg[5];
896 bool channel_eq_status;
897 enum hdmi_force_audio force_audio;
898 bool limited_color_range;
899 bool color_range_auto;
900 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
901 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
902 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
903 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
904 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
905 uint8_t num_sink_rates;
906 int sink_rates[DP_MAX_SUPPORTED_RATES];
907 /* sink or branch descriptor */
908 struct intel_dp_desc desc;
909 struct drm_dp_aux aux;
910 uint8_t train_set[4];
911 int panel_power_up_delay;
912 int panel_power_down_delay;
913 int panel_power_cycle_delay;
914 int backlight_on_delay;
915 int backlight_off_delay;
916 struct delayed_work panel_vdd_work;
918 unsigned long last_power_on;
919 unsigned long last_backlight_off;
920 ktime_t panel_power_off_time;
922 struct notifier_block edp_notifier;
925 * Pipe whose power sequencer is currently locked into
926 * this port. Only relevant on VLV/CHV.
930 * Set if the sequencer may be reset due to a power transition,
931 * requiring a reinitialization. Only relevant on BXT.
934 struct edp_power_seq pps_delays;
936 bool can_mst; /* this port supports mst */
938 int active_mst_links;
939 /* connector directly attached - won't be use for modeset in mst world */
940 struct intel_connector *attached_connector;
942 /* mst connector list */
943 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
944 struct drm_dp_mst_topology_mgr mst_mgr;
946 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
948 * This function returns the value we have to program the AUX_CTL
949 * register with to kick off an AUX transaction.
951 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
954 uint32_t aux_clock_divider);
956 /* This is called before a link training is starterd */
957 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
959 /* Displayport compliance testing */
960 unsigned long compliance_test_type;
961 unsigned long compliance_test_data;
962 bool compliance_test_active;
965 struct intel_lspcon {
967 enum drm_lspcon_mode mode;
971 struct intel_digital_port {
972 struct intel_encoder base;
976 struct intel_hdmi hdmi;
977 struct intel_lspcon lspcon;
978 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
979 bool release_cl2_override;
983 struct intel_dp_mst_encoder {
984 struct intel_encoder base;
986 struct intel_digital_port *primary;
987 struct intel_connector *connector;
990 static inline enum dpio_channel
991 vlv_dport_to_channel(struct intel_digital_port *dport)
993 switch (dport->port) {
1004 static inline enum dpio_phy
1005 vlv_dport_to_phy(struct intel_digital_port *dport)
1007 switch (dport->port) {
1018 static inline enum dpio_channel
1019 vlv_pipe_to_channel(enum pipe pipe)
1032 static inline struct intel_crtc *
1033 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1035 return dev_priv->pipe_to_crtc_mapping[pipe];
1038 static inline struct intel_crtc *
1039 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1041 return dev_priv->plane_to_crtc_mapping[plane];
1044 struct intel_flip_work {
1045 struct work_struct unpin_work;
1046 struct work_struct mmio_work;
1048 struct drm_crtc *crtc;
1049 struct drm_framebuffer *old_fb;
1050 struct drm_i915_gem_object *pending_flip_obj;
1051 struct drm_pending_vblank_event *event;
1055 struct drm_i915_gem_request *flip_queued_req;
1056 u32 flip_queued_vblank;
1057 u32 flip_ready_vblank;
1058 unsigned int rotation;
1061 struct intel_load_detect_pipe {
1062 struct drm_atomic_state *restore_state;
1065 static inline struct intel_encoder *
1066 intel_attached_encoder(struct drm_connector *connector)
1068 return to_intel_connector(connector)->encoder;
1071 static inline struct intel_digital_port *
1072 enc_to_dig_port(struct drm_encoder *encoder)
1074 return container_of(encoder, struct intel_digital_port, base.base);
1077 static inline struct intel_dp_mst_encoder *
1078 enc_to_mst(struct drm_encoder *encoder)
1080 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1083 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1085 return &enc_to_dig_port(encoder)->dp;
1088 static inline struct intel_digital_port *
1089 dp_to_dig_port(struct intel_dp *intel_dp)
1091 return container_of(intel_dp, struct intel_digital_port, dp);
1094 static inline struct intel_digital_port *
1095 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1097 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1100 /* intel_fifo_underrun.c */
1101 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1102 enum pipe pipe, bool enable);
1103 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1104 enum transcoder pch_transcoder,
1106 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1108 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1109 enum transcoder pch_transcoder);
1110 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1111 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1114 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1115 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1116 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1117 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1118 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1119 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1120 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1121 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1122 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1123 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1124 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1125 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1126 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1127 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1130 * We only use drm_irq_uninstall() at unload and VT switch, so
1131 * this is the only thing we need to check.
1133 return dev_priv->pm.irqs_enabled;
1136 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1137 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1138 unsigned int pipe_mask);
1139 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1140 unsigned int pipe_mask);
1141 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1142 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1143 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1146 void intel_crt_init(struct drm_device *dev);
1147 void intel_crt_reset(struct drm_encoder *encoder);
1150 void intel_ddi_clk_select(struct intel_encoder *encoder,
1151 struct intel_shared_dpll *pll);
1152 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1153 struct intel_crtc_state *old_crtc_state,
1154 struct drm_connector_state *old_conn_state);
1155 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1156 void hsw_fdi_link_train(struct drm_crtc *crtc);
1157 void intel_ddi_init(struct drm_device *dev, enum port port);
1158 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1159 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1160 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1161 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1162 enum transcoder cpu_transcoder);
1163 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1164 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1165 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1166 struct intel_crtc_state *crtc_state);
1167 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1168 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1169 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1170 void intel_ddi_get_config(struct intel_encoder *encoder,
1171 struct intel_crtc_state *pipe_config);
1172 struct intel_encoder *
1173 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1175 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1176 void intel_ddi_clock_get(struct intel_encoder *encoder,
1177 struct intel_crtc_state *pipe_config);
1178 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1179 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1180 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1182 unsigned int intel_fb_align_height(struct drm_device *dev,
1183 unsigned int height,
1184 uint32_t pixel_format,
1185 uint64_t fb_format_modifier);
1186 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1187 uint64_t fb_modifier, uint32_t pixel_format);
1190 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1191 void intel_audio_codec_enable(struct intel_encoder *encoder,
1192 const struct intel_crtc_state *crtc_state,
1193 const struct drm_connector_state *conn_state);
1194 void intel_audio_codec_disable(struct intel_encoder *encoder);
1195 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1196 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1198 /* intel_display.c */
1199 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1200 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1201 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1202 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1203 const char *name, u32 reg, int ref_freq);
1204 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1205 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1206 extern const struct drm_plane_funcs intel_plane_funcs;
1207 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1208 unsigned int intel_fb_xy_to_linear(int x, int y,
1209 const struct intel_plane_state *state,
1211 void intel_add_fb_offsets(int *x, int *y,
1212 const struct intel_plane_state *state, int plane);
1213 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1214 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1215 void intel_mark_busy(struct drm_i915_private *dev_priv);
1216 void intel_mark_idle(struct drm_i915_private *dev_priv);
1217 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1218 int intel_display_suspend(struct drm_device *dev);
1219 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1220 void intel_encoder_destroy(struct drm_encoder *encoder);
1221 int intel_connector_init(struct intel_connector *);
1222 struct intel_connector *intel_connector_alloc(void);
1223 bool intel_connector_get_hw_state(struct intel_connector *connector);
1224 void intel_connector_attach_encoder(struct intel_connector *connector,
1225 struct intel_encoder *encoder);
1226 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1227 struct drm_crtc *crtc);
1228 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1229 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1230 struct drm_file *file_priv);
1231 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1234 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1235 enum intel_output_type type)
1237 return crtc_state->output_types & (1 << type);
1240 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1242 return crtc_state->output_types &
1243 ((1 << INTEL_OUTPUT_DP) |
1244 (1 << INTEL_OUTPUT_DP_MST) |
1245 (1 << INTEL_OUTPUT_EDP));
1248 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1250 drm_wait_one_vblank(&dev_priv->drm, pipe);
1253 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1255 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1258 intel_wait_for_vblank(dev_priv, pipe);
1261 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1263 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1264 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1265 struct intel_digital_port *dport,
1266 unsigned int expected_mask);
1267 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1268 struct drm_display_mode *mode,
1269 struct intel_load_detect_pipe *old,
1270 struct drm_modeset_acquire_ctx *ctx);
1271 void intel_release_load_detect_pipe(struct drm_connector *connector,
1272 struct intel_load_detect_pipe *old,
1273 struct drm_modeset_acquire_ctx *ctx);
1275 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1276 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1277 struct drm_framebuffer *
1278 __intel_framebuffer_create(struct drm_device *dev,
1279 struct drm_mode_fb_cmd2 *mode_cmd,
1280 struct drm_i915_gem_object *obj);
1281 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1282 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1283 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1284 int intel_prepare_plane_fb(struct drm_plane *plane,
1285 struct drm_plane_state *new_state);
1286 void intel_cleanup_plane_fb(struct drm_plane *plane,
1287 struct drm_plane_state *old_state);
1288 int intel_plane_atomic_get_property(struct drm_plane *plane,
1289 const struct drm_plane_state *state,
1290 struct drm_property *property,
1292 int intel_plane_atomic_set_property(struct drm_plane *plane,
1293 struct drm_plane_state *state,
1294 struct drm_property *property,
1296 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1297 struct drm_plane_state *plane_state);
1299 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1300 uint64_t fb_modifier, unsigned int cpp);
1302 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1305 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1306 const struct dpll *dpll);
1307 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1308 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1310 /* modesetting asserts */
1311 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1313 void assert_pll(struct drm_i915_private *dev_priv,
1314 enum pipe pipe, bool state);
1315 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1316 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1317 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1318 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1319 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1320 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, bool state);
1322 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1323 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1324 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1325 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1326 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1327 u32 intel_compute_tile_offset(int *x, int *y,
1328 const struct intel_plane_state *state, int plane);
1329 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1330 void intel_finish_reset(struct drm_i915_private *dev_priv);
1331 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1332 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1333 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1334 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1335 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1336 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1337 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1338 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1339 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1340 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1341 unsigned int skl_cdclk_get_vco(unsigned int freq);
1342 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1343 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1344 void intel_dp_get_m_n(struct intel_crtc *crtc,
1345 struct intel_crtc_state *pipe_config);
1346 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1347 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1348 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1349 struct dpll *best_clock);
1350 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1352 bool intel_crtc_active(struct intel_crtc *crtc);
1353 void hsw_enable_ips(struct intel_crtc *crtc);
1354 void hsw_disable_ips(struct intel_crtc *crtc);
1355 enum intel_display_power_domain
1356 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1357 enum intel_display_power_domain
1358 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1359 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1360 struct intel_crtc_state *pipe_config);
1362 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1363 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1365 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1367 u32 skl_plane_ctl_format(uint32_t pixel_format);
1368 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1369 u32 skl_plane_ctl_rotation(unsigned int rotation);
1370 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1371 unsigned int rotation);
1372 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1375 void intel_csr_ucode_init(struct drm_i915_private *);
1376 void intel_csr_load_program(struct drm_i915_private *);
1377 void intel_csr_ucode_fini(struct drm_i915_private *);
1378 void intel_csr_ucode_suspend(struct drm_i915_private *);
1379 void intel_csr_ucode_resume(struct drm_i915_private *);
1382 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1383 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1384 struct intel_connector *intel_connector);
1385 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1386 int link_rate, uint8_t lane_count,
1388 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1389 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1390 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1391 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1392 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1393 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1394 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1395 bool intel_dp_compute_config(struct intel_encoder *encoder,
1396 struct intel_crtc_state *pipe_config,
1397 struct drm_connector_state *conn_state);
1398 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1399 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1401 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1402 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1403 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1404 void intel_edp_panel_on(struct intel_dp *intel_dp);
1405 void intel_edp_panel_off(struct intel_dp *intel_dp);
1406 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1407 void intel_dp_mst_suspend(struct drm_device *dev);
1408 void intel_dp_mst_resume(struct drm_device *dev);
1409 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1410 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1411 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1412 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1413 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1414 void intel_plane_destroy(struct drm_plane *plane);
1415 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1416 struct intel_crtc_state *crtc_state);
1417 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1418 struct intel_crtc_state *crtc_state);
1419 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1420 unsigned int frontbuffer_bits);
1421 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1422 unsigned int frontbuffer_bits);
1425 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1426 uint8_t dp_train_pat);
1428 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1429 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1431 intel_dp_voltage_max(struct intel_dp *intel_dp);
1433 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1434 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1435 uint8_t *link_bw, uint8_t *rate_select);
1436 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1438 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1440 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1442 return ~((1 << lane_count) - 1) & 0xf;
1445 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1446 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1447 struct intel_dp_desc *desc);
1448 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1450 /* intel_dp_aux_backlight.c */
1451 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1453 /* intel_dp_mst.c */
1454 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1455 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1457 void intel_dsi_init(struct drm_device *dev);
1459 /* intel_dsi_dcs_backlight.c */
1460 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1463 void intel_dvo_init(struct drm_device *dev);
1464 /* intel_hotplug.c */
1465 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1468 /* legacy fbdev emulation in intel_fbdev.c */
1469 #ifdef CONFIG_DRM_FBDEV_EMULATION
1470 extern int intel_fbdev_init(struct drm_device *dev);
1471 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1472 extern void intel_fbdev_fini(struct drm_device *dev);
1473 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1474 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1475 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1477 static inline int intel_fbdev_init(struct drm_device *dev)
1482 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1486 static inline void intel_fbdev_fini(struct drm_device *dev)
1490 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1494 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1498 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1504 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1505 struct drm_atomic_state *state);
1506 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1507 void intel_fbc_pre_update(struct intel_crtc *crtc,
1508 struct intel_crtc_state *crtc_state,
1509 struct intel_plane_state *plane_state);
1510 void intel_fbc_post_update(struct intel_crtc *crtc);
1511 void intel_fbc_init(struct drm_i915_private *dev_priv);
1512 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1513 void intel_fbc_enable(struct intel_crtc *crtc,
1514 struct intel_crtc_state *crtc_state,
1515 struct intel_plane_state *plane_state);
1516 void intel_fbc_disable(struct intel_crtc *crtc);
1517 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1518 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1519 unsigned int frontbuffer_bits,
1520 enum fb_op_origin origin);
1521 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1522 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1523 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1524 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1527 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1528 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1529 struct intel_connector *intel_connector);
1530 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1531 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1532 struct intel_crtc_state *pipe_config,
1533 struct drm_connector_state *conn_state);
1534 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1538 void intel_lvds_init(struct drm_device *dev);
1539 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1540 bool intel_is_dual_link_lvds(struct drm_device *dev);
1544 int intel_connector_update_modes(struct drm_connector *connector,
1546 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1547 void intel_attach_force_audio_property(struct drm_connector *connector);
1548 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1549 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1552 /* intel_overlay.c */
1553 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1554 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1555 int intel_overlay_switch_off(struct intel_overlay *overlay);
1556 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1557 struct drm_file *file_priv);
1558 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1559 struct drm_file *file_priv);
1560 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1564 int intel_panel_init(struct intel_panel *panel,
1565 struct drm_display_mode *fixed_mode,
1566 struct drm_display_mode *downclock_mode);
1567 void intel_panel_fini(struct intel_panel *panel);
1568 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1569 struct drm_display_mode *adjusted_mode);
1570 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1571 struct intel_crtc_state *pipe_config,
1573 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1574 struct intel_crtc_state *pipe_config,
1576 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1577 u32 level, u32 max);
1578 int intel_panel_setup_backlight(struct drm_connector *connector,
1580 void intel_panel_enable_backlight(struct intel_connector *connector);
1581 void intel_panel_disable_backlight(struct intel_connector *connector);
1582 void intel_panel_destroy_backlight(struct drm_connector *connector);
1583 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1584 extern struct drm_display_mode *intel_find_panel_downclock(
1585 struct drm_device *dev,
1586 struct drm_display_mode *fixed_mode,
1587 struct drm_connector *connector);
1589 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1590 int intel_backlight_device_register(struct intel_connector *connector);
1591 void intel_backlight_device_unregister(struct intel_connector *connector);
1592 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1593 static int intel_backlight_device_register(struct intel_connector *connector)
1597 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1600 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1604 void intel_psr_enable(struct intel_dp *intel_dp);
1605 void intel_psr_disable(struct intel_dp *intel_dp);
1606 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1607 unsigned frontbuffer_bits);
1608 void intel_psr_flush(struct drm_i915_private *dev_priv,
1609 unsigned frontbuffer_bits,
1610 enum fb_op_origin origin);
1611 void intel_psr_init(struct drm_device *dev);
1612 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1613 unsigned frontbuffer_bits);
1615 /* intel_runtime_pm.c */
1616 int intel_power_domains_init(struct drm_i915_private *);
1617 void intel_power_domains_fini(struct drm_i915_private *);
1618 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1619 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1620 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1621 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1622 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1624 intel_display_power_domain_str(enum intel_display_power_domain domain);
1626 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1627 enum intel_display_power_domain domain);
1628 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1629 enum intel_display_power_domain domain);
1630 void intel_display_power_get(struct drm_i915_private *dev_priv,
1631 enum intel_display_power_domain domain);
1632 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1633 enum intel_display_power_domain domain);
1634 void intel_display_power_put(struct drm_i915_private *dev_priv,
1635 enum intel_display_power_domain domain);
1638 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1640 WARN_ONCE(dev_priv->pm.suspended,
1641 "Device suspended during HW access\n");
1645 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1647 assert_rpm_device_not_suspended(dev_priv);
1648 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1649 * too much noise. */
1650 if (!atomic_read(&dev_priv->pm.wakeref_count))
1651 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1655 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1656 * @dev_priv: i915 device instance
1658 * This function disable asserts that check if we hold an RPM wakelock
1659 * reference, while keeping the device-not-suspended checks still enabled.
1660 * It's meant to be used only in special circumstances where our rule about
1661 * the wakelock refcount wrt. the device power state doesn't hold. According
1662 * to this rule at any point where we access the HW or want to keep the HW in
1663 * an active state we must hold an RPM wakelock reference acquired via one of
1664 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1665 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1666 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1667 * users should avoid using this function.
1669 * Any calls to this function must have a symmetric call to
1670 * enable_rpm_wakeref_asserts().
1673 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1675 atomic_inc(&dev_priv->pm.wakeref_count);
1679 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1680 * @dev_priv: i915 device instance
1682 * This function re-enables the RPM assert checks after disabling them with
1683 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1684 * circumstances otherwise its use should be avoided.
1686 * Any calls to this function must have a symmetric call to
1687 * disable_rpm_wakeref_asserts().
1690 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1692 atomic_dec(&dev_priv->pm.wakeref_count);
1695 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1696 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1697 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1698 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1700 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1702 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1703 bool override, unsigned int mask);
1704 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1705 enum dpio_channel ch, bool override);
1709 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1710 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1711 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1712 void intel_update_watermarks(struct intel_crtc *crtc);
1713 void intel_init_pm(struct drm_i915_private *dev_priv);
1714 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1715 void intel_pm_setup(struct drm_device *dev);
1716 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1717 void intel_gpu_ips_teardown(void);
1718 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1719 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1720 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1721 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1722 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1723 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1724 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1725 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1726 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1727 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1728 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1729 struct intel_rps_client *rps,
1730 unsigned long submitted);
1731 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1732 void vlv_wm_get_hw_state(struct drm_device *dev);
1733 void ilk_wm_get_hw_state(struct drm_device *dev);
1734 void skl_wm_get_hw_state(struct drm_device *dev);
1735 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1736 struct skl_ddb_allocation *ddb /* out */);
1737 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1738 struct skl_pipe_wm *out);
1739 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1740 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1741 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1742 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1743 const struct skl_wm_level *l2);
1744 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1745 const struct skl_ddb_entry *ddb,
1747 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1748 bool ilk_disable_lp_wm(struct drm_device *dev);
1749 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1750 static inline int intel_enable_rc6(void)
1752 return i915.enable_rc6;
1756 bool intel_sdvo_init(struct drm_device *dev,
1757 i915_reg_t reg, enum port port);
1760 /* intel_sprite.c */
1761 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1763 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1764 enum pipe pipe, int plane);
1765 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1766 struct drm_file *file_priv);
1767 void intel_pipe_update_start(struct intel_crtc *crtc);
1768 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1771 void intel_tv_init(struct drm_device *dev);
1773 /* intel_atomic.c */
1774 int intel_connector_atomic_get_property(struct drm_connector *connector,
1775 const struct drm_connector_state *state,
1776 struct drm_property *property,
1778 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1779 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1780 struct drm_crtc_state *state);
1781 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1782 void intel_atomic_state_clear(struct drm_atomic_state *);
1783 struct intel_shared_dpll_config *
1784 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1786 static inline struct intel_crtc_state *
1787 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1788 struct intel_crtc *crtc)
1790 struct drm_crtc_state *crtc_state;
1791 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1792 if (IS_ERR(crtc_state))
1793 return ERR_CAST(crtc_state);
1795 return to_intel_crtc_state(crtc_state);
1798 static inline struct intel_plane_state *
1799 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1800 struct intel_plane *plane)
1802 struct drm_plane_state *plane_state;
1804 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1806 return to_intel_plane_state(plane_state);
1809 int intel_atomic_setup_scalers(struct drm_device *dev,
1810 struct intel_crtc *intel_crtc,
1811 struct intel_crtc_state *crtc_state);
1813 /* intel_atomic_plane.c */
1814 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1815 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1816 void intel_plane_destroy_state(struct drm_plane *plane,
1817 struct drm_plane_state *state);
1818 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1821 void intel_color_init(struct drm_crtc *crtc);
1822 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1823 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1824 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1826 /* intel_lspcon.c */
1827 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1828 void lspcon_resume(struct intel_lspcon *lspcon);
1829 #endif /* __INTEL_DRV_H__ */