2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
42 #include <media/cec-notifier.h>
45 * __wait_for - magic wait macro
47 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
48 * important that we check the condition again after having timed out, since the
49 * timeout could be due to preemption or similar and we've never had a chance to
50 * check the condition before the timeout.
52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
53 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
54 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
58 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
60 /* Guarantee COND check prior to timeout */ \
70 usleep_range(wait__, wait__ * 2); \
71 if (wait__ < (Wmax)) \
77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
79 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
88 #define _wait_for_atomic(COND, US, ATOMIC) \
90 int cpu, ret, timeout = (US) * 1000; \
92 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
95 cpu = smp_processor_id(); \
97 base = local_clock(); \
99 u64 now = local_clock(); \
102 /* Guarantee COND check prior to timeout */ \
108 if (now - base >= timeout) { \
115 if (unlikely(cpu != smp_processor_id())) { \
116 timeout -= now - base; \
117 cpu = smp_processor_id(); \
118 base = local_clock(); \
125 #define wait_for_us(COND, US) \
128 BUILD_BUG_ON(!__builtin_constant_p(US)); \
130 ret__ = _wait_for((COND), (US), 10, 10); \
132 ret__ = _wait_for_atomic((COND), (US), 0); \
136 #define wait_for_atomic_us(COND, US) \
138 BUILD_BUG_ON(!__builtin_constant_p(US)); \
139 BUILD_BUG_ON((US) > 50000); \
140 _wait_for_atomic((COND), (US), 1); \
143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
145 #define KHz(x) (1000 * (x))
146 #define MHz(x) KHz(1000 * (x))
148 #define KBps(x) (1000 * (x))
149 #define MBps(x) KBps(1000 * (x))
150 #define GBps(x) ((u64)1000 * MBps((x)))
153 * Display related stuff
156 /* store information about an Ixxx DVO */
157 /* The i830->i865 use multiple DVOs with multiple i2cs */
158 /* the i915, i945 have a single sDVO i2c bus - which is different */
159 #define MAX_OUTPUTS 6
160 /* maximum connectors per crtcs in the mode set */
162 #define INTEL_I2C_BUS_DVO 1
163 #define INTEL_I2C_BUS_SDVO 2
165 /* these are outputs from the chip - integrated only
166 external chips are via DVO or SDVO output */
167 enum intel_output_type {
168 INTEL_OUTPUT_UNUSED = 0,
169 INTEL_OUTPUT_ANALOG = 1,
170 INTEL_OUTPUT_DVO = 2,
171 INTEL_OUTPUT_SDVO = 3,
172 INTEL_OUTPUT_LVDS = 4,
173 INTEL_OUTPUT_TVOUT = 5,
174 INTEL_OUTPUT_HDMI = 6,
176 INTEL_OUTPUT_EDP = 8,
177 INTEL_OUTPUT_DSI = 9,
178 INTEL_OUTPUT_DDI = 10,
179 INTEL_OUTPUT_DP_MST = 11,
182 #define INTEL_DVO_CHIP_NONE 0
183 #define INTEL_DVO_CHIP_LVDS 1
184 #define INTEL_DVO_CHIP_TMDS 2
185 #define INTEL_DVO_CHIP_TVOUT 4
187 #define INTEL_DSI_VIDEO_MODE 0
188 #define INTEL_DSI_COMMAND_MODE 1
190 struct intel_framebuffer {
191 struct drm_framebuffer base;
192 struct intel_rotation_info rot_info;
194 /* for each plane in the normal GTT view */
198 /* for each plane in the rotated GTT view */
201 unsigned int pitch; /* pixels */
206 struct drm_fb_helper helper;
207 struct intel_framebuffer *fb;
208 struct i915_vma *vma;
209 unsigned long vma_flags;
210 async_cookie_t cookie;
214 struct intel_encoder {
215 struct drm_encoder base;
217 enum intel_output_type type;
219 unsigned int cloneable;
220 bool (*hotplug)(struct intel_encoder *encoder,
221 struct intel_connector *connector);
222 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
223 struct intel_crtc_state *,
224 struct drm_connector_state *);
225 bool (*compute_config)(struct intel_encoder *,
226 struct intel_crtc_state *,
227 struct drm_connector_state *);
228 void (*pre_pll_enable)(struct intel_encoder *,
229 const struct intel_crtc_state *,
230 const struct drm_connector_state *);
231 void (*pre_enable)(struct intel_encoder *,
232 const struct intel_crtc_state *,
233 const struct drm_connector_state *);
234 void (*enable)(struct intel_encoder *,
235 const struct intel_crtc_state *,
236 const struct drm_connector_state *);
237 void (*disable)(struct intel_encoder *,
238 const struct intel_crtc_state *,
239 const struct drm_connector_state *);
240 void (*post_disable)(struct intel_encoder *,
241 const struct intel_crtc_state *,
242 const struct drm_connector_state *);
243 void (*post_pll_disable)(struct intel_encoder *,
244 const struct intel_crtc_state *,
245 const struct drm_connector_state *);
246 /* Read out the current hw state of this connector, returning true if
247 * the encoder is active. If the encoder is enabled it also set the pipe
248 * it is connected to in the pipe parameter. */
249 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
250 /* Reconstructs the equivalent mode flags for the current hardware
251 * state. This must be called _after_ display->get_pipe_config has
252 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
253 * be set correctly before calling this function. */
254 void (*get_config)(struct intel_encoder *,
255 struct intel_crtc_state *pipe_config);
256 /* Returns a mask of power domains that need to be referenced as part
257 * of the hardware state readout code. */
258 u64 (*get_power_domains)(struct intel_encoder *encoder,
259 struct intel_crtc_state *crtc_state);
261 * Called during system suspend after all pending requests for the
262 * encoder are flushed (for example for DP AUX transactions) and
263 * device interrupts are disabled.
265 void (*suspend)(struct intel_encoder *);
267 enum hpd_pin hpd_pin;
268 enum intel_display_power_domain power_domain;
269 /* for communication with audio component; protected by av_mutex */
270 const struct drm_connector *audio_connector;
274 struct drm_display_mode *fixed_mode;
275 struct drm_display_mode *downclock_mode;
284 bool combination_mode; /* gen 2/4 only */
286 bool alternate_pwm_increment; /* lpt+ */
289 bool util_pin_active_low; /* bxt+ */
290 u8 controller; /* bxt+ only */
291 struct pwm_device *pwm;
293 struct backlight_device *device;
295 /* Connector and platform specific backlight functions */
296 int (*setup)(struct intel_connector *connector, enum pipe pipe);
297 uint32_t (*get)(struct intel_connector *connector);
298 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
299 void (*disable)(const struct drm_connector_state *conn_state);
300 void (*enable)(const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state);
302 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
304 void (*power)(struct intel_connector *, bool enable);
308 struct intel_digital_port;
311 * This structure serves as a translation layer between the generic HDCP code
312 * and the bus-specific code. What that means is that HDCP over HDMI differs
313 * from HDCP over DP, so to account for these differences, we need to
314 * communicate with the receiver through this shim.
316 * For completeness, the 2 buses differ in the following ways:
318 * HDCP registers on the receiver are set via DP AUX for DP, and
319 * they are set via DDC for HDMI.
320 * - Receiver register offsets
321 * The offsets of the registers are different for DP vs. HDMI
322 * - Receiver register masks/offsets
323 * For instance, the ready bit for the KSV fifo is in a different
324 * place on DP vs HDMI
325 * - Receiver register names
326 * Seriously. In the DP spec, the 16-bit register containing
327 * downstream information is called BINFO, on HDMI it's called
328 * BSTATUS. To confuse matters further, DP has a BSTATUS register
329 * with a completely different definition.
331 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
332 * be read 3 keys at a time
334 * Since Aksv is hidden in hardware, there's different procedures
335 * to send it over DP AUX vs DDC
337 struct intel_hdcp_shim {
338 /* Outputs the transmitter's An and Aksv values to the receiver. */
339 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
341 /* Reads the receiver's key selection vector */
342 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
345 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
346 * definitions are the same in the respective specs, but the names are
347 * different. Call it BSTATUS since that's the name the HDMI spec
348 * uses and it was there first.
350 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
353 /* Determines whether a repeater is present downstream */
354 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
355 bool *repeater_present);
357 /* Reads the receiver's Ri' value */
358 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
360 /* Determines if the receiver's KSV FIFO is ready for consumption */
361 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
364 /* Reads the ksv fifo for num_downstream devices */
365 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
366 int num_downstream, u8 *ksv_fifo);
368 /* Reads a 32-bit part of V' from the receiver */
369 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
372 /* Enables HDCP signalling on the port */
373 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
376 /* Ensures the link is still protected */
377 bool (*check_link)(struct intel_digital_port *intel_dig_port);
379 /* Detects panel's hdcp capability. This is optional for HDMI. */
380 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
385 const struct intel_hdcp_shim *shim;
386 /* Mutex for hdcp state of the connector */
389 struct delayed_work check_work;
390 struct work_struct prop_work;
393 struct intel_connector {
394 struct drm_connector base;
396 * The fixed encoder this connector is connected to.
398 struct intel_encoder *encoder;
400 /* ACPI device id for ACPI and driver cooperation */
403 /* Reads out the current hw, returning true if the connector is enabled
404 * and active (i.e. dpms ON state). */
405 bool (*get_hw_state)(struct intel_connector *);
407 /* Panel info for eDP and LVDS */
408 struct intel_panel panel;
410 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
412 struct edid *detect_edid;
414 /* since POLL and HPD connectors may use the same HPD line keep the native
415 state of connector->polled in case hotplug storm detection changes it */
418 void *port; /* store this opaque as its illegal to dereference it */
420 struct intel_dp *mst_port;
422 /* Work struct to schedule a uevent on link train failure */
423 struct work_struct modeset_retry_work;
425 struct intel_hdcp hdcp;
428 struct intel_digital_connector_state {
429 struct drm_connector_state base;
431 enum hdmi_force_audio force_audio;
435 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
449 struct intel_atomic_state {
450 struct drm_atomic_state base;
454 * Logical state of cdclk (used for all scaling, watermark,
455 * etc. calculations and checks). This is computed as if all
456 * enabled crtcs were active.
458 struct intel_cdclk_state logical;
461 * Actual state of cdclk, can be different from the logical
462 * state only when all crtc's are DPMS off.
464 struct intel_cdclk_state actual;
467 bool dpll_set, modeset;
470 * Does this transaction change the pipes that are active? This mask
471 * tracks which CRTC's have changed their active state at the end of
472 * the transaction (not counting the temporary disable during modesets).
473 * This mask should only be non-zero when intel_state->modeset is true,
474 * but the converse is not necessarily true; simply changing a mode may
475 * not flip the final active status of any CRTC's
477 unsigned int active_pipe_changes;
479 unsigned int active_crtcs;
480 /* minimum acceptable cdclk for each pipe */
481 int min_cdclk[I915_MAX_PIPES];
482 /* minimum acceptable voltage level for each pipe */
483 u8 min_voltage_level[I915_MAX_PIPES];
485 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
488 * Current watermarks can't be trusted during hardware readout, so
489 * don't bother calculating intermediate watermarks.
491 bool skip_intermediate_wm;
493 bool rps_interactive;
496 struct skl_ddb_values wm_results;
498 struct i915_sw_fence commit_ready;
500 struct llist_node freed;
503 struct intel_plane_state {
504 struct drm_plane_state base;
505 struct i915_ggtt_view view;
506 struct i915_vma *vma;
508 #define PLANE_HAS_FENCE BIT(0)
514 * bytes for 0/180 degree rotation
515 * pixels for 90/270 degree rotation
521 /* plane control register */
524 /* plane color control register */
529 * = -1 : not using a scaler
530 * >= 0 : using a scalers
532 * plane requiring a scaler:
533 * - During check_plane, its bit is set in
534 * crtc_state->scaler_state.scaler_users by calling helper function
535 * update_scaler_plane.
536 * - scaler_id indicates the scaler it got assigned.
538 * plane doesn't require a scaler:
539 * - this can happen when scaling is no more required or plane simply
541 * - During check_plane, corresponding bit is reset in
542 * crtc_state->scaler_state.scaler_users by calling helper function
543 * update_scaler_plane.
550 * ICL planar formats require 2 planes that are updated as pairs.
551 * This member is used to make sure the other plane is also updated
552 * when required, and for update_slave() to find the correct
553 * plane_state to pass as argument.
555 struct intel_plane *linked_plane;
559 * If set don't update use the linked plane's state for updating
560 * this plane during atomic commit with the update_slave() callback.
562 * It's also used by the watermark code to ignore wm calculations on
563 * this plane. They're calculated by the linked plane's wm code.
567 struct drm_intel_sprite_colorkey ckey;
570 struct intel_initial_plane_config {
571 struct intel_framebuffer *fb;
578 #define SKL_MIN_SRC_W 8
579 #define SKL_MAX_SRC_W 4096
580 #define SKL_MIN_SRC_H 8
581 #define SKL_MAX_SRC_H 4096
582 #define SKL_MIN_DST_W 8
583 #define SKL_MAX_DST_W 4096
584 #define SKL_MIN_DST_H 8
585 #define SKL_MAX_DST_H 4096
586 #define ICL_MAX_SRC_W 5120
587 #define ICL_MAX_SRC_H 4096
588 #define ICL_MAX_DST_W 5120
589 #define ICL_MAX_DST_H 4096
590 #define SKL_MIN_YUV_420_SRC_W 16
591 #define SKL_MIN_YUV_420_SRC_H 16
593 struct intel_scaler {
598 struct intel_crtc_scaler_state {
599 #define SKL_NUM_SCALERS 2
600 struct intel_scaler scalers[SKL_NUM_SCALERS];
603 * scaler_users: keeps track of users requesting scalers on this crtc.
605 * If a bit is set, a user is using a scaler.
606 * Here user can be a plane or crtc as defined below:
607 * bits 0-30 - plane (bit position is index from drm_plane_index)
610 * Instead of creating a new index to cover planes and crtc, using
611 * existing drm_plane_index for planes which is well less than 31
612 * planes and bit 31 for crtc. This should be fine to cover all
615 * intel_atomic_setup_scalers will setup available scalers to users
616 * requesting scalers. It will gracefully fail if request exceeds
619 #define SKL_CRTC_INDEX 31
620 unsigned scaler_users;
622 /* scaler used by crtc for panel fitting purpose */
626 /* drm_mode->private_flags */
627 #define I915_MODE_FLAG_INHERITED 1
628 /* Flag to get scanline using frame time stamps */
629 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
631 struct intel_pipe_wm {
632 struct intel_wm_level wm[5];
636 bool sprites_enabled;
640 struct skl_plane_wm {
641 struct skl_wm_level wm[8];
642 struct skl_wm_level uv_wm[8];
643 struct skl_wm_level trans_wm;
648 struct skl_plane_wm planes[I915_MAX_PLANES];
655 VLV_WM_LEVEL_DDR_DVFS,
659 struct vlv_wm_state {
660 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
661 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
666 struct vlv_fifo_state {
667 u16 plane[I915_MAX_PLANES];
677 struct g4x_wm_state {
678 struct g4x_pipe_wm wm;
680 struct g4x_sr_wm hpll;
686 struct intel_crtc_wm_state {
690 * Intermediate watermarks; these can be
691 * programmed immediately since they satisfy
692 * both the current configuration we're
693 * switching away from and the new
694 * configuration we're switching to.
696 struct intel_pipe_wm intermediate;
699 * Optimal watermarks, programmed post-vblank
700 * when this state is committed.
702 struct intel_pipe_wm optimal;
706 /* gen9+ only needs 1-step wm programming */
707 struct skl_pipe_wm optimal;
708 struct skl_ddb_entry ddb;
712 /* "raw" watermarks (not inverted) */
713 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
714 /* intermediate watermarks (inverted) */
715 struct vlv_wm_state intermediate;
716 /* optimal watermarks (inverted) */
717 struct vlv_wm_state optimal;
718 /* display FIFO split */
719 struct vlv_fifo_state fifo_state;
723 /* "raw" watermarks */
724 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
725 /* intermediate watermarks */
726 struct g4x_wm_state intermediate;
727 /* optimal watermarks */
728 struct g4x_wm_state optimal;
733 * Platforms with two-step watermark programming will need to
734 * update watermark programming post-vblank to switch from the
735 * safe intermediate watermarks to the optimal final
738 bool need_postvbl_update;
741 enum intel_output_format {
742 INTEL_OUTPUT_FORMAT_INVALID,
743 INTEL_OUTPUT_FORMAT_RGB,
744 INTEL_OUTPUT_FORMAT_YCBCR420,
745 INTEL_OUTPUT_FORMAT_YCBCR444,
748 struct intel_crtc_state {
749 struct drm_crtc_state base;
752 * quirks - bitfield with hw state readout quirks
754 * For various reasons the hw state readout code might not be able to
755 * completely faithfully read out the current state. These cases are
756 * tracked with quirk flags so that fastboot and state checker can act
759 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
760 unsigned long quirks;
762 unsigned fb_bits; /* framebuffers to flip */
763 bool update_pipe; /* can a fast modeset be performed? */
765 bool update_wm_pre, update_wm_post; /* watermarks are updated */
766 bool fb_changed; /* fb on any of the planes is changed */
767 bool fifo_changed; /* FIFO split is changed */
769 /* Pipe source size (ie. panel fitter input size)
770 * All planes will be positioned inside this space,
771 * and get clipped at the edges. */
772 int pipe_src_w, pipe_src_h;
775 * Pipe pixel rate, adjusted for
776 * panel fitter/pipe scaler downscaling.
778 unsigned int pixel_rate;
780 /* Whether to set up the PCH/FDI. Note that we never allow sharing
781 * between pch encoders and cpu encoders. */
782 bool has_pch_encoder;
784 /* Are we sending infoframes on the attached port */
787 /* CPU Transcoder for the pipe. Currently this can only differ from the
788 * pipe on Haswell and later (where we have a special eDP transcoder)
789 * and Broxton (where we have special DSI transcoders). */
790 enum transcoder cpu_transcoder;
793 * Use reduced/limited/broadcast rbg range, compressing from the full
794 * range fed into the crtcs.
796 bool limited_color_range;
798 /* Bitmask of encoder types (enum intel_output_type)
799 * driven by the pipe.
801 unsigned int output_types;
803 /* Whether we should send NULL infoframes. Required for audio. */
806 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
807 * has_dp_encoder is set. */
811 * Enable dithering, used when the selected pipe bpp doesn't match the
817 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
818 * compliance video pattern tests.
819 * Disable dither only if it is a compliance test request for
822 bool dither_force_disable;
824 /* Controls for the clock computation, to override various stages. */
827 /* SDVO TV has a bunch of special case. To make multifunction encoders
828 * work correctly, we need to track this at runtime.*/
832 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
833 * required. This is set in the 2nd loop of calling encoder's
834 * ->compute_config if the first pick doesn't work out.
838 /* Settings for the intel dpll used on pretty much everything but
842 /* Selected dpll when shared or NULL. */
843 struct intel_shared_dpll *shared_dpll;
845 /* Actual register state of the dpll, for shared dpll cross-checking. */
846 struct intel_dpll_hw_state dpll_hw_state;
848 /* DSI PLL registers */
854 struct intel_link_m_n dp_m_n;
856 /* m2_n2 for eDP downclock */
857 struct intel_link_m_n dp_m2_n2;
864 * Frequence the dpll for the port should run at. Differs from the
865 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
866 * already multiplied by pixel_multiplier.
870 /* Used by SDVO (and if we ever fix it, HDMI). */
871 unsigned pixel_multiplier;
876 * Used by platforms having DP/HDMI PHY with programmable lane
877 * latency optimization.
879 uint8_t lane_lat_optim_mask;
881 /* minimum acceptable voltage level */
882 u8 min_voltage_level;
884 /* Panel fitter controls for gen2-gen4 + VLV */
888 u32 lvds_border_bits;
891 /* Panel fitter placement and size for Ironlake+ */
899 /* FDI configuration, only valid if has_pch_encoder is set. */
901 struct intel_link_m_n fdi_m_n;
904 bool ips_force_disable;
912 struct intel_crtc_scaler_state scaler_state;
914 /* w/a for waiting 2 vblanks during crtc enable */
915 enum pipe hsw_workaround_pipe;
917 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
920 struct intel_crtc_wm_state wm;
922 /* Gamma mode programmed on the pipe */
925 /* bitmask of visible planes (enum plane_id) */
929 /* bitmask of planes that will be updated during the commit */
932 /* HDMI scrambling status */
933 bool hdmi_scrambling;
935 /* HDMI High TMDS char rate ratio */
936 bool hdmi_high_tmds_clock_ratio;
938 /* Output format RGB/YCBCR etc */
939 enum intel_output_format output_format;
941 /* Output down scaling is done in LSPCON device */
942 bool lspcon_downsampling;
946 struct drm_crtc base;
949 * Whether the crtc and the connected output pipeline is active. Implies
950 * that crtc->enabled is set, i.e. the current mode configuration has
951 * some outputs connected to this crtc.
955 unsigned long long enabled_power_domains;
956 struct intel_overlay *overlay;
958 struct intel_crtc_state *config;
960 /* global reset count when the last flip was submitted */
961 unsigned int reset_count;
963 /* Access to these should be protected by dev_priv->irq_lock. */
964 bool cpu_fifo_underrun_disabled;
965 bool pch_fifo_underrun_disabled;
967 /* per-pipe watermark state */
969 /* watermarks currently being used */
971 struct intel_pipe_wm ilk;
972 struct vlv_wm_state vlv;
973 struct g4x_wm_state g4x;
980 unsigned start_vbl_count;
981 ktime_t start_vbl_time;
982 int min_vbl, max_vbl;
986 /* scalers available on this crtc */
991 struct drm_plane base;
992 enum i9xx_plane_id i9xx_plane;
997 uint32_t frontbuffer_bit;
1000 u32 base, cntl, size;
1004 * NOTE: Do not place new plane state fields here (e.g., when adding
1005 * new plane properties). New runtime state should now be placed in
1006 * the intel_plane_state structure and accessed via plane_state.
1009 unsigned int (*max_stride)(struct intel_plane *plane,
1010 u32 pixel_format, u64 modifier,
1011 unsigned int rotation);
1012 void (*update_plane)(struct intel_plane *plane,
1013 const struct intel_crtc_state *crtc_state,
1014 const struct intel_plane_state *plane_state);
1015 void (*update_slave)(struct intel_plane *plane,
1016 const struct intel_crtc_state *crtc_state,
1017 const struct intel_plane_state *plane_state);
1018 void (*disable_plane)(struct intel_plane *plane,
1019 struct intel_crtc *crtc);
1020 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1021 int (*check_plane)(struct intel_crtc_state *crtc_state,
1022 struct intel_plane_state *plane_state);
1025 struct intel_watermark_params {
1033 struct cxsr_latency {
1034 bool is_desktop : 1;
1039 u16 display_hpll_disable;
1041 u16 cursor_hpll_disable;
1044 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1045 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1046 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1047 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1048 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1049 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1050 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1051 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1052 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1055 i915_reg_t hdmi_reg;
1058 enum drm_dp_dual_mode_type type;
1063 bool rgb_quant_range_selectable;
1064 struct intel_connector *attached_connector;
1065 struct cec_notifier *cec_notifier;
1068 struct intel_dp_mst_encoder;
1069 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1072 * enum link_m_n_set:
1073 * When platform provides two set of M_N registers for dp, we can
1074 * program them and switch between them incase of DRRS.
1075 * But When only one such register is provided, we have to program the
1076 * required divider value on that registers itself based on the DRRS state.
1078 * M1_N1 : Program dp_m_n on M1_N1 registers
1079 * dp_m2_n2 on M2_N2 registers (If supported)
1081 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1082 * M2_N2 registers are not supported
1086 /* Sets the m1_n1 and m2_n2 */
1091 struct intel_dp_compliance_data {
1093 uint8_t video_pattern;
1094 uint16_t hdisplay, vdisplay;
1098 struct intel_dp_compliance {
1099 unsigned long test_type;
1100 struct intel_dp_compliance_data test_data;
1107 i915_reg_t output_reg;
1115 bool reset_link_params;
1116 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1117 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1118 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1119 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1120 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1123 int num_source_rates;
1124 const int *source_rates;
1125 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1127 int sink_rates[DP_MAX_SUPPORTED_RATES];
1128 bool use_rate_select;
1129 /* intersection of source and sink rates */
1130 int num_common_rates;
1131 int common_rates[DP_MAX_SUPPORTED_RATES];
1132 /* Max lane count for the current link */
1133 int max_link_lane_count;
1134 /* Max rate for the current link */
1136 /* sink or branch descriptor */
1137 struct drm_dp_desc desc;
1138 struct drm_dp_aux aux;
1139 uint8_t train_set[4];
1140 int panel_power_up_delay;
1141 int panel_power_down_delay;
1142 int panel_power_cycle_delay;
1143 int backlight_on_delay;
1144 int backlight_off_delay;
1145 struct delayed_work panel_vdd_work;
1146 bool want_panel_vdd;
1147 unsigned long last_power_on;
1148 unsigned long last_backlight_off;
1149 ktime_t panel_power_off_time;
1151 struct notifier_block edp_notifier;
1154 * Pipe whose power sequencer is currently locked into
1155 * this port. Only relevant on VLV/CHV.
1159 * Pipe currently driving the port. Used for preventing
1160 * the use of the PPS for any pipe currentrly driving
1161 * external DP as that will mess things up on VLV.
1163 enum pipe active_pipe;
1165 * Set if the sequencer may be reset due to a power transition,
1166 * requiring a reinitialization. Only relevant on BXT.
1169 struct edp_power_seq pps_delays;
1171 bool can_mst; /* this port supports mst */
1173 int active_mst_links;
1174 /* connector directly attached - won't be use for modeset in mst world */
1175 struct intel_connector *attached_connector;
1177 /* mst connector list */
1178 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1179 struct drm_dp_mst_topology_mgr mst_mgr;
1181 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1183 * This function returns the value we have to program the AUX_CTL
1184 * register with to kick off an AUX transaction.
1186 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1188 uint32_t aux_clock_divider);
1190 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1191 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1193 /* This is called before a link training is starterd */
1194 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1196 /* Displayport compliance testing */
1197 struct intel_dp_compliance compliance;
1200 enum lspcon_vendor {
1202 LSPCON_VENDOR_PARADE
1205 struct intel_lspcon {
1207 enum drm_lspcon_mode mode;
1208 enum lspcon_vendor vendor;
1211 struct intel_digital_port {
1212 struct intel_encoder base;
1213 u32 saved_port_bits;
1215 struct intel_hdmi hdmi;
1216 struct intel_lspcon lspcon;
1217 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1218 bool release_cl2_override;
1220 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1222 enum intel_display_power_domain ddi_io_power_domain;
1223 enum tc_port_type tc_type;
1225 void (*write_infoframe)(struct intel_encoder *encoder,
1226 const struct intel_crtc_state *crtc_state,
1228 const void *frame, ssize_t len);
1229 void (*set_infoframes)(struct intel_encoder *encoder,
1231 const struct intel_crtc_state *crtc_state,
1232 const struct drm_connector_state *conn_state);
1233 bool (*infoframe_enabled)(struct intel_encoder *encoder,
1234 const struct intel_crtc_state *pipe_config);
1237 struct intel_dp_mst_encoder {
1238 struct intel_encoder base;
1240 struct intel_digital_port *primary;
1241 struct intel_connector *connector;
1244 static inline enum dpio_channel
1245 vlv_dport_to_channel(struct intel_digital_port *dport)
1247 switch (dport->base.port) {
1258 static inline enum dpio_phy
1259 vlv_dport_to_phy(struct intel_digital_port *dport)
1261 switch (dport->base.port) {
1272 static inline enum dpio_channel
1273 vlv_pipe_to_channel(enum pipe pipe)
1286 static inline struct intel_crtc *
1287 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1289 return dev_priv->pipe_to_crtc_mapping[pipe];
1292 static inline struct intel_crtc *
1293 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1295 return dev_priv->plane_to_crtc_mapping[plane];
1298 struct intel_load_detect_pipe {
1299 struct drm_atomic_state *restore_state;
1302 static inline struct intel_encoder *
1303 intel_attached_encoder(struct drm_connector *connector)
1305 return to_intel_connector(connector)->encoder;
1308 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1310 switch (encoder->type) {
1311 case INTEL_OUTPUT_DDI:
1312 case INTEL_OUTPUT_DP:
1313 case INTEL_OUTPUT_EDP:
1314 case INTEL_OUTPUT_HDMI:
1321 static inline struct intel_digital_port *
1322 enc_to_dig_port(struct drm_encoder *encoder)
1324 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1326 if (intel_encoder_is_dig_port(intel_encoder))
1327 return container_of(encoder, struct intel_digital_port,
1333 static inline struct intel_digital_port *
1334 conn_to_dig_port(struct intel_connector *connector)
1336 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1339 static inline struct intel_dp_mst_encoder *
1340 enc_to_mst(struct drm_encoder *encoder)
1342 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1345 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1347 return &enc_to_dig_port(encoder)->dp;
1350 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1352 switch (encoder->type) {
1353 case INTEL_OUTPUT_DP:
1354 case INTEL_OUTPUT_EDP:
1356 case INTEL_OUTPUT_DDI:
1357 /* Skip pure HDMI/DVI DDI encoders */
1358 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1364 static inline struct intel_lspcon *
1365 enc_to_intel_lspcon(struct drm_encoder *encoder)
1367 return &enc_to_dig_port(encoder)->lspcon;
1370 static inline struct intel_digital_port *
1371 dp_to_dig_port(struct intel_dp *intel_dp)
1373 return container_of(intel_dp, struct intel_digital_port, dp);
1376 static inline struct intel_lspcon *
1377 dp_to_lspcon(struct intel_dp *intel_dp)
1379 return &dp_to_dig_port(intel_dp)->lspcon;
1382 static inline struct drm_i915_private *
1383 dp_to_i915(struct intel_dp *intel_dp)
1385 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1388 static inline struct intel_digital_port *
1389 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1391 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1394 static inline struct intel_plane_state *
1395 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1396 struct intel_plane *plane)
1398 struct drm_plane_state *ret =
1399 drm_atomic_get_plane_state(&state->base, &plane->base);
1402 return ERR_CAST(ret);
1404 return to_intel_plane_state(ret);
1407 static inline struct intel_plane_state *
1408 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1409 struct intel_plane *plane)
1411 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1415 static inline struct intel_plane_state *
1416 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1417 struct intel_plane *plane)
1419 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1423 static inline struct intel_crtc_state *
1424 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1425 struct intel_crtc *crtc)
1427 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1431 static inline struct intel_crtc_state *
1432 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1433 struct intel_crtc *crtc)
1435 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1439 /* intel_fifo_underrun.c */
1440 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1441 enum pipe pipe, bool enable);
1442 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1443 enum pipe pch_transcoder,
1445 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1447 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1448 enum pipe pch_transcoder);
1449 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1450 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1453 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1454 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1455 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1456 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1457 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1458 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1459 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1460 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1462 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1465 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1468 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1469 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1470 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1473 * We only use drm_irq_uninstall() at unload and VT switch, so
1474 * this is the only thing we need to check.
1476 return dev_priv->runtime_pm.irqs_enabled;
1479 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1480 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1482 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1484 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1485 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1486 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1489 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1490 i915_reg_t adpa_reg, enum pipe *pipe);
1491 void intel_crt_init(struct drm_i915_private *dev_priv);
1492 void intel_crt_reset(struct drm_encoder *encoder);
1495 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1496 const struct intel_crtc_state *old_crtc_state,
1497 const struct drm_connector_state *old_conn_state);
1498 void hsw_fdi_link_train(struct intel_crtc *crtc,
1499 const struct intel_crtc_state *crtc_state);
1500 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1501 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1502 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1503 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1504 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1505 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1506 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1507 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1508 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1509 void intel_ddi_get_config(struct intel_encoder *encoder,
1510 struct intel_crtc_state *pipe_config);
1512 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1514 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1515 struct intel_crtc_state *crtc_state);
1516 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1517 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1518 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1519 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1521 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1523 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1524 struct intel_crtc_state *crtc_state,
1525 struct drm_atomic_state *old_state);
1526 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1527 struct intel_crtc_state *crtc_state,
1528 struct drm_atomic_state *old_state);
1529 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1531 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1532 int color_plane, unsigned int height);
1535 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1536 void intel_audio_codec_enable(struct intel_encoder *encoder,
1537 const struct intel_crtc_state *crtc_state,
1538 const struct drm_connector_state *conn_state);
1539 void intel_audio_codec_disable(struct intel_encoder *encoder,
1540 const struct intel_crtc_state *old_crtc_state,
1541 const struct drm_connector_state *old_conn_state);
1542 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1543 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1544 void intel_audio_init(struct drm_i915_private *dev_priv);
1545 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1548 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1549 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1550 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1551 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1552 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1553 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1554 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1555 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1556 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1557 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1558 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1559 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1560 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1561 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1562 const struct intel_cdclk_state *b);
1563 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1564 const struct intel_cdclk_state *b);
1565 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1566 const struct intel_cdclk_state *cdclk_state);
1567 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1568 const char *context);
1570 /* intel_display.c */
1571 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1572 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1573 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1574 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1575 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1576 const char *name, u32 reg, int ref_freq);
1577 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1578 const char *name, u32 reg);
1579 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1580 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1581 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1582 unsigned int intel_fb_xy_to_linear(int x, int y,
1583 const struct intel_plane_state *state,
1585 void intel_add_fb_offsets(int *x, int *y,
1586 const struct intel_plane_state *state, int plane);
1587 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1588 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1589 void intel_mark_busy(struct drm_i915_private *dev_priv);
1590 void intel_mark_idle(struct drm_i915_private *dev_priv);
1591 int intel_display_suspend(struct drm_device *dev);
1592 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1593 void intel_encoder_destroy(struct drm_encoder *encoder);
1594 struct drm_display_mode *
1595 intel_encoder_current_mode(struct intel_encoder *encoder);
1596 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1597 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1598 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1600 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1601 struct drm_file *file_priv);
1602 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1605 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1606 enum intel_output_type type)
1608 return crtc_state->output_types & (1 << type);
1611 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1613 return crtc_state->output_types &
1614 ((1 << INTEL_OUTPUT_DP) |
1615 (1 << INTEL_OUTPUT_DP_MST) |
1616 (1 << INTEL_OUTPUT_EDP));
1619 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1621 drm_wait_one_vblank(&dev_priv->drm, pipe);
1624 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1626 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1629 intel_wait_for_vblank(dev_priv, pipe);
1632 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1634 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1635 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1636 struct intel_digital_port *dport,
1637 unsigned int expected_mask);
1638 int intel_get_load_detect_pipe(struct drm_connector *connector,
1639 const struct drm_display_mode *mode,
1640 struct intel_load_detect_pipe *old,
1641 struct drm_modeset_acquire_ctx *ctx);
1642 void intel_release_load_detect_pipe(struct drm_connector *connector,
1643 struct intel_load_detect_pipe *old,
1644 struct drm_modeset_acquire_ctx *ctx);
1646 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1647 const struct i915_ggtt_view *view,
1649 unsigned long *out_flags);
1650 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1651 struct drm_framebuffer *
1652 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1653 struct drm_mode_fb_cmd2 *mode_cmd);
1654 int intel_prepare_plane_fb(struct drm_plane *plane,
1655 struct drm_plane_state *new_state);
1656 void intel_cleanup_plane_fb(struct drm_plane *plane,
1657 struct drm_plane_state *old_state);
1658 int intel_plane_atomic_get_property(struct drm_plane *plane,
1659 const struct drm_plane_state *state,
1660 struct drm_property *property,
1662 int intel_plane_atomic_set_property(struct drm_plane *plane,
1663 struct drm_plane_state *state,
1664 struct drm_property *property,
1666 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1667 struct drm_crtc_state *crtc_state,
1668 const struct intel_plane_state *old_plane_state,
1669 struct drm_plane_state *plane_state);
1671 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1674 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1675 const struct dpll *dpll);
1676 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1677 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1679 /* modesetting asserts */
1680 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1682 void assert_pll(struct drm_i915_private *dev_priv,
1683 enum pipe pipe, bool state);
1684 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1685 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1686 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1687 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1688 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1689 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1690 enum pipe pipe, bool state);
1691 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1692 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1693 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1694 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1695 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1696 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1697 void intel_finish_reset(struct drm_i915_private *dev_priv);
1698 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1699 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1700 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1701 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1702 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1703 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1704 unsigned int skl_cdclk_get_vco(unsigned int freq);
1705 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1706 void intel_dp_get_m_n(struct intel_crtc *crtc,
1707 struct intel_crtc_state *pipe_config);
1708 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1709 enum link_m_n_set m_n);
1710 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1711 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1712 struct dpll *best_clock);
1713 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1715 bool intel_crtc_active(struct intel_crtc *crtc);
1716 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1717 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1718 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1719 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1720 enum intel_display_power_domain
1721 intel_aux_power_domain(struct intel_digital_port *dig_port);
1722 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1723 struct intel_crtc_state *pipe_config);
1724 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1725 struct intel_crtc_state *crtc_state);
1727 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1728 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1729 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1732 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1734 return i915_ggtt_offset(state->vma);
1737 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1738 const struct intel_plane_state *plane_state);
1739 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1740 const struct intel_plane_state *plane_state);
1741 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1742 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1744 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1745 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1746 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1747 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1748 u32 pixel_format, u64 modifier,
1749 unsigned int rotation);
1751 /* intel_connector.c */
1752 int intel_connector_init(struct intel_connector *connector);
1753 struct intel_connector *intel_connector_alloc(void);
1754 void intel_connector_free(struct intel_connector *connector);
1755 void intel_connector_destroy(struct drm_connector *connector);
1756 int intel_connector_register(struct drm_connector *connector);
1757 void intel_connector_unregister(struct drm_connector *connector);
1758 void intel_connector_attach_encoder(struct intel_connector *connector,
1759 struct intel_encoder *encoder);
1760 bool intel_connector_get_hw_state(struct intel_connector *connector);
1761 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1762 int intel_connector_update_modes(struct drm_connector *connector,
1764 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1765 void intel_attach_force_audio_property(struct drm_connector *connector);
1766 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1767 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1770 void intel_csr_ucode_init(struct drm_i915_private *);
1771 void intel_csr_load_program(struct drm_i915_private *);
1772 void intel_csr_ucode_fini(struct drm_i915_private *);
1773 void intel_csr_ucode_suspend(struct drm_i915_private *);
1774 void intel_csr_ucode_resume(struct drm_i915_private *);
1777 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1778 i915_reg_t dp_reg, enum port port,
1780 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1782 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1783 struct intel_connector *intel_connector);
1784 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1785 int link_rate, uint8_t lane_count,
1787 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1788 int link_rate, uint8_t lane_count);
1789 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1790 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1791 int intel_dp_retrain_link(struct intel_encoder *encoder,
1792 struct drm_modeset_acquire_ctx *ctx);
1793 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1794 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1795 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1796 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1797 bool intel_dp_compute_config(struct intel_encoder *encoder,
1798 struct intel_crtc_state *pipe_config,
1799 struct drm_connector_state *conn_state);
1800 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1801 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1802 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1804 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1805 const struct drm_connector_state *conn_state);
1806 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1807 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1808 void intel_edp_panel_on(struct intel_dp *intel_dp);
1809 void intel_edp_panel_off(struct intel_dp *intel_dp);
1810 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1811 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1812 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1813 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1814 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1815 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1816 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1817 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1818 void intel_plane_destroy(struct drm_plane *plane);
1819 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1820 const struct intel_crtc_state *crtc_state);
1821 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1822 const struct intel_crtc_state *crtc_state);
1823 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1824 unsigned int frontbuffer_bits);
1825 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1826 unsigned int frontbuffer_bits);
1829 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1830 uint8_t dp_train_pat);
1832 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1833 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1835 intel_dp_voltage_max(struct intel_dp *intel_dp);
1837 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1838 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1839 uint8_t *link_bw, uint8_t *rate_select);
1840 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1841 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1843 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1844 uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
1845 int mode_clock, int mode_hdisplay);
1846 uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1849 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1851 return ~((1 << lane_count) - 1) & 0xf;
1854 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1855 int intel_dp_link_required(int pixel_clock, int bpp);
1856 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1857 bool intel_digital_port_connected(struct intel_encoder *encoder);
1859 /* intel_dp_aux_backlight.c */
1860 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1862 /* intel_dp_mst.c */
1863 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1864 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1866 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1869 void icl_dsi_init(struct drm_i915_private *dev_priv);
1871 /* intel_dsi_dcs_backlight.c */
1872 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1875 void intel_dvo_init(struct drm_i915_private *dev_priv);
1876 /* intel_hotplug.c */
1877 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1878 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1879 struct intel_connector *connector);
1881 /* legacy fbdev emulation in intel_fbdev.c */
1882 #ifdef CONFIG_DRM_FBDEV_EMULATION
1883 extern int intel_fbdev_init(struct drm_device *dev);
1884 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1885 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1886 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1887 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1888 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1889 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1891 static inline int intel_fbdev_init(struct drm_device *dev)
1896 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1900 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1904 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1908 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1912 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1916 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1922 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1923 struct intel_atomic_state *state);
1924 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1925 void intel_fbc_pre_update(struct intel_crtc *crtc,
1926 struct intel_crtc_state *crtc_state,
1927 struct intel_plane_state *plane_state);
1928 void intel_fbc_post_update(struct intel_crtc *crtc);
1929 void intel_fbc_init(struct drm_i915_private *dev_priv);
1930 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1931 void intel_fbc_enable(struct intel_crtc *crtc,
1932 struct intel_crtc_state *crtc_state,
1933 struct intel_plane_state *plane_state);
1934 void intel_fbc_disable(struct intel_crtc *crtc);
1935 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1936 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1937 unsigned int frontbuffer_bits,
1938 enum fb_op_origin origin);
1939 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1940 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1941 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1942 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1943 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1946 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1948 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1949 struct intel_connector *intel_connector);
1950 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1951 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1952 struct intel_crtc_state *pipe_config,
1953 struct drm_connector_state *conn_state);
1954 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1955 struct drm_connector *connector,
1956 bool high_tmds_clock_ratio,
1958 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1959 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1962 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1963 i915_reg_t lvds_reg, enum pipe *pipe);
1964 void intel_lvds_init(struct drm_i915_private *dev_priv);
1965 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1966 bool intel_is_dual_link_lvds(struct drm_device *dev);
1968 /* intel_overlay.c */
1969 void intel_overlay_setup(struct drm_i915_private *dev_priv);
1970 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
1971 int intel_overlay_switch_off(struct intel_overlay *overlay);
1972 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1973 struct drm_file *file_priv);
1974 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1975 struct drm_file *file_priv);
1976 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1980 int intel_panel_init(struct intel_panel *panel,
1981 struct drm_display_mode *fixed_mode,
1982 struct drm_display_mode *downclock_mode);
1983 void intel_panel_fini(struct intel_panel *panel);
1984 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1985 struct drm_display_mode *adjusted_mode);
1986 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1987 struct intel_crtc_state *pipe_config,
1989 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1990 struct intel_crtc_state *pipe_config,
1992 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1993 u32 level, u32 max);
1994 int intel_panel_setup_backlight(struct drm_connector *connector,
1996 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1997 const struct drm_connector_state *conn_state);
1998 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1999 extern struct drm_display_mode *intel_find_panel_downclock(
2000 struct drm_i915_private *dev_priv,
2001 struct drm_display_mode *fixed_mode,
2002 struct drm_connector *connector);
2004 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2005 int intel_backlight_device_register(struct intel_connector *connector);
2006 void intel_backlight_device_unregister(struct intel_connector *connector);
2007 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2008 static inline int intel_backlight_device_register(struct intel_connector *connector)
2012 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2015 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2018 void intel_hdcp_atomic_check(struct drm_connector *connector,
2019 struct drm_connector_state *old_state,
2020 struct drm_connector_state *new_state);
2021 int intel_hdcp_init(struct intel_connector *connector,
2022 const struct intel_hdcp_shim *hdcp_shim);
2023 int intel_hdcp_enable(struct intel_connector *connector);
2024 int intel_hdcp_disable(struct intel_connector *connector);
2025 int intel_hdcp_check_link(struct intel_connector *connector);
2026 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2027 bool intel_hdcp_capable(struct intel_connector *connector);
2030 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2031 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2032 void intel_psr_enable(struct intel_dp *intel_dp,
2033 const struct intel_crtc_state *crtc_state);
2034 void intel_psr_disable(struct intel_dp *intel_dp,
2035 const struct intel_crtc_state *old_crtc_state);
2036 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
2037 struct drm_modeset_acquire_ctx *ctx,
2039 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2040 unsigned frontbuffer_bits,
2041 enum fb_op_origin origin);
2042 void intel_psr_flush(struct drm_i915_private *dev_priv,
2043 unsigned frontbuffer_bits,
2044 enum fb_op_origin origin);
2045 void intel_psr_init(struct drm_i915_private *dev_priv);
2046 void intel_psr_compute_config(struct intel_dp *intel_dp,
2047 struct intel_crtc_state *crtc_state);
2048 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2049 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2050 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2051 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2053 bool intel_psr_enabled(struct intel_dp *intel_dp);
2055 /* intel_quirks.c */
2056 void intel_init_quirks(struct drm_i915_private *dev_priv);
2058 /* intel_runtime_pm.c */
2059 int intel_power_domains_init(struct drm_i915_private *);
2060 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2061 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2062 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2063 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2064 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2065 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2066 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2068 enum i915_drm_suspend_mode {
2069 I915_DRM_SUSPEND_IDLE,
2070 I915_DRM_SUSPEND_MEM,
2071 I915_DRM_SUSPEND_HIBERNATE,
2074 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2075 enum i915_drm_suspend_mode);
2076 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2077 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2078 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2079 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2080 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2082 intel_display_power_domain_str(enum intel_display_power_domain domain);
2084 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2085 enum intel_display_power_domain domain);
2086 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2087 enum intel_display_power_domain domain);
2088 void intel_display_power_get(struct drm_i915_private *dev_priv,
2089 enum intel_display_power_domain domain);
2090 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2091 enum intel_display_power_domain domain);
2092 void intel_display_power_put(struct drm_i915_private *dev_priv,
2093 enum intel_display_power_domain domain);
2094 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2098 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2100 WARN_ONCE(dev_priv->runtime_pm.suspended,
2101 "Device suspended during HW access\n");
2105 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2107 assert_rpm_device_not_suspended(dev_priv);
2108 WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2109 "RPM wakelock ref not held during HW access");
2113 * disable_rpm_wakeref_asserts - disable the RPM assert checks
2114 * @dev_priv: i915 device instance
2116 * This function disable asserts that check if we hold an RPM wakelock
2117 * reference, while keeping the device-not-suspended checks still enabled.
2118 * It's meant to be used only in special circumstances where our rule about
2119 * the wakelock refcount wrt. the device power state doesn't hold. According
2120 * to this rule at any point where we access the HW or want to keep the HW in
2121 * an active state we must hold an RPM wakelock reference acquired via one of
2122 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2123 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2124 * forcewake release timer, and the GPU RPS and hangcheck works. All other
2125 * users should avoid using this function.
2127 * Any calls to this function must have a symmetric call to
2128 * enable_rpm_wakeref_asserts().
2131 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2133 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2137 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2138 * @dev_priv: i915 device instance
2140 * This function re-enables the RPM assert checks after disabling them with
2141 * disable_rpm_wakeref_asserts. It's meant to be used only in special
2142 * circumstances otherwise its use should be avoided.
2144 * Any calls to this function must have a symmetric call to
2145 * disable_rpm_wakeref_asserts().
2148 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2150 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2153 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2154 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2155 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2156 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2158 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2159 bool override, unsigned int mask);
2160 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2161 enum dpio_channel ch, bool override);
2165 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2166 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2167 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2168 void intel_update_watermarks(struct intel_crtc *crtc);
2169 void intel_init_pm(struct drm_i915_private *dev_priv);
2170 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2171 void intel_pm_setup(struct drm_i915_private *dev_priv);
2172 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2173 void intel_gpu_ips_teardown(void);
2174 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2175 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2176 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2177 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2178 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2179 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2180 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2181 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2182 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2183 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2184 void g4x_wm_get_hw_state(struct drm_device *dev);
2185 void vlv_wm_get_hw_state(struct drm_device *dev);
2186 void ilk_wm_get_hw_state(struct drm_device *dev);
2187 void skl_wm_get_hw_state(struct drm_device *dev);
2188 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2189 struct skl_ddb_allocation *ddb /* out */);
2190 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2191 struct skl_pipe_wm *out);
2192 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2193 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2194 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2195 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2196 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2197 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2198 const struct skl_wm_level *l2);
2199 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2200 const struct skl_ddb_entry entries[],
2201 int num_entries, int ignore_idx);
2202 bool ilk_disable_lp_wm(struct drm_device *dev);
2203 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2204 struct intel_crtc_state *cstate);
2205 void intel_init_ipc(struct drm_i915_private *dev_priv);
2206 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2209 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2210 i915_reg_t sdvo_reg, enum pipe *pipe);
2211 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2212 i915_reg_t reg, enum port port);
2215 /* intel_sprite.c */
2216 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2218 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2219 enum pipe pipe, int plane);
2220 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *file_priv);
2222 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2223 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2224 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2225 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2226 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2227 struct intel_plane *
2228 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2229 enum pipe pipe, enum plane_id plane_id);
2231 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2233 /* Don't need to do a gen check, these planes are only available on gen11 */
2234 if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2240 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2242 if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2245 return plane->id < PLANE_SPRITE2;
2249 void intel_tv_init(struct drm_i915_private *dev_priv);
2251 /* intel_atomic.c */
2252 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2253 const struct drm_connector_state *state,
2254 struct drm_property *property,
2256 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2257 struct drm_connector_state *state,
2258 struct drm_property *property,
2260 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2261 struct drm_connector_state *new_state);
2262 struct drm_connector_state *
2263 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2265 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2266 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2267 struct drm_crtc_state *state);
2268 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2269 void intel_atomic_state_clear(struct drm_atomic_state *);
2271 static inline struct intel_crtc_state *
2272 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2273 struct intel_crtc *crtc)
2275 struct drm_crtc_state *crtc_state;
2276 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2277 if (IS_ERR(crtc_state))
2278 return ERR_CAST(crtc_state);
2280 return to_intel_crtc_state(crtc_state);
2283 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2284 struct intel_crtc *intel_crtc,
2285 struct intel_crtc_state *crtc_state);
2287 /* intel_atomic_plane.c */
2288 struct intel_plane *intel_plane_alloc(void);
2289 void intel_plane_free(struct intel_plane *plane);
2290 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2291 void intel_plane_destroy_state(struct drm_plane *plane,
2292 struct drm_plane_state *state);
2293 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2294 void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
2295 struct intel_crtc *crtc,
2296 struct intel_crtc_state *old_crtc_state,
2297 struct intel_crtc_state *new_crtc_state);
2298 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2299 struct intel_crtc_state *crtc_state,
2300 const struct intel_plane_state *old_plane_state,
2301 struct intel_plane_state *intel_state);
2304 void intel_color_init(struct drm_crtc *crtc);
2305 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2306 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2307 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2309 /* intel_lspcon.c */
2310 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2311 void lspcon_resume(struct intel_lspcon *lspcon);
2312 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2313 void lspcon_write_infoframe(struct intel_encoder *encoder,
2314 const struct intel_crtc_state *crtc_state,
2316 const void *buf, ssize_t len);
2317 void lspcon_set_infoframes(struct intel_encoder *encoder,
2319 const struct intel_crtc_state *crtc_state,
2320 const struct drm_connector_state *conn_state);
2321 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2322 const struct intel_crtc_state *pipe_config);
2323 void lspcon_ycbcr420_config(struct drm_connector *connector,
2324 struct intel_crtc_state *crtc_state);
2326 /* intel_pipe_crc.c */
2327 #ifdef CONFIG_DEBUG_FS
2328 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2329 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2330 const char *source_name, size_t *values_cnt);
2331 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2333 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2334 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2336 #define intel_crtc_set_crc_source NULL
2337 #define intel_crtc_verify_crc_source NULL
2338 #define intel_crtc_get_crc_sources NULL
2339 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2343 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2347 #endif /* __INTEL_DRV_H__ */