drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42 #include <media/cec-notifier.h>
  43
  44 /**
  45  * __wait_for - magic wait macro
  46  *
  47  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  48  * important that we check the condition again after having timed out, since the
  49  * timeout could be due to preemption or similar and we've never had a chance to
  50  * check the condition before the timeout.
  51  */
  52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  53         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  54         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  55         int ret__;                                                      \
  56         might_sleep();                                                  \
  57         for (;;) {                                                      \
  58                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  59                 OP;                                                     \
  60                 /* Guarantee COND check prior to timeout */             \
  61                 barrier();                                              \
  62                 if (COND) {                                             \
  63                         ret__ = 0;                                      \
  64                         break;                                          \
  65                 }                                                       \
  66                 if (expired__) {                                        \
  67                         ret__ = -ETIMEDOUT;                             \
  68                         break;                                          \
  69                 }                                                       \
  70                 usleep_range(wait__, wait__ * 2);                       \
  71                 if (wait__ < (Wmax))                                    \
  72                         wait__ <<= 1;                                   \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  78                                                    (Wmax))
  79 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  80
  81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  84 #else
  85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  86 #endif
  87
  88 #define _wait_for_atomic(COND, US, ATOMIC) \
  89 ({ \
  90         int cpu, ret, timeout = (US) * 1000; \
  91         u64 base; \
  92         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  93         if (!(ATOMIC)) { \
  94                 preempt_disable(); \
  95                 cpu = smp_processor_id(); \
  96         } \
  97         base = local_clock(); \
  98         for (;;) { \
  99                 u64 now = local_clock(); \
 100                 if (!(ATOMIC)) \
 101                         preempt_enable(); \
 102                 /* Guarantee COND check prior to timeout */ \
 103                 barrier(); \
 104                 if (COND) { \
 105                         ret = 0; \
 106                         break; \
 107                 } \
 108                 if (now - base >= timeout) { \
 109                         ret = -ETIMEDOUT; \
 110                         break; \
 111                 } \
 112                 cpu_relax(); \
 113                 if (!(ATOMIC)) { \
 114                         preempt_disable(); \
 115                         if (unlikely(cpu != smp_processor_id())) { \
 116                                 timeout -= now - base; \
 117                                 cpu = smp_processor_id(); \
 118                                 base = local_clock(); \
 119                         } \
 120                 } \
 121         } \
 122         ret; \
 123 })
 124
 125 #define wait_for_us(COND, US) \
 126 ({ \
 127         int ret__; \
 128         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 129         if ((US) > 10) \
 130                 ret__ = _wait_for((COND), (US), 10, 10); \
 131         else \
 132                 ret__ = _wait_for_atomic((COND), (US), 0); \
 133         ret__; \
 134 })
 135
 136 #define wait_for_atomic_us(COND, US) \
 137 ({ \
 138         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 139         BUILD_BUG_ON((US) > 50000); \
 140         _wait_for_atomic((COND), (US), 1); \
 141 })
 142
 143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 144
 145 #define KHz(x) (1000 * (x))
 146 #define MHz(x) KHz(1000 * (x))
 147
 148 #define KBps(x) (1000 * (x))
 149 #define MBps(x) KBps(1000 * (x))
 150 #define GBps(x) ((u64)1000 * MBps((x)))
 151
 152 /*
 153  * Display related stuff
 154  */
 155
 156 /* store information about an Ixxx DVO */
 157 /* The i830->i865 use multiple DVOs with multiple i2cs */
 158 /* the i915, i945 have a single sDVO i2c bus - which is different */
 159 #define MAX_OUTPUTS 6
 160 /* maximum connectors per crtcs in the mode set */
 161
 162 #define INTEL_I2C_BUS_DVO 1
 163 #define INTEL_I2C_BUS_SDVO 2
 164
 165 /* these are outputs from the chip - integrated only
 166    external chips are via DVO or SDVO output */
 167 enum intel_output_type {
 168         INTEL_OUTPUT_UNUSED = 0,
 169         INTEL_OUTPUT_ANALOG = 1,
 170         INTEL_OUTPUT_DVO = 2,
 171         INTEL_OUTPUT_SDVO = 3,
 172         INTEL_OUTPUT_LVDS = 4,
 173         INTEL_OUTPUT_TVOUT = 5,
 174         INTEL_OUTPUT_HDMI = 6,
 175         INTEL_OUTPUT_DP = 7,
 176         INTEL_OUTPUT_EDP = 8,
 177         INTEL_OUTPUT_DSI = 9,
 178         INTEL_OUTPUT_DDI = 10,
 179         INTEL_OUTPUT_DP_MST = 11,
 180 };
 181
 182 #define INTEL_DVO_CHIP_NONE 0
 183 #define INTEL_DVO_CHIP_LVDS 1
 184 #define INTEL_DVO_CHIP_TMDS 2
 185 #define INTEL_DVO_CHIP_TVOUT 4
 186
 187 #define INTEL_DSI_VIDEO_MODE    0
 188 #define INTEL_DSI_COMMAND_MODE  1
 189
 190 struct intel_framebuffer {
 191         struct drm_framebuffer base;
 192         struct intel_rotation_info rot_info;
 193
 194         /* for each plane in the normal GTT view */
 195         struct {
 196                 unsigned int x, y;
 197         } normal[2];
 198         /* for each plane in the rotated GTT view */
 199         struct {
 200                 unsigned int x, y;
 201                 unsigned int pitch; /* pixels */
 202         } rotated[2];
 203 };
 204
 205 struct intel_fbdev {
 206         struct drm_fb_helper helper;
 207         struct intel_framebuffer *fb;
 208         struct i915_vma *vma;
 209         unsigned long vma_flags;
 210         async_cookie_t cookie;
 211         int preferred_bpp;
 212 };
 213
 214 struct intel_encoder {
 215         struct drm_encoder base;
 216
 217         enum intel_output_type type;
 218         enum port port;
 219         unsigned int cloneable;
 220         bool (*hotplug)(struct intel_encoder *encoder,
 221                         struct intel_connector *connector);
 222         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 223                                                       struct intel_crtc_state *,
 224                                                       struct drm_connector_state *);
 225         bool (*compute_config)(struct intel_encoder *,
 226                                struct intel_crtc_state *,
 227                                struct drm_connector_state *);
 228         void (*pre_pll_enable)(struct intel_encoder *,
 229                                const struct intel_crtc_state *,
 230                                const struct drm_connector_state *);
 231         void (*pre_enable)(struct intel_encoder *,
 232                            const struct intel_crtc_state *,
 233                            const struct drm_connector_state *);
 234         void (*enable)(struct intel_encoder *,
 235                        const struct intel_crtc_state *,
 236                        const struct drm_connector_state *);
 237         void (*disable)(struct intel_encoder *,
 238                         const struct intel_crtc_state *,
 239                         const struct drm_connector_state *);
 240         void (*post_disable)(struct intel_encoder *,
 241                              const struct intel_crtc_state *,
 242                              const struct drm_connector_state *);
 243         void (*post_pll_disable)(struct intel_encoder *,
 244                                  const struct intel_crtc_state *,
 245                                  const struct drm_connector_state *);
 246         /* Read out the current hw state of this connector, returning true if
 247          * the encoder is active. If the encoder is enabled it also set the pipe
 248          * it is connected to in the pipe parameter. */
 249         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 250         /* Reconstructs the equivalent mode flags for the current hardware
 251          * state. This must be called _after_ display->get_pipe_config has
 252          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 253          * be set correctly before calling this function. */
 254         void (*get_config)(struct intel_encoder *,
 255                            struct intel_crtc_state *pipe_config);
 256         /* Returns a mask of power domains that need to be referenced as part
 257          * of the hardware state readout code. */
 258         u64 (*get_power_domains)(struct intel_encoder *encoder,
 259                                  struct intel_crtc_state *crtc_state);
 260         /*
 261          * Called during system suspend after all pending requests for the
 262          * encoder are flushed (for example for DP AUX transactions) and
 263          * device interrupts are disabled.
 264          */
 265         void (*suspend)(struct intel_encoder *);
 266         int crtc_mask;
 267         enum hpd_pin hpd_pin;
 268         enum intel_display_power_domain power_domain;
 269         /* for communication with audio component; protected by av_mutex */
 270         const struct drm_connector *audio_connector;
 271 };
 272
 273 struct intel_panel {
 274         struct drm_display_mode *fixed_mode;
 275         struct drm_display_mode *downclock_mode;
 276
 277         /* backlight */
 278         struct {
 279                 bool present;
 280                 u32 level;
 281                 u32 min;
 282                 u32 max;
 283                 bool enabled;
 284                 bool combination_mode;  /* gen 2/4 only */
 285                 bool active_low_pwm;
 286                 bool alternate_pwm_increment;   /* lpt+ */
 287
 288                 /* PWM chip */
 289                 bool util_pin_active_low;       /* bxt+ */
 290                 u8 controller;          /* bxt+ only */
 291                 struct pwm_device *pwm;
 292
 293                 struct backlight_device *device;
 294
 295                 /* Connector and platform specific backlight functions */
 296                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 297                 uint32_t (*get)(struct intel_connector *connector);
 298                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 299                 void (*disable)(const struct drm_connector_state *conn_state);
 300                 void (*enable)(const struct intel_crtc_state *crtc_state,
 301                                const struct drm_connector_state *conn_state);
 302                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 303                                       uint32_t hz);
 304                 void (*power)(struct intel_connector *, bool enable);
 305         } backlight;
 306 };
 307
 308 struct intel_digital_port;
 309
 310 /*
 311  * This structure serves as a translation layer between the generic HDCP code
 312  * and the bus-specific code. What that means is that HDCP over HDMI differs
 313  * from HDCP over DP, so to account for these differences, we need to
 314  * communicate with the receiver through this shim.
 315  *
 316  * For completeness, the 2 buses differ in the following ways:
 317  *      - DP AUX vs. DDC
 318  *              HDCP registers on the receiver are set via DP AUX for DP, and
 319  *              they are set via DDC for HDMI.
 320  *      - Receiver register offsets
 321  *              The offsets of the registers are different for DP vs. HDMI
 322  *      - Receiver register masks/offsets
 323  *              For instance, the ready bit for the KSV fifo is in a different
 324  *              place on DP vs HDMI
 325  *      - Receiver register names
 326  *              Seriously. In the DP spec, the 16-bit register containing
 327  *              downstream information is called BINFO, on HDMI it's called
 328  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 329  *              with a completely different definition.
 330  *      - KSV FIFO
 331  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 332  *              be read 3 keys at a time
 333  *      - Aksv output
 334  *              Since Aksv is hidden in hardware, there's different procedures
 335  *              to send it over DP AUX vs DDC
 336  */
 337 struct intel_hdcp_shim {
 338         /* Outputs the transmitter's An and Aksv values to the receiver. */
 339         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 340
 341         /* Reads the receiver's key selection vector */
 342         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 343
 344         /*
 345          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 346          * definitions are the same in the respective specs, but the names are
 347          * different. Call it BSTATUS since that's the name the HDMI spec
 348          * uses and it was there first.
 349          */
 350         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 351                             u8 *bstatus);
 352
 353         /* Determines whether a repeater is present downstream */
 354         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 355                                 bool *repeater_present);
 356
 357         /* Reads the receiver's Ri' value */
 358         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 359
 360         /* Determines if the receiver's KSV FIFO is ready for consumption */
 361         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 362                               bool *ksv_ready);
 363
 364         /* Reads the ksv fifo for num_downstream devices */
 365         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 366                              int num_downstream, u8 *ksv_fifo);
 367
 368         /* Reads a 32-bit part of V' from the receiver */
 369         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 370                                  int i, u32 *part);
 371
 372         /* Enables HDCP signalling on the port */
 373         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 374                                  bool enable);
 375
 376         /* Ensures the link is still protected */
 377         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 378
 379         /* Detects panel's hdcp capability. This is optional for HDMI. */
 380         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 381                             bool *hdcp_capable);
 382 };
 383
 384 struct intel_hdcp {
 385         const struct intel_hdcp_shim *shim;
 386         /* Mutex for hdcp state of the connector */
 387         struct mutex mutex;
 388         u64 value;
 389         struct delayed_work check_work;
 390         struct work_struct prop_work;
 391 };
 392
 393 struct intel_connector {
 394         struct drm_connector base;
 395         /*
 396          * The fixed encoder this connector is connected to.
 397          */
 398         struct intel_encoder *encoder;
 399
 400         /* ACPI device id for ACPI and driver cooperation */
 401         u32 acpi_device_id;
 402
 403         /* Reads out the current hw, returning true if the connector is enabled
 404          * and active (i.e. dpms ON state). */
 405         bool (*get_hw_state)(struct intel_connector *);
 406
 407         /* Panel info for eDP and LVDS */
 408         struct intel_panel panel;
 409
 410         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 411         struct edid *edid;
 412         struct edid *detect_edid;
 413
 414         /* since POLL and HPD connectors may use the same HPD line keep the native
 415            state of connector->polled in case hotplug storm detection changes it */
 416         u8 polled;
 417
 418         void *port; /* store this opaque as its illegal to dereference it */
 419
 420         struct intel_dp *mst_port;
 421
 422         /* Work struct to schedule a uevent on link train failure */
 423         struct work_struct modeset_retry_work;
 424
 425         struct intel_hdcp hdcp;
 426 };
 427
 428 struct intel_digital_connector_state {
 429         struct drm_connector_state base;
 430
 431         enum hdmi_force_audio force_audio;
 432         int broadcast_rgb;
 433 };
 434
 435 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 436
 437 struct dpll {
 438         /* given values */
 439         int n;
 440         int m1, m2;
 441         int p1, p2;
 442         /* derived values */
 443         int     dot;
 444         int     vco;
 445         int     m;
 446         int     p;
 447 };
 448
 449 struct intel_atomic_state {
 450         struct drm_atomic_state base;
 451
 452         struct {
 453                 /*
 454                  * Logical state of cdclk (used for all scaling, watermark,
 455                  * etc. calculations and checks). This is computed as if all
 456                  * enabled crtcs were active.
 457                  */
 458                 struct intel_cdclk_state logical;
 459
 460                 /*
 461                  * Actual state of cdclk, can be different from the logical
 462                  * state only when all crtc's are DPMS off.
 463                  */
 464                 struct intel_cdclk_state actual;
 465         } cdclk;
 466
 467         bool dpll_set, modeset;
 468
 469         /*
 470          * Does this transaction change the pipes that are active?  This mask
 471          * tracks which CRTC's have changed their active state at the end of
 472          * the transaction (not counting the temporary disable during modesets).
 473          * This mask should only be non-zero when intel_state->modeset is true,
 474          * but the converse is not necessarily true; simply changing a mode may
 475          * not flip the final active status of any CRTC's
 476          */
 477         unsigned int active_pipe_changes;
 478
 479         unsigned int active_crtcs;
 480         /* minimum acceptable cdclk for each pipe */
 481         int min_cdclk[I915_MAX_PIPES];
 482         /* minimum acceptable voltage level for each pipe */
 483         u8 min_voltage_level[I915_MAX_PIPES];
 484
 485         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 486
 487         /*
 488          * Current watermarks can't be trusted during hardware readout, so
 489          * don't bother calculating intermediate watermarks.
 490          */
 491         bool skip_intermediate_wm;
 492
 493         bool rps_interactive;
 494
 495         /* Gen9+ only */
 496         struct skl_ddb_values wm_results;
 497
 498         struct i915_sw_fence commit_ready;
 499
 500         struct llist_node freed;
 501 };
 502
 503 struct intel_plane_state {
 504         struct drm_plane_state base;
 505         struct i915_ggtt_view view;
 506         struct i915_vma *vma;
 507         unsigned long flags;
 508 #define PLANE_HAS_FENCE BIT(0)
 509
 510         struct {
 511                 u32 offset;
 512                 /*
 513                  * Plane stride in:
 514                  * bytes for 0/180 degree rotation
 515                  * pixels for 90/270 degree rotation
 516                  */
 517                 u32 stride;
 518                 int x, y;
 519         } color_plane[2];
 520
 521         /* plane control register */
 522         u32 ctl;
 523
 524         /* plane color control register */
 525         u32 color_ctl;
 526
 527         /*
 528          * scaler_id
 529          *    = -1 : not using a scaler
 530          *    >=  0 : using a scalers
 531          *
 532          * plane requiring a scaler:
 533          *   - During check_plane, its bit is set in
 534          *     crtc_state->scaler_state.scaler_users by calling helper function
 535          *     update_scaler_plane.
 536          *   - scaler_id indicates the scaler it got assigned.
 537          *
 538          * plane doesn't require a scaler:
 539          *   - this can happen when scaling is no more required or plane simply
 540          *     got disabled.
 541          *   - During check_plane, corresponding bit is reset in
 542          *     crtc_state->scaler_state.scaler_users by calling helper function
 543          *     update_scaler_plane.
 544          */
 545         int scaler_id;
 546
 547         /*
 548          * linked_plane:
 549          *
 550          * ICL planar formats require 2 planes that are updated as pairs.
 551          * This member is used to make sure the other plane is also updated
 552          * when required, and for update_slave() to find the correct
 553          * plane_state to pass as argument.
 554          */
 555         struct intel_plane *linked_plane;
 556
 557         /*
 558          * slave:
 559          * If set don't update use the linked plane's state for updating
 560          * this plane during atomic commit with the update_slave() callback.
 561          *
 562          * It's also used by the watermark code to ignore wm calculations on
 563          * this plane. They're calculated by the linked plane's wm code.
 564          */
 565         u32 slave;
 566
 567         struct drm_intel_sprite_colorkey ckey;
 568 };
 569
 570 struct intel_initial_plane_config {
 571         struct intel_framebuffer *fb;
 572         unsigned int tiling;
 573         int size;
 574         u32 base;
 575 };
 576
 577 #define SKL_MIN_SRC_W 8
 578 #define SKL_MAX_SRC_W 4096
 579 #define SKL_MIN_SRC_H 8
 580 #define SKL_MAX_SRC_H 4096
 581 #define SKL_MIN_DST_W 8
 582 #define SKL_MAX_DST_W 4096
 583 #define SKL_MIN_DST_H 8
 584 #define SKL_MAX_DST_H 4096
 585 #define ICL_MAX_SRC_W 5120
 586 #define ICL_MAX_SRC_H 4096
 587 #define ICL_MAX_DST_W 5120
 588 #define ICL_MAX_DST_H 4096
 589 #define SKL_MIN_YUV_420_SRC_W 16
 590 #define SKL_MIN_YUV_420_SRC_H 16
 591
 592 struct intel_scaler {
 593         int in_use;
 594         uint32_t mode;
 595 };
 596
 597 struct intel_crtc_scaler_state {
 598 #define SKL_NUM_SCALERS 2
 599         struct intel_scaler scalers[SKL_NUM_SCALERS];
 600
 601         /*
 602          * scaler_users: keeps track of users requesting scalers on this crtc.
 603          *
 604          *     If a bit is set, a user is using a scaler.
 605          *     Here user can be a plane or crtc as defined below:
 606          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 607          *       bit 31    - crtc
 608          *
 609          * Instead of creating a new index to cover planes and crtc, using
 610          * existing drm_plane_index for planes which is well less than 31
 611          * planes and bit 31 for crtc. This should be fine to cover all
 612          * our platforms.
 613          *
 614          * intel_atomic_setup_scalers will setup available scalers to users
 615          * requesting scalers. It will gracefully fail if request exceeds
 616          * avilability.
 617          */
 618 #define SKL_CRTC_INDEX 31
 619         unsigned scaler_users;
 620
 621         /* scaler used by crtc for panel fitting purpose */
 622         int scaler_id;
 623 };
 624
 625 /* drm_mode->private_flags */
 626 #define I915_MODE_FLAG_INHERITED 1
 627 /* Flag to get scanline using frame time stamps */
 628 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 629
 630 struct intel_pipe_wm {
 631         struct intel_wm_level wm[5];
 632         uint32_t linetime;
 633         bool fbc_wm_enabled;
 634         bool pipe_enabled;
 635         bool sprites_enabled;
 636         bool sprites_scaled;
 637 };
 638
 639 struct skl_plane_wm {
 640         struct skl_wm_level wm[8];
 641         struct skl_wm_level uv_wm[8];
 642         struct skl_wm_level trans_wm;
 643         bool is_planar;
 644 };
 645
 646 struct skl_pipe_wm {
 647         struct skl_plane_wm planes[I915_MAX_PLANES];
 648         uint32_t linetime;
 649 };
 650
 651 enum vlv_wm_level {
 652         VLV_WM_LEVEL_PM2,
 653         VLV_WM_LEVEL_PM5,
 654         VLV_WM_LEVEL_DDR_DVFS,
 655         NUM_VLV_WM_LEVELS,
 656 };
 657
 658 struct vlv_wm_state {
 659         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 660         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 661         uint8_t num_levels;
 662         bool cxsr;
 663 };
 664
 665 struct vlv_fifo_state {
 666         u16 plane[I915_MAX_PLANES];
 667 };
 668
 669 enum g4x_wm_level {
 670         G4X_WM_LEVEL_NORMAL,
 671         G4X_WM_LEVEL_SR,
 672         G4X_WM_LEVEL_HPLL,
 673         NUM_G4X_WM_LEVELS,
 674 };
 675
 676 struct g4x_wm_state {
 677         struct g4x_pipe_wm wm;
 678         struct g4x_sr_wm sr;
 679         struct g4x_sr_wm hpll;
 680         bool cxsr;
 681         bool hpll_en;
 682         bool fbc_en;
 683 };
 684
 685 struct intel_crtc_wm_state {
 686         union {
 687                 struct {
 688                         /*
 689                          * Intermediate watermarks; these can be
 690                          * programmed immediately since they satisfy
 691                          * both the current configuration we're
 692                          * switching away from and the new
 693                          * configuration we're switching to.
 694                          */
 695                         struct intel_pipe_wm intermediate;
 696
 697                         /*
 698                          * Optimal watermarks, programmed post-vblank
 699                          * when this state is committed.
 700                          */
 701                         struct intel_pipe_wm optimal;
 702                 } ilk;
 703
 704                 struct {
 705                         /* gen9+ only needs 1-step wm programming */
 706                         struct skl_pipe_wm optimal;
 707                         struct skl_ddb_entry ddb;
 708                 } skl;
 709
 710                 struct {
 711                         /* "raw" watermarks (not inverted) */
 712                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 713                         /* intermediate watermarks (inverted) */
 714                         struct vlv_wm_state intermediate;
 715                         /* optimal watermarks (inverted) */
 716                         struct vlv_wm_state optimal;
 717                         /* display FIFO split */
 718                         struct vlv_fifo_state fifo_state;
 719                 } vlv;
 720
 721                 struct {
 722                         /* "raw" watermarks */
 723                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 724                         /* intermediate watermarks */
 725                         struct g4x_wm_state intermediate;
 726                         /* optimal watermarks */
 727                         struct g4x_wm_state optimal;
 728                 } g4x;
 729         };
 730
 731         /*
 732          * Platforms with two-step watermark programming will need to
 733          * update watermark programming post-vblank to switch from the
 734          * safe intermediate watermarks to the optimal final
 735          * watermarks.
 736          */
 737         bool need_postvbl_update;
 738 };
 739
 740 enum intel_output_format {
 741         INTEL_OUTPUT_FORMAT_INVALID,
 742         INTEL_OUTPUT_FORMAT_RGB,
 743         INTEL_OUTPUT_FORMAT_YCBCR420,
 744         INTEL_OUTPUT_FORMAT_YCBCR444,
 745 };
 746
 747 struct intel_crtc_state {
 748         struct drm_crtc_state base;
 749
 750         /**
 751          * quirks - bitfield with hw state readout quirks
 752          *
 753          * For various reasons the hw state readout code might not be able to
 754          * completely faithfully read out the current state. These cases are
 755          * tracked with quirk flags so that fastboot and state checker can act
 756          * accordingly.
 757          */
 758 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 759         unsigned long quirks;
 760
 761         unsigned fb_bits; /* framebuffers to flip */
 762         bool update_pipe; /* can a fast modeset be performed? */
 763         bool disable_cxsr;
 764         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 765         bool fb_changed; /* fb on any of the planes is changed */
 766         bool fifo_changed; /* FIFO split is changed */
 767
 768         /* Pipe source size (ie. panel fitter input size)
 769          * All planes will be positioned inside this space,
 770          * and get clipped at the edges. */
 771         int pipe_src_w, pipe_src_h;
 772
 773         /*
 774          * Pipe pixel rate, adjusted for
 775          * panel fitter/pipe scaler downscaling.
 776          */
 777         unsigned int pixel_rate;
 778
 779         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 780          * between pch encoders and cpu encoders. */
 781         bool has_pch_encoder;
 782
 783         /* Are we sending infoframes on the attached port */
 784         bool has_infoframe;
 785
 786         /* CPU Transcoder for the pipe. Currently this can only differ from the
 787          * pipe on Haswell and later (where we have a special eDP transcoder)
 788          * and Broxton (where we have special DSI transcoders). */
 789         enum transcoder cpu_transcoder;
 790
 791         /*
 792          * Use reduced/limited/broadcast rbg range, compressing from the full
 793          * range fed into the crtcs.
 794          */
 795         bool limited_color_range;
 796
 797         /* Bitmask of encoder types (enum intel_output_type)
 798          * driven by the pipe.
 799          */
 800         unsigned int output_types;
 801
 802         /* Whether we should send NULL infoframes. Required for audio. */
 803         bool has_hdmi_sink;
 804
 805         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 806          * has_dp_encoder is set. */
 807         bool has_audio;
 808
 809         /*
 810          * Enable dithering, used when the selected pipe bpp doesn't match the
 811          * plane bpp.
 812          */
 813         bool dither;
 814
 815         /*
 816          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 817          * compliance video pattern tests.
 818          * Disable dither only if it is a compliance test request for
 819          * 18bpp.
 820          */
 821         bool dither_force_disable;
 822
 823         /* Controls for the clock computation, to override various stages. */
 824         bool clock_set;
 825
 826         /* SDVO TV has a bunch of special case. To make multifunction encoders
 827          * work correctly, we need to track this at runtime.*/
 828         bool sdvo_tv_clock;
 829
 830         /*
 831          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 832          * required. This is set in the 2nd loop of calling encoder's
 833          * ->compute_config if the first pick doesn't work out.
 834          */
 835         bool bw_constrained;
 836
 837         /* Settings for the intel dpll used on pretty much everything but
 838          * haswell. */
 839         struct dpll dpll;
 840
 841         /* Selected dpll when shared or NULL. */
 842         struct intel_shared_dpll *shared_dpll;
 843
 844         /* Actual register state of the dpll, for shared dpll cross-checking. */
 845         struct intel_dpll_hw_state dpll_hw_state;
 846
 847         /* DSI PLL registers */
 848         struct {
 849                 u32 ctrl, div;
 850         } dsi_pll;
 851
 852         int pipe_bpp;
 853         struct intel_link_m_n dp_m_n;
 854
 855         /* m2_n2 for eDP downclock */
 856         struct intel_link_m_n dp_m2_n2;
 857         bool has_drrs;
 858
 859         bool has_psr;
 860         bool has_psr2;
 861
 862         /*
 863          * Frequence the dpll for the port should run at. Differs from the
 864          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 865          * already multiplied by pixel_multiplier.
 866          */
 867         int port_clock;
 868
 869         /* Used by SDVO (and if we ever fix it, HDMI). */
 870         unsigned pixel_multiplier;
 871
 872         uint8_t lane_count;
 873
 874         /*
 875          * Used by platforms having DP/HDMI PHY with programmable lane
 876          * latency optimization.
 877          */
 878         uint8_t lane_lat_optim_mask;
 879
 880         /* minimum acceptable voltage level */
 881         u8 min_voltage_level;
 882
 883         /* Panel fitter controls for gen2-gen4 + VLV */
 884         struct {
 885                 u32 control;
 886                 u32 pgm_ratios;
 887                 u32 lvds_border_bits;
 888         } gmch_pfit;
 889
 890         /* Panel fitter placement and size for Ironlake+ */
 891         struct {
 892                 u32 pos;
 893                 u32 size;
 894                 bool enabled;
 895                 bool force_thru;
 896         } pch_pfit;
 897
 898         /* FDI configuration, only valid if has_pch_encoder is set. */
 899         int fdi_lanes;
 900         struct intel_link_m_n fdi_m_n;
 901
 902         bool ips_enabled;
 903         bool ips_force_disable;
 904
 905         bool enable_fbc;
 906
 907         bool double_wide;
 908
 909         int pbn;
 910
 911         struct intel_crtc_scaler_state scaler_state;
 912
 913         /* w/a for waiting 2 vblanks during crtc enable */
 914         enum pipe hsw_workaround_pipe;
 915
 916         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 917         bool disable_lp_wm;
 918
 919         struct intel_crtc_wm_state wm;
 920
 921         /* Gamma mode programmed on the pipe */
 922         uint32_t gamma_mode;
 923
 924         /* bitmask of visible planes (enum plane_id) */
 925         u8 active_planes;
 926         u8 nv12_planes;
 927
 928         /* HDMI scrambling status */
 929         bool hdmi_scrambling;
 930
 931         /* HDMI High TMDS char rate ratio */
 932         bool hdmi_high_tmds_clock_ratio;
 933
 934         /* Output format RGB/YCBCR etc */
 935         enum intel_output_format output_format;
 936
 937         /* Output down scaling is done in LSPCON device */
 938         bool lspcon_downsampling;
 939 };
 940
 941 struct intel_crtc {
 942         struct drm_crtc base;
 943         enum pipe pipe;
 944         /*
 945          * Whether the crtc and the connected output pipeline is active. Implies
 946          * that crtc->enabled is set, i.e. the current mode configuration has
 947          * some outputs connected to this crtc.
 948          */
 949         bool active;
 950         u8 plane_ids_mask;
 951         unsigned long long enabled_power_domains;
 952         struct intel_overlay *overlay;
 953
 954         struct intel_crtc_state *config;
 955
 956         /* global reset count when the last flip was submitted */
 957         unsigned int reset_count;
 958
 959         /* Access to these should be protected by dev_priv->irq_lock. */
 960         bool cpu_fifo_underrun_disabled;
 961         bool pch_fifo_underrun_disabled;
 962
 963         /* per-pipe watermark state */
 964         struct {
 965                 /* watermarks currently being used  */
 966                 union {
 967                         struct intel_pipe_wm ilk;
 968                         struct vlv_wm_state vlv;
 969                         struct g4x_wm_state g4x;
 970                 } active;
 971         } wm;
 972
 973         int scanline_offset;
 974
 975         struct {
 976                 unsigned start_vbl_count;
 977                 ktime_t start_vbl_time;
 978                 int min_vbl, max_vbl;
 979                 int scanline_start;
 980         } debug;
 981
 982         /* scalers available on this crtc */
 983         int num_scalers;
 984 };
 985
 986 struct intel_plane {
 987         struct drm_plane base;
 988         enum i9xx_plane_id i9xx_plane;
 989         enum plane_id id;
 990         enum pipe pipe;
 991         bool has_fbc;
 992         bool has_ccs;
 993         uint32_t frontbuffer_bit;
 994
 995         struct {
 996                 u32 base, cntl, size;
 997         } cursor;
 998
 999         /*
1000          * NOTE: Do not place new plane state fields here (e.g., when adding
1001          * new plane properties).  New runtime state should now be placed in
1002          * the intel_plane_state structure and accessed via plane_state.
1003          */
1004
1005         unsigned int (*max_stride)(struct intel_plane *plane,
1006                                    u32 pixel_format, u64 modifier,
1007                                    unsigned int rotation);
1008         void (*update_plane)(struct intel_plane *plane,
1009                              const struct intel_crtc_state *crtc_state,
1010                              const struct intel_plane_state *plane_state);
1011         void (*update_slave)(struct intel_plane *plane,
1012                              const struct intel_crtc_state *crtc_state,
1013                              const struct intel_plane_state *plane_state);
1014         void (*disable_plane)(struct intel_plane *plane,
1015                               struct intel_crtc *crtc);
1016         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1017         int (*check_plane)(struct intel_crtc_state *crtc_state,
1018                            struct intel_plane_state *plane_state);
1019 };
1020
1021 struct intel_watermark_params {
1022         u16 fifo_size;
1023         u16 max_wm;
1024         u8 default_wm;
1025         u8 guard_size;
1026         u8 cacheline_size;
1027 };
1028
1029 struct cxsr_latency {
1030         bool is_desktop : 1;
1031         bool is_ddr3 : 1;
1032         u16 fsb_freq;
1033         u16 mem_freq;
1034         u16 display_sr;
1035         u16 display_hpll_disable;
1036         u16 cursor_sr;
1037         u16 cursor_hpll_disable;
1038 };
1039
1040 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1041 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1042 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1043 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1044 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1045 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1046 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1047 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1048 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1049
1050 struct intel_hdmi {
1051         i915_reg_t hdmi_reg;
1052         int ddc_bus;
1053         struct {
1054                 enum drm_dp_dual_mode_type type;
1055                 int max_tmds_clock;
1056         } dp_dual_mode;
1057         bool has_hdmi_sink;
1058         bool has_audio;
1059         bool rgb_quant_range_selectable;
1060         struct intel_connector *attached_connector;
1061         struct cec_notifier *cec_notifier;
1062 };
1063
1064 struct intel_dp_mst_encoder;
1065 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1066
1067 /*
1068  * enum link_m_n_set:
1069  *      When platform provides two set of M_N registers for dp, we can
1070  *      program them and switch between them incase of DRRS.
1071  *      But When only one such register is provided, we have to program the
1072  *      required divider value on that registers itself based on the DRRS state.
1073  *
1074  * M1_N1        : Program dp_m_n on M1_N1 registers
1075  *                        dp_m2_n2 on M2_N2 registers (If supported)
1076  *
1077  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1078  *                        M2_N2 registers are not supported
1079  */
1080
1081 enum link_m_n_set {
1082         /* Sets the m1_n1 and m2_n2 */
1083         M1_N1 = 0,
1084         M2_N2
1085 };
1086
1087 struct intel_dp_compliance_data {
1088         unsigned long edid;
1089         uint8_t video_pattern;
1090         uint16_t hdisplay, vdisplay;
1091         uint8_t bpc;
1092 };
1093
1094 struct intel_dp_compliance {
1095         unsigned long test_type;
1096         struct intel_dp_compliance_data test_data;
1097         bool test_active;
1098         int test_link_rate;
1099         u8 test_lane_count;
1100 };
1101
1102 struct intel_dp {
1103         i915_reg_t output_reg;
1104         uint32_t DP;
1105         int link_rate;
1106         uint8_t lane_count;
1107         uint8_t sink_count;
1108         bool link_mst;
1109         bool link_trained;
1110         bool has_audio;
1111         bool reset_link_params;
1112         enum aux_ch aux_ch;
1113         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1114         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1115         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1116         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1117         /* source rates */
1118         int num_source_rates;
1119         const int *source_rates;
1120         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1121         int num_sink_rates;
1122         int sink_rates[DP_MAX_SUPPORTED_RATES];
1123         bool use_rate_select;
1124         /* intersection of source and sink rates */
1125         int num_common_rates;
1126         int common_rates[DP_MAX_SUPPORTED_RATES];
1127         /* Max lane count for the current link */
1128         int max_link_lane_count;
1129         /* Max rate for the current link */
1130         int max_link_rate;
1131         /* sink or branch descriptor */
1132         struct drm_dp_desc desc;
1133         struct drm_dp_aux aux;
1134         enum intel_display_power_domain aux_power_domain;
1135         uint8_t train_set[4];
1136         int panel_power_up_delay;
1137         int panel_power_down_delay;
1138         int panel_power_cycle_delay;
1139         int backlight_on_delay;
1140         int backlight_off_delay;
1141         struct delayed_work panel_vdd_work;
1142         bool want_panel_vdd;
1143         unsigned long last_power_on;
1144         unsigned long last_backlight_off;
1145         ktime_t panel_power_off_time;
1146
1147         struct notifier_block edp_notifier;
1148
1149         /*
1150          * Pipe whose power sequencer is currently locked into
1151          * this port. Only relevant on VLV/CHV.
1152          */
1153         enum pipe pps_pipe;
1154         /*
1155          * Pipe currently driving the port. Used for preventing
1156          * the use of the PPS for any pipe currentrly driving
1157          * external DP as that will mess things up on VLV.
1158          */
1159         enum pipe active_pipe;
1160         /*
1161          * Set if the sequencer may be reset due to a power transition,
1162          * requiring a reinitialization. Only relevant on BXT.
1163          */
1164         bool pps_reset;
1165         struct edp_power_seq pps_delays;
1166
1167         bool can_mst; /* this port supports mst */
1168         bool is_mst;
1169         int active_mst_links;
1170         /* connector directly attached - won't be use for modeset in mst world */
1171         struct intel_connector *attached_connector;
1172
1173         /* mst connector list */
1174         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1175         struct drm_dp_mst_topology_mgr mst_mgr;
1176
1177         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1178         /*
1179          * This function returns the value we have to program the AUX_CTL
1180          * register with to kick off an AUX transaction.
1181          */
1182         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1183                                      int send_bytes,
1184                                      uint32_t aux_clock_divider);
1185
1186         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1187         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1188
1189         /* This is called before a link training is starterd */
1190         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1191
1192         /* Displayport compliance testing */
1193         struct intel_dp_compliance compliance;
1194 };
1195
1196 enum lspcon_vendor {
1197         LSPCON_VENDOR_MCA,
1198         LSPCON_VENDOR_PARADE
1199 };
1200
1201 struct intel_lspcon {
1202         bool active;
1203         enum drm_lspcon_mode mode;
1204         enum lspcon_vendor vendor;
1205 };
1206
1207 struct intel_digital_port {
1208         struct intel_encoder base;
1209         u32 saved_port_bits;
1210         struct intel_dp dp;
1211         struct intel_hdmi hdmi;
1212         struct intel_lspcon lspcon;
1213         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1214         bool release_cl2_override;
1215         uint8_t max_lanes;
1216         enum intel_display_power_domain ddi_io_power_domain;
1217         enum tc_port_type tc_type;
1218
1219         void (*write_infoframe)(struct intel_encoder *encoder,
1220                                 const struct intel_crtc_state *crtc_state,
1221                                 unsigned int type,
1222                                 const void *frame, ssize_t len);
1223         void (*set_infoframes)(struct intel_encoder *encoder,
1224                                bool enable,
1225                                const struct intel_crtc_state *crtc_state,
1226                                const struct drm_connector_state *conn_state);
1227         bool (*infoframe_enabled)(struct intel_encoder *encoder,
1228                                   const struct intel_crtc_state *pipe_config);
1229 };
1230
1231 struct intel_dp_mst_encoder {
1232         struct intel_encoder base;
1233         enum pipe pipe;
1234         struct intel_digital_port *primary;
1235         struct intel_connector *connector;
1236 };
1237
1238 static inline enum dpio_channel
1239 vlv_dport_to_channel(struct intel_digital_port *dport)
1240 {
1241         switch (dport->base.port) {
1242         case PORT_B:
1243         case PORT_D:
1244                 return DPIO_CH0;
1245         case PORT_C:
1246                 return DPIO_CH1;
1247         default:
1248                 BUG();
1249         }
1250 }
1251
1252 static inline enum dpio_phy
1253 vlv_dport_to_phy(struct intel_digital_port *dport)
1254 {
1255         switch (dport->base.port) {
1256         case PORT_B:
1257         case PORT_C:
1258                 return DPIO_PHY0;
1259         case PORT_D:
1260                 return DPIO_PHY1;
1261         default:
1262                 BUG();
1263         }
1264 }
1265
1266 static inline enum dpio_channel
1267 vlv_pipe_to_channel(enum pipe pipe)
1268 {
1269         switch (pipe) {
1270         case PIPE_A:
1271         case PIPE_C:
1272                 return DPIO_CH0;
1273         case PIPE_B:
1274                 return DPIO_CH1;
1275         default:
1276                 BUG();
1277         }
1278 }
1279
1280 static inline struct intel_crtc *
1281 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1282 {
1283         return dev_priv->pipe_to_crtc_mapping[pipe];
1284 }
1285
1286 static inline struct intel_crtc *
1287 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1288 {
1289         return dev_priv->plane_to_crtc_mapping[plane];
1290 }
1291
1292 struct intel_load_detect_pipe {
1293         struct drm_atomic_state *restore_state;
1294 };
1295
1296 static inline struct intel_encoder *
1297 intel_attached_encoder(struct drm_connector *connector)
1298 {
1299         return to_intel_connector(connector)->encoder;
1300 }
1301
1302 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1303 {
1304         switch (encoder->type) {
1305         case INTEL_OUTPUT_DDI:
1306         case INTEL_OUTPUT_DP:
1307         case INTEL_OUTPUT_EDP:
1308         case INTEL_OUTPUT_HDMI:
1309                 return true;
1310         default:
1311                 return false;
1312         }
1313 }
1314
1315 static inline struct intel_digital_port *
1316 enc_to_dig_port(struct drm_encoder *encoder)
1317 {
1318         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1319
1320         if (intel_encoder_is_dig_port(intel_encoder))
1321                 return container_of(encoder, struct intel_digital_port,
1322                                     base.base);
1323         else
1324                 return NULL;
1325 }
1326
1327 static inline struct intel_digital_port *
1328 conn_to_dig_port(struct intel_connector *connector)
1329 {
1330         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1331 }
1332
1333 static inline struct intel_dp_mst_encoder *
1334 enc_to_mst(struct drm_encoder *encoder)
1335 {
1336         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1337 }
1338
1339 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1340 {
1341         return &enc_to_dig_port(encoder)->dp;
1342 }
1343
1344 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1345 {
1346         switch (encoder->type) {
1347         case INTEL_OUTPUT_DP:
1348         case INTEL_OUTPUT_EDP:
1349                 return true;
1350         case INTEL_OUTPUT_DDI:
1351                 /* Skip pure HDMI/DVI DDI encoders */
1352                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1353         default:
1354                 return false;
1355         }
1356 }
1357
1358 static inline struct intel_lspcon *
1359 enc_to_intel_lspcon(struct drm_encoder *encoder)
1360 {
1361         return &enc_to_dig_port(encoder)->lspcon;
1362 }
1363
1364 static inline struct intel_digital_port *
1365 dp_to_dig_port(struct intel_dp *intel_dp)
1366 {
1367         return container_of(intel_dp, struct intel_digital_port, dp);
1368 }
1369
1370 static inline struct intel_lspcon *
1371 dp_to_lspcon(struct intel_dp *intel_dp)
1372 {
1373         return &dp_to_dig_port(intel_dp)->lspcon;
1374 }
1375
1376 static inline struct drm_i915_private *
1377 dp_to_i915(struct intel_dp *intel_dp)
1378 {
1379         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1380 }
1381
1382 static inline struct intel_digital_port *
1383 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1384 {
1385         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1386 }
1387
1388 static inline struct intel_plane_state *
1389 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1390                                  struct intel_plane *plane)
1391 {
1392         struct drm_plane_state *ret =
1393                 drm_atomic_get_plane_state(&state->base, &plane->base);
1394
1395         if (IS_ERR(ret))
1396                 return ERR_CAST(ret);
1397
1398         return to_intel_plane_state(ret);
1399 }
1400
1401 static inline struct intel_plane_state *
1402 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1403                                  struct intel_plane *plane)
1404 {
1405         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1406                                                                    &plane->base));
1407 }
1408
1409 static inline struct intel_plane_state *
1410 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1411                                  struct intel_plane *plane)
1412 {
1413         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1414                                                                    &plane->base));
1415 }
1416
1417 static inline struct intel_crtc_state *
1418 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1419                                 struct intel_crtc *crtc)
1420 {
1421         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1422                                                                  &crtc->base));
1423 }
1424
1425 static inline struct intel_crtc_state *
1426 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1427                                 struct intel_crtc *crtc)
1428 {
1429         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1430                                                                  &crtc->base));
1431 }
1432
1433 /* intel_fifo_underrun.c */
1434 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1435                                            enum pipe pipe, bool enable);
1436 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1437                                            enum pipe pch_transcoder,
1438                                            bool enable);
1439 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1440                                          enum pipe pipe);
1441 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1442                                          enum pipe pch_transcoder);
1443 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1444 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1445
1446 /* i915_irq.c */
1447 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1448 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1449 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1450 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1451 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1452 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1453 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1454 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1455
1456 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1457                                             u32 mask)
1458 {
1459         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1460 }
1461
1462 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1463 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1464 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1465 {
1466         /*
1467          * We only use drm_irq_uninstall() at unload and VT switch, so
1468          * this is the only thing we need to check.
1469          */
1470         return dev_priv->runtime_pm.irqs_enabled;
1471 }
1472
1473 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1474 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1475                                      u8 pipe_mask);
1476 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1477                                      u8 pipe_mask);
1478 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1479 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1480 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1481
1482 /* intel_crt.c */
1483 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1484                             i915_reg_t adpa_reg, enum pipe *pipe);
1485 void intel_crt_init(struct drm_i915_private *dev_priv);
1486 void intel_crt_reset(struct drm_encoder *encoder);
1487
1488 /* intel_ddi.c */
1489 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1490                                 const struct intel_crtc_state *old_crtc_state,
1491                                 const struct drm_connector_state *old_conn_state);
1492 void hsw_fdi_link_train(struct intel_crtc *crtc,
1493                         const struct intel_crtc_state *crtc_state);
1494 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1495 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1496 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1497 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1498 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1499 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1500 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1501 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1502 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1503 void intel_ddi_get_config(struct intel_encoder *encoder,
1504                           struct intel_crtc_state *pipe_config);
1505
1506 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1507                                     bool state);
1508 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1509                                          struct intel_crtc_state *crtc_state);
1510 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1511 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1512 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1513 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1514                                  u8 voltage_swing);
1515 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1516                                      bool enable);
1517 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1518                            struct intel_crtc_state *crtc_state,
1519                            struct drm_atomic_state *old_state);
1520 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1521                              struct intel_crtc_state *crtc_state,
1522                              struct drm_atomic_state *old_state);
1523
1524 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1525                                    int color_plane, unsigned int height);
1526
1527 /* intel_audio.c */
1528 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1529 void intel_audio_codec_enable(struct intel_encoder *encoder,
1530                               const struct intel_crtc_state *crtc_state,
1531                               const struct drm_connector_state *conn_state);
1532 void intel_audio_codec_disable(struct intel_encoder *encoder,
1533                                const struct intel_crtc_state *old_crtc_state,
1534                                const struct drm_connector_state *old_conn_state);
1535 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1536 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1537 void intel_audio_init(struct drm_i915_private *dev_priv);
1538 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1539
1540 /* intel_cdclk.c */
1541 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1542 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1543 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1544 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1545 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1546 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1547 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1548 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1549 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1550 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1551 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1552 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1553 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1554 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1555                                const struct intel_cdclk_state *b);
1556 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1557                          const struct intel_cdclk_state *b);
1558 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1559                      const struct intel_cdclk_state *cdclk_state);
1560 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1561                             const char *context);
1562
1563 /* intel_display.c */
1564 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1565 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1566 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1567 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1568 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1569                       const char *name, u32 reg, int ref_freq);
1570 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1571                            const char *name, u32 reg);
1572 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1573 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1574 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1575 unsigned int intel_fb_xy_to_linear(int x, int y,
1576                                    const struct intel_plane_state *state,
1577                                    int plane);
1578 void intel_add_fb_offsets(int *x, int *y,
1579                           const struct intel_plane_state *state, int plane);
1580 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1581 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1582 void intel_mark_busy(struct drm_i915_private *dev_priv);
1583 void intel_mark_idle(struct drm_i915_private *dev_priv);
1584 int intel_display_suspend(struct drm_device *dev);
1585 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1586 void intel_encoder_destroy(struct drm_encoder *encoder);
1587 struct drm_display_mode *
1588 intel_encoder_current_mode(struct intel_encoder *encoder);
1589 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1590 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1591 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1592                               enum port port);
1593 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1594                                       struct drm_file *file_priv);
1595 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1596                                              enum pipe pipe);
1597 static inline bool
1598 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1599                     enum intel_output_type type)
1600 {
1601         return crtc_state->output_types & (1 << type);
1602 }
1603 static inline bool
1604 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1605 {
1606         return crtc_state->output_types &
1607                 ((1 << INTEL_OUTPUT_DP) |
1608                  (1 << INTEL_OUTPUT_DP_MST) |
1609                  (1 << INTEL_OUTPUT_EDP));
1610 }
1611 static inline void
1612 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1613 {
1614         drm_wait_one_vblank(&dev_priv->drm, pipe);
1615 }
1616 static inline void
1617 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1618 {
1619         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1620
1621         if (crtc->active)
1622                 intel_wait_for_vblank(dev_priv, pipe);
1623 }
1624
1625 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1626
1627 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1628 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1629                          struct intel_digital_port *dport,
1630                          unsigned int expected_mask);
1631 int intel_get_load_detect_pipe(struct drm_connector *connector,
1632                                const struct drm_display_mode *mode,
1633                                struct intel_load_detect_pipe *old,
1634                                struct drm_modeset_acquire_ctx *ctx);
1635 void intel_release_load_detect_pipe(struct drm_connector *connector,
1636                                     struct intel_load_detect_pipe *old,
1637                                     struct drm_modeset_acquire_ctx *ctx);
1638 struct i915_vma *
1639 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1640                            const struct i915_ggtt_view *view,
1641                            bool uses_fence,
1642                            unsigned long *out_flags);
1643 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1644 struct drm_framebuffer *
1645 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1646                          struct drm_mode_fb_cmd2 *mode_cmd);
1647 int intel_prepare_plane_fb(struct drm_plane *plane,
1648                            struct drm_plane_state *new_state);
1649 void intel_cleanup_plane_fb(struct drm_plane *plane,
1650                             struct drm_plane_state *old_state);
1651 int intel_plane_atomic_get_property(struct drm_plane *plane,
1652                                     const struct drm_plane_state *state,
1653                                     struct drm_property *property,
1654                                     uint64_t *val);
1655 int intel_plane_atomic_set_property(struct drm_plane *plane,
1656                                     struct drm_plane_state *state,
1657                                     struct drm_property *property,
1658                                     uint64_t val);
1659 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1660                                     struct drm_crtc_state *crtc_state,
1661                                     const struct intel_plane_state *old_plane_state,
1662                                     struct drm_plane_state *plane_state);
1663
1664 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1665                                     enum pipe pipe);
1666
1667 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1668                      const struct dpll *dpll);
1669 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1670 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1671
1672 /* modesetting asserts */
1673 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1674                            enum pipe pipe);
1675 void assert_pll(struct drm_i915_private *dev_priv,
1676                 enum pipe pipe, bool state);
1677 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1678 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1679 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1680 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1681 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1682 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1683                        enum pipe pipe, bool state);
1684 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1685 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1686 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1687 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1688 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1689 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1690 void intel_finish_reset(struct drm_i915_private *dev_priv);
1691 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1692 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1693 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1694 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1695 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1696 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1697 unsigned int skl_cdclk_get_vco(unsigned int freq);
1698 void intel_dp_get_m_n(struct intel_crtc *crtc,
1699                       struct intel_crtc_state *pipe_config);
1700 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1701                       enum link_m_n_set m_n);
1702 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1703 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1704                         struct dpll *best_clock);
1705 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1706
1707 bool intel_crtc_active(struct intel_crtc *crtc);
1708 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1709 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1710 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1711 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1712 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1713                                  struct intel_crtc_state *pipe_config);
1714 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1715                                   struct intel_crtc_state *crtc_state);
1716
1717 u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1718 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1719 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1720                   u32 pixel_format);
1721
1722 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1723 {
1724         return i915_ggtt_offset(state->vma);
1725 }
1726
1727 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1728                         const struct intel_plane_state *plane_state);
1729 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1730                   const struct intel_plane_state *plane_state);
1731 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1732 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1733                      int plane);
1734 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1735 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1736 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1737 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1738                                    u32 pixel_format, u64 modifier,
1739                                    unsigned int rotation);
1740
1741 /* intel_connector.c */
1742 int intel_connector_init(struct intel_connector *connector);
1743 struct intel_connector *intel_connector_alloc(void);
1744 void intel_connector_free(struct intel_connector *connector);
1745 void intel_connector_destroy(struct drm_connector *connector);
1746 int intel_connector_register(struct drm_connector *connector);
1747 void intel_connector_unregister(struct drm_connector *connector);
1748 void intel_connector_attach_encoder(struct intel_connector *connector,
1749                                     struct intel_encoder *encoder);
1750 bool intel_connector_get_hw_state(struct intel_connector *connector);
1751 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1752 int intel_connector_update_modes(struct drm_connector *connector,
1753                                  struct edid *edid);
1754 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1755 void intel_attach_force_audio_property(struct drm_connector *connector);
1756 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1757 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1758
1759 /* intel_csr.c */
1760 void intel_csr_ucode_init(struct drm_i915_private *);
1761 void intel_csr_load_program(struct drm_i915_private *);
1762 void intel_csr_ucode_fini(struct drm_i915_private *);
1763 void intel_csr_ucode_suspend(struct drm_i915_private *);
1764 void intel_csr_ucode_resume(struct drm_i915_private *);
1765
1766 /* intel_dp.c */
1767 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1768                            i915_reg_t dp_reg, enum port port,
1769                            enum pipe *pipe);
1770 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1771                    enum port port);
1772 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1773                              struct intel_connector *intel_connector);
1774 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1775                               int link_rate, uint8_t lane_count,
1776                               bool link_mst);
1777 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1778                                             int link_rate, uint8_t lane_count);
1779 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1780 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1781 int intel_dp_retrain_link(struct intel_encoder *encoder,
1782                           struct drm_modeset_acquire_ctx *ctx);
1783 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1784 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1785 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1786 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1787 bool intel_dp_compute_config(struct intel_encoder *encoder,
1788                              struct intel_crtc_state *pipe_config,
1789                              struct drm_connector_state *conn_state);
1790 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1791 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1792 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1793                                   bool long_hpd);
1794 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1795                             const struct drm_connector_state *conn_state);
1796 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1797 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1798 void intel_edp_panel_on(struct intel_dp *intel_dp);
1799 void intel_edp_panel_off(struct intel_dp *intel_dp);
1800 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1801 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1802 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1803 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1804 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1805 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1806 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1807 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1808 void intel_plane_destroy(struct drm_plane *plane);
1809 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1810                            const struct intel_crtc_state *crtc_state);
1811 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1812                             const struct intel_crtc_state *crtc_state);
1813 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1814                                unsigned int frontbuffer_bits);
1815 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1816                           unsigned int frontbuffer_bits);
1817 void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
1818 void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port);
1819 void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port);
1820
1821 void
1822 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1823                                        uint8_t dp_train_pat);
1824 void
1825 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1826 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1827 uint8_t
1828 intel_dp_voltage_max(struct intel_dp *intel_dp);
1829 uint8_t
1830 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1831 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1832                            uint8_t *link_bw, uint8_t *rate_select);
1833 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1834 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1835 bool
1836 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1837
1838 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1839 {
1840         return ~((1 << lane_count) - 1) & 0xf;
1841 }
1842
1843 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1844 int intel_dp_link_required(int pixel_clock, int bpp);
1845 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1846 bool intel_digital_port_connected(struct intel_encoder *encoder);
1847
1848 /* intel_dp_aux_backlight.c */
1849 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1850
1851 /* intel_dp_mst.c */
1852 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1853 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1854 /* vlv_dsi.c */
1855 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1856
1857 /* intel_dsi_dcs_backlight.c */
1858 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1859
1860 /* intel_dvo.c */
1861 void intel_dvo_init(struct drm_i915_private *dev_priv);
1862 /* intel_hotplug.c */
1863 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1864 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1865                            struct intel_connector *connector);
1866
1867 /* legacy fbdev emulation in intel_fbdev.c */
1868 #ifdef CONFIG_DRM_FBDEV_EMULATION
1869 extern int intel_fbdev_init(struct drm_device *dev);
1870 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1871 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1872 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1873 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1874 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1875 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1876 #else
1877 static inline int intel_fbdev_init(struct drm_device *dev)
1878 {
1879         return 0;
1880 }
1881
1882 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1883 {
1884 }
1885
1886 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1887 {
1888 }
1889
1890 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1891 {
1892 }
1893
1894 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1895 {
1896 }
1897
1898 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1899 {
1900 }
1901
1902 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1903 {
1904 }
1905 #endif
1906
1907 /* intel_fbc.c */
1908 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1909                            struct intel_atomic_state *state);
1910 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1911 void intel_fbc_pre_update(struct intel_crtc *crtc,
1912                           struct intel_crtc_state *crtc_state,
1913                           struct intel_plane_state *plane_state);
1914 void intel_fbc_post_update(struct intel_crtc *crtc);
1915 void intel_fbc_init(struct drm_i915_private *dev_priv);
1916 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1917 void intel_fbc_enable(struct intel_crtc *crtc,
1918                       struct intel_crtc_state *crtc_state,
1919                       struct intel_plane_state *plane_state);
1920 void intel_fbc_disable(struct intel_crtc *crtc);
1921 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1922 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1923                           unsigned int frontbuffer_bits,
1924                           enum fb_op_origin origin);
1925 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1926                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1927 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1928 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1929 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1930
1931 /* intel_hdmi.c */
1932 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1933                      enum port port);
1934 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1935                                struct intel_connector *intel_connector);
1936 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1937 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1938                                struct intel_crtc_state *pipe_config,
1939                                struct drm_connector_state *conn_state);
1940 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1941                                        struct drm_connector *connector,
1942                                        bool high_tmds_clock_ratio,
1943                                        bool scrambling);
1944 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1945 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1946
1947 /* intel_lvds.c */
1948 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1949                              i915_reg_t lvds_reg, enum pipe *pipe);
1950 void intel_lvds_init(struct drm_i915_private *dev_priv);
1951 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1952 bool intel_is_dual_link_lvds(struct drm_device *dev);
1953
1954 /* intel_overlay.c */
1955 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1956 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1957 int intel_overlay_switch_off(struct intel_overlay *overlay);
1958 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1959                                   struct drm_file *file_priv);
1960 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1961                               struct drm_file *file_priv);
1962 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1963
1964
1965 /* intel_panel.c */
1966 int intel_panel_init(struct intel_panel *panel,
1967                      struct drm_display_mode *fixed_mode,
1968                      struct drm_display_mode *downclock_mode);
1969 void intel_panel_fini(struct intel_panel *panel);
1970 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1971                             struct drm_display_mode *adjusted_mode);
1972 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1973                              struct intel_crtc_state *pipe_config,
1974                              int fitting_mode);
1975 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1976                               struct intel_crtc_state *pipe_config,
1977                               int fitting_mode);
1978 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1979                                     u32 level, u32 max);
1980 int intel_panel_setup_backlight(struct drm_connector *connector,
1981                                 enum pipe pipe);
1982 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1983                                   const struct drm_connector_state *conn_state);
1984 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1985 extern struct drm_display_mode *intel_find_panel_downclock(
1986                                 struct drm_i915_private *dev_priv,
1987                                 struct drm_display_mode *fixed_mode,
1988                                 struct drm_connector *connector);
1989
1990 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1991 int intel_backlight_device_register(struct intel_connector *connector);
1992 void intel_backlight_device_unregister(struct intel_connector *connector);
1993 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1994 static inline int intel_backlight_device_register(struct intel_connector *connector)
1995 {
1996         return 0;
1997 }
1998 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1999 {
2000 }
2001 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2002
2003 /* intel_hdcp.c */
2004 void intel_hdcp_atomic_check(struct drm_connector *connector,
2005                              struct drm_connector_state *old_state,
2006                              struct drm_connector_state *new_state);
2007 int intel_hdcp_init(struct intel_connector *connector,
2008                     const struct intel_hdcp_shim *hdcp_shim);
2009 int intel_hdcp_enable(struct intel_connector *connector);
2010 int intel_hdcp_disable(struct intel_connector *connector);
2011 int intel_hdcp_check_link(struct intel_connector *connector);
2012 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2013 bool intel_hdcp_capable(struct intel_connector *connector);
2014
2015 /* intel_psr.c */
2016 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2017 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2018 void intel_psr_enable(struct intel_dp *intel_dp,
2019                       const struct intel_crtc_state *crtc_state);
2020 void intel_psr_disable(struct intel_dp *intel_dp,
2021                       const struct intel_crtc_state *old_crtc_state);
2022 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
2023                                struct drm_modeset_acquire_ctx *ctx,
2024                                u64 value);
2025 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2026                           unsigned frontbuffer_bits,
2027                           enum fb_op_origin origin);
2028 void intel_psr_flush(struct drm_i915_private *dev_priv,
2029                      unsigned frontbuffer_bits,
2030                      enum fb_op_origin origin);
2031 void intel_psr_init(struct drm_i915_private *dev_priv);
2032 void intel_psr_compute_config(struct intel_dp *intel_dp,
2033                               struct intel_crtc_state *crtc_state);
2034 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2035 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2036 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2037 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2038                             u32 *out_value);
2039
2040 /* intel_quirks.c */
2041 void intel_init_quirks(struct drm_i915_private *dev_priv);
2042
2043 /* intel_runtime_pm.c */
2044 int intel_power_domains_init(struct drm_i915_private *);
2045 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2046 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2047 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2048 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2049 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2050
2051 enum i915_drm_suspend_mode {
2052         I915_DRM_SUSPEND_IDLE,
2053         I915_DRM_SUSPEND_MEM,
2054         I915_DRM_SUSPEND_HIBERNATE,
2055 };
2056
2057 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2058                                  enum i915_drm_suspend_mode);
2059 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2060 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2061 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2062 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2063 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2064 const char *
2065 intel_display_power_domain_str(enum intel_display_power_domain domain);
2066
2067 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2068                                     enum intel_display_power_domain domain);
2069 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2070                                       enum intel_display_power_domain domain);
2071 void intel_display_power_get(struct drm_i915_private *dev_priv,
2072                              enum intel_display_power_domain domain);
2073 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2074                                         enum intel_display_power_domain domain);
2075 void intel_display_power_put(struct drm_i915_private *dev_priv,
2076                              enum intel_display_power_domain domain);
2077 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2078                             u8 req_slices);
2079
2080 static inline void
2081 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2082 {
2083         WARN_ONCE(dev_priv->runtime_pm.suspended,
2084                   "Device suspended during HW access\n");
2085 }
2086
2087 static inline void
2088 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2089 {
2090         assert_rpm_device_not_suspended(dev_priv);
2091         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2092                   "RPM wakelock ref not held during HW access");
2093 }
2094
2095 /**
2096  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2097  * @dev_priv: i915 device instance
2098  *
2099  * This function disable asserts that check if we hold an RPM wakelock
2100  * reference, while keeping the device-not-suspended checks still enabled.
2101  * It's meant to be used only in special circumstances where our rule about
2102  * the wakelock refcount wrt. the device power state doesn't hold. According
2103  * to this rule at any point where we access the HW or want to keep the HW in
2104  * an active state we must hold an RPM wakelock reference acquired via one of
2105  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2106  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2107  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2108  * users should avoid using this function.
2109  *
2110  * Any calls to this function must have a symmetric call to
2111  * enable_rpm_wakeref_asserts().
2112  */
2113 static inline void
2114 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2115 {
2116         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2117 }
2118
2119 /**
2120  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2121  * @dev_priv: i915 device instance
2122  *
2123  * This function re-enables the RPM assert checks after disabling them with
2124  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2125  * circumstances otherwise its use should be avoided.
2126  *
2127  * Any calls to this function must have a symmetric call to
2128  * disable_rpm_wakeref_asserts().
2129  */
2130 static inline void
2131 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2132 {
2133         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2134 }
2135
2136 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2137 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2138 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2139 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2140
2141 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2142                              bool override, unsigned int mask);
2143 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2144                           enum dpio_channel ch, bool override);
2145
2146
2147 /* intel_pm.c */
2148 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2149 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2150 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2151 void intel_update_watermarks(struct intel_crtc *crtc);
2152 void intel_init_pm(struct drm_i915_private *dev_priv);
2153 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2154 void intel_pm_setup(struct drm_i915_private *dev_priv);
2155 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2156 void intel_gpu_ips_teardown(void);
2157 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2158 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2159 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2160 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2161 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2162 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2163 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2164 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2165 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2166 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2167 void g4x_wm_get_hw_state(struct drm_device *dev);
2168 void vlv_wm_get_hw_state(struct drm_device *dev);
2169 void ilk_wm_get_hw_state(struct drm_device *dev);
2170 void skl_wm_get_hw_state(struct drm_device *dev);
2171 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2172                           struct skl_ddb_allocation *ddb /* out */);
2173 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2174                               struct skl_pipe_wm *out);
2175 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2176 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2177 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2178 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2179 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2180 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2181                          const struct skl_wm_level *l2);
2182 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2183                                  const struct skl_ddb_entry **entries,
2184                                  const struct skl_ddb_entry *ddb,
2185                                  int ignore);
2186 bool ilk_disable_lp_wm(struct drm_device *dev);
2187 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2188                                   struct intel_crtc_state *cstate);
2189 void intel_init_ipc(struct drm_i915_private *dev_priv);
2190 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2191
2192 /* intel_sdvo.c */
2193 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2194                              i915_reg_t sdvo_reg, enum pipe *pipe);
2195 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2196                      i915_reg_t reg, enum port port);
2197
2198
2199 /* intel_sprite.c */
2200 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2201                              int usecs);
2202 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2203                                               enum pipe pipe, int plane);
2204 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2205                                     struct drm_file *file_priv);
2206 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2207 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2208 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2209 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2210 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2211 struct intel_plane *intel_plane_alloc(void);
2212 void intel_plane_free(struct intel_plane *plane);
2213 struct intel_plane *
2214 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2215                            enum pipe pipe, enum plane_id plane_id);
2216
2217 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2218 {
2219         /* Don't need to do a gen check, these planes are only available on gen11 */
2220         if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2221                 return true;
2222
2223         return false;
2224 }
2225
2226 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2227 {
2228         if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2229                 return false;
2230
2231         return plane->id < PLANE_SPRITE2;
2232 }
2233
2234 /* intel_tv.c */
2235 void intel_tv_init(struct drm_i915_private *dev_priv);
2236
2237 /* intel_atomic.c */
2238 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2239                                                 const struct drm_connector_state *state,
2240                                                 struct drm_property *property,
2241                                                 uint64_t *val);
2242 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2243                                                 struct drm_connector_state *state,
2244                                                 struct drm_property *property,
2245                                                 uint64_t val);
2246 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2247                                          struct drm_connector_state *new_state);
2248 struct drm_connector_state *
2249 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2250
2251 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2252 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2253                                struct drm_crtc_state *state);
2254 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2255 void intel_atomic_state_clear(struct drm_atomic_state *);
2256
2257 static inline struct intel_crtc_state *
2258 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2259                             struct intel_crtc *crtc)
2260 {
2261         struct drm_crtc_state *crtc_state;
2262         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2263         if (IS_ERR(crtc_state))
2264                 return ERR_CAST(crtc_state);
2265
2266         return to_intel_crtc_state(crtc_state);
2267 }
2268
2269 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2270                                struct intel_crtc *intel_crtc,
2271                                struct intel_crtc_state *crtc_state);
2272
2273 /* intel_atomic_plane.c */
2274 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2275 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2276 void intel_plane_destroy_state(struct drm_plane *plane,
2277                                struct drm_plane_state *state);
2278 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2279 void intel_update_planes_on_crtc(struct intel_atomic_state *old_state,
2280                                  struct intel_crtc *crtc,
2281                                  struct intel_crtc_state *old_crtc_state,
2282                                  struct intel_crtc_state *new_crtc_state);
2283 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2284                                         struct intel_crtc_state *crtc_state,
2285                                         const struct intel_plane_state *old_plane_state,
2286                                         struct intel_plane_state *intel_state);
2287
2288 /* intel_color.c */
2289 void intel_color_init(struct drm_crtc *crtc);
2290 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2291 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2292 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2293
2294 /* intel_lspcon.c */
2295 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2296 void lspcon_resume(struct intel_lspcon *lspcon);
2297 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2298 void lspcon_write_infoframe(struct intel_encoder *encoder,
2299                             const struct intel_crtc_state *crtc_state,
2300                             unsigned int type,
2301                             const void *buf, ssize_t len);
2302 void lspcon_set_infoframes(struct intel_encoder *encoder,
2303                            bool enable,
2304                            const struct intel_crtc_state *crtc_state,
2305                            const struct drm_connector_state *conn_state);
2306 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2307                               const struct intel_crtc_state *pipe_config);
2308 void lspcon_ycbcr420_config(struct drm_connector *connector,
2309                             struct intel_crtc_state *crtc_state);
2310
2311 /* intel_pipe_crc.c */
2312 #ifdef CONFIG_DEBUG_FS
2313 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2314 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2315                                  const char *source_name, size_t *values_cnt);
2316 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2317                                               size_t *count);
2318 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2319 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2320 #else
2321 #define intel_crtc_set_crc_source NULL
2322 #define intel_crtc_verify_crc_source NULL
2323 #define intel_crtc_get_crc_sources NULL
2324 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2325 {
2326 }
2327
2328 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2329 {
2330 }
2331 #endif
2332 #endif /* __INTEL_DRV_H__ */