2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <linux/slab.h>
33 #include <video/mipi_display.h>
34 #include <asm/intel-mid.h>
35 #include <video/mipi_display.h>
37 #include "intel_drv.h"
38 #include "intel_dsi.h"
41 struct drm_panel panel;
42 struct intel_dsi *intel_dsi;
45 static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
47 return container_of(panel, struct vbt_panel, panel);
50 #define MIPI_TRANSFER_MODE_SHIFT 0
51 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
52 #define MIPI_PORT_SHIFT 3
54 #define PREPARE_CNT_MAX 0x3F
55 #define EXIT_ZERO_CNT_MAX 0x3F
56 #define CLK_ZERO_CNT_MAX 0xFF
57 #define TRAIL_CNT_MAX 0x1F
59 #define NS_KHZ_RATIO 1000000
61 /* base offsets for gpio pads */
62 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
63 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
64 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
65 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
66 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
67 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
68 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
69 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
70 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
71 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
72 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
73 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
75 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
76 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
83 static struct gpio_map vlv_gpio_table[] = {
84 { VLV_GPIO_NC_0_HV_DDI0_HPD },
85 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
86 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
87 { VLV_GPIO_NC_3_PANEL0_VDDEN },
88 { VLV_GPIO_NC_4_PANEL0_BKLTEN },
89 { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
90 { VLV_GPIO_NC_6_HV_DDI1_HPD },
91 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
92 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
93 { VLV_GPIO_NC_9_PANEL1_VDDEN },
94 { VLV_GPIO_NC_10_PANEL1_BKLTEN },
95 { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
98 #define CHV_GPIO_IDX_START_N 0
99 #define CHV_GPIO_IDX_START_E 73
100 #define CHV_GPIO_IDX_START_SW 100
101 #define CHV_GPIO_IDX_START_SE 198
103 #define CHV_VBT_MAX_PINS_PER_FMLY 15
105 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
106 #define CHV_GPIO_GPIOEN (1 << 15)
107 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
108 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
109 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
110 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
111 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
113 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
114 #define CHV_GPIO_CFGLOCK (1 << 31)
116 static inline enum port intel_dsi_seq_port_to_port(u8 port)
118 return port ? PORT_C : PORT_A;
121 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
124 struct mipi_dsi_device *dsi_device;
125 u8 type, flags, seq_port;
134 len = *((u16 *) data);
137 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
139 /* For DSI single link on Port A & C, the seq_port value which is
140 * parsed from Sequence Block#53 of VBT has been set to 0
141 * Now, read/write of packets for the DSI single link on Port A and
142 * Port C will based on the DVO port from VBT block 2.
144 if (intel_dsi->ports == (1 << PORT_C))
147 port = intel_dsi_seq_port_to_port(seq_port);
149 dsi_device = intel_dsi->dsi_hosts[port]->device;
151 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
155 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
156 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
158 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
160 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
163 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
164 mipi_dsi_generic_write(dsi_device, NULL, 0);
166 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
167 mipi_dsi_generic_write(dsi_device, data, 1);
169 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
170 mipi_dsi_generic_write(dsi_device, data, 2);
172 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
173 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
174 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
175 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
177 case MIPI_DSI_GENERIC_LONG_WRITE:
178 mipi_dsi_generic_write(dsi_device, data, len);
180 case MIPI_DSI_DCS_SHORT_WRITE:
181 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
183 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
184 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
186 case MIPI_DSI_DCS_READ:
187 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
189 case MIPI_DSI_DCS_LONG_WRITE:
190 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
200 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
202 u32 delay = *((const u32 *) data);
206 usleep_range(delay, delay + 10);
212 static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
213 u8 gpio_source, u8 gpio_index, bool value)
215 struct gpio_map *map;
220 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
221 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
225 map = &vlv_gpio_table[gpio_index];
227 if (dev_priv->vbt.dsi.seq_version >= 3) {
228 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
229 port = IOSF_PORT_GPIO_NC;
231 if (gpio_source == 0) {
232 port = IOSF_PORT_GPIO_NC;
233 } else if (gpio_source == 1) {
234 DRM_DEBUG_KMS("SC gpio not supported\n");
237 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
242 pconf0 = VLV_GPIO_PCONF0(map->base_offset);
243 padval = VLV_GPIO_PAD_VAL(map->base_offset);
245 mutex_lock(&dev_priv->sb_lock);
247 /* FIXME: remove constant below */
248 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
253 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
254 mutex_unlock(&dev_priv->sb_lock);
257 static void chv_exec_gpio(struct drm_i915_private *dev_priv,
258 u8 gpio_source, u8 gpio_index, bool value)
264 if (dev_priv->vbt.dsi.seq_version >= 3) {
265 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
266 /* XXX: it's unclear whether 255->57 is part of SE. */
267 gpio_index -= CHV_GPIO_IDX_START_SE;
268 port = CHV_IOSF_PORT_GPIO_SE;
269 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
270 gpio_index -= CHV_GPIO_IDX_START_SW;
271 port = CHV_IOSF_PORT_GPIO_SW;
272 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
273 gpio_index -= CHV_GPIO_IDX_START_E;
274 port = CHV_IOSF_PORT_GPIO_E;
276 port = CHV_IOSF_PORT_GPIO_N;
279 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
280 if (gpio_source != 0) {
281 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
285 if (gpio_index >= CHV_GPIO_IDX_START_E) {
286 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
291 port = CHV_IOSF_PORT_GPIO_N;
294 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
295 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
297 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
298 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
300 mutex_lock(&dev_priv->sb_lock);
301 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
302 vlv_iosf_sb_write(dev_priv, port, cfg0,
303 CHV_GPIO_GPIOCFG_GPO | CHV_GPIO_GPIOTXSTATE(value));
304 mutex_unlock(&dev_priv->sb_lock);
307 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
309 struct drm_device *dev = intel_dsi->base.base.dev;
310 struct drm_i915_private *dev_priv = to_i915(dev);
311 u8 gpio_source, gpio_index;
316 if (dev_priv->vbt.dsi.seq_version >= 3)
319 gpio_index = *data++;
321 /* gpio source in sequence v2 only */
322 if (dev_priv->vbt.dsi.seq_version == 2)
323 gpio_source = (*data >> 1) & 3;
330 if (IS_VALLEYVIEW(dev_priv))
331 vlv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
332 else if (IS_CHERRYVIEW(dev_priv))
333 chv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
335 DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
340 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
342 DRM_DEBUG_KMS("Skipping I2C element execution\n");
344 return data + *(data + 6) + 7;
347 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
349 DRM_DEBUG_KMS("Skipping SPI element execution\n");
351 return data + *(data + 5) + 6;
354 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
356 DRM_DEBUG_KMS("Skipping PMIC element execution\n");
361 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
363 static const fn_mipi_elem_exec exec_elem[] = {
364 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
365 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
366 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
367 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
368 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
369 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
373 * MIPI Sequence from VBT #53 parsing logic
374 * We have already separated each seqence during bios parsing
375 * Following is generic execution function for any sequence
378 static const char * const seq_name[] = {
379 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
380 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
381 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
382 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
383 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
384 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
385 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
386 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
387 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
388 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
389 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
392 static const char *sequence_name(enum mipi_seq seq_id)
394 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
395 return seq_name[seq_id];
400 static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id)
402 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
403 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
404 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
406 fn_mipi_elem_exec mipi_elem_exec;
408 if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
411 data = dev_priv->vbt.dsi.sequence[seq_id];
415 WARN_ON(*data != seq_id);
417 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
418 seq_id, sequence_name(seq_id));
420 /* Skip Sequence Byte. */
423 /* Skip Size of Sequence. */
424 if (dev_priv->vbt.dsi.seq_version >= 3)
428 u8 operation_byte = *data++;
429 u8 operation_size = 0;
431 if (operation_byte == MIPI_SEQ_ELEM_END)
434 if (operation_byte < ARRAY_SIZE(exec_elem))
435 mipi_elem_exec = exec_elem[operation_byte];
437 mipi_elem_exec = NULL;
439 /* Size of Operation. */
440 if (dev_priv->vbt.dsi.seq_version >= 3)
441 operation_size = *data++;
443 if (mipi_elem_exec) {
444 const u8 *next = data + operation_size;
446 data = mipi_elem_exec(intel_dsi, data);
448 /* Consistency check if we have size. */
449 if (operation_size && data != next) {
450 DRM_ERROR("Inconsistent operation size\n");
453 } else if (operation_size) {
454 /* We have size, skip. */
455 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
457 data += operation_size;
459 /* No size, can't skip without parsing. */
460 DRM_ERROR("Unsupported MIPI operation byte %u\n",
467 static int vbt_panel_prepare(struct drm_panel *panel)
469 generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
470 generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
471 generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
472 generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
477 static int vbt_panel_unprepare(struct drm_panel *panel)
479 generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
480 generic_exec_sequence(panel, MIPI_SEQ_POWER_OFF);
485 static int vbt_panel_enable(struct drm_panel *panel)
487 generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_ON);
488 generic_exec_sequence(panel, MIPI_SEQ_BACKLIGHT_ON);
493 static int vbt_panel_disable(struct drm_panel *panel)
495 generic_exec_sequence(panel, MIPI_SEQ_BACKLIGHT_OFF);
496 generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_OFF);
501 static int vbt_panel_get_modes(struct drm_panel *panel)
503 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
504 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
505 struct drm_device *dev = intel_dsi->base.base.dev;
506 struct drm_i915_private *dev_priv = to_i915(dev);
507 struct drm_display_mode *mode;
509 if (!panel->connector)
512 mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
516 mode->type |= DRM_MODE_TYPE_PREFERRED;
518 drm_mode_probed_add(panel->connector, mode);
523 static const struct drm_panel_funcs vbt_panel_funcs = {
524 .disable = vbt_panel_disable,
525 .unprepare = vbt_panel_unprepare,
526 .prepare = vbt_panel_prepare,
527 .enable = vbt_panel_enable,
528 .get_modes = vbt_panel_get_modes,
531 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
533 struct drm_device *dev = intel_dsi->base.base.dev;
534 struct drm_i915_private *dev_priv = to_i915(dev);
535 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
536 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
537 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
538 struct vbt_panel *vbt_panel;
540 u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
542 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
543 u32 ths_prepare_ns, tclk_trail_ns;
544 u32 tclk_prepare_clkzero, ths_prepare_hszero;
545 u32 lp_to_hs_switch, hs_to_lp_switch;
546 u32 pclk, computed_ddr;
547 u16 burst_mode_ratio;
552 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
553 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
554 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
555 intel_dsi->pixel_format =
556 pixel_format_from_register_bits(
557 mipi_config->videomode_color_format << 7);
558 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
560 intel_dsi->dual_link = mipi_config->dual_link;
561 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
562 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
563 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
564 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
565 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
566 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
567 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
568 intel_dsi->init_count = mipi_config->master_init_timer;
569 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
570 intel_dsi->video_frmt_cfg_bits =
571 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
575 /* In dual link mode each port needs half of pixel clock */
576 if (intel_dsi->dual_link) {
579 /* we can enable pixel_overlap if needed by panel. In this
580 * case we need to increase the pixelclock for extra pixels
582 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
583 pclk += DIV_ROUND_UP(mode->vtotal *
584 intel_dsi->pixel_overlap *
590 * Target ddr frequency from VBT / non burst ddr freq
591 * multiply by 100 to preserve remainder
593 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
594 if (mipi_config->target_burst_mode_freq) {
595 computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
597 if (mipi_config->target_burst_mode_freq <
599 DRM_ERROR("Burst mode freq is less than computed\n");
603 burst_mode_ratio = DIV_ROUND_UP(
604 mipi_config->target_burst_mode_freq * 100,
607 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
609 DRM_ERROR("Burst mode target is not set\n");
613 burst_mode_ratio = 100;
615 intel_dsi->burst_mode_ratio = burst_mode_ratio;
616 intel_dsi->pclk = pclk;
618 bitrate = (pclk * bpp) / intel_dsi->lane_count;
620 switch (intel_dsi->escape_clk_div) {
636 switch (intel_dsi->lane_count) {
639 extra_byte_count = 2;
642 extra_byte_count = 4;
646 extra_byte_count = 3;
651 * ui(s) = 1/f [f in hz]
652 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
656 ui_num = NS_KHZ_RATIO;
659 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
660 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
664 * LP byte clock = TLPX/ (8UI)
666 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
668 /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
670 * Since txddrclkhs_i is 2xUI, all the count values programmed in
671 * DPHY param register are divided by 2
675 ths_prepare_ns = max(mipi_config->ths_prepare,
676 mipi_config->tclk_prepare);
677 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
679 /* exit zero count */
680 exit_zero_cnt = DIV_ROUND_UP(
681 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
686 * Exit zero is unified val ths_zero and ths_exit
687 * minimum value for ths_exit = 110ns
688 * min (exit_zero_cnt * 2) = 110/UI
689 * exit_zero_cnt = 55/UI
691 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
695 clk_zero_cnt = DIV_ROUND_UP(
696 (tclk_prepare_clkzero - ths_prepare_ns)
697 * ui_den, 2 * ui_num);
700 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
701 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
703 if (prepare_cnt > PREPARE_CNT_MAX ||
704 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
705 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
706 trail_cnt > TRAIL_CNT_MAX)
707 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
709 if (prepare_cnt > PREPARE_CNT_MAX)
710 prepare_cnt = PREPARE_CNT_MAX;
712 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
713 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
715 if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
716 clk_zero_cnt = CLK_ZERO_CNT_MAX;
718 if (trail_cnt > TRAIL_CNT_MAX)
719 trail_cnt = TRAIL_CNT_MAX;
722 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
723 clk_zero_cnt << 8 | prepare_cnt;
726 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
727 * + 10UI + Extra Byte Count
729 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
730 * Extra Byte Count is calculated according to number of lanes.
731 * High Low Switch Count is the Max of LP to HS and
732 * HS to LP switch count
735 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
739 * The comment above does not match with the code */
740 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
741 exit_zero_cnt * 2 + 10, 8);
743 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
745 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
746 intel_dsi->hs_to_lp_count += extra_byte_count;
749 /* LP -> HS for clock lanes
750 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
752 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
753 * 2(in UI) + extra byte count
754 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
755 * 8 + extra byte count
757 intel_dsi->clk_lp_to_hs_count =
759 4 * tlpx_ui + prepare_cnt * 2 +
763 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
765 /* HS->LP for Clock Lanes
766 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
768 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
769 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
772 intel_dsi->clk_hs_to_lp_count =
773 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
775 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
777 DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
778 DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
779 "disabled" : "enabled");
780 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
781 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
782 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
783 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
784 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
786 DRM_DEBUG_KMS("Dual link: NONE\n");
787 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
788 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
789 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
790 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
791 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
792 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
793 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
794 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
795 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
796 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
797 DRM_DEBUG_KMS("BTA %s\n",
798 intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
799 "disabled" : "enabled");
801 /* delays in VBT are in unit of 100us, so need to convert
803 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
804 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
805 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
806 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
807 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
808 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
810 /* This is cheating a bit with the cleanup. */
811 vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL);
815 vbt_panel->intel_dsi = intel_dsi;
816 drm_panel_init(&vbt_panel->panel);
817 vbt_panel->panel.funcs = &vbt_panel_funcs;
818 drm_panel_add(&vbt_panel->panel);
820 /* a regular driver would get the device in probe */
821 for_each_dsi_port(port, intel_dsi->ports) {
822 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
825 return &vbt_panel->panel;