2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_hdcp.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
45 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
51 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
52 struct drm_i915_private *dev_priv = to_i915(dev);
55 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
57 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
58 "HDMI port enabled, expecting disabled\n");
62 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
63 enum transcoder cpu_transcoder)
65 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
66 TRANS_DDI_FUNC_ENABLE,
67 "HDMI transcoder function enabled, expecting disabled\n");
70 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
72 struct intel_digital_port *intel_dig_port =
73 container_of(encoder, struct intel_digital_port, base.base);
74 return &intel_dig_port->hdmi;
77 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
79 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
82 static u32 g4x_infoframe_index(unsigned int type)
85 case HDMI_INFOFRAME_TYPE_AVI:
86 return VIDEO_DIP_SELECT_AVI;
87 case HDMI_INFOFRAME_TYPE_SPD:
88 return VIDEO_DIP_SELECT_SPD;
89 case HDMI_INFOFRAME_TYPE_VENDOR:
90 return VIDEO_DIP_SELECT_VENDOR;
97 static u32 g4x_infoframe_enable(unsigned int type)
100 case HDMI_INFOFRAME_TYPE_AVI:
101 return VIDEO_DIP_ENABLE_AVI;
102 case HDMI_INFOFRAME_TYPE_SPD:
103 return VIDEO_DIP_ENABLE_SPD;
104 case HDMI_INFOFRAME_TYPE_VENDOR:
105 return VIDEO_DIP_ENABLE_VENDOR;
112 static u32 hsw_infoframe_enable(unsigned int type)
116 return VIDEO_DIP_ENABLE_VSC_HSW;
118 return VDIP_ENABLE_PPS;
119 case HDMI_INFOFRAME_TYPE_AVI:
120 return VIDEO_DIP_ENABLE_AVI_HSW;
121 case HDMI_INFOFRAME_TYPE_SPD:
122 return VIDEO_DIP_ENABLE_SPD_HSW;
123 case HDMI_INFOFRAME_TYPE_VENDOR:
124 return VIDEO_DIP_ENABLE_VS_HSW;
132 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
133 enum transcoder cpu_transcoder,
139 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
141 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
142 case HDMI_INFOFRAME_TYPE_AVI:
143 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
144 case HDMI_INFOFRAME_TYPE_SPD:
145 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
146 case HDMI_INFOFRAME_TYPE_VENDOR:
147 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
150 return INVALID_MMIO_REG;
154 static int hsw_dip_data_size(unsigned int type)
158 return VIDEO_DIP_VSC_DATA_SIZE;
160 return VIDEO_DIP_PPS_DATA_SIZE;
162 return VIDEO_DIP_DATA_SIZE;
166 static void g4x_write_infoframe(struct intel_encoder *encoder,
167 const struct intel_crtc_state *crtc_state,
169 const void *frame, ssize_t len)
171 const u32 *data = frame;
172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
173 u32 val = I915_READ(VIDEO_DIP_CTL);
176 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
178 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
179 val |= g4x_infoframe_index(type);
181 val &= ~g4x_infoframe_enable(type);
183 I915_WRITE(VIDEO_DIP_CTL, val);
185 for (i = 0; i < len; i += 4) {
186 I915_WRITE(VIDEO_DIP_DATA, *data);
189 /* Write every possible data byte to force correct ECC calculation. */
190 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
191 I915_WRITE(VIDEO_DIP_DATA, 0);
193 val |= g4x_infoframe_enable(type);
194 val &= ~VIDEO_DIP_FREQ_MASK;
195 val |= VIDEO_DIP_FREQ_VSYNC;
197 I915_WRITE(VIDEO_DIP_CTL, val);
198 POSTING_READ(VIDEO_DIP_CTL);
201 static bool g4x_infoframe_enabled(struct intel_encoder *encoder,
202 const struct intel_crtc_state *pipe_config)
204 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
205 u32 val = I915_READ(VIDEO_DIP_CTL);
207 if ((val & VIDEO_DIP_ENABLE) == 0)
210 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
213 return val & (VIDEO_DIP_ENABLE_AVI |
214 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
217 static void ibx_write_infoframe(struct intel_encoder *encoder,
218 const struct intel_crtc_state *crtc_state,
220 const void *frame, ssize_t len)
222 const u32 *data = frame;
223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
225 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
226 u32 val = I915_READ(reg);
229 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
231 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
232 val |= g4x_infoframe_index(type);
234 val &= ~g4x_infoframe_enable(type);
236 I915_WRITE(reg, val);
238 for (i = 0; i < len; i += 4) {
239 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
242 /* Write every possible data byte to force correct ECC calculation. */
243 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
244 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
246 val |= g4x_infoframe_enable(type);
247 val &= ~VIDEO_DIP_FREQ_MASK;
248 val |= VIDEO_DIP_FREQ_VSYNC;
250 I915_WRITE(reg, val);
254 static bool ibx_infoframe_enabled(struct intel_encoder *encoder,
255 const struct intel_crtc_state *pipe_config)
257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
258 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
259 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
260 u32 val = I915_READ(reg);
262 if ((val & VIDEO_DIP_ENABLE) == 0)
265 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
268 return val & (VIDEO_DIP_ENABLE_AVI |
269 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
270 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
273 static void cpt_write_infoframe(struct intel_encoder *encoder,
274 const struct intel_crtc_state *crtc_state,
276 const void *frame, ssize_t len)
278 const u32 *data = frame;
279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
281 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
282 u32 val = I915_READ(reg);
285 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
287 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
288 val |= g4x_infoframe_index(type);
290 /* The DIP control register spec says that we need to update the AVI
291 * infoframe without clearing its enable bit */
292 if (type != HDMI_INFOFRAME_TYPE_AVI)
293 val &= ~g4x_infoframe_enable(type);
295 I915_WRITE(reg, val);
297 for (i = 0; i < len; i += 4) {
298 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
301 /* Write every possible data byte to force correct ECC calculation. */
302 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
303 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
305 val |= g4x_infoframe_enable(type);
306 val &= ~VIDEO_DIP_FREQ_MASK;
307 val |= VIDEO_DIP_FREQ_VSYNC;
309 I915_WRITE(reg, val);
313 static bool cpt_infoframe_enabled(struct intel_encoder *encoder,
314 const struct intel_crtc_state *pipe_config)
316 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
317 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
318 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
320 if ((val & VIDEO_DIP_ENABLE) == 0)
323 return val & (VIDEO_DIP_ENABLE_AVI |
324 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
325 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
328 static void vlv_write_infoframe(struct intel_encoder *encoder,
329 const struct intel_crtc_state *crtc_state,
331 const void *frame, ssize_t len)
333 const u32 *data = frame;
334 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
336 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
337 u32 val = I915_READ(reg);
340 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
342 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
343 val |= g4x_infoframe_index(type);
345 val &= ~g4x_infoframe_enable(type);
347 I915_WRITE(reg, val);
349 for (i = 0; i < len; i += 4) {
350 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
353 /* Write every possible data byte to force correct ECC calculation. */
354 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
355 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
357 val |= g4x_infoframe_enable(type);
358 val &= ~VIDEO_DIP_FREQ_MASK;
359 val |= VIDEO_DIP_FREQ_VSYNC;
361 I915_WRITE(reg, val);
365 static bool vlv_infoframe_enabled(struct intel_encoder *encoder,
366 const struct intel_crtc_state *pipe_config)
368 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
369 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
370 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
372 if ((val & VIDEO_DIP_ENABLE) == 0)
375 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
378 return val & (VIDEO_DIP_ENABLE_AVI |
379 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
380 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
383 static void hsw_write_infoframe(struct intel_encoder *encoder,
384 const struct intel_crtc_state *crtc_state,
386 const void *frame, ssize_t len)
388 const u32 *data = frame;
389 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
390 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
391 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
394 u32 val = I915_READ(ctl_reg);
396 data_size = hsw_dip_data_size(type);
398 val &= ~hsw_infoframe_enable(type);
399 I915_WRITE(ctl_reg, val);
401 for (i = 0; i < len; i += 4) {
402 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
403 type, i >> 2), *data);
406 /* Write every possible data byte to force correct ECC calculation. */
407 for (; i < data_size; i += 4)
408 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
411 val |= hsw_infoframe_enable(type);
412 I915_WRITE(ctl_reg, val);
413 POSTING_READ(ctl_reg);
416 static bool hsw_infoframe_enabled(struct intel_encoder *encoder,
417 const struct intel_crtc_state *pipe_config)
419 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
420 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
422 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
423 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
424 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
428 * The data we write to the DIP data buffer registers is 1 byte bigger than the
429 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
430 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
431 * used for both technologies.
433 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
434 * DW1: DB3 | DB2 | DB1 | DB0
435 * DW2: DB7 | DB6 | DB5 | DB4
438 * (HB is Header Byte, DB is Data Byte)
440 * The hdmi pack() functions don't know about that hardware specific hole so we
441 * trick them by giving an offset into the buffer and moving back the header
444 static void intel_write_infoframe(struct intel_encoder *encoder,
445 const struct intel_crtc_state *crtc_state,
446 union hdmi_infoframe *frame)
448 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
449 u8 buffer[VIDEO_DIP_DATA_SIZE];
452 /* see comment above for the reason for this offset */
453 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
457 /* Insert the 'hole' (see big comment above) at position 3 */
458 memmove(&buffer[0], &buffer[1], 3);
462 intel_dig_port->write_infoframe(encoder,
464 frame->any.type, buffer, len);
467 static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
468 const struct intel_crtc_state *crtc_state,
469 const struct drm_connector_state *conn_state)
471 const struct drm_display_mode *adjusted_mode =
472 &crtc_state->base.adjusted_mode;
473 union hdmi_infoframe frame;
476 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
477 conn_state->connector,
480 DRM_ERROR("couldn't fill AVI infoframe\n");
484 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
485 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
486 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
487 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
489 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
491 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
492 conn_state->connector,
494 crtc_state->limited_color_range ?
495 HDMI_QUANTIZATION_RANGE_LIMITED :
496 HDMI_QUANTIZATION_RANGE_FULL);
498 drm_hdmi_avi_infoframe_content_type(&frame.avi,
501 /* TODO: handle pixel repetition for YCBCR420 outputs */
502 intel_write_infoframe(encoder, crtc_state,
506 static void intel_hdmi_set_spd_infoframe(struct intel_encoder *encoder,
507 const struct intel_crtc_state *crtc_state)
509 union hdmi_infoframe frame;
512 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
514 DRM_ERROR("couldn't fill SPD infoframe\n");
518 frame.spd.sdi = HDMI_SPD_SDI_PC;
520 intel_write_infoframe(encoder, crtc_state,
525 intel_hdmi_set_hdmi_infoframe(struct intel_encoder *encoder,
526 const struct intel_crtc_state *crtc_state,
527 const struct drm_connector_state *conn_state)
529 union hdmi_infoframe frame;
532 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
533 conn_state->connector,
534 &crtc_state->base.adjusted_mode);
538 intel_write_infoframe(encoder, crtc_state,
542 static void g4x_set_infoframes(struct intel_encoder *encoder,
544 const struct intel_crtc_state *crtc_state,
545 const struct drm_connector_state *conn_state)
547 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
548 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
549 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
550 i915_reg_t reg = VIDEO_DIP_CTL;
551 u32 val = I915_READ(reg);
552 u32 port = VIDEO_DIP_PORT(encoder->port);
554 assert_hdmi_port_disabled(intel_hdmi);
556 /* If the registers were not initialized yet, they might be zeroes,
557 * which means we're selecting the AVI DIP and we're setting its
558 * frequency to once. This seems to really confuse the HW and make
559 * things stop working (the register spec says the AVI always needs to
560 * be sent every VSync). So here we avoid writing to the register more
561 * than we need and also explicitly select the AVI DIP and explicitly
562 * set its frequency to every VSync. Avoiding to write it twice seems to
563 * be enough to solve the problem, but being defensive shouldn't hurt us
565 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
568 if (!(val & VIDEO_DIP_ENABLE))
570 if (port != (val & VIDEO_DIP_PORT_MASK)) {
571 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
572 (val & VIDEO_DIP_PORT_MASK) >> 29);
575 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
576 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
577 I915_WRITE(reg, val);
582 if (port != (val & VIDEO_DIP_PORT_MASK)) {
583 if (val & VIDEO_DIP_ENABLE) {
584 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
585 (val & VIDEO_DIP_PORT_MASK) >> 29);
588 val &= ~VIDEO_DIP_PORT_MASK;
592 val |= VIDEO_DIP_ENABLE;
593 val &= ~(VIDEO_DIP_ENABLE_AVI |
594 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
596 I915_WRITE(reg, val);
599 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
600 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
601 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
604 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
606 struct drm_connector *connector = conn_state->connector;
609 * HDMI cloning is only supported on g4x which doesn't
610 * support deep color or GCP infoframes anyway so no
611 * need to worry about multiple HDMI sinks here.
614 return connector->display_info.bpc > 8;
618 * Determine if default_phase=1 can be indicated in the GCP infoframe.
620 * From HDMI specification 1.4a:
621 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
622 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
623 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
624 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
627 static bool gcp_default_phase_possible(int pipe_bpp,
628 const struct drm_display_mode *mode)
630 unsigned int pixels_per_group;
634 /* 4 pixels in 5 clocks */
635 pixels_per_group = 4;
638 /* 2 pixels in 3 clocks */
639 pixels_per_group = 2;
642 /* 1 pixel in 2 clocks */
643 pixels_per_group = 1;
646 /* phase information not relevant for 8bpc */
650 return mode->crtc_hdisplay % pixels_per_group == 0 &&
651 mode->crtc_htotal % pixels_per_group == 0 &&
652 mode->crtc_hblank_start % pixels_per_group == 0 &&
653 mode->crtc_hblank_end % pixels_per_group == 0 &&
654 mode->crtc_hsync_start % pixels_per_group == 0 &&
655 mode->crtc_hsync_end % pixels_per_group == 0 &&
656 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
657 mode->crtc_htotal/2 % pixels_per_group == 0);
660 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
661 const struct intel_crtc_state *crtc_state,
662 const struct drm_connector_state *conn_state)
664 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
665 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
669 if (HAS_DDI(dev_priv))
670 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
671 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
672 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
673 else if (HAS_PCH_SPLIT(dev_priv))
674 reg = TVIDEO_DIP_GCP(crtc->pipe);
678 /* Indicate color depth whenever the sink supports deep color */
679 if (hdmi_sink_is_deep_color(conn_state))
680 val |= GCP_COLOR_INDICATION;
682 /* Enable default_phase whenever the display mode is suitably aligned */
683 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
684 &crtc_state->base.adjusted_mode))
685 val |= GCP_DEFAULT_PHASE_ENABLE;
687 I915_WRITE(reg, val);
692 static void ibx_set_infoframes(struct intel_encoder *encoder,
694 const struct intel_crtc_state *crtc_state,
695 const struct drm_connector_state *conn_state)
697 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
699 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
700 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
701 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
702 u32 val = I915_READ(reg);
703 u32 port = VIDEO_DIP_PORT(encoder->port);
705 assert_hdmi_port_disabled(intel_hdmi);
707 /* See the big comment in g4x_set_infoframes() */
708 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
711 if (!(val & VIDEO_DIP_ENABLE))
713 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
714 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
715 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
716 I915_WRITE(reg, val);
721 if (port != (val & VIDEO_DIP_PORT_MASK)) {
722 WARN(val & VIDEO_DIP_ENABLE,
723 "DIP already enabled on port %c\n",
724 (val & VIDEO_DIP_PORT_MASK) >> 29);
725 val &= ~VIDEO_DIP_PORT_MASK;
729 val |= VIDEO_DIP_ENABLE;
730 val &= ~(VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
734 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
735 val |= VIDEO_DIP_ENABLE_GCP;
737 I915_WRITE(reg, val);
740 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
741 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
742 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
745 static void cpt_set_infoframes(struct intel_encoder *encoder,
747 const struct intel_crtc_state *crtc_state,
748 const struct drm_connector_state *conn_state)
750 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
752 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
753 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
754 u32 val = I915_READ(reg);
756 assert_hdmi_port_disabled(intel_hdmi);
758 /* See the big comment in g4x_set_infoframes() */
759 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
762 if (!(val & VIDEO_DIP_ENABLE))
764 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
765 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
766 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
767 I915_WRITE(reg, val);
772 /* Set both together, unset both together: see the spec. */
773 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
774 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
775 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
777 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
778 val |= VIDEO_DIP_ENABLE_GCP;
780 I915_WRITE(reg, val);
783 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
784 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
785 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
788 static void vlv_set_infoframes(struct intel_encoder *encoder,
790 const struct intel_crtc_state *crtc_state,
791 const struct drm_connector_state *conn_state)
793 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
795 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
796 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
797 u32 val = I915_READ(reg);
798 u32 port = VIDEO_DIP_PORT(encoder->port);
800 assert_hdmi_port_disabled(intel_hdmi);
802 /* See the big comment in g4x_set_infoframes() */
803 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
806 if (!(val & VIDEO_DIP_ENABLE))
808 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
809 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
810 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
811 I915_WRITE(reg, val);
816 if (port != (val & VIDEO_DIP_PORT_MASK)) {
817 WARN(val & VIDEO_DIP_ENABLE,
818 "DIP already enabled on port %c\n",
819 (val & VIDEO_DIP_PORT_MASK) >> 29);
820 val &= ~VIDEO_DIP_PORT_MASK;
824 val |= VIDEO_DIP_ENABLE;
825 val &= ~(VIDEO_DIP_ENABLE_AVI |
826 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
827 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
829 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
830 val |= VIDEO_DIP_ENABLE_GCP;
832 I915_WRITE(reg, val);
835 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
836 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
837 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
840 static void hsw_set_infoframes(struct intel_encoder *encoder,
842 const struct intel_crtc_state *crtc_state,
843 const struct drm_connector_state *conn_state)
845 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
846 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
847 u32 val = I915_READ(reg);
849 assert_hdmi_transcoder_func_disabled(dev_priv,
850 crtc_state->cpu_transcoder);
852 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
853 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
854 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
857 I915_WRITE(reg, val);
862 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
863 val |= VIDEO_DIP_ENABLE_GCP_HSW;
865 I915_WRITE(reg, val);
868 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
869 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
870 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
873 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
875 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
876 struct i2c_adapter *adapter =
877 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
879 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
882 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
883 enable ? "Enabling" : "Disabling");
885 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
889 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
890 unsigned int offset, void *buffer, size_t size)
892 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
893 struct drm_i915_private *dev_priv =
894 intel_dig_port->base.base.dev->dev_private;
895 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
898 u8 start = offset & 0xff;
899 struct i2c_msg msgs[] = {
901 .addr = DRM_HDCP_DDC_ADDR,
907 .addr = DRM_HDCP_DDC_ADDR,
913 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
914 if (ret == ARRAY_SIZE(msgs))
916 return ret >= 0 ? -EIO : ret;
919 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
920 unsigned int offset, void *buffer, size_t size)
922 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
923 struct drm_i915_private *dev_priv =
924 intel_dig_port->base.base.dev->dev_private;
925 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
931 write_buf = kzalloc(size + 1, GFP_KERNEL);
935 write_buf[0] = offset & 0xff;
936 memcpy(&write_buf[1], buffer, size);
938 msg.addr = DRM_HDCP_DDC_ADDR;
943 ret = i2c_transfer(adapter, &msg, 1);
954 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
957 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
958 struct drm_i915_private *dev_priv =
959 intel_dig_port->base.base.dev->dev_private;
960 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
964 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
967 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
971 ret = intel_gmbus_output_aksv(adapter);
973 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
979 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
983 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
986 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
991 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
995 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
996 bstatus, DRM_HDCP_BSTATUS_LEN);
998 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1003 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1004 bool *repeater_present)
1009 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1011 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1014 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1019 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1023 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1024 ri_prime, DRM_HDCP_RI_LEN);
1026 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1031 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1037 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1039 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1042 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1047 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1048 int num_downstream, u8 *ksv_fifo)
1051 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1052 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1054 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1061 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1066 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1069 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1070 part, DRM_HDCP_V_PRIME_PART_LEN);
1072 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1077 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1083 usleep_range(6, 60); /* Bspec says >= 6us */
1085 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1087 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1088 enable ? "Enable" : "Disable", ret);
1095 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1097 struct drm_i915_private *dev_priv =
1098 intel_dig_port->base.base.dev->dev_private;
1099 enum port port = intel_dig_port->base.port;
1103 u8 shim[DRM_HDCP_RI_LEN];
1106 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1110 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1112 /* Wait for Ri prime match */
1113 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1114 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1115 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1116 I915_READ(PORT_HDCP_STATUS(port)));
1122 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1123 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1124 .read_bksv = intel_hdmi_hdcp_read_bksv,
1125 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1126 .repeater_present = intel_hdmi_hdcp_repeater_present,
1127 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1128 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1129 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1130 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1131 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1132 .check_link = intel_hdmi_hdcp_check_link,
1135 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1136 const struct intel_crtc_state *crtc_state)
1138 struct drm_device *dev = encoder->base.dev;
1139 struct drm_i915_private *dev_priv = to_i915(dev);
1140 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1141 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1142 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1145 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1147 hdmi_val = SDVO_ENCODING_HDMI;
1148 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1149 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1150 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1151 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1152 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1153 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1155 if (crtc_state->pipe_bpp > 24)
1156 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1158 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1160 if (crtc_state->has_hdmi_sink)
1161 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1163 if (HAS_PCH_CPT(dev_priv))
1164 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1165 else if (IS_CHERRYVIEW(dev_priv))
1166 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1168 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1170 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1171 POSTING_READ(intel_hdmi->hdmi_reg);
1174 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1177 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1178 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1179 intel_wakeref_t wakeref;
1182 wakeref = intel_display_power_get_if_enabled(dev_priv,
1183 encoder->power_domain);
1187 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1189 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1194 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1195 struct intel_crtc_state *pipe_config)
1197 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1198 struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1199 struct drm_device *dev = encoder->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1204 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1206 tmp = I915_READ(intel_hdmi->hdmi_reg);
1208 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1209 flags |= DRM_MODE_FLAG_PHSYNC;
1211 flags |= DRM_MODE_FLAG_NHSYNC;
1213 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1214 flags |= DRM_MODE_FLAG_PVSYNC;
1216 flags |= DRM_MODE_FLAG_NVSYNC;
1218 if (tmp & HDMI_MODE_SELECT_HDMI)
1219 pipe_config->has_hdmi_sink = true;
1221 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
1222 pipe_config->has_infoframe = true;
1224 if (tmp & SDVO_AUDIO_ENABLE)
1225 pipe_config->has_audio = true;
1227 if (!HAS_PCH_SPLIT(dev_priv) &&
1228 tmp & HDMI_COLOR_RANGE_16_235)
1229 pipe_config->limited_color_range = true;
1231 pipe_config->base.adjusted_mode.flags |= flags;
1233 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1234 dotclock = pipe_config->port_clock * 2 / 3;
1236 dotclock = pipe_config->port_clock;
1238 if (pipe_config->pixel_multiplier)
1239 dotclock /= pipe_config->pixel_multiplier;
1241 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1243 pipe_config->lane_count = 4;
1246 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1247 const struct intel_crtc_state *pipe_config,
1248 const struct drm_connector_state *conn_state)
1250 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1252 WARN_ON(!pipe_config->has_hdmi_sink);
1253 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1254 pipe_name(crtc->pipe));
1255 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1258 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1259 const struct intel_crtc_state *pipe_config,
1260 const struct drm_connector_state *conn_state)
1262 struct drm_device *dev = encoder->base.dev;
1263 struct drm_i915_private *dev_priv = to_i915(dev);
1264 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1267 temp = I915_READ(intel_hdmi->hdmi_reg);
1269 temp |= SDVO_ENABLE;
1270 if (pipe_config->has_audio)
1271 temp |= SDVO_AUDIO_ENABLE;
1273 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1274 POSTING_READ(intel_hdmi->hdmi_reg);
1276 if (pipe_config->has_audio)
1277 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1280 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1281 const struct intel_crtc_state *pipe_config,
1282 const struct drm_connector_state *conn_state)
1284 struct drm_device *dev = encoder->base.dev;
1285 struct drm_i915_private *dev_priv = to_i915(dev);
1286 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1289 temp = I915_READ(intel_hdmi->hdmi_reg);
1291 temp |= SDVO_ENABLE;
1292 if (pipe_config->has_audio)
1293 temp |= SDVO_AUDIO_ENABLE;
1296 * HW workaround, need to write this twice for issue
1297 * that may result in first write getting masked.
1299 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1300 POSTING_READ(intel_hdmi->hdmi_reg);
1301 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1302 POSTING_READ(intel_hdmi->hdmi_reg);
1305 * HW workaround, need to toggle enable bit off and on
1306 * for 12bpc with pixel repeat.
1308 * FIXME: BSpec says this should be done at the end of
1309 * of the modeset sequence, so not sure if this isn't too soon.
1311 if (pipe_config->pipe_bpp > 24 &&
1312 pipe_config->pixel_multiplier > 1) {
1313 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1314 POSTING_READ(intel_hdmi->hdmi_reg);
1317 * HW workaround, need to write this twice for issue
1318 * that may result in first write getting masked.
1320 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1321 POSTING_READ(intel_hdmi->hdmi_reg);
1322 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1323 POSTING_READ(intel_hdmi->hdmi_reg);
1326 if (pipe_config->has_audio)
1327 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1330 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1331 const struct intel_crtc_state *pipe_config,
1332 const struct drm_connector_state *conn_state)
1334 struct drm_device *dev = encoder->base.dev;
1335 struct drm_i915_private *dev_priv = to_i915(dev);
1336 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1337 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1338 enum pipe pipe = crtc->pipe;
1341 temp = I915_READ(intel_hdmi->hdmi_reg);
1343 temp |= SDVO_ENABLE;
1344 if (pipe_config->has_audio)
1345 temp |= SDVO_AUDIO_ENABLE;
1348 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1350 * The procedure for 12bpc is as follows:
1351 * 1. disable HDMI clock gating
1352 * 2. enable HDMI with 8bpc
1353 * 3. enable HDMI with 12bpc
1354 * 4. enable HDMI clock gating
1357 if (pipe_config->pipe_bpp > 24) {
1358 I915_WRITE(TRANS_CHICKEN1(pipe),
1359 I915_READ(TRANS_CHICKEN1(pipe)) |
1360 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1362 temp &= ~SDVO_COLOR_FORMAT_MASK;
1363 temp |= SDVO_COLOR_FORMAT_8bpc;
1366 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1367 POSTING_READ(intel_hdmi->hdmi_reg);
1369 if (pipe_config->pipe_bpp > 24) {
1370 temp &= ~SDVO_COLOR_FORMAT_MASK;
1371 temp |= HDMI_COLOR_FORMAT_12bpc;
1373 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1374 POSTING_READ(intel_hdmi->hdmi_reg);
1376 I915_WRITE(TRANS_CHICKEN1(pipe),
1377 I915_READ(TRANS_CHICKEN1(pipe)) &
1378 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1381 if (pipe_config->has_audio)
1382 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1385 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1386 const struct intel_crtc_state *pipe_config,
1387 const struct drm_connector_state *conn_state)
1391 static void intel_disable_hdmi(struct intel_encoder *encoder,
1392 const struct intel_crtc_state *old_crtc_state,
1393 const struct drm_connector_state *old_conn_state)
1395 struct drm_device *dev = encoder->base.dev;
1396 struct drm_i915_private *dev_priv = to_i915(dev);
1397 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1398 struct intel_digital_port *intel_dig_port =
1399 hdmi_to_dig_port(intel_hdmi);
1400 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1403 temp = I915_READ(intel_hdmi->hdmi_reg);
1405 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1406 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1407 POSTING_READ(intel_hdmi->hdmi_reg);
1410 * HW workaround for IBX, we need to move the port
1411 * to transcoder A after disabling it to allow the
1412 * matching DP port to be enabled on transcoder A.
1414 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1416 * We get CPU/PCH FIFO underruns on the other pipe when
1417 * doing the workaround. Sweep them under the rug.
1419 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1420 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1422 temp &= ~SDVO_PIPE_SEL_MASK;
1423 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1425 * HW workaround, need to write this twice for issue
1426 * that may result in first write getting masked.
1428 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1429 POSTING_READ(intel_hdmi->hdmi_reg);
1430 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1431 POSTING_READ(intel_hdmi->hdmi_reg);
1433 temp &= ~SDVO_ENABLE;
1434 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1435 POSTING_READ(intel_hdmi->hdmi_reg);
1437 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1438 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1439 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1442 intel_dig_port->set_infoframes(encoder,
1444 old_crtc_state, old_conn_state);
1446 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1449 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1450 const struct intel_crtc_state *old_crtc_state,
1451 const struct drm_connector_state *old_conn_state)
1453 if (old_crtc_state->has_audio)
1454 intel_audio_codec_disable(encoder,
1455 old_crtc_state, old_conn_state);
1457 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1460 static void pch_disable_hdmi(struct intel_encoder *encoder,
1461 const struct intel_crtc_state *old_crtc_state,
1462 const struct drm_connector_state *old_conn_state)
1464 if (old_crtc_state->has_audio)
1465 intel_audio_codec_disable(encoder,
1466 old_crtc_state, old_conn_state);
1469 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1470 const struct intel_crtc_state *old_crtc_state,
1471 const struct drm_connector_state *old_conn_state)
1473 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1476 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1479 const struct ddi_vbt_port_info *info =
1480 &dev_priv->vbt.ddi_port_info[encoder->port];
1483 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1484 max_tmds_clock = 594000;
1485 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1486 max_tmds_clock = 300000;
1487 else if (INTEL_GEN(dev_priv) >= 5)
1488 max_tmds_clock = 225000;
1490 max_tmds_clock = 165000;
1492 if (info->max_tmds_clock)
1493 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1495 return max_tmds_clock;
1498 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1499 bool respect_downstream_limits,
1502 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1503 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1505 if (respect_downstream_limits) {
1506 struct intel_connector *connector = hdmi->attached_connector;
1507 const struct drm_display_info *info = &connector->base.display_info;
1509 if (hdmi->dp_dual_mode.max_tmds_clock)
1510 max_tmds_clock = min(max_tmds_clock,
1511 hdmi->dp_dual_mode.max_tmds_clock);
1513 if (info->max_tmds_clock)
1514 max_tmds_clock = min(max_tmds_clock,
1515 info->max_tmds_clock);
1516 else if (!hdmi->has_hdmi_sink || force_dvi)
1517 max_tmds_clock = min(max_tmds_clock, 165000);
1520 return max_tmds_clock;
1523 static enum drm_mode_status
1524 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1525 int clock, bool respect_downstream_limits,
1528 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1531 return MODE_CLOCK_LOW;
1532 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1533 return MODE_CLOCK_HIGH;
1535 /* BXT DPLL can't generate 223-240 MHz */
1536 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1537 return MODE_CLOCK_RANGE;
1539 /* CHV DPLL can't generate 216-240 MHz */
1540 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1541 return MODE_CLOCK_RANGE;
1546 static enum drm_mode_status
1547 intel_hdmi_mode_valid(struct drm_connector *connector,
1548 struct drm_display_mode *mode)
1550 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1551 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1552 struct drm_i915_private *dev_priv = to_i915(dev);
1553 enum drm_mode_status status;
1555 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1557 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1559 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1560 return MODE_NO_DBLESCAN;
1562 clock = mode->clock;
1564 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1567 if (clock > max_dotclk)
1568 return MODE_CLOCK_HIGH;
1570 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1573 if (drm_mode_is_420_only(&connector->display_info, mode))
1576 /* check if we can do 8bpc */
1577 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1579 if (hdmi->has_hdmi_sink && !force_dvi) {
1580 /* if we can't do 8bpc we may still be able to do 12bpc */
1581 if (status != MODE_OK && !HAS_GMCH(dev_priv))
1582 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1585 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1586 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1587 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1594 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1597 struct drm_i915_private *dev_priv =
1598 to_i915(crtc_state->base.crtc->dev);
1599 struct drm_atomic_state *state = crtc_state->base.state;
1600 struct drm_connector_state *connector_state;
1601 struct drm_connector *connector;
1602 const struct drm_display_mode *adjusted_mode =
1603 &crtc_state->base.adjusted_mode;
1606 if (HAS_GMCH(dev_priv))
1609 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1612 if (crtc_state->pipe_bpp <= 8*3)
1615 if (!crtc_state->has_hdmi_sink)
1619 * HDMI deep color affects the clocks, so it's only possible
1620 * when not cloning with other encoder types.
1622 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1625 for_each_new_connector_in_state(state, connector, connector_state, i) {
1626 const struct drm_display_info *info = &connector->display_info;
1628 if (connector_state->crtc != crtc_state->base.crtc)
1631 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1632 const struct drm_hdmi_info *hdmi = &info->hdmi;
1634 if (bpc == 12 && !(hdmi->y420_dc_modes &
1635 DRM_EDID_YCBCR420_DC_36))
1637 else if (bpc == 10 && !(hdmi->y420_dc_modes &
1638 DRM_EDID_YCBCR420_DC_30))
1641 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1642 DRM_EDID_HDMI_DC_36))
1644 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1645 DRM_EDID_HDMI_DC_30))
1650 /* Display WA #1139: glk */
1651 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1652 adjusted_mode->htotal > 5460)
1655 /* Display Wa_1405510057:icl */
1656 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1657 bpc == 10 && IS_ICELAKE(dev_priv) &&
1658 (adjusted_mode->crtc_hblank_end -
1659 adjusted_mode->crtc_hblank_start) % 8 == 2)
1666 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1667 struct intel_crtc_state *config,
1668 int *clock_12bpc, int *clock_10bpc,
1671 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1673 if (!connector->ycbcr_420_allowed) {
1674 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1678 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1679 config->port_clock /= 2;
1683 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1685 /* YCBCR 420 output conversion needs a scaler */
1686 if (skl_update_scaler_crtc(config)) {
1687 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1691 intel_pch_panel_fitting(intel_crtc, config,
1692 DRM_MODE_SCALE_FULLSCREEN);
1697 int intel_hdmi_compute_config(struct intel_encoder *encoder,
1698 struct intel_crtc_state *pipe_config,
1699 struct drm_connector_state *conn_state)
1701 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1702 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1703 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1704 struct drm_connector *connector = conn_state->connector;
1705 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1706 struct intel_digital_connector_state *intel_conn_state =
1707 to_intel_digital_connector_state(conn_state);
1708 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1709 int clock_10bpc = clock_8bpc * 5 / 4;
1710 int clock_12bpc = clock_8bpc * 3 / 2;
1712 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1714 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1717 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1718 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1720 if (pipe_config->has_hdmi_sink)
1721 pipe_config->has_infoframe = true;
1723 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1724 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1725 pipe_config->limited_color_range =
1726 pipe_config->has_hdmi_sink &&
1727 drm_default_rgb_quant_range(adjusted_mode) ==
1728 HDMI_QUANTIZATION_RANGE_LIMITED;
1730 pipe_config->limited_color_range =
1731 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1734 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1735 pipe_config->pixel_multiplier = 2;
1741 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1742 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1743 &clock_12bpc, &clock_10bpc,
1745 DRM_ERROR("Can't support YCBCR420 output\n");
1750 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1751 pipe_config->has_pch_encoder = true;
1753 if (pipe_config->has_hdmi_sink) {
1754 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1755 pipe_config->has_audio = intel_hdmi->has_audio;
1757 pipe_config->has_audio =
1758 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1762 * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
1763 * to check that the higher clock still fits within limits.
1765 if (hdmi_deep_color_possible(pipe_config, 12) &&
1766 hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
1767 true, force_dvi) == MODE_OK) {
1768 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1771 /* Need to adjust the port link by 1.5x for 12bpc. */
1772 pipe_config->port_clock = clock_12bpc;
1773 } else if (hdmi_deep_color_possible(pipe_config, 10) &&
1774 hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
1775 true, force_dvi) == MODE_OK) {
1776 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
1777 desired_bpp = 10 * 3;
1779 /* Need to adjust the port link by 1.25x for 10bpc. */
1780 pipe_config->port_clock = clock_10bpc;
1782 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1785 pipe_config->port_clock = clock_8bpc;
1788 if (!pipe_config->bw_constrained) {
1789 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1790 pipe_config->pipe_bpp = desired_bpp;
1793 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1794 false, force_dvi) != MODE_OK) {
1795 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1799 /* Set user selected PAR to incoming mode's member */
1800 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1802 pipe_config->lane_count = 4;
1804 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1805 IS_GEMINILAKE(dev_priv))) {
1806 if (scdc->scrambling.low_rates)
1807 pipe_config->hdmi_scrambling = true;
1809 if (pipe_config->port_clock > 340000) {
1810 pipe_config->hdmi_scrambling = true;
1811 pipe_config->hdmi_high_tmds_clock_ratio = true;
1819 intel_hdmi_unset_edid(struct drm_connector *connector)
1821 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1823 intel_hdmi->has_hdmi_sink = false;
1824 intel_hdmi->has_audio = false;
1826 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1827 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1829 kfree(to_intel_connector(connector)->detect_edid);
1830 to_intel_connector(connector)->detect_edid = NULL;
1834 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1836 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1837 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1838 enum port port = hdmi_to_dig_port(hdmi)->base.port;
1839 struct i2c_adapter *adapter =
1840 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1841 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1844 * Type 1 DVI adaptors are not required to implement any
1845 * registers, so we can't always detect their presence.
1846 * Ideally we should be able to check the state of the
1847 * CONFIG1 pin, but no such luck on our hardware.
1849 * The only method left to us is to check the VBT to see
1850 * if the port is a dual mode capable DP port. But let's
1851 * only do that when we sucesfully read the EDID, to avoid
1852 * confusing log messages about DP dual mode adaptors when
1853 * there's nothing connected to the port.
1855 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1856 /* An overridden EDID imply that we want this port for testing.
1857 * Make sure not to set limits for that port.
1859 if (has_edid && !connector->override_edid &&
1860 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1861 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1862 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1864 type = DRM_DP_DUAL_MODE_NONE;
1868 if (type == DRM_DP_DUAL_MODE_NONE)
1871 hdmi->dp_dual_mode.type = type;
1872 hdmi->dp_dual_mode.max_tmds_clock =
1873 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1875 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1876 drm_dp_get_dual_mode_type_name(type),
1877 hdmi->dp_dual_mode.max_tmds_clock);
1881 intel_hdmi_set_edid(struct drm_connector *connector)
1883 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1884 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1885 intel_wakeref_t wakeref;
1887 bool connected = false;
1888 struct i2c_adapter *i2c;
1890 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1892 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1894 edid = drm_get_edid(connector, i2c);
1896 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1897 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1898 intel_gmbus_force_bit(i2c, true);
1899 edid = drm_get_edid(connector, i2c);
1900 intel_gmbus_force_bit(i2c, false);
1903 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1905 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
1907 to_intel_connector(connector)->detect_edid = edid;
1908 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1909 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1910 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1915 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
1920 static enum drm_connector_status
1921 intel_hdmi_detect(struct drm_connector *connector, bool force)
1923 enum drm_connector_status status = connector_status_disconnected;
1924 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1925 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1926 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
1927 intel_wakeref_t wakeref;
1929 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1930 connector->base.id, connector->name);
1932 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1934 if (IS_ICELAKE(dev_priv) &&
1935 !intel_digital_port_connected(encoder))
1938 intel_hdmi_unset_edid(connector);
1940 if (intel_hdmi_set_edid(connector))
1941 status = connector_status_connected;
1944 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
1946 if (status != connector_status_connected)
1947 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
1953 intel_hdmi_force(struct drm_connector *connector)
1955 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1956 connector->base.id, connector->name);
1958 intel_hdmi_unset_edid(connector);
1960 if (connector->status != connector_status_connected)
1963 intel_hdmi_set_edid(connector);
1966 static int intel_hdmi_get_modes(struct drm_connector *connector)
1970 edid = to_intel_connector(connector)->detect_edid;
1974 return intel_connector_update_modes(connector, edid);
1977 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1978 const struct intel_crtc_state *pipe_config,
1979 const struct drm_connector_state *conn_state)
1981 struct intel_digital_port *intel_dig_port =
1982 enc_to_dig_port(&encoder->base);
1984 intel_hdmi_prepare(encoder, pipe_config);
1986 intel_dig_port->set_infoframes(encoder,
1987 pipe_config->has_infoframe,
1988 pipe_config, conn_state);
1991 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1992 const struct intel_crtc_state *pipe_config,
1993 const struct drm_connector_state *conn_state)
1995 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1996 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1998 vlv_phy_pre_encoder_enable(encoder, pipe_config);
2001 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2004 dport->set_infoframes(encoder,
2005 pipe_config->has_infoframe,
2006 pipe_config, conn_state);
2008 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2010 vlv_wait_port_ready(dev_priv, dport, 0x0);
2013 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2014 const struct intel_crtc_state *pipe_config,
2015 const struct drm_connector_state *conn_state)
2017 intel_hdmi_prepare(encoder, pipe_config);
2019 vlv_phy_pre_pll_enable(encoder, pipe_config);
2022 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2023 const struct intel_crtc_state *pipe_config,
2024 const struct drm_connector_state *conn_state)
2026 intel_hdmi_prepare(encoder, pipe_config);
2028 chv_phy_pre_pll_enable(encoder, pipe_config);
2031 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2032 const struct intel_crtc_state *old_crtc_state,
2033 const struct drm_connector_state *old_conn_state)
2035 chv_phy_post_pll_disable(encoder, old_crtc_state);
2038 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2039 const struct intel_crtc_state *old_crtc_state,
2040 const struct drm_connector_state *old_conn_state)
2042 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2043 vlv_phy_reset_lanes(encoder, old_crtc_state);
2046 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2047 const struct intel_crtc_state *old_crtc_state,
2048 const struct drm_connector_state *old_conn_state)
2050 struct drm_device *dev = encoder->base.dev;
2051 struct drm_i915_private *dev_priv = to_i915(dev);
2053 mutex_lock(&dev_priv->sb_lock);
2055 /* Assert data lane reset */
2056 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2058 mutex_unlock(&dev_priv->sb_lock);
2061 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2062 const struct intel_crtc_state *pipe_config,
2063 const struct drm_connector_state *conn_state)
2065 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2066 struct drm_device *dev = encoder->base.dev;
2067 struct drm_i915_private *dev_priv = to_i915(dev);
2069 chv_phy_pre_encoder_enable(encoder, pipe_config);
2071 /* FIXME: Program the support xxx V-dB */
2073 chv_set_phy_signal_level(encoder, 128, 102, false);
2075 dport->set_infoframes(encoder,
2076 pipe_config->has_infoframe,
2077 pipe_config, conn_state);
2079 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2081 vlv_wait_port_ready(dev_priv, dport, 0x0);
2083 /* Second common lane will stay alive on its own now */
2084 chv_phy_release_cl2_override(encoder);
2088 intel_hdmi_connector_register(struct drm_connector *connector)
2092 ret = intel_connector_register(connector);
2096 i915_debugfs_connector_add(connector);
2101 static void intel_hdmi_destroy(struct drm_connector *connector)
2103 if (intel_attached_hdmi(connector)->cec_notifier)
2104 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2106 intel_connector_destroy(connector);
2109 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2110 .detect = intel_hdmi_detect,
2111 .force = intel_hdmi_force,
2112 .fill_modes = drm_helper_probe_single_connector_modes,
2113 .atomic_get_property = intel_digital_connector_atomic_get_property,
2114 .atomic_set_property = intel_digital_connector_atomic_set_property,
2115 .late_register = intel_hdmi_connector_register,
2116 .early_unregister = intel_connector_unregister,
2117 .destroy = intel_hdmi_destroy,
2118 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2119 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2122 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2123 .get_modes = intel_hdmi_get_modes,
2124 .mode_valid = intel_hdmi_mode_valid,
2125 .atomic_check = intel_digital_connector_atomic_check,
2128 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2129 .destroy = intel_encoder_destroy,
2133 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2135 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2137 intel_attach_force_audio_property(connector);
2138 intel_attach_broadcast_rgb_property(connector);
2139 intel_attach_aspect_ratio_property(connector);
2140 drm_connector_attach_content_type_property(connector);
2141 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2143 if (!HAS_GMCH(dev_priv))
2144 drm_connector_attach_max_bpc_property(connector, 8, 12);
2148 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2149 * @encoder: intel_encoder
2150 * @connector: drm_connector
2151 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2152 * or reset the high tmds clock ratio for scrambling
2153 * @scrambling: bool to Indicate if the function needs to set or reset
2156 * This function handles scrambling on HDMI 2.0 capable sinks.
2157 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2158 * it enables scrambling. This should be called before enabling the HDMI
2159 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2160 * detect a scrambled clock within 100 ms.
2163 * True on success, false on failure.
2165 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2166 struct drm_connector *connector,
2167 bool high_tmds_clock_ratio,
2170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2171 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2172 struct drm_scrambling *sink_scrambling =
2173 &connector->display_info.hdmi.scdc.scrambling;
2174 struct i2c_adapter *adapter =
2175 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2177 if (!sink_scrambling->supported)
2180 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2181 connector->base.id, connector->name,
2182 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2184 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2185 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2186 high_tmds_clock_ratio) &&
2187 drm_scdc_set_scrambling(adapter, scrambling);
2190 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2196 ddc_pin = GMBUS_PIN_DPB;
2199 ddc_pin = GMBUS_PIN_DPC;
2202 ddc_pin = GMBUS_PIN_DPD_CHV;
2206 ddc_pin = GMBUS_PIN_DPB;
2212 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2218 ddc_pin = GMBUS_PIN_1_BXT;
2221 ddc_pin = GMBUS_PIN_2_BXT;
2225 ddc_pin = GMBUS_PIN_1_BXT;
2231 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2238 ddc_pin = GMBUS_PIN_1_BXT;
2241 ddc_pin = GMBUS_PIN_2_BXT;
2244 ddc_pin = GMBUS_PIN_4_CNP;
2247 ddc_pin = GMBUS_PIN_3_BXT;
2251 ddc_pin = GMBUS_PIN_1_BXT;
2257 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2263 ddc_pin = GMBUS_PIN_1_BXT;
2266 ddc_pin = GMBUS_PIN_2_BXT;
2269 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2272 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2275 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2278 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2282 ddc_pin = GMBUS_PIN_2_BXT;
2288 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2295 ddc_pin = GMBUS_PIN_DPB;
2298 ddc_pin = GMBUS_PIN_DPC;
2301 ddc_pin = GMBUS_PIN_DPD;
2305 ddc_pin = GMBUS_PIN_DPB;
2311 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2314 const struct ddi_vbt_port_info *info =
2315 &dev_priv->vbt.ddi_port_info[port];
2318 if (info->alternate_ddc_pin) {
2319 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2320 info->alternate_ddc_pin, port_name(port));
2321 return info->alternate_ddc_pin;
2324 if (IS_CHERRYVIEW(dev_priv))
2325 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2326 else if (IS_GEN9_LP(dev_priv))
2327 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2328 else if (HAS_PCH_CNP(dev_priv))
2329 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2330 else if (HAS_PCH_ICP(dev_priv))
2331 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2333 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2335 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2336 ddc_pin, port_name(port));
2341 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2343 struct drm_i915_private *dev_priv =
2344 to_i915(intel_dig_port->base.base.dev);
2346 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2347 intel_dig_port->write_infoframe = vlv_write_infoframe;
2348 intel_dig_port->set_infoframes = vlv_set_infoframes;
2349 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2350 } else if (IS_G4X(dev_priv)) {
2351 intel_dig_port->write_infoframe = g4x_write_infoframe;
2352 intel_dig_port->set_infoframes = g4x_set_infoframes;
2353 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2354 } else if (HAS_DDI(dev_priv)) {
2355 if (intel_dig_port->lspcon.active) {
2356 intel_dig_port->write_infoframe =
2357 lspcon_write_infoframe;
2358 intel_dig_port->set_infoframes = lspcon_set_infoframes;
2359 intel_dig_port->infoframe_enabled =
2360 lspcon_infoframe_enabled;
2362 intel_dig_port->set_infoframes = hsw_set_infoframes;
2363 intel_dig_port->infoframe_enabled =
2364 hsw_infoframe_enabled;
2365 intel_dig_port->write_infoframe = hsw_write_infoframe;
2367 } else if (HAS_PCH_IBX(dev_priv)) {
2368 intel_dig_port->write_infoframe = ibx_write_infoframe;
2369 intel_dig_port->set_infoframes = ibx_set_infoframes;
2370 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2372 intel_dig_port->write_infoframe = cpt_write_infoframe;
2373 intel_dig_port->set_infoframes = cpt_set_infoframes;
2374 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2378 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2379 struct intel_connector *intel_connector)
2381 struct drm_connector *connector = &intel_connector->base;
2382 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2383 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2384 struct drm_device *dev = intel_encoder->base.dev;
2385 struct drm_i915_private *dev_priv = to_i915(dev);
2386 enum port port = intel_encoder->port;
2388 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2391 if (WARN(intel_dig_port->max_lanes < 4,
2392 "Not enough lanes (%d) for HDMI on port %c\n",
2393 intel_dig_port->max_lanes, port_name(port)))
2396 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2397 DRM_MODE_CONNECTOR_HDMIA);
2398 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2400 connector->interlace_allowed = 1;
2401 connector->doublescan_allowed = 0;
2402 connector->stereo_allowed = 1;
2404 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2405 connector->ycbcr_420_allowed = true;
2407 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2409 if (WARN_ON(port == PORT_A))
2411 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2413 if (HAS_DDI(dev_priv))
2414 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2416 intel_connector->get_hw_state = intel_connector_get_hw_state;
2418 intel_hdmi_add_properties(intel_hdmi, connector);
2420 if (is_hdcp_supported(dev_priv, port)) {
2421 int ret = intel_hdcp_init(intel_connector,
2422 &intel_hdmi_hdcp_shim);
2424 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2427 intel_connector_attach_encoder(intel_connector, intel_encoder);
2428 intel_hdmi->attached_connector = intel_connector;
2430 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2431 * 0xd. Failure to do so will result in spurious interrupts being
2432 * generated on the port when a cable is not attached.
2434 if (IS_G45(dev_priv)) {
2435 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2436 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2439 intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
2440 port_identifier(port));
2441 if (!intel_hdmi->cec_notifier)
2442 DRM_DEBUG_KMS("CEC notifier get failed\n");
2445 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2446 i915_reg_t hdmi_reg, enum port port)
2448 struct intel_digital_port *intel_dig_port;
2449 struct intel_encoder *intel_encoder;
2450 struct intel_connector *intel_connector;
2452 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2453 if (!intel_dig_port)
2456 intel_connector = intel_connector_alloc();
2457 if (!intel_connector) {
2458 kfree(intel_dig_port);
2462 intel_encoder = &intel_dig_port->base;
2464 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2465 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2466 "HDMI %c", port_name(port));
2468 intel_encoder->hotplug = intel_encoder_hotplug;
2469 intel_encoder->compute_config = intel_hdmi_compute_config;
2470 if (HAS_PCH_SPLIT(dev_priv)) {
2471 intel_encoder->disable = pch_disable_hdmi;
2472 intel_encoder->post_disable = pch_post_disable_hdmi;
2474 intel_encoder->disable = g4x_disable_hdmi;
2476 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2477 intel_encoder->get_config = intel_hdmi_get_config;
2478 if (IS_CHERRYVIEW(dev_priv)) {
2479 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2480 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2481 intel_encoder->enable = vlv_enable_hdmi;
2482 intel_encoder->post_disable = chv_hdmi_post_disable;
2483 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2484 } else if (IS_VALLEYVIEW(dev_priv)) {
2485 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2486 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2487 intel_encoder->enable = vlv_enable_hdmi;
2488 intel_encoder->post_disable = vlv_hdmi_post_disable;
2490 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2491 if (HAS_PCH_CPT(dev_priv))
2492 intel_encoder->enable = cpt_enable_hdmi;
2493 else if (HAS_PCH_IBX(dev_priv))
2494 intel_encoder->enable = ibx_enable_hdmi;
2496 intel_encoder->enable = g4x_enable_hdmi;
2499 intel_encoder->type = INTEL_OUTPUT_HDMI;
2500 intel_encoder->power_domain = intel_port_to_power_domain(port);
2501 intel_encoder->port = port;
2502 if (IS_CHERRYVIEW(dev_priv)) {
2504 intel_encoder->crtc_mask = 1 << 2;
2506 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2508 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2510 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2512 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2513 * to work on real hardware. And since g4x can send infoframes to
2514 * only one port anyway, nothing is lost by allowing it.
2516 if (IS_G4X(dev_priv))
2517 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2519 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2520 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2521 intel_dig_port->max_lanes = 4;
2523 intel_infoframe_init(intel_dig_port);
2525 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
2526 intel_hdmi_init_connector(intel_dig_port, intel_connector);