2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
117 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
118 enum transcoder cpu_transcoder,
119 enum hdmi_infoframe_type type,
123 case HDMI_INFOFRAME_TYPE_AVI:
124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
125 case HDMI_INFOFRAME_TYPE_SPD:
126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
127 case HDMI_INFOFRAME_TYPE_VENDOR:
128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
131 return INVALID_MMIO_REG;
135 static void g4x_write_infoframe(struct drm_encoder *encoder,
136 enum hdmi_infoframe_type type,
137 const void *frame, ssize_t len)
139 const uint32_t *data = frame;
140 struct drm_device *dev = encoder->dev;
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 u32 val = I915_READ(VIDEO_DIP_CTL);
145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
148 val |= g4x_infoframe_index(type);
150 val &= ~g4x_infoframe_enable(type);
152 I915_WRITE(VIDEO_DIP_CTL, val);
155 for (i = 0; i < len; i += 4) {
156 I915_WRITE(VIDEO_DIP_DATA, *data);
159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
161 I915_WRITE(VIDEO_DIP_DATA, 0);
164 val |= g4x_infoframe_enable(type);
165 val &= ~VIDEO_DIP_FREQ_MASK;
166 val |= VIDEO_DIP_FREQ_VSYNC;
168 I915_WRITE(VIDEO_DIP_CTL, val);
169 POSTING_READ(VIDEO_DIP_CTL);
172 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
173 const struct intel_crtc_state *pipe_config)
175 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
177 u32 val = I915_READ(VIDEO_DIP_CTL);
179 if ((val & VIDEO_DIP_ENABLE) == 0)
182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
185 return val & (VIDEO_DIP_ENABLE_AVI |
186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
189 static void ibx_write_infoframe(struct drm_encoder *encoder,
190 enum hdmi_infoframe_type type,
191 const void *frame, ssize_t len)
193 const uint32_t *data = frame;
194 struct drm_device *dev = encoder->dev;
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
198 u32 val = I915_READ(reg);
201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
204 val |= g4x_infoframe_index(type);
206 val &= ~g4x_infoframe_enable(type);
208 I915_WRITE(reg, val);
211 for (i = 0; i < len; i += 4) {
212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
215 /* Write every possible data byte to force correct ECC calculation. */
216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
220 val |= g4x_infoframe_enable(type);
221 val &= ~VIDEO_DIP_FREQ_MASK;
222 val |= VIDEO_DIP_FREQ_VSYNC;
224 I915_WRITE(reg, val);
228 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
229 const struct intel_crtc_state *pipe_config)
231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
233 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
235 u32 val = I915_READ(reg);
237 if ((val & VIDEO_DIP_ENABLE) == 0)
240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
243 return val & (VIDEO_DIP_ENABLE_AVI |
244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
248 static void cpt_write_infoframe(struct drm_encoder *encoder,
249 enum hdmi_infoframe_type type,
250 const void *frame, ssize_t len)
252 const uint32_t *data = frame;
253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
257 u32 val = I915_READ(reg);
260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
263 val |= g4x_infoframe_index(type);
265 /* The DIP control register spec says that we need to update the AVI
266 * infoframe without clearing its enable bit */
267 if (type != HDMI_INFOFRAME_TYPE_AVI)
268 val &= ~g4x_infoframe_enable(type);
270 I915_WRITE(reg, val);
273 for (i = 0; i < len; i += 4) {
274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
282 val |= g4x_infoframe_enable(type);
283 val &= ~VIDEO_DIP_FREQ_MASK;
284 val |= VIDEO_DIP_FREQ_VSYNC;
286 I915_WRITE(reg, val);
290 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
291 const struct intel_crtc_state *pipe_config)
293 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
294 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
297 if ((val & VIDEO_DIP_ENABLE) == 0)
300 return val & (VIDEO_DIP_ENABLE_AVI |
301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
305 static void vlv_write_infoframe(struct drm_encoder *encoder,
306 enum hdmi_infoframe_type type,
307 const void *frame, ssize_t len)
309 const uint32_t *data = frame;
310 struct drm_device *dev = encoder->dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
314 u32 val = I915_READ(reg);
317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
320 val |= g4x_infoframe_index(type);
322 val &= ~g4x_infoframe_enable(type);
324 I915_WRITE(reg, val);
327 for (i = 0; i < len; i += 4) {
328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
331 /* Write every possible data byte to force correct ECC calculation. */
332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
336 val |= g4x_infoframe_enable(type);
337 val &= ~VIDEO_DIP_FREQ_MASK;
338 val |= VIDEO_DIP_FREQ_VSYNC;
340 I915_WRITE(reg, val);
344 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
347 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
349 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
352 if ((val & VIDEO_DIP_ENABLE) == 0)
355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
363 static void hsw_write_infoframe(struct drm_encoder *encoder,
364 enum hdmi_infoframe_type type,
365 const void *frame, ssize_t len)
367 const uint32_t *data = frame;
368 struct drm_device *dev = encoder->dev;
369 struct drm_i915_private *dev_priv = dev->dev_private;
370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
375 u32 val = I915_READ(ctl_reg);
377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
379 val &= ~hsw_infoframe_enable(type);
380 I915_WRITE(ctl_reg, val);
383 for (i = 0; i < len; i += 4) {
384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
385 type, i >> 2), *data);
388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
394 val |= hsw_infoframe_enable(type);
395 I915_WRITE(ctl_reg, val);
396 POSTING_READ(ctl_reg);
399 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
400 const struct intel_crtc_state *pipe_config)
402 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
421 * (HB is Header Byte, DB is Data Byte)
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
427 static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
450 const struct drm_display_mode *adjusted_mode)
452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
454 union hdmi_infoframe frame;
457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
460 DRM_ERROR("couldn't fill AVI infoframe\n");
464 if (intel_hdmi->rgb_quant_range_selectable) {
465 if (intel_crtc->config->limited_color_range)
466 frame.avi.quantization_range =
467 HDMI_QUANTIZATION_RANGE_LIMITED;
469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_FULL;
473 intel_write_infoframe(encoder, &frame);
476 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
478 union hdmi_infoframe frame;
481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
483 DRM_ERROR("couldn't fill SPD infoframe\n");
487 frame.spd.sdi = HDMI_SPD_SDI_PC;
489 intel_write_infoframe(encoder, &frame);
493 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
494 const struct drm_display_mode *adjusted_mode)
496 union hdmi_infoframe frame;
499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
504 intel_write_infoframe(encoder, &frame);
507 static void g4x_set_infoframes(struct drm_encoder *encoder,
509 const struct drm_display_mode *adjusted_mode)
511 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
514 i915_reg_t reg = VIDEO_DIP_CTL;
515 u32 val = I915_READ(reg);
516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
518 assert_hdmi_port_disabled(intel_hdmi);
520 /* If the registers were not initialized yet, they might be zeroes,
521 * which means we're selecting the AVI DIP and we're setting its
522 * frequency to once. This seems to really confuse the HW and make
523 * things stop working (the register spec says the AVI always needs to
524 * be sent every VSync). So here we avoid writing to the register more
525 * than we need and also explicitly select the AVI DIP and explicitly
526 * set its frequency to every VSync. Avoiding to write it twice seems to
527 * be enough to solve the problem, but being defensive shouldn't hurt us
529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
532 if (!(val & VIDEO_DIP_ENABLE))
534 if (port != (val & VIDEO_DIP_PORT_MASK)) {
535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
536 (val & VIDEO_DIP_PORT_MASK) >> 29);
539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
541 I915_WRITE(reg, val);
546 if (port != (val & VIDEO_DIP_PORT_MASK)) {
547 if (val & VIDEO_DIP_ENABLE) {
548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
549 (val & VIDEO_DIP_PORT_MASK) >> 29);
552 val &= ~VIDEO_DIP_PORT_MASK;
556 val |= VIDEO_DIP_ENABLE;
557 val &= ~(VIDEO_DIP_ENABLE_AVI |
558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
560 I915_WRITE(reg, val);
563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
564 intel_hdmi_set_spd_infoframe(encoder);
565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
568 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
570 struct drm_device *dev = encoder->dev;
571 struct drm_connector *connector;
573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
576 * HDMI cloning is only supported on g4x which doesn't
577 * support deep color or GCP infoframes anyway so no
578 * need to worry about multiple HDMI sinks here.
580 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
581 if (connector->encoder == encoder)
582 return connector->display_info.bpc > 8;
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
597 static bool gcp_default_phase_possible(int pipe_bpp,
598 const struct drm_display_mode *mode)
600 unsigned int pixels_per_group;
604 /* 4 pixels in 5 clocks */
605 pixels_per_group = 4;
608 /* 2 pixels in 3 clocks */
609 pixels_per_group = 2;
612 /* 1 pixel in 2 clocks */
613 pixels_per_group = 1;
616 /* phase information not relevant for 8bpc */
620 return mode->crtc_hdisplay % pixels_per_group == 0 &&
621 mode->crtc_htotal % pixels_per_group == 0 &&
622 mode->crtc_hblank_start % pixels_per_group == 0 &&
623 mode->crtc_hblank_end % pixels_per_group == 0 &&
624 mode->crtc_hsync_start % pixels_per_group == 0 &&
625 mode->crtc_hsync_end % pixels_per_group == 0 &&
626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
627 mode->crtc_htotal/2 % pixels_per_group == 0);
630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
632 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
637 if (HAS_DDI(dev_priv))
638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
641 else if (HAS_PCH_SPLIT(dev_priv))
642 reg = TVIDEO_DIP_GCP(crtc->pipe);
646 /* Indicate color depth whenever the sink supports deep color */
647 if (hdmi_sink_is_deep_color(encoder))
648 val |= GCP_COLOR_INDICATION;
650 /* Enable default_phase whenever the display mode is suitably aligned */
651 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
652 &crtc->config->base.adjusted_mode))
653 val |= GCP_DEFAULT_PHASE_ENABLE;
655 I915_WRITE(reg, val);
660 static void ibx_set_infoframes(struct drm_encoder *encoder,
662 const struct drm_display_mode *adjusted_mode)
664 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
669 u32 val = I915_READ(reg);
670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
672 assert_hdmi_port_disabled(intel_hdmi);
674 /* See the big comment in g4x_set_infoframes() */
675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
678 if (!(val & VIDEO_DIP_ENABLE))
680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
683 I915_WRITE(reg, val);
688 if (port != (val & VIDEO_DIP_PORT_MASK)) {
689 WARN(val & VIDEO_DIP_ENABLE,
690 "DIP already enabled on port %c\n",
691 (val & VIDEO_DIP_PORT_MASK) >> 29);
692 val &= ~VIDEO_DIP_PORT_MASK;
696 val |= VIDEO_DIP_ENABLE;
697 val &= ~(VIDEO_DIP_ENABLE_AVI |
698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
701 if (intel_hdmi_set_gcp_infoframe(encoder))
702 val |= VIDEO_DIP_ENABLE_GCP;
704 I915_WRITE(reg, val);
707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
708 intel_hdmi_set_spd_infoframe(encoder);
709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
712 static void cpt_set_infoframes(struct drm_encoder *encoder,
714 const struct drm_display_mode *adjusted_mode)
716 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
720 u32 val = I915_READ(reg);
722 assert_hdmi_port_disabled(intel_hdmi);
724 /* See the big comment in g4x_set_infoframes() */
725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
728 if (!(val & VIDEO_DIP_ENABLE))
730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
733 I915_WRITE(reg, val);
738 /* Set both together, unset both together: see the spec. */
739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
743 if (intel_hdmi_set_gcp_infoframe(encoder))
744 val |= VIDEO_DIP_ENABLE_GCP;
746 I915_WRITE(reg, val);
749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
750 intel_hdmi_set_spd_infoframe(encoder);
751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
754 static void vlv_set_infoframes(struct drm_encoder *encoder,
756 const struct drm_display_mode *adjusted_mode)
758 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
763 u32 val = I915_READ(reg);
764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
766 assert_hdmi_port_disabled(intel_hdmi);
768 /* See the big comment in g4x_set_infoframes() */
769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
772 if (!(val & VIDEO_DIP_ENABLE))
774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
777 I915_WRITE(reg, val);
782 if (port != (val & VIDEO_DIP_PORT_MASK)) {
783 WARN(val & VIDEO_DIP_ENABLE,
784 "DIP already enabled on port %c\n",
785 (val & VIDEO_DIP_PORT_MASK) >> 29);
786 val &= ~VIDEO_DIP_PORT_MASK;
790 val |= VIDEO_DIP_ENABLE;
791 val &= ~(VIDEO_DIP_ENABLE_AVI |
792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
795 if (intel_hdmi_set_gcp_infoframe(encoder))
796 val |= VIDEO_DIP_ENABLE_GCP;
798 I915_WRITE(reg, val);
801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
802 intel_hdmi_set_spd_infoframe(encoder);
803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
806 static void hsw_set_infoframes(struct drm_encoder *encoder,
808 const struct drm_display_mode *adjusted_mode)
810 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
814 u32 val = I915_READ(reg);
816 assert_hdmi_port_disabled(intel_hdmi);
818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
823 I915_WRITE(reg, val);
828 if (intel_hdmi_set_gcp_infoframe(encoder))
829 val |= VIDEO_DIP_ENABLE_GCP_HSW;
831 I915_WRITE(reg, val);
834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
835 intel_hdmi_set_spd_infoframe(encoder);
836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
839 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
841 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
842 struct i2c_adapter *adapter =
843 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
845 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
848 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
849 enable ? "Enabling" : "Disabling");
851 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
855 static void intel_hdmi_prepare(struct intel_encoder *encoder)
857 struct drm_device *dev = encoder->base.dev;
858 struct drm_i915_private *dev_priv = dev->dev_private;
859 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
860 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
861 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
864 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
866 hdmi_val = SDVO_ENCODING_HDMI;
867 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
868 hdmi_val |= HDMI_COLOR_RANGE_16_235;
869 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
870 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
871 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
872 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
874 if (crtc->config->pipe_bpp > 24)
875 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
877 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
879 if (crtc->config->has_hdmi_sink)
880 hdmi_val |= HDMI_MODE_SELECT_HDMI;
882 if (HAS_PCH_CPT(dev))
883 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
884 else if (IS_CHERRYVIEW(dev))
885 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
887 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
889 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
890 POSTING_READ(intel_hdmi->hdmi_reg);
893 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
896 struct drm_device *dev = encoder->base.dev;
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
899 enum intel_display_power_domain power_domain;
903 power_domain = intel_display_port_power_domain(encoder);
904 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
909 tmp = I915_READ(intel_hdmi->hdmi_reg);
911 if (!(tmp & SDVO_ENABLE))
914 if (HAS_PCH_CPT(dev))
915 *pipe = PORT_TO_PIPE_CPT(tmp);
916 else if (IS_CHERRYVIEW(dev))
917 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
919 *pipe = PORT_TO_PIPE(tmp);
924 intel_display_power_put(dev_priv, power_domain);
929 static void intel_hdmi_get_config(struct intel_encoder *encoder,
930 struct intel_crtc_state *pipe_config)
932 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
933 struct drm_device *dev = encoder->base.dev;
934 struct drm_i915_private *dev_priv = dev->dev_private;
938 tmp = I915_READ(intel_hdmi->hdmi_reg);
940 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
941 flags |= DRM_MODE_FLAG_PHSYNC;
943 flags |= DRM_MODE_FLAG_NHSYNC;
945 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
946 flags |= DRM_MODE_FLAG_PVSYNC;
948 flags |= DRM_MODE_FLAG_NVSYNC;
950 if (tmp & HDMI_MODE_SELECT_HDMI)
951 pipe_config->has_hdmi_sink = true;
953 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
954 pipe_config->has_infoframe = true;
956 if (tmp & SDVO_AUDIO_ENABLE)
957 pipe_config->has_audio = true;
959 if (!HAS_PCH_SPLIT(dev) &&
960 tmp & HDMI_COLOR_RANGE_16_235)
961 pipe_config->limited_color_range = true;
963 pipe_config->base.adjusted_mode.flags |= flags;
965 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
966 dotclock = pipe_config->port_clock * 2 / 3;
968 dotclock = pipe_config->port_clock;
970 if (pipe_config->pixel_multiplier)
971 dotclock /= pipe_config->pixel_multiplier;
973 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
975 pipe_config->lane_count = 4;
978 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
980 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
982 WARN_ON(!crtc->config->has_hdmi_sink);
983 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
984 pipe_name(crtc->pipe));
985 intel_audio_codec_enable(encoder);
988 static void g4x_enable_hdmi(struct intel_encoder *encoder)
990 struct drm_device *dev = encoder->base.dev;
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
993 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
996 temp = I915_READ(intel_hdmi->hdmi_reg);
999 if (crtc->config->has_audio)
1000 temp |= SDVO_AUDIO_ENABLE;
1002 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1003 POSTING_READ(intel_hdmi->hdmi_reg);
1005 if (crtc->config->has_audio)
1006 intel_enable_hdmi_audio(encoder);
1009 static void ibx_enable_hdmi(struct intel_encoder *encoder)
1011 struct drm_device *dev = encoder->base.dev;
1012 struct drm_i915_private *dev_priv = dev->dev_private;
1013 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1014 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1017 temp = I915_READ(intel_hdmi->hdmi_reg);
1019 temp |= SDVO_ENABLE;
1020 if (crtc->config->has_audio)
1021 temp |= SDVO_AUDIO_ENABLE;
1024 * HW workaround, need to write this twice for issue
1025 * that may result in first write getting masked.
1027 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1028 POSTING_READ(intel_hdmi->hdmi_reg);
1029 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1030 POSTING_READ(intel_hdmi->hdmi_reg);
1033 * HW workaround, need to toggle enable bit off and on
1034 * for 12bpc with pixel repeat.
1036 * FIXME: BSpec says this should be done at the end of
1037 * of the modeset sequence, so not sure if this isn't too soon.
1039 if (crtc->config->pipe_bpp > 24 &&
1040 crtc->config->pixel_multiplier > 1) {
1041 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1042 POSTING_READ(intel_hdmi->hdmi_reg);
1045 * HW workaround, need to write this twice for issue
1046 * that may result in first write getting masked.
1048 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1049 POSTING_READ(intel_hdmi->hdmi_reg);
1050 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1051 POSTING_READ(intel_hdmi->hdmi_reg);
1054 if (crtc->config->has_audio)
1055 intel_enable_hdmi_audio(encoder);
1058 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1060 struct drm_device *dev = encoder->base.dev;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1063 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1064 enum pipe pipe = crtc->pipe;
1067 temp = I915_READ(intel_hdmi->hdmi_reg);
1069 temp |= SDVO_ENABLE;
1070 if (crtc->config->has_audio)
1071 temp |= SDVO_AUDIO_ENABLE;
1074 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1076 * The procedure for 12bpc is as follows:
1077 * 1. disable HDMI clock gating
1078 * 2. enable HDMI with 8bpc
1079 * 3. enable HDMI with 12bpc
1080 * 4. enable HDMI clock gating
1083 if (crtc->config->pipe_bpp > 24) {
1084 I915_WRITE(TRANS_CHICKEN1(pipe),
1085 I915_READ(TRANS_CHICKEN1(pipe)) |
1086 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1088 temp &= ~SDVO_COLOR_FORMAT_MASK;
1089 temp |= SDVO_COLOR_FORMAT_8bpc;
1092 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1093 POSTING_READ(intel_hdmi->hdmi_reg);
1095 if (crtc->config->pipe_bpp > 24) {
1096 temp &= ~SDVO_COLOR_FORMAT_MASK;
1097 temp |= HDMI_COLOR_FORMAT_12bpc;
1099 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1100 POSTING_READ(intel_hdmi->hdmi_reg);
1102 I915_WRITE(TRANS_CHICKEN1(pipe),
1103 I915_READ(TRANS_CHICKEN1(pipe)) &
1104 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1107 if (crtc->config->has_audio)
1108 intel_enable_hdmi_audio(encoder);
1111 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1115 static void intel_disable_hdmi(struct intel_encoder *encoder)
1117 struct drm_device *dev = encoder->base.dev;
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1120 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1123 temp = I915_READ(intel_hdmi->hdmi_reg);
1125 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1126 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1127 POSTING_READ(intel_hdmi->hdmi_reg);
1130 * HW workaround for IBX, we need to move the port
1131 * to transcoder A after disabling it to allow the
1132 * matching DP port to be enabled on transcoder A.
1134 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1136 * We get CPU/PCH FIFO underruns on the other pipe when
1137 * doing the workaround. Sweep them under the rug.
1139 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1140 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1142 temp &= ~SDVO_PIPE_B_SELECT;
1143 temp |= SDVO_ENABLE;
1145 * HW workaround, need to write this twice for issue
1146 * that may result in first write getting masked.
1148 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1149 POSTING_READ(intel_hdmi->hdmi_reg);
1150 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1151 POSTING_READ(intel_hdmi->hdmi_reg);
1153 temp &= ~SDVO_ENABLE;
1154 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1155 POSTING_READ(intel_hdmi->hdmi_reg);
1157 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1158 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1159 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1162 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1164 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1167 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1169 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1171 if (crtc->config->has_audio)
1172 intel_audio_codec_disable(encoder);
1174 intel_disable_hdmi(encoder);
1177 static void pch_disable_hdmi(struct intel_encoder *encoder)
1179 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1181 if (crtc->config->has_audio)
1182 intel_audio_codec_disable(encoder);
1185 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1187 intel_disable_hdmi(encoder);
1190 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1192 if (IS_G4X(dev_priv))
1194 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1200 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1201 bool respect_downstream_limits)
1203 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1204 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1206 if (respect_downstream_limits) {
1207 if (hdmi->dp_dual_mode.max_tmds_clock)
1208 max_tmds_clock = min(max_tmds_clock,
1209 hdmi->dp_dual_mode.max_tmds_clock);
1210 if (!hdmi->has_hdmi_sink)
1211 max_tmds_clock = min(max_tmds_clock, 165000);
1214 return max_tmds_clock;
1217 static enum drm_mode_status
1218 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1219 int clock, bool respect_downstream_limits)
1221 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1224 return MODE_CLOCK_LOW;
1225 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
1226 return MODE_CLOCK_HIGH;
1228 /* BXT DPLL can't generate 223-240 MHz */
1229 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1230 return MODE_CLOCK_RANGE;
1232 /* CHV DPLL can't generate 216-240 MHz */
1233 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1234 return MODE_CLOCK_RANGE;
1239 static enum drm_mode_status
1240 intel_hdmi_mode_valid(struct drm_connector *connector,
1241 struct drm_display_mode *mode)
1243 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1244 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1245 enum drm_mode_status status;
1247 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1249 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1250 return MODE_NO_DBLESCAN;
1252 clock = mode->clock;
1254 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1257 if (clock > max_dotclk)
1258 return MODE_CLOCK_HIGH;
1260 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1263 /* check if we can do 8bpc */
1264 status = hdmi_port_clock_valid(hdmi, clock, true);
1266 /* if we can't do 8bpc we may still be able to do 12bpc */
1267 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1268 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1273 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1275 struct drm_device *dev = crtc_state->base.crtc->dev;
1276 struct drm_atomic_state *state;
1277 struct intel_encoder *encoder;
1278 struct drm_connector *connector;
1279 struct drm_connector_state *connector_state;
1280 int count = 0, count_hdmi = 0;
1283 if (HAS_GMCH_DISPLAY(dev))
1286 state = crtc_state->base.state;
1288 for_each_connector_in_state(state, connector, connector_state, i) {
1289 if (connector_state->crtc != crtc_state->base.crtc)
1292 encoder = to_intel_encoder(connector_state->best_encoder);
1294 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1299 * HDMI 12bpc affects the clocks, so it's only possible
1300 * when not cloning with other encoder types.
1302 return count_hdmi > 0 && count_hdmi == count;
1305 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1306 struct intel_crtc_state *pipe_config)
1308 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1309 struct drm_device *dev = encoder->base.dev;
1310 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1311 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1312 int clock_12bpc = clock_8bpc * 3 / 2;
1315 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1317 if (pipe_config->has_hdmi_sink)
1318 pipe_config->has_infoframe = true;
1320 if (intel_hdmi->color_range_auto) {
1321 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1322 pipe_config->limited_color_range =
1323 pipe_config->has_hdmi_sink &&
1324 drm_match_cea_mode(adjusted_mode) > 1;
1326 pipe_config->limited_color_range =
1327 intel_hdmi->limited_color_range;
1330 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1331 pipe_config->pixel_multiplier = 2;
1336 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1337 pipe_config->has_pch_encoder = true;
1339 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1340 pipe_config->has_audio = true;
1343 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1344 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1345 * outputs. We also need to check that the higher clock still fits
1348 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1349 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
1350 hdmi_12bpc_possible(pipe_config)) {
1351 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1354 /* Need to adjust the port link by 1.5x for 12bpc. */
1355 pipe_config->port_clock = clock_12bpc;
1357 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1360 pipe_config->port_clock = clock_8bpc;
1363 if (!pipe_config->bw_constrained) {
1364 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1365 pipe_config->pipe_bpp = desired_bpp;
1368 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1369 false) != MODE_OK) {
1370 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1374 /* Set user selected PAR to incoming mode's member */
1375 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1377 pipe_config->lane_count = 4;
1383 intel_hdmi_unset_edid(struct drm_connector *connector)
1385 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1387 intel_hdmi->has_hdmi_sink = false;
1388 intel_hdmi->has_audio = false;
1389 intel_hdmi->rgb_quant_range_selectable = false;
1391 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1392 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1394 kfree(to_intel_connector(connector)->detect_edid);
1395 to_intel_connector(connector)->detect_edid = NULL;
1399 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1401 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1402 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1403 enum port port = hdmi_to_dig_port(hdmi)->port;
1404 struct i2c_adapter *adapter =
1405 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1406 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1409 * Type 1 DVI adaptors are not required to implement any
1410 * registers, so we can't always detect their presence.
1411 * Ideally we should be able to check the state of the
1412 * CONFIG1 pin, but no such luck on our hardware.
1414 * The only method left to us is to check the VBT to see
1415 * if the port is a dual mode capable DP port. But let's
1416 * only do that when we sucesfully read the EDID, to avoid
1417 * confusing log messages about DP dual mode adaptors when
1418 * there's nothing connected to the port.
1420 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1422 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1423 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1424 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1426 type = DRM_DP_DUAL_MODE_NONE;
1430 if (type == DRM_DP_DUAL_MODE_NONE)
1433 hdmi->dp_dual_mode.type = type;
1434 hdmi->dp_dual_mode.max_tmds_clock =
1435 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1437 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1438 drm_dp_get_dual_mode_type_name(type),
1439 hdmi->dp_dual_mode.max_tmds_clock);
1443 intel_hdmi_set_edid(struct drm_connector *connector, bool force)
1445 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1446 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1447 struct edid *edid = NULL;
1448 bool connected = false;
1451 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1453 edid = drm_get_edid(connector,
1454 intel_gmbus_get_adapter(dev_priv,
1455 intel_hdmi->ddc_bus));
1457 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1459 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1462 to_intel_connector(connector)->detect_edid = edid;
1463 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1464 intel_hdmi->rgb_quant_range_selectable =
1465 drm_rgb_quant_range_selectable(edid);
1467 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1468 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1469 intel_hdmi->has_audio =
1470 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1472 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1473 intel_hdmi->has_hdmi_sink =
1474 drm_detect_hdmi_monitor(edid);
1482 static enum drm_connector_status
1483 intel_hdmi_detect(struct drm_connector *connector, bool force)
1485 enum drm_connector_status status;
1486 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1487 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1488 bool live_status = false;
1491 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1492 connector->base.id, connector->name);
1494 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1496 for (try = 0; !live_status && try < 9; try++) {
1499 live_status = intel_digital_port_connected(dev_priv,
1500 hdmi_to_dig_port(intel_hdmi));
1504 DRM_DEBUG_KMS("HDMI live status down\n");
1506 * Live status register is not reliable on all intel platforms.
1507 * So consider live_status only for certain platforms, for
1508 * others, read EDID to determine presence of sink.
1510 if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv))
1514 intel_hdmi_unset_edid(connector);
1516 if (intel_hdmi_set_edid(connector, live_status)) {
1517 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1519 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1520 status = connector_status_connected;
1522 status = connector_status_disconnected;
1524 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1530 intel_hdmi_force(struct drm_connector *connector)
1532 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1534 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1535 connector->base.id, connector->name);
1537 intel_hdmi_unset_edid(connector);
1539 if (connector->status != connector_status_connected)
1542 intel_hdmi_set_edid(connector, true);
1543 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1546 static int intel_hdmi_get_modes(struct drm_connector *connector)
1550 edid = to_intel_connector(connector)->detect_edid;
1554 return intel_connector_update_modes(connector, edid);
1558 intel_hdmi_detect_audio(struct drm_connector *connector)
1560 bool has_audio = false;
1563 edid = to_intel_connector(connector)->detect_edid;
1564 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1565 has_audio = drm_detect_monitor_audio(edid);
1571 intel_hdmi_set_property(struct drm_connector *connector,
1572 struct drm_property *property,
1575 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1576 struct intel_digital_port *intel_dig_port =
1577 hdmi_to_dig_port(intel_hdmi);
1578 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1581 ret = drm_object_property_set_value(&connector->base, property, val);
1585 if (property == dev_priv->force_audio_property) {
1586 enum hdmi_force_audio i = val;
1589 if (i == intel_hdmi->force_audio)
1592 intel_hdmi->force_audio = i;
1594 if (i == HDMI_AUDIO_AUTO)
1595 has_audio = intel_hdmi_detect_audio(connector);
1597 has_audio = (i == HDMI_AUDIO_ON);
1599 if (i == HDMI_AUDIO_OFF_DVI)
1600 intel_hdmi->has_hdmi_sink = 0;
1602 intel_hdmi->has_audio = has_audio;
1606 if (property == dev_priv->broadcast_rgb_property) {
1607 bool old_auto = intel_hdmi->color_range_auto;
1608 bool old_range = intel_hdmi->limited_color_range;
1611 case INTEL_BROADCAST_RGB_AUTO:
1612 intel_hdmi->color_range_auto = true;
1614 case INTEL_BROADCAST_RGB_FULL:
1615 intel_hdmi->color_range_auto = false;
1616 intel_hdmi->limited_color_range = false;
1618 case INTEL_BROADCAST_RGB_LIMITED:
1619 intel_hdmi->color_range_auto = false;
1620 intel_hdmi->limited_color_range = true;
1626 if (old_auto == intel_hdmi->color_range_auto &&
1627 old_range == intel_hdmi->limited_color_range)
1633 if (property == connector->dev->mode_config.aspect_ratio_property) {
1635 case DRM_MODE_PICTURE_ASPECT_NONE:
1636 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1638 case DRM_MODE_PICTURE_ASPECT_4_3:
1639 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1641 case DRM_MODE_PICTURE_ASPECT_16_9:
1642 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1653 if (intel_dig_port->base.base.crtc)
1654 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1659 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1661 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1662 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1663 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1665 intel_hdmi_prepare(encoder);
1667 intel_hdmi->set_infoframes(&encoder->base,
1668 intel_crtc->config->has_hdmi_sink,
1672 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1674 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1675 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1676 struct drm_device *dev = encoder->base.dev;
1677 struct drm_i915_private *dev_priv = dev->dev_private;
1678 struct intel_crtc *intel_crtc =
1679 to_intel_crtc(encoder->base.crtc);
1680 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1681 enum dpio_channel port = vlv_dport_to_channel(dport);
1682 int pipe = intel_crtc->pipe;
1685 /* Enable clock channels for this port */
1686 mutex_lock(&dev_priv->sb_lock);
1687 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1694 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1697 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1698 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1699 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1700 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1701 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1702 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1703 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1704 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1706 /* Program lane clock */
1707 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1708 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1709 mutex_unlock(&dev_priv->sb_lock);
1711 intel_hdmi->set_infoframes(&encoder->base,
1712 intel_crtc->config->has_hdmi_sink,
1715 g4x_enable_hdmi(encoder);
1717 vlv_wait_port_ready(dev_priv, dport, 0x0);
1720 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1722 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1723 struct drm_device *dev = encoder->base.dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 struct intel_crtc *intel_crtc =
1726 to_intel_crtc(encoder->base.crtc);
1727 enum dpio_channel port = vlv_dport_to_channel(dport);
1728 int pipe = intel_crtc->pipe;
1730 intel_hdmi_prepare(encoder);
1732 /* Program Tx lane resets to default */
1733 mutex_lock(&dev_priv->sb_lock);
1734 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1735 DPIO_PCS_TX_LANE2_RESET |
1736 DPIO_PCS_TX_LANE1_RESET);
1737 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1738 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1739 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1740 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1741 DPIO_PCS_CLK_SOFT_RESET);
1743 /* Fix up inter-pair skew failure */
1744 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1745 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1746 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1748 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1749 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1750 mutex_unlock(&dev_priv->sb_lock);
1753 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1756 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1757 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1758 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1759 enum pipe pipe = crtc->pipe;
1762 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1764 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1766 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1767 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1769 if (crtc->config->lane_count > 2) {
1770 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1772 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1774 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1775 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1778 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1779 val |= CHV_PCS_REQ_SOFTRESET_EN;
1781 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1783 val |= DPIO_PCS_CLK_SOFT_RESET;
1784 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1786 if (crtc->config->lane_count > 2) {
1787 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1788 val |= CHV_PCS_REQ_SOFTRESET_EN;
1790 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1792 val |= DPIO_PCS_CLK_SOFT_RESET;
1793 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1797 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1799 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1800 struct drm_device *dev = encoder->base.dev;
1801 struct drm_i915_private *dev_priv = dev->dev_private;
1802 struct intel_crtc *intel_crtc =
1803 to_intel_crtc(encoder->base.crtc);
1804 enum dpio_channel ch = vlv_dport_to_channel(dport);
1805 enum pipe pipe = intel_crtc->pipe;
1808 intel_hdmi_prepare(encoder);
1811 * Must trick the second common lane into life.
1812 * Otherwise we can't even access the PLL.
1814 if (ch == DPIO_CH0 && pipe == PIPE_B)
1815 dport->release_cl2_override =
1816 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1818 chv_phy_powergate_lanes(encoder, true, 0x0);
1820 mutex_lock(&dev_priv->sb_lock);
1822 /* Assert data lane reset */
1823 chv_data_lane_soft_reset(encoder, true);
1825 /* program left/right clock distribution */
1826 if (pipe != PIPE_B) {
1827 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1828 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1830 val |= CHV_BUFLEFTENA1_FORCE;
1832 val |= CHV_BUFRIGHTENA1_FORCE;
1833 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1835 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1836 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1838 val |= CHV_BUFLEFTENA2_FORCE;
1840 val |= CHV_BUFRIGHTENA2_FORCE;
1841 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1844 /* program clock channel usage */
1845 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1846 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1848 val &= ~CHV_PCS_USEDCLKCHANNEL;
1850 val |= CHV_PCS_USEDCLKCHANNEL;
1851 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1853 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1854 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1856 val &= ~CHV_PCS_USEDCLKCHANNEL;
1858 val |= CHV_PCS_USEDCLKCHANNEL;
1859 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1862 * This a a bit weird since generally CL
1863 * matches the pipe, but here we need to
1864 * pick the CL based on the port.
1866 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1868 val &= ~CHV_CMN_USEDCLKCHANNEL;
1870 val |= CHV_CMN_USEDCLKCHANNEL;
1871 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1873 mutex_unlock(&dev_priv->sb_lock);
1876 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1878 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1879 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1882 mutex_lock(&dev_priv->sb_lock);
1884 /* disable left/right clock distribution */
1885 if (pipe != PIPE_B) {
1886 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1887 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1888 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1890 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1891 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1892 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1895 mutex_unlock(&dev_priv->sb_lock);
1898 * Leave the power down bit cleared for at least one
1899 * lane so that chv_powergate_phy_ch() will power
1900 * on something when the channel is otherwise unused.
1901 * When the port is off and the override is removed
1902 * the lanes power down anyway, so otherwise it doesn't
1903 * really matter what the state of power down bits is
1906 chv_phy_powergate_lanes(encoder, false, 0x0);
1909 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1911 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1912 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1913 struct intel_crtc *intel_crtc =
1914 to_intel_crtc(encoder->base.crtc);
1915 enum dpio_channel port = vlv_dport_to_channel(dport);
1916 int pipe = intel_crtc->pipe;
1918 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1919 mutex_lock(&dev_priv->sb_lock);
1920 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1921 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1922 mutex_unlock(&dev_priv->sb_lock);
1925 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1927 struct drm_device *dev = encoder->base.dev;
1928 struct drm_i915_private *dev_priv = dev->dev_private;
1930 mutex_lock(&dev_priv->sb_lock);
1932 /* Assert data lane reset */
1933 chv_data_lane_soft_reset(encoder, true);
1935 mutex_unlock(&dev_priv->sb_lock);
1938 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1940 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1941 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1942 struct drm_device *dev = encoder->base.dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 struct intel_crtc *intel_crtc =
1945 to_intel_crtc(encoder->base.crtc);
1946 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1947 enum dpio_channel ch = vlv_dport_to_channel(dport);
1948 int pipe = intel_crtc->pipe;
1949 int data, i, stagger;
1952 mutex_lock(&dev_priv->sb_lock);
1954 /* allow hardware to manage TX FIFO reset source */
1955 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1956 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1957 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1959 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1960 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1961 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1963 /* Program Tx latency optimal setting */
1964 for (i = 0; i < 4; i++) {
1965 /* Set the upar bit */
1966 data = (i == 1) ? 0x0 : 0x1;
1967 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1968 data << DPIO_UPAR_SHIFT);
1971 /* Data lane stagger programming */
1972 if (intel_crtc->config->port_clock > 270000)
1974 else if (intel_crtc->config->port_clock > 135000)
1976 else if (intel_crtc->config->port_clock > 67500)
1978 else if (intel_crtc->config->port_clock > 33750)
1983 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1984 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1985 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1987 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1988 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1989 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1991 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1992 DPIO_LANESTAGGER_STRAP(stagger) |
1993 DPIO_LANESTAGGER_STRAP_OVRD |
1994 DPIO_TX1_STAGGER_MASK(0x1f) |
1995 DPIO_TX1_STAGGER_MULT(6) |
1996 DPIO_TX2_STAGGER_MULT(0));
1998 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1999 DPIO_LANESTAGGER_STRAP(stagger) |
2000 DPIO_LANESTAGGER_STRAP_OVRD |
2001 DPIO_TX1_STAGGER_MASK(0x1f) |
2002 DPIO_TX1_STAGGER_MULT(7) |
2003 DPIO_TX2_STAGGER_MULT(5));
2005 /* Deassert data lane reset */
2006 chv_data_lane_soft_reset(encoder, false);
2008 /* Clear calc init */
2009 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2010 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2011 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2012 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
2013 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2015 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2016 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2017 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2018 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
2019 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2021 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2022 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2023 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2024 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2026 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2027 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2028 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2029 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2031 /* FIXME: Program the support xxx V-dB */
2033 for (i = 0; i < 4; i++) {
2034 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2035 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2036 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
2037 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2040 for (i = 0; i < 4; i++) {
2041 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2043 val &= ~DPIO_SWING_MARGIN000_MASK;
2044 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
2047 * Supposedly this value shouldn't matter when unique transition
2048 * scale is disabled, but in fact it does matter. Let's just
2049 * always program the same value and hope it's OK.
2051 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2052 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
2054 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2058 * The document said it needs to set bit 27 for ch0 and bit 26
2059 * for ch1. Might be a typo in the doc.
2060 * For now, for this unique transition scale selection, set bit
2061 * 27 for ch0 and ch1.
2063 for (i = 0; i < 4; i++) {
2064 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2065 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2066 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2069 /* Start swing calculation */
2070 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2071 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2072 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2074 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2075 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2076 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2078 mutex_unlock(&dev_priv->sb_lock);
2080 intel_hdmi->set_infoframes(&encoder->base,
2081 intel_crtc->config->has_hdmi_sink,
2084 g4x_enable_hdmi(encoder);
2086 vlv_wait_port_ready(dev_priv, dport, 0x0);
2088 /* Second common lane will stay alive on its own now */
2089 if (dport->release_cl2_override) {
2090 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2091 dport->release_cl2_override = false;
2095 static void intel_hdmi_destroy(struct drm_connector *connector)
2097 kfree(to_intel_connector(connector)->detect_edid);
2098 drm_connector_cleanup(connector);
2102 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2103 .dpms = drm_atomic_helper_connector_dpms,
2104 .detect = intel_hdmi_detect,
2105 .force = intel_hdmi_force,
2106 .fill_modes = drm_helper_probe_single_connector_modes,
2107 .set_property = intel_hdmi_set_property,
2108 .atomic_get_property = intel_connector_atomic_get_property,
2109 .destroy = intel_hdmi_destroy,
2110 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2111 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2114 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2115 .get_modes = intel_hdmi_get_modes,
2116 .mode_valid = intel_hdmi_mode_valid,
2117 .best_encoder = intel_best_encoder,
2120 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2121 .destroy = intel_encoder_destroy,
2125 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2127 intel_attach_force_audio_property(connector);
2128 intel_attach_broadcast_rgb_property(connector);
2129 intel_hdmi->color_range_auto = true;
2130 intel_attach_aspect_ratio_property(connector);
2131 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2134 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2135 struct intel_connector *intel_connector)
2137 struct drm_connector *connector = &intel_connector->base;
2138 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2139 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2140 struct drm_device *dev = intel_encoder->base.dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 enum port port = intel_dig_port->port;
2143 uint8_t alternate_ddc_pin;
2145 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2148 if (WARN(intel_dig_port->max_lanes < 4,
2149 "Not enough lanes (%d) for HDMI on port %c\n",
2150 intel_dig_port->max_lanes, port_name(port)))
2153 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2154 DRM_MODE_CONNECTOR_HDMIA);
2155 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2157 connector->interlace_allowed = 1;
2158 connector->doublescan_allowed = 0;
2159 connector->stereo_allowed = 1;
2163 if (IS_BROXTON(dev_priv))
2164 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2166 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2168 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2169 * interrupts to check the external panel connection.
2171 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
2172 intel_encoder->hpd_pin = HPD_PORT_A;
2174 intel_encoder->hpd_pin = HPD_PORT_B;
2177 if (IS_BROXTON(dev_priv))
2178 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2180 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2181 intel_encoder->hpd_pin = HPD_PORT_C;
2184 if (WARN_ON(IS_BROXTON(dev_priv)))
2185 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2186 else if (IS_CHERRYVIEW(dev_priv))
2187 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
2189 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2190 intel_encoder->hpd_pin = HPD_PORT_D;
2193 /* On SKL PORT E doesn't have seperate GMBUS pin
2194 * We rely on VBT to set a proper alternate GMBUS pin. */
2196 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2197 switch (alternate_ddc_pin) {
2199 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2202 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2205 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2208 MISSING_CASE(alternate_ddc_pin);
2210 intel_encoder->hpd_pin = HPD_PORT_E;
2213 intel_encoder->hpd_pin = HPD_PORT_A;
2214 /* Internal port only for eDP. */
2219 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2220 intel_hdmi->write_infoframe = vlv_write_infoframe;
2221 intel_hdmi->set_infoframes = vlv_set_infoframes;
2222 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2223 } else if (IS_G4X(dev)) {
2224 intel_hdmi->write_infoframe = g4x_write_infoframe;
2225 intel_hdmi->set_infoframes = g4x_set_infoframes;
2226 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2227 } else if (HAS_DDI(dev)) {
2228 intel_hdmi->write_infoframe = hsw_write_infoframe;
2229 intel_hdmi->set_infoframes = hsw_set_infoframes;
2230 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2231 } else if (HAS_PCH_IBX(dev)) {
2232 intel_hdmi->write_infoframe = ibx_write_infoframe;
2233 intel_hdmi->set_infoframes = ibx_set_infoframes;
2234 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2236 intel_hdmi->write_infoframe = cpt_write_infoframe;
2237 intel_hdmi->set_infoframes = cpt_set_infoframes;
2238 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2242 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2244 intel_connector->get_hw_state = intel_connector_get_hw_state;
2245 intel_connector->unregister = intel_connector_unregister;
2247 intel_hdmi_add_properties(intel_hdmi, connector);
2249 intel_connector_attach_encoder(intel_connector, intel_encoder);
2250 drm_connector_register(connector);
2251 intel_hdmi->attached_connector = intel_connector;
2253 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2254 * 0xd. Failure to do so will result in spurious interrupts being
2255 * generated on the port when a cable is not attached.
2257 if (IS_G4X(dev) && !IS_GM45(dev)) {
2258 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2259 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2263 void intel_hdmi_init(struct drm_device *dev,
2264 i915_reg_t hdmi_reg, enum port port)
2266 struct intel_digital_port *intel_dig_port;
2267 struct intel_encoder *intel_encoder;
2268 struct intel_connector *intel_connector;
2270 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2271 if (!intel_dig_port)
2274 intel_connector = intel_connector_alloc();
2275 if (!intel_connector) {
2276 kfree(intel_dig_port);
2280 intel_encoder = &intel_dig_port->base;
2282 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2283 DRM_MODE_ENCODER_TMDS, NULL);
2285 intel_encoder->compute_config = intel_hdmi_compute_config;
2286 if (HAS_PCH_SPLIT(dev)) {
2287 intel_encoder->disable = pch_disable_hdmi;
2288 intel_encoder->post_disable = pch_post_disable_hdmi;
2290 intel_encoder->disable = g4x_disable_hdmi;
2292 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2293 intel_encoder->get_config = intel_hdmi_get_config;
2294 if (IS_CHERRYVIEW(dev)) {
2295 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2296 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2297 intel_encoder->enable = vlv_enable_hdmi;
2298 intel_encoder->post_disable = chv_hdmi_post_disable;
2299 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2300 } else if (IS_VALLEYVIEW(dev)) {
2301 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2302 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2303 intel_encoder->enable = vlv_enable_hdmi;
2304 intel_encoder->post_disable = vlv_hdmi_post_disable;
2306 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2307 if (HAS_PCH_CPT(dev))
2308 intel_encoder->enable = cpt_enable_hdmi;
2309 else if (HAS_PCH_IBX(dev))
2310 intel_encoder->enable = ibx_enable_hdmi;
2312 intel_encoder->enable = g4x_enable_hdmi;
2315 intel_encoder->type = INTEL_OUTPUT_HDMI;
2316 if (IS_CHERRYVIEW(dev)) {
2318 intel_encoder->crtc_mask = 1 << 2;
2320 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2322 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2324 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2326 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2327 * to work on real hardware. And since g4x can send infoframes to
2328 * only one port anyway, nothing is lost by allowing it.
2331 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2333 intel_dig_port->port = port;
2334 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2335 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2336 intel_dig_port->max_lanes = 4;
2338 intel_hdmi_init_connector(intel_dig_port, intel_connector);