2 * Copyright © 2014 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "i915_gem_render_state.h"
140 #include "i915_vgpu.h"
141 #include "intel_lrc_reg.h"
142 #include "intel_mocs.h"
143 #include "intel_workarounds.h"
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
162 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
163 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
164 #define WA_TAIL_DWORDS 2
165 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
167 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
168 struct intel_engine_cs *engine,
169 struct intel_context *ce);
170 static void execlists_init_reg_state(u32 *reg_state,
171 struct i915_gem_context *ctx,
172 struct intel_engine_cs *engine,
173 struct intel_ring *ring);
175 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
177 return rb_entry(rb, struct i915_priolist, node);
180 static inline int rq_prio(const struct i915_request *rq)
182 return rq->sched.attr.priority;
185 static inline bool need_preempt(const struct intel_engine_cs *engine,
186 const struct i915_request *last,
189 return (intel_engine_has_preemption(engine) &&
190 __execlists_need_preempt(prio, rq_prio(last)) &&
191 !i915_request_completed(last));
195 * The context descriptor encodes various attributes of a context,
196 * including its GTT address and some flags. Because it's fairly
197 * expensive to calculate, we'll just do it once and cache the result,
198 * which remains valid until the context is unpinned.
200 * This is what a descriptor looks like, from LSB to MSB::
202 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
203 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
204 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
205 * bits 53-54: mbz, reserved for use by hardware
206 * bits 55-63: group ID, currently unused and set to 0
208 * Starting from Gen11, the upper dword of the descriptor has a new format:
210 * bits 32-36: reserved
211 * bits 37-47: SW context ID
212 * bits 48:53: engine instance
213 * bit 54: mbz, reserved for use by hardware
214 * bits 55-60: SW counter
215 * bits 61-63: engine class
217 * engine info, SW context ID and SW counter need to form a unique number
218 * (Context ID) per lrc.
221 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
222 struct intel_engine_cs *engine,
223 struct intel_context *ce)
227 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
228 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
230 desc = ctx->desc_template; /* bits 0-11 */
231 GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
233 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
235 GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
238 * The following 32bits are copied into the OA reports (dword 2).
239 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
242 if (INTEL_GEN(ctx->i915) >= 11) {
243 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
244 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
247 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
250 /* TODO: decide what to do with SW counter (bits 55-60) */
252 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
255 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
256 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
262 static void unwind_wa_tail(struct i915_request *rq)
264 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
265 assert_ring_tail_valid(rq->ring, rq->tail);
268 static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
270 struct i915_request *rq, *rn, *active = NULL;
271 struct list_head *uninitialized_var(pl);
272 int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
274 lockdep_assert_held(&engine->timeline.lock);
276 list_for_each_entry_safe_reverse(rq, rn,
277 &engine->timeline.requests,
279 if (i915_request_completed(rq))
282 __i915_request_unsubmit(rq);
285 GEM_BUG_ON(rq->hw_context->active);
287 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
288 if (rq_prio(rq) != prio) {
290 pl = i915_sched_lookup_priolist(engine, prio);
292 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
294 list_add(&rq->sched.link, pl);
300 * The active request is now effectively the start of a new client
301 * stream, so give it the equivalent small priority bump to prevent
302 * it being gazumped a second time by another peer.
304 if (!(prio & I915_PRIORITY_NEWCLIENT)) {
305 prio |= I915_PRIORITY_NEWCLIENT;
306 list_move_tail(&active->sched.link,
307 i915_sched_lookup_priolist(engine, prio));
312 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
314 struct intel_engine_cs *engine =
315 container_of(execlists, typeof(*engine), execlists);
317 __unwind_incomplete_requests(engine);
321 execlists_context_status_change(struct i915_request *rq, unsigned long status)
324 * Only used when GVT-g is enabled now. When GVT-g is disabled,
325 * The compiler should eliminate this function as dead-code.
327 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
330 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
335 execlists_user_begin(struct intel_engine_execlists *execlists,
336 const struct execlist_port *port)
338 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
342 execlists_user_end(struct intel_engine_execlists *execlists)
344 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
348 execlists_context_schedule_in(struct i915_request *rq)
350 GEM_BUG_ON(rq->hw_context->active);
352 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
353 intel_engine_context_in(rq->engine);
354 rq->hw_context->active = rq->engine;
358 execlists_context_schedule_out(struct i915_request *rq, unsigned long status)
360 rq->hw_context->active = NULL;
361 intel_engine_context_out(rq->engine);
362 execlists_context_status_change(rq, status);
363 trace_i915_request_out(rq);
367 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
369 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
370 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
371 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
372 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
375 static u64 execlists_update_context(struct i915_request *rq)
377 struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
378 struct intel_context *ce = rq->hw_context;
379 u32 *reg_state = ce->lrc_reg_state;
381 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
384 * True 32b PPGTT with dynamic page allocation: update PDP
385 * registers and point the unallocated PDPs to scratch page.
386 * PML4 is allocated during ppgtt init, so this is not needed
389 if (!i915_vm_is_48bit(&ppgtt->vm))
390 execlists_update_context_pdps(ppgtt, reg_state);
393 * Make sure the context image is complete before we submit it to HW.
395 * Ostensibly, writes (including the WCB) should be flushed prior to
396 * an uncached write such as our mmio register access, the empirical
397 * evidence (esp. on Braswell) suggests that the WC write into memory
398 * may not be visible to the HW prior to the completion of the UC
399 * register write and that we may begin execution from the context
400 * before its image is complete leading to invalid PD chasing.
406 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
408 if (execlists->ctrl_reg) {
409 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
410 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
412 writel(upper_32_bits(desc), execlists->submit_reg);
413 writel(lower_32_bits(desc), execlists->submit_reg);
417 static void execlists_submit_ports(struct intel_engine_cs *engine)
419 struct intel_engine_execlists *execlists = &engine->execlists;
420 struct execlist_port *port = execlists->port;
424 * We can skip acquiring intel_runtime_pm_get() here as it was taken
425 * on our behalf by the request (see i915_gem_mark_busy()) and it will
426 * not be relinquished until the device is idle (see
427 * i915_gem_idle_work_handler()). As a precaution, we make sure
428 * that all ELSP are drained i.e. we have processed the CSB,
429 * before allowing ourselves to idle and calling intel_runtime_pm_put().
431 GEM_BUG_ON(!engine->i915->gt.awake);
434 * ELSQ note: the submit queue is not cleared after being submitted
435 * to the HW so we need to make sure we always clean it up. This is
436 * currently ensured by the fact that we always write the same number
437 * of elsq entries, keep this in mind before changing the loop below.
439 for (n = execlists_num_ports(execlists); n--; ) {
440 struct i915_request *rq;
444 rq = port_unpack(&port[n], &count);
446 GEM_BUG_ON(count > !n);
448 execlists_context_schedule_in(rq);
449 port_set(&port[n], port_pack(rq, count));
450 desc = execlists_update_context(rq);
451 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
453 GEM_TRACE("%s in[%d]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
455 port[n].context_id, count,
457 rq->fence.context, rq->fence.seqno,
458 intel_engine_get_seqno(engine),
465 write_desc(execlists, desc, n);
468 /* we need to manually load the submit queue */
469 if (execlists->ctrl_reg)
470 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
472 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
475 static bool ctx_single_port_submission(const struct intel_context *ce)
477 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
478 i915_gem_context_force_single_submission(ce->gem_context));
481 static bool can_merge_ctx(const struct intel_context *prev,
482 const struct intel_context *next)
487 if (ctx_single_port_submission(prev))
493 static void port_assign(struct execlist_port *port, struct i915_request *rq)
495 GEM_BUG_ON(rq == port_request(port));
497 if (port_isset(port))
498 i915_request_put(port_request(port));
500 port_set(port, port_pack(i915_request_get(rq), port_count(port)));
503 static void inject_preempt_context(struct intel_engine_cs *engine)
505 struct intel_engine_execlists *execlists = &engine->execlists;
506 struct intel_context *ce =
507 to_intel_context(engine->i915->preempt_context, engine);
510 GEM_BUG_ON(execlists->preempt_complete_status !=
511 upper_32_bits(ce->lrc_desc));
514 * Switch to our empty preempt context so
515 * the state of the GPU is known (idle).
517 GEM_TRACE("%s\n", engine->name);
518 for (n = execlists_num_ports(execlists); --n; )
519 write_desc(execlists, 0, n);
521 write_desc(execlists, ce->lrc_desc, n);
523 /* we need to manually load the submit queue */
524 if (execlists->ctrl_reg)
525 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
527 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
528 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
531 static void complete_preempt_context(struct intel_engine_execlists *execlists)
533 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
535 if (inject_preempt_hang(execlists))
538 execlists_cancel_port_requests(execlists);
539 __unwind_incomplete_requests(container_of(execlists,
540 struct intel_engine_cs,
544 static void execlists_dequeue(struct intel_engine_cs *engine)
546 struct intel_engine_execlists * const execlists = &engine->execlists;
547 struct execlist_port *port = execlists->port;
548 const struct execlist_port * const last_port =
549 &execlists->port[execlists->port_mask];
550 struct i915_request *last = port_request(port);
555 * Hardware submission is through 2 ports. Conceptually each port
556 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
557 * static for a context, and unique to each, so we only execute
558 * requests belonging to a single context from each ring. RING_HEAD
559 * is maintained by the CS in the context image, it marks the place
560 * where it got up to last time, and through RING_TAIL we tell the CS
561 * where we want to execute up to this time.
563 * In this list the requests are in order of execution. Consecutive
564 * requests from the same context are adjacent in the ringbuffer. We
565 * can combine these requests into a single RING_TAIL update:
567 * RING_HEAD...req1...req2
569 * since to execute req2 the CS must first execute req1.
571 * Our goal then is to point each port to the end of a consecutive
572 * sequence of requests as being the most optimal (fewest wake ups
573 * and context switches) submission.
578 * Don't resubmit or switch until all outstanding
579 * preemptions (lite-restore) are seen. Then we
580 * know the next preemption status we see corresponds
581 * to this ELSP update.
583 GEM_BUG_ON(!execlists_is_active(execlists,
584 EXECLISTS_ACTIVE_USER));
585 GEM_BUG_ON(!port_count(&port[0]));
588 * If we write to ELSP a second time before the HW has had
589 * a chance to respond to the previous write, we can confuse
590 * the HW and hit "undefined behaviour". After writing to ELSP,
591 * we must then wait until we see a context-switch event from
592 * the HW to indicate that it has had a chance to respond.
594 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
597 if (need_preempt(engine, last, execlists->queue_priority)) {
598 inject_preempt_context(engine);
603 * In theory, we could coalesce more requests onto
604 * the second port (the first port is active, with
605 * no preemptions pending). However, that means we
606 * then have to deal with the possible lite-restore
607 * of the second port (as we submit the ELSP, there
608 * may be a context-switch) but also we may complete
609 * the resubmission before the context-switch. Ergo,
610 * coalescing onto the second port will cause a
611 * preemption event, but we cannot predict whether
612 * that will affect port[0] or port[1].
614 * If the second port is already active, we can wait
615 * until the next context-switch before contemplating
616 * new requests. The GPU will be busy and we should be
617 * able to resubmit the new ELSP before it idles,
618 * avoiding pipeline bubbles (momentary pauses where
619 * the driver is unable to keep up the supply of new
620 * work). However, we have to double check that the
621 * priorities of the ports haven't been switch.
623 if (port_count(&port[1]))
627 * WaIdleLiteRestore:bdw,skl
628 * Apply the wa NOOPs to prevent
629 * ring:HEAD == rq:TAIL as we resubmit the
630 * request. See gen8_emit_breadcrumb() for
631 * where we prepare the padding after the
632 * end of the request.
634 last->tail = last->wa_tail;
637 while ((rb = rb_first_cached(&execlists->queue))) {
638 struct i915_priolist *p = to_priolist(rb);
639 struct i915_request *rq, *rn;
642 priolist_for_each_request_consume(rq, rn, p, i) {
644 * Can we combine this request with the current port?
645 * It has to be the same context/ringbuffer and not
646 * have any exceptions (e.g. GVT saying never to
649 * If we can combine the requests, we can execute both
650 * by updating the RING_TAIL to point to the end of the
651 * second request, and so we never need to tell the
652 * hardware about the first.
655 !can_merge_ctx(rq->hw_context, last->hw_context)) {
657 * If we are on the second port and cannot
658 * combine this request with the last, then we
661 if (port == last_port)
665 * If GVT overrides us we only ever submit
666 * port[0], leaving port[1] empty. Note that we
667 * also have to be careful that we don't queue
668 * the same context (even though a different
669 * request) to the second port.
671 if (ctx_single_port_submission(last->hw_context) ||
672 ctx_single_port_submission(rq->hw_context))
675 GEM_BUG_ON(last->hw_context == rq->hw_context);
678 port_assign(port, last);
681 GEM_BUG_ON(port_isset(port));
684 list_del_init(&rq->sched.link);
686 __i915_request_submit(rq);
687 trace_i915_request_in(rq, port_index(port, execlists));
693 rb_erase_cached(&p->node, &execlists->queue);
694 if (p->priority != I915_PRIORITY_NORMAL)
695 kmem_cache_free(engine->i915->priorities, p);
700 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
702 * We choose queue_priority such that if we add a request of greater
703 * priority than this, we kick the submission tasklet to decide on
704 * the right order of submitting the requests to hardware. We must
705 * also be prepared to reorder requests as they are in-flight on the
706 * HW. We derive the queue_priority then as the first "hole" in
707 * the HW submission ports and if there are no available slots,
708 * the priority of the lowest executing request, i.e. last.
710 * When we do receive a higher priority request ready to run from the
711 * user, see queue_request(), the queue_priority is bumped to that
712 * request triggering preemption on the next dequeue (or subsequent
713 * interrupt for secondary ports).
715 execlists->queue_priority =
716 port != execlists->port ? rq_prio(last) : INT_MIN;
719 port_assign(port, last);
720 execlists_submit_ports(engine);
723 /* We must always keep the beast fed if we have work piled up */
724 GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
725 !port_isset(execlists->port));
727 /* Re-evaluate the executing context setup after each preemptive kick */
729 execlists_user_begin(execlists, execlists->port);
731 /* If the engine is now idle, so should be the flag; and vice versa. */
732 GEM_BUG_ON(execlists_is_active(&engine->execlists,
733 EXECLISTS_ACTIVE_USER) ==
734 !port_isset(engine->execlists.port));
738 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
740 struct execlist_port *port = execlists->port;
741 unsigned int num_ports = execlists_num_ports(execlists);
743 while (num_ports-- && port_isset(port)) {
744 struct i915_request *rq = port_request(port);
746 GEM_TRACE("%s:port%u global=%d (fence %llx:%d), (current %d)\n",
748 (unsigned int)(port - execlists->port),
750 rq->fence.context, rq->fence.seqno,
751 intel_engine_get_seqno(rq->engine));
753 GEM_BUG_ON(!execlists->active);
754 execlists_context_schedule_out(rq,
755 i915_request_completed(rq) ?
756 INTEL_CONTEXT_SCHEDULE_OUT :
757 INTEL_CONTEXT_SCHEDULE_PREEMPTED);
759 i915_request_put(rq);
761 memset(port, 0, sizeof(*port));
765 execlists_clear_all_active(execlists);
768 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
771 * After a reset, the HW starts writing into CSB entry [0]. We
772 * therefore have to set our HEAD pointer back one entry so that
773 * the *first* entry we check is entry 0. To complicate this further,
774 * as we don't wait for the first interrupt after reset, we have to
775 * fake the HW write to point back to the last entry so that our
776 * inline comparison of our cached head position against the last HW
777 * write works even before the first interrupt.
779 execlists->csb_head = execlists->csb_write_reset;
780 WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
783 static void nop_submission_tasklet(unsigned long data)
785 /* The driver is wedged; don't process any more events. */
788 static void execlists_cancel_requests(struct intel_engine_cs *engine)
790 struct intel_engine_execlists * const execlists = &engine->execlists;
791 struct i915_request *rq, *rn;
795 GEM_TRACE("%s current %d\n",
796 engine->name, intel_engine_get_seqno(engine));
799 * Before we call engine->cancel_requests(), we should have exclusive
800 * access to the submission state. This is arranged for us by the
801 * caller disabling the interrupt generation, the tasklet and other
802 * threads that may then access the same state, giving us a free hand
803 * to reset state. However, we still need to let lockdep be aware that
804 * we know this state may be accessed in hardirq context, so we
805 * disable the irq around this manipulation and we want to keep
806 * the spinlock focused on its duties and not accidentally conflate
807 * coverage to the submission's irq state. (Similarly, although we
808 * shouldn't need to disable irq around the manipulation of the
809 * submission's irq state, we also wish to remind ourselves that
812 spin_lock_irqsave(&engine->timeline.lock, flags);
814 /* Cancel the requests on the HW and clear the ELSP tracker. */
815 execlists_cancel_port_requests(execlists);
816 execlists_user_end(execlists);
818 /* Mark all executing requests as skipped. */
819 list_for_each_entry(rq, &engine->timeline.requests, link) {
820 GEM_BUG_ON(!rq->global_seqno);
821 if (!i915_request_completed(rq))
822 dma_fence_set_error(&rq->fence, -EIO);
825 /* Flush the queued requests to the timeline list (for retiring). */
826 while ((rb = rb_first_cached(&execlists->queue))) {
827 struct i915_priolist *p = to_priolist(rb);
830 priolist_for_each_request_consume(rq, rn, p, i) {
831 list_del_init(&rq->sched.link);
833 dma_fence_set_error(&rq->fence, -EIO);
834 __i915_request_submit(rq);
837 rb_erase_cached(&p->node, &execlists->queue);
838 if (p->priority != I915_PRIORITY_NORMAL)
839 kmem_cache_free(engine->i915->priorities, p);
842 /* Remaining _unready_ requests will be nop'ed when submitted */
844 execlists->queue_priority = INT_MIN;
845 execlists->queue = RB_ROOT_CACHED;
846 GEM_BUG_ON(port_isset(execlists->port));
848 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
849 execlists->tasklet.func = nop_submission_tasklet;
851 spin_unlock_irqrestore(&engine->timeline.lock, flags);
855 reset_in_progress(const struct intel_engine_execlists *execlists)
857 return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
860 static void process_csb(struct intel_engine_cs *engine)
862 struct intel_engine_execlists * const execlists = &engine->execlists;
863 struct execlist_port *port = execlists->port;
864 const u32 * const buf = execlists->csb_status;
868 * Note that csb_write, csb_status may be either in HWSP or mmio.
869 * When reading from the csb_write mmio register, we have to be
870 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
871 * the low 4bits. As it happens we know the next 4bits are always
872 * zero and so we can simply masked off the low u8 of the register
873 * and treat it identically to reading from the HWSP (without having
874 * to use explicit shifting and masking, and probably bifurcating
875 * the code to handle the legacy mmio read).
877 head = execlists->csb_head;
878 tail = READ_ONCE(*execlists->csb_write);
879 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
880 if (unlikely(head == tail))
884 * Hopefully paired with a wmb() in HW!
886 * We must complete the read of the write pointer before any reads
887 * from the CSB, so that we do not see stale values. Without an rmb
888 * (lfence) the HW may speculatively perform the CSB[] reads *before*
889 * we perform the READ_ONCE(*csb_write).
894 struct i915_request *rq;
898 if (++head == GEN8_CSB_ENTRIES)
902 * We are flying near dragons again.
904 * We hold a reference to the request in execlist_port[]
905 * but no more than that. We are operating in softirq
906 * context and so cannot hold any mutex or sleep. That
907 * prevents us stopping the requests we are processing
908 * in port[] from being retired simultaneously (the
909 * breadcrumb will be complete before we see the
910 * context-switch). As we only hold the reference to the
911 * request, any pointer chasing underneath the request
912 * is subject to a potential use-after-free. Thus we
913 * store all of the bookkeeping within port[] as
914 * required, and avoid using unguarded pointers beneath
915 * request itself. The same applies to the atomic
919 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
921 buf[2 * head + 0], buf[2 * head + 1],
924 status = buf[2 * head];
925 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
926 GEN8_CTX_STATUS_PREEMPTED))
927 execlists_set_active(execlists,
928 EXECLISTS_ACTIVE_HWACK);
929 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
930 execlists_clear_active(execlists,
931 EXECLISTS_ACTIVE_HWACK);
933 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
936 /* We should never get a COMPLETED | IDLE_ACTIVE! */
937 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
939 if (status & GEN8_CTX_STATUS_COMPLETE &&
940 buf[2*head + 1] == execlists->preempt_complete_status) {
941 GEM_TRACE("%s preempt-idle\n", engine->name);
942 complete_preempt_context(execlists);
946 if (status & GEN8_CTX_STATUS_PREEMPTED &&
947 execlists_is_active(execlists,
948 EXECLISTS_ACTIVE_PREEMPT))
951 GEM_BUG_ON(!execlists_is_active(execlists,
952 EXECLISTS_ACTIVE_USER));
954 rq = port_unpack(port, &count);
955 GEM_TRACE("%s out[0]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
957 port->context_id, count,
958 rq ? rq->global_seqno : 0,
959 rq ? rq->fence.context : 0,
960 rq ? rq->fence.seqno : 0,
961 intel_engine_get_seqno(engine),
962 rq ? rq_prio(rq) : 0);
964 /* Check the context/desc id for this event matches */
965 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
967 GEM_BUG_ON(count == 0);
970 * On the final event corresponding to the
971 * submission of this context, we expect either
972 * an element-switch event or a completion
973 * event (and on completion, the active-idle
974 * marker). No more preemptions, lite-restore
977 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
978 GEM_BUG_ON(port_isset(&port[1]) &&
979 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
980 GEM_BUG_ON(!port_isset(&port[1]) &&
981 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
984 * We rely on the hardware being strongly
985 * ordered, that the breadcrumb write is
986 * coherent (visible from the CPU) before the
987 * user interrupt and CSB is processed.
989 GEM_BUG_ON(!i915_request_completed(rq));
991 execlists_context_schedule_out(rq,
992 INTEL_CONTEXT_SCHEDULE_OUT);
993 i915_request_put(rq);
995 GEM_TRACE("%s completed ctx=%d\n",
996 engine->name, port->context_id);
998 port = execlists_port_complete(execlists, port);
999 if (port_isset(port))
1000 execlists_user_begin(execlists, port);
1002 execlists_user_end(execlists);
1004 port_set(port, port_pack(rq, count));
1006 } while (head != tail);
1008 execlists->csb_head = head;
1011 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
1013 lockdep_assert_held(&engine->timeline.lock);
1015 process_csb(engine);
1016 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))
1017 execlists_dequeue(engine);
1021 * Check the unread Context Status Buffers and manage the submission of new
1022 * contexts to the ELSP accordingly.
1024 static void execlists_submission_tasklet(unsigned long data)
1026 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1027 unsigned long flags;
1029 GEM_TRACE("%s awake?=%d, active=%x\n",
1031 engine->i915->gt.awake,
1032 engine->execlists.active);
1034 spin_lock_irqsave(&engine->timeline.lock, flags);
1035 __execlists_submission_tasklet(engine);
1036 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1039 static void queue_request(struct intel_engine_cs *engine,
1040 struct i915_sched_node *node,
1043 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio));
1046 static void __submit_queue_imm(struct intel_engine_cs *engine)
1048 struct intel_engine_execlists * const execlists = &engine->execlists;
1050 if (reset_in_progress(execlists))
1051 return; /* defer until we restart the engine following reset */
1053 if (execlists->tasklet.func == execlists_submission_tasklet)
1054 __execlists_submission_tasklet(engine);
1056 tasklet_hi_schedule(&execlists->tasklet);
1059 static void submit_queue(struct intel_engine_cs *engine, int prio)
1061 if (prio > engine->execlists.queue_priority) {
1062 engine->execlists.queue_priority = prio;
1063 __submit_queue_imm(engine);
1067 static void execlists_submit_request(struct i915_request *request)
1069 struct intel_engine_cs *engine = request->engine;
1070 unsigned long flags;
1072 /* Will be called from irq-context when using foreign fences. */
1073 spin_lock_irqsave(&engine->timeline.lock, flags);
1075 queue_request(engine, &request->sched, rq_prio(request));
1077 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1078 GEM_BUG_ON(list_empty(&request->sched.link));
1080 submit_queue(engine, rq_prio(request));
1082 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1085 static void execlists_context_destroy(struct intel_context *ce)
1087 GEM_BUG_ON(ce->pin_count);
1092 intel_ring_free(ce->ring);
1094 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1095 i915_gem_object_put(ce->state->obj);
1098 static void execlists_context_unpin(struct intel_context *ce)
1100 struct intel_engine_cs *engine;
1103 * The tasklet may still be using a pointer to our state, via an
1104 * old request. However, since we know we only unpin the context
1105 * on retirement of the following request, we know that the last
1106 * request referencing us will have had a completion CS interrupt.
1107 * If we see that it is still active, it means that the tasklet hasn't
1108 * had the chance to run yet; let it run before we teardown the
1109 * reference it may use.
1111 engine = READ_ONCE(ce->active);
1112 if (unlikely(engine)) {
1113 unsigned long flags;
1115 spin_lock_irqsave(&engine->timeline.lock, flags);
1116 process_csb(engine);
1117 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1119 GEM_BUG_ON(READ_ONCE(ce->active));
1122 i915_gem_context_unpin_hw_id(ce->gem_context);
1124 intel_ring_unpin(ce->ring);
1126 ce->state->obj->pin_global--;
1127 i915_gem_object_unpin_map(ce->state->obj);
1128 i915_vma_unpin(ce->state);
1130 i915_gem_context_put(ce->gem_context);
1133 static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
1139 * Clear this page out of any CPU caches for coherent swap-in/out.
1140 * We only want to do this on the first bind so that we do not stall
1141 * on an active context (which by nature is already on the GPU).
1143 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1144 err = i915_gem_object_set_to_wc_domain(vma->obj, true);
1149 flags = PIN_GLOBAL | PIN_HIGH;
1150 flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
1152 return i915_vma_pin(vma, 0, 0, flags);
1155 static struct intel_context *
1156 __execlists_context_pin(struct intel_engine_cs *engine,
1157 struct i915_gem_context *ctx,
1158 struct intel_context *ce)
1163 ret = execlists_context_deferred_alloc(ctx, engine, ce);
1166 GEM_BUG_ON(!ce->state);
1168 ret = __context_pin(ctx, ce->state);
1172 vaddr = i915_gem_object_pin_map(ce->state->obj,
1173 i915_coherent_map_type(ctx->i915) |
1175 if (IS_ERR(vaddr)) {
1176 ret = PTR_ERR(vaddr);
1180 ret = intel_ring_pin(ce->ring);
1184 ret = i915_gem_context_pin_hw_id(ctx);
1188 intel_lr_context_descriptor_update(ctx, engine, ce);
1190 GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
1192 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1193 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1194 i915_ggtt_offset(ce->ring->vma);
1195 ce->lrc_reg_state[CTX_RING_HEAD + 1] = ce->ring->head;
1196 ce->lrc_reg_state[CTX_RING_TAIL + 1] = ce->ring->tail;
1198 ce->state->obj->pin_global++;
1199 i915_gem_context_get(ctx);
1203 intel_ring_unpin(ce->ring);
1205 i915_gem_object_unpin_map(ce->state->obj);
1207 __i915_vma_unpin(ce->state);
1210 return ERR_PTR(ret);
1213 static const struct intel_context_ops execlists_context_ops = {
1214 .unpin = execlists_context_unpin,
1215 .destroy = execlists_context_destroy,
1218 static struct intel_context *
1219 execlists_context_pin(struct intel_engine_cs *engine,
1220 struct i915_gem_context *ctx)
1222 struct intel_context *ce = to_intel_context(ctx, engine);
1224 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1225 GEM_BUG_ON(!ctx->ppgtt);
1227 if (likely(ce->pin_count++))
1229 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1231 ce->ops = &execlists_context_ops;
1233 return __execlists_context_pin(engine, ctx, ce);
1236 static int execlists_request_alloc(struct i915_request *request)
1240 GEM_BUG_ON(!request->hw_context->pin_count);
1242 /* Flush enough space to reduce the likelihood of waiting after
1243 * we start building the request - in which case we will just
1244 * have to repeat work.
1246 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1248 ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1252 /* Note that after this point, we have committed to using
1253 * this request as it is being used to both track the
1254 * state of engine initialisation and liveness of the
1255 * golden renderstate above. Think twice before you try
1256 * to cancel/unwind this request now.
1259 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1264 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1265 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1266 * but there is a slight complication as this is applied in WA batch where the
1267 * values are only initialized once so we cannot take register value at the
1268 * beginning and reuse it further; hence we save its value to memory, upload a
1269 * constant value with bit21 set and then we restore it back with the saved value.
1270 * To simplify the WA, a constant value is formed by using the default value
1271 * of this register. This shouldn't be a problem because we are only modifying
1272 * it for a short period and this batch in non-premptible. We can ofcourse
1273 * use additional instructions that read the actual value of the register
1274 * at that time and set our bit of interest but it makes the WA complicated.
1276 * This WA is also required for Gen9 so extracting as a function avoids
1280 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1282 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1283 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1284 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1287 *batch++ = MI_LOAD_REGISTER_IMM(1);
1288 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1289 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1291 batch = gen8_emit_pipe_control(batch,
1292 PIPE_CONTROL_CS_STALL |
1293 PIPE_CONTROL_DC_FLUSH_ENABLE,
1296 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1297 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1298 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1305 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1306 * initialized at the beginning and shared across all contexts but this field
1307 * helps us to have multiple batches at different offsets and select them based
1308 * on a criteria. At the moment this batch always start at the beginning of the page
1309 * and at this point we don't have multiple wa_ctx batch buffers.
1311 * The number of WA applied are not known at the beginning; we use this field
1312 * to return the no of DWORDS written.
1314 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1315 * so it adds NOOPs as padding to make it cacheline aligned.
1316 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1317 * makes a complete batch buffer.
1319 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1321 /* WaDisableCtxRestoreArbitration:bdw,chv */
1322 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1324 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1325 if (IS_BROADWELL(engine->i915))
1326 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1328 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1329 /* Actual scratch location is at 128 bytes offset */
1330 batch = gen8_emit_pipe_control(batch,
1331 PIPE_CONTROL_FLUSH_L3 |
1332 PIPE_CONTROL_GLOBAL_GTT_IVB |
1333 PIPE_CONTROL_CS_STALL |
1334 PIPE_CONTROL_QW_WRITE,
1335 i915_ggtt_offset(engine->scratch) +
1336 2 * CACHELINE_BYTES);
1338 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1340 /* Pad to end of cacheline */
1341 while ((unsigned long)batch % CACHELINE_BYTES)
1345 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1346 * execution depends on the length specified in terms of cache lines
1347 * in the register CTX_RCS_INDIRECT_CTX
1358 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1360 GEM_BUG_ON(!count || count > 63);
1362 *batch++ = MI_LOAD_REGISTER_IMM(count);
1364 *batch++ = i915_mmio_reg_offset(lri->reg);
1365 *batch++ = lri->value;
1366 } while (lri++, --count);
1372 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1374 static const struct lri lri[] = {
1375 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1377 COMMON_SLICE_CHICKEN2,
1378 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1385 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1386 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1392 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1393 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1397 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1399 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1400 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1402 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1404 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1405 if (HAS_POOLED_EU(engine->i915)) {
1407 * EU pool configuration is setup along with golden context
1408 * during context initialization. This value depends on
1409 * device type (2x6 or 3x6) and needs to be updated based
1410 * on which subslice is disabled especially for 2x6
1411 * devices, however it is safe to load default
1412 * configuration of 3x6 device instead of masking off
1413 * corresponding bits because HW ignores bits of a disabled
1414 * subslice and drops down to appropriate config. Please
1415 * see render_state_setup() in i915_gem_render_state.c for
1416 * possible configurations, to avoid duplication they are
1417 * not shown here again.
1419 *batch++ = GEN9_MEDIA_POOL_STATE;
1420 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1421 *batch++ = 0x00777000;
1427 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1429 /* Pad to end of cacheline */
1430 while ((unsigned long)batch % CACHELINE_BYTES)
1437 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1442 * WaPipeControlBefore3DStateSamplePattern: cnl
1444 * Ensure the engine is idle prior to programming a
1445 * 3DSTATE_SAMPLE_PATTERN during a context restore.
1447 batch = gen8_emit_pipe_control(batch,
1448 PIPE_CONTROL_CS_STALL,
1451 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
1452 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
1453 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
1454 * confusing. Since gen8_emit_pipe_control() already advances the
1455 * batch by 6 dwords, we advance the other 10 here, completing a
1456 * cacheline. It's not clear if the workaround requires this padding
1457 * before other commands, or if it's just the regular padding we would
1458 * already have for the workaround bb, so leave it here for now.
1460 for (i = 0; i < 10; i++)
1463 /* Pad to end of cacheline */
1464 while ((unsigned long)batch % CACHELINE_BYTES)
1470 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1472 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1474 struct drm_i915_gem_object *obj;
1475 struct i915_vma *vma;
1478 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1480 return PTR_ERR(obj);
1482 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
1488 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
1492 engine->wa_ctx.vma = vma;
1496 i915_gem_object_put(obj);
1500 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1502 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1505 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1507 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1509 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1510 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1512 wa_bb_func_t wa_bb_fn[2];
1514 void *batch, *batch_ptr;
1518 if (GEM_DEBUG_WARN_ON(engine->id != RCS))
1521 switch (INTEL_GEN(engine->i915)) {
1525 wa_bb_fn[0] = gen10_init_indirectctx_bb;
1529 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1533 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1537 MISSING_CASE(INTEL_GEN(engine->i915));
1541 ret = lrc_setup_wa_ctx(engine);
1543 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1547 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1548 batch = batch_ptr = kmap_atomic(page);
1551 * Emit the two workaround batch buffers, recording the offset from the
1552 * start of the workaround batch buffer object for each and their
1555 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1556 wa_bb[i]->offset = batch_ptr - batch;
1557 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1558 CACHELINE_BYTES))) {
1563 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1564 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1567 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1569 kunmap_atomic(batch);
1571 lrc_destroy_wa_ctx(engine);
1576 static void enable_execlists(struct intel_engine_cs *engine)
1578 struct drm_i915_private *dev_priv = engine->i915;
1580 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1583 * Make sure we're not enabling the new 12-deep CSB
1584 * FIFO as that requires a slightly updated handling
1585 * in the ctx switch irq. Since we're currently only
1586 * using only 2 elements of the enhanced execlists the
1587 * deeper FIFO it's not needed and it's not worth adding
1588 * more statements to the irq handler to support it.
1590 if (INTEL_GEN(dev_priv) >= 11)
1591 I915_WRITE(RING_MODE_GEN7(engine),
1592 _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
1594 I915_WRITE(RING_MODE_GEN7(engine),
1595 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1597 I915_WRITE(RING_MI_MODE(engine->mmio_base),
1598 _MASKED_BIT_DISABLE(STOP_RING));
1600 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1601 engine->status_page.ggtt_offset);
1602 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1605 static bool unexpected_starting_state(struct intel_engine_cs *engine)
1607 struct drm_i915_private *dev_priv = engine->i915;
1608 bool unexpected = false;
1610 if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
1611 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
1618 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1620 intel_mocs_init_engine(engine);
1622 intel_engine_reset_breadcrumbs(engine);
1624 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
1625 struct drm_printer p = drm_debug_printer(__func__);
1627 intel_engine_dump(engine, &p, NULL);
1630 enable_execlists(engine);
1635 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1637 struct drm_i915_private *dev_priv = engine->i915;
1640 ret = gen8_init_common_ring(engine);
1644 intel_whitelist_workarounds_apply(engine);
1646 /* We need to disable the AsyncFlip performance optimisations in order
1647 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1648 * programmed to '1' on all products.
1650 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1652 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1654 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1659 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1663 ret = gen8_init_common_ring(engine);
1667 intel_whitelist_workarounds_apply(engine);
1672 static struct i915_request *
1673 execlists_reset_prepare(struct intel_engine_cs *engine)
1675 struct intel_engine_execlists * const execlists = &engine->execlists;
1676 struct i915_request *request, *active;
1677 unsigned long flags;
1679 GEM_TRACE("%s: depth<-%d\n", engine->name,
1680 atomic_read(&execlists->tasklet.count));
1683 * Prevent request submission to the hardware until we have
1684 * completed the reset in i915_gem_reset_finish(). If a request
1685 * is completed by one engine, it may then queue a request
1686 * to a second via its execlists->tasklet *just* as we are
1687 * calling engine->init_hw() and also writing the ELSP.
1688 * Turning off the execlists->tasklet until the reset is over
1689 * prevents the race.
1691 __tasklet_disable_sync_once(&execlists->tasklet);
1693 spin_lock_irqsave(&engine->timeline.lock, flags);
1696 * We want to flush the pending context switches, having disabled
1697 * the tasklet above, we can assume exclusive access to the execlists.
1698 * For this allows us to catch up with an inflight preemption event,
1699 * and avoid blaming an innocent request if the stall was due to the
1700 * preemption itself.
1702 process_csb(engine);
1705 * The last active request can then be no later than the last request
1706 * now in ELSP[0]. So search backwards from there, so that if the GPU
1707 * has advanced beyond the last CSB update, it will be pardoned.
1710 request = port_request(execlists->port);
1713 * Prevent the breadcrumb from advancing before we decide
1714 * which request is currently active.
1716 intel_engine_stop_cs(engine);
1718 list_for_each_entry_from_reverse(request,
1719 &engine->timeline.requests,
1721 if (__i915_request_completed(request,
1722 request->global_seqno))
1729 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1734 static void execlists_reset(struct intel_engine_cs *engine,
1735 struct i915_request *request)
1737 struct intel_engine_execlists * const execlists = &engine->execlists;
1738 unsigned long flags;
1741 GEM_TRACE("%s request global=%d, current=%d\n",
1742 engine->name, request ? request->global_seqno : 0,
1743 intel_engine_get_seqno(engine));
1745 spin_lock_irqsave(&engine->timeline.lock, flags);
1748 * Catch up with any missed context-switch interrupts.
1750 * Ideally we would just read the remaining CSB entries now that we
1751 * know the gpu is idle. However, the CSB registers are sometimes^W
1752 * often trashed across a GPU reset! Instead we have to rely on
1753 * guessing the missed context-switch events by looking at what
1754 * requests were completed.
1756 execlists_cancel_port_requests(execlists);
1758 /* Push back any incomplete requests for replay after the reset. */
1759 __unwind_incomplete_requests(engine);
1761 /* Following the reset, we need to reload the CSB read/write pointers */
1762 reset_csb_pointers(&engine->execlists);
1764 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1767 * If the request was innocent, we leave the request in the ELSP
1768 * and will try to replay it on restarting. The context image may
1769 * have been corrupted by the reset, in which case we may have
1770 * to service a new GPU hang, but more likely we can continue on
1773 * If the request was guilty, we presume the context is corrupt
1774 * and have to at least restore the RING register in the context
1775 * image back to the expected values to skip over the guilty request.
1777 if (!request || request->fence.error != -EIO)
1781 * We want a simple context + ring to execute the breadcrumb update.
1782 * We cannot rely on the context being intact across the GPU hang,
1783 * so clear it and rebuild just what we need for the breadcrumb.
1784 * All pending requests for this context will be zapped, and any
1785 * future request will be after userspace has had the opportunity
1786 * to recreate its own state.
1788 regs = request->hw_context->lrc_reg_state;
1789 if (engine->pinned_default_state) {
1790 memcpy(regs, /* skip restoring the vanilla PPHWSP */
1791 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
1792 engine->context_size - PAGE_SIZE);
1794 execlists_init_reg_state(regs,
1795 request->gem_context, engine, request->ring);
1797 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1798 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
1800 request->ring->head = intel_ring_wrap(request->ring, request->postfix);
1801 regs[CTX_RING_HEAD + 1] = request->ring->head;
1803 intel_ring_update_space(request->ring);
1805 /* Reset WaIdleLiteRestore:bdw,skl as well */
1806 unwind_wa_tail(request);
1809 static void execlists_reset_finish(struct intel_engine_cs *engine)
1811 struct intel_engine_execlists * const execlists = &engine->execlists;
1814 * After a GPU reset, we may have requests to replay. Do so now while
1815 * we still have the forcewake to be sure that the GPU is not allowed
1816 * to sleep before we restart and reload a context.
1819 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
1820 execlists->tasklet.func(execlists->tasklet.data);
1822 tasklet_enable(&execlists->tasklet);
1823 GEM_TRACE("%s: depth->%d\n", engine->name,
1824 atomic_read(&execlists->tasklet.count));
1827 static int intel_logical_ring_emit_pdps(struct i915_request *rq)
1829 struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
1830 struct intel_engine_cs *engine = rq->engine;
1831 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
1835 cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2);
1839 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
1840 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
1841 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1843 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1844 *cs++ = upper_32_bits(pd_daddr);
1845 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1846 *cs++ = lower_32_bits(pd_daddr);
1850 intel_ring_advance(rq, cs);
1855 static int gen8_emit_bb_start(struct i915_request *rq,
1856 u64 offset, u32 len,
1857 const unsigned int flags)
1862 /* Don't rely in hw updating PDPs, specially in lite-restore.
1863 * Ideally, we should set Force PD Restore in ctx descriptor,
1864 * but we can't. Force Restore would be a second option, but
1865 * it is unsafe in case of lite-restore (because the ctx is
1866 * not idle). PML4 is allocated during ppgtt init so this is
1867 * not needed in 48-bit.*/
1868 if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
1869 !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
1870 !intel_vgpu_active(rq->i915)) {
1871 ret = intel_logical_ring_emit_pdps(rq);
1875 rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine);
1878 cs = intel_ring_begin(rq, 6);
1883 * WaDisableCtxRestoreArbitration:bdw,chv
1885 * We don't need to perform MI_ARB_ENABLE as often as we do (in
1886 * particular all the gen that do not need the w/a at all!), if we
1887 * took care to make sure that on every switch into this context
1888 * (both ordinary and for preemption) that arbitrartion was enabled
1889 * we would be fine. However, there doesn't seem to be a downside to
1890 * being paranoid and making sure it is set before each batch and
1891 * every context-switch.
1893 * Note that if we fail to enable arbitration before the request
1894 * is complete, then we do not see the context-switch interrupt and
1895 * the engine hangs (with RING_HEAD == RING_TAIL).
1897 * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
1899 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1901 /* FIXME(BDW): Address space and security selectors. */
1902 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
1903 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
1904 *cs++ = lower_32_bits(offset);
1905 *cs++ = upper_32_bits(offset);
1907 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1909 intel_ring_advance(rq, cs);
1914 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1916 struct drm_i915_private *dev_priv = engine->i915;
1917 I915_WRITE_IMR(engine,
1918 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1919 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1922 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1924 struct drm_i915_private *dev_priv = engine->i915;
1925 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1928 static int gen8_emit_flush(struct i915_request *request, u32 mode)
1932 cs = intel_ring_begin(request, 4);
1936 cmd = MI_FLUSH_DW + 1;
1938 /* We always require a command barrier so that subsequent
1939 * commands, such as breadcrumb interrupts, are strictly ordered
1940 * wrt the contents of the write cache being flushed to memory
1941 * (and thus being coherent from the CPU).
1943 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1945 if (mode & EMIT_INVALIDATE) {
1946 cmd |= MI_INVALIDATE_TLB;
1947 if (request->engine->class == VIDEO_DECODE_CLASS)
1948 cmd |= MI_INVALIDATE_BSD;
1952 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1953 *cs++ = 0; /* upper addr */
1954 *cs++ = 0; /* value */
1955 intel_ring_advance(request, cs);
1960 static int gen8_emit_flush_render(struct i915_request *request,
1963 struct intel_engine_cs *engine = request->engine;
1965 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1966 bool vf_flush_wa = false, dc_flush_wa = false;
1970 flags |= PIPE_CONTROL_CS_STALL;
1972 if (mode & EMIT_FLUSH) {
1973 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1974 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1975 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1976 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1979 if (mode & EMIT_INVALIDATE) {
1980 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1981 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1982 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1983 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1984 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1985 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1986 flags |= PIPE_CONTROL_QW_WRITE;
1987 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1990 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1993 if (IS_GEN9(request->i915))
1996 /* WaForGAMHang:kbl */
1997 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
2009 cs = intel_ring_begin(request, len);
2014 cs = gen8_emit_pipe_control(cs, 0, 0);
2017 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
2020 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2023 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
2025 intel_ring_advance(request, cs);
2031 * Reserve space for 2 NOOPs at the end of each request to be
2032 * used as a workaround for not being allowed to do lite
2033 * restore with HEAD==TAIL (WaIdleLiteRestore).
2035 static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
2037 /* Ensure there's always at least one preemption point per-request. */
2038 *cs++ = MI_ARB_CHECK;
2040 request->wa_tail = intel_ring_offset(request, cs);
2043 static void gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
2045 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
2046 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
2048 cs = gen8_emit_ggtt_write(cs, request->global_seqno,
2049 intel_hws_seqno_address(request->engine));
2050 *cs++ = MI_USER_INTERRUPT;
2051 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2052 request->tail = intel_ring_offset(request, cs);
2053 assert_ring_tail_valid(request->ring, request->tail);
2055 gen8_emit_wa_tail(request, cs);
2057 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
2059 static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
2061 /* We're using qword write, seqno should be aligned to 8 bytes. */
2062 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
2064 cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,
2065 intel_hws_seqno_address(request->engine));
2066 *cs++ = MI_USER_INTERRUPT;
2067 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2068 request->tail = intel_ring_offset(request, cs);
2069 assert_ring_tail_valid(request->ring, request->tail);
2071 gen8_emit_wa_tail(request, cs);
2073 static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
2075 static int gen8_init_rcs_context(struct i915_request *rq)
2079 ret = intel_ctx_workarounds_emit(rq);
2083 ret = intel_rcs_context_init_mocs(rq);
2085 * Failing to program the MOCS is non-fatal.The system will not
2086 * run at peak performance. So generate an error and carry on.
2089 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2091 return i915_gem_render_state_emit(rq);
2095 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2096 * @engine: Engine Command Streamer.
2098 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2100 struct drm_i915_private *dev_priv;
2103 * Tasklet cannot be active at this point due intel_mark_active/idle
2104 * so this is just for documentation.
2106 if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
2107 &engine->execlists.tasklet.state)))
2108 tasklet_kill(&engine->execlists.tasklet);
2110 dev_priv = engine->i915;
2112 if (engine->buffer) {
2113 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2116 if (engine->cleanup)
2117 engine->cleanup(engine);
2119 intel_engine_cleanup_common(engine);
2121 lrc_destroy_wa_ctx(engine);
2123 engine->i915 = NULL;
2124 dev_priv->engine[engine->id] = NULL;
2128 void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
2130 engine->submit_request = execlists_submit_request;
2131 engine->cancel_requests = execlists_cancel_requests;
2132 engine->schedule = i915_schedule;
2133 engine->execlists.tasklet.func = execlists_submission_tasklet;
2135 engine->reset.prepare = execlists_reset_prepare;
2137 engine->park = NULL;
2138 engine->unpark = NULL;
2140 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2141 if (engine->i915->preempt_context)
2142 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
2144 engine->i915->caps.scheduler =
2145 I915_SCHEDULER_CAP_ENABLED |
2146 I915_SCHEDULER_CAP_PRIORITY;
2147 if (intel_engine_has_preemption(engine))
2148 engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
2152 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
2154 /* Default vfuncs which can be overriden by each engine. */
2155 engine->init_hw = gen8_init_common_ring;
2157 engine->reset.prepare = execlists_reset_prepare;
2158 engine->reset.reset = execlists_reset;
2159 engine->reset.finish = execlists_reset_finish;
2161 engine->context_pin = execlists_context_pin;
2162 engine->request_alloc = execlists_request_alloc;
2164 engine->emit_flush = gen8_emit_flush;
2165 engine->emit_breadcrumb = gen8_emit_breadcrumb;
2166 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
2168 engine->set_default_submission = intel_execlists_set_default_submission;
2170 if (INTEL_GEN(engine->i915) < 11) {
2171 engine->irq_enable = gen8_logical_ring_enable_irq;
2172 engine->irq_disable = gen8_logical_ring_disable_irq;
2175 * TODO: On Gen11 interrupt masks need to be clear
2176 * to allow C6 entry. Keep interrupts enabled at
2177 * and take the hit of generating extra interrupts
2178 * until a more refined solution exists.
2181 engine->emit_bb_start = gen8_emit_bb_start;
2185 logical_ring_default_irqs(struct intel_engine_cs *engine)
2187 unsigned int shift = 0;
2189 if (INTEL_GEN(engine->i915) < 11) {
2190 const u8 irq_shifts[] = {
2191 [RCS] = GEN8_RCS_IRQ_SHIFT,
2192 [BCS] = GEN8_BCS_IRQ_SHIFT,
2193 [VCS] = GEN8_VCS1_IRQ_SHIFT,
2194 [VCS2] = GEN8_VCS2_IRQ_SHIFT,
2195 [VECS] = GEN8_VECS_IRQ_SHIFT,
2198 shift = irq_shifts[engine->id];
2201 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2202 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2206 logical_ring_setup(struct intel_engine_cs *engine)
2208 intel_engine_setup_common(engine);
2210 /* Intentionally left blank. */
2211 engine->buffer = NULL;
2213 tasklet_init(&engine->execlists.tasklet,
2214 execlists_submission_tasklet, (unsigned long)engine);
2216 logical_ring_default_vfuncs(engine);
2217 logical_ring_default_irqs(engine);
2220 static bool csb_force_mmio(struct drm_i915_private *i915)
2222 /* Older GVT emulation depends upon intercepting CSB mmio */
2223 return intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915);
2226 static int logical_ring_init(struct intel_engine_cs *engine)
2228 struct drm_i915_private *i915 = engine->i915;
2229 struct intel_engine_execlists * const execlists = &engine->execlists;
2232 ret = intel_engine_init_common(engine);
2236 if (HAS_LOGICAL_RING_ELSQ(i915)) {
2237 execlists->submit_reg = i915->regs +
2238 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
2239 execlists->ctrl_reg = i915->regs +
2240 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
2242 execlists->submit_reg = i915->regs +
2243 i915_mmio_reg_offset(RING_ELSP(engine));
2246 execlists->preempt_complete_status = ~0u;
2247 if (i915->preempt_context) {
2248 struct intel_context *ce =
2249 to_intel_context(i915->preempt_context, engine);
2251 execlists->preempt_complete_status =
2252 upper_32_bits(ce->lrc_desc);
2255 execlists->csb_read =
2256 i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
2257 if (csb_force_mmio(i915)) {
2258 execlists->csb_status = (u32 __force *)
2259 (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
2261 execlists->csb_write = (u32 __force *)execlists->csb_read;
2262 execlists->csb_write_reset =
2263 _MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK,
2264 GEN8_CSB_ENTRIES - 1);
2266 execlists->csb_status =
2267 &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
2269 execlists->csb_write =
2270 &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
2271 execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1;
2273 reset_csb_pointers(execlists);
2278 int logical_render_ring_init(struct intel_engine_cs *engine)
2280 struct drm_i915_private *dev_priv = engine->i915;
2283 logical_ring_setup(engine);
2285 if (HAS_L3_DPF(dev_priv))
2286 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2288 /* Override some for render ring. */
2289 if (INTEL_GEN(dev_priv) >= 9)
2290 engine->init_hw = gen9_init_render_ring;
2292 engine->init_hw = gen8_init_render_ring;
2293 engine->init_context = gen8_init_rcs_context;
2294 engine->emit_flush = gen8_emit_flush_render;
2295 engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
2296 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
2298 ret = logical_ring_init(engine);
2302 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2304 goto err_cleanup_common;
2306 ret = intel_init_workaround_bb(engine);
2309 * We continue even if we fail to initialize WA batch
2310 * because we only expect rare glitches but nothing
2311 * critical to prevent us from using GPU
2313 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2320 intel_engine_cleanup_common(engine);
2324 int logical_xcs_ring_init(struct intel_engine_cs *engine)
2326 logical_ring_setup(engine);
2328 return logical_ring_init(engine);
2332 make_rpcs(struct drm_i915_private *dev_priv)
2334 bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
2335 u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
2336 u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
2340 * No explicit RPCS request is needed to ensure full
2341 * slice/subslice/EU enablement prior to Gen9.
2343 if (INTEL_GEN(dev_priv) < 9)
2347 * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits
2348 * wide and Icelake has up to eight subslices, specfial programming is
2349 * needed in order to correctly enable all subslices.
2351 * According to documentation software must consider the configuration
2352 * as 2x4x8 and hardware will translate this to 1x8x8.
2354 * Furthemore, even though SScount is three bits, maximum documented
2355 * value for it is four. From this some rules/restrictions follow:
2358 * If enabled subslice count is greater than four, two whole slices must
2359 * be enabled instead.
2362 * When more than one slice is enabled, hardware ignores the subslice
2365 * From these restrictions it follows that it is not possible to enable
2366 * a count of subslices between the SScount maximum of four restriction,
2367 * and the maximum available number on a particular SKU. Either all
2368 * subslices are enabled, or a count between one and four on the first
2371 if (IS_GEN11(dev_priv) && slices == 1 && subslices >= 4) {
2372 GEM_BUG_ON(subslices & 1);
2374 subslice_pg = false;
2379 * Starting in Gen9, render power gating can leave
2380 * slice/subslice/EU in a partially enabled state. We
2381 * must make an explicit request through RPCS for full
2384 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
2385 u32 mask, val = slices;
2387 if (INTEL_GEN(dev_priv) >= 11) {
2388 mask = GEN11_RPCS_S_CNT_MASK;
2389 val <<= GEN11_RPCS_S_CNT_SHIFT;
2391 mask = GEN8_RPCS_S_CNT_MASK;
2392 val <<= GEN8_RPCS_S_CNT_SHIFT;
2395 GEM_BUG_ON(val & ~mask);
2398 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val;
2402 u32 val = subslices;
2404 val <<= GEN8_RPCS_SS_CNT_SHIFT;
2406 GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK);
2407 val &= GEN8_RPCS_SS_CNT_MASK;
2409 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
2412 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2415 val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2416 GEN8_RPCS_EU_MIN_SHIFT;
2417 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
2418 val &= GEN8_RPCS_EU_MIN_MASK;
2422 val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2423 GEN8_RPCS_EU_MAX_SHIFT;
2424 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
2425 val &= GEN8_RPCS_EU_MAX_MASK;
2429 rpcs |= GEN8_RPCS_ENABLE;
2435 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2437 u32 indirect_ctx_offset;
2439 switch (INTEL_GEN(engine->i915)) {
2441 MISSING_CASE(INTEL_GEN(engine->i915));
2444 indirect_ctx_offset =
2445 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2448 indirect_ctx_offset =
2449 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2452 indirect_ctx_offset =
2453 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2456 indirect_ctx_offset =
2457 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2461 return indirect_ctx_offset;
2464 static void execlists_init_reg_state(u32 *regs,
2465 struct i915_gem_context *ctx,
2466 struct intel_engine_cs *engine,
2467 struct intel_ring *ring)
2469 struct drm_i915_private *dev_priv = engine->i915;
2470 u32 base = engine->mmio_base;
2471 bool rcs = engine->class == RENDER_CLASS;
2473 /* A context is actually a big batch buffer with several
2474 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2475 * values we are setting here are only for the first context restore:
2476 * on a subsequent save, the GPU will recreate this batchbuffer with new
2477 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2478 * we are not initializing here).
2480 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2481 MI_LRI_FORCE_POSTED;
2483 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2484 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
2485 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
2486 if (INTEL_GEN(dev_priv) < 11) {
2487 regs[CTX_CONTEXT_CONTROL + 1] |=
2488 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
2489 CTX_CTRL_RS_CTX_ENABLE);
2491 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2492 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2493 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2494 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2495 RING_CTL_SIZE(ring->size) | RING_VALID);
2496 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2497 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2498 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2499 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2500 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2501 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2503 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2505 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2506 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2507 RING_INDIRECT_CTX_OFFSET(base), 0);
2508 if (wa_ctx->indirect_ctx.size) {
2509 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2511 regs[CTX_RCS_INDIRECT_CTX + 1] =
2512 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2513 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2515 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2516 intel_lr_indirect_ctx_offset(engine) << 6;
2519 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2520 if (wa_ctx->per_ctx.size) {
2521 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2523 regs[CTX_BB_PER_CTX_PTR + 1] =
2524 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2528 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2530 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2531 /* PDP values well be assigned later if needed */
2532 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2533 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2534 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2535 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2536 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2537 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2538 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2539 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2541 if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
2542 /* 64b PPGTT (48bit canonical)
2543 * PDP0_DESCRIPTOR contains the base address to PML4 and
2544 * other PDP Descriptors are ignored.
2546 ASSIGN_CTX_PML4(ctx->ppgtt, regs);
2550 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2551 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2552 make_rpcs(dev_priv));
2554 i915_oa_init_reg_state(engine, ctx, regs);
2557 regs[CTX_END] = MI_BATCH_BUFFER_END;
2558 if (INTEL_GEN(dev_priv) >= 10)
2559 regs[CTX_END] |= BIT(0);
2563 populate_lr_context(struct i915_gem_context *ctx,
2564 struct drm_i915_gem_object *ctx_obj,
2565 struct intel_engine_cs *engine,
2566 struct intel_ring *ring)
2572 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2574 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2578 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2579 if (IS_ERR(vaddr)) {
2580 ret = PTR_ERR(vaddr);
2581 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2584 ctx_obj->mm.dirty = true;
2586 if (engine->default_state) {
2588 * We only want to copy over the template context state;
2589 * skipping over the headers reserved for GuC communication,
2590 * leaving those as zero.
2592 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2595 defaults = i915_gem_object_pin_map(engine->default_state,
2597 if (IS_ERR(defaults)) {
2598 ret = PTR_ERR(defaults);
2602 memcpy(vaddr + start, defaults + start, engine->context_size);
2603 i915_gem_object_unpin_map(engine->default_state);
2606 /* The second page of the context object contains some fields which must
2607 * be set up prior to the first execution. */
2608 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2609 execlists_init_reg_state(regs, ctx, engine, ring);
2610 if (!engine->default_state)
2611 regs[CTX_CONTEXT_CONTROL + 1] |=
2612 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2613 if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11)
2614 regs[CTX_CONTEXT_CONTROL + 1] |=
2615 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2616 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
2619 i915_gem_object_unpin_map(ctx_obj);
2623 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2624 struct intel_engine_cs *engine,
2625 struct intel_context *ce)
2627 struct drm_i915_gem_object *ctx_obj;
2628 struct i915_vma *vma;
2629 uint32_t context_size;
2630 struct intel_ring *ring;
2631 struct i915_timeline *timeline;
2637 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2640 * Before the actual start of the context image, we insert a few pages
2641 * for our own use and for sharing with the GuC.
2643 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
2645 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2646 if (IS_ERR(ctx_obj))
2647 return PTR_ERR(ctx_obj);
2649 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.vm, NULL);
2652 goto error_deref_obj;
2655 timeline = i915_timeline_create(ctx->i915, ctx->name);
2656 if (IS_ERR(timeline)) {
2657 ret = PTR_ERR(timeline);
2658 goto error_deref_obj;
2661 ring = intel_engine_create_ring(engine, timeline, ctx->ring_size);
2662 i915_timeline_put(timeline);
2664 ret = PTR_ERR(ring);
2665 goto error_deref_obj;
2668 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2670 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2671 goto error_ring_free;
2680 intel_ring_free(ring);
2682 i915_gem_object_put(ctx_obj);
2686 void intel_lr_context_resume(struct drm_i915_private *i915)
2688 struct intel_engine_cs *engine;
2689 struct i915_gem_context *ctx;
2690 enum intel_engine_id id;
2693 * Because we emit WA_TAIL_DWORDS there may be a disparity
2694 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2695 * that stored in context. As we only write new commands from
2696 * ce->ring->tail onwards, everything before that is junk. If the GPU
2697 * starts reading from its RING_HEAD from the context, it may try to
2698 * execute that junk and die.
2700 * So to avoid that we reset the context images upon resume. For
2701 * simplicity, we just zero everything out.
2703 list_for_each_entry(ctx, &i915->contexts.list, link) {
2704 for_each_engine(engine, i915, id) {
2705 struct intel_context *ce =
2706 to_intel_context(ctx, engine);
2711 intel_ring_reset(ce->ring, 0);
2713 if (ce->pin_count) { /* otherwise done in context_pin */
2714 u32 *regs = ce->lrc_reg_state;
2716 regs[CTX_RING_HEAD + 1] = ce->ring->head;
2717 regs[CTX_RING_TAIL + 1] = ce->ring->tail;
2723 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2724 #include "selftests/intel_lrc.c"