drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_pps {
  46         /* 100us units */
  47         int t1_t2;
  48         int t3;
  49         int t4;
  50         int t5;
  51         int tx;
  52
  53         int divider;
  54
  55         int port;
  56         bool powerdown_on_reset;
  57 };
  58
  59 struct intel_lvds_encoder {
  60         struct intel_encoder base;
  61
  62         bool is_dual_link;
  63         i915_reg_t reg;
  64         u32 a3_power;
  65
  66         struct intel_lvds_pps init_pps;
  67         u32 init_lvds_val;
  68
  69         struct intel_connector *attached_connector;
  70 };
  71
  72 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  73 {
  74         return container_of(encoder, struct intel_lvds_encoder, base.base);
  75 }
  76
  77 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
  78                              i915_reg_t lvds_reg, enum pipe *pipe)
  79 {
  80         u32 val;
  81
  82         val = I915_READ(lvds_reg);
  83
  84         /* asserts want to know the pipe even if the port is disabled */
  85         if (HAS_PCH_CPT(dev_priv))
  86                 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
  87         else
  88                 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
  89
  90         return val & LVDS_PORT_EN;
  91 }
  92
  93 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  94                                     enum pipe *pipe)
  95 {
  96         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  97         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  98         bool ret;
  99
 100         if (!intel_display_power_get_if_enabled(dev_priv,
 101                                                 encoder->power_domain))
 102                 return false;
 103
 104         ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
 105
 106         intel_display_power_put(dev_priv, encoder->power_domain);
 107
 108         return ret;
 109 }
 110
 111 static void intel_lvds_get_config(struct intel_encoder *encoder,
 112                                   struct intel_crtc_state *pipe_config)
 113 {
 114         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 115         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 116         u32 tmp, flags = 0;
 117
 118         pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
 119
 120         tmp = I915_READ(lvds_encoder->reg);
 121         if (tmp & LVDS_HSYNC_POLARITY)
 122                 flags |= DRM_MODE_FLAG_NHSYNC;
 123         else
 124                 flags |= DRM_MODE_FLAG_PHSYNC;
 125         if (tmp & LVDS_VSYNC_POLARITY)
 126                 flags |= DRM_MODE_FLAG_NVSYNC;
 127         else
 128                 flags |= DRM_MODE_FLAG_PVSYNC;
 129
 130         pipe_config->base.adjusted_mode.flags |= flags;
 131
 132         if (INTEL_GEN(dev_priv) < 5)
 133                 pipe_config->gmch_pfit.lvds_border_bits =
 134                         tmp & LVDS_BORDER_ENABLE;
 135
 136         /* gen2/3 store dither state in pfit control, needs to match */
 137         if (INTEL_GEN(dev_priv) < 4) {
 138                 tmp = I915_READ(PFIT_CONTROL);
 139
 140                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 141         }
 142
 143         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 144 }
 145
 146 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 147                                         struct intel_lvds_pps *pps)
 148 {
 149         u32 val;
 150
 151         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 152
 153         val = I915_READ(PP_ON_DELAYS(0));
 154         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 155                     PANEL_PORT_SELECT_SHIFT;
 156         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 157                      PANEL_POWER_UP_DELAY_SHIFT;
 158         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 159                   PANEL_LIGHT_ON_DELAY_SHIFT;
 160
 161         val = I915_READ(PP_OFF_DELAYS(0));
 162         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 163                   PANEL_POWER_DOWN_DELAY_SHIFT;
 164         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 165                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 166
 167         val = I915_READ(PP_DIVISOR(0));
 168         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 169                        PP_REFERENCE_DIVIDER_SHIFT;
 170         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 171               PANEL_POWER_CYCLE_DELAY_SHIFT;
 172         /*
 173          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 174          * too short power-cycle delay due to the asynchronous programming of
 175          * the register.
 176          */
 177         if (val)
 178                 val--;
 179         /* Convert from 100ms to 100us units */
 180         pps->t4 = val * 1000;
 181
 182         if (INTEL_GEN(dev_priv) <= 4 &&
 183             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 184                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 185                               "setting defaults\n");
 186                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 187                 pps->t1_t2 = 40 * 10;
 188                 pps->t5 = 200 * 10;
 189                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 190                 pps->t3 = 35 * 10;
 191                 pps->tx = 200 * 10;
 192         }
 193
 194         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 195                          "divider %d port %d powerdown_on_reset %d\n",
 196                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 197                          pps->divider, pps->port, pps->powerdown_on_reset);
 198 }
 199
 200 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 201                                    struct intel_lvds_pps *pps)
 202 {
 203         u32 val;
 204
 205         val = I915_READ(PP_CONTROL(0));
 206         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 207         if (pps->powerdown_on_reset)
 208                 val |= PANEL_POWER_RESET;
 209         I915_WRITE(PP_CONTROL(0), val);
 210
 211         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 212                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 213                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 214         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 215                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 216
 217         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 218         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 219                PANEL_POWER_CYCLE_DELAY_SHIFT;
 220         I915_WRITE(PP_DIVISOR(0), val);
 221 }
 222
 223 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 224                                   const struct intel_crtc_state *pipe_config,
 225                                   const struct drm_connector_state *conn_state)
 226 {
 227         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 228         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 229         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 230         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 231         int pipe = crtc->pipe;
 232         u32 temp;
 233
 234         if (HAS_PCH_SPLIT(dev_priv)) {
 235                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 236                 assert_shared_dpll_disabled(dev_priv,
 237                                             pipe_config->shared_dpll);
 238         } else {
 239                 assert_pll_disabled(dev_priv, pipe);
 240         }
 241
 242         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 243
 244         temp = lvds_encoder->init_lvds_val;
 245         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 246
 247         if (HAS_PCH_CPT(dev_priv)) {
 248                 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
 249                 temp |= LVDS_PIPE_SEL_CPT(pipe);
 250         } else {
 251                 temp &= ~LVDS_PIPE_SEL_MASK;
 252                 temp |= LVDS_PIPE_SEL(pipe);
 253         }
 254
 255         /* set the corresponsding LVDS_BORDER bit */
 256         temp &= ~LVDS_BORDER_ENABLE;
 257         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 258
 259         /*
 260          * Set the B0-B3 data pairs corresponding to whether we're going to
 261          * set the DPLLs for dual-channel mode or not.
 262          */
 263         if (lvds_encoder->is_dual_link)
 264                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 265         else
 266                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 267
 268         /*
 269          * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 270          * appropriately here, but we need to look more thoroughly into how
 271          * panels behave in the two modes. For now, let's just maintain the
 272          * value we got from the BIOS.
 273          */
 274         temp &= ~LVDS_A3_POWER_MASK;
 275         temp |= lvds_encoder->a3_power;
 276
 277         /*
 278          * Set the dithering flag on LVDS as needed, note that there is no
 279          * special lvds dither control bit on pch-split platforms, dithering is
 280          * only controlled through the PIPECONF reg.
 281          */
 282         if (IS_GEN4(dev_priv)) {
 283                 /*
 284                  * Bspec wording suggests that LVDS port dithering only exists
 285                  * for 18bpp panels.
 286                  */
 287                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 288                         temp |= LVDS_ENABLE_DITHER;
 289                 else
 290                         temp &= ~LVDS_ENABLE_DITHER;
 291         }
 292         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 293         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 294                 temp |= LVDS_HSYNC_POLARITY;
 295         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 296                 temp |= LVDS_VSYNC_POLARITY;
 297
 298         I915_WRITE(lvds_encoder->reg, temp);
 299 }
 300
 301 /*
 302  * Sets the power state for the panel.
 303  */
 304 static void intel_enable_lvds(struct intel_encoder *encoder,
 305                               const struct intel_crtc_state *pipe_config,
 306                               const struct drm_connector_state *conn_state)
 307 {
 308         struct drm_device *dev = encoder->base.dev;
 309         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 310         struct drm_i915_private *dev_priv = to_i915(dev);
 311
 312         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 313
 314         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 315         POSTING_READ(lvds_encoder->reg);
 316
 317         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
 318                 DRM_ERROR("timed out waiting for panel to power on\n");
 319
 320         intel_panel_enable_backlight(pipe_config, conn_state);
 321 }
 322
 323 static void intel_disable_lvds(struct intel_encoder *encoder,
 324                                const struct intel_crtc_state *old_crtc_state,
 325                                const struct drm_connector_state *old_conn_state)
 326 {
 327         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 329
 330         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 331         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 332                 DRM_ERROR("timed out waiting for panel to power off\n");
 333
 334         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 335         POSTING_READ(lvds_encoder->reg);
 336 }
 337
 338 static void gmch_disable_lvds(struct intel_encoder *encoder,
 339                               const struct intel_crtc_state *old_crtc_state,
 340                               const struct drm_connector_state *old_conn_state)
 341
 342 {
 343         intel_panel_disable_backlight(old_conn_state);
 344
 345         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 346 }
 347
 348 static void pch_disable_lvds(struct intel_encoder *encoder,
 349                              const struct intel_crtc_state *old_crtc_state,
 350                              const struct drm_connector_state *old_conn_state)
 351 {
 352         intel_panel_disable_backlight(old_conn_state);
 353 }
 354
 355 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 356                                   const struct intel_crtc_state *old_crtc_state,
 357                                   const struct drm_connector_state *old_conn_state)
 358 {
 359         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 360 }
 361
 362 static enum drm_mode_status
 363 intel_lvds_mode_valid(struct drm_connector *connector,
 364                       struct drm_display_mode *mode)
 365 {
 366         struct intel_connector *intel_connector = to_intel_connector(connector);
 367         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 368         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 369
 370         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 371                 return MODE_NO_DBLESCAN;
 372         if (mode->hdisplay > fixed_mode->hdisplay)
 373                 return MODE_PANEL;
 374         if (mode->vdisplay > fixed_mode->vdisplay)
 375                 return MODE_PANEL;
 376         if (fixed_mode->clock > max_pixclk)
 377                 return MODE_CLOCK_HIGH;
 378
 379         return MODE_OK;
 380 }
 381
 382 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 383                                       struct intel_crtc_state *pipe_config,
 384                                       struct drm_connector_state *conn_state)
 385 {
 386         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 387         struct intel_lvds_encoder *lvds_encoder =
 388                 to_lvds_encoder(&intel_encoder->base);
 389         struct intel_connector *intel_connector =
 390                 lvds_encoder->attached_connector;
 391         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 392         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 393         unsigned int lvds_bpp;
 394
 395         /* Should never happen!! */
 396         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 397                 DRM_ERROR("Can't support LVDS on pipe A\n");
 398                 return false;
 399         }
 400
 401         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 402                 lvds_bpp = 8*3;
 403         else
 404                 lvds_bpp = 6*3;
 405
 406         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 407                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 408                               pipe_config->pipe_bpp, lvds_bpp);
 409                 pipe_config->pipe_bpp = lvds_bpp;
 410         }
 411
 412         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 413
 414         /*
 415          * We have timings from the BIOS for the panel, put them in
 416          * to the adjusted mode.  The CRTC will be set up for this mode,
 417          * with the panel scaling set up to source from the H/VDisplay
 418          * of the original mode.
 419          */
 420         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 421                                adjusted_mode);
 422
 423         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 424                 return false;
 425
 426         if (HAS_PCH_SPLIT(dev_priv)) {
 427                 pipe_config->has_pch_encoder = true;
 428
 429                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 430                                         conn_state->scaling_mode);
 431         } else {
 432                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 433                                          conn_state->scaling_mode);
 434
 435         }
 436
 437         /*
 438          * XXX: It would be nice to support lower refresh rates on the
 439          * panels to reduce power consumption, and perhaps match the
 440          * user's requested refresh rate.
 441          */
 442
 443         return true;
 444 }
 445
 446 static enum drm_connector_status
 447 intel_lvds_detect(struct drm_connector *connector, bool force)
 448 {
 449         return connector_status_connected;
 450 }
 451
 452 /*
 453  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 454  */
 455 static int intel_lvds_get_modes(struct drm_connector *connector)
 456 {
 457         struct intel_connector *intel_connector = to_intel_connector(connector);
 458         struct drm_device *dev = connector->dev;
 459         struct drm_display_mode *mode;
 460
 461         /* use cached edid if we have one */
 462         if (!IS_ERR_OR_NULL(intel_connector->edid))
 463                 return drm_add_edid_modes(connector, intel_connector->edid);
 464
 465         mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode);
 466         if (mode == NULL)
 467                 return 0;
 468
 469         drm_mode_probed_add(connector, mode);
 470         return 1;
 471 }
 472
 473 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 474         .get_modes = intel_lvds_get_modes,
 475         .mode_valid = intel_lvds_mode_valid,
 476         .atomic_check = intel_digital_connector_atomic_check,
 477 };
 478
 479 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 480         .detect = intel_lvds_detect,
 481         .fill_modes = drm_helper_probe_single_connector_modes,
 482         .atomic_get_property = intel_digital_connector_atomic_get_property,
 483         .atomic_set_property = intel_digital_connector_atomic_set_property,
 484         .late_register = intel_connector_register,
 485         .early_unregister = intel_connector_unregister,
 486         .destroy = intel_connector_destroy,
 487         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 488         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 489 };
 490
 491 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 492         .destroy = intel_encoder_destroy,
 493 };
 494
 495 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 496 {
 497         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 498         return 1;
 499 }
 500
 501 /* These systems claim to have LVDS, but really don't */
 502 static const struct dmi_system_id intel_no_lvds[] = {
 503         {
 504                 .callback = intel_no_lvds_dmi_callback,
 505                 .ident = "Apple Mac Mini (Core series)",
 506                 .matches = {
 507                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 508                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 509                 },
 510         },
 511         {
 512                 .callback = intel_no_lvds_dmi_callback,
 513                 .ident = "Apple Mac Mini (Core 2 series)",
 514                 .matches = {
 515                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 516                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 517                 },
 518         },
 519         {
 520                 .callback = intel_no_lvds_dmi_callback,
 521                 .ident = "MSI IM-945GSE-A",
 522                 .matches = {
 523                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 524                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 525                 },
 526         },
 527         {
 528                 .callback = intel_no_lvds_dmi_callback,
 529                 .ident = "Dell Studio Hybrid",
 530                 .matches = {
 531                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 532                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 533                 },
 534         },
 535         {
 536                 .callback = intel_no_lvds_dmi_callback,
 537                 .ident = "Dell OptiPlex FX170",
 538                 .matches = {
 539                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 540                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 541                 },
 542         },
 543         {
 544                 .callback = intel_no_lvds_dmi_callback,
 545                 .ident = "AOpen Mini PC",
 546                 .matches = {
 547                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 548                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 549                 },
 550         },
 551         {
 552                 .callback = intel_no_lvds_dmi_callback,
 553                 .ident = "AOpen Mini PC MP915",
 554                 .matches = {
 555                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 556                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 557                 },
 558         },
 559         {
 560                 .callback = intel_no_lvds_dmi_callback,
 561                 .ident = "AOpen i915GMm-HFS",
 562                 .matches = {
 563                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 564                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 565                 },
 566         },
 567         {
 568                 .callback = intel_no_lvds_dmi_callback,
 569                 .ident = "AOpen i45GMx-I",
 570                 .matches = {
 571                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 572                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 573                 },
 574         },
 575         {
 576                 .callback = intel_no_lvds_dmi_callback,
 577                 .ident = "Aopen i945GTt-VFA",
 578                 .matches = {
 579                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 580                 },
 581         },
 582         {
 583                 .callback = intel_no_lvds_dmi_callback,
 584                 .ident = "Clientron U800",
 585                 .matches = {
 586                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 587                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 588                 },
 589         },
 590         {
 591                 .callback = intel_no_lvds_dmi_callback,
 592                 .ident = "Clientron E830",
 593                 .matches = {
 594                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 595                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 596                 },
 597         },
 598         {
 599                 .callback = intel_no_lvds_dmi_callback,
 600                 .ident = "Asus EeeBox PC EB1007",
 601                 .matches = {
 602                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 603                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 604                 },
 605         },
 606         {
 607                 .callback = intel_no_lvds_dmi_callback,
 608                 .ident = "Asus AT5NM10T-I",
 609                 .matches = {
 610                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 611                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 612                 },
 613         },
 614         {
 615                 .callback = intel_no_lvds_dmi_callback,
 616                 .ident = "Hewlett-Packard HP t5740",
 617                 .matches = {
 618                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 619                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 620                 },
 621         },
 622         {
 623                 .callback = intel_no_lvds_dmi_callback,
 624                 .ident = "Hewlett-Packard t5745",
 625                 .matches = {
 626                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 627                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 628                 },
 629         },
 630         {
 631                 .callback = intel_no_lvds_dmi_callback,
 632                 .ident = "Hewlett-Packard st5747",
 633                 .matches = {
 634                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 635                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 636                 },
 637         },
 638         {
 639                 .callback = intel_no_lvds_dmi_callback,
 640                 .ident = "MSI Wind Box DC500",
 641                 .matches = {
 642                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 643                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 644                 },
 645         },
 646         {
 647                 .callback = intel_no_lvds_dmi_callback,
 648                 .ident = "Gigabyte GA-D525TUD",
 649                 .matches = {
 650                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 651                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 652                 },
 653         },
 654         {
 655                 .callback = intel_no_lvds_dmi_callback,
 656                 .ident = "Supermicro X7SPA-H",
 657                 .matches = {
 658                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 659                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 660                 },
 661         },
 662         {
 663                 .callback = intel_no_lvds_dmi_callback,
 664                 .ident = "Fujitsu Esprimo Q900",
 665                 .matches = {
 666                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 667                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 668                 },
 669         },
 670         {
 671                 .callback = intel_no_lvds_dmi_callback,
 672                 .ident = "Intel D410PT",
 673                 .matches = {
 674                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 675                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 676                 },
 677         },
 678         {
 679                 .callback = intel_no_lvds_dmi_callback,
 680                 .ident = "Intel D425KT",
 681                 .matches = {
 682                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 683                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 684                 },
 685         },
 686         {
 687                 .callback = intel_no_lvds_dmi_callback,
 688                 .ident = "Intel D510MO",
 689                 .matches = {
 690                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 691                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 692                 },
 693         },
 694         {
 695                 .callback = intel_no_lvds_dmi_callback,
 696                 .ident = "Intel D525MW",
 697                 .matches = {
 698                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 699                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 700                 },
 701         },
 702         {
 703                 .callback = intel_no_lvds_dmi_callback,
 704                 .ident = "Radiant P845",
 705                 .matches = {
 706                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 707                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 708                 },
 709         },
 710
 711         { }     /* terminating entry */
 712 };
 713
 714 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 715 {
 716         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 717         return 1;
 718 }
 719
 720 static const struct dmi_system_id intel_dual_link_lvds[] = {
 721         {
 722                 .callback = intel_dual_link_lvds_callback,
 723                 .ident = "Apple MacBook Pro 15\" (2010)",
 724                 .matches = {
 725                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 726                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 727                 },
 728         },
 729         {
 730                 .callback = intel_dual_link_lvds_callback,
 731                 .ident = "Apple MacBook Pro 15\" (2011)",
 732                 .matches = {
 733                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 734                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 735                 },
 736         },
 737         {
 738                 .callback = intel_dual_link_lvds_callback,
 739                 .ident = "Apple MacBook Pro 15\" (2012)",
 740                 .matches = {
 741                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 742                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 743                 },
 744         },
 745         { }     /* terminating entry */
 746 };
 747
 748 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 749 {
 750         struct intel_encoder *intel_encoder;
 751
 752         for_each_intel_encoder(dev, intel_encoder)
 753                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 754                         return intel_encoder;
 755
 756         return NULL;
 757 }
 758
 759 bool intel_is_dual_link_lvds(struct drm_device *dev)
 760 {
 761         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 762
 763         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 764 }
 765
 766 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 767 {
 768         struct drm_device *dev = lvds_encoder->base.base.dev;
 769         unsigned int val;
 770         struct drm_i915_private *dev_priv = to_i915(dev);
 771
 772         /* use the module option value if specified */
 773         if (i915_modparams.lvds_channel_mode > 0)
 774                 return i915_modparams.lvds_channel_mode == 2;
 775
 776         /* single channel LVDS is limited to 112 MHz */
 777         if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999)
 778                 return true;
 779
 780         if (dmi_check_system(intel_dual_link_lvds))
 781                 return true;
 782
 783         /*
 784          * BIOS should set the proper LVDS register value at boot, but
 785          * in reality, it doesn't set the value when the lid is closed;
 786          * we need to check "the value to be set" in VBT when LVDS
 787          * register is uninitialized.
 788          */
 789         val = I915_READ(lvds_encoder->reg);
 790         if (HAS_PCH_CPT(dev_priv))
 791                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
 792         else
 793                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
 794         if (val == 0)
 795                 val = dev_priv->vbt.bios_lvds_val;
 796
 797         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 798 }
 799
 800 static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 801 {
 802         /*
 803          * With the introduction of the PCH we gained a dedicated
 804          * LVDS presence pin, use it.
 805          */
 806         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 807                 return true;
 808
 809         /*
 810          * Otherwise LVDS was only attached to mobile products,
 811          * except for the inglorious 830gm
 812          */
 813         if (INTEL_GEN(dev_priv) <= 4 &&
 814             IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 815                 return true;
 816
 817         return false;
 818 }
 819
 820 /**
 821  * intel_lvds_init - setup LVDS connectors on this device
 822  * @dev_priv: i915 device
 823  *
 824  * Create the connector, register the LVDS DDC bus, and try to figure out what
 825  * modes we can display on the LVDS panel (if present).
 826  */
 827 void intel_lvds_init(struct drm_i915_private *dev_priv)
 828 {
 829         struct drm_device *dev = &dev_priv->drm;
 830         struct intel_lvds_encoder *lvds_encoder;
 831         struct intel_encoder *intel_encoder;
 832         struct intel_connector *intel_connector;
 833         struct drm_connector *connector;
 834         struct drm_encoder *encoder;
 835         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 836         struct drm_display_mode *fixed_mode = NULL;
 837         struct drm_display_mode *downclock_mode = NULL;
 838         struct edid *edid;
 839         i915_reg_t lvds_reg;
 840         u32 lvds;
 841         u8 pin;
 842         u32 allowed_scalers;
 843
 844         if (!intel_lvds_supported(dev_priv))
 845                 return;
 846
 847         /* Skip init on machines we know falsely report LVDS */
 848         if (dmi_check_system(intel_no_lvds)) {
 849                 WARN(!dev_priv->vbt.int_lvds_support,
 850                      "Useless DMI match. Internal LVDS support disabled by VBT\n");
 851                 return;
 852         }
 853
 854         if (!dev_priv->vbt.int_lvds_support) {
 855                 DRM_DEBUG_KMS("Internal LVDS support disabled by VBT\n");
 856                 return;
 857         }
 858
 859         if (HAS_PCH_SPLIT(dev_priv))
 860                 lvds_reg = PCH_LVDS;
 861         else
 862                 lvds_reg = LVDS;
 863
 864         lvds = I915_READ(lvds_reg);
 865
 866         if (HAS_PCH_SPLIT(dev_priv)) {
 867                 if ((lvds & LVDS_DETECTED) == 0)
 868                         return;
 869         }
 870
 871         pin = GMBUS_PIN_PANEL;
 872         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 873                 if ((lvds & LVDS_PORT_EN) == 0) {
 874                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
 875                         return;
 876                 }
 877                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
 878         }
 879
 880         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 881         if (!lvds_encoder)
 882                 return;
 883
 884         intel_connector = intel_connector_alloc();
 885         if (!intel_connector) {
 886                 kfree(lvds_encoder);
 887                 return;
 888         }
 889
 890         lvds_encoder->attached_connector = intel_connector;
 891
 892         intel_encoder = &lvds_encoder->base;
 893         encoder = &intel_encoder->base;
 894         connector = &intel_connector->base;
 895         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
 896                            DRM_MODE_CONNECTOR_LVDS);
 897
 898         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
 899                          DRM_MODE_ENCODER_LVDS, "LVDS");
 900
 901         intel_encoder->enable = intel_enable_lvds;
 902         intel_encoder->pre_enable = intel_pre_enable_lvds;
 903         intel_encoder->compute_config = intel_lvds_compute_config;
 904         if (HAS_PCH_SPLIT(dev_priv)) {
 905                 intel_encoder->disable = pch_disable_lvds;
 906                 intel_encoder->post_disable = pch_post_disable_lvds;
 907         } else {
 908                 intel_encoder->disable = gmch_disable_lvds;
 909         }
 910         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
 911         intel_encoder->get_config = intel_lvds_get_config;
 912         intel_connector->get_hw_state = intel_connector_get_hw_state;
 913
 914         intel_connector_attach_encoder(intel_connector, intel_encoder);
 915
 916         intel_encoder->type = INTEL_OUTPUT_LVDS;
 917         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 918         intel_encoder->port = PORT_NONE;
 919         intel_encoder->cloneable = 0;
 920         if (HAS_PCH_SPLIT(dev_priv))
 921                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 922         else if (IS_GEN4(dev_priv))
 923                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
 924         else
 925                 intel_encoder->crtc_mask = (1 << 1);
 926
 927         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
 928         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 929         connector->interlace_allowed = false;
 930         connector->doublescan_allowed = false;
 931
 932         lvds_encoder->reg = lvds_reg;
 933
 934         /* create the scaling mode property */
 935         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
 936         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
 937         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
 938         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
 939         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
 940
 941         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
 942         lvds_encoder->init_lvds_val = lvds;
 943
 944         /*
 945          * LVDS discovery:
 946          * 1) check for EDID on DDC
 947          * 2) check for VBT data
 948          * 3) check to see if LVDS is already on
 949          *    if none of the above, no panel
 950          */
 951
 952         /*
 953          * Attempt to get the fixed panel mode from DDC.  Assume that the
 954          * preferred mode is the right one.
 955          */
 956         mutex_lock(&dev->mode_config.mutex);
 957         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
 958                 edid = drm_get_edid_switcheroo(connector,
 959                                     intel_gmbus_get_adapter(dev_priv, pin));
 960         else
 961                 edid = drm_get_edid(connector,
 962                                     intel_gmbus_get_adapter(dev_priv, pin));
 963         if (edid) {
 964                 if (drm_add_edid_modes(connector, edid)) {
 965                         drm_connector_update_edid_property(connector,
 966                                                                 edid);
 967                 } else {
 968                         kfree(edid);
 969                         edid = ERR_PTR(-EINVAL);
 970                 }
 971         } else {
 972                 edid = ERR_PTR(-ENOENT);
 973         }
 974         intel_connector->edid = edid;
 975
 976         list_for_each_entry(scan, &connector->probed_modes, head) {
 977                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
 978                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
 979                         drm_mode_debug_printmodeline(scan);
 980
 981                         fixed_mode = drm_mode_duplicate(dev, scan);
 982                         if (fixed_mode)
 983                                 goto out;
 984                 }
 985         }
 986
 987         /* Failed to get EDID, what about VBT? */
 988         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
 989                 DRM_DEBUG_KMS("using mode from VBT: ");
 990                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
 991
 992                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
 993                 if (fixed_mode) {
 994                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 995                         connector->display_info.width_mm = fixed_mode->width_mm;
 996                         connector->display_info.height_mm = fixed_mode->height_mm;
 997                         goto out;
 998                 }
 999         }
1000
1001         /*
1002          * If we didn't get EDID, try checking if the panel is already turned
1003          * on.  If so, assume that whatever is currently programmed is the
1004          * correct mode.
1005          */
1006         fixed_mode = intel_encoder_current_mode(intel_encoder);
1007         if (fixed_mode) {
1008                 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1009                 drm_mode_debug_printmodeline(fixed_mode);
1010                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1011         }
1012
1013         /* If we still don't have a mode after all that, give up. */
1014         if (!fixed_mode)
1015                 goto failed;
1016
1017 out:
1018         mutex_unlock(&dev->mode_config.mutex);
1019
1020         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1021         intel_panel_setup_backlight(connector, INVALID_PIPE);
1022
1023         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1024         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1025                       lvds_encoder->is_dual_link ? "dual" : "single");
1026
1027         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1028
1029         return;
1030
1031 failed:
1032         mutex_unlock(&dev->mode_config.mutex);
1033
1034         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1035         drm_connector_cleanup(connector);
1036         drm_encoder_cleanup(encoder);
1037         kfree(lvds_encoder);
1038         intel_connector_free(intel_connector);
1039         return;
1040 }