drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_reg.h"
  32 #include "intel_drv.h"
  33 #include "intel_frontbuffer.h"
  34
  35 /* Limits for overlay size. According to intel doc, the real limits are:
  36  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  37  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  38  * the mininum of both.  */
  39 #define IMAGE_MAX_WIDTH         2048
  40 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  41 /* on 830 and 845 these large limits result in the card hanging */
  42 #define IMAGE_MAX_WIDTH_LEGACY  1024
  43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  44
  45 /* overlay register definitions */
  46 /* OCMD register */
  47 #define OCMD_TILED_SURFACE      (0x1<<19)
  48 #define OCMD_MIRROR_MASK        (0x3<<17)
  49 #define OCMD_MIRROR_MODE        (0x3<<17)
  50 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  51 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  52 #define OCMD_MIRROR_BOTH        (0x3<<17)
  53 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  54 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  55 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  56 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  58 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  60 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  61 #define OCMD_YUV_422_PACKED     (0x8<<10)
  62 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  63 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  64 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  65 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  66 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  67 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  68 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  69 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  70 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  71 #define OCMD_TEST_MODE          (0x1<<4)
  72 #define OCMD_BUFFER_SELECT      (0x3<<2)
  73 #define OCMD_BUFFER0            (0x0<<2)
  74 #define OCMD_BUFFER1            (0x1<<2)
  75 #define OCMD_FIELD_SELECT       (0x1<<2)
  76 #define OCMD_FIELD0             (0x0<<1)
  77 #define OCMD_FIELD1             (0x1<<1)
  78 #define OCMD_ENABLE             (0x1<<0)
  79
  80 /* OCONFIG register */
  81 #define OCONF_PIPE_MASK         (0x1<<18)
  82 #define OCONF_PIPE_A            (0x0<<18)
  83 #define OCONF_PIPE_B            (0x1<<18)
  84 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  85 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  86 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  87 #define OCONF_CSC_BYPASS        (0x1<<4)
  88 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  89 #define OCONF_TEST_MODE         (0x1<<2)
  90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  91 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  92
  93 /* DCLRKM (dst-key) register */
  94 #define DST_KEY_ENABLE          (0x1<<31)
  95 #define CLK_RGB24_MASK          0x0
  96 #define CLK_RGB16_MASK          0x070307
  97 #define CLK_RGB15_MASK          0x070707
  98 #define CLK_RGB8I_MASK          0xffffff
  99
 100 #define RGB16_TO_COLORKEY(c) \
 101         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 102 #define RGB15_TO_COLORKEY(c) \
 103         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 104
 105 /* overlay flip addr flag */
 106 #define OFC_UPDATE              0x1
 107
 108 /* polyphase filter coefficients */
 109 #define N_HORIZ_Y_TAPS          5
 110 #define N_VERT_Y_TAPS           3
 111 #define N_HORIZ_UV_TAPS         3
 112 #define N_VERT_UV_TAPS          3
 113 #define N_PHASES                17
 114 #define MAX_TAPS                5
 115
 116 /* memory bufferd overlay registers */
 117 struct overlay_registers {
 118         u32 OBUF_0Y;
 119         u32 OBUF_1Y;
 120         u32 OBUF_0U;
 121         u32 OBUF_0V;
 122         u32 OBUF_1U;
 123         u32 OBUF_1V;
 124         u32 OSTRIDE;
 125         u32 YRGB_VPH;
 126         u32 UV_VPH;
 127         u32 HORZ_PH;
 128         u32 INIT_PHS;
 129         u32 DWINPOS;
 130         u32 DWINSZ;
 131         u32 SWIDTH;
 132         u32 SWIDTHSW;
 133         u32 SHEIGHT;
 134         u32 YRGBSCALE;
 135         u32 UVSCALE;
 136         u32 OCLRC0;
 137         u32 OCLRC1;
 138         u32 DCLRKV;
 139         u32 DCLRKM;
 140         u32 SCLRKVH;
 141         u32 SCLRKVL;
 142         u32 SCLRKEN;
 143         u32 OCONFIG;
 144         u32 OCMD;
 145         u32 RESERVED1; /* 0x6C */
 146         u32 OSTART_0Y;
 147         u32 OSTART_1Y;
 148         u32 OSTART_0U;
 149         u32 OSTART_0V;
 150         u32 OSTART_1U;
 151         u32 OSTART_1V;
 152         u32 OTILEOFF_0Y;
 153         u32 OTILEOFF_1Y;
 154         u32 OTILEOFF_0U;
 155         u32 OTILEOFF_0V;
 156         u32 OTILEOFF_1U;
 157         u32 OTILEOFF_1V;
 158         u32 FASTHSCALE; /* 0xA0 */
 159         u32 UVSCALEV; /* 0xA4 */
 160         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 161         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 162         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 163         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 164         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 165         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 166         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 167         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 168         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 169 };
 170
 171 struct intel_overlay {
 172         struct drm_i915_private *i915;
 173         struct intel_crtc *crtc;
 174         struct i915_vma *vma;
 175         struct i915_vma *old_vma;
 176         bool active;
 177         bool pfit_active;
 178         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 179         u32 color_key:24;
 180         u32 color_key_enabled:1;
 181         u32 brightness, contrast, saturation;
 182         u32 old_xscale, old_yscale;
 183         /* register access */
 184         u32 flip_addr;
 185         struct drm_i915_gem_object *reg_bo;
 186         /* flip handling */
 187         struct i915_gem_active last_flip;
 188 };
 189
 190 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
 191                                       bool enable)
 192 {
 193         struct pci_dev *pdev = dev_priv->drm.pdev;
 194         u8 val;
 195
 196         /* WA_OVERLAY_CLKGATE:alm */
 197         if (enable)
 198                 I915_WRITE(DSPCLK_GATE_D, 0);
 199         else
 200                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 201
 202         /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
 203         pci_bus_read_config_byte(pdev->bus,
 204                                  PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
 205         if (enable)
 206                 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
 207         else
 208                 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
 209         pci_bus_write_config_byte(pdev->bus,
 210                                   PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
 211 }
 212
 213 static struct overlay_registers __iomem *
 214 intel_overlay_map_regs(struct intel_overlay *overlay)
 215 {
 216         struct drm_i915_private *dev_priv = overlay->i915;
 217         struct overlay_registers __iomem *regs;
 218
 219         if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
 220                 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
 221         else
 222                 regs = io_mapping_map_wc(&dev_priv->ggtt.mappable,
 223                                          overlay->flip_addr,
 224                                          PAGE_SIZE);
 225
 226         return regs;
 227 }
 228
 229 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
 230                                      struct overlay_registers __iomem *regs)
 231 {
 232         if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
 233                 io_mapping_unmap(regs);
 234 }
 235
 236 static void intel_overlay_submit_request(struct intel_overlay *overlay,
 237                                          struct drm_i915_gem_request *req,
 238                                          i915_gem_retire_fn retire)
 239 {
 240         GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
 241                                         &overlay->i915->drm.struct_mutex));
 242         i915_gem_active_set_retire_fn(&overlay->last_flip, retire,
 243                                       &overlay->i915->drm.struct_mutex);
 244         i915_gem_active_set(&overlay->last_flip, req);
 245         i915_add_request(req);
 246 }
 247
 248 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 249                                          struct drm_i915_gem_request *req,
 250                                          i915_gem_retire_fn retire)
 251 {
 252         intel_overlay_submit_request(overlay, req, retire);
 253         return i915_gem_active_retire(&overlay->last_flip,
 254                                       &overlay->i915->drm.struct_mutex);
 255 }
 256
 257 static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay)
 258 {
 259         struct drm_i915_private *dev_priv = overlay->i915;
 260         struct intel_engine_cs *engine = dev_priv->engine[RCS];
 261
 262         return i915_gem_request_alloc(engine, dev_priv->kernel_context);
 263 }
 264
 265 /* overlay needs to be disable in OCMD reg */
 266 static int intel_overlay_on(struct intel_overlay *overlay)
 267 {
 268         struct drm_i915_private *dev_priv = overlay->i915;
 269         struct drm_i915_gem_request *req;
 270         struct intel_ring *ring;
 271         int ret;
 272
 273         WARN_ON(overlay->active);
 274         WARN_ON(IS_I830(dev_priv) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
 275
 276         req = alloc_request(overlay);
 277         if (IS_ERR(req))
 278                 return PTR_ERR(req);
 279
 280         ret = intel_ring_begin(req, 4);
 281         if (ret) {
 282                 i915_add_request_no_flush(req);
 283                 return ret;
 284         }
 285
 286         overlay->active = true;
 287
 288         if (IS_I830(dev_priv))
 289                 i830_overlay_clock_gating(dev_priv, false);
 290
 291         ring = req->ring;
 292         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 293         intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
 294         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 295         intel_ring_emit(ring, MI_NOOP);
 296         intel_ring_advance(ring);
 297
 298         return intel_overlay_do_wait_request(overlay, req, NULL);
 299 }
 300
 301 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
 302                                        struct i915_vma *vma)
 303 {
 304         enum pipe pipe = overlay->crtc->pipe;
 305
 306         WARN_ON(overlay->old_vma);
 307
 308         i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
 309                           vma ? vma->obj : NULL,
 310                           INTEL_FRONTBUFFER_OVERLAY(pipe));
 311
 312         intel_frontbuffer_flip_prepare(overlay->i915,
 313                                        INTEL_FRONTBUFFER_OVERLAY(pipe));
 314
 315         overlay->old_vma = overlay->vma;
 316         if (vma)
 317                 overlay->vma = i915_vma_get(vma);
 318         else
 319                 overlay->vma = NULL;
 320 }
 321
 322 /* overlay needs to be enabled in OCMD reg */
 323 static int intel_overlay_continue(struct intel_overlay *overlay,
 324                                   struct i915_vma *vma,
 325                                   bool load_polyphase_filter)
 326 {
 327         struct drm_i915_private *dev_priv = overlay->i915;
 328         struct drm_i915_gem_request *req;
 329         struct intel_ring *ring;
 330         u32 flip_addr = overlay->flip_addr;
 331         u32 tmp;
 332         int ret;
 333
 334         WARN_ON(!overlay->active);
 335
 336         if (load_polyphase_filter)
 337                 flip_addr |= OFC_UPDATE;
 338
 339         /* check for underruns */
 340         tmp = I915_READ(DOVSTA);
 341         if (tmp & (1 << 17))
 342                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 343
 344         req = alloc_request(overlay);
 345         if (IS_ERR(req))
 346                 return PTR_ERR(req);
 347
 348         ret = intel_ring_begin(req, 2);
 349         if (ret) {
 350                 i915_add_request_no_flush(req);
 351                 return ret;
 352         }
 353
 354         ring = req->ring;
 355         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 356         intel_ring_emit(ring, flip_addr);
 357         intel_ring_advance(ring);
 358
 359         intel_overlay_flip_prepare(overlay, vma);
 360
 361         intel_overlay_submit_request(overlay, req, NULL);
 362
 363         return 0;
 364 }
 365
 366 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
 367 {
 368         struct i915_vma *vma;
 369
 370         vma = fetch_and_zero(&overlay->old_vma);
 371         if (WARN_ON(!vma))
 372                 return;
 373
 374         intel_frontbuffer_flip_complete(overlay->i915,
 375                                         INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 376
 377         i915_gem_object_unpin_from_display_plane(vma);
 378         i915_vma_put(vma);
 379 }
 380
 381 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
 382                                                struct drm_i915_gem_request *req)
 383 {
 384         struct intel_overlay *overlay =
 385                 container_of(active, typeof(*overlay), last_flip);
 386
 387         intel_overlay_release_old_vma(overlay);
 388 }
 389
 390 static void intel_overlay_off_tail(struct i915_gem_active *active,
 391                                    struct drm_i915_gem_request *req)
 392 {
 393         struct intel_overlay *overlay =
 394                 container_of(active, typeof(*overlay), last_flip);
 395         struct drm_i915_private *dev_priv = overlay->i915;
 396
 397         intel_overlay_release_old_vma(overlay);
 398
 399         overlay->crtc->overlay = NULL;
 400         overlay->crtc = NULL;
 401         overlay->active = false;
 402
 403         if (IS_I830(dev_priv))
 404                 i830_overlay_clock_gating(dev_priv, true);
 405 }
 406
 407 /* overlay needs to be disabled in OCMD reg */
 408 static int intel_overlay_off(struct intel_overlay *overlay)
 409 {
 410         struct drm_i915_private *dev_priv = overlay->i915;
 411         struct drm_i915_gem_request *req;
 412         struct intel_ring *ring;
 413         u32 flip_addr = overlay->flip_addr;
 414         int ret;
 415
 416         WARN_ON(!overlay->active);
 417
 418         /* According to intel docs the overlay hw may hang (when switching
 419          * off) without loading the filter coeffs. It is however unclear whether
 420          * this applies to the disabling of the overlay or to the switching off
 421          * of the hw. Do it in both cases */
 422         flip_addr |= OFC_UPDATE;
 423
 424         req = alloc_request(overlay);
 425         if (IS_ERR(req))
 426                 return PTR_ERR(req);
 427
 428         ret = intel_ring_begin(req, 6);
 429         if (ret) {
 430                 i915_add_request_no_flush(req);
 431                 return ret;
 432         }
 433
 434         ring = req->ring;
 435         /* wait for overlay to go idle */
 436         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 437         intel_ring_emit(ring, flip_addr);
 438         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 439         /* turn overlay off */
 440         if (IS_I830(dev_priv)) {
 441                 /* Workaround: Don't disable the overlay fully, since otherwise
 442                  * it dies on the next OVERLAY_ON cmd. */
 443                 intel_ring_emit(ring, MI_NOOP);
 444                 intel_ring_emit(ring, MI_NOOP);
 445                 intel_ring_emit(ring, MI_NOOP);
 446         } else {
 447                 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
 448                 intel_ring_emit(ring, flip_addr);
 449                 intel_ring_emit(ring,
 450                                 MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 451         }
 452         intel_ring_advance(ring);
 453
 454         intel_overlay_flip_prepare(overlay, NULL);
 455
 456         return intel_overlay_do_wait_request(overlay, req,
 457                                              intel_overlay_off_tail);
 458 }
 459
 460 /* recover from an interruption due to a signal
 461  * We have to be careful not to repeat work forever an make forward progess. */
 462 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 463 {
 464         return i915_gem_active_retire(&overlay->last_flip,
 465                                       &overlay->i915->drm.struct_mutex);
 466 }
 467
 468 /* Wait for pending overlay flip and release old frame.
 469  * Needs to be called before the overlay register are changed
 470  * via intel_overlay_(un)map_regs
 471  */
 472 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 473 {
 474         struct drm_i915_private *dev_priv = overlay->i915;
 475         int ret;
 476
 477         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 478
 479         /* Only wait if there is actually an old frame to release to
 480          * guarantee forward progress.
 481          */
 482         if (!overlay->old_vma)
 483                 return 0;
 484
 485         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 486                 /* synchronous slowpath */
 487                 struct drm_i915_gem_request *req;
 488                 struct intel_ring *ring;
 489
 490                 req = alloc_request(overlay);
 491                 if (IS_ERR(req))
 492                         return PTR_ERR(req);
 493
 494                 ret = intel_ring_begin(req, 2);
 495                 if (ret) {
 496                         i915_add_request_no_flush(req);
 497                         return ret;
 498                 }
 499
 500                 ring = req->ring;
 501                 intel_ring_emit(ring,
 502                                 MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 503                 intel_ring_emit(ring, MI_NOOP);
 504                 intel_ring_advance(ring);
 505
 506                 ret = intel_overlay_do_wait_request(overlay, req,
 507                                                     intel_overlay_release_old_vid_tail);
 508                 if (ret)
 509                         return ret;
 510         } else
 511                 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
 512
 513         return 0;
 514 }
 515
 516 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 517 {
 518         struct intel_overlay *overlay = dev_priv->overlay;
 519
 520         if (!overlay)
 521                 return;
 522
 523         intel_overlay_release_old_vid(overlay);
 524
 525         overlay->old_xscale = 0;
 526         overlay->old_yscale = 0;
 527         overlay->crtc = NULL;
 528         overlay->active = false;
 529 }
 530
 531 struct put_image_params {
 532         int format;
 533         short dst_x;
 534         short dst_y;
 535         short dst_w;
 536         short dst_h;
 537         short src_w;
 538         short src_scan_h;
 539         short src_scan_w;
 540         short src_h;
 541         short stride_Y;
 542         short stride_UV;
 543         int offset_Y;
 544         int offset_U;
 545         int offset_V;
 546 };
 547
 548 static int packed_depth_bytes(u32 format)
 549 {
 550         switch (format & I915_OVERLAY_DEPTH_MASK) {
 551         case I915_OVERLAY_YUV422:
 552                 return 4;
 553         case I915_OVERLAY_YUV411:
 554                 /* return 6; not implemented */
 555         default:
 556                 return -EINVAL;
 557         }
 558 }
 559
 560 static int packed_width_bytes(u32 format, short width)
 561 {
 562         switch (format & I915_OVERLAY_DEPTH_MASK) {
 563         case I915_OVERLAY_YUV422:
 564                 return width << 1;
 565         default:
 566                 return -EINVAL;
 567         }
 568 }
 569
 570 static int uv_hsubsampling(u32 format)
 571 {
 572         switch (format & I915_OVERLAY_DEPTH_MASK) {
 573         case I915_OVERLAY_YUV422:
 574         case I915_OVERLAY_YUV420:
 575                 return 2;
 576         case I915_OVERLAY_YUV411:
 577         case I915_OVERLAY_YUV410:
 578                 return 4;
 579         default:
 580                 return -EINVAL;
 581         }
 582 }
 583
 584 static int uv_vsubsampling(u32 format)
 585 {
 586         switch (format & I915_OVERLAY_DEPTH_MASK) {
 587         case I915_OVERLAY_YUV420:
 588         case I915_OVERLAY_YUV410:
 589                 return 2;
 590         case I915_OVERLAY_YUV422:
 591         case I915_OVERLAY_YUV411:
 592                 return 1;
 593         default:
 594                 return -EINVAL;
 595         }
 596 }
 597
 598 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
 599 {
 600         u32 sw;
 601
 602         if (IS_GEN2(dev_priv))
 603                 sw = ALIGN((offset & 31) + width, 32);
 604         else
 605                 sw = ALIGN((offset & 63) + width, 64);
 606
 607         if (sw == 0)
 608                 return 0;
 609
 610         return (sw - 32) >> 3;
 611 }
 612
 613 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
 614         [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
 615         [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
 616         [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
 617         [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
 618         [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
 619         [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
 620         [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
 621         [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
 622         [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
 623         [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
 624         [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
 625         [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
 626         [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
 627         [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
 628         [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
 629         [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
 630         [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
 631 };
 632
 633 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
 634         [ 0] = { 0x3000, 0x1800, 0x1800, },
 635         [ 1] = { 0xb000, 0x18d0, 0x2e60, },
 636         [ 2] = { 0xb000, 0x1990, 0x2ce0, },
 637         [ 3] = { 0xb020, 0x1a68, 0x2b40, },
 638         [ 4] = { 0xb040, 0x1b20, 0x29e0, },
 639         [ 5] = { 0xb060, 0x1bd8, 0x2880, },
 640         [ 6] = { 0xb080, 0x1c88, 0x3e60, },
 641         [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
 642         [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
 643         [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
 644         [10] = { 0xb100, 0x1eb8, 0x3620, },
 645         [11] = { 0xb100, 0x1f18, 0x34a0, },
 646         [12] = { 0xb100, 0x1f68, 0x3360, },
 647         [13] = { 0xb0e0, 0x1fa8, 0x3240, },
 648         [14] = { 0xb0c0, 0x1fe0, 0x3140, },
 649         [15] = { 0xb060, 0x1ff0, 0x30a0, },
 650         [16] = { 0x3000, 0x0800, 0x3000, },
 651 };
 652
 653 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 654 {
 655         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 656         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 657                     sizeof(uv_static_hcoeffs));
 658 }
 659
 660 static bool update_scaling_factors(struct intel_overlay *overlay,
 661                                    struct overlay_registers __iomem *regs,
 662                                    struct put_image_params *params)
 663 {
 664         /* fixed point with a 12 bit shift */
 665         u32 xscale, yscale, xscale_UV, yscale_UV;
 666 #define FP_SHIFT 12
 667 #define FRACT_MASK 0xfff
 668         bool scale_changed = false;
 669         int uv_hscale = uv_hsubsampling(params->format);
 670         int uv_vscale = uv_vsubsampling(params->format);
 671
 672         if (params->dst_w > 1)
 673                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 674                         /(params->dst_w);
 675         else
 676                 xscale = 1 << FP_SHIFT;
 677
 678         if (params->dst_h > 1)
 679                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 680                         /(params->dst_h);
 681         else
 682                 yscale = 1 << FP_SHIFT;
 683
 684         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 685         xscale_UV = xscale/uv_hscale;
 686         yscale_UV = yscale/uv_vscale;
 687         /* make the Y scale to UV scale ratio an exact multiply */
 688         xscale = xscale_UV * uv_hscale;
 689         yscale = yscale_UV * uv_vscale;
 690         /*} else {
 691           xscale_UV = 0;
 692           yscale_UV = 0;
 693           }*/
 694
 695         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 696                 scale_changed = true;
 697         overlay->old_xscale = xscale;
 698         overlay->old_yscale = yscale;
 699
 700         iowrite32(((yscale & FRACT_MASK) << 20) |
 701                   ((xscale >> FP_SHIFT)  << 16) |
 702                   ((xscale & FRACT_MASK) << 3),
 703                  &regs->YRGBSCALE);
 704
 705         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 706                   ((xscale_UV >> FP_SHIFT)  << 16) |
 707                   ((xscale_UV & FRACT_MASK) << 3),
 708                  &regs->UVSCALE);
 709
 710         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 711                    ((yscale_UV >> FP_SHIFT) << 0)),
 712                  &regs->UVSCALEV);
 713
 714         if (scale_changed)
 715                 update_polyphase_filter(regs);
 716
 717         return scale_changed;
 718 }
 719
 720 static void update_colorkey(struct intel_overlay *overlay,
 721                             struct overlay_registers __iomem *regs)
 722 {
 723         const struct intel_plane_state *state =
 724                 to_intel_plane_state(overlay->crtc->base.primary->state);
 725         u32 key = overlay->color_key;
 726         u32 format = 0;
 727         u32 flags = 0;
 728
 729         if (overlay->color_key_enabled)
 730                 flags |= DST_KEY_ENABLE;
 731
 732         if (state->base.visible)
 733                 format = state->base.fb->pixel_format;
 734
 735         switch (format) {
 736         case DRM_FORMAT_C8:
 737                 key = 0;
 738                 flags |= CLK_RGB8I_MASK;
 739                 break;
 740         case DRM_FORMAT_XRGB1555:
 741                 key = RGB15_TO_COLORKEY(key);
 742                 flags |= CLK_RGB15_MASK;
 743                 break;
 744         case DRM_FORMAT_RGB565:
 745                 key = RGB16_TO_COLORKEY(key);
 746                 flags |= CLK_RGB16_MASK;
 747                 break;
 748         default:
 749                 flags |= CLK_RGB24_MASK;
 750                 break;
 751         }
 752
 753         iowrite32(key, &regs->DCLRKV);
 754         iowrite32(flags, &regs->DCLRKM);
 755 }
 756
 757 static u32 overlay_cmd_reg(struct put_image_params *params)
 758 {
 759         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 760
 761         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 762                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 763                 case I915_OVERLAY_YUV422:
 764                         cmd |= OCMD_YUV_422_PLANAR;
 765                         break;
 766                 case I915_OVERLAY_YUV420:
 767                         cmd |= OCMD_YUV_420_PLANAR;
 768                         break;
 769                 case I915_OVERLAY_YUV411:
 770                 case I915_OVERLAY_YUV410:
 771                         cmd |= OCMD_YUV_410_PLANAR;
 772                         break;
 773                 }
 774         } else { /* YUV packed */
 775                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 776                 case I915_OVERLAY_YUV422:
 777                         cmd |= OCMD_YUV_422_PACKED;
 778                         break;
 779                 case I915_OVERLAY_YUV411:
 780                         cmd |= OCMD_YUV_411_PACKED;
 781                         break;
 782                 }
 783
 784                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 785                 case I915_OVERLAY_NO_SWAP:
 786                         break;
 787                 case I915_OVERLAY_UV_SWAP:
 788                         cmd |= OCMD_UV_SWAP;
 789                         break;
 790                 case I915_OVERLAY_Y_SWAP:
 791                         cmd |= OCMD_Y_SWAP;
 792                         break;
 793                 case I915_OVERLAY_Y_AND_UV_SWAP:
 794                         cmd |= OCMD_Y_AND_UV_SWAP;
 795                         break;
 796                 }
 797         }
 798
 799         return cmd;
 800 }
 801
 802 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 803                                       struct drm_i915_gem_object *new_bo,
 804                                       struct put_image_params *params)
 805 {
 806         int ret, tmp_width;
 807         struct overlay_registers __iomem *regs;
 808         bool scale_changed = false;
 809         struct drm_i915_private *dev_priv = overlay->i915;
 810         u32 swidth, swidthsw, sheight, ostride;
 811         enum pipe pipe = overlay->crtc->pipe;
 812         struct i915_vma *vma;
 813
 814         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 815         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 816
 817         ret = intel_overlay_release_old_vid(overlay);
 818         if (ret != 0)
 819                 return ret;
 820
 821         vma = i915_gem_object_pin_to_display_plane(new_bo, 0,
 822                                                    &i915_ggtt_view_normal);
 823         if (IS_ERR(vma))
 824                 return PTR_ERR(vma);
 825
 826         ret = i915_vma_put_fence(vma);
 827         if (ret)
 828                 goto out_unpin;
 829
 830         if (!overlay->active) {
 831                 u32 oconfig;
 832                 regs = intel_overlay_map_regs(overlay);
 833                 if (!regs) {
 834                         ret = -ENOMEM;
 835                         goto out_unpin;
 836                 }
 837                 oconfig = OCONF_CC_OUT_8BIT;
 838                 if (IS_GEN4(dev_priv))
 839                         oconfig |= OCONF_CSC_MODE_BT709;
 840                 oconfig |= pipe == 0 ?
 841                         OCONF_PIPE_A : OCONF_PIPE_B;
 842                 iowrite32(oconfig, &regs->OCONFIG);
 843                 intel_overlay_unmap_regs(overlay, regs);
 844
 845                 ret = intel_overlay_on(overlay);
 846                 if (ret != 0)
 847                         goto out_unpin;
 848         }
 849
 850         regs = intel_overlay_map_regs(overlay);
 851         if (!regs) {
 852                 ret = -ENOMEM;
 853                 goto out_unpin;
 854         }
 855
 856         iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
 857         iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
 858
 859         if (params->format & I915_OVERLAY_YUV_PACKED)
 860                 tmp_width = packed_width_bytes(params->format, params->src_w);
 861         else
 862                 tmp_width = params->src_w;
 863
 864         swidth = params->src_w;
 865         swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
 866         sheight = params->src_h;
 867         iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 868         ostride = params->stride_Y;
 869
 870         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 871                 int uv_hscale = uv_hsubsampling(params->format);
 872                 int uv_vscale = uv_vsubsampling(params->format);
 873                 u32 tmp_U, tmp_V;
 874                 swidth |= (params->src_w/uv_hscale) << 16;
 875                 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
 876                                       params->src_w/uv_hscale);
 877                 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
 878                                       params->src_w/uv_hscale);
 879                 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
 880                 sheight |= (params->src_h/uv_vscale) << 16;
 881                 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 882                           &regs->OBUF_0U);
 883                 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 884                           &regs->OBUF_0V);
 885                 ostride |= params->stride_UV << 16;
 886         }
 887
 888         iowrite32(swidth, &regs->SWIDTH);
 889         iowrite32(swidthsw, &regs->SWIDTHSW);
 890         iowrite32(sheight, &regs->SHEIGHT);
 891         iowrite32(ostride, &regs->OSTRIDE);
 892
 893         scale_changed = update_scaling_factors(overlay, regs, params);
 894
 895         update_colorkey(overlay, regs);
 896
 897         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 898
 899         intel_overlay_unmap_regs(overlay, regs);
 900
 901         ret = intel_overlay_continue(overlay, vma, scale_changed);
 902         if (ret)
 903                 goto out_unpin;
 904
 905         return 0;
 906
 907 out_unpin:
 908         i915_gem_object_unpin_from_display_plane(vma);
 909         return ret;
 910 }
 911
 912 int intel_overlay_switch_off(struct intel_overlay *overlay)
 913 {
 914         struct drm_i915_private *dev_priv = overlay->i915;
 915         struct overlay_registers __iomem *regs;
 916         int ret;
 917
 918         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 919         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 920
 921         ret = intel_overlay_recover_from_interrupt(overlay);
 922         if (ret != 0)
 923                 return ret;
 924
 925         if (!overlay->active)
 926                 return 0;
 927
 928         ret = intel_overlay_release_old_vid(overlay);
 929         if (ret != 0)
 930                 return ret;
 931
 932         regs = intel_overlay_map_regs(overlay);
 933         iowrite32(0, &regs->OCMD);
 934         intel_overlay_unmap_regs(overlay, regs);
 935
 936         return intel_overlay_off(overlay);
 937 }
 938
 939 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 940                                           struct intel_crtc *crtc)
 941 {
 942         if (!crtc->active)
 943                 return -EINVAL;
 944
 945         /* can't use the overlay with double wide pipe */
 946         if (crtc->config->double_wide)
 947                 return -EINVAL;
 948
 949         return 0;
 950 }
 951
 952 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 953 {
 954         struct drm_i915_private *dev_priv = overlay->i915;
 955         u32 pfit_control = I915_READ(PFIT_CONTROL);
 956         u32 ratio;
 957
 958         /* XXX: This is not the same logic as in the xorg driver, but more in
 959          * line with the intel documentation for the i965
 960          */
 961         if (INTEL_GEN(dev_priv) >= 4) {
 962                 /* on i965 use the PGM reg to read out the autoscaler values */
 963                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 964         } else {
 965                 if (pfit_control & VERT_AUTO_SCALE)
 966                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 967                 else
 968                         ratio = I915_READ(PFIT_PGM_RATIOS);
 969                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 970         }
 971
 972         overlay->pfit_vscale_ratio = ratio;
 973 }
 974
 975 static int check_overlay_dst(struct intel_overlay *overlay,
 976                              struct drm_intel_overlay_put_image *rec)
 977 {
 978         const struct intel_crtc_state *pipe_config =
 979                 overlay->crtc->config;
 980
 981         if (rec->dst_x < pipe_config->pipe_src_w &&
 982             rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
 983             rec->dst_y < pipe_config->pipe_src_h &&
 984             rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
 985                 return 0;
 986         else
 987                 return -EINVAL;
 988 }
 989
 990 static int check_overlay_scaling(struct put_image_params *rec)
 991 {
 992         u32 tmp;
 993
 994         /* downscaling limit is 8.0 */
 995         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 996         if (tmp > 7)
 997                 return -EINVAL;
 998         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 999         if (tmp > 7)
1000                 return -EINVAL;
1001
1002         return 0;
1003 }
1004
1005 static int check_overlay_src(struct drm_i915_private *dev_priv,
1006                              struct drm_intel_overlay_put_image *rec,
1007                              struct drm_i915_gem_object *new_bo)
1008 {
1009         int uv_hscale = uv_hsubsampling(rec->flags);
1010         int uv_vscale = uv_vsubsampling(rec->flags);
1011         u32 stride_mask;
1012         int depth;
1013         u32 tmp;
1014
1015         /* check src dimensions */
1016         if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
1017                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
1018                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
1019                         return -EINVAL;
1020         } else {
1021                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
1022                     rec->src_width  > IMAGE_MAX_WIDTH)
1023                         return -EINVAL;
1024         }
1025
1026         /* better safe than sorry, use 4 as the maximal subsampling ratio */
1027         if (rec->src_height < N_VERT_Y_TAPS*4 ||
1028             rec->src_width  < N_HORIZ_Y_TAPS*4)
1029                 return -EINVAL;
1030
1031         /* check alignment constraints */
1032         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1033         case I915_OVERLAY_RGB:
1034                 /* not implemented */
1035                 return -EINVAL;
1036
1037         case I915_OVERLAY_YUV_PACKED:
1038                 if (uv_vscale != 1)
1039                         return -EINVAL;
1040
1041                 depth = packed_depth_bytes(rec->flags);
1042                 if (depth < 0)
1043                         return depth;
1044
1045                 /* ignore UV planes */
1046                 rec->stride_UV = 0;
1047                 rec->offset_U = 0;
1048                 rec->offset_V = 0;
1049                 /* check pixel alignment */
1050                 if (rec->offset_Y % depth)
1051                         return -EINVAL;
1052                 break;
1053
1054         case I915_OVERLAY_YUV_PLANAR:
1055                 if (uv_vscale < 0 || uv_hscale < 0)
1056                         return -EINVAL;
1057                 /* no offset restrictions for planar formats */
1058                 break;
1059
1060         default:
1061                 return -EINVAL;
1062         }
1063
1064         if (rec->src_width % uv_hscale)
1065                 return -EINVAL;
1066
1067         /* stride checking */
1068         if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1069                 stride_mask = 255;
1070         else
1071                 stride_mask = 63;
1072
1073         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1074                 return -EINVAL;
1075         if (IS_GEN4(dev_priv) && rec->stride_Y < 512)
1076                 return -EINVAL;
1077
1078         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1079                 4096 : 8192;
1080         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1081                 return -EINVAL;
1082
1083         /* check buffer dimensions */
1084         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1085         case I915_OVERLAY_RGB:
1086         case I915_OVERLAY_YUV_PACKED:
1087                 /* always 4 Y values per depth pixels */
1088                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1089                         return -EINVAL;
1090
1091                 tmp = rec->stride_Y*rec->src_height;
1092                 if (rec->offset_Y + tmp > new_bo->base.size)
1093                         return -EINVAL;
1094                 break;
1095
1096         case I915_OVERLAY_YUV_PLANAR:
1097                 if (rec->src_width > rec->stride_Y)
1098                         return -EINVAL;
1099                 if (rec->src_width/uv_hscale > rec->stride_UV)
1100                         return -EINVAL;
1101
1102                 tmp = rec->stride_Y * rec->src_height;
1103                 if (rec->offset_Y + tmp > new_bo->base.size)
1104                         return -EINVAL;
1105
1106                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1107                 if (rec->offset_U + tmp > new_bo->base.size ||
1108                     rec->offset_V + tmp > new_bo->base.size)
1109                         return -EINVAL;
1110                 break;
1111         }
1112
1113         return 0;
1114 }
1115
1116 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1117                                   struct drm_file *file_priv)
1118 {
1119         struct drm_intel_overlay_put_image *put_image_rec = data;
1120         struct drm_i915_private *dev_priv = to_i915(dev);
1121         struct intel_overlay *overlay;
1122         struct drm_crtc *drmmode_crtc;
1123         struct intel_crtc *crtc;
1124         struct drm_i915_gem_object *new_bo;
1125         struct put_image_params *params;
1126         int ret;
1127
1128         overlay = dev_priv->overlay;
1129         if (!overlay) {
1130                 DRM_DEBUG("userspace bug: no overlay\n");
1131                 return -ENODEV;
1132         }
1133
1134         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1135                 drm_modeset_lock_all(dev);
1136                 mutex_lock(&dev->struct_mutex);
1137
1138                 ret = intel_overlay_switch_off(overlay);
1139
1140                 mutex_unlock(&dev->struct_mutex);
1141                 drm_modeset_unlock_all(dev);
1142
1143                 return ret;
1144         }
1145
1146         params = kmalloc(sizeof(*params), GFP_KERNEL);
1147         if (!params)
1148                 return -ENOMEM;
1149
1150         drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1151         if (!drmmode_crtc) {
1152                 ret = -ENOENT;
1153                 goto out_free;
1154         }
1155         crtc = to_intel_crtc(drmmode_crtc);
1156
1157         new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle);
1158         if (!new_bo) {
1159                 ret = -ENOENT;
1160                 goto out_free;
1161         }
1162
1163         drm_modeset_lock_all(dev);
1164         mutex_lock(&dev->struct_mutex);
1165
1166         if (i915_gem_object_is_tiled(new_bo)) {
1167                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1168                 ret = -EINVAL;
1169                 goto out_unlock;
1170         }
1171
1172         ret = intel_overlay_recover_from_interrupt(overlay);
1173         if (ret != 0)
1174                 goto out_unlock;
1175
1176         if (overlay->crtc != crtc) {
1177                 ret = intel_overlay_switch_off(overlay);
1178                 if (ret != 0)
1179                         goto out_unlock;
1180
1181                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1182                 if (ret != 0)
1183                         goto out_unlock;
1184
1185                 overlay->crtc = crtc;
1186                 crtc->overlay = overlay;
1187
1188                 /* line too wide, i.e. one-line-mode */
1189                 if (crtc->config->pipe_src_w > 1024 &&
1190                     crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1191                         overlay->pfit_active = true;
1192                         update_pfit_vscale_ratio(overlay);
1193                 } else
1194                         overlay->pfit_active = false;
1195         }
1196
1197         ret = check_overlay_dst(overlay, put_image_rec);
1198         if (ret != 0)
1199                 goto out_unlock;
1200
1201         if (overlay->pfit_active) {
1202                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1203                                  overlay->pfit_vscale_ratio);
1204                 /* shifting right rounds downwards, so add 1 */
1205                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1206                                  overlay->pfit_vscale_ratio) + 1;
1207         } else {
1208                 params->dst_y = put_image_rec->dst_y;
1209                 params->dst_h = put_image_rec->dst_height;
1210         }
1211         params->dst_x = put_image_rec->dst_x;
1212         params->dst_w = put_image_rec->dst_width;
1213
1214         params->src_w = put_image_rec->src_width;
1215         params->src_h = put_image_rec->src_height;
1216         params->src_scan_w = put_image_rec->src_scan_width;
1217         params->src_scan_h = put_image_rec->src_scan_height;
1218         if (params->src_scan_h > params->src_h ||
1219             params->src_scan_w > params->src_w) {
1220                 ret = -EINVAL;
1221                 goto out_unlock;
1222         }
1223
1224         ret = check_overlay_src(dev_priv, put_image_rec, new_bo);
1225         if (ret != 0)
1226                 goto out_unlock;
1227         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1228         params->stride_Y = put_image_rec->stride_Y;
1229         params->stride_UV = put_image_rec->stride_UV;
1230         params->offset_Y = put_image_rec->offset_Y;
1231         params->offset_U = put_image_rec->offset_U;
1232         params->offset_V = put_image_rec->offset_V;
1233
1234         /* Check scaling after src size to prevent a divide-by-zero. */
1235         ret = check_overlay_scaling(params);
1236         if (ret != 0)
1237                 goto out_unlock;
1238
1239         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1240         if (ret != 0)
1241                 goto out_unlock;
1242
1243         mutex_unlock(&dev->struct_mutex);
1244         drm_modeset_unlock_all(dev);
1245         i915_gem_object_put(new_bo);
1246
1247         kfree(params);
1248
1249         return 0;
1250
1251 out_unlock:
1252         mutex_unlock(&dev->struct_mutex);
1253         drm_modeset_unlock_all(dev);
1254         i915_gem_object_put(new_bo);
1255 out_free:
1256         kfree(params);
1257
1258         return ret;
1259 }
1260
1261 static void update_reg_attrs(struct intel_overlay *overlay,
1262                              struct overlay_registers __iomem *regs)
1263 {
1264         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1265                   &regs->OCLRC0);
1266         iowrite32(overlay->saturation, &regs->OCLRC1);
1267 }
1268
1269 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1270 {
1271         int i;
1272
1273         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1274                 return false;
1275
1276         for (i = 0; i < 3; i++) {
1277                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1278                         return false;
1279         }
1280
1281         return true;
1282 }
1283
1284 static bool check_gamma5_errata(u32 gamma5)
1285 {
1286         int i;
1287
1288         for (i = 0; i < 3; i++) {
1289                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1290                         return false;
1291         }
1292
1293         return true;
1294 }
1295
1296 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1297 {
1298         if (!check_gamma_bounds(0, attrs->gamma0) ||
1299             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1300             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1301             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1302             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1303             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1304             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1305                 return -EINVAL;
1306
1307         if (!check_gamma5_errata(attrs->gamma5))
1308                 return -EINVAL;
1309
1310         return 0;
1311 }
1312
1313 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1314                               struct drm_file *file_priv)
1315 {
1316         struct drm_intel_overlay_attrs *attrs = data;
1317         struct drm_i915_private *dev_priv = to_i915(dev);
1318         struct intel_overlay *overlay;
1319         struct overlay_registers __iomem *regs;
1320         int ret;
1321
1322         overlay = dev_priv->overlay;
1323         if (!overlay) {
1324                 DRM_DEBUG("userspace bug: no overlay\n");
1325                 return -ENODEV;
1326         }
1327
1328         drm_modeset_lock_all(dev);
1329         mutex_lock(&dev->struct_mutex);
1330
1331         ret = -EINVAL;
1332         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1333                 attrs->color_key  = overlay->color_key;
1334                 attrs->brightness = overlay->brightness;
1335                 attrs->contrast   = overlay->contrast;
1336                 attrs->saturation = overlay->saturation;
1337
1338                 if (!IS_GEN2(dev_priv)) {
1339                         attrs->gamma0 = I915_READ(OGAMC0);
1340                         attrs->gamma1 = I915_READ(OGAMC1);
1341                         attrs->gamma2 = I915_READ(OGAMC2);
1342                         attrs->gamma3 = I915_READ(OGAMC3);
1343                         attrs->gamma4 = I915_READ(OGAMC4);
1344                         attrs->gamma5 = I915_READ(OGAMC5);
1345                 }
1346         } else {
1347                 if (attrs->brightness < -128 || attrs->brightness > 127)
1348                         goto out_unlock;
1349                 if (attrs->contrast > 255)
1350                         goto out_unlock;
1351                 if (attrs->saturation > 1023)
1352                         goto out_unlock;
1353
1354                 overlay->color_key  = attrs->color_key;
1355                 overlay->brightness = attrs->brightness;
1356                 overlay->contrast   = attrs->contrast;
1357                 overlay->saturation = attrs->saturation;
1358
1359                 regs = intel_overlay_map_regs(overlay);
1360                 if (!regs) {
1361                         ret = -ENOMEM;
1362                         goto out_unlock;
1363                 }
1364
1365                 update_reg_attrs(overlay, regs);
1366
1367                 intel_overlay_unmap_regs(overlay, regs);
1368
1369                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1370                         if (IS_GEN2(dev_priv))
1371                                 goto out_unlock;
1372
1373                         if (overlay->active) {
1374                                 ret = -EBUSY;
1375                                 goto out_unlock;
1376                         }
1377
1378                         ret = check_gamma(attrs);
1379                         if (ret)
1380                                 goto out_unlock;
1381
1382                         I915_WRITE(OGAMC0, attrs->gamma0);
1383                         I915_WRITE(OGAMC1, attrs->gamma1);
1384                         I915_WRITE(OGAMC2, attrs->gamma2);
1385                         I915_WRITE(OGAMC3, attrs->gamma3);
1386                         I915_WRITE(OGAMC4, attrs->gamma4);
1387                         I915_WRITE(OGAMC5, attrs->gamma5);
1388                 }
1389         }
1390         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1391
1392         ret = 0;
1393 out_unlock:
1394         mutex_unlock(&dev->struct_mutex);
1395         drm_modeset_unlock_all(dev);
1396
1397         return ret;
1398 }
1399
1400 void intel_setup_overlay(struct drm_i915_private *dev_priv)
1401 {
1402         struct intel_overlay *overlay;
1403         struct drm_i915_gem_object *reg_bo;
1404         struct overlay_registers __iomem *regs;
1405         struct i915_vma *vma = NULL;
1406         int ret;
1407
1408         if (!HAS_OVERLAY(dev_priv))
1409                 return;
1410
1411         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1412         if (!overlay)
1413                 return;
1414
1415         mutex_lock(&dev_priv->drm.struct_mutex);
1416         if (WARN_ON(dev_priv->overlay))
1417                 goto out_free;
1418
1419         overlay->i915 = dev_priv;
1420
1421         reg_bo = NULL;
1422         if (!OVERLAY_NEEDS_PHYSICAL(dev_priv))
1423                 reg_bo = i915_gem_object_create_stolen(dev_priv, PAGE_SIZE);
1424         if (reg_bo == NULL)
1425                 reg_bo = i915_gem_object_create(dev_priv, PAGE_SIZE);
1426         if (IS_ERR(reg_bo))
1427                 goto out_free;
1428         overlay->reg_bo = reg_bo;
1429
1430         if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) {
1431                 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
1432                 if (ret) {
1433                         DRM_ERROR("failed to attach phys overlay regs\n");
1434                         goto out_free_bo;
1435                 }
1436                 overlay->flip_addr = reg_bo->phys_handle->busaddr;
1437         } else {
1438                 vma = i915_gem_object_ggtt_pin(reg_bo, NULL,
1439                                                0, PAGE_SIZE, PIN_MAPPABLE);
1440                 if (IS_ERR(vma)) {
1441                         DRM_ERROR("failed to pin overlay register bo\n");
1442                         ret = PTR_ERR(vma);
1443                         goto out_free_bo;
1444                 }
1445                 overlay->flip_addr = i915_ggtt_offset(vma);
1446
1447                 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1448                 if (ret) {
1449                         DRM_ERROR("failed to move overlay register bo into the GTT\n");
1450                         goto out_unpin_bo;
1451                 }
1452         }
1453
1454         /* init all values */
1455         overlay->color_key = 0x0101fe;
1456         overlay->color_key_enabled = true;
1457         overlay->brightness = -19;
1458         overlay->contrast = 75;
1459         overlay->saturation = 146;
1460
1461         init_request_active(&overlay->last_flip, NULL);
1462
1463         regs = intel_overlay_map_regs(overlay);
1464         if (!regs)
1465                 goto out_unpin_bo;
1466
1467         memset_io(regs, 0, sizeof(struct overlay_registers));
1468         update_polyphase_filter(regs);
1469         update_reg_attrs(overlay, regs);
1470
1471         intel_overlay_unmap_regs(overlay, regs);
1472
1473         dev_priv->overlay = overlay;
1474         mutex_unlock(&dev_priv->drm.struct_mutex);
1475         DRM_INFO("initialized overlay support\n");
1476         return;
1477
1478 out_unpin_bo:
1479         if (vma)
1480                 i915_vma_unpin(vma);
1481 out_free_bo:
1482         i915_gem_object_put(reg_bo);
1483 out_free:
1484         mutex_unlock(&dev_priv->drm.struct_mutex);
1485         kfree(overlay);
1486         return;
1487 }
1488
1489 void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
1490 {
1491         if (!dev_priv->overlay)
1492                 return;
1493
1494         /* The bo's should be free'd by the generic code already.
1495          * Furthermore modesetting teardown happens beforehand so the
1496          * hardware should be off already */
1497         WARN_ON(dev_priv->overlay->active);
1498
1499         i915_gem_object_put(dev_priv->overlay->reg_bo);
1500         kfree(dev_priv->overlay);
1501 }
1502
1503 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1504
1505 struct intel_overlay_error_state {
1506         struct overlay_registers regs;
1507         unsigned long base;
1508         u32 dovsta;
1509         u32 isr;
1510 };
1511
1512 static struct overlay_registers __iomem *
1513 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1514 {
1515         struct drm_i915_private *dev_priv = overlay->i915;
1516         struct overlay_registers __iomem *regs;
1517
1518         if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
1519                 /* Cast to make sparse happy, but it's wc memory anyway, so
1520                  * equivalent to the wc io mapping on X86. */
1521                 regs = (struct overlay_registers __iomem *)
1522                         overlay->reg_bo->phys_handle->vaddr;
1523         else
1524                 regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.mappable,
1525                                                 overlay->flip_addr);
1526
1527         return regs;
1528 }
1529
1530 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1531                                         struct overlay_registers __iomem *regs)
1532 {
1533         if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
1534                 io_mapping_unmap_atomic(regs);
1535 }
1536
1537 struct intel_overlay_error_state *
1538 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1539 {
1540         struct intel_overlay *overlay = dev_priv->overlay;
1541         struct intel_overlay_error_state *error;
1542         struct overlay_registers __iomem *regs;
1543
1544         if (!overlay || !overlay->active)
1545                 return NULL;
1546
1547         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1548         if (error == NULL)
1549                 return NULL;
1550
1551         error->dovsta = I915_READ(DOVSTA);
1552         error->isr = I915_READ(ISR);
1553         error->base = overlay->flip_addr;
1554
1555         regs = intel_overlay_map_regs_atomic(overlay);
1556         if (!regs)
1557                 goto err;
1558
1559         memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1560         intel_overlay_unmap_regs_atomic(overlay, regs);
1561
1562         return error;
1563
1564 err:
1565         kfree(error);
1566         return NULL;
1567 }
1568
1569 void
1570 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1571                                 struct intel_overlay_error_state *error)
1572 {
1573         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1574                           error->dovsta, error->isr);
1575         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1576                           error->base);
1577
1578 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1579         P(OBUF_0Y);
1580         P(OBUF_1Y);
1581         P(OBUF_0U);
1582         P(OBUF_0V);
1583         P(OBUF_1U);
1584         P(OBUF_1V);
1585         P(OSTRIDE);
1586         P(YRGB_VPH);
1587         P(UV_VPH);
1588         P(HORZ_PH);
1589         P(INIT_PHS);
1590         P(DWINPOS);
1591         P(DWINSZ);
1592         P(SWIDTH);
1593         P(SWIDTHSW);
1594         P(SHEIGHT);
1595         P(YRGBSCALE);
1596         P(UVSCALE);
1597         P(OCLRC0);
1598         P(OCLRC1);
1599         P(DCLRKV);
1600         P(DCLRKM);
1601         P(SCLRKVH);
1602         P(SCLRKVL);
1603         P(SCLRKEN);
1604         P(OCONFIG);
1605         P(OCMD);
1606         P(OSTART_0Y);
1607         P(OSTART_1Y);
1608         P(OSTART_0U);
1609         P(OSTART_0V);
1610         P(OSTART_1U);
1611         P(OSTART_1V);
1612         P(OTILEOFF_0Y);
1613         P(OTILEOFF_1Y);
1614         P(OTILEOFF_0U);
1615         P(OTILEOFF_0V);
1616         P(OTILEOFF_1U);
1617         P(OTILEOFF_1V);
1618         P(FASTHSCALE);
1619         P(UVSCALEV);
1620 #undef P
1621 }
1622
1623 #endif