drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         I915_WRITE(GEN8_CONFIG0,
  66                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  67
  68         /* WaEnableChickenDCPR:skl,bxt,kbl,glk */
  69         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  70                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  71
  72         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  73         /* WaFbcWakeMemOn:skl,bxt,kbl,glk */
  74         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  75                    DISP_FBC_WM_DIS |
  76                    DISP_FBC_MEMORY_WAKE);
  77
  78         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  79         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  80                    ILK_DPFC_DISABLE_DUMMY0);
  81 }
  82
  83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
  84 {
  85         gen9_init_clock_gating(dev_priv);
  86
  87         /* WaDisableSDEUnitClockGating:bxt */
  88         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  89                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  90
  91         /*
  92          * FIXME:
  93          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  94          */
  95         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  96                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  97
  98         /*
  99          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 100          * to stay fully on.
 101          */
 102         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 103                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 104 }
 105
 106 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 107 {
 108         gen9_init_clock_gating(dev_priv);
 109
 110         /*
 111          * WaDisablePWMClockGating:glk
 112          * Backlight PWM may stop in the asserted state, causing backlight
 113          * to stay fully on.
 114          */
 115         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 116                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 117
 118         /* WaDDIIOTimeout:glk */
 119         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
 120                 u32 val = I915_READ(CHICKEN_MISC_2);
 121                 val &= ~(GLK_CL0_PWR_DOWN |
 122                          GLK_CL1_PWR_DOWN |
 123                          GLK_CL2_PWR_DOWN);
 124                 I915_WRITE(CHICKEN_MISC_2, val);
 125         }
 126
 127 }
 128
 129 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 130 {
 131         u32 tmp;
 132
 133         tmp = I915_READ(CLKCFG);
 134
 135         switch (tmp & CLKCFG_FSB_MASK) {
 136         case CLKCFG_FSB_533:
 137                 dev_priv->fsb_freq = 533; /* 133*4 */
 138                 break;
 139         case CLKCFG_FSB_800:
 140                 dev_priv->fsb_freq = 800; /* 200*4 */
 141                 break;
 142         case CLKCFG_FSB_667:
 143                 dev_priv->fsb_freq =  667; /* 167*4 */
 144                 break;
 145         case CLKCFG_FSB_400:
 146                 dev_priv->fsb_freq = 400; /* 100*4 */
 147                 break;
 148         }
 149
 150         switch (tmp & CLKCFG_MEM_MASK) {
 151         case CLKCFG_MEM_533:
 152                 dev_priv->mem_freq = 533;
 153                 break;
 154         case CLKCFG_MEM_667:
 155                 dev_priv->mem_freq = 667;
 156                 break;
 157         case CLKCFG_MEM_800:
 158                 dev_priv->mem_freq = 800;
 159                 break;
 160         }
 161
 162         /* detect pineview DDR3 setting */
 163         tmp = I915_READ(CSHRDDR3CTL);
 164         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 165 }
 166
 167 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 168 {
 169         u16 ddrpll, csipll;
 170
 171         ddrpll = I915_READ16(DDRMPLL1);
 172         csipll = I915_READ16(CSIPLL0);
 173
 174         switch (ddrpll & 0xff) {
 175         case 0xc:
 176                 dev_priv->mem_freq = 800;
 177                 break;
 178         case 0x10:
 179                 dev_priv->mem_freq = 1066;
 180                 break;
 181         case 0x14:
 182                 dev_priv->mem_freq = 1333;
 183                 break;
 184         case 0x18:
 185                 dev_priv->mem_freq = 1600;
 186                 break;
 187         default:
 188                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 189                                  ddrpll & 0xff);
 190                 dev_priv->mem_freq = 0;
 191                 break;
 192         }
 193
 194         dev_priv->ips.r_t = dev_priv->mem_freq;
 195
 196         switch (csipll & 0x3ff) {
 197         case 0x00c:
 198                 dev_priv->fsb_freq = 3200;
 199                 break;
 200         case 0x00e:
 201                 dev_priv->fsb_freq = 3733;
 202                 break;
 203         case 0x010:
 204                 dev_priv->fsb_freq = 4266;
 205                 break;
 206         case 0x012:
 207                 dev_priv->fsb_freq = 4800;
 208                 break;
 209         case 0x014:
 210                 dev_priv->fsb_freq = 5333;
 211                 break;
 212         case 0x016:
 213                 dev_priv->fsb_freq = 5866;
 214                 break;
 215         case 0x018:
 216                 dev_priv->fsb_freq = 6400;
 217                 break;
 218         default:
 219                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 220                                  csipll & 0x3ff);
 221                 dev_priv->fsb_freq = 0;
 222                 break;
 223         }
 224
 225         if (dev_priv->fsb_freq == 3200) {
 226                 dev_priv->ips.c_m = 0;
 227         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 228                 dev_priv->ips.c_m = 1;
 229         } else {
 230                 dev_priv->ips.c_m = 2;
 231         }
 232 }
 233
 234 static const struct cxsr_latency cxsr_latency_table[] = {
 235         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 236         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 237         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 238         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 239         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 240
 241         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 242         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 243         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 244         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 245         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 246
 247         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 248         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 249         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 250         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 251         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 252
 253         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 254         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 255         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 256         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 257         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 258
 259         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 260         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 261         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 262         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 263         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 264
 265         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 266         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 267         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 268         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 269         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 270 };
 271
 272 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 273                                                          bool is_ddr3,
 274                                                          int fsb,
 275                                                          int mem)
 276 {
 277         const struct cxsr_latency *latency;
 278         int i;
 279
 280         if (fsb == 0 || mem == 0)
 281                 return NULL;
 282
 283         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 284                 latency = &cxsr_latency_table[i];
 285                 if (is_desktop == latency->is_desktop &&
 286                     is_ddr3 == latency->is_ddr3 &&
 287                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 288                         return latency;
 289         }
 290
 291         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 292
 293         return NULL;
 294 }
 295
 296 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 297 {
 298         u32 val;
 299
 300         mutex_lock(&dev_priv->rps.hw_lock);
 301
 302         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 303         if (enable)
 304                 val &= ~FORCE_DDR_HIGH_FREQ;
 305         else
 306                 val |= FORCE_DDR_HIGH_FREQ;
 307         val &= ~FORCE_DDR_LOW_FREQ;
 308         val |= FORCE_DDR_FREQ_REQ_ACK;
 309         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 310
 311         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 312                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 313                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 314
 315         mutex_unlock(&dev_priv->rps.hw_lock);
 316 }
 317
 318 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 319 {
 320         u32 val;
 321
 322         mutex_lock(&dev_priv->rps.hw_lock);
 323
 324         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 325         if (enable)
 326                 val |= DSP_MAXFIFO_PM5_ENABLE;
 327         else
 328                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 329         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 330
 331         mutex_unlock(&dev_priv->rps.hw_lock);
 332 }
 333
 334 #define FW_WM(value, plane) \
 335         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 336
 337 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 338 {
 339         bool was_enabled;
 340         u32 val;
 341
 342         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 343                 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 344                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 345                 POSTING_READ(FW_BLC_SELF_VLV);
 346         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 347                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 348                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 349                 POSTING_READ(FW_BLC_SELF);
 350         } else if (IS_PINEVIEW(dev_priv)) {
 351                 val = I915_READ(DSPFW3);
 352                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 353                 if (enable)
 354                         val |= PINEVIEW_SELF_REFRESH_EN;
 355                 else
 356                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 357                 I915_WRITE(DSPFW3, val);
 358                 POSTING_READ(DSPFW3);
 359         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 360                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 361                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 362                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 363                 I915_WRITE(FW_BLC_SELF, val);
 364                 POSTING_READ(FW_BLC_SELF);
 365         } else if (IS_I915GM(dev_priv)) {
 366                 /*
 367                  * FIXME can't find a bit like this for 915G, and
 368                  * and yet it does have the related watermark in
 369                  * FW_BLC_SELF. What's going on?
 370                  */
 371                 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 372                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 373                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 374                 I915_WRITE(INSTPM, val);
 375                 POSTING_READ(INSTPM);
 376         } else {
 377                 return false;
 378         }
 379
 380         DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
 381                       enableddisabled(enable),
 382                       enableddisabled(was_enabled));
 383
 384         return was_enabled;
 385 }
 386
 387 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 388 {
 389         bool ret;
 390
 391         mutex_lock(&dev_priv->wm.wm_mutex);
 392         ret = _intel_set_memory_cxsr(dev_priv, enable);
 393         dev_priv->wm.vlv.cxsr = enable;
 394         mutex_unlock(&dev_priv->wm.wm_mutex);
 395
 396         return ret;
 397 }
 398
 399 /*
 400  * Latency for FIFO fetches is dependent on several factors:
 401  *   - memory configuration (speed, channels)
 402  *   - chipset
 403  *   - current MCH state
 404  * It can be fairly high in some situations, so here we assume a fairly
 405  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 406  * set this value too high, the FIFO will fetch frequently to stay full)
 407  * and power consumption (set it too low to save power and we might see
 408  * FIFO underruns and display "flicker").
 409  *
 410  * A value of 5us seems to be a good balance; safe for very low end
 411  * platforms but not overly aggressive on lower latency configs.
 412  */
 413 static const int pessimal_latency_ns = 5000;
 414
 415 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 416         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 417
 418 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 419 {
 420         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 421         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 422         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 423         enum pipe pipe = crtc->pipe;
 424         int sprite0_start, sprite1_start;
 425
 426         switch (pipe) {
 427                 uint32_t dsparb, dsparb2, dsparb3;
 428         case PIPE_A:
 429                 dsparb = I915_READ(DSPARB);
 430                 dsparb2 = I915_READ(DSPARB2);
 431                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 432                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 433                 break;
 434         case PIPE_B:
 435                 dsparb = I915_READ(DSPARB);
 436                 dsparb2 = I915_READ(DSPARB2);
 437                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 438                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 439                 break;
 440         case PIPE_C:
 441                 dsparb2 = I915_READ(DSPARB2);
 442                 dsparb3 = I915_READ(DSPARB3);
 443                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 444                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 445                 break;
 446         default:
 447                 MISSING_CASE(pipe);
 448                 return;
 449         }
 450
 451         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 452         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 453         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 454         fifo_state->plane[PLANE_CURSOR] = 63;
 455
 456         DRM_DEBUG_KMS("Pipe %c FIFO size: %d/%d/%d/%d\n",
 457                       pipe_name(pipe),
 458                       fifo_state->plane[PLANE_PRIMARY],
 459                       fifo_state->plane[PLANE_SPRITE0],
 460                       fifo_state->plane[PLANE_SPRITE1],
 461                       fifo_state->plane[PLANE_CURSOR]);
 462 }
 463
 464 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 465 {
 466         uint32_t dsparb = I915_READ(DSPARB);
 467         int size;
 468
 469         size = dsparb & 0x7f;
 470         if (plane)
 471                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 472
 473         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 474                       plane ? "B" : "A", size);
 475
 476         return size;
 477 }
 478
 479 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 480 {
 481         uint32_t dsparb = I915_READ(DSPARB);
 482         int size;
 483
 484         size = dsparb & 0x1ff;
 485         if (plane)
 486                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 487         size >>= 1; /* Convert to cachelines */
 488
 489         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 490                       plane ? "B" : "A", size);
 491
 492         return size;
 493 }
 494
 495 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 496 {
 497         uint32_t dsparb = I915_READ(DSPARB);
 498         int size;
 499
 500         size = dsparb & 0x7f;
 501         size >>= 2; /* Convert to cachelines */
 502
 503         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 504                       plane ? "B" : "A",
 505                       size);
 506
 507         return size;
 508 }
 509
 510 /* Pineview has different values for various configs */
 511 static const struct intel_watermark_params pineview_display_wm = {
 512         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 513         .max_wm = PINEVIEW_MAX_WM,
 514         .default_wm = PINEVIEW_DFT_WM,
 515         .guard_size = PINEVIEW_GUARD_WM,
 516         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 519         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 520         .max_wm = PINEVIEW_MAX_WM,
 521         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 522         .guard_size = PINEVIEW_GUARD_WM,
 523         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params pineview_cursor_wm = {
 526         .fifo_size = PINEVIEW_CURSOR_FIFO,
 527         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 528         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 529         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 530         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 531 };
 532 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 533         .fifo_size = PINEVIEW_CURSOR_FIFO,
 534         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 535         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 536         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 537         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 538 };
 539 static const struct intel_watermark_params g4x_wm_info = {
 540         .fifo_size = G4X_FIFO_SIZE,
 541         .max_wm = G4X_MAX_WM,
 542         .default_wm = G4X_MAX_WM,
 543         .guard_size = 2,
 544         .cacheline_size = G4X_FIFO_LINE_SIZE,
 545 };
 546 static const struct intel_watermark_params g4x_cursor_wm_info = {
 547         .fifo_size = I965_CURSOR_FIFO,
 548         .max_wm = I965_CURSOR_MAX_WM,
 549         .default_wm = I965_CURSOR_DFT_WM,
 550         .guard_size = 2,
 551         .cacheline_size = G4X_FIFO_LINE_SIZE,
 552 };
 553 static const struct intel_watermark_params i965_cursor_wm_info = {
 554         .fifo_size = I965_CURSOR_FIFO,
 555         .max_wm = I965_CURSOR_MAX_WM,
 556         .default_wm = I965_CURSOR_DFT_WM,
 557         .guard_size = 2,
 558         .cacheline_size = I915_FIFO_LINE_SIZE,
 559 };
 560 static const struct intel_watermark_params i945_wm_info = {
 561         .fifo_size = I945_FIFO_SIZE,
 562         .max_wm = I915_MAX_WM,
 563         .default_wm = 1,
 564         .guard_size = 2,
 565         .cacheline_size = I915_FIFO_LINE_SIZE,
 566 };
 567 static const struct intel_watermark_params i915_wm_info = {
 568         .fifo_size = I915_FIFO_SIZE,
 569         .max_wm = I915_MAX_WM,
 570         .default_wm = 1,
 571         .guard_size = 2,
 572         .cacheline_size = I915_FIFO_LINE_SIZE,
 573 };
 574 static const struct intel_watermark_params i830_a_wm_info = {
 575         .fifo_size = I855GM_FIFO_SIZE,
 576         .max_wm = I915_MAX_WM,
 577         .default_wm = 1,
 578         .guard_size = 2,
 579         .cacheline_size = I830_FIFO_LINE_SIZE,
 580 };
 581 static const struct intel_watermark_params i830_bc_wm_info = {
 582         .fifo_size = I855GM_FIFO_SIZE,
 583         .max_wm = I915_MAX_WM/2,
 584         .default_wm = 1,
 585         .guard_size = 2,
 586         .cacheline_size = I830_FIFO_LINE_SIZE,
 587 };
 588 static const struct intel_watermark_params i845_wm_info = {
 589         .fifo_size = I830_FIFO_SIZE,
 590         .max_wm = I915_MAX_WM,
 591         .default_wm = 1,
 592         .guard_size = 2,
 593         .cacheline_size = I830_FIFO_LINE_SIZE,
 594 };
 595
 596 /**
 597  * intel_calculate_wm - calculate watermark level
 598  * @clock_in_khz: pixel clock
 599  * @wm: chip FIFO params
 600  * @cpp: bytes per pixel
 601  * @latency_ns: memory latency for the platform
 602  *
 603  * Calculate the watermark level (the level at which the display plane will
 604  * start fetching from memory again).  Each chip has a different display
 605  * FIFO size and allocation, so the caller needs to figure that out and pass
 606  * in the correct intel_watermark_params structure.
 607  *
 608  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 609  * on the pixel size.  When it reaches the watermark level, it'll start
 610  * fetching FIFO line sized based chunks from memory until the FIFO fills
 611  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 612  * will occur, and a display engine hang could result.
 613  */
 614 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 615                                         const struct intel_watermark_params *wm,
 616                                         int fifo_size, int cpp,
 617                                         unsigned long latency_ns)
 618 {
 619         long entries_required, wm_size;
 620
 621         /*
 622          * Note: we need to make sure we don't overflow for various clock &
 623          * latency values.
 624          * clocks go from a few thousand to several hundred thousand.
 625          * latency is usually a few thousand
 626          */
 627         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 628                 1000;
 629         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 630
 631         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 632
 633         wm_size = fifo_size - (entries_required + wm->guard_size);
 634
 635         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 636
 637         /* Don't promote wm_size to unsigned... */
 638         if (wm_size > (long)wm->max_wm)
 639                 wm_size = wm->max_wm;
 640         if (wm_size <= 0)
 641                 wm_size = wm->default_wm;
 642
 643         /*
 644          * Bspec seems to indicate that the value shouldn't be lower than
 645          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 646          * Lets go for 8 which is the burst size since certain platforms
 647          * already use a hardcoded 8 (which is what the spec says should be
 648          * done).
 649          */
 650         if (wm_size <= 8)
 651                 wm_size = 8;
 652
 653         return wm_size;
 654 }
 655
 656 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 657 {
 658         struct intel_crtc *crtc, *enabled = NULL;
 659
 660         for_each_intel_crtc(&dev_priv->drm, crtc) {
 661                 if (intel_crtc_active(crtc)) {
 662                         if (enabled)
 663                                 return NULL;
 664                         enabled = crtc;
 665                 }
 666         }
 667
 668         return enabled;
 669 }
 670
 671 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 672 {
 673         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 674         struct intel_crtc *crtc;
 675         const struct cxsr_latency *latency;
 676         u32 reg;
 677         unsigned long wm;
 678
 679         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 680                                          dev_priv->is_ddr3,
 681                                          dev_priv->fsb_freq,
 682                                          dev_priv->mem_freq);
 683         if (!latency) {
 684                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 685                 intel_set_memory_cxsr(dev_priv, false);
 686                 return;
 687         }
 688
 689         crtc = single_enabled_crtc(dev_priv);
 690         if (crtc) {
 691                 const struct drm_display_mode *adjusted_mode =
 692                         &crtc->config->base.adjusted_mode;
 693                 const struct drm_framebuffer *fb =
 694                         crtc->base.primary->state->fb;
 695                 int cpp = fb->format->cpp[0];
 696                 int clock = adjusted_mode->crtc_clock;
 697
 698                 /* Display SR */
 699                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 700                                         pineview_display_wm.fifo_size,
 701                                         cpp, latency->display_sr);
 702                 reg = I915_READ(DSPFW1);
 703                 reg &= ~DSPFW_SR_MASK;
 704                 reg |= FW_WM(wm, SR);
 705                 I915_WRITE(DSPFW1, reg);
 706                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 707
 708                 /* cursor SR */
 709                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 710                                         pineview_display_wm.fifo_size,
 711                                         cpp, latency->cursor_sr);
 712                 reg = I915_READ(DSPFW3);
 713                 reg &= ~DSPFW_CURSOR_SR_MASK;
 714                 reg |= FW_WM(wm, CURSOR_SR);
 715                 I915_WRITE(DSPFW3, reg);
 716
 717                 /* Display HPLL off SR */
 718                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 719                                         pineview_display_hplloff_wm.fifo_size,
 720                                         cpp, latency->display_hpll_disable);
 721                 reg = I915_READ(DSPFW3);
 722                 reg &= ~DSPFW_HPLL_SR_MASK;
 723                 reg |= FW_WM(wm, HPLL_SR);
 724                 I915_WRITE(DSPFW3, reg);
 725
 726                 /* cursor HPLL off SR */
 727                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 728                                         pineview_display_hplloff_wm.fifo_size,
 729                                         cpp, latency->cursor_hpll_disable);
 730                 reg = I915_READ(DSPFW3);
 731                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 732                 reg |= FW_WM(wm, HPLL_CURSOR);
 733                 I915_WRITE(DSPFW3, reg);
 734                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 735
 736                 intel_set_memory_cxsr(dev_priv, true);
 737         } else {
 738                 intel_set_memory_cxsr(dev_priv, false);
 739         }
 740 }
 741
 742 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
 743                             int plane,
 744                             const struct intel_watermark_params *display,
 745                             int display_latency_ns,
 746                             const struct intel_watermark_params *cursor,
 747                             int cursor_latency_ns,
 748                             int *plane_wm,
 749                             int *cursor_wm)
 750 {
 751         struct intel_crtc *crtc;
 752         const struct drm_display_mode *adjusted_mode;
 753         const struct drm_framebuffer *fb;
 754         int htotal, hdisplay, clock, cpp;
 755         int line_time_us, line_count;
 756         int entries, tlb_miss;
 757
 758         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 759         if (!intel_crtc_active(crtc)) {
 760                 *cursor_wm = cursor->guard_size;
 761                 *plane_wm = display->guard_size;
 762                 return false;
 763         }
 764
 765         adjusted_mode = &crtc->config->base.adjusted_mode;
 766         fb = crtc->base.primary->state->fb;
 767         clock = adjusted_mode->crtc_clock;
 768         htotal = adjusted_mode->crtc_htotal;
 769         hdisplay = crtc->config->pipe_src_w;
 770         cpp = fb->format->cpp[0];
 771
 772         /* Use the small buffer method to calculate plane watermark */
 773         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 774         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 775         if (tlb_miss > 0)
 776                 entries += tlb_miss;
 777         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 778         *plane_wm = entries + display->guard_size;
 779         if (*plane_wm > (int)display->max_wm)
 780                 *plane_wm = display->max_wm;
 781
 782         /* Use the large buffer method to calculate cursor watermark */
 783         line_time_us = max(htotal * 1000 / clock, 1);
 784         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 785         entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
 786         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 787         if (tlb_miss > 0)
 788                 entries += tlb_miss;
 789         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 790         *cursor_wm = entries + cursor->guard_size;
 791         if (*cursor_wm > (int)cursor->max_wm)
 792                 *cursor_wm = (int)cursor->max_wm;
 793
 794         return true;
 795 }
 796
 797 /*
 798  * Check the wm result.
 799  *
 800  * If any calculated watermark values is larger than the maximum value that
 801  * can be programmed into the associated watermark register, that watermark
 802  * must be disabled.
 803  */
 804 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
 805                            int display_wm, int cursor_wm,
 806                            const struct intel_watermark_params *display,
 807                            const struct intel_watermark_params *cursor)
 808 {
 809         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 810                       display_wm, cursor_wm);
 811
 812         if (display_wm > display->max_wm) {
 813                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 814                               display_wm, display->max_wm);
 815                 return false;
 816         }
 817
 818         if (cursor_wm > cursor->max_wm) {
 819                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 820                               cursor_wm, cursor->max_wm);
 821                 return false;
 822         }
 823
 824         if (!(display_wm || cursor_wm)) {
 825                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 826                 return false;
 827         }
 828
 829         return true;
 830 }
 831
 832 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
 833                              int plane,
 834                              int latency_ns,
 835                              const struct intel_watermark_params *display,
 836                              const struct intel_watermark_params *cursor,
 837                              int *display_wm, int *cursor_wm)
 838 {
 839         struct intel_crtc *crtc;
 840         const struct drm_display_mode *adjusted_mode;
 841         const struct drm_framebuffer *fb;
 842         int hdisplay, htotal, cpp, clock;
 843         unsigned long line_time_us;
 844         int line_count, line_size;
 845         int small, large;
 846         int entries;
 847
 848         if (!latency_ns) {
 849                 *display_wm = *cursor_wm = 0;
 850                 return false;
 851         }
 852
 853         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 854         adjusted_mode = &crtc->config->base.adjusted_mode;
 855         fb = crtc->base.primary->state->fb;
 856         clock = adjusted_mode->crtc_clock;
 857         htotal = adjusted_mode->crtc_htotal;
 858         hdisplay = crtc->config->pipe_src_w;
 859         cpp = fb->format->cpp[0];
 860
 861         line_time_us = max(htotal * 1000 / clock, 1);
 862         line_count = (latency_ns / line_time_us + 1000) / 1000;
 863         line_size = hdisplay * cpp;
 864
 865         /* Use the minimum of the small and large buffer method for primary */
 866         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 867         large = line_count * line_size;
 868
 869         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 870         *display_wm = entries + display->guard_size;
 871
 872         /* calculate the self-refresh watermark for display cursor */
 873         entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
 874         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 875         *cursor_wm = entries + cursor->guard_size;
 876
 877         return g4x_check_srwm(dev_priv,
 878                               *display_wm, *cursor_wm,
 879                               display, cursor);
 880 }
 881
 882 #define FW_WM_VLV(value, plane) \
 883         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 884
 885 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 886                                 const struct vlv_wm_values *wm)
 887 {
 888         enum pipe pipe;
 889
 890         for_each_pipe(dev_priv, pipe) {
 891                 I915_WRITE(VLV_DDL(pipe),
 892                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
 893                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
 894                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
 895                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
 896         }
 897
 898         /*
 899          * Zero the (unused) WM1 watermarks, and also clear all the
 900          * high order bits so that there are no out of bounds values
 901          * present in the registers during the reprogramming.
 902          */
 903         I915_WRITE(DSPHOWM, 0);
 904         I915_WRITE(DSPHOWM1, 0);
 905         I915_WRITE(DSPFW4, 0);
 906         I915_WRITE(DSPFW5, 0);
 907         I915_WRITE(DSPFW6, 0);
 908
 909         I915_WRITE(DSPFW1,
 910                    FW_WM(wm->sr.plane, SR) |
 911                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 912                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 913                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 914         I915_WRITE(DSPFW2,
 915                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
 916                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 917                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 918         I915_WRITE(DSPFW3,
 919                    FW_WM(wm->sr.cursor, CURSOR_SR));
 920
 921         if (IS_CHERRYVIEW(dev_priv)) {
 922                 I915_WRITE(DSPFW7_CHV,
 923                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
 924                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
 925                 I915_WRITE(DSPFW8_CHV,
 926                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
 927                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
 928                 I915_WRITE(DSPFW9_CHV,
 929                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
 930                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
 931                 I915_WRITE(DSPHOWM,
 932                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 933                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
 934                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
 935                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
 936                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
 937                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
 938                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
 939                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
 940                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
 941                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
 942         } else {
 943                 I915_WRITE(DSPFW7,
 944                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
 945                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
 946                 I915_WRITE(DSPHOWM,
 947                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 948                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
 949                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
 950                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
 951                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
 952                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
 953                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
 954         }
 955
 956         POSTING_READ(DSPFW1);
 957 }
 958
 959 #undef FW_WM_VLV
 960
 961 /* latency must be in 0.1us units. */
 962 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 963                                    unsigned int pipe_htotal,
 964                                    unsigned int horiz_pixels,
 965                                    unsigned int cpp,
 966                                    unsigned int latency)
 967 {
 968         unsigned int ret;
 969
 970         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 971         ret = (ret + 1) * horiz_pixels * cpp;
 972         ret = DIV_ROUND_UP(ret, 64);
 973
 974         return ret;
 975 }
 976
 977 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
 978 {
 979         /* all latencies in usec */
 980         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 981
 982         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 983
 984         if (IS_CHERRYVIEW(dev_priv)) {
 985                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 986                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 987
 988                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 989         }
 990 }
 991
 992 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 993                                      const struct intel_plane_state *plane_state,
 994                                      int level)
 995 {
 996         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 997         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 998         const struct drm_display_mode *adjusted_mode =
 999                 &crtc_state->base.adjusted_mode;
1000         int clock, htotal, cpp, width, wm;
1001
1002         if (dev_priv->wm.pri_latency[level] == 0)
1003                 return USHRT_MAX;
1004
1005         if (!plane_state->base.visible)
1006                 return 0;
1007
1008         cpp = plane_state->base.fb->format->cpp[0];
1009         clock = adjusted_mode->crtc_clock;
1010         htotal = adjusted_mode->crtc_htotal;
1011         width = crtc_state->pipe_src_w;
1012         if (WARN_ON(htotal == 0))
1013                 htotal = 1;
1014
1015         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1016                 /*
1017                  * FIXME the formula gives values that are
1018                  * too big for the cursor FIFO, and hence we
1019                  * would never be able to use cursors. For
1020                  * now just hardcode the watermark.
1021                  */
1022                 wm = 63;
1023         } else {
1024                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1025                                     dev_priv->wm.pri_latency[level] * 10);
1026         }
1027
1028         return min_t(int, wm, USHRT_MAX);
1029 }
1030
1031 static void vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1032 {
1033         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1034         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1035         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1036         struct drm_device *dev = crtc->base.dev;
1037         struct intel_plane *plane;
1038         unsigned int total_rate = 0;
1039         const int fifo_size = 512 - 1;
1040         int fifo_extra, fifo_left = fifo_size;
1041
1042         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1043                 struct intel_plane_state *state =
1044                         to_intel_plane_state(plane->base.state);
1045
1046                 if (plane->id == PLANE_CURSOR)
1047                         continue;
1048
1049                 if (state->base.visible) {
1050                         wm_state->num_active_planes++;
1051                         total_rate += state->base.fb->format->cpp[0];
1052                 }
1053         }
1054
1055         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1056                 struct intel_plane_state *state =
1057                         to_intel_plane_state(plane->base.state);
1058                 unsigned int rate;
1059
1060                 if (plane->id == PLANE_CURSOR) {
1061                         fifo_state->plane[plane->id] = 63;
1062                         continue;
1063                 }
1064
1065                 if (!state->base.visible) {
1066                         fifo_state->plane[plane->id] = 0;
1067                         continue;
1068                 }
1069
1070                 rate = state->base.fb->format->cpp[0];
1071                 fifo_state->plane[plane->id] = fifo_size * rate / total_rate;
1072                 fifo_left -= fifo_state->plane[plane->id];
1073         }
1074
1075         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1076
1077         /* spread the remainder evenly */
1078         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1079                 int plane_extra;
1080
1081                 if (fifo_left == 0)
1082                         break;
1083
1084                 if (plane->id == PLANE_CURSOR)
1085                         continue;
1086
1087                 /* give it all to the first plane if none are active */
1088                 if (fifo_state->plane[plane->id] == 0 &&
1089                     wm_state->num_active_planes)
1090                         continue;
1091
1092                 plane_extra = min(fifo_extra, fifo_left);
1093                 fifo_state->plane[plane->id] += plane_extra;
1094                 fifo_left -= plane_extra;
1095         }
1096
1097         WARN_ON(fifo_left != 0);
1098 }
1099
1100 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1101 {
1102         if (wm > fifo_size)
1103                 return USHRT_MAX;
1104         else
1105                 return fifo_size - wm;
1106 }
1107
1108 static void vlv_invert_wms(struct intel_crtc_state *crtc_state)
1109 {
1110         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1111         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1112         const struct vlv_fifo_state *fifo_state =
1113                 &crtc_state->wm.vlv.fifo_state;
1114         int level;
1115
1116         for (level = 0; level < wm_state->num_levels; level++) {
1117                 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1118                 const int sr_fifo_size =
1119                         INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1120                 enum plane_id plane_id;
1121
1122                 wm_state->sr[level].plane =
1123                         vlv_invert_wm_value(wm_state->sr[level].plane,
1124                                             sr_fifo_size);
1125                 wm_state->sr[level].cursor =
1126                         vlv_invert_wm_value(wm_state->sr[level].cursor,
1127                                             63);
1128
1129                 for_each_plane_id_on_crtc(crtc, plane_id) {
1130                         wm_state->wm[level].plane[plane_id] =
1131                                 vlv_invert_wm_value(wm_state->wm[level].plane[plane_id],
1132                                                     fifo_state->plane[plane_id]);
1133                 }
1134         }
1135 }
1136
1137 static void vlv_compute_wm(struct intel_crtc_state *crtc_state)
1138 {
1139         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1140         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1141         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1142         const struct vlv_fifo_state *fifo_state =
1143                 &crtc_state->wm.vlv.fifo_state;
1144         struct intel_plane *plane;
1145         int level;
1146
1147         memset(wm_state, 0, sizeof(*wm_state));
1148
1149         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1150         wm_state->num_levels = dev_priv->wm.max_level + 1;
1151
1152         wm_state->num_active_planes = 0;
1153
1154         vlv_compute_fifo(crtc_state);
1155
1156         if (wm_state->num_active_planes != 1)
1157                 wm_state->cxsr = false;
1158
1159         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1160                 struct intel_plane_state *state =
1161                         to_intel_plane_state(plane->base.state);
1162                 int level;
1163
1164                 if (!state->base.visible)
1165                         continue;
1166
1167                 /* normal watermarks */
1168                 for (level = 0; level < wm_state->num_levels; level++) {
1169                         int wm = vlv_compute_wm_level(crtc_state, state, level);
1170                         int max_wm = fifo_state->plane[plane->id];
1171
1172                         /* hack */
1173                         if (WARN_ON(level == 0 && wm > max_wm))
1174                                 wm = max_wm;
1175
1176                         if (wm > max_wm)
1177                                 break;
1178
1179                         wm_state->wm[level].plane[plane->id] = wm;
1180                 }
1181
1182                 wm_state->num_levels = level;
1183
1184                 if (!wm_state->cxsr)
1185                         continue;
1186
1187                 /* maxfifo watermarks */
1188                 if (plane->id == PLANE_CURSOR) {
1189                         for (level = 0; level < wm_state->num_levels; level++)
1190                                 wm_state->sr[level].cursor =
1191                                         wm_state->wm[level].plane[PLANE_CURSOR];
1192                 } else {
1193                         for (level = 0; level < wm_state->num_levels; level++)
1194                                 wm_state->sr[level].plane =
1195                                         max(wm_state->sr[level].plane,
1196                                             wm_state->wm[level].plane[plane->id]);
1197                 }
1198         }
1199
1200         /* clear any (partially) filled invalid levels */
1201         for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
1202                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1203                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1204         }
1205
1206         vlv_invert_wms(crtc_state);
1207 }
1208
1209 #define VLV_FIFO(plane, value) \
1210         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1211
1212 static void vlv_pipe_set_fifo_size(const struct intel_crtc_state *crtc_state)
1213 {
1214         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1215         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1216         const struct vlv_fifo_state *fifo_state =
1217                 &crtc_state->wm.vlv.fifo_state;
1218         int sprite0_start, sprite1_start, fifo_size;
1219
1220         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1221         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1222         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1223
1224         WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1225         WARN_ON(fifo_size != 511);
1226
1227         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1228                       pipe_name(crtc->pipe), sprite0_start,
1229                       sprite1_start, fifo_size);
1230
1231         spin_lock(&dev_priv->wm.dsparb_lock);
1232
1233         switch (crtc->pipe) {
1234                 uint32_t dsparb, dsparb2, dsparb3;
1235         case PIPE_A:
1236                 dsparb = I915_READ(DSPARB);
1237                 dsparb2 = I915_READ(DSPARB2);
1238
1239                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1240                             VLV_FIFO(SPRITEB, 0xff));
1241                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1242                            VLV_FIFO(SPRITEB, sprite1_start));
1243
1244                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1245                              VLV_FIFO(SPRITEB_HI, 0x1));
1246                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1247                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1248
1249                 I915_WRITE(DSPARB, dsparb);
1250                 I915_WRITE(DSPARB2, dsparb2);
1251                 break;
1252         case PIPE_B:
1253                 dsparb = I915_READ(DSPARB);
1254                 dsparb2 = I915_READ(DSPARB2);
1255
1256                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1257                             VLV_FIFO(SPRITED, 0xff));
1258                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1259                            VLV_FIFO(SPRITED, sprite1_start));
1260
1261                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1262                              VLV_FIFO(SPRITED_HI, 0xff));
1263                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1264                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1265
1266                 I915_WRITE(DSPARB, dsparb);
1267                 I915_WRITE(DSPARB2, dsparb2);
1268                 break;
1269         case PIPE_C:
1270                 dsparb3 = I915_READ(DSPARB3);
1271                 dsparb2 = I915_READ(DSPARB2);
1272
1273                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1274                              VLV_FIFO(SPRITEF, 0xff));
1275                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1276                             VLV_FIFO(SPRITEF, sprite1_start));
1277
1278                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1279                              VLV_FIFO(SPRITEF_HI, 0xff));
1280                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1281                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1282
1283                 I915_WRITE(DSPARB3, dsparb3);
1284                 I915_WRITE(DSPARB2, dsparb2);
1285                 break;
1286         default:
1287                 break;
1288         }
1289
1290         POSTING_READ(DSPARB);
1291
1292         spin_unlock(&dev_priv->wm.dsparb_lock);
1293 }
1294
1295 #undef VLV_FIFO
1296
1297 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
1298                          struct vlv_wm_values *wm)
1299 {
1300         struct intel_crtc *crtc;
1301         int num_active_crtcs = 0;
1302
1303         wm->level = dev_priv->wm.max_level;
1304         wm->cxsr = true;
1305
1306         for_each_intel_crtc(&dev_priv->drm, crtc) {
1307                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
1308
1309                 if (!crtc->active)
1310                         continue;
1311
1312                 if (!wm_state->cxsr)
1313                         wm->cxsr = false;
1314
1315                 num_active_crtcs++;
1316                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1317         }
1318
1319         if (num_active_crtcs != 1)
1320                 wm->cxsr = false;
1321
1322         if (num_active_crtcs > 1)
1323                 wm->level = VLV_WM_LEVEL_PM2;
1324
1325         for_each_intel_crtc(&dev_priv->drm, crtc) {
1326                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
1327                 enum pipe pipe = crtc->pipe;
1328
1329                 if (!crtc->active)
1330                         continue;
1331
1332                 wm->pipe[pipe] = wm_state->wm[wm->level];
1333                 if (wm->cxsr)
1334                         wm->sr = wm_state->sr[wm->level];
1335
1336                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
1337                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
1338                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
1339                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
1340         }
1341 }
1342
1343 static bool is_disabling(int old, int new, int threshold)
1344 {
1345         return old >= threshold && new < threshold;
1346 }
1347
1348 static bool is_enabling(int old, int new, int threshold)
1349 {
1350         return old < threshold && new >= threshold;
1351 }
1352
1353 static void vlv_update_wm(struct intel_crtc *crtc)
1354 {
1355         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1356         struct intel_crtc_state *crtc_state =
1357                 to_intel_crtc_state(crtc->base.state);
1358         enum pipe pipe = crtc->pipe;
1359         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
1360         struct vlv_wm_values new_wm = {};
1361
1362         vlv_compute_wm(crtc_state);
1363         crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
1364         vlv_merge_wm(dev_priv, &new_wm);
1365
1366         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) {
1367                 /* FIXME should be part of crtc atomic commit */
1368                 vlv_pipe_set_fifo_size(crtc_state);
1369                 return;
1370         }
1371
1372         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1373                 chv_set_memory_dvfs(dev_priv, false);
1374
1375         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1376                 chv_set_memory_pm5(dev_priv, false);
1377
1378         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1379                 _intel_set_memory_cxsr(dev_priv, false);
1380
1381         /* FIXME should be part of crtc atomic commit */
1382         vlv_pipe_set_fifo_size(crtc_state);
1383
1384         vlv_write_wm_values(dev_priv, &new_wm);
1385
1386         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1387                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1388                       pipe_name(pipe), new_wm.pipe[pipe].plane[PLANE_PRIMARY], new_wm.pipe[pipe].plane[PLANE_CURSOR],
1389                       new_wm.pipe[pipe].plane[PLANE_SPRITE0], new_wm.pipe[pipe].plane[PLANE_SPRITE1],
1390                       new_wm.sr.plane, new_wm.sr.cursor, new_wm.level, new_wm.cxsr);
1391
1392         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1393                 _intel_set_memory_cxsr(dev_priv, true);
1394
1395         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1396                 chv_set_memory_pm5(dev_priv, true);
1397
1398         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1399                 chv_set_memory_dvfs(dev_priv, true);
1400
1401         *old_wm = new_wm;
1402 }
1403
1404 #define single_plane_enabled(mask) is_power_of_2(mask)
1405
1406 static void g4x_update_wm(struct intel_crtc *crtc)
1407 {
1408         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1409         static const int sr_latency_ns = 12000;
1410         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1411         int plane_sr, cursor_sr;
1412         unsigned int enabled = 0;
1413         bool cxsr_enabled;
1414
1415         if (g4x_compute_wm0(dev_priv, PIPE_A,
1416                             &g4x_wm_info, pessimal_latency_ns,
1417                             &g4x_cursor_wm_info, pessimal_latency_ns,
1418                             &planea_wm, &cursora_wm))
1419                 enabled |= 1 << PIPE_A;
1420
1421         if (g4x_compute_wm0(dev_priv, PIPE_B,
1422                             &g4x_wm_info, pessimal_latency_ns,
1423                             &g4x_cursor_wm_info, pessimal_latency_ns,
1424                             &planeb_wm, &cursorb_wm))
1425                 enabled |= 1 << PIPE_B;
1426
1427         if (single_plane_enabled(enabled) &&
1428             g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1429                              sr_latency_ns,
1430                              &g4x_wm_info,
1431                              &g4x_cursor_wm_info,
1432                              &plane_sr, &cursor_sr)) {
1433                 cxsr_enabled = true;
1434         } else {
1435                 cxsr_enabled = false;
1436                 intel_set_memory_cxsr(dev_priv, false);
1437                 plane_sr = cursor_sr = 0;
1438         }
1439
1440         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1441                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1442                       planea_wm, cursora_wm,
1443                       planeb_wm, cursorb_wm,
1444                       plane_sr, cursor_sr);
1445
1446         I915_WRITE(DSPFW1,
1447                    FW_WM(plane_sr, SR) |
1448                    FW_WM(cursorb_wm, CURSORB) |
1449                    FW_WM(planeb_wm, PLANEB) |
1450                    FW_WM(planea_wm, PLANEA));
1451         I915_WRITE(DSPFW2,
1452                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1453                    FW_WM(cursora_wm, CURSORA));
1454         /* HPLL off in SR has some issues on G4x... disable it */
1455         I915_WRITE(DSPFW3,
1456                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1457                    FW_WM(cursor_sr, CURSOR_SR));
1458
1459         if (cxsr_enabled)
1460                 intel_set_memory_cxsr(dev_priv, true);
1461 }
1462
1463 static void i965_update_wm(struct intel_crtc *unused_crtc)
1464 {
1465         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1466         struct intel_crtc *crtc;
1467         int srwm = 1;
1468         int cursor_sr = 16;
1469         bool cxsr_enabled;
1470
1471         /* Calc sr entries for one plane configs */
1472         crtc = single_enabled_crtc(dev_priv);
1473         if (crtc) {
1474                 /* self-refresh has much higher latency */
1475                 static const int sr_latency_ns = 12000;
1476                 const struct drm_display_mode *adjusted_mode =
1477                         &crtc->config->base.adjusted_mode;
1478                 const struct drm_framebuffer *fb =
1479                         crtc->base.primary->state->fb;
1480                 int clock = adjusted_mode->crtc_clock;
1481                 int htotal = adjusted_mode->crtc_htotal;
1482                 int hdisplay = crtc->config->pipe_src_w;
1483                 int cpp = fb->format->cpp[0];
1484                 unsigned long line_time_us;
1485                 int entries;
1486
1487                 line_time_us = max(htotal * 1000 / clock, 1);
1488
1489                 /* Use ns/us then divide to preserve precision */
1490                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1491                         cpp * hdisplay;
1492                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1493                 srwm = I965_FIFO_SIZE - entries;
1494                 if (srwm < 0)
1495                         srwm = 1;
1496                 srwm &= 0x1ff;
1497                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1498                               entries, srwm);
1499
1500                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1501                         cpp * crtc->base.cursor->state->crtc_w;
1502                 entries = DIV_ROUND_UP(entries,
1503                                           i965_cursor_wm_info.cacheline_size);
1504                 cursor_sr = i965_cursor_wm_info.fifo_size -
1505                         (entries + i965_cursor_wm_info.guard_size);
1506
1507                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1508                         cursor_sr = i965_cursor_wm_info.max_wm;
1509
1510                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1511                               "cursor %d\n", srwm, cursor_sr);
1512
1513                 cxsr_enabled = true;
1514         } else {
1515                 cxsr_enabled = false;
1516                 /* Turn off self refresh if both pipes are enabled */
1517                 intel_set_memory_cxsr(dev_priv, false);
1518         }
1519
1520         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1521                       srwm);
1522
1523         /* 965 has limitations... */
1524         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1525                    FW_WM(8, CURSORB) |
1526                    FW_WM(8, PLANEB) |
1527                    FW_WM(8, PLANEA));
1528         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1529                    FW_WM(8, PLANEC_OLD));
1530         /* update cursor SR watermark */
1531         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1532
1533         if (cxsr_enabled)
1534                 intel_set_memory_cxsr(dev_priv, true);
1535 }
1536
1537 #undef FW_WM
1538
1539 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1540 {
1541         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1542         const struct intel_watermark_params *wm_info;
1543         uint32_t fwater_lo;
1544         uint32_t fwater_hi;
1545         int cwm, srwm = 1;
1546         int fifo_size;
1547         int planea_wm, planeb_wm;
1548         struct intel_crtc *crtc, *enabled = NULL;
1549
1550         if (IS_I945GM(dev_priv))
1551                 wm_info = &i945_wm_info;
1552         else if (!IS_GEN2(dev_priv))
1553                 wm_info = &i915_wm_info;
1554         else
1555                 wm_info = &i830_a_wm_info;
1556
1557         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1558         crtc = intel_get_crtc_for_plane(dev_priv, 0);
1559         if (intel_crtc_active(crtc)) {
1560                 const struct drm_display_mode *adjusted_mode =
1561                         &crtc->config->base.adjusted_mode;
1562                 const struct drm_framebuffer *fb =
1563                         crtc->base.primary->state->fb;
1564                 int cpp;
1565
1566                 if (IS_GEN2(dev_priv))
1567                         cpp = 4;
1568                 else
1569                         cpp = fb->format->cpp[0];
1570
1571                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1572                                                wm_info, fifo_size, cpp,
1573                                                pessimal_latency_ns);
1574                 enabled = crtc;
1575         } else {
1576                 planea_wm = fifo_size - wm_info->guard_size;
1577                 if (planea_wm > (long)wm_info->max_wm)
1578                         planea_wm = wm_info->max_wm;
1579         }
1580
1581         if (IS_GEN2(dev_priv))
1582                 wm_info = &i830_bc_wm_info;
1583
1584         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1585         crtc = intel_get_crtc_for_plane(dev_priv, 1);
1586         if (intel_crtc_active(crtc)) {
1587                 const struct drm_display_mode *adjusted_mode =
1588                         &crtc->config->base.adjusted_mode;
1589                 const struct drm_framebuffer *fb =
1590                         crtc->base.primary->state->fb;
1591                 int cpp;
1592
1593                 if (IS_GEN2(dev_priv))
1594                         cpp = 4;
1595                 else
1596                         cpp = fb->format->cpp[0];
1597
1598                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1599                                                wm_info, fifo_size, cpp,
1600                                                pessimal_latency_ns);
1601                 if (enabled == NULL)
1602                         enabled = crtc;
1603                 else
1604                         enabled = NULL;
1605         } else {
1606                 planeb_wm = fifo_size - wm_info->guard_size;
1607                 if (planeb_wm > (long)wm_info->max_wm)
1608                         planeb_wm = wm_info->max_wm;
1609         }
1610
1611         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1612
1613         if (IS_I915GM(dev_priv) && enabled) {
1614                 struct drm_i915_gem_object *obj;
1615
1616                 obj = intel_fb_obj(enabled->base.primary->state->fb);
1617
1618                 /* self-refresh seems busted with untiled */
1619                 if (!i915_gem_object_is_tiled(obj))
1620                         enabled = NULL;
1621         }
1622
1623         /*
1624          * Overlay gets an aggressive default since video jitter is bad.
1625          */
1626         cwm = 2;
1627
1628         /* Play safe and disable self-refresh before adjusting watermarks. */
1629         intel_set_memory_cxsr(dev_priv, false);
1630
1631         /* Calc sr entries for one plane configs */
1632         if (HAS_FW_BLC(dev_priv) && enabled) {
1633                 /* self-refresh has much higher latency */
1634                 static const int sr_latency_ns = 6000;
1635                 const struct drm_display_mode *adjusted_mode =
1636                         &enabled->config->base.adjusted_mode;
1637                 const struct drm_framebuffer *fb =
1638                         enabled->base.primary->state->fb;
1639                 int clock = adjusted_mode->crtc_clock;
1640                 int htotal = adjusted_mode->crtc_htotal;
1641                 int hdisplay = enabled->config->pipe_src_w;
1642                 int cpp;
1643                 unsigned long line_time_us;
1644                 int entries;
1645
1646                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1647                         cpp = 4;
1648                 else
1649                         cpp = fb->format->cpp[0];
1650
1651                 line_time_us = max(htotal * 1000 / clock, 1);
1652
1653                 /* Use ns/us then divide to preserve precision */
1654                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1655                         cpp * hdisplay;
1656                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1657                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1658                 srwm = wm_info->fifo_size - entries;
1659                 if (srwm < 0)
1660                         srwm = 1;
1661
1662                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1663                         I915_WRITE(FW_BLC_SELF,
1664                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1665                 else
1666                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1667         }
1668
1669         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1670                       planea_wm, planeb_wm, cwm, srwm);
1671
1672         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1673         fwater_hi = (cwm & 0x1f);
1674
1675         /* Set request length to 8 cachelines per fetch */
1676         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1677         fwater_hi = fwater_hi | (1 << 8);
1678
1679         I915_WRITE(FW_BLC, fwater_lo);
1680         I915_WRITE(FW_BLC2, fwater_hi);
1681
1682         if (enabled)
1683                 intel_set_memory_cxsr(dev_priv, true);
1684 }
1685
1686 static void i845_update_wm(struct intel_crtc *unused_crtc)
1687 {
1688         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1689         struct intel_crtc *crtc;
1690         const struct drm_display_mode *adjusted_mode;
1691         uint32_t fwater_lo;
1692         int planea_wm;
1693
1694         crtc = single_enabled_crtc(dev_priv);
1695         if (crtc == NULL)
1696                 return;
1697
1698         adjusted_mode = &crtc->config->base.adjusted_mode;
1699         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1700                                        &i845_wm_info,
1701                                        dev_priv->display.get_fifo_size(dev_priv, 0),
1702                                        4, pessimal_latency_ns);
1703         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1704         fwater_lo |= (3<<8) | planea_wm;
1705
1706         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1707
1708         I915_WRITE(FW_BLC, fwater_lo);
1709 }
1710
1711 /* latency must be in 0.1us units. */
1712 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1713 {
1714         uint64_t ret;
1715
1716         if (WARN(latency == 0, "Latency value missing\n"))
1717                 return UINT_MAX;
1718
1719         ret = (uint64_t) pixel_rate * cpp * latency;
1720         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1721
1722         return ret;
1723 }
1724
1725 /* latency must be in 0.1us units. */
1726 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1727                                uint32_t horiz_pixels, uint8_t cpp,
1728                                uint32_t latency)
1729 {
1730         uint32_t ret;
1731
1732         if (WARN(latency == 0, "Latency value missing\n"))
1733                 return UINT_MAX;
1734         if (WARN_ON(!pipe_htotal))
1735                 return UINT_MAX;
1736
1737         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1738         ret = (ret + 1) * horiz_pixels * cpp;
1739         ret = DIV_ROUND_UP(ret, 64) + 2;
1740         return ret;
1741 }
1742
1743 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1744                            uint8_t cpp)
1745 {
1746         /*
1747          * Neither of these should be possible since this function shouldn't be
1748          * called if the CRTC is off or the plane is invisible.  But let's be
1749          * extra paranoid to avoid a potential divide-by-zero if we screw up
1750          * elsewhere in the driver.
1751          */
1752         if (WARN_ON(!cpp))
1753                 return 0;
1754         if (WARN_ON(!horiz_pixels))
1755                 return 0;
1756
1757         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1758 }
1759
1760 struct ilk_wm_maximums {
1761         uint16_t pri;
1762         uint16_t spr;
1763         uint16_t cur;
1764         uint16_t fbc;
1765 };
1766
1767 /*
1768  * For both WM_PIPE and WM_LP.
1769  * mem_value must be in 0.1us units.
1770  */
1771 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1772                                    const struct intel_plane_state *pstate,
1773                                    uint32_t mem_value,
1774                                    bool is_lp)
1775 {
1776         uint32_t method1, method2;
1777         int cpp;
1778
1779         if (!cstate->base.active || !pstate->base.visible)
1780                 return 0;
1781
1782         cpp = pstate->base.fb->format->cpp[0];
1783
1784         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
1785
1786         if (!is_lp)
1787                 return method1;
1788
1789         method2 = ilk_wm_method2(cstate->pixel_rate,
1790                                  cstate->base.adjusted_mode.crtc_htotal,
1791                                  drm_rect_width(&pstate->base.dst),
1792                                  cpp, mem_value);
1793
1794         return min(method1, method2);
1795 }
1796
1797 /*
1798  * For both WM_PIPE and WM_LP.
1799  * mem_value must be in 0.1us units.
1800  */
1801 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1802                                    const struct intel_plane_state *pstate,
1803                                    uint32_t mem_value)
1804 {
1805         uint32_t method1, method2;
1806         int cpp;
1807
1808         if (!cstate->base.active || !pstate->base.visible)
1809                 return 0;
1810
1811         cpp = pstate->base.fb->format->cpp[0];
1812
1813         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
1814         method2 = ilk_wm_method2(cstate->pixel_rate,
1815                                  cstate->base.adjusted_mode.crtc_htotal,
1816                                  drm_rect_width(&pstate->base.dst),
1817                                  cpp, mem_value);
1818         return min(method1, method2);
1819 }
1820
1821 /*
1822  * For both WM_PIPE and WM_LP.
1823  * mem_value must be in 0.1us units.
1824  */
1825 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1826                                    const struct intel_plane_state *pstate,
1827                                    uint32_t mem_value)
1828 {
1829         int cpp;
1830
1831         /*
1832          * Treat cursor with fb as always visible since cursor updates
1833          * can happen faster than the vrefresh rate, and the current
1834          * watermark code doesn't handle that correctly. Cursor updates
1835          * which set/clear the fb or change the cursor size are going
1836          * to get throttled by intel_legacy_cursor_update() to work
1837          * around this problem with the watermark code.
1838          */
1839         if (!cstate->base.active || !pstate->base.fb)
1840                 return 0;
1841
1842         cpp = pstate->base.fb->format->cpp[0];
1843
1844         return ilk_wm_method2(cstate->pixel_rate,
1845                               cstate->base.adjusted_mode.crtc_htotal,
1846                               pstate->base.crtc_w, cpp, mem_value);
1847 }
1848
1849 /* Only for WM_LP. */
1850 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1851                                    const struct intel_plane_state *pstate,
1852                                    uint32_t pri_val)
1853 {
1854         int cpp;
1855
1856         if (!cstate->base.active || !pstate->base.visible)
1857                 return 0;
1858
1859         cpp = pstate->base.fb->format->cpp[0];
1860
1861         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1862 }
1863
1864 static unsigned int
1865 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
1866 {
1867         if (INTEL_GEN(dev_priv) >= 8)
1868                 return 3072;
1869         else if (INTEL_GEN(dev_priv) >= 7)
1870                 return 768;
1871         else
1872                 return 512;
1873 }
1874
1875 static unsigned int
1876 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1877                      int level, bool is_sprite)
1878 {
1879         if (INTEL_GEN(dev_priv) >= 8)
1880                 /* BDW primary/sprite plane watermarks */
1881                 return level == 0 ? 255 : 2047;
1882         else if (INTEL_GEN(dev_priv) >= 7)
1883                 /* IVB/HSW primary/sprite plane watermarks */
1884                 return level == 0 ? 127 : 1023;
1885         else if (!is_sprite)
1886                 /* ILK/SNB primary plane watermarks */
1887                 return level == 0 ? 127 : 511;
1888         else
1889                 /* ILK/SNB sprite plane watermarks */
1890                 return level == 0 ? 63 : 255;
1891 }
1892
1893 static unsigned int
1894 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
1895 {
1896         if (INTEL_GEN(dev_priv) >= 7)
1897                 return level == 0 ? 63 : 255;
1898         else
1899                 return level == 0 ? 31 : 63;
1900 }
1901
1902 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
1903 {
1904         if (INTEL_GEN(dev_priv) >= 8)
1905                 return 31;
1906         else
1907                 return 15;
1908 }
1909
1910 /* Calculate the maximum primary/sprite plane watermark */
1911 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1912                                      int level,
1913                                      const struct intel_wm_config *config,
1914                                      enum intel_ddb_partitioning ddb_partitioning,
1915                                      bool is_sprite)
1916 {
1917         struct drm_i915_private *dev_priv = to_i915(dev);
1918         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
1919
1920         /* if sprites aren't enabled, sprites get nothing */
1921         if (is_sprite && !config->sprites_enabled)
1922                 return 0;
1923
1924         /* HSW allows LP1+ watermarks even with multiple pipes */
1925         if (level == 0 || config->num_pipes_active > 1) {
1926                 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
1927
1928                 /*
1929                  * For some reason the non self refresh
1930                  * FIFO size is only half of the self
1931                  * refresh FIFO size on ILK/SNB.
1932                  */
1933                 if (INTEL_GEN(dev_priv) <= 6)
1934                         fifo_size /= 2;
1935         }
1936
1937         if (config->sprites_enabled) {
1938                 /* level 0 is always calculated with 1:1 split */
1939                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1940                         if (is_sprite)
1941                                 fifo_size *= 5;
1942                         fifo_size /= 6;
1943                 } else {
1944                         fifo_size /= 2;
1945                 }
1946         }
1947
1948         /* clamp to max that the registers can hold */
1949         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
1950 }
1951
1952 /* Calculate the maximum cursor plane watermark */
1953 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1954                                       int level,
1955                                       const struct intel_wm_config *config)
1956 {
1957         /* HSW LP1+ watermarks w/ multiple pipes */
1958         if (level > 0 && config->num_pipes_active > 1)
1959                 return 64;
1960
1961         /* otherwise just report max that registers can hold */
1962         return ilk_cursor_wm_reg_max(to_i915(dev), level);
1963 }
1964
1965 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1966                                     int level,
1967                                     const struct intel_wm_config *config,
1968                                     enum intel_ddb_partitioning ddb_partitioning,
1969                                     struct ilk_wm_maximums *max)
1970 {
1971         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1972         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1973         max->cur = ilk_cursor_wm_max(dev, level, config);
1974         max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
1975 }
1976
1977 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
1978                                         int level,
1979                                         struct ilk_wm_maximums *max)
1980 {
1981         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
1982         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
1983         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
1984         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
1985 }
1986
1987 static bool ilk_validate_wm_level(int level,
1988                                   const struct ilk_wm_maximums *max,
1989                                   struct intel_wm_level *result)
1990 {
1991         bool ret;
1992
1993         /* already determined to be invalid? */
1994         if (!result->enable)
1995                 return false;
1996
1997         result->enable = result->pri_val <= max->pri &&
1998                          result->spr_val <= max->spr &&
1999                          result->cur_val <= max->cur;
2000
2001         ret = result->enable;
2002
2003         /*
2004          * HACK until we can pre-compute everything,
2005          * and thus fail gracefully if LP0 watermarks
2006          * are exceeded...
2007          */
2008         if (level == 0 && !result->enable) {
2009                 if (result->pri_val > max->pri)
2010                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2011                                       level, result->pri_val, max->pri);
2012                 if (result->spr_val > max->spr)
2013                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2014                                       level, result->spr_val, max->spr);
2015                 if (result->cur_val > max->cur)
2016                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2017                                       level, result->cur_val, max->cur);
2018
2019                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2020                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2021                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2022                 result->enable = true;
2023         }
2024
2025         return ret;
2026 }
2027
2028 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2029                                  const struct intel_crtc *intel_crtc,
2030                                  int level,
2031                                  struct intel_crtc_state *cstate,
2032                                  struct intel_plane_state *pristate,
2033                                  struct intel_plane_state *sprstate,
2034                                  struct intel_plane_state *curstate,
2035                                  struct intel_wm_level *result)
2036 {
2037         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2038         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2039         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2040
2041         /* WM1+ latency values stored in 0.5us units */
2042         if (level > 0) {
2043                 pri_latency *= 5;
2044                 spr_latency *= 5;
2045                 cur_latency *= 5;
2046         }
2047
2048         if (pristate) {
2049                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2050                                                      pri_latency, level);
2051                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2052         }
2053
2054         if (sprstate)
2055                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2056
2057         if (curstate)
2058                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2059
2060         result->enable = true;
2061 }
2062
2063 static uint32_t
2064 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2065 {
2066         const struct intel_atomic_state *intel_state =
2067                 to_intel_atomic_state(cstate->base.state);
2068         const struct drm_display_mode *adjusted_mode =
2069                 &cstate->base.adjusted_mode;
2070         u32 linetime, ips_linetime;
2071
2072         if (!cstate->base.active)
2073                 return 0;
2074         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2075                 return 0;
2076         if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2077                 return 0;
2078
2079         /* The WM are computed with base on how long it takes to fill a single
2080          * row at the given clock rate, multiplied by 8.
2081          * */
2082         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2083                                      adjusted_mode->crtc_clock);
2084         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2085                                          intel_state->cdclk.logical.cdclk);
2086
2087         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2088                PIPE_WM_LINETIME_TIME(linetime);
2089 }
2090
2091 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2092                                   uint16_t wm[8])
2093 {
2094         if (IS_GEN9(dev_priv)) {
2095                 uint32_t val;
2096                 int ret, i;
2097                 int level, max_level = ilk_wm_max_level(dev_priv);
2098
2099                 /* read the first set of memory latencies[0:3] */
2100                 val = 0; /* data0 to be programmed to 0 for first set */
2101                 mutex_lock(&dev_priv->rps.hw_lock);
2102                 ret = sandybridge_pcode_read(dev_priv,
2103                                              GEN9_PCODE_READ_MEM_LATENCY,
2104                                              &val);
2105                 mutex_unlock(&dev_priv->rps.hw_lock);
2106
2107                 if (ret) {
2108                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2109                         return;
2110                 }
2111
2112                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2113                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2114                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2115                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2116                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2117                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2118                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2119
2120                 /* read the second set of memory latencies[4:7] */
2121                 val = 1; /* data0 to be programmed to 1 for second set */
2122                 mutex_lock(&dev_priv->rps.hw_lock);
2123                 ret = sandybridge_pcode_read(dev_priv,
2124                                              GEN9_PCODE_READ_MEM_LATENCY,
2125                                              &val);
2126                 mutex_unlock(&dev_priv->rps.hw_lock);
2127                 if (ret) {
2128                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2129                         return;
2130                 }
2131
2132                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2133                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2134                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2135                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2136                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2137                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2138                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2139
2140                 /*
2141                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2142                  * need to be disabled. We make sure to sanitize the values out
2143                  * of the punit to satisfy this requirement.
2144                  */
2145                 for (level = 1; level <= max_level; level++) {
2146                         if (wm[level] == 0) {
2147                                 for (i = level + 1; i <= max_level; i++)
2148                                         wm[i] = 0;
2149                                 break;
2150                         }
2151                 }
2152
2153                 /*
2154                  * WaWmMemoryReadLatency:skl,glk
2155                  *
2156                  * punit doesn't take into account the read latency so we need
2157                  * to add 2us to the various latency levels we retrieve from the
2158                  * punit when level 0 response data us 0us.
2159                  */
2160                 if (wm[0] == 0) {
2161                         wm[0] += 2;
2162                         for (level = 1; level <= max_level; level++) {
2163                                 if (wm[level] == 0)
2164                                         break;
2165                                 wm[level] += 2;
2166                         }
2167                 }
2168
2169         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2170                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2171
2172                 wm[0] = (sskpd >> 56) & 0xFF;
2173                 if (wm[0] == 0)
2174                         wm[0] = sskpd & 0xF;
2175                 wm[1] = (sskpd >> 4) & 0xFF;
2176                 wm[2] = (sskpd >> 12) & 0xFF;
2177                 wm[3] = (sskpd >> 20) & 0x1FF;
2178                 wm[4] = (sskpd >> 32) & 0x1FF;
2179         } else if (INTEL_GEN(dev_priv) >= 6) {
2180                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2181
2182                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2183                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2184                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2185                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2186         } else if (INTEL_GEN(dev_priv) >= 5) {
2187                 uint32_t mltr = I915_READ(MLTR_ILK);
2188
2189                 /* ILK primary LP0 latency is 700 ns */
2190                 wm[0] = 7;
2191                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2192                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2193         }
2194 }
2195
2196 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2197                                        uint16_t wm[5])
2198 {
2199         /* ILK sprite LP0 latency is 1300 ns */
2200         if (IS_GEN5(dev_priv))
2201                 wm[0] = 13;
2202 }
2203
2204 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2205                                        uint16_t wm[5])
2206 {
2207         /* ILK cursor LP0 latency is 1300 ns */
2208         if (IS_GEN5(dev_priv))
2209                 wm[0] = 13;
2210
2211         /* WaDoubleCursorLP3Latency:ivb */
2212         if (IS_IVYBRIDGE(dev_priv))
2213                 wm[3] *= 2;
2214 }
2215
2216 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2217 {
2218         /* how many WM levels are we expecting */
2219         if (INTEL_GEN(dev_priv) >= 9)
2220                 return 7;
2221         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2222                 return 4;
2223         else if (INTEL_GEN(dev_priv) >= 6)
2224                 return 3;
2225         else
2226                 return 2;
2227 }
2228
2229 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2230                                    const char *name,
2231                                    const uint16_t wm[8])
2232 {
2233         int level, max_level = ilk_wm_max_level(dev_priv);
2234
2235         for (level = 0; level <= max_level; level++) {
2236                 unsigned int latency = wm[level];
2237
2238                 if (latency == 0) {
2239                         DRM_ERROR("%s WM%d latency not provided\n",
2240                                   name, level);
2241                         continue;
2242                 }
2243
2244                 /*
2245                  * - latencies are in us on gen9.
2246                  * - before then, WM1+ latency values are in 0.5us units
2247                  */
2248                 if (IS_GEN9(dev_priv))
2249                         latency *= 10;
2250                 else if (level > 0)
2251                         latency *= 5;
2252
2253                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2254                               name, level, wm[level],
2255                               latency / 10, latency % 10);
2256         }
2257 }
2258
2259 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2260                                     uint16_t wm[5], uint16_t min)
2261 {
2262         int level, max_level = ilk_wm_max_level(dev_priv);
2263
2264         if (wm[0] >= min)
2265                 return false;
2266
2267         wm[0] = max(wm[0], min);
2268         for (level = 1; level <= max_level; level++)
2269                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2270
2271         return true;
2272 }
2273
2274 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2275 {
2276         bool changed;
2277
2278         /*
2279          * The BIOS provided WM memory latency values are often
2280          * inadequate for high resolution displays. Adjust them.
2281          */
2282         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2283                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2284                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2285
2286         if (!changed)
2287                 return;
2288
2289         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2290         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2291         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2292         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2293 }
2294
2295 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2296 {
2297         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2298
2299         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2300                sizeof(dev_priv->wm.pri_latency));
2301         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2302                sizeof(dev_priv->wm.pri_latency));
2303
2304         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2305         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2306
2307         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2308         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2309         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2310
2311         if (IS_GEN6(dev_priv))
2312                 snb_wm_latency_quirk(dev_priv);
2313 }
2314
2315 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2316 {
2317         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2318         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2319 }
2320
2321 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2322                                  struct intel_pipe_wm *pipe_wm)
2323 {
2324         /* LP0 watermark maximums depend on this pipe alone */
2325         const struct intel_wm_config config = {
2326                 .num_pipes_active = 1,
2327                 .sprites_enabled = pipe_wm->sprites_enabled,
2328                 .sprites_scaled = pipe_wm->sprites_scaled,
2329         };
2330         struct ilk_wm_maximums max;
2331
2332         /* LP0 watermarks always use 1/2 DDB partitioning */
2333         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2334
2335         /* At least LP0 must be valid */
2336         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2337                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2338                 return false;
2339         }
2340
2341         return true;
2342 }
2343
2344 /* Compute new watermarks for the pipe */
2345 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2346 {
2347         struct drm_atomic_state *state = cstate->base.state;
2348         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2349         struct intel_pipe_wm *pipe_wm;
2350         struct drm_device *dev = state->dev;
2351         const struct drm_i915_private *dev_priv = to_i915(dev);
2352         struct intel_plane *intel_plane;
2353         struct intel_plane_state *pristate = NULL;
2354         struct intel_plane_state *sprstate = NULL;
2355         struct intel_plane_state *curstate = NULL;
2356         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2357         struct ilk_wm_maximums max;
2358
2359         pipe_wm = &cstate->wm.ilk.optimal;
2360
2361         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2362                 struct intel_plane_state *ps;
2363
2364                 ps = intel_atomic_get_existing_plane_state(state,
2365                                                            intel_plane);
2366                 if (!ps)
2367                         continue;
2368
2369                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2370                         pristate = ps;
2371                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2372                         sprstate = ps;
2373                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2374                         curstate = ps;
2375         }
2376
2377         pipe_wm->pipe_enabled = cstate->base.active;
2378         if (sprstate) {
2379                 pipe_wm->sprites_enabled = sprstate->base.visible;
2380                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2381                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2382                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2383         }
2384
2385         usable_level = max_level;
2386
2387         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2388         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
2389                 usable_level = 1;
2390
2391         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2392         if (pipe_wm->sprites_scaled)
2393                 usable_level = 0;
2394
2395         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2396                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2397
2398         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2399         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2400
2401         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2402                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2403
2404         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2405                 return -EINVAL;
2406
2407         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
2408
2409         for (level = 1; level <= max_level; level++) {
2410                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2411
2412                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2413                                      pristate, sprstate, curstate, wm);
2414
2415                 /*
2416                  * Disable any watermark level that exceeds the
2417                  * register maximums since such watermarks are
2418                  * always invalid.
2419                  */
2420                 if (level > usable_level)
2421                         continue;
2422
2423                 if (ilk_validate_wm_level(level, &max, wm))
2424                         pipe_wm->wm[level] = *wm;
2425                 else
2426                         usable_level = level;
2427         }
2428
2429         return 0;
2430 }
2431
2432 /*
2433  * Build a set of 'intermediate' watermark values that satisfy both the old
2434  * state and the new state.  These can be programmed to the hardware
2435  * immediately.
2436  */
2437 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2438                                        struct intel_crtc *intel_crtc,
2439                                        struct intel_crtc_state *newstate)
2440 {
2441         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2442         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2443         int level, max_level = ilk_wm_max_level(to_i915(dev));
2444
2445         /*
2446          * Start with the final, target watermarks, then combine with the
2447          * currently active watermarks to get values that are safe both before
2448          * and after the vblank.
2449          */
2450         *a = newstate->wm.ilk.optimal;
2451         a->pipe_enabled |= b->pipe_enabled;
2452         a->sprites_enabled |= b->sprites_enabled;
2453         a->sprites_scaled |= b->sprites_scaled;
2454
2455         for (level = 0; level <= max_level; level++) {
2456                 struct intel_wm_level *a_wm = &a->wm[level];
2457                 const struct intel_wm_level *b_wm = &b->wm[level];
2458
2459                 a_wm->enable &= b_wm->enable;
2460                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2461                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2462                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2463                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2464         }
2465
2466         /*
2467          * We need to make sure that these merged watermark values are
2468          * actually a valid configuration themselves.  If they're not,
2469          * there's no safe way to transition from the old state to
2470          * the new state, so we need to fail the atomic transaction.
2471          */
2472         if (!ilk_validate_pipe_wm(dev, a))
2473                 return -EINVAL;
2474
2475         /*
2476          * If our intermediate WM are identical to the final WM, then we can
2477          * omit the post-vblank programming; only update if it's different.
2478          */
2479         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2480                 newstate->wm.need_postvbl_update = false;
2481
2482         return 0;
2483 }
2484
2485 /*
2486  * Merge the watermarks from all active pipes for a specific level.
2487  */
2488 static void ilk_merge_wm_level(struct drm_device *dev,
2489                                int level,
2490                                struct intel_wm_level *ret_wm)
2491 {
2492         const struct intel_crtc *intel_crtc;
2493
2494         ret_wm->enable = true;
2495
2496         for_each_intel_crtc(dev, intel_crtc) {
2497                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2498                 const struct intel_wm_level *wm = &active->wm[level];
2499
2500                 if (!active->pipe_enabled)
2501                         continue;
2502
2503                 /*
2504                  * The watermark values may have been used in the past,
2505                  * so we must maintain them in the registers for some
2506                  * time even if the level is now disabled.
2507                  */
2508                 if (!wm->enable)
2509                         ret_wm->enable = false;
2510
2511                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2512                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2513                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2514                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2515         }
2516 }
2517
2518 /*
2519  * Merge all low power watermarks for all active pipes.
2520  */
2521 static void ilk_wm_merge(struct drm_device *dev,
2522                          const struct intel_wm_config *config,
2523                          const struct ilk_wm_maximums *max,
2524                          struct intel_pipe_wm *merged)
2525 {
2526         struct drm_i915_private *dev_priv = to_i915(dev);
2527         int level, max_level = ilk_wm_max_level(dev_priv);
2528         int last_enabled_level = max_level;
2529
2530         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2531         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2532             config->num_pipes_active > 1)
2533                 last_enabled_level = 0;
2534
2535         /* ILK: FBC WM must be disabled always */
2536         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
2537
2538         /* merge each WM1+ level */
2539         for (level = 1; level <= max_level; level++) {
2540                 struct intel_wm_level *wm = &merged->wm[level];
2541
2542                 ilk_merge_wm_level(dev, level, wm);
2543
2544                 if (level > last_enabled_level)
2545                         wm->enable = false;
2546                 else if (!ilk_validate_wm_level(level, max, wm))
2547                         /* make sure all following levels get disabled */
2548                         last_enabled_level = level - 1;
2549
2550                 /*
2551                  * The spec says it is preferred to disable
2552                  * FBC WMs instead of disabling a WM level.
2553                  */
2554                 if (wm->fbc_val > max->fbc) {
2555                         if (wm->enable)
2556                                 merged->fbc_wm_enabled = false;
2557                         wm->fbc_val = 0;
2558                 }
2559         }
2560
2561         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2562         /*
2563          * FIXME this is racy. FBC might get enabled later.
2564          * What we should check here is whether FBC can be
2565          * enabled sometime later.
2566          */
2567         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2568             intel_fbc_is_active(dev_priv)) {
2569                 for (level = 2; level <= max_level; level++) {
2570                         struct intel_wm_level *wm = &merged->wm[level];
2571
2572                         wm->enable = false;
2573                 }
2574         }
2575 }
2576
2577 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2578 {
2579         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2580         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2581 }
2582
2583 /* The value we need to program into the WM_LPx latency field */
2584 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2585 {
2586         struct drm_i915_private *dev_priv = to_i915(dev);
2587
2588         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2589                 return 2 * level;
2590         else
2591                 return dev_priv->wm.pri_latency[level];
2592 }
2593
2594 static void ilk_compute_wm_results(struct drm_device *dev,
2595                                    const struct intel_pipe_wm *merged,
2596                                    enum intel_ddb_partitioning partitioning,
2597                                    struct ilk_wm_values *results)
2598 {
2599         struct drm_i915_private *dev_priv = to_i915(dev);
2600         struct intel_crtc *intel_crtc;
2601         int level, wm_lp;
2602
2603         results->enable_fbc_wm = merged->fbc_wm_enabled;
2604         results->partitioning = partitioning;
2605
2606         /* LP1+ register values */
2607         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2608                 const struct intel_wm_level *r;
2609
2610                 level = ilk_wm_lp_to_level(wm_lp, merged);
2611
2612                 r = &merged->wm[level];
2613
2614                 /*
2615                  * Maintain the watermark values even if the level is
2616                  * disabled. Doing otherwise could cause underruns.
2617                  */
2618                 results->wm_lp[wm_lp - 1] =
2619                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2620                         (r->pri_val << WM1_LP_SR_SHIFT) |
2621                         r->cur_val;
2622
2623                 if (r->enable)
2624                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2625
2626                 if (INTEL_GEN(dev_priv) >= 8)
2627                         results->wm_lp[wm_lp - 1] |=
2628                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2629                 else
2630                         results->wm_lp[wm_lp - 1] |=
2631                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2632
2633                 /*
2634                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2635                  * level is disabled. Doing otherwise could cause underruns.
2636                  */
2637                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
2638                         WARN_ON(wm_lp != 1);
2639                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2640                 } else
2641                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2642         }
2643
2644         /* LP0 register values */
2645         for_each_intel_crtc(dev, intel_crtc) {
2646                 enum pipe pipe = intel_crtc->pipe;
2647                 const struct intel_wm_level *r =
2648                         &intel_crtc->wm.active.ilk.wm[0];
2649
2650                 if (WARN_ON(!r->enable))
2651                         continue;
2652
2653                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2654
2655                 results->wm_pipe[pipe] =
2656                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2657                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2658                         r->cur_val;
2659         }
2660 }
2661
2662 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2663  * case both are at the same level. Prefer r1 in case they're the same. */
2664 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2665                                                   struct intel_pipe_wm *r1,
2666                                                   struct intel_pipe_wm *r2)
2667 {
2668         int level, max_level = ilk_wm_max_level(to_i915(dev));
2669         int level1 = 0, level2 = 0;
2670
2671         for (level = 1; level <= max_level; level++) {
2672                 if (r1->wm[level].enable)
2673                         level1 = level;
2674                 if (r2->wm[level].enable)
2675                         level2 = level;
2676         }
2677
2678         if (level1 == level2) {
2679                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2680                         return r2;
2681                 else
2682                         return r1;
2683         } else if (level1 > level2) {
2684                 return r1;
2685         } else {
2686                 return r2;
2687         }
2688 }
2689
2690 /* dirty bits used to track which watermarks need changes */
2691 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2692 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2693 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2694 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2695 #define WM_DIRTY_FBC (1 << 24)
2696 #define WM_DIRTY_DDB (1 << 25)
2697
2698 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2699                                          const struct ilk_wm_values *old,
2700                                          const struct ilk_wm_values *new)
2701 {
2702         unsigned int dirty = 0;
2703         enum pipe pipe;
2704         int wm_lp;
2705
2706         for_each_pipe(dev_priv, pipe) {
2707                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2708                         dirty |= WM_DIRTY_LINETIME(pipe);
2709                         /* Must disable LP1+ watermarks too */
2710                         dirty |= WM_DIRTY_LP_ALL;
2711                 }
2712
2713                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2714                         dirty |= WM_DIRTY_PIPE(pipe);
2715                         /* Must disable LP1+ watermarks too */
2716                         dirty |= WM_DIRTY_LP_ALL;
2717                 }
2718         }
2719
2720         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2721                 dirty |= WM_DIRTY_FBC;
2722                 /* Must disable LP1+ watermarks too */
2723                 dirty |= WM_DIRTY_LP_ALL;
2724         }
2725
2726         if (old->partitioning != new->partitioning) {
2727                 dirty |= WM_DIRTY_DDB;
2728                 /* Must disable LP1+ watermarks too */
2729                 dirty |= WM_DIRTY_LP_ALL;
2730         }
2731
2732         /* LP1+ watermarks already deemed dirty, no need to continue */
2733         if (dirty & WM_DIRTY_LP_ALL)
2734                 return dirty;
2735
2736         /* Find the lowest numbered LP1+ watermark in need of an update... */
2737         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2738                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2739                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2740                         break;
2741         }
2742
2743         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2744         for (; wm_lp <= 3; wm_lp++)
2745                 dirty |= WM_DIRTY_LP(wm_lp);
2746
2747         return dirty;
2748 }
2749
2750 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2751                                unsigned int dirty)
2752 {
2753         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2754         bool changed = false;
2755
2756         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2757                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2758                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2759                 changed = true;
2760         }
2761         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2762                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2763                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2764                 changed = true;
2765         }
2766         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2767                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2768                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2769                 changed = true;
2770         }
2771
2772         /*
2773          * Don't touch WM1S_LP_EN here.
2774          * Doing so could cause underruns.
2775          */
2776
2777         return changed;
2778 }
2779
2780 /*
2781  * The spec says we shouldn't write when we don't need, because every write
2782  * causes WMs to be re-evaluated, expending some power.
2783  */
2784 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2785                                 struct ilk_wm_values *results)
2786 {
2787         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2788         unsigned int dirty;
2789         uint32_t val;
2790
2791         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2792         if (!dirty)
2793                 return;
2794
2795         _ilk_disable_lp_wm(dev_priv, dirty);
2796
2797         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2798                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2799         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2800                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2801         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2802                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2803
2804         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2805                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2806         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2807                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2808         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2809                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2810
2811         if (dirty & WM_DIRTY_DDB) {
2812                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2813                         val = I915_READ(WM_MISC);
2814                         if (results->partitioning == INTEL_DDB_PART_1_2)
2815                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2816                         else
2817                                 val |= WM_MISC_DATA_PARTITION_5_6;
2818                         I915_WRITE(WM_MISC, val);
2819                 } else {
2820                         val = I915_READ(DISP_ARB_CTL2);
2821                         if (results->partitioning == INTEL_DDB_PART_1_2)
2822                                 val &= ~DISP_DATA_PARTITION_5_6;
2823                         else
2824                                 val |= DISP_DATA_PARTITION_5_6;
2825                         I915_WRITE(DISP_ARB_CTL2, val);
2826                 }
2827         }
2828
2829         if (dirty & WM_DIRTY_FBC) {
2830                 val = I915_READ(DISP_ARB_CTL);
2831                 if (results->enable_fbc_wm)
2832                         val &= ~DISP_FBC_WM_DIS;
2833                 else
2834                         val |= DISP_FBC_WM_DIS;
2835                 I915_WRITE(DISP_ARB_CTL, val);
2836         }
2837
2838         if (dirty & WM_DIRTY_LP(1) &&
2839             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2840                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2841
2842         if (INTEL_GEN(dev_priv) >= 7) {
2843                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2844                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2845                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2846                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2847         }
2848
2849         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2850                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2851         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2852                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2853         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2854                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2855
2856         dev_priv->wm.hw = *results;
2857 }
2858
2859 bool ilk_disable_lp_wm(struct drm_device *dev)
2860 {
2861         struct drm_i915_private *dev_priv = to_i915(dev);
2862
2863         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2864 }
2865
2866 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2867
2868 /*
2869  * FIXME: We still don't have the proper code detect if we need to apply the WA,
2870  * so assume we'll always need it in order to avoid underruns.
2871  */
2872 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2873 {
2874         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2875
2876         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
2877                 return true;
2878
2879         return false;
2880 }
2881
2882 static bool
2883 intel_has_sagv(struct drm_i915_private *dev_priv)
2884 {
2885         if (IS_KABYLAKE(dev_priv))
2886                 return true;
2887
2888         if (IS_SKYLAKE(dev_priv) &&
2889             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2890                 return true;
2891
2892         return false;
2893 }
2894
2895 /*
2896  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2897  * depending on power and performance requirements. The display engine access
2898  * to system memory is blocked during the adjustment time. Because of the
2899  * blocking time, having this enabled can cause full system hangs and/or pipe
2900  * underruns if we don't meet all of the following requirements:
2901  *
2902  *  - <= 1 pipe enabled
2903  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2904  *  - We're not using an interlaced display configuration
2905  */
2906 int
2907 intel_enable_sagv(struct drm_i915_private *dev_priv)
2908 {
2909         int ret;
2910
2911         if (!intel_has_sagv(dev_priv))
2912                 return 0;
2913
2914         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2915                 return 0;
2916
2917         DRM_DEBUG_KMS("Enabling the SAGV\n");
2918         mutex_lock(&dev_priv->rps.hw_lock);
2919
2920         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2921                                       GEN9_SAGV_ENABLE);
2922
2923         /* We don't need to wait for the SAGV when enabling */
2924         mutex_unlock(&dev_priv->rps.hw_lock);
2925
2926         /*
2927          * Some skl systems, pre-release machines in particular,
2928          * don't actually have an SAGV.
2929          */
2930         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2931                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2932                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2933                 return 0;
2934         } else if (ret < 0) {
2935                 DRM_ERROR("Failed to enable the SAGV\n");
2936                 return ret;
2937         }
2938
2939         dev_priv->sagv_status = I915_SAGV_ENABLED;
2940         return 0;
2941 }
2942
2943 int
2944 intel_disable_sagv(struct drm_i915_private *dev_priv)
2945 {
2946         int ret;
2947
2948         if (!intel_has_sagv(dev_priv))
2949                 return 0;
2950
2951         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2952                 return 0;
2953
2954         DRM_DEBUG_KMS("Disabling the SAGV\n");
2955         mutex_lock(&dev_priv->rps.hw_lock);
2956
2957         /* bspec says to keep retrying for at least 1 ms */
2958         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2959                                 GEN9_SAGV_DISABLE,
2960                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
2961                                 1);
2962         mutex_unlock(&dev_priv->rps.hw_lock);
2963
2964         /*
2965          * Some skl systems, pre-release machines in particular,
2966          * don't actually have an SAGV.
2967          */
2968         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2969                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2970                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2971                 return 0;
2972         } else if (ret < 0) {
2973                 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
2974                 return ret;
2975         }
2976
2977         dev_priv->sagv_status = I915_SAGV_DISABLED;
2978         return 0;
2979 }
2980
2981 bool intel_can_enable_sagv(struct drm_atomic_state *state)
2982 {
2983         struct drm_device *dev = state->dev;
2984         struct drm_i915_private *dev_priv = to_i915(dev);
2985         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2986         struct intel_crtc *crtc;
2987         struct intel_plane *plane;
2988         struct intel_crtc_state *cstate;
2989         enum pipe pipe;
2990         int level, latency;
2991
2992         if (!intel_has_sagv(dev_priv))
2993                 return false;
2994
2995         /*
2996          * SKL workaround: bspec recommends we disable the SAGV when we have
2997          * more then one pipe enabled
2998          *
2999          * If there are no active CRTCs, no additional checks need be performed
3000          */
3001         if (hweight32(intel_state->active_crtcs) == 0)
3002                 return true;
3003         else if (hweight32(intel_state->active_crtcs) > 1)
3004                 return false;
3005
3006         /* Since we're now guaranteed to only have one active CRTC... */
3007         pipe = ffs(intel_state->active_crtcs) - 1;
3008         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3009         cstate = to_intel_crtc_state(crtc->base.state);
3010
3011         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3012                 return false;
3013
3014         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3015                 struct skl_plane_wm *wm =
3016                         &cstate->wm.skl.optimal.planes[plane->id];
3017
3018                 /* Skip this plane if it's not enabled */
3019                 if (!wm->wm[0].plane_en)
3020                         continue;
3021
3022                 /* Find the highest enabled wm level for this plane */
3023                 for (level = ilk_wm_max_level(dev_priv);
3024                      !wm->wm[level].plane_en; --level)
3025                      { }
3026
3027                 latency = dev_priv->wm.skl_latency[level];
3028
3029                 if (skl_needs_memory_bw_wa(intel_state) &&
3030                     plane->base.state->fb->modifier ==
3031                     I915_FORMAT_MOD_X_TILED)
3032                         latency += 15;
3033
3034                 /*
3035                  * If any of the planes on this pipe don't enable wm levels
3036                  * that incur memory latencies higher then 30µs we can't enable
3037                  * the SAGV
3038                  */
3039                 if (latency < SKL_SAGV_BLOCK_TIME)
3040                         return false;
3041         }
3042
3043         return true;
3044 }
3045
3046 static void
3047 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3048                                    const struct intel_crtc_state *cstate,
3049                                    struct skl_ddb_entry *alloc, /* out */
3050                                    int *num_active /* out */)
3051 {
3052         struct drm_atomic_state *state = cstate->base.state;
3053         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3054         struct drm_i915_private *dev_priv = to_i915(dev);
3055         struct drm_crtc *for_crtc = cstate->base.crtc;
3056         unsigned int pipe_size, ddb_size;
3057         int nth_active_pipe;
3058
3059         if (WARN_ON(!state) || !cstate->base.active) {
3060                 alloc->start = 0;
3061                 alloc->end = 0;
3062                 *num_active = hweight32(dev_priv->active_crtcs);
3063                 return;
3064         }
3065
3066         if (intel_state->active_pipe_changes)
3067                 *num_active = hweight32(intel_state->active_crtcs);
3068         else
3069                 *num_active = hweight32(dev_priv->active_crtcs);
3070
3071         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3072         WARN_ON(ddb_size == 0);
3073
3074         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3075
3076         /*
3077          * If the state doesn't change the active CRTC's, then there's
3078          * no need to recalculate; the existing pipe allocation limits
3079          * should remain unchanged.  Note that we're safe from racing
3080          * commits since any racing commit that changes the active CRTC
3081          * list would need to grab _all_ crtc locks, including the one
3082          * we currently hold.
3083          */
3084         if (!intel_state->active_pipe_changes) {
3085                 /*
3086                  * alloc may be cleared by clear_intel_crtc_state,
3087                  * copy from old state to be sure
3088                  */
3089                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3090                 return;
3091         }
3092
3093         nth_active_pipe = hweight32(intel_state->active_crtcs &
3094                                     (drm_crtc_mask(for_crtc) - 1));
3095         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3096         alloc->start = nth_active_pipe * ddb_size / *num_active;
3097         alloc->end = alloc->start + pipe_size;
3098 }
3099
3100 static unsigned int skl_cursor_allocation(int num_active)
3101 {
3102         if (num_active == 1)
3103                 return 32;
3104
3105         return 8;
3106 }
3107
3108 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3109 {
3110         entry->start = reg & 0x3ff;
3111         entry->end = (reg >> 16) & 0x3ff;
3112         if (entry->end)
3113                 entry->end += 1;
3114 }
3115
3116 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3117                           struct skl_ddb_allocation *ddb /* out */)
3118 {
3119         struct intel_crtc *crtc;
3120
3121         memset(ddb, 0, sizeof(*ddb));
3122
3123         for_each_intel_crtc(&dev_priv->drm, crtc) {
3124                 enum intel_display_power_domain power_domain;
3125                 enum plane_id plane_id;
3126                 enum pipe pipe = crtc->pipe;
3127
3128                 power_domain = POWER_DOMAIN_PIPE(pipe);
3129                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3130                         continue;
3131
3132                 for_each_plane_id_on_crtc(crtc, plane_id) {
3133                         u32 val;
3134
3135                         if (plane_id != PLANE_CURSOR)
3136                                 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3137                         else
3138                                 val = I915_READ(CUR_BUF_CFG(pipe));
3139
3140                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3141                 }
3142
3143                 intel_display_power_put(dev_priv, power_domain);
3144         }
3145 }
3146
3147 /*
3148  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3149  * The bspec defines downscale amount as:
3150  *
3151  * """
3152  * Horizontal down scale amount = maximum[1, Horizontal source size /
3153  *                                           Horizontal destination size]
3154  * Vertical down scale amount = maximum[1, Vertical source size /
3155  *                                         Vertical destination size]
3156  * Total down scale amount = Horizontal down scale amount *
3157  *                           Vertical down scale amount
3158  * """
3159  *
3160  * Return value is provided in 16.16 fixed point form to retain fractional part.
3161  * Caller should take care of dividing & rounding off the value.
3162  */
3163 static uint32_t
3164 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3165 {
3166         uint32_t downscale_h, downscale_w;
3167         uint32_t src_w, src_h, dst_w, dst_h;
3168
3169         if (WARN_ON(!pstate->base.visible))
3170                 return DRM_PLANE_HELPER_NO_SCALING;
3171
3172         /* n.b., src is 16.16 fixed point, dst is whole integer */
3173         src_w = drm_rect_width(&pstate->base.src);
3174         src_h = drm_rect_height(&pstate->base.src);
3175         dst_w = drm_rect_width(&pstate->base.dst);
3176         dst_h = drm_rect_height(&pstate->base.dst);
3177         if (drm_rotation_90_or_270(pstate->base.rotation))
3178                 swap(dst_w, dst_h);
3179
3180         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3181         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3182
3183         /* Provide result in 16.16 fixed point */
3184         return (uint64_t)downscale_w * downscale_h >> 16;
3185 }
3186
3187 static unsigned int
3188 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3189                              const struct drm_plane_state *pstate,
3190                              int y)
3191 {
3192         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3193         uint32_t down_scale_amount, data_rate;
3194         uint32_t width = 0, height = 0;
3195         struct drm_framebuffer *fb;
3196         u32 format;
3197
3198         if (!intel_pstate->base.visible)
3199                 return 0;
3200
3201         fb = pstate->fb;
3202         format = fb->format->format;
3203
3204         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3205                 return 0;
3206         if (y && format != DRM_FORMAT_NV12)
3207                 return 0;
3208
3209         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3210         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3211
3212         if (drm_rotation_90_or_270(pstate->rotation))
3213                 swap(width, height);
3214
3215         /* for planar format */
3216         if (format == DRM_FORMAT_NV12) {
3217                 if (y)  /* y-plane data rate */
3218                         data_rate = width * height *
3219                                 fb->format->cpp[0];
3220                 else    /* uv-plane data rate */
3221                         data_rate = (width / 2) * (height / 2) *
3222                                 fb->format->cpp[1];
3223         } else {
3224                 /* for packed formats */
3225                 data_rate = width * height * fb->format->cpp[0];
3226         }
3227
3228         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3229
3230         return (uint64_t)data_rate * down_scale_amount >> 16;
3231 }
3232
3233 /*
3234  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3235  * a 8192x4096@32bpp framebuffer:
3236  *   3 * 4096 * 8192  * 4 < 2^32
3237  */
3238 static unsigned int
3239 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3240                                  unsigned *plane_data_rate,
3241                                  unsigned *plane_y_data_rate)
3242 {
3243         struct drm_crtc_state *cstate = &intel_cstate->base;
3244         struct drm_atomic_state *state = cstate->state;
3245         struct drm_plane *plane;
3246         const struct drm_plane_state *pstate;
3247         unsigned int total_data_rate = 0;
3248
3249         if (WARN_ON(!state))
3250                 return 0;
3251
3252         /* Calculate and cache data rate for each plane */
3253         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3254                 enum plane_id plane_id = to_intel_plane(plane)->id;
3255                 unsigned int rate;
3256
3257                 /* packed/uv */
3258                 rate = skl_plane_relative_data_rate(intel_cstate,
3259                                                     pstate, 0);
3260                 plane_data_rate[plane_id] = rate;
3261
3262                 total_data_rate += rate;
3263
3264                 /* y-plane */
3265                 rate = skl_plane_relative_data_rate(intel_cstate,
3266                                                     pstate, 1);
3267                 plane_y_data_rate[plane_id] = rate;
3268
3269                 total_data_rate += rate;
3270         }
3271
3272         return total_data_rate;
3273 }
3274
3275 static uint16_t
3276 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3277                   const int y)
3278 {
3279         struct drm_framebuffer *fb = pstate->fb;
3280         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3281         uint32_t src_w, src_h;
3282         uint32_t min_scanlines = 8;
3283         uint8_t plane_bpp;
3284
3285         if (WARN_ON(!fb))
3286                 return 0;
3287
3288         /* For packed formats, no y-plane, return 0 */
3289         if (y && fb->format->format != DRM_FORMAT_NV12)
3290                 return 0;
3291
3292         /* For Non Y-tile return 8-blocks */
3293         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3294             fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3295                 return 8;
3296
3297         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3298         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3299
3300         if (drm_rotation_90_or_270(pstate->rotation))
3301                 swap(src_w, src_h);
3302
3303         /* Halve UV plane width and height for NV12 */
3304         if (fb->format->format == DRM_FORMAT_NV12 && !y) {
3305                 src_w /= 2;
3306                 src_h /= 2;
3307         }
3308
3309         if (fb->format->format == DRM_FORMAT_NV12 && !y)
3310                 plane_bpp = fb->format->cpp[1];
3311         else
3312                 plane_bpp = fb->format->cpp[0];
3313
3314         if (drm_rotation_90_or_270(pstate->rotation)) {
3315                 switch (plane_bpp) {
3316                 case 1:
3317                         min_scanlines = 32;
3318                         break;
3319                 case 2:
3320                         min_scanlines = 16;
3321                         break;
3322                 case 4:
3323                         min_scanlines = 8;
3324                         break;
3325                 case 8:
3326                         min_scanlines = 4;
3327                         break;
3328                 default:
3329                         WARN(1, "Unsupported pixel depth %u for rotation",
3330                              plane_bpp);
3331                         min_scanlines = 32;
3332                 }
3333         }
3334
3335         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3336 }
3337
3338 static void
3339 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3340                  uint16_t *minimum, uint16_t *y_minimum)
3341 {
3342         const struct drm_plane_state *pstate;
3343         struct drm_plane *plane;
3344
3345         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3346                 enum plane_id plane_id = to_intel_plane(plane)->id;
3347
3348                 if (plane_id == PLANE_CURSOR)
3349                         continue;
3350
3351                 if (!pstate->visible)
3352                         continue;
3353
3354                 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
3355                 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
3356         }
3357
3358         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3359 }
3360
3361 static int
3362 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3363                       struct skl_ddb_allocation *ddb /* out */)
3364 {
3365         struct drm_atomic_state *state = cstate->base.state;
3366         struct drm_crtc *crtc = cstate->base.crtc;
3367         struct drm_device *dev = crtc->dev;
3368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369         enum pipe pipe = intel_crtc->pipe;
3370         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3371         uint16_t alloc_size, start;
3372         uint16_t minimum[I915_MAX_PLANES] = {};
3373         uint16_t y_minimum[I915_MAX_PLANES] = {};
3374         unsigned int total_data_rate;
3375         enum plane_id plane_id;
3376         int num_active;
3377         unsigned plane_data_rate[I915_MAX_PLANES] = {};
3378         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3379
3380         /* Clear the partitioning for disabled planes. */
3381         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3382         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3383
3384         if (WARN_ON(!state))
3385                 return 0;
3386
3387         if (!cstate->base.active) {
3388                 alloc->start = alloc->end = 0;
3389                 return 0;
3390         }
3391
3392         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3393         alloc_size = skl_ddb_entry_size(alloc);
3394         if (alloc_size == 0) {
3395                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3396                 return 0;
3397         }
3398
3399         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3400
3401         /*
3402          * 1. Allocate the mininum required blocks for each active plane
3403          * and allocate the cursor, it doesn't require extra allocation
3404          * proportional to the data rate.
3405          */
3406
3407         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3408                 alloc_size -= minimum[plane_id];
3409                 alloc_size -= y_minimum[plane_id];
3410         }
3411
3412         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3413         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3414
3415         /*
3416          * 2. Distribute the remaining space in proportion to the amount of
3417          * data each plane needs to fetch from memory.
3418          *
3419          * FIXME: we may not allocate every single block here.
3420          */
3421         total_data_rate = skl_get_total_relative_data_rate(cstate,
3422                                                            plane_data_rate,
3423                                                            plane_y_data_rate);
3424         if (total_data_rate == 0)
3425                 return 0;
3426
3427         start = alloc->start;
3428         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3429                 unsigned int data_rate, y_data_rate;
3430                 uint16_t plane_blocks, y_plane_blocks = 0;
3431
3432                 if (plane_id == PLANE_CURSOR)
3433                         continue;
3434
3435                 data_rate = plane_data_rate[plane_id];
3436
3437                 /*
3438                  * allocation for (packed formats) or (uv-plane part of planar format):
3439                  * promote the expression to 64 bits to avoid overflowing, the
3440                  * result is < available as data_rate / total_data_rate < 1
3441                  */
3442                 plane_blocks = minimum[plane_id];
3443                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3444                                         total_data_rate);
3445
3446                 /* Leave disabled planes at (0,0) */
3447                 if (data_rate) {
3448                         ddb->plane[pipe][plane_id].start = start;
3449                         ddb->plane[pipe][plane_id].end = start + plane_blocks;
3450                 }
3451
3452                 start += plane_blocks;
3453
3454                 /*
3455                  * allocation for y_plane part of planar format:
3456                  */
3457                 y_data_rate = plane_y_data_rate[plane_id];
3458
3459                 y_plane_blocks = y_minimum[plane_id];
3460                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3461                                         total_data_rate);
3462
3463                 if (y_data_rate) {
3464                         ddb->y_plane[pipe][plane_id].start = start;
3465                         ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
3466                 }
3467
3468                 start += y_plane_blocks;
3469         }
3470
3471         return 0;
3472 }
3473
3474 /*
3475  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3476  * for the read latency) and cpp should always be <= 8, so that
3477  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3478  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3479 */
3480 static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
3481                                          uint32_t latency)
3482 {
3483         uint32_t wm_intermediate_val;
3484         uint_fixed_16_16_t ret;
3485
3486         if (latency == 0)
3487                 return FP_16_16_MAX;
3488
3489         wm_intermediate_val = latency * pixel_rate * cpp;
3490         ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
3491         return ret;
3492 }
3493
3494 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
3495                         uint32_t pipe_htotal,
3496                         uint32_t latency,
3497                         uint_fixed_16_16_t plane_blocks_per_line)
3498 {
3499         uint32_t wm_intermediate_val;
3500         uint_fixed_16_16_t ret;
3501
3502         if (latency == 0)
3503                 return FP_16_16_MAX;
3504
3505         wm_intermediate_val = latency * pixel_rate;
3506         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
3507                                            pipe_htotal * 1000);
3508         ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line);
3509         return ret;
3510 }
3511
3512 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3513                                               struct intel_plane_state *pstate)
3514 {
3515         uint64_t adjusted_pixel_rate;
3516         uint64_t downscale_amount;
3517         uint64_t pixel_rate;
3518
3519         /* Shouldn't reach here on disabled planes... */
3520         if (WARN_ON(!pstate->base.visible))
3521                 return 0;
3522
3523         /*
3524          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3525          * with additional adjustments for plane-specific scaling.
3526          */
3527         adjusted_pixel_rate = cstate->pixel_rate;
3528         downscale_amount = skl_plane_downscale_amount(pstate);
3529
3530         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3531         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3532
3533         return pixel_rate;
3534 }
3535
3536 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3537                                 struct intel_crtc_state *cstate,
3538                                 struct intel_plane_state *intel_pstate,
3539                                 uint16_t ddb_allocation,
3540                                 int level,
3541                                 uint16_t *out_blocks, /* out */
3542                                 uint8_t *out_lines, /* out */
3543                                 bool *enabled /* out */)
3544 {
3545         struct drm_plane_state *pstate = &intel_pstate->base;
3546         struct drm_framebuffer *fb = pstate->fb;
3547         uint32_t latency = dev_priv->wm.skl_latency[level];
3548         uint_fixed_16_16_t method1, method2;
3549         uint_fixed_16_16_t plane_blocks_per_line;
3550         uint_fixed_16_16_t selected_result;
3551         uint32_t interm_pbpl;
3552         uint32_t plane_bytes_per_line;
3553         uint32_t res_blocks, res_lines;
3554         uint8_t cpp;
3555         uint32_t width = 0, height = 0;
3556         uint32_t plane_pixel_rate;
3557         uint_fixed_16_16_t y_tile_minimum;
3558         uint32_t y_min_scanlines;
3559         struct intel_atomic_state *state =
3560                 to_intel_atomic_state(cstate->base.state);
3561         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3562         bool y_tiled, x_tiled;
3563
3564         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3565                 *enabled = false;
3566                 return 0;
3567         }
3568
3569         y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3570                   fb->modifier == I915_FORMAT_MOD_Yf_TILED;
3571         x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
3572
3573         /* Display WA #1141: kbl. */
3574         if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
3575                 latency += 4;
3576
3577         if (apply_memory_bw_wa && x_tiled)
3578                 latency += 15;
3579
3580         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3581         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3582
3583         if (drm_rotation_90_or_270(pstate->rotation))
3584                 swap(width, height);
3585
3586         cpp = fb->format->cpp[0];
3587         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3588
3589         if (drm_rotation_90_or_270(pstate->rotation)) {
3590                 int cpp = (fb->format->format == DRM_FORMAT_NV12) ?
3591                         fb->format->cpp[1] :
3592                         fb->format->cpp[0];
3593
3594                 switch (cpp) {
3595                 case 1:
3596                         y_min_scanlines = 16;
3597                         break;
3598                 case 2:
3599                         y_min_scanlines = 8;
3600                         break;
3601                 case 4:
3602                         y_min_scanlines = 4;
3603                         break;
3604                 default:
3605                         MISSING_CASE(cpp);
3606                         return -EINVAL;
3607                 }
3608         } else {
3609                 y_min_scanlines = 4;
3610         }
3611
3612         if (apply_memory_bw_wa)
3613                 y_min_scanlines *= 2;
3614
3615         plane_bytes_per_line = width * cpp;
3616         if (y_tiled) {
3617                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
3618                                            y_min_scanlines, 512);
3619                 plane_blocks_per_line =
3620                       fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
3621         } else if (x_tiled) {
3622                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
3623                 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3624         } else {
3625                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
3626                 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3627         }
3628
3629         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3630         method2 = skl_wm_method2(plane_pixel_rate,
3631                                  cstate->base.adjusted_mode.crtc_htotal,
3632                                  latency,
3633                                  plane_blocks_per_line);
3634
3635         y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines,
3636                                              plane_blocks_per_line);
3637
3638         if (y_tiled) {
3639                 selected_result = max_fixed_16_16(method2, y_tile_minimum);
3640         } else {
3641                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3642                     (plane_bytes_per_line / 512 < 1))
3643                         selected_result = method2;
3644                 else if ((ddb_allocation /
3645                         fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
3646                         selected_result = min_fixed_16_16(method1, method2);
3647                 else
3648                         selected_result = method1;
3649         }
3650
3651         res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1;
3652         res_lines = DIV_ROUND_UP(selected_result.val,
3653                                  plane_blocks_per_line.val);
3654
3655         if (level >= 1 && level <= 7) {
3656                 if (y_tiled) {
3657                         res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
3658                         res_lines += y_min_scanlines;
3659                 } else {
3660                         res_blocks++;
3661                 }
3662         }
3663
3664         if (res_blocks >= ddb_allocation || res_lines > 31) {
3665                 *enabled = false;
3666
3667                 /*
3668                  * If there are no valid level 0 watermarks, then we can't
3669                  * support this display configuration.
3670                  */
3671                 if (level) {
3672                         return 0;
3673                 } else {
3674                         struct drm_plane *plane = pstate->plane;
3675
3676                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3677                         DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
3678                                       plane->base.id, plane->name,
3679                                       res_blocks, ddb_allocation, res_lines);
3680                         return -EINVAL;
3681                 }
3682         }
3683
3684         *out_blocks = res_blocks;
3685         *out_lines = res_lines;
3686         *enabled = true;
3687
3688         return 0;
3689 }
3690
3691 static int
3692 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3693                      struct skl_ddb_allocation *ddb,
3694                      struct intel_crtc_state *cstate,
3695                      struct intel_plane *intel_plane,
3696                      int level,
3697                      struct skl_wm_level *result)
3698 {
3699         struct drm_atomic_state *state = cstate->base.state;
3700         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3701         struct drm_plane *plane = &intel_plane->base;
3702         struct intel_plane_state *intel_pstate = NULL;
3703         uint16_t ddb_blocks;
3704         enum pipe pipe = intel_crtc->pipe;
3705         int ret;
3706
3707         if (state)
3708                 intel_pstate =
3709                         intel_atomic_get_existing_plane_state(state,
3710                                                               intel_plane);
3711
3712         /*
3713          * Note: If we start supporting multiple pending atomic commits against
3714          * the same planes/CRTC's in the future, plane->state will no longer be
3715          * the correct pre-state to use for the calculations here and we'll
3716          * need to change where we get the 'unchanged' plane data from.
3717          *
3718          * For now this is fine because we only allow one queued commit against
3719          * a CRTC.  Even if the plane isn't modified by this transaction and we
3720          * don't have a plane lock, we still have the CRTC's lock, so we know
3721          * that no other transactions are racing with us to update it.
3722          */
3723         if (!intel_pstate)
3724                 intel_pstate = to_intel_plane_state(plane->state);
3725
3726         WARN_ON(!intel_pstate->base.fb);
3727
3728         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
3729
3730         ret = skl_compute_plane_wm(dev_priv,
3731                                    cstate,
3732                                    intel_pstate,
3733                                    ddb_blocks,
3734                                    level,
3735                                    &result->plane_res_b,
3736                                    &result->plane_res_l,
3737                                    &result->plane_en);
3738         if (ret)
3739                 return ret;
3740
3741         return 0;
3742 }
3743
3744 static uint32_t
3745 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3746 {
3747         struct drm_atomic_state *state = cstate->base.state;
3748         struct drm_i915_private *dev_priv = to_i915(state->dev);
3749         uint32_t pixel_rate;
3750         uint32_t linetime_wm;
3751
3752         if (!cstate->base.active)
3753                 return 0;
3754
3755         pixel_rate = cstate->pixel_rate;
3756
3757         if (WARN_ON(pixel_rate == 0))
3758                 return 0;
3759
3760         linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
3761                                    1000, pixel_rate);
3762
3763         /* Display WA #1135: bxt. */
3764         if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
3765                 linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
3766
3767         return linetime_wm;
3768 }
3769
3770 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3771                                       struct skl_wm_level *trans_wm /* out */)
3772 {
3773         if (!cstate->base.active)
3774                 return;
3775
3776         /* Until we know more, just disable transition WMs */
3777         trans_wm->plane_en = false;
3778 }
3779
3780 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3781                              struct skl_ddb_allocation *ddb,
3782                              struct skl_pipe_wm *pipe_wm)
3783 {
3784         struct drm_device *dev = cstate->base.crtc->dev;
3785         const struct drm_i915_private *dev_priv = to_i915(dev);
3786         struct intel_plane *intel_plane;
3787         struct skl_plane_wm *wm;
3788         int level, max_level = ilk_wm_max_level(dev_priv);
3789         int ret;
3790
3791         /*
3792          * We'll only calculate watermarks for planes that are actually
3793          * enabled, so make sure all other planes are set as disabled.
3794          */
3795         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3796
3797         for_each_intel_plane_mask(&dev_priv->drm,
3798                                   intel_plane,
3799                                   cstate->base.plane_mask) {
3800                 wm = &pipe_wm->planes[intel_plane->id];
3801
3802                 for (level = 0; level <= max_level; level++) {
3803                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3804                                                    intel_plane, level,
3805                                                    &wm->wm[level]);
3806                         if (ret)
3807                                 return ret;
3808                 }
3809                 skl_compute_transition_wm(cstate, &wm->trans_wm);
3810         }
3811         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3812
3813         return 0;
3814 }
3815
3816 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3817                                 i915_reg_t reg,
3818                                 const struct skl_ddb_entry *entry)
3819 {
3820         if (entry->end)
3821                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3822         else
3823                 I915_WRITE(reg, 0);
3824 }
3825
3826 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3827                                i915_reg_t reg,
3828                                const struct skl_wm_level *level)
3829 {
3830         uint32_t val = 0;
3831
3832         if (level->plane_en) {
3833                 val |= PLANE_WM_EN;
3834                 val |= level->plane_res_b;
3835                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3836         }
3837
3838         I915_WRITE(reg, val);
3839 }
3840
3841 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3842                                const struct skl_plane_wm *wm,
3843                                const struct skl_ddb_allocation *ddb,
3844                                enum plane_id plane_id)
3845 {
3846         struct drm_crtc *crtc = &intel_crtc->base;
3847         struct drm_device *dev = crtc->dev;
3848         struct drm_i915_private *dev_priv = to_i915(dev);
3849         int level, max_level = ilk_wm_max_level(dev_priv);
3850         enum pipe pipe = intel_crtc->pipe;
3851
3852         for (level = 0; level <= max_level; level++) {
3853                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
3854                                    &wm->wm[level]);
3855         }
3856         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
3857                            &wm->trans_wm);
3858
3859         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
3860                             &ddb->plane[pipe][plane_id]);
3861         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
3862                             &ddb->y_plane[pipe][plane_id]);
3863 }
3864
3865 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3866                                 const struct skl_plane_wm *wm,
3867                                 const struct skl_ddb_allocation *ddb)
3868 {
3869         struct drm_crtc *crtc = &intel_crtc->base;
3870         struct drm_device *dev = crtc->dev;
3871         struct drm_i915_private *dev_priv = to_i915(dev);
3872         int level, max_level = ilk_wm_max_level(dev_priv);
3873         enum pipe pipe = intel_crtc->pipe;
3874
3875         for (level = 0; level <= max_level; level++) {
3876                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3877                                    &wm->wm[level]);
3878         }
3879         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3880
3881         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3882                             &ddb->plane[pipe][PLANE_CURSOR]);
3883 }
3884
3885 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3886                          const struct skl_wm_level *l2)
3887 {
3888         if (l1->plane_en != l2->plane_en)
3889                 return false;
3890
3891         /* If both planes aren't enabled, the rest shouldn't matter */
3892         if (!l1->plane_en)
3893                 return true;
3894
3895         return (l1->plane_res_l == l2->plane_res_l &&
3896                 l1->plane_res_b == l2->plane_res_b);
3897 }
3898
3899 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3900                                            const struct skl_ddb_entry *b)
3901 {
3902         return a->start < b->end && b->start < a->end;
3903 }
3904
3905 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3906                                  const struct skl_ddb_entry *ddb,
3907                                  int ignore)
3908 {
3909         int i;
3910
3911         for (i = 0; i < I915_MAX_PIPES; i++)
3912                 if (i != ignore && entries[i] &&
3913                     skl_ddb_entries_overlap(ddb, entries[i]))
3914                         return true;
3915
3916         return false;
3917 }
3918
3919 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3920                               const struct skl_pipe_wm *old_pipe_wm,
3921                               struct skl_pipe_wm *pipe_wm, /* out */
3922                               struct skl_ddb_allocation *ddb, /* out */
3923                               bool *changed /* out */)
3924 {
3925         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3926         int ret;
3927
3928         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3929         if (ret)
3930                 return ret;
3931
3932         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3933                 *changed = false;
3934         else
3935                 *changed = true;
3936
3937         return 0;
3938 }
3939
3940 static uint32_t
3941 pipes_modified(struct drm_atomic_state *state)
3942 {
3943         struct drm_crtc *crtc;
3944         struct drm_crtc_state *cstate;
3945         uint32_t i, ret = 0;
3946
3947         for_each_crtc_in_state(state, crtc, cstate, i)
3948                 ret |= drm_crtc_mask(crtc);
3949
3950         return ret;
3951 }
3952
3953 static int
3954 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3955 {
3956         struct drm_atomic_state *state = cstate->base.state;
3957         struct drm_device *dev = state->dev;
3958         struct drm_crtc *crtc = cstate->base.crtc;
3959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3960         struct drm_i915_private *dev_priv = to_i915(dev);
3961         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3962         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3963         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3964         struct drm_plane_state *plane_state;
3965         struct drm_plane *plane;
3966         enum pipe pipe = intel_crtc->pipe;
3967
3968         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3969
3970         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3971                 enum plane_id plane_id = to_intel_plane(plane)->id;
3972
3973                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
3974                                         &new_ddb->plane[pipe][plane_id]) &&
3975                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
3976                                         &new_ddb->y_plane[pipe][plane_id]))
3977                         continue;
3978
3979                 plane_state = drm_atomic_get_plane_state(state, plane);
3980                 if (IS_ERR(plane_state))
3981                         return PTR_ERR(plane_state);
3982         }
3983
3984         return 0;
3985 }
3986
3987 static int
3988 skl_compute_ddb(struct drm_atomic_state *state)
3989 {
3990         struct drm_device *dev = state->dev;
3991         struct drm_i915_private *dev_priv = to_i915(dev);
3992         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3993         struct intel_crtc *intel_crtc;
3994         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3995         uint32_t realloc_pipes = pipes_modified(state);
3996         int ret;
3997
3998         /*
3999          * If this is our first atomic update following hardware readout,
4000          * we can't trust the DDB that the BIOS programmed for us.  Let's
4001          * pretend that all pipes switched active status so that we'll
4002          * ensure a full DDB recompute.
4003          */
4004         if (dev_priv->wm.distrust_bios_wm) {
4005                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4006                                        state->acquire_ctx);
4007                 if (ret)
4008                         return ret;
4009
4010                 intel_state->active_pipe_changes = ~0;
4011
4012                 /*
4013                  * We usually only initialize intel_state->active_crtcs if we
4014                  * we're doing a modeset; make sure this field is always
4015                  * initialized during the sanitization process that happens
4016                  * on the first commit too.
4017                  */
4018                 if (!intel_state->modeset)
4019                         intel_state->active_crtcs = dev_priv->active_crtcs;
4020         }
4021
4022         /*
4023          * If the modeset changes which CRTC's are active, we need to
4024          * recompute the DDB allocation for *all* active pipes, even
4025          * those that weren't otherwise being modified in any way by this
4026          * atomic commit.  Due to the shrinking of the per-pipe allocations
4027          * when new active CRTC's are added, it's possible for a pipe that
4028          * we were already using and aren't changing at all here to suddenly
4029          * become invalid if its DDB needs exceeds its new allocation.
4030          *
4031          * Note that if we wind up doing a full DDB recompute, we can't let
4032          * any other display updates race with this transaction, so we need
4033          * to grab the lock on *all* CRTC's.
4034          */
4035         if (intel_state->active_pipe_changes) {
4036                 realloc_pipes = ~0;
4037                 intel_state->wm_results.dirty_pipes = ~0;
4038         }
4039
4040         /*
4041          * We're not recomputing for the pipes not included in the commit, so
4042          * make sure we start with the current state.
4043          */
4044         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4045
4046         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4047                 struct intel_crtc_state *cstate;
4048
4049                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4050                 if (IS_ERR(cstate))
4051                         return PTR_ERR(cstate);
4052
4053                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4054                 if (ret)
4055                         return ret;
4056
4057                 ret = skl_ddb_add_affected_planes(cstate);
4058                 if (ret)
4059                         return ret;
4060         }
4061
4062         return 0;
4063 }
4064
4065 static void
4066 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4067                      struct skl_wm_values *src,
4068                      enum pipe pipe)
4069 {
4070         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4071                sizeof(dst->ddb.y_plane[pipe]));
4072         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4073                sizeof(dst->ddb.plane[pipe]));
4074 }
4075
4076 static void
4077 skl_print_wm_changes(const struct drm_atomic_state *state)
4078 {
4079         const struct drm_device *dev = state->dev;
4080         const struct drm_i915_private *dev_priv = to_i915(dev);
4081         const struct intel_atomic_state *intel_state =
4082                 to_intel_atomic_state(state);
4083         const struct drm_crtc *crtc;
4084         const struct drm_crtc_state *cstate;
4085         const struct intel_plane *intel_plane;
4086         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4087         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4088         int i;
4089
4090         for_each_crtc_in_state(state, crtc, cstate, i) {
4091                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4092                 enum pipe pipe = intel_crtc->pipe;
4093
4094                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4095                         enum plane_id plane_id = intel_plane->id;
4096                         const struct skl_ddb_entry *old, *new;
4097
4098                         old = &old_ddb->plane[pipe][plane_id];
4099                         new = &new_ddb->plane[pipe][plane_id];
4100
4101                         if (skl_ddb_entry_equal(old, new))
4102                                 continue;
4103
4104                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4105                                          intel_plane->base.base.id,
4106                                          intel_plane->base.name,
4107                                          old->start, old->end,
4108                                          new->start, new->end);
4109                 }
4110         }
4111 }
4112
4113 static int
4114 skl_compute_wm(struct drm_atomic_state *state)
4115 {
4116         struct drm_crtc *crtc;
4117         struct drm_crtc_state *cstate;
4118         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4119         struct skl_wm_values *results = &intel_state->wm_results;
4120         struct skl_pipe_wm *pipe_wm;
4121         bool changed = false;
4122         int ret, i;
4123
4124         /*
4125          * If this transaction isn't actually touching any CRTC's, don't
4126          * bother with watermark calculation.  Note that if we pass this
4127          * test, we're guaranteed to hold at least one CRTC state mutex,
4128          * which means we can safely use values like dev_priv->active_crtcs
4129          * since any racing commits that want to update them would need to
4130          * hold _all_ CRTC state mutexes.
4131          */
4132         for_each_crtc_in_state(state, crtc, cstate, i)
4133                 changed = true;
4134         if (!changed)
4135                 return 0;
4136
4137         /* Clear all dirty flags */
4138         results->dirty_pipes = 0;
4139
4140         ret = skl_compute_ddb(state);
4141         if (ret)
4142                 return ret;
4143
4144         /*
4145          * Calculate WM's for all pipes that are part of this transaction.
4146          * Note that the DDB allocation above may have added more CRTC's that
4147          * weren't otherwise being modified (and set bits in dirty_pipes) if
4148          * pipe allocations had to change.
4149          *
4150          * FIXME:  Now that we're doing this in the atomic check phase, we
4151          * should allow skl_update_pipe_wm() to return failure in cases where
4152          * no suitable watermark values can be found.
4153          */
4154         for_each_crtc_in_state(state, crtc, cstate, i) {
4155                 struct intel_crtc_state *intel_cstate =
4156                         to_intel_crtc_state(cstate);
4157                 const struct skl_pipe_wm *old_pipe_wm =
4158                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4159
4160                 pipe_wm = &intel_cstate->wm.skl.optimal;
4161                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4162                                          &results->ddb, &changed);
4163                 if (ret)
4164                         return ret;
4165
4166                 if (changed)
4167                         results->dirty_pipes |= drm_crtc_mask(crtc);
4168
4169                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4170                         /* This pipe's WM's did not change */
4171                         continue;
4172
4173                 intel_cstate->update_wm_pre = true;
4174         }
4175
4176         skl_print_wm_changes(state);
4177
4178         return 0;
4179 }
4180
4181 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4182                                       struct intel_crtc_state *cstate)
4183 {
4184         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4185         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4186         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4187         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
4188         enum pipe pipe = crtc->pipe;
4189         enum plane_id plane_id;
4190
4191         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4192                 return;
4193
4194         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4195
4196         for_each_plane_id_on_crtc(crtc, plane_id) {
4197                 if (plane_id != PLANE_CURSOR)
4198                         skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
4199                                            ddb, plane_id);
4200                 else
4201                         skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
4202                                             ddb);
4203         }
4204 }
4205
4206 static void skl_initial_wm(struct intel_atomic_state *state,
4207                            struct intel_crtc_state *cstate)
4208 {
4209         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4210         struct drm_device *dev = intel_crtc->base.dev;
4211         struct drm_i915_private *dev_priv = to_i915(dev);
4212         struct skl_wm_values *results = &state->wm_results;
4213         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4214         enum pipe pipe = intel_crtc->pipe;
4215
4216         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4217                 return;
4218
4219         mutex_lock(&dev_priv->wm.wm_mutex);
4220
4221         if (cstate->base.active_changed)
4222                 skl_atomic_update_crtc_wm(state, cstate);
4223
4224         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4225
4226         mutex_unlock(&dev_priv->wm.wm_mutex);
4227 }
4228
4229 static void ilk_compute_wm_config(struct drm_device *dev,
4230                                   struct intel_wm_config *config)
4231 {
4232         struct intel_crtc *crtc;
4233
4234         /* Compute the currently _active_ config */
4235         for_each_intel_crtc(dev, crtc) {
4236                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4237
4238                 if (!wm->pipe_enabled)
4239                         continue;
4240
4241                 config->sprites_enabled |= wm->sprites_enabled;
4242                 config->sprites_scaled |= wm->sprites_scaled;
4243                 config->num_pipes_active++;
4244         }
4245 }
4246
4247 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4248 {
4249         struct drm_device *dev = &dev_priv->drm;
4250         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4251         struct ilk_wm_maximums max;
4252         struct intel_wm_config config = {};
4253         struct ilk_wm_values results = {};
4254         enum intel_ddb_partitioning partitioning;
4255
4256         ilk_compute_wm_config(dev, &config);
4257
4258         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4259         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4260
4261         /* 5/6 split only in single pipe config on IVB+ */
4262         if (INTEL_GEN(dev_priv) >= 7 &&
4263             config.num_pipes_active == 1 && config.sprites_enabled) {
4264                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4265                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4266
4267                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4268         } else {
4269                 best_lp_wm = &lp_wm_1_2;
4270         }
4271
4272         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4273                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4274
4275         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4276
4277         ilk_write_wm_values(dev_priv, &results);
4278 }
4279
4280 static void ilk_initial_watermarks(struct intel_atomic_state *state,
4281                                    struct intel_crtc_state *cstate)
4282 {
4283         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4284         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4285
4286         mutex_lock(&dev_priv->wm.wm_mutex);
4287         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4288         ilk_program_watermarks(dev_priv);
4289         mutex_unlock(&dev_priv->wm.wm_mutex);
4290 }
4291
4292 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4293                                     struct intel_crtc_state *cstate)
4294 {
4295         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4296         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4297
4298         mutex_lock(&dev_priv->wm.wm_mutex);
4299         if (cstate->wm.need_postvbl_update) {
4300                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4301                 ilk_program_watermarks(dev_priv);
4302         }
4303         mutex_unlock(&dev_priv->wm.wm_mutex);
4304 }
4305
4306 static inline void skl_wm_level_from_reg_val(uint32_t val,
4307                                              struct skl_wm_level *level)
4308 {
4309         level->plane_en = val & PLANE_WM_EN;
4310         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4311         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4312                 PLANE_WM_LINES_MASK;
4313 }
4314
4315 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4316                               struct skl_pipe_wm *out)
4317 {
4318         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4320         enum pipe pipe = intel_crtc->pipe;
4321         int level, max_level;
4322         enum plane_id plane_id;
4323         uint32_t val;
4324
4325         max_level = ilk_wm_max_level(dev_priv);
4326
4327         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4328                 struct skl_plane_wm *wm = &out->planes[plane_id];
4329
4330                 for (level = 0; level <= max_level; level++) {
4331                         if (plane_id != PLANE_CURSOR)
4332                                 val = I915_READ(PLANE_WM(pipe, plane_id, level));
4333                         else
4334                                 val = I915_READ(CUR_WM(pipe, level));
4335
4336                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
4337                 }
4338
4339                 if (plane_id != PLANE_CURSOR)
4340                         val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
4341                 else
4342                         val = I915_READ(CUR_WM_TRANS(pipe));
4343
4344                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4345         }
4346
4347         if (!intel_crtc->active)
4348                 return;
4349
4350         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4351 }
4352
4353 void skl_wm_get_hw_state(struct drm_device *dev)
4354 {
4355         struct drm_i915_private *dev_priv = to_i915(dev);
4356         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4357         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4358         struct drm_crtc *crtc;
4359         struct intel_crtc *intel_crtc;
4360         struct intel_crtc_state *cstate;
4361
4362         skl_ddb_get_hw_state(dev_priv, ddb);
4363         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4364                 intel_crtc = to_intel_crtc(crtc);
4365                 cstate = to_intel_crtc_state(crtc->state);
4366
4367                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4368
4369                 if (intel_crtc->active)
4370                         hw->dirty_pipes |= drm_crtc_mask(crtc);
4371         }
4372
4373         if (dev_priv->active_crtcs) {
4374                 /* Fully recompute DDB on first atomic commit */
4375                 dev_priv->wm.distrust_bios_wm = true;
4376         } else {
4377                 /* Easy/common case; just sanitize DDB now if everything off */
4378                 memset(ddb, 0, sizeof(*ddb));
4379         }
4380 }
4381
4382 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4383 {
4384         struct drm_device *dev = crtc->dev;
4385         struct drm_i915_private *dev_priv = to_i915(dev);
4386         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4388         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4389         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4390         enum pipe pipe = intel_crtc->pipe;
4391         static const i915_reg_t wm0_pipe_reg[] = {
4392                 [PIPE_A] = WM0_PIPEA_ILK,
4393                 [PIPE_B] = WM0_PIPEB_ILK,
4394                 [PIPE_C] = WM0_PIPEC_IVB,
4395         };
4396
4397         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4398         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4399                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4400
4401         memset(active, 0, sizeof(*active));
4402
4403         active->pipe_enabled = intel_crtc->active;
4404
4405         if (active->pipe_enabled) {
4406                 u32 tmp = hw->wm_pipe[pipe];
4407
4408                 /*
4409                  * For active pipes LP0 watermark is marked as
4410                  * enabled, and LP1+ watermaks as disabled since
4411                  * we can't really reverse compute them in case
4412                  * multiple pipes are active.
4413                  */
4414                 active->wm[0].enable = true;
4415                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4416                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4417                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4418                 active->linetime = hw->wm_linetime[pipe];
4419         } else {
4420                 int level, max_level = ilk_wm_max_level(dev_priv);
4421
4422                 /*
4423                  * For inactive pipes, all watermark levels
4424                  * should be marked as enabled but zeroed,
4425                  * which is what we'd compute them to.
4426                  */
4427                 for (level = 0; level <= max_level; level++)
4428                         active->wm[level].enable = true;
4429         }
4430
4431         intel_crtc->wm.active.ilk = *active;
4432 }
4433
4434 #define _FW_WM(value, plane) \
4435         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4436 #define _FW_WM_VLV(value, plane) \
4437         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4438
4439 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4440                                struct vlv_wm_values *wm)
4441 {
4442         enum pipe pipe;
4443         uint32_t tmp;
4444
4445         for_each_pipe(dev_priv, pipe) {
4446                 tmp = I915_READ(VLV_DDL(pipe));
4447
4448                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
4449                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4450                 wm->ddl[pipe].plane[PLANE_CURSOR] =
4451                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4452                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
4453                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4454                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
4455                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4456         }
4457
4458         tmp = I915_READ(DSPFW1);
4459         wm->sr.plane = _FW_WM(tmp, SR);
4460         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
4461         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
4462         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
4463
4464         tmp = I915_READ(DSPFW2);
4465         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
4466         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
4467         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
4468
4469         tmp = I915_READ(DSPFW3);
4470         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4471
4472         if (IS_CHERRYVIEW(dev_priv)) {
4473                 tmp = I915_READ(DSPFW7_CHV);
4474                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4475                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4476
4477                 tmp = I915_READ(DSPFW8_CHV);
4478                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
4479                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
4480
4481                 tmp = I915_READ(DSPFW9_CHV);
4482                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
4483                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
4484
4485                 tmp = I915_READ(DSPHOWM);
4486                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4487                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4488                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4489                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
4490                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4491                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4492                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4493                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4494                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4495                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4496         } else {
4497                 tmp = I915_READ(DSPFW7);
4498                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4499                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4500
4501                 tmp = I915_READ(DSPHOWM);
4502                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4503                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4504                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4505                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4506                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4507                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4508                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4509         }
4510 }
4511
4512 #undef _FW_WM
4513 #undef _FW_WM_VLV
4514
4515 void vlv_wm_get_hw_state(struct drm_device *dev)
4516 {
4517         struct drm_i915_private *dev_priv = to_i915(dev);
4518         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4519         struct intel_crtc *crtc;
4520         enum pipe pipe;
4521         u32 val;
4522
4523         vlv_read_wm_values(dev_priv, wm);
4524
4525         for_each_intel_crtc(dev, crtc)
4526                 vlv_get_fifo_size(to_intel_crtc_state(crtc->base.state));
4527
4528         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4529         wm->level = VLV_WM_LEVEL_PM2;
4530
4531         if (IS_CHERRYVIEW(dev_priv)) {
4532                 mutex_lock(&dev_priv->rps.hw_lock);
4533
4534                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4535                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4536                         wm->level = VLV_WM_LEVEL_PM5;
4537
4538                 /*
4539                  * If DDR DVFS is disabled in the BIOS, Punit
4540                  * will never ack the request. So if that happens
4541                  * assume we don't have to enable/disable DDR DVFS
4542                  * dynamically. To test that just set the REQ_ACK
4543                  * bit to poke the Punit, but don't change the
4544                  * HIGH/LOW bits so that we don't actually change
4545                  * the current state.
4546                  */
4547                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4548                 val |= FORCE_DDR_FREQ_REQ_ACK;
4549                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4550
4551                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4552                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4553                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4554                                       "assuming DDR DVFS is disabled\n");
4555                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4556                 } else {
4557                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4558                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4559                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4560                 }
4561
4562                 mutex_unlock(&dev_priv->rps.hw_lock);
4563         }
4564
4565         for_each_pipe(dev_priv, pipe)
4566                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4567                               pipe_name(pipe),
4568                               wm->pipe[pipe].plane[PLANE_PRIMARY],
4569                               wm->pipe[pipe].plane[PLANE_CURSOR],
4570                               wm->pipe[pipe].plane[PLANE_SPRITE0],
4571                               wm->pipe[pipe].plane[PLANE_SPRITE1]);
4572
4573         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4574                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4575 }
4576
4577 void ilk_wm_get_hw_state(struct drm_device *dev)
4578 {
4579         struct drm_i915_private *dev_priv = to_i915(dev);
4580         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4581         struct drm_crtc *crtc;
4582
4583         for_each_crtc(dev, crtc)
4584                 ilk_pipe_wm_get_hw_state(crtc);
4585
4586         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4587         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4588         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4589
4590         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4591         if (INTEL_GEN(dev_priv) >= 7) {
4592                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4593                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4594         }
4595
4596         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4597                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4598                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4599         else if (IS_IVYBRIDGE(dev_priv))
4600                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4601                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4602
4603         hw->enable_fbc_wm =
4604                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4605 }
4606
4607 /**
4608  * intel_update_watermarks - update FIFO watermark values based on current modes
4609  *
4610  * Calculate watermark values for the various WM regs based on current mode
4611  * and plane configuration.
4612  *
4613  * There are several cases to deal with here:
4614  *   - normal (i.e. non-self-refresh)
4615  *   - self-refresh (SR) mode
4616  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4617  *   - lines are small relative to FIFO size (buffer can hold more than 2
4618  *     lines), so need to account for TLB latency
4619  *
4620  *   The normal calculation is:
4621  *     watermark = dotclock * bytes per pixel * latency
4622  *   where latency is platform & configuration dependent (we assume pessimal
4623  *   values here).
4624  *
4625  *   The SR calculation is:
4626  *     watermark = (trunc(latency/line time)+1) * surface width *
4627  *       bytes per pixel
4628  *   where
4629  *     line time = htotal / dotclock
4630  *     surface width = hdisplay for normal plane and 64 for cursor
4631  *   and latency is assumed to be high, as above.
4632  *
4633  * The final value programmed to the register should always be rounded up,
4634  * and include an extra 2 entries to account for clock crossings.
4635  *
4636  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4637  * to set the non-SR watermarks to 8.
4638  */
4639 void intel_update_watermarks(struct intel_crtc *crtc)
4640 {
4641         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4642
4643         if (dev_priv->display.update_wm)
4644                 dev_priv->display.update_wm(crtc);
4645 }
4646
4647 /*
4648  * Lock protecting IPS related data structures
4649  */
4650 DEFINE_SPINLOCK(mchdev_lock);
4651
4652 /* Global for IPS driver to get at the current i915 device. Protected by
4653  * mchdev_lock. */
4654 static struct drm_i915_private *i915_mch_dev;
4655
4656 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4657 {
4658         u16 rgvswctl;
4659
4660         lockdep_assert_held(&mchdev_lock);
4661
4662         rgvswctl = I915_READ16(MEMSWCTL);
4663         if (rgvswctl & MEMCTL_CMD_STS) {
4664                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4665                 return false; /* still busy with another command */
4666         }
4667
4668         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4669                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4670         I915_WRITE16(MEMSWCTL, rgvswctl);
4671         POSTING_READ16(MEMSWCTL);
4672
4673         rgvswctl |= MEMCTL_CMD_STS;
4674         I915_WRITE16(MEMSWCTL, rgvswctl);
4675
4676         return true;
4677 }
4678
4679 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4680 {
4681         u32 rgvmodectl;
4682         u8 fmax, fmin, fstart, vstart;
4683
4684         spin_lock_irq(&mchdev_lock);
4685
4686         rgvmodectl = I915_READ(MEMMODECTL);
4687
4688         /* Enable temp reporting */
4689         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4690         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4691
4692         /* 100ms RC evaluation intervals */
4693         I915_WRITE(RCUPEI, 100000);
4694         I915_WRITE(RCDNEI, 100000);
4695
4696         /* Set max/min thresholds to 90ms and 80ms respectively */
4697         I915_WRITE(RCBMAXAVG, 90000);
4698         I915_WRITE(RCBMINAVG, 80000);
4699
4700         I915_WRITE(MEMIHYST, 1);
4701
4702         /* Set up min, max, and cur for interrupt handling */
4703         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4704         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4705         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4706                 MEMMODE_FSTART_SHIFT;
4707
4708         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4709                 PXVFREQ_PX_SHIFT;
4710
4711         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4712         dev_priv->ips.fstart = fstart;
4713
4714         dev_priv->ips.max_delay = fstart;
4715         dev_priv->ips.min_delay = fmin;
4716         dev_priv->ips.cur_delay = fstart;
4717
4718         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4719                          fmax, fmin, fstart);
4720
4721         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4722
4723         /*
4724          * Interrupts will be enabled in ironlake_irq_postinstall
4725          */
4726
4727         I915_WRITE(VIDSTART, vstart);
4728         POSTING_READ(VIDSTART);
4729
4730         rgvmodectl |= MEMMODE_SWMODE_EN;
4731         I915_WRITE(MEMMODECTL, rgvmodectl);
4732
4733         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4734                 DRM_ERROR("stuck trying to change perf mode\n");
4735         mdelay(1);
4736
4737         ironlake_set_drps(dev_priv, fstart);
4738
4739         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4740                 I915_READ(DDREC) + I915_READ(CSIEC);
4741         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4742         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4743         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4744
4745         spin_unlock_irq(&mchdev_lock);
4746 }
4747
4748 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4749 {
4750         u16 rgvswctl;
4751
4752         spin_lock_irq(&mchdev_lock);
4753
4754         rgvswctl = I915_READ16(MEMSWCTL);
4755
4756         /* Ack interrupts, disable EFC interrupt */
4757         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4758         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4759         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4760         I915_WRITE(DEIIR, DE_PCU_EVENT);
4761         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4762
4763         /* Go back to the starting frequency */
4764         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4765         mdelay(1);
4766         rgvswctl |= MEMCTL_CMD_STS;
4767         I915_WRITE(MEMSWCTL, rgvswctl);
4768         mdelay(1);
4769
4770         spin_unlock_irq(&mchdev_lock);
4771 }
4772
4773 /* There's a funny hw issue where the hw returns all 0 when reading from
4774  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4775  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4776  * all limits and the gpu stuck at whatever frequency it is at atm).
4777  */
4778 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4779 {
4780         u32 limits;
4781
4782         /* Only set the down limit when we've reached the lowest level to avoid
4783          * getting more interrupts, otherwise leave this clear. This prevents a
4784          * race in the hw when coming out of rc6: There's a tiny window where
4785          * the hw runs at the minimal clock before selecting the desired
4786          * frequency, if the down threshold expires in that window we will not
4787          * receive a down interrupt. */
4788         if (IS_GEN9(dev_priv)) {
4789                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4790                 if (val <= dev_priv->rps.min_freq_softlimit)
4791                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4792         } else {
4793                 limits = dev_priv->rps.max_freq_softlimit << 24;
4794                 if (val <= dev_priv->rps.min_freq_softlimit)
4795                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4796         }
4797
4798         return limits;
4799 }
4800
4801 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4802 {
4803         int new_power;
4804         u32 threshold_up = 0, threshold_down = 0; /* in % */
4805         u32 ei_up = 0, ei_down = 0;
4806
4807         new_power = dev_priv->rps.power;
4808         switch (dev_priv->rps.power) {
4809         case LOW_POWER:
4810                 if (val > dev_priv->rps.efficient_freq + 1 &&
4811                     val > dev_priv->rps.cur_freq)
4812                         new_power = BETWEEN;
4813                 break;
4814
4815         case BETWEEN:
4816                 if (val <= dev_priv->rps.efficient_freq &&
4817                     val < dev_priv->rps.cur_freq)
4818                         new_power = LOW_POWER;
4819                 else if (val >= dev_priv->rps.rp0_freq &&
4820                          val > dev_priv->rps.cur_freq)
4821                         new_power = HIGH_POWER;
4822                 break;
4823
4824         case HIGH_POWER:
4825                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4826                     val < dev_priv->rps.cur_freq)
4827                         new_power = BETWEEN;
4828                 break;
4829         }
4830         /* Max/min bins are special */
4831         if (val <= dev_priv->rps.min_freq_softlimit)
4832                 new_power = LOW_POWER;
4833         if (val >= dev_priv->rps.max_freq_softlimit)
4834                 new_power = HIGH_POWER;
4835         if (new_power == dev_priv->rps.power)
4836                 return;
4837
4838         /* Note the units here are not exactly 1us, but 1280ns. */
4839         switch (new_power) {
4840         case LOW_POWER:
4841                 /* Upclock if more than 95% busy over 16ms */
4842                 ei_up = 16000;
4843                 threshold_up = 95;
4844
4845                 /* Downclock if less than 85% busy over 32ms */
4846                 ei_down = 32000;
4847                 threshold_down = 85;
4848                 break;
4849
4850         case BETWEEN:
4851                 /* Upclock if more than 90% busy over 13ms */
4852                 ei_up = 13000;
4853                 threshold_up = 90;
4854
4855                 /* Downclock if less than 75% busy over 32ms */
4856                 ei_down = 32000;
4857                 threshold_down = 75;
4858                 break;
4859
4860         case HIGH_POWER:
4861                 /* Upclock if more than 85% busy over 10ms */
4862                 ei_up = 10000;
4863                 threshold_up = 85;
4864
4865                 /* Downclock if less than 60% busy over 32ms */
4866                 ei_down = 32000;
4867                 threshold_down = 60;
4868                 break;
4869         }
4870
4871         /* When byt can survive without system hang with dynamic
4872          * sw freq adjustments, this restriction can be lifted.
4873          */
4874         if (IS_VALLEYVIEW(dev_priv))
4875                 goto skip_hw_write;
4876
4877         I915_WRITE(GEN6_RP_UP_EI,
4878                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4879         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4880                    GT_INTERVAL_FROM_US(dev_priv,
4881                                        ei_up * threshold_up / 100));
4882
4883         I915_WRITE(GEN6_RP_DOWN_EI,
4884                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4885         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4886                    GT_INTERVAL_FROM_US(dev_priv,
4887                                        ei_down * threshold_down / 100));
4888
4889         I915_WRITE(GEN6_RP_CONTROL,
4890                    GEN6_RP_MEDIA_TURBO |
4891                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4892                    GEN6_RP_MEDIA_IS_GFX |
4893                    GEN6_RP_ENABLE |
4894                    GEN6_RP_UP_BUSY_AVG |
4895                    GEN6_RP_DOWN_IDLE_AVG);
4896
4897 skip_hw_write:
4898         dev_priv->rps.power = new_power;
4899         dev_priv->rps.up_threshold = threshold_up;
4900         dev_priv->rps.down_threshold = threshold_down;
4901         dev_priv->rps.last_adj = 0;
4902 }
4903
4904 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4905 {
4906         u32 mask = 0;
4907
4908         if (val > dev_priv->rps.min_freq_softlimit)
4909                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4910         if (val < dev_priv->rps.max_freq_softlimit)
4911                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4912
4913         mask &= dev_priv->pm_rps_events;
4914
4915         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4916 }
4917
4918 /* gen6_set_rps is called to update the frequency request, but should also be
4919  * called when the range (min_delay and max_delay) is modified so that we can
4920  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4921 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4922 {
4923         /* min/max delay may still have been modified so be sure to
4924          * write the limits value.
4925          */
4926         if (val != dev_priv->rps.cur_freq) {
4927                 gen6_set_rps_thresholds(dev_priv, val);
4928
4929                 if (IS_GEN9(dev_priv))
4930                         I915_WRITE(GEN6_RPNSWREQ,
4931                                    GEN9_FREQUENCY(val));
4932                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4933                         I915_WRITE(GEN6_RPNSWREQ,
4934                                    HSW_FREQUENCY(val));
4935                 else
4936                         I915_WRITE(GEN6_RPNSWREQ,
4937                                    GEN6_FREQUENCY(val) |
4938                                    GEN6_OFFSET(0) |
4939                                    GEN6_AGGRESSIVE_TURBO);
4940         }
4941
4942         /* Make sure we continue to get interrupts
4943          * until we hit the minimum or maximum frequencies.
4944          */
4945         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4946         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4947
4948         dev_priv->rps.cur_freq = val;
4949         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4950
4951         return 0;
4952 }
4953
4954 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4955 {
4956         int err;
4957
4958         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4959                       "Odd GPU freq value\n"))
4960                 val &= ~1;
4961
4962         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4963
4964         if (val != dev_priv->rps.cur_freq) {
4965                 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4966                 if (err)
4967                         return err;
4968
4969                 gen6_set_rps_thresholds(dev_priv, val);
4970         }
4971
4972         dev_priv->rps.cur_freq = val;
4973         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4974
4975         return 0;
4976 }
4977
4978 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4979  *
4980  * * If Gfx is Idle, then
4981  * 1. Forcewake Media well.
4982  * 2. Request idle freq.
4983  * 3. Release Forcewake of Media well.
4984 */
4985 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4986 {
4987         u32 val = dev_priv->rps.idle_freq;
4988         int err;
4989
4990         if (dev_priv->rps.cur_freq <= val)
4991                 return;
4992
4993         /* The punit delays the write of the frequency and voltage until it
4994          * determines the GPU is awake. During normal usage we don't want to
4995          * waste power changing the frequency if the GPU is sleeping (rc6).
4996          * However, the GPU and driver is now idle and we do not want to delay
4997          * switching to minimum voltage (reducing power whilst idle) as we do
4998          * not expect to be woken in the near future and so must flush the
4999          * change by waking the device.
5000          *
5001          * We choose to take the media powerwell (either would do to trick the
5002          * punit into committing the voltage change) as that takes a lot less
5003          * power than the render powerwell.
5004          */
5005         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5006         err = valleyview_set_rps(dev_priv, val);
5007         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5008
5009         if (err)
5010                 DRM_ERROR("Failed to set RPS for idle\n");
5011 }
5012
5013 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5014 {
5015         mutex_lock(&dev_priv->rps.hw_lock);
5016         if (dev_priv->rps.enabled) {
5017                 u8 freq;
5018
5019                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5020                         gen6_rps_reset_ei(dev_priv);
5021                 I915_WRITE(GEN6_PMINTRMSK,
5022                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5023
5024                 gen6_enable_rps_interrupts(dev_priv);
5025
5026                 /* Use the user's desired frequency as a guide, but for better
5027                  * performance, jump directly to RPe as our starting frequency.
5028                  */
5029                 freq = max(dev_priv->rps.cur_freq,
5030                            dev_priv->rps.efficient_freq);
5031
5032                 if (intel_set_rps(dev_priv,
5033                                   clamp(freq,
5034                                         dev_priv->rps.min_freq_softlimit,
5035                                         dev_priv->rps.max_freq_softlimit)))
5036                         DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
5037         }
5038         mutex_unlock(&dev_priv->rps.hw_lock);
5039 }
5040
5041 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5042 {
5043         /* Flush our bottom-half so that it does not race with us
5044          * setting the idle frequency and so that it is bounded by
5045          * our rpm wakeref. And then disable the interrupts to stop any
5046          * futher RPS reclocking whilst we are asleep.
5047          */
5048         gen6_disable_rps_interrupts(dev_priv);
5049
5050         mutex_lock(&dev_priv->rps.hw_lock);
5051         if (dev_priv->rps.enabled) {
5052                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5053                         vlv_set_rps_idle(dev_priv);
5054                 else
5055                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5056                 dev_priv->rps.last_adj = 0;
5057                 I915_WRITE(GEN6_PMINTRMSK,
5058                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5059         }
5060         mutex_unlock(&dev_priv->rps.hw_lock);
5061
5062         spin_lock(&dev_priv->rps.client_lock);
5063         while (!list_empty(&dev_priv->rps.clients))
5064                 list_del_init(dev_priv->rps.clients.next);
5065         spin_unlock(&dev_priv->rps.client_lock);
5066 }
5067
5068 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5069                     struct intel_rps_client *rps,
5070                     unsigned long submitted)
5071 {
5072         /* This is intentionally racy! We peek at the state here, then
5073          * validate inside the RPS worker.
5074          */
5075         if (!(dev_priv->gt.awake &&
5076               dev_priv->rps.enabled &&
5077               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5078                 return;
5079
5080         /* Force a RPS boost (and don't count it against the client) if
5081          * the GPU is severely congested.
5082          */
5083         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5084                 rps = NULL;
5085
5086         spin_lock(&dev_priv->rps.client_lock);
5087         if (rps == NULL || list_empty(&rps->link)) {
5088                 spin_lock_irq(&dev_priv->irq_lock);
5089                 if (dev_priv->rps.interrupts_enabled) {
5090                         dev_priv->rps.client_boost = true;
5091                         schedule_work(&dev_priv->rps.work);
5092                 }
5093                 spin_unlock_irq(&dev_priv->irq_lock);
5094
5095                 if (rps != NULL) {
5096                         list_add(&rps->link, &dev_priv->rps.clients);
5097                         rps->boosts++;
5098                 } else
5099                         dev_priv->rps.boosts++;
5100         }
5101         spin_unlock(&dev_priv->rps.client_lock);
5102 }
5103
5104 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5105 {
5106         int err;
5107
5108         lockdep_assert_held(&dev_priv->rps.hw_lock);
5109         GEM_BUG_ON(val > dev_priv->rps.max_freq);
5110         GEM_BUG_ON(val < dev_priv->rps.min_freq);
5111
5112         if (!dev_priv->rps.enabled) {
5113                 dev_priv->rps.cur_freq = val;
5114                 return 0;
5115         }
5116
5117         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5118                 err = valleyview_set_rps(dev_priv, val);
5119         else
5120                 err = gen6_set_rps(dev_priv, val);
5121
5122         return err;
5123 }
5124
5125 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5126 {
5127         I915_WRITE(GEN6_RC_CONTROL, 0);
5128         I915_WRITE(GEN9_PG_ENABLE, 0);
5129 }
5130
5131 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5132 {
5133         I915_WRITE(GEN6_RP_CONTROL, 0);
5134 }
5135
5136 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5137 {
5138         I915_WRITE(GEN6_RC_CONTROL, 0);
5139         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5140         I915_WRITE(GEN6_RP_CONTROL, 0);
5141 }
5142
5143 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5144 {
5145         I915_WRITE(GEN6_RC_CONTROL, 0);
5146 }
5147
5148 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5149 {
5150         /* we're doing forcewake before Disabling RC6,
5151          * This what the BIOS expects when going into suspend */
5152         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5153
5154         I915_WRITE(GEN6_RC_CONTROL, 0);
5155
5156         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5157 }
5158
5159 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5160 {
5161         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5162                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5163                         mode = GEN6_RC_CTL_RC6_ENABLE;
5164                 else
5165                         mode = 0;
5166         }
5167         if (HAS_RC6p(dev_priv))
5168                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5169                                  "RC6 %s RC6p %s RC6pp %s\n",
5170                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5171                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5172                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5173
5174         else
5175                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5176                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5177 }
5178
5179 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5180 {
5181         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5182         bool enable_rc6 = true;
5183         unsigned long rc6_ctx_base;
5184         u32 rc_ctl;
5185         int rc_sw_target;
5186
5187         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5188         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5189                        RC_SW_TARGET_STATE_SHIFT;
5190         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5191                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5192                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5193                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5194                          rc_sw_target);
5195
5196         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5197                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5198                 enable_rc6 = false;
5199         }
5200
5201         /*
5202          * The exact context size is not known for BXT, so assume a page size
5203          * for this check.
5204          */
5205         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5206         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5207               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5208                                         ggtt->stolen_reserved_size))) {
5209                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5210                 enable_rc6 = false;
5211         }
5212
5213         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5214               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5215               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5216               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5217                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5218                 enable_rc6 = false;
5219         }
5220
5221         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5222             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5223             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5224                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5225                 enable_rc6 = false;
5226         }
5227
5228         if (!I915_READ(GEN6_GFXPAUSE)) {
5229                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5230                 enable_rc6 = false;
5231         }
5232
5233         if (!I915_READ(GEN8_MISC_CTRL0)) {
5234                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5235                 enable_rc6 = false;
5236         }
5237
5238         return enable_rc6;
5239 }
5240
5241 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5242 {
5243         /* No RC6 before Ironlake and code is gone for ilk. */
5244         if (INTEL_INFO(dev_priv)->gen < 6)
5245                 return 0;
5246
5247         if (!enable_rc6)
5248                 return 0;
5249
5250         if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5251                 DRM_INFO("RC6 disabled by BIOS\n");
5252                 return 0;
5253         }
5254
5255         /* Respect the kernel parameter if it is set */
5256         if (enable_rc6 >= 0) {
5257                 int mask;
5258
5259                 if (HAS_RC6p(dev_priv))
5260                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5261                                INTEL_RC6pp_ENABLE;
5262                 else
5263                         mask = INTEL_RC6_ENABLE;
5264
5265                 if ((enable_rc6 & mask) != enable_rc6)
5266                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5267                                          "(requested %d, valid %d)\n",
5268                                          enable_rc6 & mask, enable_rc6, mask);
5269
5270                 return enable_rc6 & mask;
5271         }
5272
5273         if (IS_IVYBRIDGE(dev_priv))
5274                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5275
5276         return INTEL_RC6_ENABLE;
5277 }
5278
5279 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5280 {
5281         /* All of these values are in units of 50MHz */
5282
5283         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5284         if (IS_GEN9_LP(dev_priv)) {
5285                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5286                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5287                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5288                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5289         } else {
5290                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5291                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5292                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5293                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5294         }
5295         /* hw_max = RP0 until we check for overclocking */
5296         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5297
5298         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5299         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5300             IS_GEN9_BC(dev_priv)) {
5301                 u32 ddcc_status = 0;
5302
5303                 if (sandybridge_pcode_read(dev_priv,
5304                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5305                                            &ddcc_status) == 0)
5306                         dev_priv->rps.efficient_freq =
5307                                 clamp_t(u8,
5308                                         ((ddcc_status >> 8) & 0xff),
5309                                         dev_priv->rps.min_freq,
5310                                         dev_priv->rps.max_freq);
5311         }
5312
5313         if (IS_GEN9_BC(dev_priv)) {
5314                 /* Store the frequency values in 16.66 MHZ units, which is
5315                  * the natural hardware unit for SKL
5316                  */
5317                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5318                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5319                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5320                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5321                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5322         }
5323 }
5324
5325 static void reset_rps(struct drm_i915_private *dev_priv,
5326                       int (*set)(struct drm_i915_private *, u8))
5327 {
5328         u8 freq = dev_priv->rps.cur_freq;
5329
5330         /* force a reset */
5331         dev_priv->rps.power = -1;
5332         dev_priv->rps.cur_freq = -1;
5333
5334         if (set(dev_priv, freq))
5335                 DRM_ERROR("Failed to reset RPS to initial values\n");
5336 }
5337
5338 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5339 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5340 {
5341         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5342
5343         /* Program defaults and thresholds for RPS*/
5344         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5345                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5346
5347         /* 1 second timeout*/
5348         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5349                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5350
5351         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5352
5353         /* Leaning on the below call to gen6_set_rps to program/setup the
5354          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5355          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5356         reset_rps(dev_priv, gen6_set_rps);
5357
5358         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5359 }
5360
5361 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5362 {
5363         struct intel_engine_cs *engine;
5364         enum intel_engine_id id;
5365         uint32_t rc6_mask = 0;
5366
5367         /* 1a: Software RC state - RC0 */
5368         I915_WRITE(GEN6_RC_STATE, 0);
5369
5370         /* 1b: Get forcewake during program sequence. Although the driver
5371          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5372         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5373
5374         /* 2a: Disable RC states. */
5375         I915_WRITE(GEN6_RC_CONTROL, 0);
5376
5377         /* 2b: Program RC6 thresholds.*/
5378
5379         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5380         if (IS_SKYLAKE(dev_priv))
5381                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5382         else
5383                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5384         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5385         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5386         for_each_engine(engine, dev_priv, id)
5387                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5388
5389         if (HAS_GUC(dev_priv))
5390                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5391
5392         I915_WRITE(GEN6_RC_SLEEP, 0);
5393
5394         /* 2c: Program Coarse Power Gating Policies. */
5395         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5396         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5397
5398         /* 3a: Enable RC6 */
5399         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5400                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5401         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5402         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5403         I915_WRITE(GEN6_RC_CONTROL,
5404                    GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
5405
5406         /*
5407          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5408          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5409          */
5410         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5411                 I915_WRITE(GEN9_PG_ENABLE, 0);
5412         else
5413                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5414                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5415
5416         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5417 }
5418
5419 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5420 {
5421         struct intel_engine_cs *engine;
5422         enum intel_engine_id id;
5423         uint32_t rc6_mask = 0;
5424
5425         /* 1a: Software RC state - RC0 */
5426         I915_WRITE(GEN6_RC_STATE, 0);
5427
5428         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5429          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5430         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5431
5432         /* 2a: Disable RC states. */
5433         I915_WRITE(GEN6_RC_CONTROL, 0);
5434
5435         /* 2b: Program RC6 thresholds.*/
5436         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5437         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5438         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5439         for_each_engine(engine, dev_priv, id)
5440                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5441         I915_WRITE(GEN6_RC_SLEEP, 0);
5442         if (IS_BROADWELL(dev_priv))
5443                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5444         else
5445                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5446
5447         /* 3: Enable RC6 */
5448         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5449                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5450         intel_print_rc6_info(dev_priv, rc6_mask);
5451         if (IS_BROADWELL(dev_priv))
5452                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5453                                 GEN7_RC_CTL_TO_MODE |
5454                                 rc6_mask);
5455         else
5456                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5457                                 GEN6_RC_CTL_EI_MODE(1) |
5458                                 rc6_mask);
5459
5460         /* 4 Program defaults and thresholds for RPS*/
5461         I915_WRITE(GEN6_RPNSWREQ,
5462                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5463         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5464                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5465         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5466         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5467
5468         /* Docs recommend 900MHz, and 300 MHz respectively */
5469         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5470                    dev_priv->rps.max_freq_softlimit << 24 |
5471                    dev_priv->rps.min_freq_softlimit << 16);
5472
5473         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5474         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5475         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5476         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5477
5478         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5479
5480         /* 5: Enable RPS */
5481         I915_WRITE(GEN6_RP_CONTROL,
5482                    GEN6_RP_MEDIA_TURBO |
5483                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5484                    GEN6_RP_MEDIA_IS_GFX |
5485                    GEN6_RP_ENABLE |
5486                    GEN6_RP_UP_BUSY_AVG |
5487                    GEN6_RP_DOWN_IDLE_AVG);
5488
5489         /* 6: Ring frequency + overclocking (our driver does this later */
5490
5491         reset_rps(dev_priv, gen6_set_rps);
5492
5493         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5494 }
5495
5496 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5497 {
5498         struct intel_engine_cs *engine;
5499         enum intel_engine_id id;
5500         u32 rc6vids, rc6_mask = 0;
5501         u32 gtfifodbg;
5502         int rc6_mode;
5503         int ret;
5504
5505         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5506
5507         /* Here begins a magic sequence of register writes to enable
5508          * auto-downclocking.
5509          *
5510          * Perhaps there might be some value in exposing these to
5511          * userspace...
5512          */
5513         I915_WRITE(GEN6_RC_STATE, 0);
5514
5515         /* Clear the DBG now so we don't confuse earlier errors */
5516         gtfifodbg = I915_READ(GTFIFODBG);
5517         if (gtfifodbg) {
5518                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5519                 I915_WRITE(GTFIFODBG, gtfifodbg);
5520         }
5521
5522         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5523
5524         /* disable the counters and set deterministic thresholds */
5525         I915_WRITE(GEN6_RC_CONTROL, 0);
5526
5527         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5528         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5529         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5530         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5531         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5532
5533         for_each_engine(engine, dev_priv, id)
5534                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5535
5536         I915_WRITE(GEN6_RC_SLEEP, 0);
5537         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5538         if (IS_IVYBRIDGE(dev_priv))
5539                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5540         else
5541                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5542         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5543         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5544
5545         /* Check if we are enabling RC6 */
5546         rc6_mode = intel_enable_rc6();
5547         if (rc6_mode & INTEL_RC6_ENABLE)
5548                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5549
5550         /* We don't use those on Haswell */
5551         if (!IS_HASWELL(dev_priv)) {
5552                 if (rc6_mode & INTEL_RC6p_ENABLE)
5553                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5554
5555                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5556                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5557         }
5558
5559         intel_print_rc6_info(dev_priv, rc6_mask);
5560
5561         I915_WRITE(GEN6_RC_CONTROL,
5562                    rc6_mask |
5563                    GEN6_RC_CTL_EI_MODE(1) |
5564                    GEN6_RC_CTL_HW_ENABLE);
5565
5566         /* Power down if completely idle for over 50ms */
5567         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5568         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5569
5570         reset_rps(dev_priv, gen6_set_rps);
5571
5572         rc6vids = 0;
5573         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5574         if (IS_GEN6(dev_priv) && ret) {
5575                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5576         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5577                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5578                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5579                 rc6vids &= 0xffff00;
5580                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5581                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5582                 if (ret)
5583                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5584         }
5585
5586         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5587 }
5588
5589 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5590 {
5591         int min_freq = 15;
5592         unsigned int gpu_freq;
5593         unsigned int max_ia_freq, min_ring_freq;
5594         unsigned int max_gpu_freq, min_gpu_freq;
5595         int scaling_factor = 180;
5596         struct cpufreq_policy *policy;
5597
5598         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5599
5600         policy = cpufreq_cpu_get(0);
5601         if (policy) {
5602                 max_ia_freq = policy->cpuinfo.max_freq;
5603                 cpufreq_cpu_put(policy);
5604         } else {
5605                 /*
5606                  * Default to measured freq if none found, PCU will ensure we
5607                  * don't go over
5608                  */
5609                 max_ia_freq = tsc_khz;
5610         }
5611
5612         /* Convert from kHz to MHz */
5613         max_ia_freq /= 1000;
5614
5615         min_ring_freq = I915_READ(DCLK) & 0xf;
5616         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5617         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5618
5619         if (IS_GEN9_BC(dev_priv)) {
5620                 /* Convert GT frequency to 50 HZ units */
5621                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5622                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5623         } else {
5624                 min_gpu_freq = dev_priv->rps.min_freq;
5625                 max_gpu_freq = dev_priv->rps.max_freq;
5626         }
5627
5628         /*
5629          * For each potential GPU frequency, load a ring frequency we'd like
5630          * to use for memory access.  We do this by specifying the IA frequency
5631          * the PCU should use as a reference to determine the ring frequency.
5632          */
5633         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5634                 int diff = max_gpu_freq - gpu_freq;
5635                 unsigned int ia_freq = 0, ring_freq = 0;
5636
5637                 if (IS_GEN9_BC(dev_priv)) {
5638                         /*
5639                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5640                          * No floor required for ring frequency on SKL.
5641                          */
5642                         ring_freq = gpu_freq;
5643                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5644                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5645                         ring_freq = max(min_ring_freq, gpu_freq);
5646                 } else if (IS_HASWELL(dev_priv)) {
5647                         ring_freq = mult_frac(gpu_freq, 5, 4);
5648                         ring_freq = max(min_ring_freq, ring_freq);
5649                         /* leave ia_freq as the default, chosen by cpufreq */
5650                 } else {
5651                         /* On older processors, there is no separate ring
5652                          * clock domain, so in order to boost the bandwidth
5653                          * of the ring, we need to upclock the CPU (ia_freq).
5654                          *
5655                          * For GPU frequencies less than 750MHz,
5656                          * just use the lowest ring freq.
5657                          */
5658                         if (gpu_freq < min_freq)
5659                                 ia_freq = 800;
5660                         else
5661                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5662                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5663                 }
5664
5665                 sandybridge_pcode_write(dev_priv,
5666                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5667                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5668                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5669                                         gpu_freq);
5670         }
5671 }
5672
5673 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5674 {
5675         u32 val, rp0;
5676
5677         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5678
5679         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5680         case 8:
5681                 /* (2 * 4) config */
5682                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5683                 break;
5684         case 12:
5685                 /* (2 * 6) config */
5686                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5687                 break;
5688         case 16:
5689                 /* (2 * 8) config */
5690         default:
5691                 /* Setting (2 * 8) Min RP0 for any other combination */
5692                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5693                 break;
5694         }
5695
5696         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5697
5698         return rp0;
5699 }
5700
5701 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5702 {
5703         u32 val, rpe;
5704
5705         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5706         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5707
5708         return rpe;
5709 }
5710
5711 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5712 {
5713         u32 val, rp1;
5714
5715         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5716         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5717
5718         return rp1;
5719 }
5720
5721 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
5722 {
5723         u32 val, rpn;
5724
5725         val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
5726         rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
5727                        FB_GFX_FREQ_FUSE_MASK);
5728
5729         return rpn;
5730 }
5731
5732 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5733 {
5734         u32 val, rp1;
5735
5736         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5737
5738         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5739
5740         return rp1;
5741 }
5742
5743 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5744 {
5745         u32 val, rp0;
5746
5747         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5748
5749         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5750         /* Clamp to max */
5751         rp0 = min_t(u32, rp0, 0xea);
5752
5753         return rp0;
5754 }
5755
5756 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5757 {
5758         u32 val, rpe;
5759
5760         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5761         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5762         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5763         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5764
5765         return rpe;
5766 }
5767
5768 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5769 {
5770         u32 val;
5771
5772         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5773         /*
5774          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5775          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5776          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5777          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5778          * to make sure it matches what Punit accepts.
5779          */
5780         return max_t(u32, val, 0xc0);
5781 }
5782
5783 /* Check that the pctx buffer wasn't move under us. */
5784 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5785 {
5786         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5787
5788         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5789                              dev_priv->vlv_pctx->stolen->start);
5790 }
5791
5792
5793 /* Check that the pcbr address is not empty. */
5794 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5795 {
5796         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5797
5798         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5799 }
5800
5801 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5802 {
5803         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5804         unsigned long pctx_paddr, paddr;
5805         u32 pcbr;
5806         int pctx_size = 32*1024;
5807
5808         pcbr = I915_READ(VLV_PCBR);
5809         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5810                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5811                 paddr = (dev_priv->mm.stolen_base +
5812                          (ggtt->stolen_size - pctx_size));
5813
5814                 pctx_paddr = (paddr & (~4095));
5815                 I915_WRITE(VLV_PCBR, pctx_paddr);
5816         }
5817
5818         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5819 }
5820
5821 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5822 {
5823         struct drm_i915_gem_object *pctx;
5824         unsigned long pctx_paddr;
5825         u32 pcbr;
5826         int pctx_size = 24*1024;
5827
5828         pcbr = I915_READ(VLV_PCBR);
5829         if (pcbr) {
5830                 /* BIOS set it up already, grab the pre-alloc'd space */
5831                 int pcbr_offset;
5832
5833                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5834                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
5835                                                                       pcbr_offset,
5836                                                                       I915_GTT_OFFSET_NONE,
5837                                                                       pctx_size);
5838                 goto out;
5839         }
5840
5841         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5842
5843         /*
5844          * From the Gunit register HAS:
5845          * The Gfx driver is expected to program this register and ensure
5846          * proper allocation within Gfx stolen memory.  For example, this
5847          * register should be programmed such than the PCBR range does not
5848          * overlap with other ranges, such as the frame buffer, protected
5849          * memory, or any other relevant ranges.
5850          */
5851         pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
5852         if (!pctx) {
5853                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5854                 goto out;
5855         }
5856
5857         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5858         I915_WRITE(VLV_PCBR, pctx_paddr);
5859
5860 out:
5861         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5862         dev_priv->vlv_pctx = pctx;
5863 }
5864
5865 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5866 {
5867         if (WARN_ON(!dev_priv->vlv_pctx))
5868                 return;
5869
5870         i915_gem_object_put(dev_priv->vlv_pctx);
5871         dev_priv->vlv_pctx = NULL;
5872 }
5873
5874 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5875 {
5876         dev_priv->rps.gpll_ref_freq =
5877                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5878                                   CCK_GPLL_CLOCK_CONTROL,
5879                                   dev_priv->czclk_freq);
5880
5881         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5882                          dev_priv->rps.gpll_ref_freq);
5883 }
5884
5885 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5886 {
5887         u32 val;
5888
5889         valleyview_setup_pctx(dev_priv);
5890
5891         vlv_init_gpll_ref_freq(dev_priv);
5892
5893         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5894         switch ((val >> 6) & 3) {
5895         case 0:
5896         case 1:
5897                 dev_priv->mem_freq = 800;
5898                 break;
5899         case 2:
5900                 dev_priv->mem_freq = 1066;
5901                 break;
5902         case 3:
5903                 dev_priv->mem_freq = 1333;
5904                 break;
5905         }
5906         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5907
5908         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5909         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5910         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5911                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5912                          dev_priv->rps.max_freq);
5913
5914         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5915         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5916                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5917                          dev_priv->rps.efficient_freq);
5918
5919         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5920         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5921                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5922                          dev_priv->rps.rp1_freq);
5923
5924         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5925         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5926                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5927                          dev_priv->rps.min_freq);
5928 }
5929
5930 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5931 {
5932         u32 val;
5933
5934         cherryview_setup_pctx(dev_priv);
5935
5936         vlv_init_gpll_ref_freq(dev_priv);
5937
5938         mutex_lock(&dev_priv->sb_lock);
5939         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5940         mutex_unlock(&dev_priv->sb_lock);
5941
5942         switch ((val >> 2) & 0x7) {
5943         case 3:
5944                 dev_priv->mem_freq = 2000;
5945                 break;
5946         default:
5947                 dev_priv->mem_freq = 1600;
5948                 break;
5949         }
5950         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5951
5952         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5953         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5954         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5955                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5956                          dev_priv->rps.max_freq);
5957
5958         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5959         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5960                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5961                          dev_priv->rps.efficient_freq);
5962
5963         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5964         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5965                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5966                          dev_priv->rps.rp1_freq);
5967
5968         dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
5969         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5970                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5971                          dev_priv->rps.min_freq);
5972
5973         WARN_ONCE((dev_priv->rps.max_freq |
5974                    dev_priv->rps.efficient_freq |
5975                    dev_priv->rps.rp1_freq |
5976                    dev_priv->rps.min_freq) & 1,
5977                   "Odd GPU freq values\n");
5978 }
5979
5980 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5981 {
5982         valleyview_cleanup_pctx(dev_priv);
5983 }
5984
5985 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5986 {
5987         struct intel_engine_cs *engine;
5988         enum intel_engine_id id;
5989         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5990
5991         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5992
5993         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5994                                              GT_FIFO_FREE_ENTRIES_CHV);
5995         if (gtfifodbg) {
5996                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5997                                  gtfifodbg);
5998                 I915_WRITE(GTFIFODBG, gtfifodbg);
5999         }
6000
6001         cherryview_check_pctx(dev_priv);
6002
6003         /* 1a & 1b: Get forcewake during program sequence. Although the driver
6004          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6005         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6006
6007         /*  Disable RC states. */
6008         I915_WRITE(GEN6_RC_CONTROL, 0);
6009
6010         /* 2a: Program RC6 thresholds.*/
6011         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6012         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6013         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6014
6015         for_each_engine(engine, dev_priv, id)
6016                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6017         I915_WRITE(GEN6_RC_SLEEP, 0);
6018
6019         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6020         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6021
6022         /* allows RC6 residency counter to work */
6023         I915_WRITE(VLV_COUNTER_CONTROL,
6024                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6025                                       VLV_MEDIA_RC6_COUNT_EN |
6026                                       VLV_RENDER_RC6_COUNT_EN));
6027
6028         /* For now we assume BIOS is allocating and populating the PCBR  */
6029         pcbr = I915_READ(VLV_PCBR);
6030
6031         /* 3: Enable RC6 */
6032         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6033             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6034                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6035
6036         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6037
6038         /* 4 Program defaults and thresholds for RPS*/
6039         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6040         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6041         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6042         I915_WRITE(GEN6_RP_UP_EI, 66000);
6043         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6044
6045         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6046
6047         /* 5: Enable RPS */
6048         I915_WRITE(GEN6_RP_CONTROL,
6049                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6050                    GEN6_RP_MEDIA_IS_GFX |
6051                    GEN6_RP_ENABLE |
6052                    GEN6_RP_UP_BUSY_AVG |
6053                    GEN6_RP_DOWN_IDLE_AVG);
6054
6055         /* Setting Fixed Bias */
6056         val = VLV_OVERRIDE_EN |
6057                   VLV_SOC_TDP_EN |
6058                   CHV_BIAS_CPU_50_SOC_50;
6059         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6060
6061         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6062
6063         /* RPS code assumes GPLL is used */
6064         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6065
6066         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6067         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6068
6069         reset_rps(dev_priv, valleyview_set_rps);
6070
6071         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6072 }
6073
6074 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6075 {
6076         struct intel_engine_cs *engine;
6077         enum intel_engine_id id;
6078         u32 gtfifodbg, val, rc6_mode = 0;
6079
6080         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6081
6082         valleyview_check_pctx(dev_priv);
6083
6084         gtfifodbg = I915_READ(GTFIFODBG);
6085         if (gtfifodbg) {
6086                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6087                                  gtfifodbg);
6088                 I915_WRITE(GTFIFODBG, gtfifodbg);
6089         }
6090
6091         /* If VLV, Forcewake all wells, else re-direct to regular path */
6092         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6093
6094         /*  Disable RC states. */
6095         I915_WRITE(GEN6_RC_CONTROL, 0);
6096
6097         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6098         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6099         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6100         I915_WRITE(GEN6_RP_UP_EI, 66000);
6101         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6102
6103         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6104
6105         I915_WRITE(GEN6_RP_CONTROL,
6106                    GEN6_RP_MEDIA_TURBO |
6107                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6108                    GEN6_RP_MEDIA_IS_GFX |
6109                    GEN6_RP_ENABLE |
6110                    GEN6_RP_UP_BUSY_AVG |
6111                    GEN6_RP_DOWN_IDLE_CONT);
6112
6113         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6114         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6115         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6116
6117         for_each_engine(engine, dev_priv, id)
6118                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6119
6120         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6121
6122         /* allows RC6 residency counter to work */
6123         I915_WRITE(VLV_COUNTER_CONTROL,
6124                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6125                                       VLV_RENDER_RC0_COUNT_EN |
6126                                       VLV_MEDIA_RC6_COUNT_EN |
6127                                       VLV_RENDER_RC6_COUNT_EN));
6128
6129         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6130                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6131
6132         intel_print_rc6_info(dev_priv, rc6_mode);
6133
6134         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6135
6136         /* Setting Fixed Bias */
6137         val = VLV_OVERRIDE_EN |
6138                   VLV_SOC_TDP_EN |
6139                   VLV_BIAS_CPU_125_SOC_875;
6140         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6141
6142         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6143
6144         /* RPS code assumes GPLL is used */
6145         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6146
6147         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6148         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6149
6150         reset_rps(dev_priv, valleyview_set_rps);
6151
6152         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6153 }
6154
6155 static unsigned long intel_pxfreq(u32 vidfreq)
6156 {
6157         unsigned long freq;
6158         int div = (vidfreq & 0x3f0000) >> 16;
6159         int post = (vidfreq & 0x3000) >> 12;
6160         int pre = (vidfreq & 0x7);
6161
6162         if (!pre)
6163                 return 0;
6164
6165         freq = ((div * 133333) / ((1<<post) * pre));
6166
6167         return freq;
6168 }
6169
6170 static const struct cparams {
6171         u16 i;
6172         u16 t;
6173         u16 m;
6174         u16 c;
6175 } cparams[] = {
6176         { 1, 1333, 301, 28664 },
6177         { 1, 1066, 294, 24460 },
6178         { 1, 800, 294, 25192 },
6179         { 0, 1333, 276, 27605 },
6180         { 0, 1066, 276, 27605 },
6181         { 0, 800, 231, 23784 },
6182 };
6183
6184 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6185 {
6186         u64 total_count, diff, ret;
6187         u32 count1, count2, count3, m = 0, c = 0;
6188         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6189         int i;
6190
6191         lockdep_assert_held(&mchdev_lock);
6192
6193         diff1 = now - dev_priv->ips.last_time1;
6194
6195         /* Prevent division-by-zero if we are asking too fast.
6196          * Also, we don't get interesting results if we are polling
6197          * faster than once in 10ms, so just return the saved value
6198          * in such cases.
6199          */
6200         if (diff1 <= 10)
6201                 return dev_priv->ips.chipset_power;
6202
6203         count1 = I915_READ(DMIEC);
6204         count2 = I915_READ(DDREC);
6205         count3 = I915_READ(CSIEC);
6206
6207         total_count = count1 + count2 + count3;
6208
6209         /* FIXME: handle per-counter overflow */
6210         if (total_count < dev_priv->ips.last_count1) {
6211                 diff = ~0UL - dev_priv->ips.last_count1;
6212                 diff += total_count;
6213         } else {
6214                 diff = total_count - dev_priv->ips.last_count1;
6215         }
6216
6217         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6218                 if (cparams[i].i == dev_priv->ips.c_m &&
6219                     cparams[i].t == dev_priv->ips.r_t) {
6220                         m = cparams[i].m;
6221                         c = cparams[i].c;
6222                         break;
6223                 }
6224         }
6225
6226         diff = div_u64(diff, diff1);
6227         ret = ((m * diff) + c);
6228         ret = div_u64(ret, 10);
6229
6230         dev_priv->ips.last_count1 = total_count;
6231         dev_priv->ips.last_time1 = now;
6232
6233         dev_priv->ips.chipset_power = ret;
6234
6235         return ret;
6236 }
6237
6238 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6239 {
6240         unsigned long val;
6241
6242         if (INTEL_INFO(dev_priv)->gen != 5)
6243                 return 0;
6244
6245         spin_lock_irq(&mchdev_lock);
6246
6247         val = __i915_chipset_val(dev_priv);
6248
6249         spin_unlock_irq(&mchdev_lock);
6250
6251         return val;
6252 }
6253
6254 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6255 {
6256         unsigned long m, x, b;
6257         u32 tsfs;
6258
6259         tsfs = I915_READ(TSFS);
6260
6261         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6262         x = I915_READ8(TR1);
6263
6264         b = tsfs & TSFS_INTR_MASK;
6265
6266         return ((m * x) / 127) - b;
6267 }
6268
6269 static int _pxvid_to_vd(u8 pxvid)
6270 {
6271         if (pxvid == 0)
6272                 return 0;
6273
6274         if (pxvid >= 8 && pxvid < 31)
6275                 pxvid = 31;
6276
6277         return (pxvid + 2) * 125;
6278 }
6279
6280 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6281 {
6282         const int vd = _pxvid_to_vd(pxvid);
6283         const int vm = vd - 1125;
6284
6285         if (INTEL_INFO(dev_priv)->is_mobile)
6286                 return vm > 0 ? vm : 0;
6287
6288         return vd;
6289 }
6290
6291 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6292 {
6293         u64 now, diff, diffms;
6294         u32 count;
6295
6296         lockdep_assert_held(&mchdev_lock);
6297
6298         now = ktime_get_raw_ns();
6299         diffms = now - dev_priv->ips.last_time2;
6300         do_div(diffms, NSEC_PER_MSEC);
6301
6302         /* Don't divide by 0 */
6303         if (!diffms)
6304                 return;
6305
6306         count = I915_READ(GFXEC);
6307
6308         if (count < dev_priv->ips.last_count2) {
6309                 diff = ~0UL - dev_priv->ips.last_count2;
6310                 diff += count;
6311         } else {
6312                 diff = count - dev_priv->ips.last_count2;
6313         }
6314
6315         dev_priv->ips.last_count2 = count;
6316         dev_priv->ips.last_time2 = now;
6317
6318         /* More magic constants... */
6319         diff = diff * 1181;
6320         diff = div_u64(diff, diffms * 10);
6321         dev_priv->ips.gfx_power = diff;
6322 }
6323
6324 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6325 {
6326         if (INTEL_INFO(dev_priv)->gen != 5)
6327                 return;
6328
6329         spin_lock_irq(&mchdev_lock);
6330
6331         __i915_update_gfx_val(dev_priv);
6332
6333         spin_unlock_irq(&mchdev_lock);
6334 }
6335
6336 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6337 {
6338         unsigned long t, corr, state1, corr2, state2;
6339         u32 pxvid, ext_v;
6340
6341         lockdep_assert_held(&mchdev_lock);
6342
6343         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6344         pxvid = (pxvid >> 24) & 0x7f;
6345         ext_v = pvid_to_extvid(dev_priv, pxvid);
6346
6347         state1 = ext_v;
6348
6349         t = i915_mch_val(dev_priv);
6350
6351         /* Revel in the empirically derived constants */
6352
6353         /* Correction factor in 1/100000 units */
6354         if (t > 80)
6355                 corr = ((t * 2349) + 135940);
6356         else if (t >= 50)
6357                 corr = ((t * 964) + 29317);
6358         else /* < 50 */
6359                 corr = ((t * 301) + 1004);
6360
6361         corr = corr * ((150142 * state1) / 10000 - 78642);
6362         corr /= 100000;
6363         corr2 = (corr * dev_priv->ips.corr);
6364
6365         state2 = (corr2 * state1) / 10000;
6366         state2 /= 100; /* convert to mW */
6367
6368         __i915_update_gfx_val(dev_priv);
6369
6370         return dev_priv->ips.gfx_power + state2;
6371 }
6372
6373 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6374 {
6375         unsigned long val;
6376
6377         if (INTEL_INFO(dev_priv)->gen != 5)
6378                 return 0;
6379
6380         spin_lock_irq(&mchdev_lock);
6381
6382         val = __i915_gfx_val(dev_priv);
6383
6384         spin_unlock_irq(&mchdev_lock);
6385
6386         return val;
6387 }
6388
6389 /**
6390  * i915_read_mch_val - return value for IPS use
6391  *
6392  * Calculate and return a value for the IPS driver to use when deciding whether
6393  * we have thermal and power headroom to increase CPU or GPU power budget.
6394  */
6395 unsigned long i915_read_mch_val(void)
6396 {
6397         struct drm_i915_private *dev_priv;
6398         unsigned long chipset_val, graphics_val, ret = 0;
6399
6400         spin_lock_irq(&mchdev_lock);
6401         if (!i915_mch_dev)
6402                 goto out_unlock;
6403         dev_priv = i915_mch_dev;
6404
6405         chipset_val = __i915_chipset_val(dev_priv);
6406         graphics_val = __i915_gfx_val(dev_priv);
6407
6408         ret = chipset_val + graphics_val;
6409
6410 out_unlock:
6411         spin_unlock_irq(&mchdev_lock);
6412
6413         return ret;
6414 }
6415 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6416
6417 /**
6418  * i915_gpu_raise - raise GPU frequency limit
6419  *
6420  * Raise the limit; IPS indicates we have thermal headroom.
6421  */
6422 bool i915_gpu_raise(void)
6423 {
6424         struct drm_i915_private *dev_priv;
6425         bool ret = true;
6426
6427         spin_lock_irq(&mchdev_lock);
6428         if (!i915_mch_dev) {
6429                 ret = false;
6430                 goto out_unlock;
6431         }
6432         dev_priv = i915_mch_dev;
6433
6434         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6435                 dev_priv->ips.max_delay--;
6436
6437 out_unlock:
6438         spin_unlock_irq(&mchdev_lock);
6439
6440         return ret;
6441 }
6442 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6443
6444 /**
6445  * i915_gpu_lower - lower GPU frequency limit
6446  *
6447  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6448  * frequency maximum.
6449  */
6450 bool i915_gpu_lower(void)
6451 {
6452         struct drm_i915_private *dev_priv;
6453         bool ret = true;
6454
6455         spin_lock_irq(&mchdev_lock);
6456         if (!i915_mch_dev) {
6457                 ret = false;
6458                 goto out_unlock;
6459         }
6460         dev_priv = i915_mch_dev;
6461
6462         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6463                 dev_priv->ips.max_delay++;
6464
6465 out_unlock:
6466         spin_unlock_irq(&mchdev_lock);
6467
6468         return ret;
6469 }
6470 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6471
6472 /**
6473  * i915_gpu_busy - indicate GPU business to IPS
6474  *
6475  * Tell the IPS driver whether or not the GPU is busy.
6476  */
6477 bool i915_gpu_busy(void)
6478 {
6479         bool ret = false;
6480
6481         spin_lock_irq(&mchdev_lock);
6482         if (i915_mch_dev)
6483                 ret = i915_mch_dev->gt.awake;
6484         spin_unlock_irq(&mchdev_lock);
6485
6486         return ret;
6487 }
6488 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6489
6490 /**
6491  * i915_gpu_turbo_disable - disable graphics turbo
6492  *
6493  * Disable graphics turbo by resetting the max frequency and setting the
6494  * current frequency to the default.
6495  */
6496 bool i915_gpu_turbo_disable(void)
6497 {
6498         struct drm_i915_private *dev_priv;
6499         bool ret = true;
6500
6501         spin_lock_irq(&mchdev_lock);
6502         if (!i915_mch_dev) {
6503                 ret = false;
6504                 goto out_unlock;
6505         }
6506         dev_priv = i915_mch_dev;
6507
6508         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6509
6510         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6511                 ret = false;
6512
6513 out_unlock:
6514         spin_unlock_irq(&mchdev_lock);
6515
6516         return ret;
6517 }
6518 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6519
6520 /**
6521  * Tells the intel_ips driver that the i915 driver is now loaded, if
6522  * IPS got loaded first.
6523  *
6524  * This awkward dance is so that neither module has to depend on the
6525  * other in order for IPS to do the appropriate communication of
6526  * GPU turbo limits to i915.
6527  */
6528 static void
6529 ips_ping_for_i915_load(void)
6530 {
6531         void (*link)(void);
6532
6533         link = symbol_get(ips_link_to_i915_driver);
6534         if (link) {
6535                 link();
6536                 symbol_put(ips_link_to_i915_driver);
6537         }
6538 }
6539
6540 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6541 {
6542         /* We only register the i915 ips part with intel-ips once everything is
6543          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6544         spin_lock_irq(&mchdev_lock);
6545         i915_mch_dev = dev_priv;
6546         spin_unlock_irq(&mchdev_lock);
6547
6548         ips_ping_for_i915_load();
6549 }
6550
6551 void intel_gpu_ips_teardown(void)
6552 {
6553         spin_lock_irq(&mchdev_lock);
6554         i915_mch_dev = NULL;
6555         spin_unlock_irq(&mchdev_lock);
6556 }
6557
6558 static void intel_init_emon(struct drm_i915_private *dev_priv)
6559 {
6560         u32 lcfuse;
6561         u8 pxw[16];
6562         int i;
6563
6564         /* Disable to program */
6565         I915_WRITE(ECR, 0);
6566         POSTING_READ(ECR);
6567
6568         /* Program energy weights for various events */
6569         I915_WRITE(SDEW, 0x15040d00);
6570         I915_WRITE(CSIEW0, 0x007f0000);
6571         I915_WRITE(CSIEW1, 0x1e220004);
6572         I915_WRITE(CSIEW2, 0x04000004);
6573
6574         for (i = 0; i < 5; i++)
6575                 I915_WRITE(PEW(i), 0);
6576         for (i = 0; i < 3; i++)
6577                 I915_WRITE(DEW(i), 0);
6578
6579         /* Program P-state weights to account for frequency power adjustment */
6580         for (i = 0; i < 16; i++) {
6581                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6582                 unsigned long freq = intel_pxfreq(pxvidfreq);
6583                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6584                         PXVFREQ_PX_SHIFT;
6585                 unsigned long val;
6586
6587                 val = vid * vid;
6588                 val *= (freq / 1000);
6589                 val *= 255;
6590                 val /= (127*127*900);
6591                 if (val > 0xff)
6592                         DRM_ERROR("bad pxval: %ld\n", val);
6593                 pxw[i] = val;
6594         }
6595         /* Render standby states get 0 weight */
6596         pxw[14] = 0;
6597         pxw[15] = 0;
6598
6599         for (i = 0; i < 4; i++) {
6600                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6601                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6602                 I915_WRITE(PXW(i), val);
6603         }
6604
6605         /* Adjust magic regs to magic values (more experimental results) */
6606         I915_WRITE(OGW0, 0);
6607         I915_WRITE(OGW1, 0);
6608         I915_WRITE(EG0, 0x00007f00);
6609         I915_WRITE(EG1, 0x0000000e);
6610         I915_WRITE(EG2, 0x000e0000);
6611         I915_WRITE(EG3, 0x68000300);
6612         I915_WRITE(EG4, 0x42000000);
6613         I915_WRITE(EG5, 0x00140031);
6614         I915_WRITE(EG6, 0);
6615         I915_WRITE(EG7, 0);
6616
6617         for (i = 0; i < 8; i++)
6618                 I915_WRITE(PXWL(i), 0);
6619
6620         /* Enable PMON + select events */
6621         I915_WRITE(ECR, 0x80000019);
6622
6623         lcfuse = I915_READ(LCFUSE02);
6624
6625         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6626 }
6627
6628 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6629 {
6630         /*
6631          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6632          * requirement.
6633          */
6634         if (!i915.enable_rc6) {
6635                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6636                 intel_runtime_pm_get(dev_priv);
6637         }
6638
6639         mutex_lock(&dev_priv->drm.struct_mutex);
6640         mutex_lock(&dev_priv->rps.hw_lock);
6641
6642         /* Initialize RPS limits (for userspace) */
6643         if (IS_CHERRYVIEW(dev_priv))
6644                 cherryview_init_gt_powersave(dev_priv);
6645         else if (IS_VALLEYVIEW(dev_priv))
6646                 valleyview_init_gt_powersave(dev_priv);
6647         else if (INTEL_GEN(dev_priv) >= 6)
6648                 gen6_init_rps_frequencies(dev_priv);
6649
6650         /* Derive initial user preferences/limits from the hardware limits */
6651         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6652         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6653
6654         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6655         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6656
6657         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6658                 dev_priv->rps.min_freq_softlimit =
6659                         max_t(int,
6660                               dev_priv->rps.efficient_freq,
6661                               intel_freq_opcode(dev_priv, 450));
6662
6663         /* After setting max-softlimit, find the overclock max freq */
6664         if (IS_GEN6(dev_priv) ||
6665             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6666                 u32 params = 0;
6667
6668                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6669                 if (params & BIT(31)) { /* OC supported */
6670                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6671                                          (dev_priv->rps.max_freq & 0xff) * 50,
6672                                          (params & 0xff) * 50);
6673                         dev_priv->rps.max_freq = params & 0xff;
6674                 }
6675         }
6676
6677         /* Finally allow us to boost to max by default */
6678         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6679
6680         mutex_unlock(&dev_priv->rps.hw_lock);
6681         mutex_unlock(&dev_priv->drm.struct_mutex);
6682
6683         intel_autoenable_gt_powersave(dev_priv);
6684 }
6685
6686 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6687 {
6688         if (IS_VALLEYVIEW(dev_priv))
6689                 valleyview_cleanup_gt_powersave(dev_priv);
6690
6691         if (!i915.enable_rc6)
6692                 intel_runtime_pm_put(dev_priv);
6693 }
6694
6695 /**
6696  * intel_suspend_gt_powersave - suspend PM work and helper threads
6697  * @dev_priv: i915 device
6698  *
6699  * We don't want to disable RC6 or other features here, we just want
6700  * to make sure any work we've queued has finished and won't bother
6701  * us while we're suspended.
6702  */
6703 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6704 {
6705         if (INTEL_GEN(dev_priv) < 6)
6706                 return;
6707
6708         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6709                 intel_runtime_pm_put(dev_priv);
6710
6711         /* gen6_rps_idle() will be called later to disable interrupts */
6712 }
6713
6714 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6715 {
6716         dev_priv->rps.enabled = true; /* force disabling */
6717         intel_disable_gt_powersave(dev_priv);
6718
6719         gen6_reset_rps_interrupts(dev_priv);
6720 }
6721
6722 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6723 {
6724         if (!READ_ONCE(dev_priv->rps.enabled))
6725                 return;
6726
6727         mutex_lock(&dev_priv->rps.hw_lock);
6728
6729         if (INTEL_GEN(dev_priv) >= 9) {
6730                 gen9_disable_rc6(dev_priv);
6731                 gen9_disable_rps(dev_priv);
6732         } else if (IS_CHERRYVIEW(dev_priv)) {
6733                 cherryview_disable_rps(dev_priv);
6734         } else if (IS_VALLEYVIEW(dev_priv)) {
6735                 valleyview_disable_rps(dev_priv);
6736         } else if (INTEL_GEN(dev_priv) >= 6) {
6737                 gen6_disable_rps(dev_priv);
6738         }  else if (IS_IRONLAKE_M(dev_priv)) {
6739                 ironlake_disable_drps(dev_priv);
6740         }
6741
6742         dev_priv->rps.enabled = false;
6743         mutex_unlock(&dev_priv->rps.hw_lock);
6744 }
6745
6746 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6747 {
6748         /* We shouldn't be disabling as we submit, so this should be less
6749          * racy than it appears!
6750          */
6751         if (READ_ONCE(dev_priv->rps.enabled))
6752                 return;
6753
6754         /* Powersaving is controlled by the host when inside a VM */
6755         if (intel_vgpu_active(dev_priv))
6756                 return;
6757
6758         mutex_lock(&dev_priv->rps.hw_lock);
6759
6760         if (IS_CHERRYVIEW(dev_priv)) {
6761                 cherryview_enable_rps(dev_priv);
6762         } else if (IS_VALLEYVIEW(dev_priv)) {
6763                 valleyview_enable_rps(dev_priv);
6764         } else if (INTEL_GEN(dev_priv) >= 9) {
6765                 gen9_enable_rc6(dev_priv);
6766                 gen9_enable_rps(dev_priv);
6767                 if (IS_GEN9_BC(dev_priv))
6768                         gen6_update_ring_freq(dev_priv);
6769         } else if (IS_BROADWELL(dev_priv)) {
6770                 gen8_enable_rps(dev_priv);
6771                 gen6_update_ring_freq(dev_priv);
6772         } else if (INTEL_GEN(dev_priv) >= 6) {
6773                 gen6_enable_rps(dev_priv);
6774                 gen6_update_ring_freq(dev_priv);
6775         } else if (IS_IRONLAKE_M(dev_priv)) {
6776                 ironlake_enable_drps(dev_priv);
6777                 intel_init_emon(dev_priv);
6778         }
6779
6780         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6781         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6782
6783         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6784         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6785
6786         dev_priv->rps.enabled = true;
6787         mutex_unlock(&dev_priv->rps.hw_lock);
6788 }
6789
6790 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6791 {
6792         struct drm_i915_private *dev_priv =
6793                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6794         struct intel_engine_cs *rcs;
6795         struct drm_i915_gem_request *req;
6796
6797         if (READ_ONCE(dev_priv->rps.enabled))
6798                 goto out;
6799
6800         rcs = dev_priv->engine[RCS];
6801         if (rcs->last_retired_context)
6802                 goto out;
6803
6804         if (!rcs->init_context)
6805                 goto out;
6806
6807         mutex_lock(&dev_priv->drm.struct_mutex);
6808
6809         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6810         if (IS_ERR(req))
6811                 goto unlock;
6812
6813         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6814                 rcs->init_context(req);
6815
6816         /* Mark the device busy, calling intel_enable_gt_powersave() */
6817         i915_add_request_no_flush(req);
6818
6819 unlock:
6820         mutex_unlock(&dev_priv->drm.struct_mutex);
6821 out:
6822         intel_runtime_pm_put(dev_priv);
6823 }
6824
6825 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6826 {
6827         if (READ_ONCE(dev_priv->rps.enabled))
6828                 return;
6829
6830         if (IS_IRONLAKE_M(dev_priv)) {
6831                 ironlake_enable_drps(dev_priv);
6832                 intel_init_emon(dev_priv);
6833         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6834                 /*
6835                  * PCU communication is slow and this doesn't need to be
6836                  * done at any specific time, so do this out of our fast path
6837                  * to make resume and init faster.
6838                  *
6839                  * We depend on the HW RC6 power context save/restore
6840                  * mechanism when entering D3 through runtime PM suspend. So
6841                  * disable RPM until RPS/RC6 is properly setup. We can only
6842                  * get here via the driver load/system resume/runtime resume
6843                  * paths, so the _noresume version is enough (and in case of
6844                  * runtime resume it's necessary).
6845                  */
6846                 if (queue_delayed_work(dev_priv->wq,
6847                                        &dev_priv->rps.autoenable_work,
6848                                        round_jiffies_up_relative(HZ)))
6849                         intel_runtime_pm_get_noresume(dev_priv);
6850         }
6851 }
6852
6853 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6854 {
6855         /*
6856          * On Ibex Peak and Cougar Point, we need to disable clock
6857          * gating for the panel power sequencer or it will fail to
6858          * start up when no ports are active.
6859          */
6860         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6861 }
6862
6863 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6864 {
6865         enum pipe pipe;
6866
6867         for_each_pipe(dev_priv, pipe) {
6868                 I915_WRITE(DSPCNTR(pipe),
6869                            I915_READ(DSPCNTR(pipe)) |
6870                            DISPPLANE_TRICKLE_FEED_DISABLE);
6871
6872                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6873                 POSTING_READ(DSPSURF(pipe));
6874         }
6875 }
6876
6877 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6878 {
6879         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6880         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6881         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6882
6883         /*
6884          * Don't touch WM1S_LP_EN here.
6885          * Doing so could cause underruns.
6886          */
6887 }
6888
6889 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6890 {
6891         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6892
6893         /*
6894          * Required for FBC
6895          * WaFbcDisableDpfcClockGating:ilk
6896          */
6897         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6898                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6899                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6900
6901         I915_WRITE(PCH_3DCGDIS0,
6902                    MARIUNIT_CLOCK_GATE_DISABLE |
6903                    SVSMUNIT_CLOCK_GATE_DISABLE);
6904         I915_WRITE(PCH_3DCGDIS1,
6905                    VFMUNIT_CLOCK_GATE_DISABLE);
6906
6907         /*
6908          * According to the spec the following bits should be set in
6909          * order to enable memory self-refresh
6910          * The bit 22/21 of 0x42004
6911          * The bit 5 of 0x42020
6912          * The bit 15 of 0x45000
6913          */
6914         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6915                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6916                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6917         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6918         I915_WRITE(DISP_ARB_CTL,
6919                    (I915_READ(DISP_ARB_CTL) |
6920                     DISP_FBC_WM_DIS));
6921
6922         ilk_init_lp_watermarks(dev_priv);
6923
6924         /*
6925          * Based on the document from hardware guys the following bits
6926          * should be set unconditionally in order to enable FBC.
6927          * The bit 22 of 0x42000
6928          * The bit 22 of 0x42004
6929          * The bit 7,8,9 of 0x42020.
6930          */
6931         if (IS_IRONLAKE_M(dev_priv)) {
6932                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6933                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6934                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6935                            ILK_FBCQ_DIS);
6936                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6937                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6938                            ILK_DPARB_GATE);
6939         }
6940
6941         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6942
6943         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6944                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6945                    ILK_ELPIN_409_SELECT);
6946         I915_WRITE(_3D_CHICKEN2,
6947                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6948                    _3D_CHICKEN2_WM_READ_PIPELINED);
6949
6950         /* WaDisableRenderCachePipelinedFlush:ilk */
6951         I915_WRITE(CACHE_MODE_0,
6952                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6953
6954         /* WaDisable_RenderCache_OperationalFlush:ilk */
6955         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6956
6957         g4x_disable_trickle_feed(dev_priv);
6958
6959         ibx_init_clock_gating(dev_priv);
6960 }
6961
6962 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6963 {
6964         int pipe;
6965         uint32_t val;
6966
6967         /*
6968          * On Ibex Peak and Cougar Point, we need to disable clock
6969          * gating for the panel power sequencer or it will fail to
6970          * start up when no ports are active.
6971          */
6972         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6973                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6974                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6975         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6976                    DPLS_EDP_PPS_FIX_DIS);
6977         /* The below fixes the weird display corruption, a few pixels shifted
6978          * downward, on (only) LVDS of some HP laptops with IVY.
6979          */
6980         for_each_pipe(dev_priv, pipe) {
6981                 val = I915_READ(TRANS_CHICKEN2(pipe));
6982                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6983                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6984                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6985                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6986                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6987                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6988                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6989                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6990         }
6991         /* WADP0ClockGatingDisable */
6992         for_each_pipe(dev_priv, pipe) {
6993                 I915_WRITE(TRANS_CHICKEN1(pipe),
6994                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6995         }
6996 }
6997
6998 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
6999 {
7000         uint32_t tmp;
7001
7002         tmp = I915_READ(MCH_SSKPD);
7003         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7004                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7005                               tmp);
7006 }
7007
7008 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7009 {
7010         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7011
7012         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7013
7014         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7015                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7016                    ILK_ELPIN_409_SELECT);
7017
7018         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7019         I915_WRITE(_3D_CHICKEN,
7020                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7021
7022         /* WaDisable_RenderCache_OperationalFlush:snb */
7023         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7024
7025         /*
7026          * BSpec recoomends 8x4 when MSAA is used,
7027          * however in practice 16x4 seems fastest.
7028          *
7029          * Note that PS/WM thread counts depend on the WIZ hashing
7030          * disable bit, which we don't touch here, but it's good
7031          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7032          */
7033         I915_WRITE(GEN6_GT_MODE,
7034                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7035
7036         ilk_init_lp_watermarks(dev_priv);
7037
7038         I915_WRITE(CACHE_MODE_0,
7039                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7040
7041         I915_WRITE(GEN6_UCGCTL1,
7042                    I915_READ(GEN6_UCGCTL1) |
7043                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7044                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7045
7046         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7047          * gating disable must be set.  Failure to set it results in
7048          * flickering pixels due to Z write ordering failures after
7049          * some amount of runtime in the Mesa "fire" demo, and Unigine
7050          * Sanctuary and Tropics, and apparently anything else with
7051          * alpha test or pixel discard.
7052          *
7053          * According to the spec, bit 11 (RCCUNIT) must also be set,
7054          * but we didn't debug actual testcases to find it out.
7055          *
7056          * WaDisableRCCUnitClockGating:snb
7057          * WaDisableRCPBUnitClockGating:snb
7058          */
7059         I915_WRITE(GEN6_UCGCTL2,
7060                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7061                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7062
7063         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7064         I915_WRITE(_3D_CHICKEN3,
7065                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7066
7067         /*
7068          * Bspec says:
7069          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7070          * 3DSTATE_SF number of SF output attributes is more than 16."
7071          */
7072         I915_WRITE(_3D_CHICKEN3,
7073                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7074
7075         /*
7076          * According to the spec the following bits should be
7077          * set in order to enable memory self-refresh and fbc:
7078          * The bit21 and bit22 of 0x42000
7079          * The bit21 and bit22 of 0x42004
7080          * The bit5 and bit7 of 0x42020
7081          * The bit14 of 0x70180
7082          * The bit14 of 0x71180
7083          *
7084          * WaFbcAsynchFlipDisableFbcQueue:snb
7085          */
7086         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7087                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7088                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7089         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7090                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7091                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7092         I915_WRITE(ILK_DSPCLK_GATE_D,
7093                    I915_READ(ILK_DSPCLK_GATE_D) |
7094                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7095                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7096
7097         g4x_disable_trickle_feed(dev_priv);
7098
7099         cpt_init_clock_gating(dev_priv);
7100
7101         gen6_check_mch_setup(dev_priv);
7102 }
7103
7104 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7105 {
7106         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7107
7108         /*
7109          * WaVSThreadDispatchOverride:ivb,vlv
7110          *
7111          * This actually overrides the dispatch
7112          * mode for all thread types.
7113          */
7114         reg &= ~GEN7_FF_SCHED_MASK;
7115         reg |= GEN7_FF_TS_SCHED_HW;
7116         reg |= GEN7_FF_VS_SCHED_HW;
7117         reg |= GEN7_FF_DS_SCHED_HW;
7118
7119         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7120 }
7121
7122 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7123 {
7124         /*
7125          * TODO: this bit should only be enabled when really needed, then
7126          * disabled when not needed anymore in order to save power.
7127          */
7128         if (HAS_PCH_LPT_LP(dev_priv))
7129                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7130                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7131                            PCH_LP_PARTITION_LEVEL_DISABLE);
7132
7133         /* WADPOClockGatingDisable:hsw */
7134         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7135                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7136                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7137 }
7138
7139 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7140 {
7141         if (HAS_PCH_LPT_LP(dev_priv)) {
7142                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7143
7144                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7145                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7146         }
7147 }
7148
7149 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7150                                    int general_prio_credits,
7151                                    int high_prio_credits)
7152 {
7153         u32 misccpctl;
7154
7155         /* WaTempDisableDOPClkGating:bdw */
7156         misccpctl = I915_READ(GEN7_MISCCPCTL);
7157         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7158
7159         I915_WRITE(GEN8_L3SQCREG1,
7160                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7161                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7162
7163         /*
7164          * Wait at least 100 clocks before re-enabling clock gating.
7165          * See the definition of L3SQCREG1 in BSpec.
7166          */
7167         POSTING_READ(GEN8_L3SQCREG1);
7168         udelay(1);
7169         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7170 }
7171
7172 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7173 {
7174         gen9_init_clock_gating(dev_priv);
7175
7176         /* WaDisableSDEUnitClockGating:kbl */
7177         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7178                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7179                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7180
7181         /* WaDisableGamClockGating:kbl */
7182         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7183                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7184                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7185
7186         /* WaFbcNukeOnHostModify:kbl */
7187         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7188                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7189 }
7190
7191 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7192 {
7193         gen9_init_clock_gating(dev_priv);
7194
7195         /* WAC6entrylatency:skl */
7196         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7197                    FBC_LLC_FULLY_OPEN);
7198
7199         /* WaFbcNukeOnHostModify:skl */
7200         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7201                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7202 }
7203
7204 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7205 {
7206         enum pipe pipe;
7207
7208         ilk_init_lp_watermarks(dev_priv);
7209
7210         /* WaSwitchSolVfFArbitrationPriority:bdw */
7211         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7212
7213         /* WaPsrDPAMaskVBlankInSRD:bdw */
7214         I915_WRITE(CHICKEN_PAR1_1,
7215                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7216
7217         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7218         for_each_pipe(dev_priv, pipe) {
7219                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7220                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7221                            BDW_DPRS_MASK_VBLANK_SRD);
7222         }
7223
7224         /* WaVSRefCountFullforceMissDisable:bdw */
7225         /* WaDSRefCountFullforceMissDisable:bdw */
7226         I915_WRITE(GEN7_FF_THREAD_MODE,
7227                    I915_READ(GEN7_FF_THREAD_MODE) &
7228                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7229
7230         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7231                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7232
7233         /* WaDisableSDEUnitClockGating:bdw */
7234         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7235                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7236
7237         /* WaProgramL3SqcReg1Default:bdw */
7238         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7239
7240         /*
7241          * WaGttCachingOffByDefault:bdw
7242          * GTT cache may not work with big pages, so if those
7243          * are ever enabled GTT cache may need to be disabled.
7244          */
7245         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7246
7247         /* WaKVMNotificationOnConfigChange:bdw */
7248         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7249                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7250
7251         lpt_init_clock_gating(dev_priv);
7252
7253         /* WaDisableDopClockGating:bdw
7254          *
7255          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7256          * clock gating.
7257          */
7258         I915_WRITE(GEN6_UCGCTL1,
7259                    I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
7260 }
7261
7262 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7263 {
7264         ilk_init_lp_watermarks(dev_priv);
7265
7266         /* L3 caching of data atomics doesn't work -- disable it. */
7267         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7268         I915_WRITE(HSW_ROW_CHICKEN3,
7269                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7270
7271         /* This is required by WaCatErrorRejectionIssue:hsw */
7272         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7273                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7274                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7275
7276         /* WaVSRefCountFullforceMissDisable:hsw */
7277         I915_WRITE(GEN7_FF_THREAD_MODE,
7278                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7279
7280         /* WaDisable_RenderCache_OperationalFlush:hsw */
7281         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7282
7283         /* enable HiZ Raw Stall Optimization */
7284         I915_WRITE(CACHE_MODE_0_GEN7,
7285                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7286
7287         /* WaDisable4x2SubspanOptimization:hsw */
7288         I915_WRITE(CACHE_MODE_1,
7289                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7290
7291         /*
7292          * BSpec recommends 8x4 when MSAA is used,
7293          * however in practice 16x4 seems fastest.
7294          *
7295          * Note that PS/WM thread counts depend on the WIZ hashing
7296          * disable bit, which we don't touch here, but it's good
7297          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7298          */
7299         I915_WRITE(GEN7_GT_MODE,
7300                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7301
7302         /* WaSampleCChickenBitEnable:hsw */
7303         I915_WRITE(HALF_SLICE_CHICKEN3,
7304                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7305
7306         /* WaSwitchSolVfFArbitrationPriority:hsw */
7307         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7308
7309         /* WaRsPkgCStateDisplayPMReq:hsw */
7310         I915_WRITE(CHICKEN_PAR1_1,
7311                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7312
7313         lpt_init_clock_gating(dev_priv);
7314 }
7315
7316 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7317 {
7318         uint32_t snpcr;
7319
7320         ilk_init_lp_watermarks(dev_priv);
7321
7322         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7323
7324         /* WaDisableEarlyCull:ivb */
7325         I915_WRITE(_3D_CHICKEN3,
7326                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7327
7328         /* WaDisableBackToBackFlipFix:ivb */
7329         I915_WRITE(IVB_CHICKEN3,
7330                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7331                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7332
7333         /* WaDisablePSDDualDispatchEnable:ivb */
7334         if (IS_IVB_GT1(dev_priv))
7335                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7336                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7337
7338         /* WaDisable_RenderCache_OperationalFlush:ivb */
7339         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7340
7341         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7342         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7343                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7344
7345         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7346         I915_WRITE(GEN7_L3CNTLREG1,
7347                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7348         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7349                    GEN7_WA_L3_CHICKEN_MODE);
7350         if (IS_IVB_GT1(dev_priv))
7351                 I915_WRITE(GEN7_ROW_CHICKEN2,
7352                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7353         else {
7354                 /* must write both registers */
7355                 I915_WRITE(GEN7_ROW_CHICKEN2,
7356                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7357                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7358                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7359         }
7360
7361         /* WaForceL3Serialization:ivb */
7362         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7363                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7364
7365         /*
7366          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7367          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7368          */
7369         I915_WRITE(GEN6_UCGCTL2,
7370                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7371
7372         /* This is required by WaCatErrorRejectionIssue:ivb */
7373         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7374                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7375                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7376
7377         g4x_disable_trickle_feed(dev_priv);
7378
7379         gen7_setup_fixed_func_scheduler(dev_priv);
7380
7381         if (0) { /* causes HiZ corruption on ivb:gt1 */
7382                 /* enable HiZ Raw Stall Optimization */
7383                 I915_WRITE(CACHE_MODE_0_GEN7,
7384                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7385         }
7386
7387         /* WaDisable4x2SubspanOptimization:ivb */
7388         I915_WRITE(CACHE_MODE_1,
7389                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7390
7391         /*
7392          * BSpec recommends 8x4 when MSAA is used,
7393          * however in practice 16x4 seems fastest.
7394          *
7395          * Note that PS/WM thread counts depend on the WIZ hashing
7396          * disable bit, which we don't touch here, but it's good
7397          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7398          */
7399         I915_WRITE(GEN7_GT_MODE,
7400                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7401
7402         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7403         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7404         snpcr |= GEN6_MBC_SNPCR_MED;
7405         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7406
7407         if (!HAS_PCH_NOP(dev_priv))
7408                 cpt_init_clock_gating(dev_priv);
7409
7410         gen6_check_mch_setup(dev_priv);
7411 }
7412
7413 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7414 {
7415         /* WaDisableEarlyCull:vlv */
7416         I915_WRITE(_3D_CHICKEN3,
7417                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7418
7419         /* WaDisableBackToBackFlipFix:vlv */
7420         I915_WRITE(IVB_CHICKEN3,
7421                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7422                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7423
7424         /* WaPsdDispatchEnable:vlv */
7425         /* WaDisablePSDDualDispatchEnable:vlv */
7426         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7427                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7428                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7429
7430         /* WaDisable_RenderCache_OperationalFlush:vlv */
7431         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7432
7433         /* WaForceL3Serialization:vlv */
7434         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7435                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7436
7437         /* WaDisableDopClockGating:vlv */
7438         I915_WRITE(GEN7_ROW_CHICKEN2,
7439                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7440
7441         /* This is required by WaCatErrorRejectionIssue:vlv */
7442         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7443                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7444                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7445
7446         gen7_setup_fixed_func_scheduler(dev_priv);
7447
7448         /*
7449          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7450          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7451          */
7452         I915_WRITE(GEN6_UCGCTL2,
7453                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7454
7455         /* WaDisableL3Bank2xClockGate:vlv
7456          * Disabling L3 clock gating- MMIO 940c[25] = 1
7457          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7458         I915_WRITE(GEN7_UCGCTL4,
7459                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7460
7461         /*
7462          * BSpec says this must be set, even though
7463          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7464          */
7465         I915_WRITE(CACHE_MODE_1,
7466                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7467
7468         /*
7469          * BSpec recommends 8x4 when MSAA is used,
7470          * however in practice 16x4 seems fastest.
7471          *
7472          * Note that PS/WM thread counts depend on the WIZ hashing
7473          * disable bit, which we don't touch here, but it's good
7474          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7475          */
7476         I915_WRITE(GEN7_GT_MODE,
7477                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7478
7479         /*
7480          * WaIncreaseL3CreditsForVLVB0:vlv
7481          * This is the hardware default actually.
7482          */
7483         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7484
7485         /*
7486          * WaDisableVLVClockGating_VBIIssue:vlv
7487          * Disable clock gating on th GCFG unit to prevent a delay
7488          * in the reporting of vblank events.
7489          */
7490         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7491 }
7492
7493 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7494 {
7495         /* WaVSRefCountFullforceMissDisable:chv */
7496         /* WaDSRefCountFullforceMissDisable:chv */
7497         I915_WRITE(GEN7_FF_THREAD_MODE,
7498                    I915_READ(GEN7_FF_THREAD_MODE) &
7499                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7500
7501         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7502         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7503                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7504
7505         /* WaDisableCSUnitClockGating:chv */
7506         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7507                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7508
7509         /* WaDisableSDEUnitClockGating:chv */
7510         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7511                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7512
7513         /*
7514          * WaProgramL3SqcReg1Default:chv
7515          * See gfxspecs/Related Documents/Performance Guide/
7516          * LSQC Setting Recommendations.
7517          */
7518         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7519
7520         /*
7521          * GTT cache may not work with big pages, so if those
7522          * are ever enabled GTT cache may need to be disabled.
7523          */
7524         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7525 }
7526
7527 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7528 {
7529         uint32_t dspclk_gate;
7530
7531         I915_WRITE(RENCLK_GATE_D1, 0);
7532         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7533                    GS_UNIT_CLOCK_GATE_DISABLE |
7534                    CL_UNIT_CLOCK_GATE_DISABLE);
7535         I915_WRITE(RAMCLK_GATE_D, 0);
7536         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7537                 OVRUNIT_CLOCK_GATE_DISABLE |
7538                 OVCUNIT_CLOCK_GATE_DISABLE;
7539         if (IS_GM45(dev_priv))
7540                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7541         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7542
7543         /* WaDisableRenderCachePipelinedFlush */
7544         I915_WRITE(CACHE_MODE_0,
7545                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7546
7547         /* WaDisable_RenderCache_OperationalFlush:g4x */
7548         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7549
7550         g4x_disable_trickle_feed(dev_priv);
7551 }
7552
7553 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7554 {
7555         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7556         I915_WRITE(RENCLK_GATE_D2, 0);
7557         I915_WRITE(DSPCLK_GATE_D, 0);
7558         I915_WRITE(RAMCLK_GATE_D, 0);
7559         I915_WRITE16(DEUC, 0);
7560         I915_WRITE(MI_ARB_STATE,
7561                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7562
7563         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7564         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7565 }
7566
7567 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7568 {
7569         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7570                    I965_RCC_CLOCK_GATE_DISABLE |
7571                    I965_RCPB_CLOCK_GATE_DISABLE |
7572                    I965_ISC_CLOCK_GATE_DISABLE |
7573                    I965_FBC_CLOCK_GATE_DISABLE);
7574         I915_WRITE(RENCLK_GATE_D2, 0);
7575         I915_WRITE(MI_ARB_STATE,
7576                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7577
7578         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7579         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7580 }
7581
7582 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7583 {
7584         u32 dstate = I915_READ(D_STATE);
7585
7586         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7587                 DSTATE_DOT_CLOCK_GATING;
7588         I915_WRITE(D_STATE, dstate);
7589
7590         if (IS_PINEVIEW(dev_priv))
7591                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7592
7593         /* IIR "flip pending" means done if this bit is set */
7594         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7595
7596         /* interrupts should cause a wake up from C3 */
7597         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7598
7599         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7600         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7601
7602         I915_WRITE(MI_ARB_STATE,
7603                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7604 }
7605
7606 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7607 {
7608         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7609
7610         /* interrupts should cause a wake up from C3 */
7611         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7612                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7613
7614         I915_WRITE(MEM_MODE,
7615                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7616 }
7617
7618 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7619 {
7620         I915_WRITE(MEM_MODE,
7621                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7622                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7623 }
7624
7625 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7626 {
7627         dev_priv->display.init_clock_gating(dev_priv);
7628 }
7629
7630 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7631 {
7632         if (HAS_PCH_LPT(dev_priv))
7633                 lpt_suspend_hw(dev_priv);
7634 }
7635
7636 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7637 {
7638         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7639 }
7640
7641 /**
7642  * intel_init_clock_gating_hooks - setup the clock gating hooks
7643  * @dev_priv: device private
7644  *
7645  * Setup the hooks that configure which clocks of a given platform can be
7646  * gated and also apply various GT and display specific workarounds for these
7647  * platforms. Note that some GT specific workarounds are applied separately
7648  * when GPU contexts or batchbuffers start their execution.
7649  */
7650 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7651 {
7652         if (IS_SKYLAKE(dev_priv))
7653                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7654         else if (IS_KABYLAKE(dev_priv))
7655                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7656         else if (IS_BROXTON(dev_priv))
7657                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7658         else if (IS_GEMINILAKE(dev_priv))
7659                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
7660         else if (IS_BROADWELL(dev_priv))
7661                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7662         else if (IS_CHERRYVIEW(dev_priv))
7663                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7664         else if (IS_HASWELL(dev_priv))
7665                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7666         else if (IS_IVYBRIDGE(dev_priv))
7667                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7668         else if (IS_VALLEYVIEW(dev_priv))
7669                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7670         else if (IS_GEN6(dev_priv))
7671                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7672         else if (IS_GEN5(dev_priv))
7673                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7674         else if (IS_G4X(dev_priv))
7675                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7676         else if (IS_I965GM(dev_priv))
7677                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7678         else if (IS_I965G(dev_priv))
7679                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7680         else if (IS_GEN3(dev_priv))
7681                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7682         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7683                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7684         else if (IS_GEN2(dev_priv))
7685                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7686         else {
7687                 MISSING_CASE(INTEL_DEVID(dev_priv));
7688                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7689         }
7690 }
7691
7692 /* Set up chip specific power management-related functions */
7693 void intel_init_pm(struct drm_i915_private *dev_priv)
7694 {
7695         intel_fbc_init(dev_priv);
7696
7697         /* For cxsr */
7698         if (IS_PINEVIEW(dev_priv))
7699                 i915_pineview_get_mem_freq(dev_priv);
7700         else if (IS_GEN5(dev_priv))
7701                 i915_ironlake_get_mem_freq(dev_priv);
7702
7703         /* For FIFO watermark updates */
7704         if (INTEL_GEN(dev_priv) >= 9) {
7705                 skl_setup_wm_latency(dev_priv);
7706                 dev_priv->display.initial_watermarks = skl_initial_wm;
7707                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
7708                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7709         } else if (HAS_PCH_SPLIT(dev_priv)) {
7710                 ilk_setup_wm_latency(dev_priv);
7711
7712                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7713                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7714                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7715                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7716                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7717                         dev_priv->display.compute_intermediate_wm =
7718                                 ilk_compute_intermediate_wm;
7719                         dev_priv->display.initial_watermarks =
7720                                 ilk_initial_watermarks;
7721                         dev_priv->display.optimize_watermarks =
7722                                 ilk_optimize_watermarks;
7723                 } else {
7724                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7725                                       "Disable CxSR\n");
7726                 }
7727         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7728                 vlv_setup_wm_latency(dev_priv);
7729                 dev_priv->display.update_wm = vlv_update_wm;
7730         } else if (IS_PINEVIEW(dev_priv)) {
7731                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7732                                             dev_priv->is_ddr3,
7733                                             dev_priv->fsb_freq,
7734                                             dev_priv->mem_freq)) {
7735                         DRM_INFO("failed to find known CxSR latency "
7736                                  "(found ddr%s fsb freq %d, mem freq %d), "
7737                                  "disabling CxSR\n",
7738                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7739                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7740                         /* Disable CxSR and never update its watermark again */
7741                         intel_set_memory_cxsr(dev_priv, false);
7742                         dev_priv->display.update_wm = NULL;
7743                 } else
7744                         dev_priv->display.update_wm = pineview_update_wm;
7745         } else if (IS_G4X(dev_priv)) {
7746                 dev_priv->display.update_wm = g4x_update_wm;
7747         } else if (IS_GEN4(dev_priv)) {
7748                 dev_priv->display.update_wm = i965_update_wm;
7749         } else if (IS_GEN3(dev_priv)) {
7750                 dev_priv->display.update_wm = i9xx_update_wm;
7751                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7752         } else if (IS_GEN2(dev_priv)) {
7753                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7754                         dev_priv->display.update_wm = i845_update_wm;
7755                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7756                 } else {
7757                         dev_priv->display.update_wm = i9xx_update_wm;
7758                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7759                 }
7760         } else {
7761                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7762         }
7763 }
7764
7765 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7766 {
7767         uint32_t flags =
7768                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7769
7770         switch (flags) {
7771         case GEN6_PCODE_SUCCESS:
7772                 return 0;
7773         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7774         case GEN6_PCODE_ILLEGAL_CMD:
7775                 return -ENXIO;
7776         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7777         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7778                 return -EOVERFLOW;
7779         case GEN6_PCODE_TIMEOUT:
7780                 return -ETIMEDOUT;
7781         default:
7782                 MISSING_CASE(flags)
7783                 return 0;
7784         }
7785 }
7786
7787 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7788 {
7789         uint32_t flags =
7790                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7791
7792         switch (flags) {
7793         case GEN6_PCODE_SUCCESS:
7794                 return 0;
7795         case GEN6_PCODE_ILLEGAL_CMD:
7796                 return -ENXIO;
7797         case GEN7_PCODE_TIMEOUT:
7798                 return -ETIMEDOUT;
7799         case GEN7_PCODE_ILLEGAL_DATA:
7800                 return -EINVAL;
7801         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7802                 return -EOVERFLOW;
7803         default:
7804                 MISSING_CASE(flags);
7805                 return 0;
7806         }
7807 }
7808
7809 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7810 {
7811         int status;
7812
7813         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7814
7815         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7816          * use te fw I915_READ variants to reduce the amount of work
7817          * required when reading/writing.
7818          */
7819
7820         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7821                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7822                 return -EAGAIN;
7823         }
7824
7825         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7826         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7827         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7828
7829         if (intel_wait_for_register_fw(dev_priv,
7830                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7831                                        500)) {
7832                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7833                 return -ETIMEDOUT;
7834         }
7835
7836         *val = I915_READ_FW(GEN6_PCODE_DATA);
7837         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7838
7839         if (INTEL_GEN(dev_priv) > 6)
7840                 status = gen7_check_mailbox_status(dev_priv);
7841         else
7842                 status = gen6_check_mailbox_status(dev_priv);
7843
7844         if (status) {
7845                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7846                                  status);
7847                 return status;
7848         }
7849
7850         return 0;
7851 }
7852
7853 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7854                             u32 mbox, u32 val)
7855 {
7856         int status;
7857
7858         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7859
7860         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7861          * use te fw I915_READ variants to reduce the amount of work
7862          * required when reading/writing.
7863          */
7864
7865         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7866                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7867                 return -EAGAIN;
7868         }
7869
7870         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7871         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7872         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7873
7874         if (intel_wait_for_register_fw(dev_priv,
7875                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7876                                        500)) {
7877                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7878                 return -ETIMEDOUT;
7879         }
7880
7881         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7882
7883         if (INTEL_GEN(dev_priv) > 6)
7884                 status = gen7_check_mailbox_status(dev_priv);
7885         else
7886                 status = gen6_check_mailbox_status(dev_priv);
7887
7888         if (status) {
7889                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7890                                  status);
7891                 return status;
7892         }
7893
7894         return 0;
7895 }
7896
7897 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
7898                                   u32 request, u32 reply_mask, u32 reply,
7899                                   u32 *status)
7900 {
7901         u32 val = request;
7902
7903         *status = sandybridge_pcode_read(dev_priv, mbox, &val);
7904
7905         return *status || ((val & reply_mask) == reply);
7906 }
7907
7908 /**
7909  * skl_pcode_request - send PCODE request until acknowledgment
7910  * @dev_priv: device private
7911  * @mbox: PCODE mailbox ID the request is targeted for
7912  * @request: request ID
7913  * @reply_mask: mask used to check for request acknowledgment
7914  * @reply: value used to check for request acknowledgment
7915  * @timeout_base_ms: timeout for polling with preemption enabled
7916  *
7917  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7918  * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
7919  * The request is acknowledged once the PCODE reply dword equals @reply after
7920  * applying @reply_mask. Polling is first attempted with preemption enabled
7921  * for @timeout_base_ms and if this times out for another 50 ms with
7922  * preemption disabled.
7923  *
7924  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
7925  * other error as reported by PCODE.
7926  */
7927 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
7928                       u32 reply_mask, u32 reply, int timeout_base_ms)
7929 {
7930         u32 status;
7931         int ret;
7932
7933         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7934
7935 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
7936                                    &status)
7937
7938         /*
7939          * Prime the PCODE by doing a request first. Normally it guarantees
7940          * that a subsequent request, at most @timeout_base_ms later, succeeds.
7941          * _wait_for() doesn't guarantee when its passed condition is evaluated
7942          * first, so send the first request explicitly.
7943          */
7944         if (COND) {
7945                 ret = 0;
7946                 goto out;
7947         }
7948         ret = _wait_for(COND, timeout_base_ms * 1000, 10);
7949         if (!ret)
7950                 goto out;
7951
7952         /*
7953          * The above can time out if the number of requests was low (2 in the
7954          * worst case) _and_ PCODE was busy for some reason even after a
7955          * (queued) request and @timeout_base_ms delay. As a workaround retry
7956          * the poll with preemption disabled to maximize the number of
7957          * requests. Increase the timeout from @timeout_base_ms to 50ms to
7958          * account for interrupts that could reduce the number of these
7959          * requests, and for any quirks of the PCODE firmware that delays
7960          * the request completion.
7961          */
7962         DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
7963         WARN_ON_ONCE(timeout_base_ms > 3);
7964         preempt_disable();
7965         ret = wait_for_atomic(COND, 50);
7966         preempt_enable();
7967
7968 out:
7969         return ret ? ret : status;
7970 #undef COND
7971 }
7972
7973 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7974 {
7975         /*
7976          * N = val - 0xb7
7977          * Slow = Fast = GPLL ref * N
7978          */
7979         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7980 }
7981
7982 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7983 {
7984         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7985 }
7986
7987 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7988 {
7989         /*
7990          * N = val / 2
7991          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7992          */
7993         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7994 }
7995
7996 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7997 {
7998         /* CHV needs even values */
7999         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
8000 }
8001
8002 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
8003 {
8004         if (IS_GEN9(dev_priv))
8005                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
8006                                          GEN9_FREQ_SCALER);
8007         else if (IS_CHERRYVIEW(dev_priv))
8008                 return chv_gpu_freq(dev_priv, val);
8009         else if (IS_VALLEYVIEW(dev_priv))
8010                 return byt_gpu_freq(dev_priv, val);
8011         else
8012                 return val * GT_FREQUENCY_MULTIPLIER;
8013 }
8014
8015 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
8016 {
8017         if (IS_GEN9(dev_priv))
8018                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
8019                                          GT_FREQUENCY_MULTIPLIER);
8020         else if (IS_CHERRYVIEW(dev_priv))
8021                 return chv_freq_opcode(dev_priv, val);
8022         else if (IS_VALLEYVIEW(dev_priv))
8023                 return byt_freq_opcode(dev_priv, val);
8024         else
8025                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
8026 }
8027
8028 struct request_boost {
8029         struct work_struct work;
8030         struct drm_i915_gem_request *req;
8031 };
8032
8033 static void __intel_rps_boost_work(struct work_struct *work)
8034 {
8035         struct request_boost *boost = container_of(work, struct request_boost, work);
8036         struct drm_i915_gem_request *req = boost->req;
8037
8038         if (!i915_gem_request_completed(req))
8039                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
8040
8041         i915_gem_request_put(req);
8042         kfree(boost);
8043 }
8044
8045 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8046 {
8047         struct request_boost *boost;
8048
8049         if (req == NULL || INTEL_GEN(req->i915) < 6)
8050                 return;
8051
8052         if (i915_gem_request_completed(req))
8053                 return;
8054
8055         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8056         if (boost == NULL)
8057                 return;
8058
8059         boost->req = i915_gem_request_get(req);
8060
8061         INIT_WORK(&boost->work, __intel_rps_boost_work);
8062         queue_work(req->i915->wq, &boost->work);
8063 }
8064
8065 void intel_pm_setup(struct drm_i915_private *dev_priv)
8066 {
8067         mutex_init(&dev_priv->rps.hw_lock);
8068         spin_lock_init(&dev_priv->rps.client_lock);
8069
8070         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8071                           __intel_autoenable_gt_powersave);
8072         INIT_LIST_HEAD(&dev_priv->rps.clients);
8073
8074         dev_priv->pm.suspended = false;
8075         atomic_set(&dev_priv->pm.wakeref_count, 0);
8076 }