2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
32 #include <drm/i915_drm.h>
35 #include "i915_gem_render_state.h"
36 #include "i915_reset.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39 #include "intel_workarounds.h"
41 /* Rough estimate of the typical request size, performing a flush,
42 * set-context and then emitting the batch.
44 #define LEGACY_REQUEST_SIZE 200
46 unsigned int intel_ring_update_space(struct intel_ring *ring)
50 space = __intel_ring_space(ring->head, ring->emit, ring->size);
57 gen2_render_ring_flush(struct i915_request *rq, u32 mode)
59 unsigned int num_store_dw;
64 if (mode & EMIT_INVALIDATE)
66 if (mode & EMIT_FLUSH)
69 cs = intel_ring_begin(rq, 2 + 3 * num_store_dw);
74 while (num_store_dw--) {
75 *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
76 *cs++ = i915_scratch_offset(rq->i915);
79 *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
81 intel_ring_advance(rq, cs);
87 gen4_render_ring_flush(struct i915_request *rq, u32 mode)
95 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
96 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
97 * also flushed at 2d versus 3d pipeline switches.
101 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
102 * MI_READ_FLUSH is set, and is always flushed on 965.
104 * I915_GEM_DOMAIN_COMMAND may not exist?
106 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
107 * invalidated when MI_EXE_FLUSH is set.
109 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
110 * invalidated with every MI_FLUSH.
114 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
115 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
116 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
117 * are flushed at any MI_FLUSH.
121 if (mode & EMIT_INVALIDATE) {
123 if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5))
124 cmd |= MI_INVALIDATE_ISP;
128 if (mode & EMIT_INVALIDATE)
131 cs = intel_ring_begin(rq, i);
138 * A random delay to let the CS invalidate take effect? Without this
139 * delay, the GPU relocation path fails as the CS does not see
140 * the updated contents. Just as important, if we apply the flushes
141 * to the EMIT_FLUSH branch (i.e. immediately after the relocation
142 * write and before the invalidate on the next batch), the relocations
143 * still fail. This implies that is a delay following invalidation
144 * that is required to reset the caches as opposed to a delay to
145 * ensure the memory is written.
147 if (mode & EMIT_INVALIDATE) {
148 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
149 *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
153 for (i = 0; i < 12; i++)
156 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
157 *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
164 intel_ring_advance(rq, cs);
170 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
171 * implementing two workarounds on gen6. From section 1.4.7.1
172 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
174 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
175 * produced by non-pipelined state commands), software needs to first
176 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
179 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
180 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
182 * And the workaround for these two requires this workaround first:
184 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
185 * BEFORE the pipe-control with a post-sync op and no write-cache
188 * And this last workaround is tricky because of the requirements on
189 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
192 * "1 of the following must also be set:
193 * - Render Target Cache Flush Enable ([12] of DW1)
194 * - Depth Cache Flush Enable ([0] of DW1)
195 * - Stall at Pixel Scoreboard ([1] of DW1)
196 * - Depth Stall ([13] of DW1)
197 * - Post-Sync Operation ([13] of DW1)
198 * - Notify Enable ([8] of DW1)"
200 * The cache flushes require the workaround flush that triggered this
201 * one, so we can't use it. Depth stall would trigger the same.
202 * Post-sync nonzero is what triggered this second workaround, so we
203 * can't use that one either. Notify enable is IRQs, which aren't
204 * really our business. That leaves only stall at scoreboard.
207 gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
209 u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
212 cs = intel_ring_begin(rq, 6);
216 *cs++ = GFX_OP_PIPE_CONTROL(5);
217 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
218 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
219 *cs++ = 0; /* low dword */
220 *cs++ = 0; /* high dword */
222 intel_ring_advance(rq, cs);
224 cs = intel_ring_begin(rq, 6);
228 *cs++ = GFX_OP_PIPE_CONTROL(5);
229 *cs++ = PIPE_CONTROL_QW_WRITE;
230 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
234 intel_ring_advance(rq, cs);
240 gen6_render_ring_flush(struct i915_request *rq, u32 mode)
242 u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret = gen6_emit_post_sync_nonzero_flush(rq);
251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
255 if (mode & EMIT_FLUSH) {
256 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
257 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
262 flags |= PIPE_CONTROL_CS_STALL;
264 if (mode & EMIT_INVALIDATE) {
265 flags |= PIPE_CONTROL_TLB_INVALIDATE;
266 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
269 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
270 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
272 * TLB invalidate requires a post-sync write.
274 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
277 cs = intel_ring_begin(rq, 4);
281 *cs++ = GFX_OP_PIPE_CONTROL(4);
283 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
285 intel_ring_advance(rq, cs);
290 static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
292 /* First we do the gen6_emit_post_sync_nonzero_flush w/a */
293 *cs++ = GFX_OP_PIPE_CONTROL(4);
294 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
298 *cs++ = GFX_OP_PIPE_CONTROL(4);
299 *cs++ = PIPE_CONTROL_QW_WRITE;
300 *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
303 /* Finally we can flush and with it emit the breadcrumb */
304 *cs++ = GFX_OP_PIPE_CONTROL(4);
305 *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
306 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
307 PIPE_CONTROL_DC_FLUSH_ENABLE |
308 PIPE_CONTROL_QW_WRITE |
309 PIPE_CONTROL_CS_STALL);
310 *cs++ = rq->timeline->hwsp_offset | PIPE_CONTROL_GLOBAL_GTT;
311 *cs++ = rq->fence.seqno;
313 *cs++ = GFX_OP_PIPE_CONTROL(4);
314 *cs++ = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_STORE_DATA_INDEX;
315 *cs++ = I915_GEM_HWS_HANGCHECK_ADDR | PIPE_CONTROL_GLOBAL_GTT;
316 *cs++ = intel_engine_next_hangcheck_seqno(rq->engine);
318 *cs++ = MI_USER_INTERRUPT;
321 rq->tail = intel_ring_offset(rq, cs);
322 assert_ring_tail_valid(rq->ring, rq->tail);
328 gen7_render_ring_cs_stall_wa(struct i915_request *rq)
332 cs = intel_ring_begin(rq, 4);
336 *cs++ = GFX_OP_PIPE_CONTROL(4);
337 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
340 intel_ring_advance(rq, cs);
346 gen7_render_ring_flush(struct i915_request *rq, u32 mode)
348 u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
359 flags |= PIPE_CONTROL_CS_STALL;
361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
365 if (mode & EMIT_FLUSH) {
366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
368 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
369 flags |= PIPE_CONTROL_FLUSH_ENABLE;
371 if (mode & EMIT_INVALIDATE) {
372 flags |= PIPE_CONTROL_TLB_INVALIDATE;
373 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
374 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
375 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
376 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
377 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
378 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
380 * TLB invalidate requires a post-sync write.
382 flags |= PIPE_CONTROL_QW_WRITE;
383 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
385 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
387 /* Workaround: we must issue a pipe_control with CS-stall bit
388 * set before a pipe_control command that has the state cache
389 * invalidate bit set. */
390 gen7_render_ring_cs_stall_wa(rq);
393 cs = intel_ring_begin(rq, 4);
397 *cs++ = GFX_OP_PIPE_CONTROL(4);
399 *cs++ = scratch_addr;
401 intel_ring_advance(rq, cs);
406 static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
408 *cs++ = GFX_OP_PIPE_CONTROL(4);
409 *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
410 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
411 PIPE_CONTROL_DC_FLUSH_ENABLE |
412 PIPE_CONTROL_FLUSH_ENABLE |
413 PIPE_CONTROL_QW_WRITE |
414 PIPE_CONTROL_GLOBAL_GTT_IVB |
415 PIPE_CONTROL_CS_STALL);
416 *cs++ = rq->timeline->hwsp_offset;
417 *cs++ = rq->fence.seqno;
419 *cs++ = GFX_OP_PIPE_CONTROL(4);
420 *cs++ = (PIPE_CONTROL_QW_WRITE |
421 PIPE_CONTROL_STORE_DATA_INDEX |
422 PIPE_CONTROL_GLOBAL_GTT_IVB);
423 *cs++ = I915_GEM_HWS_HANGCHECK_ADDR;
424 *cs++ = intel_engine_next_hangcheck_seqno(rq->engine);
426 *cs++ = MI_USER_INTERRUPT;
429 rq->tail = intel_ring_offset(rq, cs);
430 assert_ring_tail_valid(rq->ring, rq->tail);
435 static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
437 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
438 GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
440 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
441 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
442 *cs++ = rq->fence.seqno;
444 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
445 *cs++ = I915_GEM_HWS_HANGCHECK_ADDR | MI_FLUSH_DW_USE_GTT;
446 *cs++ = intel_engine_next_hangcheck_seqno(rq->engine);
448 *cs++ = MI_USER_INTERRUPT;
451 rq->tail = intel_ring_offset(rq, cs);
452 assert_ring_tail_valid(rq->ring, rq->tail);
457 #define GEN7_XCS_WA 32
458 static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
462 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
463 GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
465 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
466 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
467 *cs++ = rq->fence.seqno;
469 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
470 *cs++ = I915_GEM_HWS_HANGCHECK_ADDR | MI_FLUSH_DW_USE_GTT;
471 *cs++ = intel_engine_next_hangcheck_seqno(rq->engine);
473 for (i = 0; i < GEN7_XCS_WA; i++) {
474 *cs++ = MI_STORE_DWORD_INDEX;
475 *cs++ = I915_GEM_HWS_SEQNO_ADDR;
476 *cs++ = rq->fence.seqno;
483 *cs++ = MI_USER_INTERRUPT;
485 rq->tail = intel_ring_offset(rq, cs);
486 assert_ring_tail_valid(rq->ring, rq->tail);
492 static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
495 * Keep the render interrupt unmasked as this papers over
496 * lost interrupts following a reset.
498 if (engine->class == RENDER_CLASS) {
499 if (INTEL_GEN(engine->i915) >= 6)
502 mask &= ~I915_USER_INTERRUPT;
505 intel_engine_set_hwsp_writemask(engine, mask);
508 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
510 struct drm_i915_private *dev_priv = engine->i915;
513 addr = lower_32_bits(phys);
514 if (INTEL_GEN(dev_priv) >= 4)
515 addr |= (phys >> 28) & 0xf0;
517 I915_WRITE(HWS_PGA, addr);
520 static struct page *status_page(struct intel_engine_cs *engine)
522 struct drm_i915_gem_object *obj = engine->status_page.vma->obj;
524 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
525 return sg_page(obj->mm.pages->sgl);
528 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
530 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));
531 set_hwstam(engine, ~0u);
534 static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
536 struct drm_i915_private *dev_priv = engine->i915;
540 * The ring status page addresses are no longer next to the rest of
541 * the ring registers as of gen7.
543 if (IS_GEN(dev_priv, 7)) {
544 switch (engine->id) {
546 * No more rings exist on Gen7. Default case is only to shut up
547 * gcc switch check warning.
550 GEM_BUG_ON(engine->id);
553 hwsp = RENDER_HWS_PGA_GEN7;
556 hwsp = BLT_HWS_PGA_GEN7;
559 hwsp = BSD_HWS_PGA_GEN7;
562 hwsp = VEBOX_HWS_PGA_GEN7;
565 } else if (IS_GEN(dev_priv, 6)) {
566 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
568 hwsp = RING_HWS_PGA(engine->mmio_base);
571 I915_WRITE(hwsp, offset);
575 static void flush_cs_tlb(struct intel_engine_cs *engine)
577 struct drm_i915_private *dev_priv = engine->i915;
579 if (!IS_GEN_RANGE(dev_priv, 6, 7))
582 /* ring should be idle before issuing a sync flush*/
583 WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
585 ENGINE_WRITE(engine, RING_INSTPM,
586 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
588 if (intel_wait_for_register(engine->uncore,
589 RING_INSTPM(engine->mmio_base),
590 INSTPM_SYNC_FLUSH, 0,
592 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
596 static void ring_setup_status_page(struct intel_engine_cs *engine)
598 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));
599 set_hwstam(engine, ~0u);
601 flush_cs_tlb(engine);
604 static bool stop_ring(struct intel_engine_cs *engine)
606 struct drm_i915_private *dev_priv = engine->i915;
608 if (INTEL_GEN(dev_priv) > 2) {
610 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
611 if (intel_wait_for_register(engine->uncore,
612 RING_MI_MODE(engine->mmio_base),
616 DRM_ERROR("%s : timed out trying to stop ring\n",
620 * Sometimes we observe that the idle flag is not
621 * set even though the ring is empty. So double
622 * check before giving up.
624 if (ENGINE_READ(engine, RING_HEAD) !=
625 ENGINE_READ(engine, RING_TAIL))
630 ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
632 ENGINE_WRITE(engine, RING_HEAD, 0);
633 ENGINE_WRITE(engine, RING_TAIL, 0);
635 /* The ring must be empty before it is disabled */
636 ENGINE_WRITE(engine, RING_CTL, 0);
638 return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
641 static int init_ring_common(struct intel_engine_cs *engine)
643 struct drm_i915_private *dev_priv = engine->i915;
644 struct intel_ring *ring = engine->buffer;
647 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
649 if (!stop_ring(engine)) {
650 /* G45 ring initialization often fails to reset head to zero */
651 DRM_DEBUG_DRIVER("%s head not reset to zero "
652 "ctl %08x head %08x tail %08x start %08x\n",
654 ENGINE_READ(engine, RING_CTL),
655 ENGINE_READ(engine, RING_HEAD),
656 ENGINE_READ(engine, RING_TAIL),
657 ENGINE_READ(engine, RING_START));
659 if (!stop_ring(engine)) {
660 DRM_ERROR("failed to set %s head to zero "
661 "ctl %08x head %08x tail %08x start %08x\n",
663 ENGINE_READ(engine, RING_CTL),
664 ENGINE_READ(engine, RING_HEAD),
665 ENGINE_READ(engine, RING_TAIL),
666 ENGINE_READ(engine, RING_START));
672 if (HWS_NEEDS_PHYSICAL(dev_priv))
673 ring_setup_phys_status_page(engine);
675 ring_setup_status_page(engine);
677 intel_engine_reset_breadcrumbs(engine);
679 /* Enforce ordering by reading HEAD register back */
680 ENGINE_READ(engine, RING_HEAD);
682 /* Initialize the ring. This must happen _after_ we've cleared the ring
683 * registers with the above sequence (the readback of the HEAD registers
684 * also enforces ordering), otherwise the hw might lose the new ring
685 * register values. */
686 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma));
688 /* WaClearRingBufHeadRegAtInit:ctg,elk */
689 if (ENGINE_READ(engine, RING_HEAD))
690 DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n",
691 engine->name, ENGINE_READ(engine, RING_HEAD));
693 /* Check that the ring offsets point within the ring! */
694 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
695 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
696 intel_ring_update_space(ring);
698 /* First wake the ring up to an empty/idle ring */
699 ENGINE_WRITE(engine, RING_HEAD, ring->head);
700 ENGINE_WRITE(engine, RING_TAIL, ring->head);
701 ENGINE_POSTING_READ(engine, RING_TAIL);
703 ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID);
705 /* If the head is still not zero, the ring is dead */
706 if (intel_wait_for_register(engine->uncore,
707 RING_CTL(engine->mmio_base),
708 RING_VALID, RING_VALID,
710 DRM_ERROR("%s initialization failed "
711 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
713 ENGINE_READ(engine, RING_CTL),
714 ENGINE_READ(engine, RING_CTL) & RING_VALID,
715 ENGINE_READ(engine, RING_HEAD), ring->head,
716 ENGINE_READ(engine, RING_TAIL), ring->tail,
717 ENGINE_READ(engine, RING_START),
718 i915_ggtt_offset(ring->vma));
723 if (INTEL_GEN(dev_priv) > 2)
725 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
727 /* Now awake, let it get started */
728 if (ring->tail != ring->head) {
729 ENGINE_WRITE(engine, RING_TAIL, ring->tail);
730 ENGINE_POSTING_READ(engine, RING_TAIL);
733 /* Papering over lost _interrupts_ immediately following the restart */
734 intel_engine_queue_breadcrumbs(engine);
736 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
741 static void reset_prepare(struct intel_engine_cs *engine)
743 intel_engine_stop_cs(engine);
746 static void reset_ring(struct intel_engine_cs *engine, bool stalled)
748 struct i915_timeline *tl = &engine->timeline;
749 struct i915_request *pos, *rq;
754 spin_lock_irqsave(&tl->lock, flags);
755 list_for_each_entry(pos, &tl->requests, link) {
756 if (!i915_request_completed(pos)) {
763 * The guilty request will get skipped on a hung engine.
765 * Users of client default contexts do not rely on logical
766 * state preserved between batches so it is safe to execute
767 * queued requests following the hang. Non default contexts
768 * rely on preserved state, so skipping a batch loses the
769 * evolution of the state and it needs to be considered corrupted.
770 * Executing more queued batches on top of corrupted state is
771 * risky. But we take the risk by trying to advance through
772 * the queued requests in order to make the client behaviour
773 * more predictable around resets, by not throwing away random
774 * amount of batches it has prepared for execution. Sophisticated
775 * clients can use gem_reset_stats_ioctl and dma fence status
776 * (exported via sync_file info ioctl on explicit fences) to observe
777 * when it loses the context state and should rebuild accordingly.
779 * The context ban, and ultimately the client ban, mechanism are safety
780 * valves if client submission ends up resulting in nothing more than
786 * Try to restore the logical GPU state to match the
787 * continuation of the request queue. If we skip the
788 * context/PD restore, then the next request may try to execute
789 * assuming that its context is valid and loaded on the GPU and
790 * so may try to access invalid memory, prompting repeated GPU
793 * If the request was guilty, we still restore the logical
794 * state in case the next request requires it (e.g. the
795 * aliasing ppgtt), but skip over the hung batch.
797 * If the request was innocent, we try to replay the request
798 * with the restored context.
800 i915_reset_request(rq, stalled);
802 GEM_BUG_ON(rq->ring != engine->buffer);
805 head = engine->buffer->tail;
807 engine->buffer->head = intel_ring_wrap(engine->buffer, head);
809 spin_unlock_irqrestore(&tl->lock, flags);
812 static void reset_finish(struct intel_engine_cs *engine)
816 static int intel_rcs_ctx_init(struct i915_request *rq)
820 ret = intel_engine_emit_ctx_wa(rq);
824 ret = i915_gem_render_state_emit(rq);
831 static int init_render_ring(struct intel_engine_cs *engine)
833 struct drm_i915_private *dev_priv = engine->i915;
834 int ret = init_ring_common(engine);
838 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
839 if (IS_GEN_RANGE(dev_priv, 4, 6))
840 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
842 /* We need to disable the AsyncFlip performance optimisations in order
843 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
844 * programmed to '1' on all products.
846 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
848 if (IS_GEN_RANGE(dev_priv, 6, 7))
849 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
851 /* Required for the hardware to program scanline values for waiting */
852 /* WaEnableFlushTlbInvalidationMode:snb */
853 if (IS_GEN(dev_priv, 6))
855 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
857 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
858 if (IS_GEN(dev_priv, 7))
859 I915_WRITE(GFX_MODE_GEN7,
860 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
861 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
863 if (IS_GEN(dev_priv, 6)) {
864 /* From the Sandybridge PRM, volume 1 part 3, page 24:
865 * "If this bit is set, STCunit will have LRA as replacement
866 * policy. [...] This bit must be reset. LRA replacement
867 * policy is not supported."
869 I915_WRITE(CACHE_MODE_0,
870 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
873 if (IS_GEN_RANGE(dev_priv, 6, 7))
874 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
876 if (INTEL_GEN(dev_priv) >= 6)
877 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
882 static void cancel_requests(struct intel_engine_cs *engine)
884 struct i915_request *request;
887 spin_lock_irqsave(&engine->timeline.lock, flags);
889 /* Mark all submitted requests as skipped. */
890 list_for_each_entry(request, &engine->timeline.requests, link) {
891 if (!i915_request_signaled(request))
892 dma_fence_set_error(&request->fence, -EIO);
894 i915_request_mark_complete(request);
897 /* Remaining _unready_ requests will be nop'ed when submitted */
899 spin_unlock_irqrestore(&engine->timeline.lock, flags);
902 static void i9xx_submit_request(struct i915_request *request)
904 i915_request_submit(request);
906 ENGINE_WRITE(request->engine, RING_TAIL,
907 intel_ring_set_tail(request->ring, request->tail));
910 static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
912 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
913 GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
917 *cs++ = MI_STORE_DWORD_INDEX;
918 *cs++ = I915_GEM_HWS_SEQNO_ADDR;
919 *cs++ = rq->fence.seqno;
921 *cs++ = MI_STORE_DWORD_INDEX;
922 *cs++ = I915_GEM_HWS_HANGCHECK_ADDR;
923 *cs++ = intel_engine_next_hangcheck_seqno(rq->engine);
925 *cs++ = MI_USER_INTERRUPT;
927 rq->tail = intel_ring_offset(rq, cs);
928 assert_ring_tail_valid(rq->ring, rq->tail);
933 #define GEN5_WA_STORES 8 /* must be at least 1! */
934 static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
938 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
939 GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
943 *cs++ = MI_STORE_DWORD_INDEX;
944 *cs++ = I915_GEM_HWS_HANGCHECK_ADDR;
945 *cs++ = intel_engine_next_hangcheck_seqno(rq->engine);
947 BUILD_BUG_ON(GEN5_WA_STORES < 1);
948 for (i = 0; i < GEN5_WA_STORES; i++) {
949 *cs++ = MI_STORE_DWORD_INDEX;
950 *cs++ = I915_GEM_HWS_SEQNO_ADDR;
951 *cs++ = rq->fence.seqno;
954 *cs++ = MI_USER_INTERRUPT;
957 rq->tail = intel_ring_offset(rq, cs);
958 assert_ring_tail_valid(rq->ring, rq->tail);
962 #undef GEN5_WA_STORES
965 gen5_irq_enable(struct intel_engine_cs *engine)
967 gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
971 gen5_irq_disable(struct intel_engine_cs *engine)
973 gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
977 i9xx_irq_enable(struct intel_engine_cs *engine)
979 GEM_BUG_ON(engine->id != RCS0);
981 engine->i915->irq_mask &= ~engine->irq_enable_mask;
982 ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
983 ENGINE_POSTING_READ(engine, RING_IMR);
987 i9xx_irq_disable(struct intel_engine_cs *engine)
989 GEM_BUG_ON(engine->id != RCS0);
991 engine->i915->irq_mask |= engine->irq_enable_mask;
992 ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
996 i8xx_irq_enable(struct intel_engine_cs *engine)
998 struct drm_i915_private *dev_priv = engine->i915;
1000 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1001 I915_WRITE16(IMR, dev_priv->irq_mask);
1002 POSTING_READ16(RING_IMR(engine->mmio_base));
1006 i8xx_irq_disable(struct intel_engine_cs *engine)
1008 struct drm_i915_private *dev_priv = engine->i915;
1010 dev_priv->irq_mask |= engine->irq_enable_mask;
1011 I915_WRITE16(IMR, dev_priv->irq_mask);
1015 bsd_ring_flush(struct i915_request *rq, u32 mode)
1019 cs = intel_ring_begin(rq, 2);
1025 intel_ring_advance(rq, cs);
1030 gen6_irq_enable(struct intel_engine_cs *engine)
1032 ENGINE_WRITE(engine, RING_IMR,
1033 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1035 /* Flush/delay to ensure the RING_IMR is active before the GT IMR */
1036 ENGINE_POSTING_READ(engine, RING_IMR);
1038 gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
1042 gen6_irq_disable(struct intel_engine_cs *engine)
1044 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
1045 gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
1049 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
1051 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);
1053 /* Flush/delay to ensure the RING_IMR is active before the GT IMR */
1054 ENGINE_POSTING_READ(engine, RING_IMR);
1056 gen6_unmask_pm_irq(engine->i915, engine->irq_enable_mask);
1060 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
1062 ENGINE_WRITE(engine, RING_IMR, ~0);
1063 gen6_mask_pm_irq(engine->i915, engine->irq_enable_mask);
1067 i965_emit_bb_start(struct i915_request *rq,
1068 u64 offset, u32 length,
1069 unsigned int dispatch_flags)
1073 cs = intel_ring_begin(rq, 2);
1077 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
1078 I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
1080 intel_ring_advance(rq, cs);
1085 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1086 #define I830_BATCH_LIMIT SZ_256K
1087 #define I830_TLB_ENTRIES (2)
1088 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1090 i830_emit_bb_start(struct i915_request *rq,
1091 u64 offset, u32 len,
1092 unsigned int dispatch_flags)
1094 u32 *cs, cs_offset = i915_scratch_offset(rq->i915);
1096 GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE);
1098 cs = intel_ring_begin(rq, 6);
1102 /* Evict the invalid PTE TLBs */
1103 *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
1104 *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
1105 *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
1109 intel_ring_advance(rq, cs);
1111 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1112 if (len > I830_BATCH_LIMIT)
1115 cs = intel_ring_begin(rq, 6 + 2);
1119 /* Blit the batch (which has now all relocs applied) to the
1120 * stable batch scratch bo area (so that the CS never
1121 * stumbles over its tlb invalidation bug) ...
1123 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
1124 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
1125 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
1132 intel_ring_advance(rq, cs);
1134 /* ... and execute it. */
1138 cs = intel_ring_begin(rq, 2);
1142 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1143 *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1144 MI_BATCH_NON_SECURE);
1145 intel_ring_advance(rq, cs);
1151 i915_emit_bb_start(struct i915_request *rq,
1152 u64 offset, u32 len,
1153 unsigned int dispatch_flags)
1157 cs = intel_ring_begin(rq, 2);
1161 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1162 *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1163 MI_BATCH_NON_SECURE);
1164 intel_ring_advance(rq, cs);
1169 int intel_ring_pin(struct intel_ring *ring)
1171 struct i915_vma *vma = ring->vma;
1172 enum i915_map_type map = i915_coherent_map_type(vma->vm->i915);
1177 GEM_BUG_ON(ring->vaddr);
1179 ret = i915_timeline_pin(ring->timeline);
1185 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1186 flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
1188 if (vma->obj->stolen)
1189 flags |= PIN_MAPPABLE;
1193 ret = i915_vma_pin(vma, 0, 0, flags);
1195 goto unpin_timeline;
1197 if (i915_vma_is_map_and_fenceable(vma))
1198 addr = (void __force *)i915_vma_pin_iomap(vma);
1200 addr = i915_gem_object_pin_map(vma->obj, map);
1202 ret = PTR_ERR(addr);
1206 vma->obj->pin_global++;
1212 i915_vma_unpin(vma);
1214 i915_timeline_unpin(ring->timeline);
1218 void intel_ring_reset(struct intel_ring *ring, u32 tail)
1220 GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
1225 intel_ring_update_space(ring);
1228 void intel_ring_unpin(struct intel_ring *ring)
1230 GEM_BUG_ON(!ring->vma);
1231 GEM_BUG_ON(!ring->vaddr);
1233 /* Discard any unused bytes beyond that submitted to hw. */
1234 intel_ring_reset(ring, ring->tail);
1236 if (i915_vma_is_map_and_fenceable(ring->vma))
1237 i915_vma_unpin_iomap(ring->vma);
1239 i915_gem_object_unpin_map(ring->vma->obj);
1242 ring->vma->obj->pin_global--;
1243 i915_vma_unpin(ring->vma);
1245 i915_timeline_unpin(ring->timeline);
1248 static struct i915_vma *
1249 intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1251 struct i915_address_space *vm = &dev_priv->ggtt.vm;
1252 struct drm_i915_gem_object *obj;
1253 struct i915_vma *vma;
1255 obj = i915_gem_object_create_stolen(dev_priv, size);
1257 obj = i915_gem_object_create_internal(dev_priv, size);
1259 return ERR_CAST(obj);
1262 * Mark ring buffers as read-only from GPU side (so no stray overwrites)
1263 * if supported by the platform's GGTT.
1265 if (vm->has_read_only)
1266 i915_gem_object_set_readonly(obj);
1268 vma = i915_vma_instance(obj, vm, NULL);
1275 i915_gem_object_put(obj);
1280 intel_engine_create_ring(struct intel_engine_cs *engine,
1281 struct i915_timeline *timeline,
1284 struct intel_ring *ring;
1285 struct i915_vma *vma;
1287 GEM_BUG_ON(!is_power_of_2(size));
1288 GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1289 GEM_BUG_ON(timeline == &engine->timeline);
1290 lockdep_assert_held(&engine->i915->drm.struct_mutex);
1292 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1294 return ERR_PTR(-ENOMEM);
1296 kref_init(&ring->ref);
1297 INIT_LIST_HEAD(&ring->request_list);
1298 ring->timeline = i915_timeline_get(timeline);
1301 /* Workaround an erratum on the i830 which causes a hang if
1302 * the TAIL pointer points to within the last 2 cachelines
1305 ring->effective_size = size;
1306 if (IS_I830(engine->i915) || IS_I845G(engine->i915))
1307 ring->effective_size -= 2 * CACHELINE_BYTES;
1309 intel_ring_update_space(ring);
1311 vma = intel_ring_create_vma(engine->i915, size);
1314 return ERR_CAST(vma);
1321 void intel_ring_free(struct kref *ref)
1323 struct intel_ring *ring = container_of(ref, typeof(*ring), ref);
1324 struct drm_i915_gem_object *obj = ring->vma->obj;
1326 i915_vma_close(ring->vma);
1327 __i915_gem_object_release_unless_active(obj);
1329 i915_timeline_put(ring->timeline);
1333 static void __ring_context_fini(struct intel_context *ce)
1335 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1336 i915_gem_object_put(ce->state->obj);
1339 static void ring_context_destroy(struct kref *ref)
1341 struct intel_context *ce = container_of(ref, typeof(*ce), ref);
1343 GEM_BUG_ON(intel_context_is_pinned(ce));
1346 __ring_context_fini(ce);
1348 intel_context_free(ce);
1351 static int __context_pin_ppgtt(struct i915_gem_context *ctx)
1353 struct i915_hw_ppgtt *ppgtt;
1356 ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
1358 err = gen6_ppgtt_pin(ppgtt);
1363 static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
1365 struct i915_hw_ppgtt *ppgtt;
1367 ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
1369 gen6_ppgtt_unpin(ppgtt);
1372 static int __context_pin(struct intel_context *ce)
1374 struct i915_vma *vma;
1381 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
1386 * And mark is as a globally pinned object to let the shrinker know
1387 * it cannot reclaim the object until we release it.
1389 vma->obj->pin_global++;
1390 vma->obj->mm.dirty = true;
1395 static void __context_unpin(struct intel_context *ce)
1397 struct i915_vma *vma;
1403 vma->obj->pin_global--;
1404 i915_vma_unpin(vma);
1407 static void ring_context_unpin(struct intel_context *ce)
1409 __context_unpin_ppgtt(ce->gem_context);
1410 __context_unpin(ce);
1413 static struct i915_vma *
1414 alloc_context_vma(struct intel_engine_cs *engine)
1416 struct drm_i915_private *i915 = engine->i915;
1417 struct drm_i915_gem_object *obj;
1418 struct i915_vma *vma;
1421 obj = i915_gem_object_create(i915, engine->context_size);
1423 return ERR_CAST(obj);
1426 * Try to make the context utilize L3 as well as LLC.
1428 * On VLV we don't have L3 controls in the PTEs so we
1429 * shouldn't touch the cache level, especially as that
1430 * would make the object snooped which might have a
1431 * negative performance impact.
1433 * Snooping is required on non-llc platforms in execlist
1434 * mode, but since all GGTT accesses use PAT entry 0 we
1435 * get snooping anyway regardless of cache_level.
1437 * This is only applicable for Ivy Bridge devices since
1438 * later platforms don't have L3 control bits in the PTE.
1440 if (IS_IVYBRIDGE(i915))
1441 i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC);
1443 if (engine->default_state) {
1444 void *defaults, *vaddr;
1446 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1447 if (IS_ERR(vaddr)) {
1448 err = PTR_ERR(vaddr);
1452 defaults = i915_gem_object_pin_map(engine->default_state,
1454 if (IS_ERR(defaults)) {
1455 err = PTR_ERR(defaults);
1459 memcpy(vaddr, defaults, engine->context_size);
1460 i915_gem_object_unpin_map(engine->default_state);
1462 i915_gem_object_flush_map(obj);
1463 i915_gem_object_unpin_map(obj);
1466 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1475 i915_gem_object_unpin_map(obj);
1477 i915_gem_object_put(obj);
1478 return ERR_PTR(err);
1481 static int ring_context_pin(struct intel_context *ce)
1483 struct intel_engine_cs *engine = ce->engine;
1486 /* One ringbuffer to rule them all */
1487 GEM_BUG_ON(!engine->buffer);
1488 ce->ring = engine->buffer;
1490 if (!ce->state && engine->context_size) {
1491 struct i915_vma *vma;
1493 vma = alloc_context_vma(engine);
1495 return PTR_ERR(vma);
1500 err = __context_pin(ce);
1504 err = __context_pin_ppgtt(ce->gem_context);
1511 __context_unpin(ce);
1515 static const struct intel_context_ops ring_context_ops = {
1516 .pin = ring_context_pin,
1517 .unpin = ring_context_unpin,
1518 .destroy = ring_context_destroy,
1521 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1523 struct i915_timeline *timeline;
1524 struct intel_ring *ring;
1527 err = intel_engine_setup_common(engine);
1531 timeline = i915_timeline_create(engine->i915, engine->status_page.vma);
1532 if (IS_ERR(timeline)) {
1533 err = PTR_ERR(timeline);
1536 GEM_BUG_ON(timeline->has_initial_breadcrumb);
1538 ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
1539 i915_timeline_put(timeline);
1541 err = PTR_ERR(ring);
1545 err = intel_ring_pin(ring);
1549 GEM_BUG_ON(engine->buffer);
1550 engine->buffer = ring;
1552 err = intel_engine_init_common(engine);
1556 GEM_BUG_ON(ring->timeline->hwsp_ggtt != engine->status_page.vma);
1561 intel_ring_unpin(ring);
1563 intel_ring_put(ring);
1565 intel_engine_cleanup_common(engine);
1569 void intel_engine_cleanup(struct intel_engine_cs *engine)
1571 struct drm_i915_private *dev_priv = engine->i915;
1573 WARN_ON(INTEL_GEN(dev_priv) > 2 &&
1574 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
1576 intel_ring_unpin(engine->buffer);
1577 intel_ring_put(engine->buffer);
1579 if (engine->cleanup)
1580 engine->cleanup(engine);
1582 intel_engine_cleanup_common(engine);
1584 dev_priv->engine[engine->id] = NULL;
1588 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
1590 struct intel_engine_cs *engine;
1591 enum intel_engine_id id;
1593 /* Restart from the beginning of the rings for convenience */
1594 for_each_engine(engine, dev_priv, id)
1595 intel_ring_reset(engine->buffer, 0);
1598 static int load_pd_dir(struct i915_request *rq,
1599 const struct i915_hw_ppgtt *ppgtt)
1601 const struct intel_engine_cs * const engine = rq->engine;
1604 cs = intel_ring_begin(rq, 6);
1608 *cs++ = MI_LOAD_REGISTER_IMM(1);
1609 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
1610 *cs++ = PP_DIR_DCLV_2G;
1612 *cs++ = MI_LOAD_REGISTER_IMM(1);
1613 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
1614 *cs++ = ppgtt->pd.base.ggtt_offset << 10;
1616 intel_ring_advance(rq, cs);
1621 static int flush_pd_dir(struct i915_request *rq)
1623 const struct intel_engine_cs * const engine = rq->engine;
1626 cs = intel_ring_begin(rq, 4);
1630 /* Stall until the page table load is complete */
1631 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1632 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
1633 *cs++ = i915_scratch_offset(rq->i915);
1636 intel_ring_advance(rq, cs);
1640 static inline int mi_set_context(struct i915_request *rq, u32 flags)
1642 struct drm_i915_private *i915 = rq->i915;
1643 struct intel_engine_cs *engine = rq->engine;
1644 enum intel_engine_id id;
1645 const int num_engines =
1646 IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0;
1647 bool force_restore = false;
1651 flags |= MI_MM_SPACE_GTT;
1652 if (IS_HASWELL(i915))
1653 /* These flags are for resource streamer on HSW+ */
1654 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
1656 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1659 if (IS_GEN(i915, 7))
1660 len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
1661 if (flags & MI_FORCE_RESTORE) {
1662 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
1663 flags &= ~MI_FORCE_RESTORE;
1664 force_restore = true;
1668 cs = intel_ring_begin(rq, len);
1672 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1673 if (IS_GEN(i915, 7)) {
1674 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1676 struct intel_engine_cs *signaller;
1678 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
1679 for_each_engine(signaller, i915, id) {
1680 if (signaller == engine)
1683 *cs++ = i915_mmio_reg_offset(
1684 RING_PSMI_CTL(signaller->mmio_base));
1685 *cs++ = _MASKED_BIT_ENABLE(
1686 GEN6_PSMI_SLEEP_MSG_DISABLE);
1691 if (force_restore) {
1693 * The HW doesn't handle being told to restore the current
1694 * context very well. Quite often it likes goes to go off and
1695 * sulk, especially when it is meant to be reloading PP_DIR.
1696 * A very simple fix to force the reload is to simply switch
1697 * away from the current context and back again.
1699 * Note that the kernel_context will contain random state
1700 * following the INHIBIT_RESTORE. We accept this since we
1701 * never use the kernel_context state; it is merely a
1702 * placeholder we use to flush other contexts.
1704 *cs++ = MI_SET_CONTEXT;
1705 *cs++ = i915_ggtt_offset(engine->kernel_context->state) |
1711 *cs++ = MI_SET_CONTEXT;
1712 *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
1714 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
1715 * WaMiSetContext_Hang:snb,ivb,vlv
1719 if (IS_GEN(i915, 7)) {
1721 struct intel_engine_cs *signaller;
1722 i915_reg_t last_reg = {}; /* keep gcc quiet */
1724 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
1725 for_each_engine(signaller, i915, id) {
1726 if (signaller == engine)
1729 last_reg = RING_PSMI_CTL(signaller->mmio_base);
1730 *cs++ = i915_mmio_reg_offset(last_reg);
1731 *cs++ = _MASKED_BIT_DISABLE(
1732 GEN6_PSMI_SLEEP_MSG_DISABLE);
1735 /* Insert a delay before the next switch! */
1736 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1737 *cs++ = i915_mmio_reg_offset(last_reg);
1738 *cs++ = i915_scratch_offset(rq->i915);
1741 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1744 intel_ring_advance(rq, cs);
1749 static int remap_l3(struct i915_request *rq, int slice)
1751 u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
1757 cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
1762 * Note: We do not worry about the concurrent register cacheline hang
1763 * here because no other code should access these registers other than
1764 * at initialization time.
1766 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
1767 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
1768 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
1769 *cs++ = remap_info[i];
1772 intel_ring_advance(rq, cs);
1777 static int switch_context(struct i915_request *rq)
1779 struct intel_engine_cs *engine = rq->engine;
1780 struct i915_gem_context *ctx = rq->gem_context;
1781 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
1782 unsigned int unwind_mm = 0;
1786 lockdep_assert_held(&rq->i915->drm.struct_mutex);
1787 GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
1793 * Baytail takes a little more convincing that it really needs
1794 * to reload the PD between contexts. It is not just a little
1795 * longer, as adding more stalls after the load_pd_dir (i.e.
1796 * adding a long loop around flush_pd_dir) is not as effective
1797 * as reloading the PD umpteen times. 32 is derived from
1798 * experimentation (gem_exec_parallel/fds) and has no good
1802 if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915))
1806 ret = load_pd_dir(rq, ppgtt);
1811 if (ppgtt->pd_dirty_engines & engine->mask) {
1812 unwind_mm = engine->mask;
1813 ppgtt->pd_dirty_engines &= ~unwind_mm;
1814 hw_flags = MI_FORCE_RESTORE;
1818 if (rq->hw_context->state) {
1819 GEM_BUG_ON(engine->id != RCS0);
1822 * The kernel context(s) is treated as pure scratch and is not
1823 * expected to retain any state (as we sacrifice it during
1824 * suspend and on resume it may be corrupted). This is ok,
1825 * as nothing actually executes using the kernel context; it
1826 * is purely used for flushing user contexts.
1828 if (i915_gem_context_is_kernel(ctx))
1829 hw_flags = MI_RESTORE_INHIBIT;
1831 ret = mi_set_context(rq, hw_flags);
1837 ret = engine->emit_flush(rq, EMIT_INVALIDATE);
1841 ret = flush_pd_dir(rq);
1846 * Not only do we need a full barrier (post-sync write) after
1847 * invalidating the TLBs, but we need to wait a little bit
1848 * longer. Whether this is merely delaying us, or the
1849 * subsequent flush is a key part of serialising with the
1850 * post-sync op, this extra pass appears vital before a
1853 ret = engine->emit_flush(rq, EMIT_INVALIDATE);
1857 ret = engine->emit_flush(rq, EMIT_FLUSH);
1862 if (ctx->remap_slice) {
1863 for (i = 0; i < MAX_L3_SLICES; i++) {
1864 if (!(ctx->remap_slice & BIT(i)))
1867 ret = remap_l3(rq, i);
1872 ctx->remap_slice = 0;
1879 ppgtt->pd_dirty_engines |= unwind_mm;
1884 static int ring_request_alloc(struct i915_request *request)
1888 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context));
1889 GEM_BUG_ON(request->timeline->has_initial_breadcrumb);
1892 * Flush enough space to reduce the likelihood of waiting after
1893 * we start building the request - in which case we will just
1894 * have to repeat work.
1896 request->reserved_space += LEGACY_REQUEST_SIZE;
1898 ret = switch_context(request);
1902 /* Unconditionally invalidate GPU caches and TLBs. */
1903 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
1907 request->reserved_space -= LEGACY_REQUEST_SIZE;
1911 static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes)
1913 struct i915_request *target;
1916 lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex);
1918 if (intel_ring_update_space(ring) >= bytes)
1921 GEM_BUG_ON(list_empty(&ring->request_list));
1922 list_for_each_entry(target, &ring->request_list, ring_link) {
1923 /* Would completion of this request free enough space? */
1924 if (bytes <= __intel_ring_space(target->postfix,
1925 ring->emit, ring->size))
1929 if (WARN_ON(&target->ring_link == &ring->request_list))
1932 timeout = i915_request_wait(target,
1933 I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
1934 MAX_SCHEDULE_TIMEOUT);
1938 i915_request_retire_upto(target);
1940 intel_ring_update_space(ring);
1941 GEM_BUG_ON(ring->space < bytes);
1945 u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)
1947 struct intel_ring *ring = rq->ring;
1948 const unsigned int remain_usable = ring->effective_size - ring->emit;
1949 const unsigned int bytes = num_dwords * sizeof(u32);
1950 unsigned int need_wrap = 0;
1951 unsigned int total_bytes;
1954 /* Packets must be qword aligned. */
1955 GEM_BUG_ON(num_dwords & 1);
1957 total_bytes = bytes + rq->reserved_space;
1958 GEM_BUG_ON(total_bytes > ring->effective_size);
1960 if (unlikely(total_bytes > remain_usable)) {
1961 const int remain_actual = ring->size - ring->emit;
1963 if (bytes > remain_usable) {
1965 * Not enough space for the basic request. So need to
1966 * flush out the remainder and then wait for
1969 total_bytes += remain_actual;
1970 need_wrap = remain_actual | 1;
1973 * The base request will fit but the reserved space
1974 * falls off the end. So we don't need an immediate
1975 * wrap and only need to effectively wait for the
1976 * reserved size from the start of ringbuffer.
1978 total_bytes = rq->reserved_space + remain_actual;
1982 if (unlikely(total_bytes > ring->space)) {
1986 * Space is reserved in the ringbuffer for finalising the
1987 * request, as that cannot be allowed to fail. During request
1988 * finalisation, reserved_space is set to 0 to stop the
1989 * overallocation and the assumption is that then we never need
1990 * to wait (which has the risk of failing with EINTR).
1992 * See also i915_request_alloc() and i915_request_add().
1994 GEM_BUG_ON(!rq->reserved_space);
1996 ret = wait_for_space(ring, total_bytes);
1998 return ERR_PTR(ret);
2001 if (unlikely(need_wrap)) {
2003 GEM_BUG_ON(need_wrap > ring->space);
2004 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
2005 GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));
2007 /* Fill the tail with MI_NOOP */
2008 memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));
2009 ring->space -= need_wrap;
2013 GEM_BUG_ON(ring->emit > ring->size - bytes);
2014 GEM_BUG_ON(ring->space < bytes);
2015 cs = ring->vaddr + ring->emit;
2016 GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
2017 ring->emit += bytes;
2018 ring->space -= bytes;
2023 /* Align the ring tail to a cacheline boundary */
2024 int intel_ring_cacheline_align(struct i915_request *rq)
2029 num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);
2030 if (num_dwords == 0)
2033 num_dwords = CACHELINE_DWORDS - num_dwords;
2034 GEM_BUG_ON(num_dwords & 1);
2036 cs = intel_ring_begin(rq, num_dwords);
2040 memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2);
2041 intel_ring_advance(rq, cs);
2043 GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1));
2047 static void gen6_bsd_submit_request(struct i915_request *request)
2049 struct intel_uncore *uncore = request->engine->uncore;
2051 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
2053 /* Every tail move must follow the sequence below */
2055 /* Disable notification that the ring is IDLE. The GT
2056 * will then assume that it is busy and bring it out of rc6.
2058 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
2059 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2061 /* Clear the context id. Here be magic! */
2062 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
2064 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2065 if (__intel_wait_for_register_fw(uncore,
2066 GEN6_BSD_SLEEP_PSMI_CONTROL,
2067 GEN6_BSD_SLEEP_INDICATOR,
2070 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2072 /* Now that the ring is fully powered up, update the tail */
2073 i9xx_submit_request(request);
2075 /* Let the ring send IDLE messages to the GT again,
2076 * and so let it sleep to conserve power when idle.
2078 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
2079 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2081 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
2084 static int mi_flush_dw(struct i915_request *rq, u32 flags)
2088 cs = intel_ring_begin(rq, 4);
2095 * We always require a command barrier so that subsequent
2096 * commands, such as breadcrumb interrupts, are strictly ordered
2097 * wrt the contents of the write cache being flushed to memory
2098 * (and thus being coherent from the CPU).
2100 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2103 * Bspec vol 1c.3 - blitter engine command streamer:
2104 * "If ENABLED, all TLBs will be invalidated once the flush
2105 * operation is complete. This bit is only valid when the
2106 * Post-Sync Operation field is a value of 1h or 3h."
2111 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2115 intel_ring_advance(rq, cs);
2120 static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)
2122 return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0);
2125 static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
2127 return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD);
2131 hsw_emit_bb_start(struct i915_request *rq,
2132 u64 offset, u32 len,
2133 unsigned int dispatch_flags)
2137 cs = intel_ring_begin(rq, 2);
2141 *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
2142 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW);
2143 /* bit0-7 is the length on GEN6+ */
2145 intel_ring_advance(rq, cs);
2151 gen6_emit_bb_start(struct i915_request *rq,
2152 u64 offset, u32 len,
2153 unsigned int dispatch_flags)
2157 cs = intel_ring_begin(rq, 2);
2161 *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
2162 0 : MI_BATCH_NON_SECURE_I965);
2163 /* bit0-7 is the length on GEN6+ */
2165 intel_ring_advance(rq, cs);
2170 /* Blitter support (SandyBridge+) */
2172 static int gen6_ring_flush(struct i915_request *rq, u32 mode)
2174 return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB);
2177 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2178 struct intel_engine_cs *engine)
2180 if (INTEL_GEN(dev_priv) >= 6) {
2181 engine->irq_enable = gen6_irq_enable;
2182 engine->irq_disable = gen6_irq_disable;
2183 } else if (INTEL_GEN(dev_priv) >= 5) {
2184 engine->irq_enable = gen5_irq_enable;
2185 engine->irq_disable = gen5_irq_disable;
2186 } else if (INTEL_GEN(dev_priv) >= 3) {
2187 engine->irq_enable = i9xx_irq_enable;
2188 engine->irq_disable = i9xx_irq_disable;
2190 engine->irq_enable = i8xx_irq_enable;
2191 engine->irq_disable = i8xx_irq_disable;
2195 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
2197 engine->submit_request = i9xx_submit_request;
2198 engine->cancel_requests = cancel_requests;
2200 engine->park = NULL;
2201 engine->unpark = NULL;
2204 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
2206 i9xx_set_default_submission(engine);
2207 engine->submit_request = gen6_bsd_submit_request;
2210 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2211 struct intel_engine_cs *engine)
2213 /* gen8+ are only supported with execlists */
2214 GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
2216 intel_ring_init_irq(dev_priv, engine);
2218 engine->init_hw = init_ring_common;
2219 engine->reset.prepare = reset_prepare;
2220 engine->reset.reset = reset_ring;
2221 engine->reset.finish = reset_finish;
2223 engine->cops = &ring_context_ops;
2224 engine->request_alloc = ring_request_alloc;
2227 * Using a global execution timeline; the previous final breadcrumb is
2228 * equivalent to our next initial bread so we can elide
2229 * engine->emit_init_breadcrumb().
2231 engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb;
2232 if (IS_GEN(dev_priv, 5))
2233 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
2235 engine->set_default_submission = i9xx_set_default_submission;
2237 if (INTEL_GEN(dev_priv) >= 6)
2238 engine->emit_bb_start = gen6_emit_bb_start;
2239 else if (INTEL_GEN(dev_priv) >= 4)
2240 engine->emit_bb_start = i965_emit_bb_start;
2241 else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
2242 engine->emit_bb_start = i830_emit_bb_start;
2244 engine->emit_bb_start = i915_emit_bb_start;
2247 int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2249 struct drm_i915_private *dev_priv = engine->i915;
2252 intel_ring_default_vfuncs(dev_priv, engine);
2254 if (HAS_L3_DPF(dev_priv))
2255 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2257 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2259 if (INTEL_GEN(dev_priv) >= 7) {
2260 engine->init_context = intel_rcs_ctx_init;
2261 engine->emit_flush = gen7_render_ring_flush;
2262 engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb;
2263 } else if (IS_GEN(dev_priv, 6)) {
2264 engine->init_context = intel_rcs_ctx_init;
2265 engine->emit_flush = gen6_render_ring_flush;
2266 engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb;
2267 } else if (IS_GEN(dev_priv, 5)) {
2268 engine->emit_flush = gen4_render_ring_flush;
2270 if (INTEL_GEN(dev_priv) < 4)
2271 engine->emit_flush = gen2_render_ring_flush;
2273 engine->emit_flush = gen4_render_ring_flush;
2274 engine->irq_enable_mask = I915_USER_INTERRUPT;
2277 if (IS_HASWELL(dev_priv))
2278 engine->emit_bb_start = hsw_emit_bb_start;
2280 engine->init_hw = init_render_ring;
2282 ret = intel_init_ring_buffer(engine);
2289 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2291 struct drm_i915_private *dev_priv = engine->i915;
2293 intel_ring_default_vfuncs(dev_priv, engine);
2295 if (INTEL_GEN(dev_priv) >= 6) {
2296 /* gen6 bsd needs a special wa for tail updates */
2297 if (IS_GEN(dev_priv, 6))
2298 engine->set_default_submission = gen6_bsd_set_default_submission;
2299 engine->emit_flush = gen6_bsd_ring_flush;
2300 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2302 if (IS_GEN(dev_priv, 6))
2303 engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb;
2305 engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb;
2307 engine->emit_flush = bsd_ring_flush;
2308 if (IS_GEN(dev_priv, 5))
2309 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2311 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2314 return intel_init_ring_buffer(engine);
2317 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2319 struct drm_i915_private *dev_priv = engine->i915;
2321 GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
2323 intel_ring_default_vfuncs(dev_priv, engine);
2325 engine->emit_flush = gen6_ring_flush;
2326 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2328 if (IS_GEN(dev_priv, 6))
2329 engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb;
2331 engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb;
2333 return intel_init_ring_buffer(engine);
2336 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2338 struct drm_i915_private *dev_priv = engine->i915;
2340 GEM_BUG_ON(INTEL_GEN(dev_priv) < 7);
2342 intel_ring_default_vfuncs(dev_priv, engine);
2344 engine->emit_flush = gen6_ring_flush;
2345 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2346 engine->irq_enable = hsw_vebox_irq_enable;
2347 engine->irq_disable = hsw_vebox_irq_disable;
2349 engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb;
2351 return intel_init_ring_buffer(engine);