drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  53                                          enum i915_power_well_id power_well_id);
  54
  55 const char *
  56 intel_display_power_domain_str(enum intel_display_power_domain domain)
  57 {
  58         switch (domain) {
  59         case POWER_DOMAIN_PIPE_A:
  60                 return "PIPE_A";
  61         case POWER_DOMAIN_PIPE_B:
  62                 return "PIPE_B";
  63         case POWER_DOMAIN_PIPE_C:
  64                 return "PIPE_C";
  65         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  66                 return "PIPE_A_PANEL_FITTER";
  67         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  68                 return "PIPE_B_PANEL_FITTER";
  69         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  70                 return "PIPE_C_PANEL_FITTER";
  71         case POWER_DOMAIN_TRANSCODER_A:
  72                 return "TRANSCODER_A";
  73         case POWER_DOMAIN_TRANSCODER_B:
  74                 return "TRANSCODER_B";
  75         case POWER_DOMAIN_TRANSCODER_C:
  76                 return "TRANSCODER_C";
  77         case POWER_DOMAIN_TRANSCODER_EDP:
  78                 return "TRANSCODER_EDP";
  79         case POWER_DOMAIN_TRANSCODER_DSI_A:
  80                 return "TRANSCODER_DSI_A";
  81         case POWER_DOMAIN_TRANSCODER_DSI_C:
  82                 return "TRANSCODER_DSI_C";
  83         case POWER_DOMAIN_PORT_DDI_A_LANES:
  84                 return "PORT_DDI_A_LANES";
  85         case POWER_DOMAIN_PORT_DDI_B_LANES:
  86                 return "PORT_DDI_B_LANES";
  87         case POWER_DOMAIN_PORT_DDI_C_LANES:
  88                 return "PORT_DDI_C_LANES";
  89         case POWER_DOMAIN_PORT_DDI_D_LANES:
  90                 return "PORT_DDI_D_LANES";
  91         case POWER_DOMAIN_PORT_DDI_E_LANES:
  92                 return "PORT_DDI_E_LANES";
  93         case POWER_DOMAIN_PORT_DDI_F_LANES:
  94                 return "PORT_DDI_F_LANES";
  95         case POWER_DOMAIN_PORT_DDI_A_IO:
  96                 return "PORT_DDI_A_IO";
  97         case POWER_DOMAIN_PORT_DDI_B_IO:
  98                 return "PORT_DDI_B_IO";
  99         case POWER_DOMAIN_PORT_DDI_C_IO:
 100                 return "PORT_DDI_C_IO";
 101         case POWER_DOMAIN_PORT_DDI_D_IO:
 102                 return "PORT_DDI_D_IO";
 103         case POWER_DOMAIN_PORT_DDI_E_IO:
 104                 return "PORT_DDI_E_IO";
 105         case POWER_DOMAIN_PORT_DDI_F_IO:
 106                 return "PORT_DDI_F_IO";
 107         case POWER_DOMAIN_PORT_DSI:
 108                 return "PORT_DSI";
 109         case POWER_DOMAIN_PORT_CRT:
 110                 return "PORT_CRT";
 111         case POWER_DOMAIN_PORT_OTHER:
 112                 return "PORT_OTHER";
 113         case POWER_DOMAIN_VGA:
 114                 return "VGA";
 115         case POWER_DOMAIN_AUDIO:
 116                 return "AUDIO";
 117         case POWER_DOMAIN_PLLS:
 118                 return "PLLS";
 119         case POWER_DOMAIN_AUX_A:
 120                 return "AUX_A";
 121         case POWER_DOMAIN_AUX_B:
 122                 return "AUX_B";
 123         case POWER_DOMAIN_AUX_C:
 124                 return "AUX_C";
 125         case POWER_DOMAIN_AUX_D:
 126                 return "AUX_D";
 127         case POWER_DOMAIN_AUX_E:
 128                 return "AUX_E";
 129         case POWER_DOMAIN_AUX_F:
 130                 return "AUX_F";
 131         case POWER_DOMAIN_AUX_IO_A:
 132                 return "AUX_IO_A";
 133         case POWER_DOMAIN_AUX_TBT1:
 134                 return "AUX_TBT1";
 135         case POWER_DOMAIN_AUX_TBT2:
 136                 return "AUX_TBT2";
 137         case POWER_DOMAIN_AUX_TBT3:
 138                 return "AUX_TBT3";
 139         case POWER_DOMAIN_AUX_TBT4:
 140                 return "AUX_TBT4";
 141         case POWER_DOMAIN_GMBUS:
 142                 return "GMBUS";
 143         case POWER_DOMAIN_INIT:
 144                 return "INIT";
 145         case POWER_DOMAIN_MODESET:
 146                 return "MODESET";
 147         case POWER_DOMAIN_GT_IRQ:
 148                 return "GT_IRQ";
 149         default:
 150                 MISSING_CASE(domain);
 151                 return "?";
 152         }
 153 }
 154
 155 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 156                                     struct i915_power_well *power_well)
 157 {
 158         DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name);
 159         power_well->desc->ops->enable(dev_priv, power_well);
 160         power_well->hw_enabled = true;
 161 }
 162
 163 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 164                                      struct i915_power_well *power_well)
 165 {
 166         DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name);
 167         power_well->hw_enabled = false;
 168         power_well->desc->ops->disable(dev_priv, power_well);
 169 }
 170
 171 static void intel_power_well_get(struct drm_i915_private *dev_priv,
 172                                  struct i915_power_well *power_well)
 173 {
 174         if (!power_well->count++)
 175                 intel_power_well_enable(dev_priv, power_well);
 176 }
 177
 178 static void intel_power_well_put(struct drm_i915_private *dev_priv,
 179                                  struct i915_power_well *power_well)
 180 {
 181         WARN(!power_well->count, "Use count on power well %s is already zero",
 182              power_well->desc->name);
 183
 184         if (!--power_well->count)
 185                 intel_power_well_disable(dev_priv, power_well);
 186 }
 187
 188 /**
 189  * __intel_display_power_is_enabled - unlocked check for a power domain
 190  * @dev_priv: i915 device instance
 191  * @domain: power domain to check
 192  *
 193  * This is the unlocked version of intel_display_power_is_enabled() and should
 194  * only be used from error capture and recovery code where deadlocks are
 195  * possible.
 196  *
 197  * Returns:
 198  * True when the power domain is enabled, false otherwise.
 199  */
 200 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 201                                       enum intel_display_power_domain domain)
 202 {
 203         struct i915_power_well *power_well;
 204         bool is_enabled;
 205
 206         if (dev_priv->runtime_pm.suspended)
 207                 return false;
 208
 209         is_enabled = true;
 210
 211         for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
 212                 if (power_well->desc->always_on)
 213                         continue;
 214
 215                 if (!power_well->hw_enabled) {
 216                         is_enabled = false;
 217                         break;
 218                 }
 219         }
 220
 221         return is_enabled;
 222 }
 223
 224 /**
 225  * intel_display_power_is_enabled - check for a power domain
 226  * @dev_priv: i915 device instance
 227  * @domain: power domain to check
 228  *
 229  * This function can be used to check the hw power domain state. It is mostly
 230  * used in hardware state readout functions. Everywhere else code should rely
 231  * upon explicit power domain reference counting to ensure that the hardware
 232  * block is powered up before accessing it.
 233  *
 234  * Callers must hold the relevant modesetting locks to ensure that concurrent
 235  * threads can't disable the power well while the caller tries to read a few
 236  * registers.
 237  *
 238  * Returns:
 239  * True when the power domain is enabled, false otherwise.
 240  */
 241 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 242                                     enum intel_display_power_domain domain)
 243 {
 244         struct i915_power_domains *power_domains;
 245         bool ret;
 246
 247         power_domains = &dev_priv->power_domains;
 248
 249         mutex_lock(&power_domains->lock);
 250         ret = __intel_display_power_is_enabled(dev_priv, domain);
 251         mutex_unlock(&power_domains->lock);
 252
 253         return ret;
 254 }
 255
 256 /*
 257  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 258  * when not needed anymore. We have 4 registers that can request the power well
 259  * to be enabled, and it will only be disabled if none of the registers is
 260  * requesting it to be enabled.
 261  */
 262 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
 263                                        u8 irq_pipe_mask, bool has_vga)
 264 {
 265         struct pci_dev *pdev = dev_priv->drm.pdev;
 266
 267         /*
 268          * After we re-enable the power well, if we touch VGA register 0x3d5
 269          * we'll get unclaimed register interrupts. This stops after we write
 270          * anything to the VGA MSR register. The vgacon module uses this
 271          * register all the time, so if we unbind our driver and, as a
 272          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 273          * console_unlock(). So make here we touch the VGA MSR register, making
 274          * sure vgacon can keep working normally without triggering interrupts
 275          * and error messages.
 276          */
 277         if (has_vga) {
 278                 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
 279                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 280                 vga_put(pdev, VGA_RSRC_LEGACY_IO);
 281         }
 282
 283         if (irq_pipe_mask)
 284                 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
 285 }
 286
 287 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
 288                                        u8 irq_pipe_mask)
 289 {
 290         if (irq_pipe_mask)
 291                 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
 292 }
 293
 294
 295 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
 296                                            struct i915_power_well *power_well)
 297 {
 298         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 299         int pw_idx = power_well->desc->hsw.idx;
 300
 301         /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
 302         WARN_ON(intel_wait_for_register(dev_priv,
 303                                         regs->driver,
 304                                         HSW_PWR_WELL_CTL_STATE(pw_idx),
 305                                         HSW_PWR_WELL_CTL_STATE(pw_idx),
 306                                         1));
 307 }
 308
 309 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
 310                                      const struct i915_power_well_regs *regs,
 311                                      int pw_idx)
 312 {
 313         u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
 314         u32 ret;
 315
 316         ret = I915_READ(regs->bios) & req_mask ? 1 : 0;
 317         ret |= I915_READ(regs->driver) & req_mask ? 2 : 0;
 318         if (regs->kvmr.reg)
 319                 ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0;
 320         ret |= I915_READ(regs->debug) & req_mask ? 8 : 0;
 321
 322         return ret;
 323 }
 324
 325 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
 326                                             struct i915_power_well *power_well)
 327 {
 328         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 329         int pw_idx = power_well->desc->hsw.idx;
 330         bool disabled;
 331         u32 reqs;
 332
 333         /*
 334          * Bspec doesn't require waiting for PWs to get disabled, but still do
 335          * this for paranoia. The known cases where a PW will be forced on:
 336          * - a KVMR request on any power well via the KVMR request register
 337          * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
 338          *   DEBUG request registers
 339          * Skip the wait in case any of the request bits are set and print a
 340          * diagnostic message.
 341          */
 342         wait_for((disabled = !(I915_READ(regs->driver) &
 343                                HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
 344                  (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
 345         if (disabled)
 346                 return;
 347
 348         DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
 349                       power_well->desc->name,
 350                       !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
 351 }
 352
 353 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
 354                                            enum skl_power_gate pg)
 355 {
 356         /* Timeout 5us for PG#0, for other PGs 1us */
 357         WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
 358                                         SKL_FUSE_PG_DIST_STATUS(pg),
 359                                         SKL_FUSE_PG_DIST_STATUS(pg), 1));
 360 }
 361
 362 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 363                                   struct i915_power_well *power_well)
 364 {
 365         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 366         int pw_idx = power_well->desc->hsw.idx;
 367         bool wait_fuses = power_well->desc->hsw.has_fuses;
 368         enum skl_power_gate uninitialized_var(pg);
 369         u32 val;
 370
 371         if (wait_fuses) {
 372                 pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
 373                                                  SKL_PW_CTL_IDX_TO_PG(pw_idx);
 374                 /*
 375                  * For PW1 we have to wait both for the PW0/PG0 fuse state
 376                  * before enabling the power well and PW1/PG1's own fuse
 377                  * state after the enabling. For all other power wells with
 378                  * fuses we only have to wait for that PW/PG's fuse state
 379                  * after the enabling.
 380                  */
 381                 if (pg == SKL_PG1)
 382                         gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
 383         }
 384
 385         val = I915_READ(regs->driver);
 386         I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
 387         hsw_wait_for_power_well_enable(dev_priv, power_well);
 388
 389         /* Display WA #1178: cnl */
 390         if (IS_CANNONLAKE(dev_priv) &&
 391             pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
 392             pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
 393                 val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx));
 394                 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
 395                 I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val);
 396         }
 397
 398         if (wait_fuses)
 399                 gen9_wait_for_power_well_fuses(dev_priv, pg);
 400
 401         hsw_power_well_post_enable(dev_priv,
 402                                    power_well->desc->hsw.irq_pipe_mask,
 403                                    power_well->desc->hsw.has_vga);
 404 }
 405
 406 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 407                                    struct i915_power_well *power_well)
 408 {
 409         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 410         int pw_idx = power_well->desc->hsw.idx;
 411         u32 val;
 412
 413         hsw_power_well_pre_disable(dev_priv,
 414                                    power_well->desc->hsw.irq_pipe_mask);
 415
 416         val = I915_READ(regs->driver);
 417         I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
 418         hsw_wait_for_power_well_disable(dev_priv, power_well);
 419 }
 420
 421 #define ICL_AUX_PW_TO_PORT(pw_idx)      ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
 422
 423 static void
 424 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 425                                     struct i915_power_well *power_well)
 426 {
 427         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 428         int pw_idx = power_well->desc->hsw.idx;
 429         enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
 430         u32 val;
 431
 432         val = I915_READ(regs->driver);
 433         I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
 434
 435         val = I915_READ(ICL_PORT_CL_DW12(port));
 436         I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
 437
 438         hsw_wait_for_power_well_enable(dev_priv, power_well);
 439
 440         /* Display WA #1178: icl */
 441         if (IS_ICELAKE(dev_priv) &&
 442             pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
 443             !intel_bios_is_port_edp(dev_priv, port)) {
 444                 val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
 445                 val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
 446                 I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
 447         }
 448 }
 449
 450 static void
 451 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
 452                                      struct i915_power_well *power_well)
 453 {
 454         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 455         int pw_idx = power_well->desc->hsw.idx;
 456         enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
 457         u32 val;
 458
 459         val = I915_READ(ICL_PORT_CL_DW12(port));
 460         I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
 461
 462         val = I915_READ(regs->driver);
 463         I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
 464
 465         hsw_wait_for_power_well_disable(dev_priv, power_well);
 466 }
 467
 468 #define ICL_AUX_PW_TO_CH(pw_idx)        \
 469         ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
 470
 471 static void
 472 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 473                                  struct i915_power_well *power_well)
 474 {
 475         enum aux_ch aux_ch = ICL_AUX_PW_TO_CH(power_well->desc->hsw.idx);
 476         u32 val;
 477
 478         val = I915_READ(DP_AUX_CH_CTL(aux_ch));
 479         val &= ~DP_AUX_CH_CTL_TBT_IO;
 480         if (power_well->desc->hsw.is_tc_tbt)
 481                 val |= DP_AUX_CH_CTL_TBT_IO;
 482         I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
 483
 484         hsw_power_well_enable(dev_priv, power_well);
 485 }
 486
 487 /*
 488  * We should only use the power well if we explicitly asked the hardware to
 489  * enable it, so check if it's enabled and also check if we've requested it to
 490  * be enabled.
 491  */
 492 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 493                                    struct i915_power_well *power_well)
 494 {
 495         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 496         enum i915_power_well_id id = power_well->desc->id;
 497         int pw_idx = power_well->desc->hsw.idx;
 498         u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
 499                    HSW_PWR_WELL_CTL_STATE(pw_idx);
 500         u32 val;
 501
 502         val = I915_READ(regs->driver);
 503
 504         /*
 505          * On GEN9 big core due to a DMC bug the driver's request bits for PW1
 506          * and the MISC_IO PW will be not restored, so check instead for the
 507          * BIOS's own request bits, which are forced-on for these power wells
 508          * when exiting DC5/6.
 509          */
 510         if (IS_GEN9(dev_priv) && !IS_GEN9_LP(dev_priv) &&
 511             (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
 512                 val |= I915_READ(regs->bios);
 513
 514         return (val & mask) == mask;
 515 }
 516
 517 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 518 {
 519         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 520                   "DC9 already programmed to be enabled.\n");
 521         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 522                   "DC5 still not disabled to enable DC9.\n");
 523         WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) &
 524                   HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
 525                   "Power well 2 on.\n");
 526         WARN_ONCE(intel_irqs_enabled(dev_priv),
 527                   "Interrupts not disabled yet.\n");
 528
 529          /*
 530           * TODO: check for the following to verify the conditions to enter DC9
 531           * state are satisfied:
 532           * 1] Check relevant display engine registers to verify if mode set
 533           * disable sequence was followed.
 534           * 2] Check if display uninitialize sequence is initialized.
 535           */
 536 }
 537
 538 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 539 {
 540         WARN_ONCE(intel_irqs_enabled(dev_priv),
 541                   "Interrupts not disabled yet.\n");
 542         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 543                   "DC5 still not disabled.\n");
 544
 545          /*
 546           * TODO: check for the following to verify DC9 state was indeed
 547           * entered before programming to disable it:
 548           * 1] Check relevant display engine registers to verify if mode
 549           *  set disable sequence was followed.
 550           * 2] Check if display uninitialize sequence is initialized.
 551           */
 552 }
 553
 554 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 555                                 u32 state)
 556 {
 557         int rewrites = 0;
 558         int rereads = 0;
 559         u32 v;
 560
 561         I915_WRITE(DC_STATE_EN, state);
 562
 563         /* It has been observed that disabling the dc6 state sometimes
 564          * doesn't stick and dmc keeps returning old value. Make sure
 565          * the write really sticks enough times and also force rewrite until
 566          * we are confident that state is exactly what we want.
 567          */
 568         do  {
 569                 v = I915_READ(DC_STATE_EN);
 570
 571                 if (v != state) {
 572                         I915_WRITE(DC_STATE_EN, state);
 573                         rewrites++;
 574                         rereads = 0;
 575                 } else if (rereads++ > 5) {
 576                         break;
 577                 }
 578
 579         } while (rewrites < 100);
 580
 581         if (v != state)
 582                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 583                           state, v);
 584
 585         /* Most of the times we need one retry, avoid spam */
 586         if (rewrites > 1)
 587                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 588                               state, rewrites);
 589 }
 590
 591 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 592 {
 593         u32 mask;
 594
 595         mask = DC_STATE_EN_UPTO_DC5;
 596         if (INTEL_GEN(dev_priv) >= 11)
 597                 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
 598         else if (IS_GEN9_LP(dev_priv))
 599                 mask |= DC_STATE_EN_DC9;
 600         else
 601                 mask |= DC_STATE_EN_UPTO_DC6;
 602
 603         return mask;
 604 }
 605
 606 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 607 {
 608         u32 val;
 609
 610         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 611
 612         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 613                       dev_priv->csr.dc_state, val);
 614         dev_priv->csr.dc_state = val;
 615 }
 616
 617 /**
 618  * gen9_set_dc_state - set target display C power state
 619  * @dev_priv: i915 device instance
 620  * @state: target DC power state
 621  * - DC_STATE_DISABLE
 622  * - DC_STATE_EN_UPTO_DC5
 623  * - DC_STATE_EN_UPTO_DC6
 624  * - DC_STATE_EN_DC9
 625  *
 626  * Signal to DMC firmware/HW the target DC power state passed in @state.
 627  * DMC/HW can turn off individual display clocks and power rails when entering
 628  * a deeper DC power state (higher in number) and turns these back when exiting
 629  * that state to a shallower power state (lower in number). The HW will decide
 630  * when to actually enter a given state on an on-demand basis, for instance
 631  * depending on the active state of display pipes. The state of display
 632  * registers backed by affected power rails are saved/restored as needed.
 633  *
 634  * Based on the above enabling a deeper DC power state is asynchronous wrt.
 635  * enabling it. Disabling a deeper power state is synchronous: for instance
 636  * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
 637  * back on and register state is restored. This is guaranteed by the MMIO write
 638  * to DC_STATE_EN blocking until the state is restored.
 639  */
 640 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 641 {
 642         uint32_t val;
 643         uint32_t mask;
 644
 645         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 646                 state &= dev_priv->csr.allowed_dc_mask;
 647
 648         val = I915_READ(DC_STATE_EN);
 649         mask = gen9_dc_mask(dev_priv);
 650         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 651                       val & mask, state);
 652
 653         /* Check if DMC is ignoring our DC state requests */
 654         if ((val & mask) != dev_priv->csr.dc_state)
 655                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 656                           dev_priv->csr.dc_state, val & mask);
 657
 658         val &= ~mask;
 659         val |= state;
 660
 661         gen9_write_dc_state(dev_priv, val);
 662
 663         dev_priv->csr.dc_state = val & mask;
 664 }
 665
 666 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 667 {
 668         assert_can_enable_dc9(dev_priv);
 669
 670         DRM_DEBUG_KMS("Enabling DC9\n");
 671         /*
 672          * Power sequencer reset is not needed on
 673          * platforms with South Display Engine on PCH,
 674          * because PPS registers are always on.
 675          */
 676         if (!HAS_PCH_SPLIT(dev_priv))
 677                 intel_power_sequencer_reset(dev_priv);
 678         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 679 }
 680
 681 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 682 {
 683         assert_can_disable_dc9(dev_priv);
 684
 685         DRM_DEBUG_KMS("Disabling DC9\n");
 686
 687         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 688
 689         intel_pps_unlock_regs_wa(dev_priv);
 690 }
 691
 692 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 693 {
 694         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 695                   "CSR program storage start is NULL\n");
 696         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 697         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 698 }
 699
 700 static struct i915_power_well *
 701 lookup_power_well(struct drm_i915_private *dev_priv,
 702                   enum i915_power_well_id power_well_id)
 703 {
 704         struct i915_power_well *power_well;
 705
 706         for_each_power_well(dev_priv, power_well)
 707                 if (power_well->desc->id == power_well_id)
 708                         return power_well;
 709
 710         /*
 711          * It's not feasible to add error checking code to the callers since
 712          * this condition really shouldn't happen and it doesn't even make sense
 713          * to abort things like display initialization sequences. Just return
 714          * the first power well and hope the WARN gets reported so we can fix
 715          * our driver.
 716          */
 717         WARN(1, "Power well %d not defined for this platform\n", power_well_id);
 718         return &dev_priv->power_domains.power_wells[0];
 719 }
 720
 721 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 722 {
 723         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 724                                         SKL_DISP_PW_2);
 725
 726         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 727
 728         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 729                   "DC5 already programmed to be enabled.\n");
 730         assert_rpm_wakelock_held(dev_priv);
 731
 732         assert_csr_loaded(dev_priv);
 733 }
 734
 735 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 736 {
 737         assert_can_enable_dc5(dev_priv);
 738
 739         DRM_DEBUG_KMS("Enabling DC5\n");
 740
 741         /* Wa Display #1183: skl,kbl,cfl */
 742         if (IS_GEN9_BC(dev_priv))
 743                 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
 744                            SKL_SELECT_ALTERNATE_DC_EXIT);
 745
 746         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 747 }
 748
 749 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 750 {
 751         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 752                   "Backlight is not disabled.\n");
 753         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 754                   "DC6 already programmed to be enabled.\n");
 755
 756         assert_csr_loaded(dev_priv);
 757 }
 758
 759 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 760 {
 761         assert_can_enable_dc6(dev_priv);
 762
 763         DRM_DEBUG_KMS("Enabling DC6\n");
 764
 765         /* Wa Display #1183: skl,kbl,cfl */
 766         if (IS_GEN9_BC(dev_priv))
 767                 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
 768                            SKL_SELECT_ALTERNATE_DC_EXIT);
 769
 770         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 771 }
 772
 773 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 774                                    struct i915_power_well *power_well)
 775 {
 776         const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
 777         int pw_idx = power_well->desc->hsw.idx;
 778         u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
 779         u32 bios_req = I915_READ(regs->bios);
 780
 781         /* Take over the request bit if set by BIOS. */
 782         if (bios_req & mask) {
 783                 u32 drv_req = I915_READ(regs->driver);
 784
 785                 if (!(drv_req & mask))
 786                         I915_WRITE(regs->driver, drv_req | mask);
 787                 I915_WRITE(regs->bios, bios_req & ~mask);
 788         }
 789 }
 790
 791 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 792                                            struct i915_power_well *power_well)
 793 {
 794         bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
 795 }
 796
 797 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 798                                             struct i915_power_well *power_well)
 799 {
 800         bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
 801 }
 802
 803 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 804                                             struct i915_power_well *power_well)
 805 {
 806         return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
 807 }
 808
 809 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 810 {
 811         struct i915_power_well *power_well;
 812
 813         power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
 814         if (power_well->count > 0)
 815                 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
 816
 817         power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
 818         if (power_well->count > 0)
 819                 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
 820
 821         if (IS_GEMINILAKE(dev_priv)) {
 822                 power_well = lookup_power_well(dev_priv,
 823                                                GLK_DISP_PW_DPIO_CMN_C);
 824                 if (power_well->count > 0)
 825                         bxt_ddi_phy_verify_state(dev_priv,
 826                                                  power_well->desc->bxt.phy);
 827         }
 828 }
 829
 830 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 831                                            struct i915_power_well *power_well)
 832 {
 833         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 834 }
 835
 836 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 837 {
 838         u32 tmp = I915_READ(DBUF_CTL);
 839
 840         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
 841              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
 842              "Unexpected DBuf power power state (0x%08x)\n", tmp);
 843 }
 844
 845 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 846                                           struct i915_power_well *power_well)
 847 {
 848         struct intel_cdclk_state cdclk_state = {};
 849
 850         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 851
 852         dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
 853         /* Can't read out voltage_level so can't use intel_cdclk_changed() */
 854         WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
 855
 856         gen9_assert_dbuf_enabled(dev_priv);
 857
 858         if (IS_GEN9_LP(dev_priv))
 859                 bxt_verify_ddi_phy_power_wells(dev_priv);
 860
 861         if (INTEL_GEN(dev_priv) >= 11)
 862                 /*
 863                  * DMC retains HW context only for port A, the other combo
 864                  * PHY's HW context for port B is lost after DC transitions,
 865                  * so we need to restore it manually.
 866                  */
 867                 icl_combo_phys_init(dev_priv);
 868 }
 869
 870 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 871                                            struct i915_power_well *power_well)
 872 {
 873         if (!dev_priv->csr.dmc_payload)
 874                 return;
 875
 876         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 877                 skl_enable_dc6(dev_priv);
 878         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 879                 gen9_enable_dc5(dev_priv);
 880 }
 881
 882 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
 883                                          struct i915_power_well *power_well)
 884 {
 885 }
 886
 887 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 888                                            struct i915_power_well *power_well)
 889 {
 890 }
 891
 892 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 893                                              struct i915_power_well *power_well)
 894 {
 895         return true;
 896 }
 897
 898 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
 899                                          struct i915_power_well *power_well)
 900 {
 901         if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
 902                 i830_enable_pipe(dev_priv, PIPE_A);
 903         if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
 904                 i830_enable_pipe(dev_priv, PIPE_B);
 905 }
 906
 907 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
 908                                           struct i915_power_well *power_well)
 909 {
 910         i830_disable_pipe(dev_priv, PIPE_B);
 911         i830_disable_pipe(dev_priv, PIPE_A);
 912 }
 913
 914 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
 915                                           struct i915_power_well *power_well)
 916 {
 917         return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
 918                 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
 919 }
 920
 921 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
 922                                           struct i915_power_well *power_well)
 923 {
 924         if (power_well->count > 0)
 925                 i830_pipes_power_well_enable(dev_priv, power_well);
 926         else
 927                 i830_pipes_power_well_disable(dev_priv, power_well);
 928 }
 929
 930 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 931                                struct i915_power_well *power_well, bool enable)
 932 {
 933         int pw_idx = power_well->desc->vlv.idx;
 934         u32 mask;
 935         u32 state;
 936         u32 ctrl;
 937
 938         mask = PUNIT_PWRGT_MASK(pw_idx);
 939         state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
 940                          PUNIT_PWRGT_PWR_GATE(pw_idx);
 941
 942         mutex_lock(&dev_priv->pcu_lock);
 943
 944 #define COND \
 945         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 946
 947         if (COND)
 948                 goto out;
 949
 950         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 951         ctrl &= ~mask;
 952         ctrl |= state;
 953         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 954
 955         if (wait_for(COND, 100))
 956                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 957                           state,
 958                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 959
 960 #undef COND
 961
 962 out:
 963         mutex_unlock(&dev_priv->pcu_lock);
 964 }
 965
 966 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 967                                   struct i915_power_well *power_well)
 968 {
 969         vlv_set_power_well(dev_priv, power_well, true);
 970 }
 971
 972 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 973                                    struct i915_power_well *power_well)
 974 {
 975         vlv_set_power_well(dev_priv, power_well, false);
 976 }
 977
 978 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 979                                    struct i915_power_well *power_well)
 980 {
 981         int pw_idx = power_well->desc->vlv.idx;
 982         bool enabled = false;
 983         u32 mask;
 984         u32 state;
 985         u32 ctrl;
 986
 987         mask = PUNIT_PWRGT_MASK(pw_idx);
 988         ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
 989
 990         mutex_lock(&dev_priv->pcu_lock);
 991
 992         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 993         /*
 994          * We only ever set the power-on and power-gate states, anything
 995          * else is unexpected.
 996          */
 997         WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
 998                 state != PUNIT_PWRGT_PWR_GATE(pw_idx));
 999         if (state == ctrl)
1000                 enabled = true;
1001
1002         /*
1003          * A transient state at this point would mean some unexpected party
1004          * is poking at the power controls too.
1005          */
1006         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1007         WARN_ON(ctrl != state);
1008
1009         mutex_unlock(&dev_priv->pcu_lock);
1010
1011         return enabled;
1012 }
1013
1014 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1015 {
1016         u32 val;
1017
1018         /*
1019          * On driver load, a pipe may be active and driving a DSI display.
1020          * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
1021          * (and never recovering) in this case. intel_dsi_post_disable() will
1022          * clear it when we turn off the display.
1023          */
1024         val = I915_READ(DSPCLK_GATE_D);
1025         val &= DPOUNIT_CLOCK_GATE_DISABLE;
1026         val |= VRHUNIT_CLOCK_GATE_DISABLE;
1027         I915_WRITE(DSPCLK_GATE_D, val);
1028
1029         /*
1030          * Disable trickle feed and enable pnd deadline calculation
1031          */
1032         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1033         I915_WRITE(CBR1_VLV, 0);
1034
1035         WARN_ON(dev_priv->rawclk_freq == 0);
1036
1037         I915_WRITE(RAWCLK_FREQ_VLV,
1038                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
1039 }
1040
1041 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1042 {
1043         struct intel_encoder *encoder;
1044         enum pipe pipe;
1045
1046         /*
1047          * Enable the CRI clock source so we can get at the
1048          * display and the reference clock for VGA
1049          * hotplug / manual detection. Supposedly DSI also
1050          * needs the ref clock up and running.
1051          *
1052          * CHV DPLL B/C have some issues if VGA mode is enabled.
1053          */
1054         for_each_pipe(dev_priv, pipe) {
1055                 u32 val = I915_READ(DPLL(pipe));
1056
1057                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1058                 if (pipe != PIPE_A)
1059                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1060
1061                 I915_WRITE(DPLL(pipe), val);
1062         }
1063
1064         vlv_init_display_clock_gating(dev_priv);
1065
1066         spin_lock_irq(&dev_priv->irq_lock);
1067         valleyview_enable_display_irqs(dev_priv);
1068         spin_unlock_irq(&dev_priv->irq_lock);
1069
1070         /*
1071          * During driver initialization/resume we can avoid restoring the
1072          * part of the HW/SW state that will be inited anyway explicitly.
1073          */
1074         if (dev_priv->power_domains.initializing)
1075                 return;
1076
1077         intel_hpd_init(dev_priv);
1078
1079         /* Re-enable the ADPA, if we have one */
1080         for_each_intel_encoder(&dev_priv->drm, encoder) {
1081                 if (encoder->type == INTEL_OUTPUT_ANALOG)
1082                         intel_crt_reset(&encoder->base);
1083         }
1084
1085         i915_redisable_vga_power_on(dev_priv);
1086
1087         intel_pps_unlock_regs_wa(dev_priv);
1088 }
1089
1090 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1091 {
1092         spin_lock_irq(&dev_priv->irq_lock);
1093         valleyview_disable_display_irqs(dev_priv);
1094         spin_unlock_irq(&dev_priv->irq_lock);
1095
1096         /* make sure we're done processing display irqs */
1097         synchronize_irq(dev_priv->drm.irq);
1098
1099         intel_power_sequencer_reset(dev_priv);
1100
1101         /* Prevent us from re-enabling polling on accident in late suspend */
1102         if (!dev_priv->drm.dev->power.is_suspended)
1103                 intel_hpd_poll_init(dev_priv);
1104 }
1105
1106 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1107                                           struct i915_power_well *power_well)
1108 {
1109         vlv_set_power_well(dev_priv, power_well, true);
1110
1111         vlv_display_power_well_init(dev_priv);
1112 }
1113
1114 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1115                                            struct i915_power_well *power_well)
1116 {
1117         vlv_display_power_well_deinit(dev_priv);
1118
1119         vlv_set_power_well(dev_priv, power_well, false);
1120 }
1121
1122 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1123                                            struct i915_power_well *power_well)
1124 {
1125         /* since ref/cri clock was enabled */
1126         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1127
1128         vlv_set_power_well(dev_priv, power_well, true);
1129
1130         /*
1131          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1132          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1133          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1134          *   b. The other bits such as sfr settings / modesel may all
1135          *      be set to 0.
1136          *
1137          * This should only be done on init and resume from S3 with
1138          * both PLLs disabled, or we risk losing DPIO and PLL
1139          * synchronization.
1140          */
1141         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1142 }
1143
1144 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1145                                             struct i915_power_well *power_well)
1146 {
1147         enum pipe pipe;
1148
1149         for_each_pipe(dev_priv, pipe)
1150                 assert_pll_disabled(dev_priv, pipe);
1151
1152         /* Assert common reset */
1153         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1154
1155         vlv_set_power_well(dev_priv, power_well, false);
1156 }
1157
1158 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
1159
1160 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1161
1162 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1163 {
1164         struct i915_power_well *cmn_bc =
1165                 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1166         struct i915_power_well *cmn_d =
1167                 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1168         u32 phy_control = dev_priv->chv_phy_control;
1169         u32 phy_status = 0;
1170         u32 phy_status_mask = 0xffffffff;
1171
1172         /*
1173          * The BIOS can leave the PHY is some weird state
1174          * where it doesn't fully power down some parts.
1175          * Disable the asserts until the PHY has been fully
1176          * reset (ie. the power well has been disabled at
1177          * least once).
1178          */
1179         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1180                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1181                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1182                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1183                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1184                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1185                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1186
1187         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1188                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1189                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1190                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1191
1192         if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
1193                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1194
1195                 /* this assumes override is only used to enable lanes */
1196                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1197                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1198
1199                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1200                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1201
1202                 /* CL1 is on whenever anything is on in either channel */
1203                 if (BITS_SET(phy_control,
1204                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1205                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1206                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1207
1208                 /*
1209                  * The DPLLB check accounts for the pipe B + port A usage
1210                  * with CL2 powered up but all the lanes in the second channel
1211                  * powered down.
1212                  */
1213                 if (BITS_SET(phy_control,
1214                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1215                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1216                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1217
1218                 if (BITS_SET(phy_control,
1219                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1220                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1221                 if (BITS_SET(phy_control,
1222                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1223                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1224
1225                 if (BITS_SET(phy_control,
1226                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1227                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1228                 if (BITS_SET(phy_control,
1229                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1230                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1231         }
1232
1233         if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
1234                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1235
1236                 /* this assumes override is only used to enable lanes */
1237                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1238                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1239
1240                 if (BITS_SET(phy_control,
1241                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1242                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1243
1244                 if (BITS_SET(phy_control,
1245                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1246                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1247                 if (BITS_SET(phy_control,
1248                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1249                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1250         }
1251
1252         phy_status &= phy_status_mask;
1253
1254         /*
1255          * The PHY may be busy with some initial calibration and whatnot,
1256          * so the power state can take a while to actually change.
1257          */
1258         if (intel_wait_for_register(dev_priv,
1259                                     DISPLAY_PHY_STATUS,
1260                                     phy_status_mask,
1261                                     phy_status,
1262                                     10))
1263                 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1264                           I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
1265                            phy_status, dev_priv->chv_phy_control);
1266 }
1267
1268 #undef BITS_SET
1269
1270 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1271                                            struct i915_power_well *power_well)
1272 {
1273         enum dpio_phy phy;
1274         enum pipe pipe;
1275         uint32_t tmp;
1276
1277         WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1278                      power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
1279
1280         if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
1281                 pipe = PIPE_A;
1282                 phy = DPIO_PHY0;
1283         } else {
1284                 pipe = PIPE_C;
1285                 phy = DPIO_PHY1;
1286         }
1287
1288         /* since ref/cri clock was enabled */
1289         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1290         vlv_set_power_well(dev_priv, power_well, true);
1291
1292         /* Poll for phypwrgood signal */
1293         if (intel_wait_for_register(dev_priv,
1294                                     DISPLAY_PHY_STATUS,
1295                                     PHY_POWERGOOD(phy),
1296                                     PHY_POWERGOOD(phy),
1297                                     1))
1298                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1299
1300         mutex_lock(&dev_priv->sb_lock);
1301
1302         /* Enable dynamic power down */
1303         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1304         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1305                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1306         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1307
1308         if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
1309                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1310                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1311                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1312         } else {
1313                 /*
1314                  * Force the non-existing CL2 off. BXT does this
1315                  * too, so maybe it saves some power even though
1316                  * CL2 doesn't exist?
1317                  */
1318                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1319                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1320                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1321         }
1322
1323         mutex_unlock(&dev_priv->sb_lock);
1324
1325         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1326         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1327
1328         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1329                       phy, dev_priv->chv_phy_control);
1330
1331         assert_chv_phy_status(dev_priv);
1332 }
1333
1334 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1335                                             struct i915_power_well *power_well)
1336 {
1337         enum dpio_phy phy;
1338
1339         WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1340                      power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
1341
1342         if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
1343                 phy = DPIO_PHY0;
1344                 assert_pll_disabled(dev_priv, PIPE_A);
1345                 assert_pll_disabled(dev_priv, PIPE_B);
1346         } else {
1347                 phy = DPIO_PHY1;
1348                 assert_pll_disabled(dev_priv, PIPE_C);
1349         }
1350
1351         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1352         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1353
1354         vlv_set_power_well(dev_priv, power_well, false);
1355
1356         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1357                       phy, dev_priv->chv_phy_control);
1358
1359         /* PHY is fully reset now, so we can enable the PHY state asserts */
1360         dev_priv->chv_phy_assert[phy] = true;
1361
1362         assert_chv_phy_status(dev_priv);
1363 }
1364
1365 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1366                                      enum dpio_channel ch, bool override, unsigned int mask)
1367 {
1368         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1369         u32 reg, val, expected, actual;
1370
1371         /*
1372          * The BIOS can leave the PHY is some weird state
1373          * where it doesn't fully power down some parts.
1374          * Disable the asserts until the PHY has been fully
1375          * reset (ie. the power well has been disabled at
1376          * least once).
1377          */
1378         if (!dev_priv->chv_phy_assert[phy])
1379                 return;
1380
1381         if (ch == DPIO_CH0)
1382                 reg = _CHV_CMN_DW0_CH0;
1383         else
1384                 reg = _CHV_CMN_DW6_CH1;
1385
1386         mutex_lock(&dev_priv->sb_lock);
1387         val = vlv_dpio_read(dev_priv, pipe, reg);
1388         mutex_unlock(&dev_priv->sb_lock);
1389
1390         /*
1391          * This assumes !override is only used when the port is disabled.
1392          * All lanes should power down even without the override when
1393          * the port is disabled.
1394          */
1395         if (!override || mask == 0xf) {
1396                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1397                 /*
1398                  * If CH1 common lane is not active anymore
1399                  * (eg. for pipe B DPLL) the entire channel will
1400                  * shut down, which causes the common lane registers
1401                  * to read as 0. That means we can't actually check
1402                  * the lane power down status bits, but as the entire
1403                  * register reads as 0 it's a good indication that the
1404                  * channel is indeed entirely powered down.
1405                  */
1406                 if (ch == DPIO_CH1 && val == 0)
1407                         expected = 0;
1408         } else if (mask != 0x0) {
1409                 expected = DPIO_ANYDL_POWERDOWN;
1410         } else {
1411                 expected = 0;
1412         }
1413
1414         if (ch == DPIO_CH0)
1415                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1416         else
1417                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1418         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1419
1420         WARN(actual != expected,
1421              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1422              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1423              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1424              reg, val);
1425 }
1426
1427 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1428                           enum dpio_channel ch, bool override)
1429 {
1430         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1431         bool was_override;
1432
1433         mutex_lock(&power_domains->lock);
1434
1435         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1436
1437         if (override == was_override)
1438                 goto out;
1439
1440         if (override)
1441                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1442         else
1443                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1444
1445         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1446
1447         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1448                       phy, ch, dev_priv->chv_phy_control);
1449
1450         assert_chv_phy_status(dev_priv);
1451
1452 out:
1453         mutex_unlock(&power_domains->lock);
1454
1455         return was_override;
1456 }
1457
1458 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1459                              bool override, unsigned int mask)
1460 {
1461         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1462         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1463         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1464         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1465
1466         mutex_lock(&power_domains->lock);
1467
1468         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1469         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1470
1471         if (override)
1472                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1473         else
1474                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1475
1476         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1477
1478         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1479                       phy, ch, mask, dev_priv->chv_phy_control);
1480
1481         assert_chv_phy_status(dev_priv);
1482
1483         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1484
1485         mutex_unlock(&power_domains->lock);
1486 }
1487
1488 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1489                                         struct i915_power_well *power_well)
1490 {
1491         enum pipe pipe = PIPE_A;
1492         bool enabled;
1493         u32 state, ctrl;
1494
1495         mutex_lock(&dev_priv->pcu_lock);
1496
1497         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1498         /*
1499          * We only ever set the power-on and power-gate states, anything
1500          * else is unexpected.
1501          */
1502         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1503         enabled = state == DP_SSS_PWR_ON(pipe);
1504
1505         /*
1506          * A transient state at this point would mean some unexpected party
1507          * is poking at the power controls too.
1508          */
1509         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1510         WARN_ON(ctrl << 16 != state);
1511
1512         mutex_unlock(&dev_priv->pcu_lock);
1513
1514         return enabled;
1515 }
1516
1517 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1518                                     struct i915_power_well *power_well,
1519                                     bool enable)
1520 {
1521         enum pipe pipe = PIPE_A;
1522         u32 state;
1523         u32 ctrl;
1524
1525         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1526
1527         mutex_lock(&dev_priv->pcu_lock);
1528
1529 #define COND \
1530         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1531
1532         if (COND)
1533                 goto out;
1534
1535         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1536         ctrl &= ~DP_SSC_MASK(pipe);
1537         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1538         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1539
1540         if (wait_for(COND, 100))
1541                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1542                           state,
1543                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1544
1545 #undef COND
1546
1547 out:
1548         mutex_unlock(&dev_priv->pcu_lock);
1549 }
1550
1551 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1552                                        struct i915_power_well *power_well)
1553 {
1554         chv_set_pipe_power_well(dev_priv, power_well, true);
1555
1556         vlv_display_power_well_init(dev_priv);
1557 }
1558
1559 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1560                                         struct i915_power_well *power_well)
1561 {
1562         vlv_display_power_well_deinit(dev_priv);
1563
1564         chv_set_pipe_power_well(dev_priv, power_well, false);
1565 }
1566
1567 static void
1568 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1569                                  enum intel_display_power_domain domain)
1570 {
1571         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1572         struct i915_power_well *power_well;
1573
1574         for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
1575                 intel_power_well_get(dev_priv, power_well);
1576
1577         power_domains->domain_use_count[domain]++;
1578 }
1579
1580 /**
1581  * intel_display_power_get - grab a power domain reference
1582  * @dev_priv: i915 device instance
1583  * @domain: power domain to reference
1584  *
1585  * This function grabs a power domain reference for @domain and ensures that the
1586  * power domain and all its parents are powered up. Therefore users should only
1587  * grab a reference to the innermost power domain they need.
1588  *
1589  * Any power domain reference obtained by this function must have a symmetric
1590  * call to intel_display_power_put() to release the reference again.
1591  */
1592 void intel_display_power_get(struct drm_i915_private *dev_priv,
1593                              enum intel_display_power_domain domain)
1594 {
1595         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1596
1597         intel_runtime_pm_get(dev_priv);
1598
1599         mutex_lock(&power_domains->lock);
1600
1601         __intel_display_power_get_domain(dev_priv, domain);
1602
1603         mutex_unlock(&power_domains->lock);
1604 }
1605
1606 /**
1607  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1608  * @dev_priv: i915 device instance
1609  * @domain: power domain to reference
1610  *
1611  * This function grabs a power domain reference for @domain and ensures that the
1612  * power domain and all its parents are powered up. Therefore users should only
1613  * grab a reference to the innermost power domain they need.
1614  *
1615  * Any power domain reference obtained by this function must have a symmetric
1616  * call to intel_display_power_put() to release the reference again.
1617  */
1618 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1619                                         enum intel_display_power_domain domain)
1620 {
1621         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1622         bool is_enabled;
1623
1624         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1625                 return false;
1626
1627         mutex_lock(&power_domains->lock);
1628
1629         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1630                 __intel_display_power_get_domain(dev_priv, domain);
1631                 is_enabled = true;
1632         } else {
1633                 is_enabled = false;
1634         }
1635
1636         mutex_unlock(&power_domains->lock);
1637
1638         if (!is_enabled)
1639                 intel_runtime_pm_put(dev_priv);
1640
1641         return is_enabled;
1642 }
1643
1644 /**
1645  * intel_display_power_put - release a power domain reference
1646  * @dev_priv: i915 device instance
1647  * @domain: power domain to reference
1648  *
1649  * This function drops the power domain reference obtained by
1650  * intel_display_power_get() and might power down the corresponding hardware
1651  * block right away if this is the last reference.
1652  */
1653 void intel_display_power_put(struct drm_i915_private *dev_priv,
1654                              enum intel_display_power_domain domain)
1655 {
1656         struct i915_power_domains *power_domains;
1657         struct i915_power_well *power_well;
1658
1659         power_domains = &dev_priv->power_domains;
1660
1661         mutex_lock(&power_domains->lock);
1662
1663         WARN(!power_domains->domain_use_count[domain],
1664              "Use count on domain %s is already zero\n",
1665              intel_display_power_domain_str(domain));
1666         power_domains->domain_use_count[domain]--;
1667
1668         for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
1669                 intel_power_well_put(dev_priv, power_well);
1670
1671         mutex_unlock(&power_domains->lock);
1672
1673         intel_runtime_pm_put(dev_priv);
1674 }
1675
1676 #define I830_PIPES_POWER_DOMAINS (              \
1677         BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
1678         BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
1679         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
1680         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1681         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
1682         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
1683         BIT_ULL(POWER_DOMAIN_INIT))
1684
1685 #define VLV_DISPLAY_POWER_DOMAINS (             \
1686         BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
1687         BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
1688         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
1689         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1690         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
1691         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
1692         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1693         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1694         BIT_ULL(POWER_DOMAIN_PORT_DSI) |                \
1695         BIT_ULL(POWER_DOMAIN_PORT_CRT) |                \
1696         BIT_ULL(POWER_DOMAIN_VGA) |                     \
1697         BIT_ULL(POWER_DOMAIN_AUDIO) |           \
1698         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1699         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1700         BIT_ULL(POWER_DOMAIN_GMBUS) |           \
1701         BIT_ULL(POWER_DOMAIN_INIT))
1702
1703 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1704         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1705         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1706         BIT_ULL(POWER_DOMAIN_PORT_CRT) |                \
1707         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1708         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1709         BIT_ULL(POWER_DOMAIN_INIT))
1710
1711 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1712         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1713         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1714         BIT_ULL(POWER_DOMAIN_INIT))
1715
1716 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1717         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1718         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1719         BIT_ULL(POWER_DOMAIN_INIT))
1720
1721 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1722         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1723         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1724         BIT_ULL(POWER_DOMAIN_INIT))
1725
1726 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1727         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1728         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1729         BIT_ULL(POWER_DOMAIN_INIT))
1730
1731 #define CHV_DISPLAY_POWER_DOMAINS (             \
1732         BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
1733         BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
1734         BIT_ULL(POWER_DOMAIN_PIPE_C) |          \
1735         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
1736         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1737         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |     \
1738         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
1739         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
1740         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |    \
1741         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1742         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1743         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
1744         BIT_ULL(POWER_DOMAIN_PORT_DSI) |                \
1745         BIT_ULL(POWER_DOMAIN_VGA) |                     \
1746         BIT_ULL(POWER_DOMAIN_AUDIO) |           \
1747         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1748         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1749         BIT_ULL(POWER_DOMAIN_AUX_D) |           \
1750         BIT_ULL(POWER_DOMAIN_GMBUS) |           \
1751         BIT_ULL(POWER_DOMAIN_INIT))
1752
1753 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1754         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1755         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1756         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1757         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1758         BIT_ULL(POWER_DOMAIN_INIT))
1759
1760 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1761         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
1762         BIT_ULL(POWER_DOMAIN_AUX_D) |           \
1763         BIT_ULL(POWER_DOMAIN_INIT))
1764
1765 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1766         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1767         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1768         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |             \
1769         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1770         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1771         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1772         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1773         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1774         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1775         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1776         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1777         BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
1778         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1779         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1780         BIT_ULL(POWER_DOMAIN_INIT))
1781
1782 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1783         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1784         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1785         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1786         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1787         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1788         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1789         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1790         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1791         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1792         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1793         BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
1794         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1795         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1796         BIT_ULL(POWER_DOMAIN_INIT))
1797
1798 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
1799         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1800         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1801         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1802         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1803         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1804         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1805         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1806         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1807         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1808         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1809         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |                \
1810         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
1811         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1812         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
1813         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1814         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1815         BIT_ULL(POWER_DOMAIN_INIT))
1816 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS (          \
1817         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
1818         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
1819         BIT_ULL(POWER_DOMAIN_INIT))
1820 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS (            \
1821         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
1822         BIT_ULL(POWER_DOMAIN_INIT))
1823 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS (            \
1824         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
1825         BIT_ULL(POWER_DOMAIN_INIT))
1826 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS (            \
1827         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
1828         BIT_ULL(POWER_DOMAIN_INIT))
1829 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
1830         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
1831         BIT_ULL(POWER_DOMAIN_GT_IRQ) |                  \
1832         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
1833         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1834         BIT_ULL(POWER_DOMAIN_INIT))
1835
1836 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
1837         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1838         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1839         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1840         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1841         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1842         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1843         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1844         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1845         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1846         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
1847         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1848         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1849         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1850         BIT_ULL(POWER_DOMAIN_INIT))
1851 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
1852         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
1853         BIT_ULL(POWER_DOMAIN_GT_IRQ) |                  \
1854         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
1855         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1856         BIT_ULL(POWER_DOMAIN_GMBUS) |                   \
1857         BIT_ULL(POWER_DOMAIN_INIT))
1858 #define BXT_DPIO_CMN_A_POWER_DOMAINS (                  \
1859         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
1860         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1861         BIT_ULL(POWER_DOMAIN_INIT))
1862 #define BXT_DPIO_CMN_BC_POWER_DOMAINS (                 \
1863         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1864         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1865         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
1866         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1867         BIT_ULL(POWER_DOMAIN_INIT))
1868
1869 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
1870         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1871         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1872         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1873         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1874         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1875         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1876         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1877         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1878         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1879         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
1880         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1881         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1882         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1883         BIT_ULL(POWER_DOMAIN_INIT))
1884 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS (            \
1885         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
1886 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS (            \
1887         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
1888 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS (            \
1889         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
1890 #define GLK_DPIO_CMN_A_POWER_DOMAINS (                  \
1891         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
1892         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1893         BIT_ULL(POWER_DOMAIN_INIT))
1894 #define GLK_DPIO_CMN_B_POWER_DOMAINS (                  \
1895         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1896         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
1897         BIT_ULL(POWER_DOMAIN_INIT))
1898 #define GLK_DPIO_CMN_C_POWER_DOMAINS (                  \
1899         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1900         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1901         BIT_ULL(POWER_DOMAIN_INIT))
1902 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS (               \
1903         BIT_ULL(POWER_DOMAIN_AUX_A) |           \
1904         BIT_ULL(POWER_DOMAIN_AUX_IO_A) |                \
1905         BIT_ULL(POWER_DOMAIN_INIT))
1906 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS (               \
1907         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1908         BIT_ULL(POWER_DOMAIN_INIT))
1909 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS (               \
1910         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1911         BIT_ULL(POWER_DOMAIN_INIT))
1912 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS (              \
1913         GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
1914         BIT_ULL(POWER_DOMAIN_GT_IRQ) |                  \
1915         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
1916         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1917         BIT_ULL(POWER_DOMAIN_GMBUS) |                   \
1918         BIT_ULL(POWER_DOMAIN_INIT))
1919
1920 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
1921         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1922         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1923         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1924         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1925         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1926         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1927         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1928         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1929         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1930         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1931         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |                \
1932         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
1933         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1934         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
1935         BIT_ULL(POWER_DOMAIN_AUX_F) |                   \
1936         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1937         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1938         BIT_ULL(POWER_DOMAIN_INIT))
1939 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (            \
1940         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
1941         BIT_ULL(POWER_DOMAIN_INIT))
1942 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (            \
1943         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
1944         BIT_ULL(POWER_DOMAIN_INIT))
1945 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (            \
1946         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
1947         BIT_ULL(POWER_DOMAIN_INIT))
1948 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (            \
1949         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
1950         BIT_ULL(POWER_DOMAIN_INIT))
1951 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS (               \
1952         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1953         BIT_ULL(POWER_DOMAIN_AUX_IO_A) |                \
1954         BIT_ULL(POWER_DOMAIN_INIT))
1955 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS (               \
1956         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
1957         BIT_ULL(POWER_DOMAIN_INIT))
1958 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS (               \
1959         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
1960         BIT_ULL(POWER_DOMAIN_INIT))
1961 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS (               \
1962         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
1963         BIT_ULL(POWER_DOMAIN_INIT))
1964 #define CNL_DISPLAY_AUX_F_POWER_DOMAINS (               \
1965         BIT_ULL(POWER_DOMAIN_AUX_F) |                   \
1966         BIT_ULL(POWER_DOMAIN_INIT))
1967 #define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS (            \
1968         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) |           \
1969         BIT_ULL(POWER_DOMAIN_INIT))
1970 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
1971         CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
1972         BIT_ULL(POWER_DOMAIN_GT_IRQ) |                  \
1973         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
1974         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
1975         BIT_ULL(POWER_DOMAIN_INIT))
1976
1977 /*
1978  * ICL PW_0/PG_0 domains (HW/DMC control):
1979  * - PCI
1980  * - clocks except port PLL
1981  * - central power except FBC
1982  * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
1983  * ICL PW_1/PG_1 domains (HW/DMC control):
1984  * - DBUF function
1985  * - PIPE_A and its planes, except VGA
1986  * - transcoder EDP + PSR
1987  * - transcoder DSI
1988  * - DDI_A
1989  * - FBC
1990  */
1991 #define ICL_PW_4_POWER_DOMAINS (                        \
1992         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1993         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |     \
1994         BIT_ULL(POWER_DOMAIN_INIT))
1995         /* VDSC/joining */
1996 #define ICL_PW_3_POWER_DOMAINS (                        \
1997         ICL_PW_4_POWER_DOMAINS |                        \
1998         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1999         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
2000         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
2001         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
2002         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
2003         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
2004         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
2005         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
2006         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
2007         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
2008         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
2009         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |        \
2010         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
2011         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |        \
2012         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) |           \
2013         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
2014         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
2015         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
2016         BIT_ULL(POWER_DOMAIN_AUX_E) |                   \
2017         BIT_ULL(POWER_DOMAIN_AUX_F) |                   \
2018         BIT_ULL(POWER_DOMAIN_AUX_TBT1) |                \
2019         BIT_ULL(POWER_DOMAIN_AUX_TBT2) |                \
2020         BIT_ULL(POWER_DOMAIN_AUX_TBT3) |                \
2021         BIT_ULL(POWER_DOMAIN_AUX_TBT4) |                \
2022         BIT_ULL(POWER_DOMAIN_VGA) |                     \
2023         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
2024         BIT_ULL(POWER_DOMAIN_INIT))
2025         /*
2026          * - transcoder WD
2027          * - KVMR (HW control)
2028          */
2029 #define ICL_PW_2_POWER_DOMAINS (                        \
2030         ICL_PW_3_POWER_DOMAINS |                        \
2031         BIT_ULL(POWER_DOMAIN_INIT))
2032         /*
2033          * - eDP/DSI VDSC
2034          * - KVMR (HW control)
2035          */
2036 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
2037         ICL_PW_2_POWER_DOMAINS |                        \
2038         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
2039         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
2040         BIT_ULL(POWER_DOMAIN_INIT))
2041
2042 #define ICL_DDI_IO_A_POWER_DOMAINS (                    \
2043         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
2044 #define ICL_DDI_IO_B_POWER_DOMAINS (                    \
2045         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
2046 #define ICL_DDI_IO_C_POWER_DOMAINS (                    \
2047         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
2048 #define ICL_DDI_IO_D_POWER_DOMAINS (                    \
2049         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
2050 #define ICL_DDI_IO_E_POWER_DOMAINS (                    \
2051         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
2052 #define ICL_DDI_IO_F_POWER_DOMAINS (                    \
2053         BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
2054
2055 #define ICL_AUX_A_IO_POWER_DOMAINS (                    \
2056         BIT_ULL(POWER_DOMAIN_AUX_IO_A) |                \
2057         BIT_ULL(POWER_DOMAIN_AUX_A))
2058 #define ICL_AUX_B_IO_POWER_DOMAINS (                    \
2059         BIT_ULL(POWER_DOMAIN_AUX_B))
2060 #define ICL_AUX_C_IO_POWER_DOMAINS (                    \
2061         BIT_ULL(POWER_DOMAIN_AUX_C))
2062 #define ICL_AUX_D_IO_POWER_DOMAINS (                    \
2063         BIT_ULL(POWER_DOMAIN_AUX_D))
2064 #define ICL_AUX_E_IO_POWER_DOMAINS (                    \
2065         BIT_ULL(POWER_DOMAIN_AUX_E))
2066 #define ICL_AUX_F_IO_POWER_DOMAINS (                    \
2067         BIT_ULL(POWER_DOMAIN_AUX_F))
2068 #define ICL_AUX_TBT1_IO_POWER_DOMAINS (                 \
2069         BIT_ULL(POWER_DOMAIN_AUX_TBT1))
2070 #define ICL_AUX_TBT2_IO_POWER_DOMAINS (                 \
2071         BIT_ULL(POWER_DOMAIN_AUX_TBT2))
2072 #define ICL_AUX_TBT3_IO_POWER_DOMAINS (                 \
2073         BIT_ULL(POWER_DOMAIN_AUX_TBT3))
2074 #define ICL_AUX_TBT4_IO_POWER_DOMAINS (                 \
2075         BIT_ULL(POWER_DOMAIN_AUX_TBT4))
2076
2077 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
2078         .sync_hw = i9xx_power_well_sync_hw_noop,
2079         .enable = i9xx_always_on_power_well_noop,
2080         .disable = i9xx_always_on_power_well_noop,
2081         .is_enabled = i9xx_always_on_power_well_enabled,
2082 };
2083
2084 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
2085         .sync_hw = i9xx_power_well_sync_hw_noop,
2086         .enable = chv_pipe_power_well_enable,
2087         .disable = chv_pipe_power_well_disable,
2088         .is_enabled = chv_pipe_power_well_enabled,
2089 };
2090
2091 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
2092         .sync_hw = i9xx_power_well_sync_hw_noop,
2093         .enable = chv_dpio_cmn_power_well_enable,
2094         .disable = chv_dpio_cmn_power_well_disable,
2095         .is_enabled = vlv_power_well_enabled,
2096 };
2097
2098 static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
2099         {
2100                 .name = "always-on",
2101                 .always_on = true,
2102                 .domains = POWER_DOMAIN_MASK,
2103                 .ops = &i9xx_always_on_power_well_ops,
2104                 .id = DISP_PW_ID_NONE,
2105         },
2106 };
2107
2108 static const struct i915_power_well_ops i830_pipes_power_well_ops = {
2109         .sync_hw = i830_pipes_power_well_sync_hw,
2110         .enable = i830_pipes_power_well_enable,
2111         .disable = i830_pipes_power_well_disable,
2112         .is_enabled = i830_pipes_power_well_enabled,
2113 };
2114
2115 static const struct i915_power_well_desc i830_power_wells[] = {
2116         {
2117                 .name = "always-on",
2118                 .always_on = true,
2119                 .domains = POWER_DOMAIN_MASK,
2120                 .ops = &i9xx_always_on_power_well_ops,
2121                 .id = DISP_PW_ID_NONE,
2122         },
2123         {
2124                 .name = "pipes",
2125                 .domains = I830_PIPES_POWER_DOMAINS,
2126                 .ops = &i830_pipes_power_well_ops,
2127                 .id = DISP_PW_ID_NONE,
2128         },
2129 };
2130
2131 static const struct i915_power_well_ops hsw_power_well_ops = {
2132         .sync_hw = hsw_power_well_sync_hw,
2133         .enable = hsw_power_well_enable,
2134         .disable = hsw_power_well_disable,
2135         .is_enabled = hsw_power_well_enabled,
2136 };
2137
2138 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
2139         .sync_hw = i9xx_power_well_sync_hw_noop,
2140         .enable = gen9_dc_off_power_well_enable,
2141         .disable = gen9_dc_off_power_well_disable,
2142         .is_enabled = gen9_dc_off_power_well_enabled,
2143 };
2144
2145 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
2146         .sync_hw = i9xx_power_well_sync_hw_noop,
2147         .enable = bxt_dpio_cmn_power_well_enable,
2148         .disable = bxt_dpio_cmn_power_well_disable,
2149         .is_enabled = bxt_dpio_cmn_power_well_enabled,
2150 };
2151
2152 static const struct i915_power_well_regs hsw_power_well_regs = {
2153         .bios   = HSW_PWR_WELL_CTL1,
2154         .driver = HSW_PWR_WELL_CTL2,
2155         .kvmr   = HSW_PWR_WELL_CTL3,
2156         .debug  = HSW_PWR_WELL_CTL4,
2157 };
2158
2159 static const struct i915_power_well_desc hsw_power_wells[] = {
2160         {
2161                 .name = "always-on",
2162                 .always_on = true,
2163                 .domains = POWER_DOMAIN_MASK,
2164                 .ops = &i9xx_always_on_power_well_ops,
2165                 .id = DISP_PW_ID_NONE,
2166         },
2167         {
2168                 .name = "display",
2169                 .domains = HSW_DISPLAY_POWER_DOMAINS,
2170                 .ops = &hsw_power_well_ops,
2171                 .id = HSW_DISP_PW_GLOBAL,
2172                 {
2173                         .hsw.regs = &hsw_power_well_regs,
2174                         .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
2175                         .hsw.has_vga = true,
2176                 },
2177         },
2178 };
2179
2180 static const struct i915_power_well_desc bdw_power_wells[] = {
2181         {
2182                 .name = "always-on",
2183                 .always_on = true,
2184                 .domains = POWER_DOMAIN_MASK,
2185                 .ops = &i9xx_always_on_power_well_ops,
2186                 .id = DISP_PW_ID_NONE,
2187         },
2188         {
2189                 .name = "display",
2190                 .domains = BDW_DISPLAY_POWER_DOMAINS,
2191                 .ops = &hsw_power_well_ops,
2192                 .id = HSW_DISP_PW_GLOBAL,
2193                 {
2194                         .hsw.regs = &hsw_power_well_regs,
2195                         .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
2196                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2197                         .hsw.has_vga = true,
2198                 },
2199         },
2200 };
2201
2202 static const struct i915_power_well_ops vlv_display_power_well_ops = {
2203         .sync_hw = i9xx_power_well_sync_hw_noop,
2204         .enable = vlv_display_power_well_enable,
2205         .disable = vlv_display_power_well_disable,
2206         .is_enabled = vlv_power_well_enabled,
2207 };
2208
2209 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
2210         .sync_hw = i9xx_power_well_sync_hw_noop,
2211         .enable = vlv_dpio_cmn_power_well_enable,
2212         .disable = vlv_dpio_cmn_power_well_disable,
2213         .is_enabled = vlv_power_well_enabled,
2214 };
2215
2216 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
2217         .sync_hw = i9xx_power_well_sync_hw_noop,
2218         .enable = vlv_power_well_enable,
2219         .disable = vlv_power_well_disable,
2220         .is_enabled = vlv_power_well_enabled,
2221 };
2222
2223 static const struct i915_power_well_desc vlv_power_wells[] = {
2224         {
2225                 .name = "always-on",
2226                 .always_on = true,
2227                 .domains = POWER_DOMAIN_MASK,
2228                 .ops = &i9xx_always_on_power_well_ops,
2229                 .id = DISP_PW_ID_NONE,
2230         },
2231         {
2232                 .name = "display",
2233                 .domains = VLV_DISPLAY_POWER_DOMAINS,
2234                 .ops = &vlv_display_power_well_ops,
2235                 .id = VLV_DISP_PW_DISP2D,
2236                 {
2237                         .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
2238                 },
2239         },
2240         {
2241                 .name = "dpio-tx-b-01",
2242                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2243                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2244                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2245                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2246                 .ops = &vlv_dpio_power_well_ops,
2247                 .id = DISP_PW_ID_NONE,
2248                 {
2249                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
2250                 },
2251         },
2252         {
2253                 .name = "dpio-tx-b-23",
2254                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2255                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2256                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2257                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2258                 .ops = &vlv_dpio_power_well_ops,
2259                 .id = DISP_PW_ID_NONE,
2260                 {
2261                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
2262                 },
2263         },
2264         {
2265                 .name = "dpio-tx-c-01",
2266                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2267                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2268                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2269                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2270                 .ops = &vlv_dpio_power_well_ops,
2271                 .id = DISP_PW_ID_NONE,
2272                 {
2273                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
2274                 },
2275         },
2276         {
2277                 .name = "dpio-tx-c-23",
2278                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2279                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2280                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2281                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2282                 .ops = &vlv_dpio_power_well_ops,
2283                 .id = DISP_PW_ID_NONE,
2284                 {
2285                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
2286                 },
2287         },
2288         {
2289                 .name = "dpio-common",
2290                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
2291                 .ops = &vlv_dpio_cmn_power_well_ops,
2292                 .id = VLV_DISP_PW_DPIO_CMN_BC,
2293                 {
2294                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
2295                 },
2296         },
2297 };
2298
2299 static const struct i915_power_well_desc chv_power_wells[] = {
2300         {
2301                 .name = "always-on",
2302                 .always_on = true,
2303                 .domains = POWER_DOMAIN_MASK,
2304                 .ops = &i9xx_always_on_power_well_ops,
2305                 .id = DISP_PW_ID_NONE,
2306         },
2307         {
2308                 .name = "display",
2309                 /*
2310                  * Pipe A power well is the new disp2d well. Pipe B and C
2311                  * power wells don't actually exist. Pipe A power well is
2312                  * required for any pipe to work.
2313                  */
2314                 .domains = CHV_DISPLAY_POWER_DOMAINS,
2315                 .ops = &chv_pipe_power_well_ops,
2316                 .id = DISP_PW_ID_NONE,
2317         },
2318         {
2319                 .name = "dpio-common-bc",
2320                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2321                 .ops = &chv_dpio_cmn_power_well_ops,
2322                 .id = VLV_DISP_PW_DPIO_CMN_BC,
2323                 {
2324                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
2325                 },
2326         },
2327         {
2328                 .name = "dpio-common-d",
2329                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2330                 .ops = &chv_dpio_cmn_power_well_ops,
2331                 .id = CHV_DISP_PW_DPIO_CMN_D,
2332                 {
2333                         .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
2334                 },
2335         },
2336 };
2337
2338 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2339                                          enum i915_power_well_id power_well_id)
2340 {
2341         struct i915_power_well *power_well;
2342         bool ret;
2343
2344         power_well = lookup_power_well(dev_priv, power_well_id);
2345         ret = power_well->desc->ops->is_enabled(dev_priv, power_well);
2346
2347         return ret;
2348 }
2349
2350 static const struct i915_power_well_desc skl_power_wells[] = {
2351         {
2352                 .name = "always-on",
2353                 .always_on = true,
2354                 .domains = POWER_DOMAIN_MASK,
2355                 .ops = &i9xx_always_on_power_well_ops,
2356                 .id = DISP_PW_ID_NONE,
2357         },
2358         {
2359                 .name = "power well 1",
2360                 /* Handled by the DMC firmware */
2361                 .always_on = true,
2362                 .domains = 0,
2363                 .ops = &hsw_power_well_ops,
2364                 .id = SKL_DISP_PW_1,
2365                 {
2366                         .hsw.regs = &hsw_power_well_regs,
2367                         .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2368                         .hsw.has_fuses = true,
2369                 },
2370         },
2371         {
2372                 .name = "MISC IO power well",
2373                 /* Handled by the DMC firmware */
2374                 .always_on = true,
2375                 .domains = 0,
2376                 .ops = &hsw_power_well_ops,
2377                 .id = SKL_DISP_PW_MISC_IO,
2378                 {
2379                         .hsw.regs = &hsw_power_well_regs,
2380                         .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
2381                 },
2382         },
2383         {
2384                 .name = "DC off",
2385                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2386                 .ops = &gen9_dc_off_power_well_ops,
2387                 .id = DISP_PW_ID_NONE,
2388         },
2389         {
2390                 .name = "power well 2",
2391                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2392                 .ops = &hsw_power_well_ops,
2393                 .id = SKL_DISP_PW_2,
2394                 {
2395                         .hsw.regs = &hsw_power_well_regs,
2396                         .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2397                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2398                         .hsw.has_vga = true,
2399                         .hsw.has_fuses = true,
2400                 },
2401         },
2402         {
2403                 .name = "DDI A/E IO power well",
2404                 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
2405                 .ops = &hsw_power_well_ops,
2406                 .id = DISP_PW_ID_NONE,
2407                 {
2408                         .hsw.regs = &hsw_power_well_regs,
2409                         .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
2410                 },
2411         },
2412         {
2413                 .name = "DDI B IO power well",
2414                 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2415                 .ops = &hsw_power_well_ops,
2416                 .id = DISP_PW_ID_NONE,
2417                 {
2418                         .hsw.regs = &hsw_power_well_regs,
2419                         .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2420                 },
2421         },
2422         {
2423                 .name = "DDI C IO power well",
2424                 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2425                 .ops = &hsw_power_well_ops,
2426                 .id = DISP_PW_ID_NONE,
2427                 {
2428                         .hsw.regs = &hsw_power_well_regs,
2429                         .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2430                 },
2431         },
2432         {
2433                 .name = "DDI D IO power well",
2434                 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
2435                 .ops = &hsw_power_well_ops,
2436                 .id = DISP_PW_ID_NONE,
2437                 {
2438                         .hsw.regs = &hsw_power_well_regs,
2439                         .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2440                 },
2441         },
2442 };
2443
2444 static const struct i915_power_well_desc bxt_power_wells[] = {
2445         {
2446                 .name = "always-on",
2447                 .always_on = true,
2448                 .domains = POWER_DOMAIN_MASK,
2449                 .ops = &i9xx_always_on_power_well_ops,
2450                 .id = DISP_PW_ID_NONE,
2451         },
2452         {
2453                 .name = "power well 1",
2454                 /* Handled by the DMC firmware */
2455                 .always_on = true,
2456                 .domains = 0,
2457                 .ops = &hsw_power_well_ops,
2458                 .id = SKL_DISP_PW_1,
2459                 {
2460                         .hsw.regs = &hsw_power_well_regs,
2461                         .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2462                         .hsw.has_fuses = true,
2463                 },
2464         },
2465         {
2466                 .name = "DC off",
2467                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2468                 .ops = &gen9_dc_off_power_well_ops,
2469                 .id = DISP_PW_ID_NONE,
2470         },
2471         {
2472                 .name = "power well 2",
2473                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2474                 .ops = &hsw_power_well_ops,
2475                 .id = SKL_DISP_PW_2,
2476                 {
2477                         .hsw.regs = &hsw_power_well_regs,
2478                         .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2479                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2480                         .hsw.has_vga = true,
2481                         .hsw.has_fuses = true,
2482                 },
2483         },
2484         {
2485                 .name = "dpio-common-a",
2486                 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2487                 .ops = &bxt_dpio_cmn_power_well_ops,
2488                 .id = BXT_DISP_PW_DPIO_CMN_A,
2489                 {
2490                         .bxt.phy = DPIO_PHY1,
2491                 },
2492         },
2493         {
2494                 .name = "dpio-common-bc",
2495                 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2496                 .ops = &bxt_dpio_cmn_power_well_ops,
2497                 .id = VLV_DISP_PW_DPIO_CMN_BC,
2498                 {
2499                         .bxt.phy = DPIO_PHY0,
2500                 },
2501         },
2502 };
2503
2504 static const struct i915_power_well_desc glk_power_wells[] = {
2505         {
2506                 .name = "always-on",
2507                 .always_on = true,
2508                 .domains = POWER_DOMAIN_MASK,
2509                 .ops = &i9xx_always_on_power_well_ops,
2510                 .id = DISP_PW_ID_NONE,
2511         },
2512         {
2513                 .name = "power well 1",
2514                 /* Handled by the DMC firmware */
2515                 .always_on = true,
2516                 .domains = 0,
2517                 .ops = &hsw_power_well_ops,
2518                 .id = SKL_DISP_PW_1,
2519                 {
2520                         .hsw.regs = &hsw_power_well_regs,
2521                         .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2522                         .hsw.has_fuses = true,
2523                 },
2524         },
2525         {
2526                 .name = "DC off",
2527                 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
2528                 .ops = &gen9_dc_off_power_well_ops,
2529                 .id = DISP_PW_ID_NONE,
2530         },
2531         {
2532                 .name = "power well 2",
2533                 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2534                 .ops = &hsw_power_well_ops,
2535                 .id = SKL_DISP_PW_2,
2536                 {
2537                         .hsw.regs = &hsw_power_well_regs,
2538                         .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2539                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2540                         .hsw.has_vga = true,
2541                         .hsw.has_fuses = true,
2542                 },
2543         },
2544         {
2545                 .name = "dpio-common-a",
2546                 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
2547                 .ops = &bxt_dpio_cmn_power_well_ops,
2548                 .id = BXT_DISP_PW_DPIO_CMN_A,
2549                 {
2550                         .bxt.phy = DPIO_PHY1,
2551                 },
2552         },
2553         {
2554                 .name = "dpio-common-b",
2555                 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
2556                 .ops = &bxt_dpio_cmn_power_well_ops,
2557                 .id = VLV_DISP_PW_DPIO_CMN_BC,
2558                 {
2559                         .bxt.phy = DPIO_PHY0,
2560                 },
2561         },
2562         {
2563                 .name = "dpio-common-c",
2564                 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
2565                 .ops = &bxt_dpio_cmn_power_well_ops,
2566                 .id = GLK_DISP_PW_DPIO_CMN_C,
2567                 {
2568                         .bxt.phy = DPIO_PHY2,
2569                 },
2570         },
2571         {
2572                 .name = "AUX A",
2573                 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
2574                 .ops = &hsw_power_well_ops,
2575                 .id = DISP_PW_ID_NONE,
2576                 {
2577                         .hsw.regs = &hsw_power_well_regs,
2578                         .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2579                 },
2580         },
2581         {
2582                 .name = "AUX B",
2583                 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
2584                 .ops = &hsw_power_well_ops,
2585                 .id = DISP_PW_ID_NONE,
2586                 {
2587                         .hsw.regs = &hsw_power_well_regs,
2588                         .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2589                 },
2590         },
2591         {
2592                 .name = "AUX C",
2593                 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
2594                 .ops = &hsw_power_well_ops,
2595                 .id = DISP_PW_ID_NONE,
2596                 {
2597                         .hsw.regs = &hsw_power_well_regs,
2598                         .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2599                 },
2600         },
2601         {
2602                 .name = "DDI A IO power well",
2603                 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
2604                 .ops = &hsw_power_well_ops,
2605                 .id = DISP_PW_ID_NONE,
2606                 {
2607                         .hsw.regs = &hsw_power_well_regs,
2608                         .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2609                 },
2610         },
2611         {
2612                 .name = "DDI B IO power well",
2613                 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2614                 .ops = &hsw_power_well_ops,
2615                 .id = DISP_PW_ID_NONE,
2616                 {
2617                         .hsw.regs = &hsw_power_well_regs,
2618                         .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2619                 },
2620         },
2621         {
2622                 .name = "DDI C IO power well",
2623                 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2624                 .ops = &hsw_power_well_ops,
2625                 .id = DISP_PW_ID_NONE,
2626                 {
2627                         .hsw.regs = &hsw_power_well_regs,
2628                         .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2629                 },
2630         },
2631 };
2632
2633 static const struct i915_power_well_desc cnl_power_wells[] = {
2634         {
2635                 .name = "always-on",
2636                 .always_on = true,
2637                 .domains = POWER_DOMAIN_MASK,
2638                 .ops = &i9xx_always_on_power_well_ops,
2639                 .id = DISP_PW_ID_NONE,
2640         },
2641         {
2642                 .name = "power well 1",
2643                 /* Handled by the DMC firmware */
2644                 .always_on = true,
2645                 .domains = 0,
2646                 .ops = &hsw_power_well_ops,
2647                 .id = SKL_DISP_PW_1,
2648                 {
2649                         .hsw.regs = &hsw_power_well_regs,
2650                         .hsw.idx = SKL_PW_CTL_IDX_PW_1,
2651                         .hsw.has_fuses = true,
2652                 },
2653         },
2654         {
2655                 .name = "AUX A",
2656                 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
2657                 .ops = &hsw_power_well_ops,
2658                 .id = DISP_PW_ID_NONE,
2659                 {
2660                         .hsw.regs = &hsw_power_well_regs,
2661                         .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
2662                 },
2663         },
2664         {
2665                 .name = "AUX B",
2666                 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
2667                 .ops = &hsw_power_well_ops,
2668                 .id = DISP_PW_ID_NONE,
2669                 {
2670                         .hsw.regs = &hsw_power_well_regs,
2671                         .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
2672                 },
2673         },
2674         {
2675                 .name = "AUX C",
2676                 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
2677                 .ops = &hsw_power_well_ops,
2678                 .id = DISP_PW_ID_NONE,
2679                 {
2680                         .hsw.regs = &hsw_power_well_regs,
2681                         .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
2682                 },
2683         },
2684         {
2685                 .name = "AUX D",
2686                 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
2687                 .ops = &hsw_power_well_ops,
2688                 .id = DISP_PW_ID_NONE,
2689                 {
2690                         .hsw.regs = &hsw_power_well_regs,
2691                         .hsw.idx = CNL_PW_CTL_IDX_AUX_D,
2692                 },
2693         },
2694         {
2695                 .name = "DC off",
2696                 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
2697                 .ops = &gen9_dc_off_power_well_ops,
2698                 .id = DISP_PW_ID_NONE,
2699         },
2700         {
2701                 .name = "power well 2",
2702                 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2703                 .ops = &hsw_power_well_ops,
2704                 .id = SKL_DISP_PW_2,
2705                 {
2706                         .hsw.regs = &hsw_power_well_regs,
2707                         .hsw.idx = SKL_PW_CTL_IDX_PW_2,
2708                         .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2709                         .hsw.has_vga = true,
2710                         .hsw.has_fuses = true,
2711                 },
2712         },
2713         {
2714                 .name = "DDI A IO power well",
2715                 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
2716                 .ops = &hsw_power_well_ops,
2717                 .id = DISP_PW_ID_NONE,
2718                 {
2719                         .hsw.regs = &hsw_power_well_regs,
2720                         .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
2721                 },
2722         },
2723         {
2724                 .name = "DDI B IO power well",
2725                 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
2726                 .ops = &hsw_power_well_ops,
2727                 .id = DISP_PW_ID_NONE,
2728                 {
2729                         .hsw.regs = &hsw_power_well_regs,
2730                         .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
2731                 },
2732         },
2733         {
2734                 .name = "DDI C IO power well",
2735                 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
2736                 .ops = &hsw_power_well_ops,
2737                 .id = DISP_PW_ID_NONE,
2738                 {
2739                         .hsw.regs = &hsw_power_well_regs,
2740                         .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
2741                 },
2742         },
2743         {
2744                 .name = "DDI D IO power well",
2745                 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
2746                 .ops = &hsw_power_well_ops,
2747                 .id = DISP_PW_ID_NONE,
2748                 {
2749                         .hsw.regs = &hsw_power_well_regs,
2750                         .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
2751                 },
2752         },
2753         {
2754                 .name = "DDI F IO power well",
2755                 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
2756                 .ops = &hsw_power_well_ops,
2757                 .id = DISP_PW_ID_NONE,
2758                 {
2759                         .hsw.regs = &hsw_power_well_regs,
2760                         .hsw.idx = CNL_PW_CTL_IDX_DDI_F,
2761                 },
2762         },
2763         {
2764                 .name = "AUX F",
2765                 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
2766                 .ops = &hsw_power_well_ops,
2767                 .id = DISP_PW_ID_NONE,
2768                 {
2769                         .hsw.regs = &hsw_power_well_regs,
2770                         .hsw.idx = CNL_PW_CTL_IDX_AUX_F,
2771                 },
2772         },
2773 };
2774
2775 static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = {
2776         .sync_hw = hsw_power_well_sync_hw,
2777         .enable = icl_combo_phy_aux_power_well_enable,
2778         .disable = icl_combo_phy_aux_power_well_disable,
2779         .is_enabled = hsw_power_well_enabled,
2780 };
2781
2782 static const struct i915_power_well_ops icl_tc_phy_aux_power_well_ops = {
2783         .sync_hw = hsw_power_well_sync_hw,
2784         .enable = icl_tc_phy_aux_power_well_enable,
2785         .disable = hsw_power_well_disable,
2786         .is_enabled = hsw_power_well_enabled,
2787 };
2788
2789 static const struct i915_power_well_regs icl_aux_power_well_regs = {
2790         .bios   = ICL_PWR_WELL_CTL_AUX1,
2791         .driver = ICL_PWR_WELL_CTL_AUX2,
2792         .debug  = ICL_PWR_WELL_CTL_AUX4,
2793 };
2794
2795 static const struct i915_power_well_regs icl_ddi_power_well_regs = {
2796         .bios   = ICL_PWR_WELL_CTL_DDI1,
2797         .driver = ICL_PWR_WELL_CTL_DDI2,
2798         .debug  = ICL_PWR_WELL_CTL_DDI4,
2799 };
2800
2801 static const struct i915_power_well_desc icl_power_wells[] = {
2802         {
2803                 .name = "always-on",
2804                 .always_on = true,
2805                 .domains = POWER_DOMAIN_MASK,
2806                 .ops = &i9xx_always_on_power_well_ops,
2807                 .id = DISP_PW_ID_NONE,
2808         },
2809         {
2810                 .name = "power well 1",
2811                 /* Handled by the DMC firmware */
2812                 .always_on = true,
2813                 .domains = 0,
2814                 .ops = &hsw_power_well_ops,
2815                 .id = SKL_DISP_PW_1,
2816                 {
2817                         .hsw.regs = &hsw_power_well_regs,
2818                         .hsw.idx = ICL_PW_CTL_IDX_PW_1,
2819                         .hsw.has_fuses = true,
2820                 },
2821         },
2822         {
2823                 .name = "DC off",
2824                 .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
2825                 .ops = &gen9_dc_off_power_well_ops,
2826                 .id = DISP_PW_ID_NONE,
2827         },
2828         {
2829                 .name = "power well 2",
2830                 .domains = ICL_PW_2_POWER_DOMAINS,
2831                 .ops = &hsw_power_well_ops,
2832                 .id = SKL_DISP_PW_2,
2833                 {
2834                         .hsw.regs = &hsw_power_well_regs,
2835                         .hsw.idx = ICL_PW_CTL_IDX_PW_2,
2836                         .hsw.has_fuses = true,
2837                 },
2838         },
2839         {
2840                 .name = "power well 3",
2841                 .domains = ICL_PW_3_POWER_DOMAINS,
2842                 .ops = &hsw_power_well_ops,
2843                 .id = DISP_PW_ID_NONE,
2844                 {
2845                         .hsw.regs = &hsw_power_well_regs,
2846                         .hsw.idx = ICL_PW_CTL_IDX_PW_3,
2847                         .hsw.irq_pipe_mask = BIT(PIPE_B),
2848                         .hsw.has_vga = true,
2849                         .hsw.has_fuses = true,
2850                 },
2851         },
2852         {
2853                 .name = "DDI A IO",
2854                 .domains = ICL_DDI_IO_A_POWER_DOMAINS,
2855                 .ops = &hsw_power_well_ops,
2856                 .id = DISP_PW_ID_NONE,
2857                 {
2858                         .hsw.regs = &icl_ddi_power_well_regs,
2859                         .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
2860                 },
2861         },
2862         {
2863                 .name = "DDI B IO",
2864                 .domains = ICL_DDI_IO_B_POWER_DOMAINS,
2865                 .ops = &hsw_power_well_ops,
2866                 .id = DISP_PW_ID_NONE,
2867                 {
2868                         .hsw.regs = &icl_ddi_power_well_regs,
2869                         .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
2870                 },
2871         },
2872         {
2873                 .name = "DDI C IO",
2874                 .domains = ICL_DDI_IO_C_POWER_DOMAINS,
2875                 .ops = &hsw_power_well_ops,
2876                 .id = DISP_PW_ID_NONE,
2877                 {
2878                         .hsw.regs = &icl_ddi_power_well_regs,
2879                         .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
2880                 },
2881         },
2882         {
2883                 .name = "DDI D IO",
2884                 .domains = ICL_DDI_IO_D_POWER_DOMAINS,
2885                 .ops = &hsw_power_well_ops,
2886                 .id = DISP_PW_ID_NONE,
2887                 {
2888                         .hsw.regs = &icl_ddi_power_well_regs,
2889                         .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
2890                 },
2891         },
2892         {
2893                 .name = "DDI E IO",
2894                 .domains = ICL_DDI_IO_E_POWER_DOMAINS,
2895                 .ops = &hsw_power_well_ops,
2896                 .id = DISP_PW_ID_NONE,
2897                 {
2898                         .hsw.regs = &icl_ddi_power_well_regs,
2899                         .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
2900                 },
2901         },
2902         {
2903                 .name = "DDI F IO",
2904                 .domains = ICL_DDI_IO_F_POWER_DOMAINS,
2905                 .ops = &hsw_power_well_ops,
2906                 .id = DISP_PW_ID_NONE,
2907                 {
2908                         .hsw.regs = &icl_ddi_power_well_regs,
2909                         .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
2910                 },
2911         },
2912         {
2913                 .name = "AUX A",
2914                 .domains = ICL_AUX_A_IO_POWER_DOMAINS,
2915                 .ops = &icl_combo_phy_aux_power_well_ops,
2916                 .id = DISP_PW_ID_NONE,
2917                 {
2918                         .hsw.regs = &icl_aux_power_well_regs,
2919                         .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
2920                 },
2921         },
2922         {
2923                 .name = "AUX B",
2924                 .domains = ICL_AUX_B_IO_POWER_DOMAINS,
2925                 .ops = &icl_combo_phy_aux_power_well_ops,
2926                 .id = DISP_PW_ID_NONE,
2927                 {
2928                         .hsw.regs = &icl_aux_power_well_regs,
2929                         .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
2930                 },
2931         },
2932         {
2933                 .name = "AUX C",
2934                 .domains = ICL_AUX_C_IO_POWER_DOMAINS,
2935                 .ops = &icl_tc_phy_aux_power_well_ops,
2936                 .id = DISP_PW_ID_NONE,
2937                 {
2938                         .hsw.regs = &icl_aux_power_well_regs,
2939                         .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
2940                         .hsw.is_tc_tbt = false,
2941                 },
2942         },
2943         {
2944                 .name = "AUX D",
2945                 .domains = ICL_AUX_D_IO_POWER_DOMAINS,
2946                 .ops = &icl_tc_phy_aux_power_well_ops,
2947                 .id = DISP_PW_ID_NONE,
2948                 {
2949                         .hsw.regs = &icl_aux_power_well_regs,
2950                         .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
2951                         .hsw.is_tc_tbt = false,
2952                 },
2953         },
2954         {
2955                 .name = "AUX E",
2956                 .domains = ICL_AUX_E_IO_POWER_DOMAINS,
2957                 .ops = &icl_tc_phy_aux_power_well_ops,
2958                 .id = DISP_PW_ID_NONE,
2959                 {
2960                         .hsw.regs = &icl_aux_power_well_regs,
2961                         .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
2962                         .hsw.is_tc_tbt = false,
2963                 },
2964         },
2965         {
2966                 .name = "AUX F",
2967                 .domains = ICL_AUX_F_IO_POWER_DOMAINS,
2968                 .ops = &icl_tc_phy_aux_power_well_ops,
2969                 .id = DISP_PW_ID_NONE,
2970                 {
2971                         .hsw.regs = &icl_aux_power_well_regs,
2972                         .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
2973                         .hsw.is_tc_tbt = false,
2974                 },
2975         },
2976         {
2977                 .name = "AUX TBT1",
2978                 .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
2979                 .ops = &icl_tc_phy_aux_power_well_ops,
2980                 .id = DISP_PW_ID_NONE,
2981                 {
2982                         .hsw.regs = &icl_aux_power_well_regs,
2983                         .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
2984                         .hsw.is_tc_tbt = true,
2985                 },
2986         },
2987         {
2988                 .name = "AUX TBT2",
2989                 .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
2990                 .ops = &icl_tc_phy_aux_power_well_ops,
2991                 .id = DISP_PW_ID_NONE,
2992                 {
2993                         .hsw.regs = &icl_aux_power_well_regs,
2994                         .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
2995                         .hsw.is_tc_tbt = true,
2996                 },
2997         },
2998         {
2999                 .name = "AUX TBT3",
3000                 .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
3001                 .ops = &icl_tc_phy_aux_power_well_ops,
3002                 .id = DISP_PW_ID_NONE,
3003                 {
3004                         .hsw.regs = &icl_aux_power_well_regs,
3005                         .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
3006                         .hsw.is_tc_tbt = true,
3007                 },
3008         },
3009         {
3010                 .name = "AUX TBT4",
3011                 .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
3012                 .ops = &icl_tc_phy_aux_power_well_ops,
3013                 .id = DISP_PW_ID_NONE,
3014                 {
3015                         .hsw.regs = &icl_aux_power_well_regs,
3016                         .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
3017                         .hsw.is_tc_tbt = true,
3018                 },
3019         },
3020         {
3021                 .name = "power well 4",
3022                 .domains = ICL_PW_4_POWER_DOMAINS,
3023                 .ops = &hsw_power_well_ops,
3024                 .id = DISP_PW_ID_NONE,
3025                 {
3026                         .hsw.regs = &hsw_power_well_regs,
3027                         .hsw.idx = ICL_PW_CTL_IDX_PW_4,
3028                         .hsw.has_fuses = true,
3029                         .hsw.irq_pipe_mask = BIT(PIPE_C),
3030                 },
3031         },
3032 };
3033
3034 static int
3035 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
3036                                    int disable_power_well)
3037 {
3038         if (disable_power_well >= 0)
3039                 return !!disable_power_well;
3040
3041         return 1;
3042 }
3043
3044 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
3045                                     int enable_dc)
3046 {
3047         uint32_t mask;
3048         int requested_dc;
3049         int max_dc;
3050
3051         if (INTEL_GEN(dev_priv) >= 11) {
3052                 max_dc = 2;
3053                 /*
3054                  * DC9 has a separate HW flow from the rest of the DC states,
3055                  * not depending on the DMC firmware. It's needed by system
3056                  * suspend/resume, so allow it unconditionally.
3057                  */
3058                 mask = DC_STATE_EN_DC9;
3059         } else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) {
3060                 max_dc = 2;
3061                 mask = 0;
3062         } else if (IS_GEN9_LP(dev_priv)) {
3063                 max_dc = 1;
3064                 mask = DC_STATE_EN_DC9;
3065         } else {
3066                 max_dc = 0;
3067                 mask = 0;
3068         }
3069
3070         if (!i915_modparams.disable_power_well)
3071                 max_dc = 0;
3072
3073         if (enable_dc >= 0 && enable_dc <= max_dc) {
3074                 requested_dc = enable_dc;
3075         } else if (enable_dc == -1) {
3076                 requested_dc = max_dc;
3077         } else if (enable_dc > max_dc && enable_dc <= 2) {
3078                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
3079                               enable_dc, max_dc);
3080                 requested_dc = max_dc;
3081         } else {
3082                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
3083                 requested_dc = max_dc;
3084         }
3085
3086         if (requested_dc > 1)
3087                 mask |= DC_STATE_EN_UPTO_DC6;
3088         if (requested_dc > 0)
3089                 mask |= DC_STATE_EN_UPTO_DC5;
3090
3091         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
3092
3093         return mask;
3094 }
3095
3096 static int
3097 __set_power_wells(struct i915_power_domains *power_domains,
3098                   const struct i915_power_well_desc *power_well_descs,
3099                   int power_well_count)
3100 {
3101         u64 power_well_ids = 0;
3102         int i;
3103
3104         power_domains->power_well_count = power_well_count;
3105         power_domains->power_wells =
3106                                 kcalloc(power_well_count,
3107                                         sizeof(*power_domains->power_wells),
3108                                         GFP_KERNEL);
3109         if (!power_domains->power_wells)
3110                 return -ENOMEM;
3111
3112         for (i = 0; i < power_well_count; i++) {
3113                 enum i915_power_well_id id = power_well_descs[i].id;
3114
3115                 power_domains->power_wells[i].desc = &power_well_descs[i];
3116
3117                 if (id == DISP_PW_ID_NONE)
3118                         continue;
3119
3120                 WARN_ON(id >= sizeof(power_well_ids) * 8);
3121                 WARN_ON(power_well_ids & BIT_ULL(id));
3122                 power_well_ids |= BIT_ULL(id);
3123         }
3124
3125         return 0;
3126 }
3127
3128 #define set_power_wells(power_domains, __power_well_descs) \
3129         __set_power_wells(power_domains, __power_well_descs, \
3130                           ARRAY_SIZE(__power_well_descs))
3131
3132 /**
3133  * intel_power_domains_init - initializes the power domain structures
3134  * @dev_priv: i915 device instance
3135  *
3136  * Initializes the power domain structures for @dev_priv depending upon the
3137  * supported platform.
3138  */
3139 int intel_power_domains_init(struct drm_i915_private *dev_priv)
3140 {
3141         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3142         int err;
3143
3144         i915_modparams.disable_power_well =
3145                 sanitize_disable_power_well_option(dev_priv,
3146                                                    i915_modparams.disable_power_well);
3147         dev_priv->csr.allowed_dc_mask =
3148                 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc);
3149
3150         BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
3151
3152         mutex_init(&power_domains->lock);
3153
3154         /*
3155          * The enabling order will be from lower to higher indexed wells,
3156          * the disabling order is reversed.
3157          */
3158         if (IS_ICELAKE(dev_priv)) {
3159                 err = set_power_wells(power_domains, icl_power_wells);
3160         } else if (IS_CANNONLAKE(dev_priv)) {
3161                 err = set_power_wells(power_domains, cnl_power_wells);
3162
3163                 /*
3164                  * DDI and Aux IO are getting enabled for all ports
3165                  * regardless the presence or use. So, in order to avoid
3166                  * timeouts, lets remove them from the list
3167                  * for the SKUs without port F.
3168                  */
3169                 if (!IS_CNL_WITH_PORT_F(dev_priv))
3170                         power_domains->power_well_count -= 2;
3171         } else if (IS_GEMINILAKE(dev_priv)) {
3172                 err = set_power_wells(power_domains, glk_power_wells);
3173         } else if (IS_BROXTON(dev_priv)) {
3174                 err = set_power_wells(power_domains, bxt_power_wells);
3175         } else if (IS_GEN9_BC(dev_priv)) {
3176                 err = set_power_wells(power_domains, skl_power_wells);
3177         } else if (IS_CHERRYVIEW(dev_priv)) {
3178                 err = set_power_wells(power_domains, chv_power_wells);
3179         } else if (IS_BROADWELL(dev_priv)) {
3180                 err = set_power_wells(power_domains, bdw_power_wells);
3181         } else if (IS_HASWELL(dev_priv)) {
3182                 err = set_power_wells(power_domains, hsw_power_wells);
3183         } else if (IS_VALLEYVIEW(dev_priv)) {
3184                 err = set_power_wells(power_domains, vlv_power_wells);
3185         } else if (IS_I830(dev_priv)) {
3186                 err = set_power_wells(power_domains, i830_power_wells);
3187         } else {
3188                 err = set_power_wells(power_domains, i9xx_always_on_power_well);
3189         }
3190
3191         return err;
3192 }
3193
3194 /**
3195  * intel_power_domains_cleanup - clean up power domains resources
3196  * @dev_priv: i915 device instance
3197  *
3198  * Release any resources acquired by intel_power_domains_init()
3199  */
3200 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
3201 {
3202         kfree(dev_priv->power_domains.power_wells);
3203 }
3204
3205 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
3206 {
3207         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3208         struct i915_power_well *power_well;
3209
3210         mutex_lock(&power_domains->lock);
3211         for_each_power_well(dev_priv, power_well) {
3212                 power_well->desc->ops->sync_hw(dev_priv, power_well);
3213                 power_well->hw_enabled =
3214                         power_well->desc->ops->is_enabled(dev_priv, power_well);
3215         }
3216         mutex_unlock(&power_domains->lock);
3217 }
3218
3219 static inline
3220 bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
3221                           i915_reg_t reg, bool enable)
3222 {
3223         u32 val, status;
3224
3225         val = I915_READ(reg);
3226         val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST);
3227         I915_WRITE(reg, val);
3228         POSTING_READ(reg);
3229         udelay(10);
3230
3231         status = I915_READ(reg) & DBUF_POWER_STATE;
3232         if ((enable && !status) || (!enable && status)) {
3233                 DRM_ERROR("DBus power %s timeout!\n",
3234                           enable ? "enable" : "disable");
3235                 return false;
3236         }
3237         return true;
3238 }
3239
3240 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
3241 {
3242         intel_dbuf_slice_set(dev_priv, DBUF_CTL, true);
3243 }
3244
3245 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
3246 {
3247         intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
3248 }
3249
3250 static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
3251 {
3252         if (INTEL_GEN(dev_priv) < 11)
3253                 return 1;
3254         return 2;
3255 }
3256
3257 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
3258                             u8 req_slices)
3259 {
3260         const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
3261         bool ret;
3262
3263         if (req_slices > intel_dbuf_max_slices(dev_priv)) {
3264                 DRM_ERROR("Invalid number of dbuf slices requested\n");
3265                 return;
3266         }
3267
3268         if (req_slices == hw_enabled_slices || req_slices == 0)
3269                 return;
3270
3271         if (req_slices > hw_enabled_slices)
3272                 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
3273         else
3274                 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
3275
3276         if (ret)
3277                 dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
3278 }
3279
3280 static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
3281 {
3282         I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
3283         I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
3284         POSTING_READ(DBUF_CTL_S2);
3285
3286         udelay(10);
3287
3288         if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
3289             !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
3290                 DRM_ERROR("DBuf power enable timeout\n");
3291         else
3292                 dev_priv->wm.skl_hw.ddb.enabled_slices = 2;
3293 }
3294
3295 static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
3296 {
3297         I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
3298         I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
3299         POSTING_READ(DBUF_CTL_S2);
3300
3301         udelay(10);
3302
3303         if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
3304             (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
3305                 DRM_ERROR("DBuf power disable timeout!\n");
3306         else
3307                 dev_priv->wm.skl_hw.ddb.enabled_slices = 0;
3308 }
3309
3310 static void icl_mbus_init(struct drm_i915_private *dev_priv)
3311 {
3312         uint32_t val;
3313
3314         val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
3315               MBUS_ABOX_BT_CREDIT_POOL2(16) |
3316               MBUS_ABOX_B_CREDIT(1) |
3317               MBUS_ABOX_BW_CREDIT(1);
3318
3319         I915_WRITE(MBUS_ABOX_CTL, val);
3320 }
3321
3322 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
3323                                       bool enable)
3324 {
3325         i915_reg_t reg;
3326         u32 reset_bits, val;
3327
3328         if (IS_IVYBRIDGE(dev_priv)) {
3329                 reg = GEN7_MSG_CTL;
3330                 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
3331         } else {
3332                 reg = HSW_NDE_RSTWRN_OPT;
3333                 reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
3334         }
3335
3336         val = I915_READ(reg);
3337
3338         if (enable)
3339                 val |= reset_bits;
3340         else
3341                 val &= ~reset_bits;
3342
3343         I915_WRITE(reg, val);
3344 }
3345
3346 static void skl_display_core_init(struct drm_i915_private *dev_priv,
3347                                    bool resume)
3348 {
3349         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3350         struct i915_power_well *well;
3351
3352         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3353
3354         /* enable PCH reset handshake */
3355         intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
3356
3357         /* enable PG1 and Misc I/O */
3358         mutex_lock(&power_domains->lock);
3359
3360         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3361         intel_power_well_enable(dev_priv, well);
3362
3363         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
3364         intel_power_well_enable(dev_priv, well);
3365
3366         mutex_unlock(&power_domains->lock);
3367
3368         skl_init_cdclk(dev_priv);
3369
3370         gen9_dbuf_enable(dev_priv);
3371
3372         if (resume && dev_priv->csr.dmc_payload)
3373                 intel_csr_load_program(dev_priv);
3374 }
3375
3376 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
3377 {
3378         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3379         struct i915_power_well *well;
3380
3381         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3382
3383         gen9_dbuf_disable(dev_priv);
3384
3385         skl_uninit_cdclk(dev_priv);
3386
3387         /* The spec doesn't call for removing the reset handshake flag */
3388         /* disable PG1 and Misc I/O */
3389
3390         mutex_lock(&power_domains->lock);
3391
3392         /*
3393          * BSpec says to keep the MISC IO power well enabled here, only
3394          * remove our request for power well 1.
3395          * Note that even though the driver's request is removed power well 1
3396          * may stay enabled after this due to DMC's own request on it.
3397          */
3398         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3399         intel_power_well_disable(dev_priv, well);
3400
3401         mutex_unlock(&power_domains->lock);
3402
3403         usleep_range(10, 30);           /* 10 us delay per Bspec */
3404 }
3405
3406 void bxt_display_core_init(struct drm_i915_private *dev_priv,
3407                            bool resume)
3408 {
3409         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3410         struct i915_power_well *well;
3411
3412         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3413
3414         /*
3415          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
3416          * or else the reset will hang because there is no PCH to respond.
3417          * Move the handshake programming to initialization sequence.
3418          * Previously was left up to BIOS.
3419          */
3420         intel_pch_reset_handshake(dev_priv, false);
3421
3422         /* Enable PG1 */
3423         mutex_lock(&power_domains->lock);
3424
3425         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3426         intel_power_well_enable(dev_priv, well);
3427
3428         mutex_unlock(&power_domains->lock);
3429
3430         bxt_init_cdclk(dev_priv);
3431
3432         gen9_dbuf_enable(dev_priv);
3433
3434         if (resume && dev_priv->csr.dmc_payload)
3435                 intel_csr_load_program(dev_priv);
3436 }
3437
3438 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
3439 {
3440         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3441         struct i915_power_well *well;
3442
3443         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3444
3445         gen9_dbuf_disable(dev_priv);
3446
3447         bxt_uninit_cdclk(dev_priv);
3448
3449         /* The spec doesn't call for removing the reset handshake flag */
3450
3451         /*
3452          * Disable PW1 (PG1).
3453          * Note that even though the driver's request is removed power well 1
3454          * may stay enabled after this due to DMC's own request on it.
3455          */
3456         mutex_lock(&power_domains->lock);
3457
3458         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3459         intel_power_well_disable(dev_priv, well);
3460
3461         mutex_unlock(&power_domains->lock);
3462
3463         usleep_range(10, 30);           /* 10 us delay per Bspec */
3464 }
3465
3466 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
3467 {
3468         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3469         struct i915_power_well *well;
3470
3471         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3472
3473         /* 1. Enable PCH Reset Handshake */
3474         intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
3475
3476         /* 2-3. */
3477         cnl_combo_phys_init(dev_priv);
3478
3479         /*
3480          * 4. Enable Power Well 1 (PG1).
3481          *    The AUX IO power wells will be enabled on demand.
3482          */
3483         mutex_lock(&power_domains->lock);
3484         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3485         intel_power_well_enable(dev_priv, well);
3486         mutex_unlock(&power_domains->lock);
3487
3488         /* 5. Enable CD clock */
3489         cnl_init_cdclk(dev_priv);
3490
3491         /* 6. Enable DBUF */
3492         gen9_dbuf_enable(dev_priv);
3493
3494         if (resume && dev_priv->csr.dmc_payload)
3495                 intel_csr_load_program(dev_priv);
3496 }
3497
3498 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
3499 {
3500         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3501         struct i915_power_well *well;
3502
3503         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3504
3505         /* 1. Disable all display engine functions -> aready done */
3506
3507         /* 2. Disable DBUF */
3508         gen9_dbuf_disable(dev_priv);
3509
3510         /* 3. Disable CD clock */
3511         cnl_uninit_cdclk(dev_priv);
3512
3513         /*
3514          * 4. Disable Power Well 1 (PG1).
3515          *    The AUX IO power wells are toggled on demand, so they are already
3516          *    disabled at this point.
3517          */
3518         mutex_lock(&power_domains->lock);
3519         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3520         intel_power_well_disable(dev_priv, well);
3521         mutex_unlock(&power_domains->lock);
3522
3523         usleep_range(10, 30);           /* 10 us delay per Bspec */
3524
3525         /* 5. */
3526         cnl_combo_phys_uninit(dev_priv);
3527 }
3528
3529 void icl_display_core_init(struct drm_i915_private *dev_priv,
3530                            bool resume)
3531 {
3532         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3533         struct i915_power_well *well;
3534
3535         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3536
3537         /* 1. Enable PCH reset handshake. */
3538         intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
3539
3540         /* 2-3. */
3541         icl_combo_phys_init(dev_priv);
3542
3543         /*
3544          * 4. Enable Power Well 1 (PG1).
3545          *    The AUX IO power wells will be enabled on demand.
3546          */
3547         mutex_lock(&power_domains->lock);
3548         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3549         intel_power_well_enable(dev_priv, well);
3550         mutex_unlock(&power_domains->lock);
3551
3552         /* 5. Enable CDCLK. */
3553         icl_init_cdclk(dev_priv);
3554
3555         /* 6. Enable DBUF. */
3556         icl_dbuf_enable(dev_priv);
3557
3558         /* 7. Setup MBUS. */
3559         icl_mbus_init(dev_priv);
3560
3561         if (resume && dev_priv->csr.dmc_payload)
3562                 intel_csr_load_program(dev_priv);
3563 }
3564
3565 void icl_display_core_uninit(struct drm_i915_private *dev_priv)
3566 {
3567         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3568         struct i915_power_well *well;
3569
3570         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
3571
3572         /* 1. Disable all display engine functions -> aready done */
3573
3574         /* 2. Disable DBUF */
3575         icl_dbuf_disable(dev_priv);
3576
3577         /* 3. Disable CD clock */
3578         icl_uninit_cdclk(dev_priv);
3579
3580         /*
3581          * 4. Disable Power Well 1 (PG1).
3582          *    The AUX IO power wells are toggled on demand, so they are already
3583          *    disabled at this point.
3584          */
3585         mutex_lock(&power_domains->lock);
3586         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
3587         intel_power_well_disable(dev_priv, well);
3588         mutex_unlock(&power_domains->lock);
3589
3590         /* 5. */
3591         icl_combo_phys_uninit(dev_priv);
3592 }
3593
3594 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
3595 {
3596         struct i915_power_well *cmn_bc =
3597                 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
3598         struct i915_power_well *cmn_d =
3599                 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
3600
3601         /*
3602          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
3603          * workaround never ever read DISPLAY_PHY_CONTROL, and
3604          * instead maintain a shadow copy ourselves. Use the actual
3605          * power well state and lane status to reconstruct the
3606          * expected initial value.
3607          */
3608         dev_priv->chv_phy_control =
3609                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
3610                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
3611                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
3612                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
3613                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
3614
3615         /*
3616          * If all lanes are disabled we leave the override disabled
3617          * with all power down bits cleared to match the state we
3618          * would use after disabling the port. Otherwise enable the
3619          * override and set the lane powerdown bits accding to the
3620          * current lane status.
3621          */
3622         if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
3623                 uint32_t status = I915_READ(DPLL(PIPE_A));
3624                 unsigned int mask;
3625
3626                 mask = status & DPLL_PORTB_READY_MASK;
3627                 if (mask == 0xf)
3628                         mask = 0x0;
3629                 else
3630                         dev_priv->chv_phy_control |=
3631                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
3632
3633                 dev_priv->chv_phy_control |=
3634                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
3635
3636                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
3637                 if (mask == 0xf)
3638                         mask = 0x0;
3639                 else
3640                         dev_priv->chv_phy_control |=
3641                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
3642
3643                 dev_priv->chv_phy_control |=
3644                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
3645
3646                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
3647
3648                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
3649         } else {
3650                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
3651         }
3652
3653         if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
3654                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
3655                 unsigned int mask;
3656
3657                 mask = status & DPLL_PORTD_READY_MASK;
3658
3659                 if (mask == 0xf)
3660                         mask = 0x0;
3661                 else
3662                         dev_priv->chv_phy_control |=
3663                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
3664
3665                 dev_priv->chv_phy_control |=
3666                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
3667
3668                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
3669
3670                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
3671         } else {
3672                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
3673         }
3674
3675         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
3676
3677         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
3678                       dev_priv->chv_phy_control);
3679 }
3680
3681 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
3682 {
3683         struct i915_power_well *cmn =
3684                 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
3685         struct i915_power_well *disp2d =
3686                 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
3687
3688         /* If the display might be already active skip this */
3689         if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
3690             disp2d->desc->ops->is_enabled(dev_priv, disp2d) &&
3691             I915_READ(DPIO_CTL) & DPIO_CMNRST)
3692                 return;
3693
3694         DRM_DEBUG_KMS("toggling display PHY side reset\n");
3695
3696         /* cmnlane needs DPLL registers */
3697         disp2d->desc->ops->enable(dev_priv, disp2d);
3698
3699         /*
3700          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
3701          * Need to assert and de-assert PHY SB reset by gating the
3702          * common lane power, then un-gating it.
3703          * Simply ungating isn't enough to reset the PHY enough to get
3704          * ports and lanes running.
3705          */
3706         cmn->desc->ops->disable(dev_priv, cmn);
3707 }
3708
3709 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
3710
3711 /**
3712  * intel_power_domains_init_hw - initialize hardware power domain state
3713  * @dev_priv: i915 device instance
3714  * @resume: Called from resume code paths or not
3715  *
3716  * This function initializes the hardware power domain state and enables all
3717  * power wells belonging to the INIT power domain. Power wells in other
3718  * domains (and not in the INIT domain) are referenced or disabled by
3719  * intel_modeset_readout_hw_state(). After that the reference count of each
3720  * power well must match its HW enabled state, see
3721  * intel_power_domains_verify_state().
3722  *
3723  * It will return with power domains disabled (to be enabled later by
3724  * intel_power_domains_enable()) and must be paired with
3725  * intel_power_domains_fini_hw().
3726  */
3727 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
3728 {
3729         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3730
3731         power_domains->initializing = true;
3732
3733         if (IS_ICELAKE(dev_priv)) {
3734                 icl_display_core_init(dev_priv, resume);
3735         } else if (IS_CANNONLAKE(dev_priv)) {
3736                 cnl_display_core_init(dev_priv, resume);
3737         } else if (IS_GEN9_BC(dev_priv)) {
3738                 skl_display_core_init(dev_priv, resume);
3739         } else if (IS_GEN9_LP(dev_priv)) {
3740                 bxt_display_core_init(dev_priv, resume);
3741         } else if (IS_CHERRYVIEW(dev_priv)) {
3742                 mutex_lock(&power_domains->lock);
3743                 chv_phy_control_init(dev_priv);
3744                 mutex_unlock(&power_domains->lock);
3745         } else if (IS_VALLEYVIEW(dev_priv)) {
3746                 mutex_lock(&power_domains->lock);
3747                 vlv_cmnlane_wa(dev_priv);
3748                 mutex_unlock(&power_domains->lock);
3749         } else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
3750                 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
3751
3752         /*
3753          * Keep all power wells enabled for any dependent HW access during
3754          * initialization and to make sure we keep BIOS enabled display HW
3755          * resources powered until display HW readout is complete. We drop
3756          * this reference in intel_power_domains_enable().
3757          */
3758         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
3759         /* Disable power support if the user asked so. */
3760         if (!i915_modparams.disable_power_well)
3761                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
3762         intel_power_domains_sync_hw(dev_priv);
3763
3764         power_domains->initializing = false;
3765 }
3766
3767 /**
3768  * intel_power_domains_fini_hw - deinitialize hw power domain state
3769  * @dev_priv: i915 device instance
3770  *
3771  * De-initializes the display power domain HW state. It also ensures that the
3772  * device stays powered up so that the driver can be reloaded.
3773  *
3774  * It must be called with power domains already disabled (after a call to
3775  * intel_power_domains_disable()) and must be paired with
3776  * intel_power_domains_init_hw().
3777  */
3778 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv)
3779 {
3780         /* Keep the power well enabled, but cancel its rpm wakeref. */
3781         intel_runtime_pm_put(dev_priv);
3782
3783         /* Remove the refcount we took to keep power well support disabled. */
3784         if (!i915_modparams.disable_power_well)
3785                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3786
3787         intel_power_domains_verify_state(dev_priv);
3788 }
3789
3790 /**
3791  * intel_power_domains_enable - enable toggling of display power wells
3792  * @dev_priv: i915 device instance
3793  *
3794  * Enable the ondemand enabling/disabling of the display power wells. Note that
3795  * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
3796  * only at specific points of the display modeset sequence, thus they are not
3797  * affected by the intel_power_domains_enable()/disable() calls. The purpose
3798  * of these function is to keep the rest of power wells enabled until the end
3799  * of display HW readout (which will acquire the power references reflecting
3800  * the current HW state).
3801  */
3802 void intel_power_domains_enable(struct drm_i915_private *dev_priv)
3803 {
3804         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3805
3806         intel_power_domains_verify_state(dev_priv);
3807 }
3808
3809 /**
3810  * intel_power_domains_disable - disable toggling of display power wells
3811  * @dev_priv: i915 device instance
3812  *
3813  * Disable the ondemand enabling/disabling of the display power wells. See
3814  * intel_power_domains_enable() for which power wells this call controls.
3815  */
3816 void intel_power_domains_disable(struct drm_i915_private *dev_priv)
3817 {
3818         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
3819
3820         intel_power_domains_verify_state(dev_priv);
3821 }
3822
3823 /**
3824  * intel_power_domains_suspend - suspend power domain state
3825  * @dev_priv: i915 device instance
3826  * @suspend_mode: specifies the target suspend state (idle, mem, hibernation)
3827  *
3828  * This function prepares the hardware power domain state before entering
3829  * system suspend.
3830  *
3831  * It must be called with power domains already disabled (after a call to
3832  * intel_power_domains_disable()) and paired with intel_power_domains_resume().
3833  */
3834 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
3835                                  enum i915_drm_suspend_mode suspend_mode)
3836 {
3837         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3838
3839         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3840
3841         /*
3842          * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
3843          * support don't manually deinit the power domains. This also means the
3844          * CSR/DMC firmware will stay active, it will power down any HW
3845          * resources as required and also enable deeper system power states
3846          * that would be blocked if the firmware was inactive.
3847          */
3848         if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
3849             suspend_mode == I915_DRM_SUSPEND_IDLE &&
3850             dev_priv->csr.dmc_payload != NULL) {
3851                 intel_power_domains_verify_state(dev_priv);
3852                 return;
3853         }
3854
3855         /*
3856          * Even if power well support was disabled we still want to disable
3857          * power wells if power domains must be deinitialized for suspend.
3858          */
3859         if (!i915_modparams.disable_power_well) {
3860                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3861                 intel_power_domains_verify_state(dev_priv);
3862         }
3863
3864         if (IS_ICELAKE(dev_priv))
3865                 icl_display_core_uninit(dev_priv);
3866         else if (IS_CANNONLAKE(dev_priv))
3867                 cnl_display_core_uninit(dev_priv);
3868         else if (IS_GEN9_BC(dev_priv))
3869                 skl_display_core_uninit(dev_priv);
3870         else if (IS_GEN9_LP(dev_priv))
3871                 bxt_display_core_uninit(dev_priv);
3872
3873         power_domains->display_core_suspended = true;
3874 }
3875
3876 /**
3877  * intel_power_domains_resume - resume power domain state
3878  * @dev_priv: i915 device instance
3879  *
3880  * This function resume the hardware power domain state during system resume.
3881  *
3882  * It will return with power domain support disabled (to be enabled later by
3883  * intel_power_domains_enable()) and must be paired with
3884  * intel_power_domains_suspend().
3885  */
3886 void intel_power_domains_resume(struct drm_i915_private *dev_priv)
3887 {
3888         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3889
3890         if (power_domains->display_core_suspended) {
3891                 intel_power_domains_init_hw(dev_priv, true);
3892                 power_domains->display_core_suspended = false;
3893         } else {
3894                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
3895         }
3896
3897         intel_power_domains_verify_state(dev_priv);
3898 }
3899
3900 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
3901
3902 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
3903 {
3904         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3905         struct i915_power_well *power_well;
3906
3907         for_each_power_well(dev_priv, power_well) {
3908                 enum intel_display_power_domain domain;
3909
3910                 DRM_DEBUG_DRIVER("%-25s %d\n",
3911                                  power_well->desc->name, power_well->count);
3912
3913                 for_each_power_domain(domain, power_well->desc->domains)
3914                         DRM_DEBUG_DRIVER("  %-23s %d\n",
3915                                          intel_display_power_domain_str(domain),
3916                                          power_domains->domain_use_count[domain]);
3917         }
3918 }
3919
3920 /**
3921  * intel_power_domains_verify_state - verify the HW/SW state for all power wells
3922  * @dev_priv: i915 device instance
3923  *
3924  * Verify if the reference count of each power well matches its HW enabled
3925  * state and the total refcount of the domains it belongs to. This must be
3926  * called after modeset HW state sanitization, which is responsible for
3927  * acquiring reference counts for any power wells in use and disabling the
3928  * ones left on by BIOS but not required by any active output.
3929  */
3930 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
3931 {
3932         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3933         struct i915_power_well *power_well;
3934         bool dump_domain_info;
3935
3936         mutex_lock(&power_domains->lock);
3937
3938         dump_domain_info = false;
3939         for_each_power_well(dev_priv, power_well) {
3940                 enum intel_display_power_domain domain;
3941                 int domains_count;
3942                 bool enabled;
3943
3944                 enabled = power_well->desc->ops->is_enabled(dev_priv,
3945                                                             power_well);
3946                 if ((power_well->count || power_well->desc->always_on) !=
3947                     enabled)
3948                         DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)",
3949                                   power_well->desc->name,
3950                                   power_well->count, enabled);
3951
3952                 domains_count = 0;
3953                 for_each_power_domain(domain, power_well->desc->domains)
3954                         domains_count += power_domains->domain_use_count[domain];
3955
3956                 if (power_well->count != domains_count) {
3957                         DRM_ERROR("power well %s refcount/domain refcount mismatch "
3958                                   "(refcount %d/domains refcount %d)\n",
3959                                   power_well->desc->name, power_well->count,
3960                                   domains_count);
3961                         dump_domain_info = true;
3962                 }
3963         }
3964
3965         if (dump_domain_info) {
3966                 static bool dumped;
3967
3968                 if (!dumped) {
3969                         intel_power_domains_dump_info(dev_priv);
3970                         dumped = true;
3971                 }
3972         }
3973
3974         mutex_unlock(&power_domains->lock);
3975 }
3976
3977 #else
3978
3979 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
3980 {
3981 }
3982
3983 #endif
3984
3985 /**
3986  * intel_runtime_pm_get - grab a runtime pm reference
3987  * @dev_priv: i915 device instance
3988  *
3989  * This function grabs a device-level runtime pm reference (mostly used for GEM
3990  * code to ensure the GTT or GT is on) and ensures that it is powered up.
3991  *
3992  * Any runtime pm reference obtained by this function must have a symmetric
3993  * call to intel_runtime_pm_put() to release the reference again.
3994  */
3995 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
3996 {
3997         struct pci_dev *pdev = dev_priv->drm.pdev;
3998         struct device *kdev = &pdev->dev;
3999         int ret;
4000
4001         ret = pm_runtime_get_sync(kdev);
4002         WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
4003
4004         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
4005         assert_rpm_wakelock_held(dev_priv);
4006 }
4007
4008 /**
4009  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
4010  * @dev_priv: i915 device instance
4011  *
4012  * This function grabs a device-level runtime pm reference if the device is
4013  * already in use and ensures that it is powered up. It is illegal to try
4014  * and access the HW should intel_runtime_pm_get_if_in_use() report failure.
4015  *
4016  * Any runtime pm reference obtained by this function must have a symmetric
4017  * call to intel_runtime_pm_put() to release the reference again.
4018  *
4019  * Returns: True if the wakeref was acquired, or False otherwise.
4020  */
4021 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
4022 {
4023         if (IS_ENABLED(CONFIG_PM)) {
4024                 struct pci_dev *pdev = dev_priv->drm.pdev;
4025                 struct device *kdev = &pdev->dev;
4026
4027                 /*
4028                  * In cases runtime PM is disabled by the RPM core and we get
4029                  * an -EINVAL return value we are not supposed to call this
4030                  * function, since the power state is undefined. This applies
4031                  * atm to the late/early system suspend/resume handlers.
4032                  */
4033                 if (pm_runtime_get_if_in_use(kdev) <= 0)
4034                         return false;
4035         }
4036
4037         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
4038         assert_rpm_wakelock_held(dev_priv);
4039
4040         return true;
4041 }
4042
4043 /**
4044  * intel_runtime_pm_get_noresume - grab a runtime pm reference
4045  * @dev_priv: i915 device instance
4046  *
4047  * This function grabs a device-level runtime pm reference (mostly used for GEM
4048  * code to ensure the GTT or GT is on).
4049  *
4050  * It will _not_ power up the device but instead only check that it's powered
4051  * on.  Therefore it is only valid to call this functions from contexts where
4052  * the device is known to be powered up and where trying to power it up would
4053  * result in hilarity and deadlocks. That pretty much means only the system
4054  * suspend/resume code where this is used to grab runtime pm references for
4055  * delayed setup down in work items.
4056  *
4057  * Any runtime pm reference obtained by this function must have a symmetric
4058  * call to intel_runtime_pm_put() to release the reference again.
4059  */
4060 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
4061 {
4062         struct pci_dev *pdev = dev_priv->drm.pdev;
4063         struct device *kdev = &pdev->dev;
4064
4065         assert_rpm_wakelock_held(dev_priv);
4066         pm_runtime_get_noresume(kdev);
4067
4068         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
4069 }
4070
4071 /**
4072  * intel_runtime_pm_put - release a runtime pm reference
4073  * @dev_priv: i915 device instance
4074  *
4075  * This function drops the device-level runtime pm reference obtained by
4076  * intel_runtime_pm_get() and might power down the corresponding
4077  * hardware block right away if this is the last reference.
4078  */
4079 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
4080 {
4081         struct pci_dev *pdev = dev_priv->drm.pdev;
4082         struct device *kdev = &pdev->dev;
4083
4084         assert_rpm_wakelock_held(dev_priv);
4085         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
4086
4087         pm_runtime_mark_last_busy(kdev);
4088         pm_runtime_put_autosuspend(kdev);
4089 }
4090
4091 /**
4092  * intel_runtime_pm_enable - enable runtime pm
4093  * @dev_priv: i915 device instance
4094  *
4095  * This function enables runtime pm at the end of the driver load sequence.
4096  *
4097  * Note that this function does currently not enable runtime pm for the
4098  * subordinate display power domains. That is done by
4099  * intel_power_domains_enable().
4100  */
4101 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
4102 {
4103         struct pci_dev *pdev = dev_priv->drm.pdev;
4104         struct device *kdev = &pdev->dev;
4105
4106         /*
4107          * Disable the system suspend direct complete optimization, which can
4108          * leave the device suspended skipping the driver's suspend handlers
4109          * if the device was already runtime suspended. This is needed due to
4110          * the difference in our runtime and system suspend sequence and
4111          * becaue the HDA driver may require us to enable the audio power
4112          * domain during system suspend.
4113          */
4114         dev_pm_set_driver_flags(kdev, DPM_FLAG_NEVER_SKIP);
4115
4116         pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
4117         pm_runtime_mark_last_busy(kdev);
4118
4119         /*
4120          * Take a permanent reference to disable the RPM functionality and drop
4121          * it only when unloading the driver. Use the low level get/put helpers,
4122          * so the driver's own RPM reference tracking asserts also work on
4123          * platforms without RPM support.
4124          */
4125         if (!HAS_RUNTIME_PM(dev_priv)) {
4126                 int ret;
4127
4128                 pm_runtime_dont_use_autosuspend(kdev);
4129                 ret = pm_runtime_get_sync(kdev);
4130                 WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
4131         } else {
4132                 pm_runtime_use_autosuspend(kdev);
4133         }
4134
4135         /*
4136          * The core calls the driver load handler with an RPM reference held.
4137          * We drop that here and will reacquire it during unloading in
4138          * intel_power_domains_fini().
4139          */
4140         pm_runtime_put_autosuspend(kdev);
4141 }
4142
4143 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
4144 {
4145         struct pci_dev *pdev = dev_priv->drm.pdev;
4146         struct device *kdev = &pdev->dev;
4147
4148         /* Transfer rpm ownership back to core */
4149         WARN(pm_runtime_get_sync(&dev_priv->drm.pdev->dev) < 0,
4150              "Failed to pass rpm ownership back to core\n");
4151
4152         pm_runtime_dont_use_autosuspend(kdev);
4153
4154         if (!HAS_RUNTIME_PM(dev_priv))
4155                 pm_runtime_put(kdev);
4156 }